diff --git a/arch/arm/src/stm32/Kconfig b/arch/arm/src/stm32/Kconfig
index 4dcdc0a5a0e..c706cfed7bf 100644
--- a/arch/arm/src/stm32/Kconfig
+++ b/arch/arm/src/stm32/Kconfig
@@ -1403,9 +1403,6 @@ config STM32_I2C
 config STM32_CAN
 	bool
 
-config STM32_OTGFS2
-	bool
-
 menu "Alternate Pin Mapping"
 
 choice
diff --git a/arch/arm/src/stm32/chip/stm32f40xxx_pinmap.h b/arch/arm/src/stm32/chip/stm32f40xxx_pinmap.h
index 79c9789a219..7ded147fc2b 100644
--- a/arch/arm/src/stm32/chip/stm32f40xxx_pinmap.h
+++ b/arch/arm/src/stm32/chip/stm32f40xxx_pinmap.h
@@ -400,12 +400,6 @@
 #define GPIO_OTGHSFS_DP       (GPIO_ALT|GPIO_FLOAT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN15)
 #define GPIO_OTGHSFS_ID       (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN12)
 
-#ifdef CONFIG_STM32_OTGFS2
-#  define GPIO_OTGFS2_DM      (GPIO_ALT|GPIO_FLOAT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN14)
-#  define GPIO_OTGFS2_DP      (GPIO_ALT|GPIO_FLOAT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN15)
-#  define GPIO_OTGFS2_ID      (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN12)
-#endif
-
 #define GPIO_OTGHS_DM         (GPIO_ALT|GPIO_FLOAT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN14)
 #define GPIO_OTGHS_DP         (GPIO_ALT|GPIO_FLOAT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN15)
 #define GPIO_OTGHS_ID         (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN12)
diff --git a/arch/arm/src/stm32/stm32_otgfsdev.c b/arch/arm/src/stm32/stm32_otgfsdev.c
index 051cf5510f4..861a10c0393 100644
--- a/arch/arm/src/stm32/stm32_otgfsdev.c
+++ b/arch/arm/src/stm32/stm32_otgfsdev.c
@@ -5132,10 +5132,6 @@ static void stm32_hwinitialize(FAR struct stm32_usbdev_s *priv)
 
   stm32_putreg(OTGFS_GAHBCFG_TXFELVL, STM32_OTGFS_GAHBCFG);
 
-  /* For OTGFS2 mode (FS mode of the HS module), we must select the FS PHY
-   * mode prior to issuing a soft reset.
-   */
-
   /* Common USB OTG core initialization */
   /* Reset after a PHY select and set Host mode.  First, wait for AHB master
    * IDLE state.