Merge remote-tracking branch 'origin/master' into ieee802154

2026-05-31 23:40:19 +08:00 · 2017-05-04 07:11:19 -06:00
parent 2b8d60970b 7035723aeb
commit 6a45afdd75
121 changed files with 39623 additions and 212 deletions
@@ -313,6 +313,25 @@ config UIMAGE_ENTRY_POINT
 	hex "uImage entry point"
 	default 0x0
 endif
 menuconfig DFU_BINARY
 	bool "DFU binary format"
 	select RAW_BINARY
 	---help---
 	Create the dfu binary used with dfu-utils.
 if DFU_BINARY
 config DFU_BASE
 	hex "Address DFU image is loaded to"
 config DFU_VID
 	hex "VID to use for DFU image"
 config DFU_PID
 	hex "PID to use for DFU image"
 endif
 endmenu # Binary Output Formats
@@ -108,8 +108,12 @@
 #  define STM32L4_NSAI                     2   /* SAI1-2 */
 #  define STM32L4_NSDMMC                   1   /* SDMMC interface */
 #  define STM32L4_NDMA                     2   /* DMA1-2 */
 #if defined(CONFIG_STM32L4_STM32L496XX)
 #  define STM32L4_NPORTS                   9   /* 9 GPIO ports, GPIOA-I */
 #else
 #  define STM32L4_NPORTS                   8   /* 8 GPIO ports, GPIOA-H */
-#  define STM32L4_NADC                     3   /* 12-bit ADC1-3, 24 channels (except V series) */
+#endif
 #  define STM32L4_NADC                     3   /* 12-bit ADC1-3, upto 24 channels */
 #  define STM32L4_NDAC                     2   /* 12-bit DAC1-2 */
 #  define STM32L4_NCRC                     1   /* CRC */
 #  define STM32L4_NCOMP                    2   /* Comparators */
@@ -221,6 +221,10 @@ ifeq ($(CONFIG_COMP),y)
 CHIP_CSRCS += stm32_comp.c
 endif
 ifeq ($(CONFIG_OPAMP),y)
 CHIP_CSRCS += stm32_opamp.c
 endif
 ifeq ($(CONFIG_STM32_1WIREDRIVER),y)
 CHIP_CSRCS += stm32_1wire.c
 endif
@@ -54,7 +54,7 @@
 /* Register Addresses *******************************************************************************/
-#define STM32_OPAMP2_CSR            (STM32_OPAMP2_BASE+STM32_OPAMP2_CSR_OFFSET)
+#define STM32_OPAMP2_CSR            (STM32_OPAMP_BASE+STM32_OPAMP2_CSR_OFFSET)
 /* Register Bitfield Definitions ****************************************************/
@@ -66,7 +66,7 @@
 #define OPAMP_CSR_VPSEL_SHIFT       (3)         /* Bits 2-3: OPAMP non inverting input selection */
 #define OPAMP_CSR_VPSEL_MASK        (3 << OPAMP_CSR_VPSEL_SHIFT)
                                                                    /* 00: Reserved  */
-#  define OPAMP_CSR_VPSEL_PB13      (1 << OPAMP_CSR_VPSEL_SHIFT)    /* 01: PB14 */
+#  define OPAMP_CSR_VPSEL_PB14      (1 << OPAMP_CSR_VPSEL_SHIFT)    /* 01: PB14 */
 #  define OPAMP_CSR_VPSEL_PB0       (2 << OPAMP_CSR_VPSEL_SHIFT)    /* 10: PB0 */
 #  define OPAMP_CSR_VPSEL_PA7       (3 << OPAMP_CSR_VPSEL_SHIFT)    /* 11: PA7 */
                                                /* Bit 4: Reserved  */
@@ -74,7 +74,7 @@
 #define OPAMP_CSR_VMSEL_MASK        (3 << OPAMP_CSR_VMSEL_SHIFT)
 #  define OPAMP_CSR_VMSEL_PC5       (0 << OPAMP_CSR_VMSEL_SHIFT)    /* 00: PC5 */
 #  define OPAMP_CSR_VMSEL_PA5       (1 << OPAMP_CSR_VMSEL_SHIFT)    /* 01: PA5 */
-#  define OPAMP_CSR_VMSEL_RESISTOR  (2 << OPAMP_CSR_VMSEL_SHIFT)    /* 10: Resistor feedback output */
+#  define OPAMP_CSR_VMSEL_PGA       (2 << OPAMP_CSR_VMSEL_SHIFT)    /* 10: Resistor feedback output (PGA mode)*/
 #  define OPAMP_CSR_VMSEL_FOLLOWER  (3 << OPAMP_CSR_VMSEL_SHIFT)    /* 11: Follower mode */
 #define OPAMP_CSR_TCMEN             (1 << 7)    /* Bit 7: Timer controlled Mux mode enable */
 #define OPAMP_CSR_VMSSEL            (1 << 8)    /* Bit 8: OPAMP inverting input secondary selection */
@@ -337,9 +337,10 @@
 #define GPIO_OPAMP2_VINM_1   (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN5)
 #define GPIO_OPAMP2_VINM_2   (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN5)
 #define GPIO_OPAMP2_VOUT     (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN6)
-#define GPIO_OPAMP2_VINP_1   (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN7)
+#undef  GPIO_OPAMP2_VINP_1      /* not supported in F33XX */
-#define GPIO_OPAMP2_VINP_2   (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN0)
+#define GPIO_OPAMP2_VINP_2   (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN7)
-#define GPIO_OPAMP2_VINP_3   (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN14)
+#define GPIO_OPAMP2_VINP_3   (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN0)
 #define GPIO_OPAMP2_VINP_4   (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN14)
 /* TSC */
@@ -69,6 +69,7 @@
 #include "stm32_gpio.h"
 #include "stm32_i2c.h"
 #include "stm32_ltdc.h"
 #include "stm32_opamp.h"
 #include "stm32_pwr.h"
 #include "stm32_rcc.h"
 #include "stm32_rtc.h"
@@ -1454,8 +1454,8 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv)
 *
 ************************************************************************************/
-#ifdef CONFIG_I2C_POLLED
+#ifndef CONFIG_I2C_POLLED
-static int stm32_i2c2_isr(int irq, void *context, FAR void *arg)
+static int stm32_i2c_isr(int irq, void *context, FAR void *arg)
 {
  struct stm32_i2c_priv_s *priv = (struct stm32_i2c_priv_s *)arg;
@@ -0,0 +1,231 @@
 /************************************************************************************
 * arch/arm/src/stm32/stm32_opamp.h
 *
 *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
 *   Author: Mateusz Szafoni <raiden00@railab.me>
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 * 3. Neither the name NuttX nor the names of its contributors may be
 *    used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 *
 ************************************************************************************/
 #ifndef __ARCH_ARM_SRC_STM32_STM32_OPAMP_H
 #define __ARCH_ARM_SRC_STM32_STM32_OPAMP_H
 /************************************************************************************
 * Included Files
 ************************************************************************************/
 #include <nuttx/config.h>
 #include "chip.h"
 #ifdef CONFIG_STM32_OPAMP
 #if defined(CONFIG_STM32_STM32F30XX)
 #  error "OPAMP support for STM32F30XX not implemented yet"
 #elif defined(CONFIG_STM32_STM32F33XX)
 #  include "chip/stm32f33xxx_opamp.h"
 #endif
 #include <nuttx/analog/opamp.h>
 /************************************************************************************
 * Pre-processor definitions
 ************************************************************************************/
 /* OPAMP operation mode */
 #define OPAMP_MODE_STANDALONE 0
 #define OPAMP_MODE_FOLLOWER 1
 #define OPAMP_MODE_PGA 2
 /* Timer controlled Mux mode */
 #define OPAMP_MUX_DISABLE 0
 #define OPAMP_MUX_ENABLE 1
 /* User callibration  */
 #define OPAMP_USERCAL_DISABLE 0
 #define OPAMP_USERCAL_ENABLE  1
 /* Default configuration */
 #define OPAMP_MODE_DEFAULT    OPAMP_MODE_STANDALONE /* Standalone mode */
 #define OPAMP_MUX_DEFAULT     OPAMP_MUX_DISABLE     /* MUX disabled */
 #define OPAMP_USERCAL_DEFAULT OPAMP_USERCAL_DISABLE /* User calibration disabled */
 #define OPAMP_GAIN_DEFAULT    OPAMP_GAIN_2          /* Gain in PGA mode = 2 */
 #define OPAMP_LOCK_DEFAULT    OPAMP_LOCK_RW         /* Do not lock CSR register */
 /************************************************************************************
 * Public Types
 ************************************************************************************/
 /* CSR register lock state */
 enum stm32_opamp_lock_e
 {
  OPAMP_LOCK_RW,
  OPAMP_LOCK_RO
 };
 /* Gain in PGA mode */
 enum stm32_opamp_gain_e
 {
  OPAMP_GAIN_2,
  OPAMP_GAIN_4,
  OPAMP_GAIN_8,
  OPAMP_GAIN_2_VM0,
  OPAMP_GAIN_4_VM0,
  OPAMP_GAIN_8_VM0,
  OPAMP_GAIN_16_VM0,
  OPAMP_GAIN_2_VM1,
  OPAMP_GAIN_4_VM1,
  OPAMP_GAIN_8_VM1,
  OPAMP_GAIN_16_VM1
 };
 /* Input selection and secondary input selection use the same GPIOs */
 #ifdef CONFIG_STM32_OPAMP1
 enum stm32_opamp1_vpsel_e
 {
  OPAMP1_VPSEL_PA7,
  OPAMP1_VPSEL_PA5,
  OPAMP1_VPSEL_PA3,
  OPAMP1_VPSEL_PA1
 };
 enum stm32_opamp1_vmsel_e
 {
  OPAMP1_VMSEL_PC5,
  OPAMP1_VMSEL_PA3,
  OPAMP1_VMSEL_PGAMODE,
  OPAMP1_VMSEL_FOLLOWER,
 };
 #endif
 #ifdef CONFIG_STM32_OPAMP2
 enum stm32_opamp2_vpsel_e
 {
 #ifndef CONFIG_STM32_STM32F33XX
  /* TODO: STM32F303xB/C and STM32F358C devices only */
  OPAMP2_VPSEL_PD14,
 #endif
  OPAMP2_VPSEL_PB14,
  OPAMP2_VPSEL_PB0,
  OPAMP2_VPSEL_PA7
 };
 enum stm32_opamp2_vmsel_e
 {
  OPAMP2_VMSEL_PC5,
  OPAMP2_VMSEL_PA5,
  OPAMP2_VMSEL_PGAMODE,
  OPAMP2_VMSEL_FOLLOWER
 };
 #endif
 #ifdef CONFIG_STM32_OPAMP3
 enum stm32_opamp3_vpsel_e
 {
  OPAMP3_VPSEL_PB13,
  OPAMP3_VPSEL_PA5,
  OPAMP3_VPSEL_PA1,
  OPAMP3_VPSEL_PB0
 };
 enum stm32_opamp3_vmsel_e
 {
  OPAMP3_VMSEL_PB10,
  OPAMP3_VMSEL_PB2,
  OPAMP3_VMSEL_PGAMODE,
  OPAMP3_VMSEL_FOLLOWER
 };
 #endif
 #ifdef CONFIG_STM32_OPAMP4
 enum stm32_opamp4_vpsel_e
 {
  OPAMP4_VPSEL_PD11,
  OPAMP4_VPSEL_PB11,
  OPAMP4_VPSEL_PA4,
  OPAMP4_VPSEL_PB13
 };
 enum stm32_opamp4_vmsel_e
 {
  OPAMP4_VMSEL_PB10,
  OPAMP4_VMSEL_PD8,
  OPAMP4_VMSEL_PGAMODE,
  OPAMP4_VMSEL_FOLLOWER
 };
 #endif
 /************************************************************************************
 * Public Function Prototypes
 ************************************************************************************/
 #ifndef __ASSEMBLY__
 #ifdef __cplusplus
 #define EXTERN extern "C"
 extern "C"
 {
 #else
 #define EXTERN extern
 #endif
 /****************************************************************************
 * Name: stm32_opampinitialize
 *
 * Description:
 *   Initialize the OPAMP.
 *
 * Input Parameters:
 *   intf - The OPAMP interface number.
 *
 * Returned Value:
 *   Valid OPAMP device structure reference on succcess; a NULL on failure.
 *
 * Assumptions:
 *   1. Clock to the OPAMP block has enabled,
 *   2. Board-specific logic has already configured
 *
 ****************************************************************************/
 FAR struct opamp_dev_s* stm32_opampinitialize(int intf);
 #undef EXTERN
 #ifdef __cplusplus
 }
 #endif
 #endif /* __ASSEMBLY__ */
 #endif  /* CONFIG_STM32_OPAMP */
 #endif /* __ARCH_ARM_SRC_STM32_STM32_OPAMP_H */
@@ -300,6 +300,8 @@
 #  endif
 #endif
 #define STM32_SDIO_USE_DEFAULT_BLOCKSIZE ((uint8_t)-1)
 /****************************************************************************
 * Private Types
 ****************************************************************************/
@@ -333,6 +335,12 @@ struct stm32_dev_s
  size_t             remaining;  /* Number of bytes remaining in the transfer */
  uint32_t           xfrmask;    /* Interrupt enables for data transfer */
  /* Fixed transfer block size support */
 #ifdef CONFIG_SDIO_BLOCKSETUP
  uint8_t            block_size;
 #endif
  /* DMA data transfer support */
  bool               widebus;    /* Required for DMA support */
@@ -443,6 +451,10 @@ static int  stm32_attach(FAR struct sdio_dev_s *dev);
 static int  stm32_sendcmd(FAR struct sdio_dev_s *dev, uint32_t cmd,
              uint32_t arg);
 #ifdef CONFIG_SDIO_BLOCKSETUP
 static void stm32_blocksetup(FAR struct sdio_dev_s *dev,
              unsigned int blocklen, unsigned int nblocks);
 #endif
 static int  stm32_recvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer,
              size_t nbytes);
 static int  stm32_sendsetup(FAR struct sdio_dev_s *dev,
@@ -456,8 +468,6 @@ static int  stm32_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd,
              uint32_t rlong[4]);
 static int  stm32_recvshort(FAR struct sdio_dev_s *dev, uint32_t cmd,
              uint32_t *rshort);
 static int  stm32_recvnotimpl(FAR struct sdio_dev_s *dev, uint32_t cmd,
              uint32_t *rnotimpl);
 /* EVENT handler */
@@ -507,7 +517,7 @@ struct stm32_dev_s g_sdiodev =
    .attach           = stm32_attach,
    .sendcmd          = stm32_sendcmd,
 #ifdef CONFIG_SDIO_BLOCKSETUP
-    .blocksetup       = stm32_blocksetup, /* Not implemented yet */
+    .blocksetup       = stm32_blocksetup,
 #endif
    .recvsetup        = stm32_recvsetup,
    .sendsetup        = stm32_sendsetup,
@@ -516,8 +526,8 @@ struct stm32_dev_s g_sdiodev =
    .recvR1           = stm32_recvshortcrc,
    .recvR2           = stm32_recvlong,
    .recvR3           = stm32_recvshort,
-    .recvR4           = stm32_recvnotimpl,
+    .recvR4           = stm32_recvshort,
-    .recvR5           = stm32_recvnotimpl,
+    .recvR5           = stm32_recvshortcrc,
    .recvR6           = stm32_recvshortcrc,
    .recvR7           = stm32_recvshort,
    .waitenable       = stm32_waitenable,
@@ -1015,7 +1025,7 @@ static void stm32_dataconfig(uint32_t timeout, uint32_t dlen, uint32_t dctrl)
  regval  =  getreg32(STM32_SDIO_DCTRL);
  regval &= ~(SDIO_DCTRL_DTDIR | SDIO_DCTRL_DTMODE | SDIO_DCTRL_DBLOCKSIZE_MASK);
  dctrl  &=  (SDIO_DCTRL_DTDIR | SDIO_DCTRL_DTMODE | SDIO_DCTRL_DBLOCKSIZE_MASK);
-  regval |=  (dctrl | SDIO_DCTRL_DTEN);
+  regval |=  (dctrl | SDIO_DCTRL_DTEN | SDIO_DCTRL_SDIOEN);
  putreg32(regval, STM32_SDIO_DCTRL);
 }
@@ -1865,6 +1875,34 @@ static int stm32_sendcmd(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t arg)
  return OK;
 }
 /****************************************************************************
 * Name: stm32_blocksetup
 *
 * Description:
 *   Configure block size and the number of blocks for next transfer
 *
 * Input Parameters:
 *   dev       - An instance of the SDIO device interface
 *   blocklen  - The selected block size.
 *   nblocklen - The number of blocks to transfer
 *
 * Returned Value:
 *   None
 *
 ****************************************************************************/
 #ifdef CONFIG_SDIO_BLOCKSETUP
 static void stm32_blocksetup(FAR struct sdio_dev_s *dev,
                             unsigned int blocklen, unsigned int nblocks)
 {
  struct stm32_dev_s *priv = (struct stm32_dev_s *)dev;
  /* Configure block size for next transfer */
  priv->block_size = stm32_log2(blocklen);
 }
 #endif
 /****************************************************************************
 * Name: stm32_recvsetup
 *
@@ -1911,7 +1949,17 @@ static int stm32_recvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer,
  /* Then set up the SDIO data path */
-  dblocksize = stm32_log2(nbytes) << SDIO_DCTRL_DBLOCKSIZE_SHIFT;
+#ifdef CONFIG_SDIO_BLOCKSETUP
  if (priv->block_size != STM32_SDIO_USE_DEFAULT_BLOCKSIZE)
    {
      dblocksize = priv->block_size << SDIO_DCTRL_DBLOCKSIZE_SHIFT;
    }
  else
 #endif
    {
      dblocksize = stm32_log2(nbytes) << SDIO_DCTRL_DBLOCKSIZE_SHIFT;
    }
  stm32_dataconfig(SDIO_DTIMER_DATATIMEOUT, nbytes, dblocksize | SDIO_DCTRL_DTDIR);
  /* And enable interrupts */
@@ -1965,7 +2013,17 @@ static int stm32_sendsetup(FAR struct sdio_dev_s *dev, FAR const uint8_t *buffer
  /* Then set up the SDIO data path */
-  dblocksize = stm32_log2(nbytes) << SDIO_DCTRL_DBLOCKSIZE_SHIFT;
+#ifdef CONFIG_SDIO_BLOCKSETUP
  if (priv->block_size != STM32_SDIO_USE_DEFAULT_BLOCKSIZE)
    {
      dblocksize = priv->block_size << SDIO_DCTRL_DBLOCKSIZE_SHIFT;
    }
  else
 #endif
    {
      dblocksize = stm32_log2(nbytes) << SDIO_DCTRL_DBLOCKSIZE_SHIFT;
    }
  stm32_dataconfig(SDIO_DTIMER_DATATIMEOUT, nbytes, dblocksize);
  /* Enable TX interrupts */
@@ -2061,15 +2119,13 @@ static int stm32_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd)
    case MMCSD_R1_RESPONSE:
    case MMCSD_R1B_RESPONSE:
    case MMCSD_R2_RESPONSE:
    case MMCSD_R4_RESPONSE:
    case MMCSD_R5_RESPONSE:
    case MMCSD_R6_RESPONSE:
      events  = SDIO_RESPDONE_STA;
      timeout = SDIO_LONGTIMEOUT;
      break;
    case MMCSD_R4_RESPONSE:
    case MMCSD_R5_RESPONSE:
      return -ENOSYS;
    case MMCSD_R3_RESPONSE:
    case MMCSD_R7_RESPONSE:
      events  = SDIO_RESPDONE_STA;
@@ -2161,6 +2217,7 @@ static int stm32_recvshortcrc(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t
  else if ((cmd & MMCSD_RESPONSE_MASK) != MMCSD_R1_RESPONSE &&
           (cmd & MMCSD_RESPONSE_MASK) != MMCSD_R1B_RESPONSE &&
           (cmd & MMCSD_RESPONSE_MASK) != MMCSD_R5_RESPONSE &&
           (cmd & MMCSD_RESPONSE_MASK) != MMCSD_R6_RESPONSE)
    {
      mcerr("ERROR: Wrong response CMD=%08x\n", cmd);
@@ -2276,6 +2333,7 @@ static int stm32_recvshort(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t *r
 #ifdef CONFIG_DEBUG_MEMCARD_INFO
  if ((cmd & MMCSD_RESPONSE_MASK) != MMCSD_R3_RESPONSE &&
      (cmd & MMCSD_RESPONSE_MASK) != MMCSD_R4_RESPONSE &&
      (cmd & MMCSD_RESPONSE_MASK) != MMCSD_R7_RESPONSE)
    {
      mcerr("ERROR: Wrong response CMD=%08x\n", cmd);
@@ -2301,17 +2359,10 @@ static int stm32_recvshort(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t *r
    {
      *rshort = getreg32(STM32_SDIO_RESP1);
    }
  return ret;
 }
 /* MMC responses not supported */
 static int stm32_recvnotimpl(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t *rnotimpl)
 {
  putreg32(SDIO_RESPDONE_ICR | SDIO_CMDDONE_ICR, STM32_SDIO_ICR);
  return -ENOSYS;
 }
 /****************************************************************************
 * Name: stm32_waitenable
 *
@@ -2670,7 +2721,17 @@ static int stm32_dmarecvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer,
  /* Then set up the SDIO data path */
-  dblocksize = stm32_log2(buflen) << SDIO_DCTRL_DBLOCKSIZE_SHIFT;
+#ifdef CONFIG_SDIO_BLOCKSETUP
  if (priv->block_size != STM32_SDIO_USE_DEFAULT_BLOCKSIZE)
    {
      dblocksize = priv->block_size << SDIO_DCTRL_DBLOCKSIZE_SHIFT;
    }
  else
 #endif
    {
      dblocksize = stm32_log2(buflen) << SDIO_DCTRL_DBLOCKSIZE_SHIFT;
    }
  stm32_dataconfig(SDIO_DTIMER_DATATIMEOUT, buflen, dblocksize | SDIO_DCTRL_DTDIR);
  /* Configure the RX DMA */
@@ -2739,7 +2800,17 @@ static int stm32_dmasendsetup(FAR struct sdio_dev_s *dev,
  /* Then set up the SDIO data path */
-  dblocksize = stm32_log2(buflen) << SDIO_DCTRL_DBLOCKSIZE_SHIFT;
+#ifdef CONFIG_SDIO_BLOCKSETUP
  if (priv->block_size != STM32_SDIO_USE_DEFAULT_BLOCKSIZE)
    {
      dblocksize = priv->block_size << SDIO_DCTRL_DBLOCKSIZE_SHIFT;
    }
  else
 #endif
    {
      dblocksize = stm32_log2(buflen) << SDIO_DCTRL_DBLOCKSIZE_SHIFT;
    }
  stm32_dataconfig(SDIO_DTIMER_DATATIMEOUT, buflen, dblocksize);
  /* Configure the TX DMA */
@@ -26,7 +26,7 @@ config ARCH_CHIP_STM32F745VE
 	select STM32F7_FLASH_CONFIG_E
 	select STM32F7_IO_CONFIG_V
 	---help---
-		STM32 F7 Cortex M7, 512 320K FLASH, 320K (240+16+64) Kb SRAM
+		STM32 F7 Cortex M7, 512 FLASH, 320K (240+16+64) Kb SRAM
 config ARCH_CHIP_STM32F745IG
 	bool "STM32F745IG"
@@ -835,7 +835,7 @@ config STM32F7_FLASH_CONFIG_E
 	bool
 	default n
-config STM32F7_FLASH_CONFIG_I
+config STM32F7_FLASH_CONFIG_G
 	bool
 	default n
@@ -844,7 +844,7 @@ config STM32F7_FLASH_CONFIG_I
 	default n
 choice
-	prompt "Overrdide Flash Size Designator"
+	prompt "Override Flash Size Designator"
 	depends on ARCH_CHIP_STM32F7
 	default STM32F7_FLASH_OVERRIDE_DEFAULT
 	---help---
@@ -862,7 +862,7 @@ choice
 		Examples:
 		   If the STM32F745VE is chosen, the Flash configuration would be 'E', if a variant of
-		   the part with a  2048 KiB Flash is released in the future one could simply select
+		   the part with a 2048 KiB Flash is released in the future one could simply select
 		   the 'I' designator here.
 		   If an STM32F7xxx Series parts is chosen the default Flash configuration will be set
@@ -880,7 +880,7 @@ config STM32F7_FLASH_OVERRIDE_G
 config STM32F7_FLASH_OVERRIDE_I
 			bool "I 2048KiB"
-endchoice # "Overrdide Flash Size Designator"
+endchoice # "Override Flash Size Designator"
 menu "STM32 Peripheral Support"
@@ -895,7 +895,6 @@ config STM32F7_HAVE_FSMC
 	bool
 	default n
 config STM32F7_HAVE_ETHRNET
 	bool
 	default n
@@ -928,7 +927,6 @@ config STM32F7_HAVE_ADC3_DMA
 	bool
 	default n
 config STM32F7_HAVE_CAN3
 	bool
 	default n
@@ -966,7 +964,7 @@ config STM32F7_HAVE_DFSDM1
 	default n
 # These "hidden" settings are the OR of individual peripheral selections
-# indicating that the general capabilitiy is required.
+# indicating that the general capability is required.
 config STM32F7_ADC
 	bool
@@ -1616,6 +1614,18 @@ config UART8_RXDMA
 	---help---
 		In high data rate usage, Rx DMA may eliminate Rx overrun errors
 config STM32F7_SERIAL_RXDMA_BUFFER_SIZE
 	int "Rx DMA buffer size"
 	default 32
 	depends on USART1_RXDMA || USART2_RXDMA || USART3_RXDMA || UART4_RXDMA || UART5_RXDMA || USART6_RXDMA || UART7_RXDMA || UART8_RXDMA
 	---help---
 		The DMA buffer size when using RX DMA to emulate a FIFO.
 		When streaming data, the generic serial layer will be called
 		every time the FIFO receives half this number of bytes.
 		Value given here will be rounded up to next multiple of 32 bytes.
 config SERIAL_DISABLE_REORDERING
 	bool "Disable reordering of ttySx devices."
 	depends on STM32F7_USART1 || STM32F7_USART2 || STM32F7_USART3 || STM32F7_UART4 || STM32F7_UART5 || STM32F7_USART6 || STM32F7_UART7 || STM32F7_UART8
@@ -56,13 +56,11 @@
 #define _K(x) ((x)*1024)
 #if !defined(CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT) && \
-    !defined(CONFIG_STM32_FLASH_OVERRIDE_E) && \
+    !defined(CONFIG_STM32F7_FLASH_OVERRIDE_E) && \
-    !defined(CONFIG_STM32_FLASH_OVERRIDE_F) && \
+    !defined(CONFIG_STM32F7_FLASH_OVERRIDE_G) && \
-    !defined(CONFIG_STM32_FLASH_OVERRIDE_G) && \
+    !defined(CONFIG_STM32F7_FLASH_CONFIG_E) && \
-    !defined(CONFIG_STM32_FLASH_CONFIG_E) && \
+    !defined(CONFIG_STM32F7_FLASH_CONFIG_G)
-    !defined(CONFIG_STM32_FLASH_CONFIG_F) && \
+#  define CONFIG_STM32F7_FLASH_OVERRIDE_E
    !defined(CONFIG_STM32_FLASH_CONFIG_G)
 #  define CONFIG_STM32_FLASH_OVERRIDE_E
 #  warning "Flash size not defined defaulting to 512KiB (E)"
 #endif
@@ -82,14 +80,14 @@
 #  endif
 #endif
-#if defined(CONFIG_STM32_FLASH_CONFIG_E)
+#if defined(CONFIG_STM32F7_FLASH_CONFIG_E)
 #  define STM32_FLASH_NPAGES      6
 #  define STM32_FLASH_SIZE        _K((4 * 32) + (1 * 128) + (1 * 256))
 #  define STM32_FLASH_SIZES       {_K(32), _K(32), _K(32), _K(32),  \
                                   _K(128), _K(256)}
-#elif defined(CONFIG_STM32_FLASH_CONFIG_G)
+#elif defined(CONFIG_STM32F7_FLASH_CONFIG_G)
 #  define STM32_FLASH_NPAGES      8
 #  define STM32_FLASH_SIZE        _K((4 * 32) + (1 * 128) + (3 * 256))
@@ -56,15 +56,13 @@
 #define _K(x) ((x)*1024)
 #if !defined(CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT) && \
-    !defined(CONFIG_STM32_FLASH_OVERRIDE_E) && \
+    !defined(CONFIG_STM32F7_FLASH_OVERRIDE_E) && \
-    !defined(CONFIG_STM32_FLASH_OVERRIDE_F) && \
+    !defined(CONFIG_STM32F7_FLASH_OVERRIDE_G) && \
-    !defined(CONFIG_STM32_FLASH_OVERRIDE_G) && \
+    !defined(CONFIG_STM32F7_FLASH_OVERRIDE_I) && \
-    !defined(CONFIG_STM32_FLASH_OVERRIDE_I) && \
+    !defined(CONFIG_STM32F7_FLASH_CONFIG_E) && \
-    !defined(CONFIG_STM32_FLASH_CONFIG_E) && \
+    !defined(CONFIG_STM32F7_FLASH_CONFIG_G) && \
-    !defined(CONFIG_STM32_FLASH_CONFIG_F) && \
+    !defined(CONFIG_STM32F7_FLASH_CONFIG_I)
-    !defined(CONFIG_STM32_FLASH_CONFIG_G) && \
+#  define CONFIG_STM32F7_FLASH_OVERRIDE_E
    !defined(CONFIG_STM32_FLASH_CONFIG_I)
 #  define CONFIG_STM32_FLASH_OVERRIDE_E
 #  warning "Flash size not defined defaulting to 512KiB (E)"
 #endif
@@ -89,21 +87,21 @@
 #  endif
 #endif
-#if defined(CONFIG_STM32_FLASH_CONFIG_E)
+#if defined(CONFIG_STM32F7_FLASH_CONFIG_E)
 #  define STM32_FLASH_NPAGES      6
 #  define STM32_FLASH_SIZE        _K((4 * 32) + (1 * 128) + (1 * 256))
 #  define STM32_FLASH_SIZES       {_K(32), _K(32), _K(32), _K(32),  \
                                   _K(128), _K(256)}
-#elif defined(CONFIG_STM32_FLASH_CONFIG_G)
+#elif defined(CONFIG_STM32F7_FLASH_CONFIG_G)
 #  define STM32_FLASH_NPAGES      8
 #  define STM32_FLASH_SIZE        _K((4 * 32) + (1 * 128) + (3 * 256))
 #  define STM32_FLASH_SIZES       {_K(32), _K(32), _K(32), _K(32),  \
                                  _K(128), _K(256), _K(256), _K(256)}
-#elif defined(CONFIG_STM32_FLASH_CONFIG_I)
+#elif defined(CONFIG_STM32F7_FLASH_CONFIG_I)
 #  define STM32_FLASH_NPAGES      12
 #  define STM32_FLASH_SIZE        _K((4 * 32) + (1 * 128) + (7 * 256))
@@ -2141,7 +2141,7 @@ static int stm32_i2c_isr(int irq, void *context, FAR void *arg)
  struct stm32_i2c_priv_s *priv = (struct stm32_i2c_priv_s *)arg;
  DEBUGASSERT(priv != NULL);
-  return stm32_i2c_isr_process(&stm32_i2c1_priv);
+  return stm32_i2c_isr_process(priv);
 }
 #endif
@@ -159,15 +159,30 @@
 /* The DMA buffer size when using RX DMA to emulate a FIFO.
 *
- * When streaming data, the generic serial layer will be called
+ * When streaming data, the generic serial layer will be called every time
- * every time the FIFO receives half this number of bytes.
+ * the FIFO receives half this number of bytes.
 *
- * This buffer size should be an even multiple of the Cortex-M7
+ * This buffer size should be an even multiple of the Cortex-M7 D-Cache line
- * D-Cache line size so that it can be individually invalidated.
+ * size, ARMV7M_DCACHE_LINESIZE, so that it can be individually invalidated.
 *
 * Should there be a Cortex-M7 without a D-Cache, ARMV7M_DCACHE_LINESIZE
 * would be zero!
 */
 #  if !defined(ARMV7M_DCACHE_LINESIZE) || ARMV7M_DCACHE_LINESIZE == 0
 #    undef ARMV7M_DCACHE_LINESIZE
 #    define ARMV7M_DCACHE_LINESIZE 32
 #  endif
 #  if !defined(CONFIG_STM32F7_SERIAL_RXDMA_BUFFER_SIZE) || \
      (CONFIG_STM32F7_SERIAL_RXDMA_BUFFER_SIZE < ARMV7M_DCACHE_LINESIZE)
 #    undef CONFIG_STM32F7_SERIAL_RXDMA_BUFFER_SIZE
 #    define CONFIG_STM32F7_SERIAL_RXDMA_BUFFER_SIZE ARMV7M_DCACHE_LINESIZE
 #  endif
 #  define RXDMA_BUFFER_MASK   (ARMV7M_DCACHE_LINESIZE - 1)
-#  define RXDMA_BUFFER_SIZE   ((32 + RXDMA_BUFFER_MASK) & ~RXDMA_BUFFER_MASK)
+#  define RXDMA_BUFFER_SIZE   ((CONFIG_STM32F7_SERIAL_RXDMA_BUFFER_SIZE \
                                + RXDMA_BUFFER_MASK) & ~RXDMA_BUFFER_MASK)
 /* DMA priority */
@@ -61,6 +61,18 @@ endchoice # STM32 L4 Chip Selection
 # Chip families
 config STM32L4_STM32L4X3
 	bool
 	default n
 	select STM32L4_HAVE_USART1
 	select STM32L4_HAVE_USART2
 	select STM32L4_HAVE_USART3 if !(STM32L4_L432XX || STM32L4_L442XX)
 	select STM32L4_HAVE_LPTIM1
 	select STM32L4_HAVE_LPTIM2
 	select STM32L4_HAVE_COMP
 	select STM32L4_HAVE_SAI1
 	select STM32L4_HAVE_LCD if !(STM32L4_STM32L4X1 || STM32L4_STM32L4X2)
 config STM32L4_STM32L4X5
 	bool
 	default n
 	select STM32L4_HAVE_USART1
@@ -91,18 +103,12 @@ config STM32L4_STM32L476XX
 	default n
 	select STM32L4_STM32L4X6
 	select ARCH_HAVE_FPU
 	select ARCH_HAVE_DPFPU # REVISIT
 	select ARMV7M_HAVE_ITCM
 	select ARMV7M_HAVE_DTCM
 config STM32L4_STM32L486XX
 	bool
 	default n
 	select STM32L4_STM32L4X6
 	select ARCH_HAVE_FPU
 	select ARCH_HAVE_DPFPU # REVISIT
 	select ARMV7M_HAVE_ITCM
 	select ARMV7M_HAVE_DTCM
 	select STM32L4_FLASH_1024KB
 config STM32L4_STM32L496XX
@@ -110,9 +116,6 @@ config STM32L4_STM32L496XX
 	default n
 	select STM32L4_STM32L4X6
 	select ARCH_HAVE_FPU
 	select ARCH_HAVE_DPFPU # REVISIT
 	select ARMV7M_HAVE_ITCM
 	select ARMV7M_HAVE_DTCM
 	select STM32L4_HAVE_I2C4
 	select STM32L4_HAVE_CAN2
 	select STM32L4_HAVE_DCMI
@@ -127,13 +127,6 @@ ifeq ($(CONFIG_BUILD_PROTECTED),y)
 CHIP_CSRCS += stm32l4_userspace.c stm32l4_mpuinit.c
 endif
 ifeq ($(CONFIG_ARMV7M_DTCM),y)
 CHIP_CSRCS += stm32l4_dtcm.c
 ifeq ($(CONFIG_STM32L4_DTCM_PROCFS),y)
 CHIP_CSRCS += stm32l4_procfs_dtcm.c
 endif
 endif
 ifeq ($(CONFIG_STM32L4_DMA),y)
 CHIP_CSRCS += stm32l4_dma.c
 endif
@@ -166,6 +166,19 @@
 #  define STM32L4_GPIOH_AFRH         (STM32L4_GPIOH_BASE+STM32L4_GPIO_AFRH_OFFSET)
 #endif
 #if STM32L4_NPORTS > 8
 #  define STM32L4_GPIOI_MODER        (STM32L4_GPIOI_BASE+STM32L4_GPIO_MODER_OFFSET)
 #  define STM32L4_GPIOI_OTYPER       (STM32L4_GPIOI_BASE+STM32L4_GPIO_OTYPER_OFFSET)
 #  define STM32L4_GPIOI_OSPEED       (STM32L4_GPIOI_BASE+STM32L4_GPIO_OSPEED_OFFSET)
 #  define STM32L4_GPIOI_PUPDR        (STM32L4_GPIOI_BASE+STM32L4_GPIO_PUPDR_OFFSET)
 #  define STM32L4_GPIOI_IDR          (STM32L4_GPIOI_BASE+STM32L4_GPIO_IDR_OFFSET)
 #  define STM32L4_GPIOI_ODR          (STM32L4_GPIOI_BASE+STM32L4_GPIO_ODR_OFFSET)
 #  define STM32L4_GPIOI_BSRR         (STM32L4_GPIOI_BASE+STM32L4_GPIO_BSRR_OFFSET)
 #  define STM32L4_GPIOI_LCKR         (STM32L4_GPIOI_BASE+STM32L4_GPIO_LCKR_OFFSET)
 #  define STM32L4_GPIOI_AFRL         (STM32L4_GPIOI_BASE+STM32L4_GPIO_AFRL_OFFSET)
 #  define STM32L4_GPIOI_AFRH         (STM32L4_GPIOI_BASE+STM32L4_GPIO_AFRH_OFFSET)
 #endif
 /* Register Bitfield Definitions ****************************************************/
 /* GPIO port mode register */
@@ -163,7 +163,36 @@
 #define GPIO_DCMI_HSYNC_1      (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN4)
 #define GPIO_DCMI_HSYNC_2      (GPIO_ALT|GPIO_AF10|GPIO_PORTD|GPIO_PIN8)
 #define GPIO_DCMI_VSYNC_1      (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN7)
-/* TODO: DCMI data pins missing */
+#define GPIO_DCMI_VSYNC_2      (GPIO_ALT|GPIO_AF10|GPIO_PORTI|GPIO_PIN5)
 #define GPIO_DCMI_D0_1         (GPIO_ALT|GPIO_AF5|GPIO_PORTA|GPIO_PIN9)
 #define GPIO_DCMI_D0_2         (GPIO_ALT|GPIO_AF10|GPIO_PORTC|GPIO_PIN6)
 #define GPIO_DCMI_D1_1         (GPIO_ALT|GPIO_AF5|GPIO_PORTA|GPIO_PIN10)
 #define GPIO_DCMI_D1_2         (GPIO_ALT|GPIO_AF10|GPIO_PORTC|GPIO_PIN7)
 #define GPIO_DCMI_D2_1         (GPIO_ALT|GPIO_AF10|GPIO_PORTC|GPIO_PIN8)
 #define GPIO_DCMI_D2_2         (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN0)
 #define GPIO_DCMI_D3_1         (GPIO_ALT|GPIO_AF4|GPIO_PORTC|GPIO_PIN9)
 #define GPIO_DCMI_D3_2         (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN1)
 #define GPIO_DCMI_D4_1         (GPIO_ALT|GPIO_AF10|GPIO_PORTC|GPIO_PIN11)
 #define GPIO_DCMI_D4_2         (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN4)
 #define GPIO_DCMI_D5_1         (GPIO_ALT|GPIO_AF4|GPIO_PORTD|GPIO_PIN3)
 #define GPIO_DCMI_D5_2         (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN6)
 #define GPIO_DCMI_D6_1         (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN8)
 #define GPIO_DCMI_D6_2         (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN5)
 #define GPIO_DCMI_D7_1         (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN9)
 #define GPIO_DCMI_D7_2         (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN6)
 #define GPIO_DCMI_D8_1         (GPIO_ALT|GPIO_AF10|GPIO_PORTC|GPIO_PIN10)
 #define GPIO_DCMI_D8_2         (GPIO_ALT|GPIO_AF10|GPIO_PORTH|GPIO_PIN6)
 #define GPIO_DCMI_D9_1         (GPIO_ALT|GPIO_AF10|GPIO_PORTC|GPIO_PIN12)
 #define GPIO_DCMI_D9_2         (GPIO_ALT|GPIO_AF10|GPIO_PORTH|GPIO_PIN7)
 #define GPIO_DCMI_D10_1        (GPIO_ALT|GPIO_AF4|GPIO_PORTD|GPIO_PIN6)
 #define GPIO_DCMI_D10_2        (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN5)
 #define GPIO_DCMI_D11_1        (GPIO_ALT|GPIO_AF10|GPIO_PORTD|GPIO_PIN2)
 #define GPIO_DCMI_D11_2        (GPIO_ALT|GPIO_AF10|GPIO_PORTF|GPIO_PIN10)
 #define GPIO_DCMI_D12_1        (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN4)
 #define GPIO_DCMI_D12_2        (GPIO_ALT|GPIO_AF10|GPIO_PORTF|GPIO_PIN11)
 #define GPIO_DCMI_D13_1        (GPIO_ALT|GPIO_AF10|GPIO_PORTG|GPIO_PIN15)
 #define GPIO_DCMI_D13_2        (GPIO_ALT|GPIO_AF10|GPIO_PORTI|GPIO_PIN0)
 /* Digital Filter for Sigma-Delta Modulators (DFSDM) */
@@ -300,14 +329,15 @@
 #define GPIO_I2C4_SDA_2        (GPIO_ALT|GPIO_AF3 |GPIO_PORTB|GPIO_PIN11)
 #define GPIO_I2C4_SDA_3        (GPIO_ALT|GPIO_AF2 |GPIO_PORTC|GPIO_PIN1)
 #define GPIO_I2C4_SDA_4        (GPIO_ALT|GPIO_AF4 |GPIO_PORTD|GPIO_PIN13)
 #define GPIO_I2C4_SDA_5        (GPIO_ALT|GPIO_AF4 |GPIO_PORTF|GPIO_PIN15)
 #define GPIO_I2C4_SCL_1        (GPIO_ALT|GPIO_AF5 |GPIO_PORTB|GPIO_PIN6)
 #define GPIO_I2C4_SCL_2        (GPIO_ALT|GPIO_AF3 |GPIO_PORTB|GPIO_PIN10)
 #define GPIO_I2C4_SCL_3        (GPIO_ALT|GPIO_AF2 |GPIO_PORTC|GPIO_PIN0)
 #define GPIO_I2C4_SCL_4        (GPIO_ALT|GPIO_AF4 |GPIO_PORTD|GPIO_PIN12)
 #define GPIO_I2C4_SCL_5        (GPIO_ALT|GPIO_AF4 |GPIO_PORTF|GPIO_PIN14)
 #define GPIO_I2C4_SMBA_1       (GPIO_ALT|GPIO_AF5 |GPIO_PORTA|GPIO_PIN14)
 #define GPIO_I2C4_SMBA_2       (GPIO_ALT|GPIO_AF4 |GPIO_PORTD|GPIO_PIN11)
-#define GPIO_I2C4_SMBA_3       (GPIO_ALT|GPIO_AF4 |GPIO_PORTD|GPIO_PIN11)
+#define GPIO_I2C4_SMBA_3       (GPIO_ALT|GPIO_AF4 |GPIO_PORTF|GPIO_PIN13)
 #define GPIO_I2C4_SMBA_4       (GPIO_ALT|GPIO_AF4 |GPIO_PORTF|GPIO_PIN13)
 /* JTAG */
@@ -88,6 +88,9 @@ const uint32_t g_gpiobase[STM32L4_NPORTS] =
 #if STM32L4_NPORTS > 7
  STM32L4_GPIOH_BASE,
 #endif
 #if STM32L4_NPORTS > 8
  STM32L4_GPIOI_BASE,
 #endif
 };
 /****************************************************************************
@@ -212,6 +212,7 @@
 #  define GPIO_PORTF                  (5 << GPIO_PORT_SHIFT)     /*   GPIOF */
 #  define GPIO_PORTG                  (6 << GPIO_PORT_SHIFT)     /*   GPIOG */
 #  define GPIO_PORTH                  (7 << GPIO_PORT_SHIFT)     /*   GPIOH */
 #  define GPIO_PORTI                  (8 << GPIO_PORT_SHIFT)     /*   GPIOI */
 /* This identifies the bit in the port:
 *
@@ -1535,7 +1535,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv)
 #ifdef CONFIG_STM32L4_I2C2
 static int stm32l4_i2c_isr(int irq, void *context, FAR void *arg)
 {
-  struct stm32l4_i2c_priv_s *priv = (struct stm32l4_i2c_priv_s *priv)arg;
+  struct stm32l4_i2c_priv_s *priv = (struct stm32l4_i2c_priv_s *)arg;
  DEBUGASSERT(priv != NULL);
  return stm32l4_i2c_isr_process(priv);
@@ -210,6 +210,9 @@ static inline void rcc_enableahb2(void)
 #endif
 #if STM32L4_NPORTS > 7
             | RCC_AHB2ENR_GPIOHEN
 #endif
 #if STM32L4_NPORTS > 8
             | RCC_AHB2ENR_GPIOIEN
 #endif
             );
 #endif
@@ -114,7 +114,6 @@ static inline int elf_sectname(FAR struct elf_loadinfo_s *loadinfo,
  /* Loop until we get the entire section name into memory */
  buffer    = loadinfo->iobuffer;
  bytesread = 0;
  for (; ; )
@@ -136,7 +135,7 @@ static inline int elf_sectname(FAR struct elf_loadinfo_s *loadinfo,
      /* Read that number of bytes into the array */
      buffer = &loadinfo->iobuffer[bytesread];
-      ret = elf_read(loadinfo, buffer, readlen, offset);
+      ret = elf_read(loadinfo, buffer, readlen, offset + bytesread);
      if (ret < 0)
        {
          berr("Failed to read section name\n");
@@ -708,7 +708,7 @@ config ARCH_BOARD_NUCLEO_144
 	select ARCH_HAVE_IRQBUTTONS
 	---help---
 		STMicro Nucleo-144 development board featuring STMicroelectronics
-		F2, F3, F4 and F7 MCU families.  The board is a "Hardware pattern"
+		F2, F3, F4, F7 and L4 MCU families.  The board is a "Hardware pattern"
 		that can be populated with the 144 pin package of the following MCUs:
 			Target STM32    Order code
@@ -716,14 +716,44 @@ config ARCH_BOARD_NUCLEO_144
 			STM32F303ZET6   NUCLEO-F303ZE
 			STM32F429ZIT6   NUCLEO-F429ZI
 			STM32F446ZET6   NUCLEO-F446ZE
 			STM32F746ZGT6   NUCLEO-F746ZG
 			STM32F767ZIT6   NUCLEO-F767ZI
 			STM32L496ZGT6   NUCLEO-L496ZG
 			STM32L496ZGT6P  NUCLEO-L496ZG-P
-		Supported in this release are:
+		Supported in this configuration are:
-			NUCLEO-F746ZG - STM32F746ZGT6 a 216MHz Cortex-M7, w/FPU - 1024KiB
+			NUCLEO-F746ZG - STM32F746ZGT6 a 216MHz Cortex-M7, w/FPU -
-				Flash memory and 320KiB SRAM.
+				1024KiB Flash memory and 320KiB SRAM.
 			NUCLEO-F767ZI - STM32F767ZIT6 a 216MHz Cortex-M7, w/DPFPU -
 				2048KiB Flash memory and 512KiB SRAM.
 config ARCH_BOARD_NUCLEO_L496ZG
 	bool "STM32L496 Nucleo L496ZG"
 	depends on ARCH_CHIP_STM32L496ZG
 	select ARCH_HAVE_LEDS
 	select ARCH_HAVE_BUTTONS
 	select ARCH_HAVE_IRQBUTTONS
 	---help---
 		STMicro Nucleo-144 development board featuring STMicroelectronics
 		F2, F3, F4, F7 and L4 MCU families.  The board is a "Hardware pattern"
 		that can be populated with the 144 pin package of the following MCUs:
 			Target STM32    Order code
 			STM32F207ZGT6   NUCLEO-F207ZG
 			STM32F303ZET6   NUCLEO-F303ZE
 			STM32F429ZIT6   NUCLEO-F429ZI
 			STM32F446ZET6   NUCLEO-F446ZE
 			STM32F746ZGT6   NUCLEO-F746ZG
 			STM32F767ZIT6   NUCLEO-F767ZI
 			STM32L496ZGT6   NUCLEO-L496ZG
 			STM32L496ZGT6P  NUCLEO-L496ZG-P
 		Supported in this configuration are:
 			NUCLEO-L496ZG - STM32L496ZGT6 a 80MHz Cortex-M4, w/FPU -
 				1024KiB Flash memory and 320KiB SRAM.
 config ARCH_BOARD_NUCLEO_F072RB
 	bool "STM32F072 Nucleo F072RB"
 	depends on ARCH_CHIP_STM32F072RB
@@ -733,6 +763,15 @@ config ARCH_BOARD_NUCLEO_F072RB
 	---help---
 		STMicro Nucleo F072RB board based on the STMicro STM32F072RBT6 MCU.
 config ARCH_BOARD_NUCLEO_F091RC
 	bool "STM32F091 Nucleo F091RC"
 	depends on ARCH_CHIP_STM32F091RC
 	select ARCH_HAVE_LEDS
 	select ARCH_HAVE_BUTTONS
 	select ARCH_HAVE_IRQBUTTONS
 	---help---
 		STMicro Nucleo F091RC board based on the STMicro STM32F091RCT6 MCU.
 config ARCH_BOARD_NUCLEO_F303RE
 	bool "STM32F303 Nucleo F303RE"
 	depends on ARCH_CHIP_STM32F303RE
@@ -1514,10 +1553,12 @@ config ARCH_BOARD
 	default "pic32mz-starterkit"       if ARCH_BOARD_PIC32MZ_STARTERKIT
 	default "nucleo-144"               if ARCH_BOARD_NUCLEO_144
 	default "nucleo-f072rb"            if ARCH_BOARD_NUCLEO_F072RB
 	default "nucleo-f091rc"            if ARCH_BOARD_NUCLEO_F091RC
 	default "nucleo-f303re"            if ARCH_BOARD_NUCLEO_F303RE
 	default "nucleo-f334r8"            if ARCH_BOARD_NUCLEO_F334R8
 	default "nucleo-f4x1re"            if ARCH_BOARD_NUCLEO_F401RE || ARCH_BOARD_NUCLEO_F411RE
 	default "nucleo-l476rg"            if ARCH_BOARD_NUCLEO_L476RG
 	default "nucleo-l496zg"            if ARCH_BOARD_NUCLEO_L496ZG
 	default "qemu-i486"                if ARCH_BOARD_QEMU_I486
 	default "sabre-6quad"              if ARCH_BOARD_SABRE_6QUAD
 	default "sama5d2-xult"             if ARCH_BOARD_SAMA5D2_XULT
@@ -1823,6 +1864,9 @@ endif
 if ARCH_BOARD_NUCLEO_F072RB
 source "configs/nucleo-f072rb/Kconfig"
 endif
 if ARCH_BOARD_NUCLEO_F091RC
 source "configs/nucleo-f091rc/Kconfig"
 endif
 if ARCH_BOARD_NUCLEO_F303RE
 source "configs/nucleo-f303re/Kconfig"
 endif
@@ -1835,6 +1879,9 @@ endif
 if ARCH_BOARD_NUCLEO_L476RG
 source "configs/nucleo-l476rg/Kconfig"
 endif
 if ARCH_BOARD_NUCLEO_L496ZG
 source "configs/nucleo-l496zg/Kconfig"
 endif
 if ARCH_BOARD_QEMU_I486
 source "configs/qemu-i486/Kconfig"
 endif
@@ -32,14 +32,17 @@ Nucleo-144 Boards:
 The Nucleo-144 is a standard board for use with several STM32 parts in the
 LQFP144 package.  Variants include
-  STM32 Part    Board Variant Name
+  STM32 Part     Board Variant Name
-  ------------- ------------------
+  -------------  ------------------
-  STM32F207ZGT6 NUCLEO-F207ZG
+  STM32F207ZGT6  NUCLEO-F207ZG
-  STM32F303ZET6 NUCLEO-F303ZE
+  STM32F303ZET6  NUCLEO-F303ZE
-  STM32F429ZIT6 NUCLEO-F429ZI
+  STM32F429ZIT6  NUCLEO-F429ZI
-  STM32F446ZET6 NUCLEO-F446ZE
+  STM32F446ZET6  NUCLEO-F446ZE
-  STM32F746ZGT6 NUCLEO-F746ZG
+  STM32F746ZGT6  NUCLEO-F746ZG
-  STM32F767ZIT6 NUCLEO-F767ZI
+  STM32F767ZIT6  NUCLEO-F767ZI
  STM32L496ZGT6  NUCLEO-L496ZG
  STM32L496ZGT6P NUCLEO-L496ZG-P
  ------------- ------------------
 This directory is intended to support all Nucleo-144 variants since the
@@ -48,9 +51,10 @@ board design provides uniformity in the documentation from ST and should
 allow us to quickly change configurations by just cloning a configuration
 and changing the CPU choice and board initialization.  Unfortunately for
 the developer, the CPU specific information must be extracted from the
-common information in the documentation.
+common information in the documentation. The exception are the STM32L496ZG
 boards, which are supported by configs/nucleo-l496zg
-Please read the User Manaul UM1727: Getting started with STM32 Nucleo board
+Please read the User Manual UM1727: Getting started with STM32 Nucleo board
 software development tools and take note of the Powering options for the
 board (6.3 Power supply and power selection) and the Solder bridges based
 hardware configuration changes that are configurable (6.11 Solder bridges).
@@ -1,5 +1,5 @@
 /****************************************************************************
- * config/nucleo-144/src/stm32_appinitilaize.c
+ * config/nucleo-144/src/stm32_appinitialize.c
 *
 *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
 *   Authors: Gregory Nutt <gnutt@nuttx.org>
@@ -42,6 +42,7 @@
 #include <nuttx/config.h>
 #include <sys/types.h>
 #include <sys/mount.h>
 #include <debug.h>
 #include <syslog.h>
@@ -0,0 +1,8 @@
 #
 # For a description of the syntax of this configuration file,
 # see the file kconfig-language.txt in the NuttX tools repository.
 #
 if ARCH_BOARD_NUCLEO_F091RC
 endif
@@ -0,0 +1,319 @@
 Nucleo-F091RC README
 ====================
  This README file discusess the port of NuttX to the STMicro Nucleo-F091RC
  board.  That board features the STM32F091RCT6 MCU with 256KiB of FLASH
  and 32KiB of SRAM.
 Contents
 ========
  - Nucleo-64 Boards
  - LEDs
  - Buttons
  - Serial Console
  - Configurations
 Nucleo-64 Boards
 ================
  The Nucleo-F091RC is a member of the Nucleo-64 board family.  The Nucleo-64
  is a standard board for use with several STM32 parts in the LQFP64 package.
  Variants including:
    Order code    Targeted STM32
    ------------- --------------
    NUCLEO-F030R8 STM32F030R8T6
    NUCLEO-F070RB STM32F070RBT6
    NUCLEO-F072RB STM32F072RBT6
    NUCLEO-F091RC STM32F091RCT6
    NUCLEO-F103RB STM32F103RBT6
    NUCLEO-F302R8 STM32F302R8T6
    NUCLEO-F303RE STM32F303RET6
    NUCLEO-F334R8 STM32F334R8T6
    NUCLEO-F401RE STM32F401RET6
    NUCLEO-F410RB STM32F410RBT6
    NUCLEO-F411RE STM32F411RET6
    NUCLEO-F446RE STM32F446RET6
    NUCLEO-L053R8 STM32L053R8T6
    NUCLEO-L073RZ STM32L073RZT6
    NUCLEO-L152RE STM32L152RET6
    NUCLEO-L452RE STM32L452RET6
    NUCLEO-L476RG STM32L476RGT6
 LEDs
 ====
  The Nucleo-64 board has one user controlable LED, User LD2.  This green
  LED is a user LED connected to Arduino signal D13 corresponding to STM32
  I/O PA5 (PB13 on other some other Nucleo-64 boards).
    - When the I/O is HIGH value, the LED is on
    - When the I/O is LOW, the LED is off
  These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is
  defined.  In that case, the usage by the board port is defined in
  include/board.h and src/stm32_autoleds.c. The LEDs are used to encode
  OS-related events as follows when the red LED (PE24) is available:
    SYMBOL                Meaning                   LD2
    -------------------  -----------------------  -----------
    LED_STARTED          NuttX has been started     OFF
    LED_HEAPALLOCATE     Heap has been allocated    OFF
    LED_IRQSENABLED      Interrupts enabled         OFF
    LED_STACKCREATED     Idle stack created         ON
    LED_INIRQ            In an interrupt            No change
    LED_SIGNAL           In a signal handler        No change
    LED_ASSERTION        An assertion failed        No change
    LED_PANIC            The system has crashed     Blinking
    LED_IDLE             MCU is is sleep mode       Not used
  Thus if LD2, NuttX has successfully booted and is, apparently, running
  normally.  If LD2 is flashing at approximately 2Hz, then a fatal error
  has been detected and the system has halted.
 Buttons
 =======
  B1 USER: the user button is connected to the I/O PC13 (pin 2) of the STM32
  microcontroller.
 Serial Console
 ==============
  USART1
  ------
  Pins and Connectors:
    RXD: PA10  D3  CN9 pin 3, CN10 pin 33
         PB7                  CN7  pin 21
    TXD: PA9   D8  CN5 pin 1, CN10 pin 21
         PB6   D10 CN5 pin 3, CN10 pin 17
  NOTE:  You may need to edit the include/board.h to select different USART1
  pin selections.
  TTL to RS-232 converter connection:
    Nucleo CN10 STM32F072RB
    ----------- ------------
    Pin 21 PA9  USART1_TX   *Warning you make need to reverse RX/TX on
    Pin 33 PA10 USART1_RX    some RS-232 converters
    Pin 20 GND
    Pin 8  U5V
  To configure USART1 as the console:
    CONFIG_STM32_USART1=y
    CONFIG_USART1_SERIALDRIVER=y
    CONFIG_USART1_SERIAL_CONSOLE=y
    CONFIG_USART1_RXBUFSIZE=256
    CONFIG_USART1_TXBUFSIZE=256
    CONFIG_USART1_BAUD=115200
    CONFIG_USART1_BITS=8
    CONFIG_USART1_PARITY=0
    CONFIG_USART1_2STOP=0
  USART2
  ------
  Pins and Connectors:
    RXD: PA3  To be provided
         PA15
         PD6
    TXD: PA2
         PA14
         PD5
  USART3
  ------
  Pins and Connectors:
    RXD: PB11 To be provided
         PC5
         PC11
         D9
    TXD: PB10
         PC4
         PC10
         D8
  See "Virtual COM Port" and "RS-232 Shield" below.
  USART3
  ------
  Pins and Connectors:
    RXD: PA1  To be provided
         PC11
    TXD: PA0
         PC10
  Virtual COM Port
  ----------------
  Yet another option is to use UART2 and the USB virtual COM port.  This
  option may be more convenient for long term development, but is painful
  to use during board bring-up.
  Solder Bridges.  This configuration requires:
  - SB62 and SB63 Open: PA2 and PA3 on STM32 MCU are disconnected to D1
    and D0 (pin 7 and pin 8) on Arduino connector CN9 and ST Morpho
    connector CN10.
  - SB13 and SB14 Closed:  PA2 and PA3 on STM32F103C8T6 (ST-LINK MCU) are
    connected to PA3 and PA2 on STM32 MCU to have USART communication
    between them. Thus SB61, SB62 and SB63 should be OFF.
  Configuring USART2 is the same as given above.
  Question:  What BAUD should be configure to interface with the Virtual
  COM port?  115200 8N1?
  Default
  -------
  As shipped, SB62 and SB63 are open and SB13 and SB14 closed, so the
  virtual COM port is enabled.
  RS-232 Shield
  -------------
  Supports a single RS-232 connected via
    Nucleo    STM32F4x1RE     Shield
    --------- --------------- --------
    CN9 Pin 1 PA3  USART2_RXD RXD
    CN9 Pin 2 PA2  USART2_TXD TXD
  Support for this shield is enabled by selecting USART2 and configuring
  SB13, 14, 62, and 63 as described above under "Virtual COM Port"
 Configurations
 ==============
  Information Common to All Configurations
  ----------------------------------------
  Each configuration is maintained in a sub-directory and can be
  selected as follow:
    cd tools
    ./configure.sh nucleo-f091rc/<subdir>
    cd -
  Before building, make sure the PATH environment variable includes the
  correct path to the directory than holds your toolchain binaries.
  And then build NuttX by simply typing the following.  At the conclusion of
  the make, the nuttx binary will reside in an ELF file called, simply, nuttx.
    make oldconfig
    make
  The <subdir> that is provided above as an argument to the tools/configure.sh
  must be is one of the following.
  NOTES:
    1. These configurations use the mconf-based configuration tool.  To
      change any of these configurations using that tool, you should:
      a. Build and install the kconfig-mconf tool.  See nuttx/README.txt
         see additional README.txt files in the NuttX tools repository.
      b. Execute 'make menuconfig' in nuttx/ in order to start the
         reconfiguration process.
    2. Unless stated otherwise, all configurations generate console
       output on USART2, as described above under "Serial Console".  The 
       elevant configuration settings are listed below:
         CONFIG_STM32_USART2=y
         CONFIG_STM32_USART2_SERIALDRIVER=y
         CONFIG_STM32_USART=y
         CONFIG_USART2_SERIALDRIVER=y
         CONFIG_USART2_SERIAL_CONSOLE=y
         CONFIG_USART2_RXBUFSIZE=256
         CONFIG_USART2_TXBUFSIZE=256
         CONFIG_USART2_BAUD=115200
         CONFIG_USART2_BITS=8
         CONFIG_USART2_PARITY=0
         CONFIG_USART2_2STOP=0
  3. All of these configurations are set up to build under Linux using the
     "GNU Tools for ARM Embedded Processors" that is maintained by ARM
     (unless stated otherwise in the description of the configuration).
       https://launchpad.net/gcc-arm-embedded
     That toolchain selection can easily be reconfigured using
     'make menuconfig'.  Here are the relevant current settings:
     Build Setup:
       CONFIG_HOST_LINUX=y                 : Linux environment
     System Type -> Toolchain:
       CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL=y : GNU ARM EABI toolchain
  Configuration sub-directories
  -----------------------------
  nsh:
    Configures the NuttShell (nsh) located at examples/nsh.  This
    configuration is focused on low level, command-line driver testing.
    NOTES:
    1. This initial release of this configuration was very minimal, but
       also very small:
       $ size nuttx
          text    data     bss     dec     hex filename
         32000      92    1172   33264    81f0 nuttx
       The current version, additional features have been enabled:  board
       bring-up initialization, button support, the procfs file system,
       and NSH built-in application support.  The size increased as follows:
       $ size nuttx
          text    data     bss     dec     hex filename
         40231      92    1208   41531    a23b nuttx
       Those additional features cost about 8KiB FLASH.  I believe that is a
       good use of the STM32F072RB's FLASH, but if you interested in the
       more minimal configuration, here is what was changed:
       Removed
         CONFIG_BINFMT_DISABLE=y
         CONFIG_DISABLE_MOUNTPOINT=y
         CONFIG_NSH_DISABLE_CD=y
       Added:
         CONFIG_ARCH_BUTTONS=y
         CONFIG_ARCH_IRQBUTTONS=y
         CONFIG_BUILTIN=y
         CONFIG_BUILTIN_PROXY_STACKSIZE=1024
         CONFIG_FS_PROCFS=y
         CONFIG_NSH_PROC_MOUNTPOINT="/proc"
         CONFIG_LIB_BOARDCTL=y
         CONFIG_NSH_ARCHINIT=y
         CONFIG_NSH_BUILTIN_APPS=y
       Support for NSH built-in applications is enabled for future use. 
       However, no built applications are enabled in this base configuration.
    2. C++ support for applications is NOT enabled.  That could be enabled
       with the following configuration changes:
         CONFIG_HAVE_CXX=y
         CONFIG_HAVE_CXXINITIALIZE=y
         CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y
       And also support fo C++ constructors under
       apps/platform/nucleo-stm32f072rb.
@@ -0,0 +1,241 @@
 /************************************************************************************
 * configs/nucleo-f091rc/include/board.h
 *
 *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
 *   Author: Gregory Nutt <gnutt@nuttx.org>
 *           Alan Carvalho de Assis <acassis@gmail.com>
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 * 3. Neither the name NuttX nor the names of its contributors may be
 *    used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 *
 ************************************************************************************/
 #ifndef __CONFIG_NUCLEO_F091RC_INCLUDE_BOARD_H
 #define __CONFIG_NUCLEO_F091RC_INCLUDE_BOARD_H
 /************************************************************************************
 * Included Files
 ************************************************************************************/
 #include <nuttx/config.h>
 #ifndef __ASSEMBLY__
 # include <stdint.h>
 #endif
 /************************************************************************************
 * Pre-processor Definitions
 ************************************************************************************/
 /* Clocking *************************************************************************/
 /* Four different clock sources can be used to drive the system clock (SYSCLK):
 *
 * - HSI high-speed internal oscillator clock
 *   Generated from an internal 8 MHz RC oscillator
 * - HSE high-speed external oscillator clock
 *   Normally driven by an external crystal (X3).  However, this crystal is not
 *   fitted on the Nucleo-F091RC board.
 * - PLL clock
 * - MSI multispeed internal oscillator clock
 *   The MSI clock signal is generated from an internal RC oscillator. Seven frequency
 *   ranges are available: 65.536 kHz, 131.072 kHz, 262.144 kHz, 524.288 kHz, 1.048 MHz,
 *   2.097 MHz (default value) and 4.194 MHz.
 *
 * The devices have the following two secondary clock sources
 * - LSI low-speed internal RC clock
 *   Drives the watchdog and RTC.  Approximately 37KHz
 * - LSE low-speed external oscillator clock
 *   Driven by 32.768KHz crystal (X2) on the OSC32_IN and OSC32_OUT pins.
 */
 #define STM32F0_BOARD_XTAL         8000000ul        /* X3 on board (not fitted)*/
 #define STM32F0_HSI_FREQUENCY      8000000ul        /* Approximately 8MHz */
 #define STM32F0_HSI14_FREQUENCY    14000000ul       /* HSI14 for ADC */
 #define STM32F0_HSI48_FREQUENCY    48000000ul       /* HSI48 for USB, only some STM32F0xx */
 #define STM32F0_HSE_FREQUENCY      STM32F0_BOARD_XTAL
 #define STM32F0_LSI_FREQUENCY      40000            /* Approximately 40KHz */
 #define STM32F0_LSE_FREQUENCY      32768            /* X2 on board */
 /* PLL Configuration
 *
 *   - PLL source is HSI       -> 8MHz input (nominal)
 *   - PLL source predivider 2 -> 4MHz divided down PLL VCO clock output
 *   - PLL multipler is 12     -> 48MHz PLL VCO clock output (for USB)
 *
 * Resulting SYSCLK frequency is 8MHz x 12 / 2 = 48MHz
 *
 * USB:
 *   If the USB interface is used in the application, it requires a precise
 *   48MHz clock which can be generated from either the (1) the internal
 *   main PLL with the HSE clock source using an HSE crystal oscillator.  In
 *   this case,  the PLL VCO clock (defined by STM32F0_CFGR_PLLMUL) must be
 *   programmed to output a 96 MHz frequency. This is required to provide a
 *   48MHz clock to the (USBCLK = PLLVCO/2).  Or (2) by using the internal
 *   48MHz oscillator in automatic trimming mode. The synchronization for
 *   this oscillator can be taken from the USB data stream itself (SOF
 *   signalization) which allows crystal-less operation.
 * SYSCLK
 *   The system clock is derived from the PLL VCO divided by the output
 *   division factor.
 * Limitations:
 *   - 96 MHz as PLLVCO when the product is in range 1 (1.8V),
 *   - 48 MHz as PLLVCO when the product is in range 2 (1.5V),
 *   - 24 MHz when the product is in range 3 (1.2V).
 *   - Output division to avoid exceeding 32 MHz as SYSCLK.
 *   - The minimum input clock frequency for PLL is 2 MHz (when using HSE as
 *     PLL source).
 */
 #define STM32F0_CFGR_PLLSRC        RCC_CFGR_PLLSRC_HSId2         /* Source is HSI/2 */
 #define STM32F0_PLLSRC_FREQUENCY   (STM32F0_HSI_FREQUENCY/2)     /* 8MHz / 2 = 4MHz */
 #ifdef CONFIG_STM32F0_USB
 #  undef  STM32F0_CFGR2_PREDIV                                   /* Not used with source HSI/2 */
 #  define STM32F0_CFGR_PLLMUL      RCC_CFGR_PLLMUL_CLKx12        /* PLLMUL = 12 */
 #  define STM32F0_PLL_FREQUENCY    (12*STM32F0_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */
 #else
 #  undef  STM32F0_CFGR2_PREDIV                                   /* Not used with source HSI/2 */
 #  define STM32F0_CFGR_PLLMUL      RCC_CFGR_PLLMUL_CLKx12        /* PLLMUL = 12 */
 #  define STM32F0_PLL_FREQUENCY    (12*STM32F0_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */
 #endif
 /* Use the PLL and set the SYSCLK source to be the divided down PLL VCO output
 * frequency (STM32F0_PLL_FREQUENCY divided by the PLLDIV value).
 */
 #define STM32F0_SYSCLK_SW          RCC_CFGR_SW_PLL       /* Use the PLL as the SYSCLK */
 #define STM32F0_SYSCLK_SWS         RCC_CFGR_SWS_PLL
 #ifdef CONFIG_STM32F0_USB
 #  define STM32F0_SYSCLK_FREQUENCY STM32F0_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */
 #else
 #  define STM32F0_SYSCLK_FREQUENCY STM32F0_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */
 #endif
 #define STM32F0_RCC_CFGR_HPRE      RCC_CFGR_HPRE_SYSCLK
 #define STM32F0_HCLK_FREQUENCY     STM32F0_SYSCLK_FREQUENCY
 #define STM32F0_BOARD_HCLK         STM32F0_HCLK_FREQUENCY    /* Same as above, to satisfy compiler */
 /* APB1 clock (PCLK1) is HCLK (48MHz) */
 #define STM32F0_RCC_CFGR_PPRE1     RCC_CFGR_PPRE1_HCLK
 #define STM32F0_PCLK1_FREQUENCY    (STM32F0_HCLK_FREQUENCY)
 /* APB2 clock (PCLK2) is HCLK (48MHz) */
 #define STM32F0_RCC_CFGR_PPRE2     RCC_CFGR_PPRE2_HCLK
 #define STM32F0_PCLK2_FREQUENCY    STM32F0_HCLK_FREQUENCY
 #define STM32F0_APB2_CLKIN         (STM32F0_PCLK2_FREQUENCY)
 /* APB1 timers 1-3, 6-7, and 14-17 will receive PCLK1 */
 #define STM32F0_APB1_TIM1_CLKIN    (STM32F0_PCLK1_FREQUENCY)
 #define STM32F0_APB1_TIM2_CLKIN    (STM32F0_PCLK1_FREQUENCY)
 #define STM32F0_APB1_TIM3_CLKIN    (STM32F0_PCLK1_FREQUENCY)
 #define STM32F0_APB1_TIM6_CLKIN    (STM32F0_PCLK1_FREQUENCY)
 #define STM32F0_APB1_TIM7_CLKIN    (STM32F0_PCLK1_FREQUENCY)
 #define STM32F0_APB1_TIM14_CLKIN   (STM32F0_PCLK1_FREQUENCY)
 #define STM32F0_APB1_TIM15_CLKIN   (STM32F0_PCLK1_FREQUENCY)
 #define STM32F0_APB1_TIM16_CLKIN   (STM32F0_PCLK1_FREQUENCY)
 #define STM32F0_APB1_TIM17_CLKIN   (STM32F0_PCLK1_FREQUENCY)
 /* LED definitions ******************************************************************/
 /* LEDs
 *
 * The Nucleo-64 board has one user controlable LED, User LD2.  This green
 * LED is a user LED connected to Arduino signal D13 corresponding to STM32
 * I/O PA5 (PB13 on other some other Nucleo-64 boards).
 *
 *   - When the I/O is HIGH value, the LED is on
 *   - When the I/O is LOW, the LED is off
 */
 /* LED index values for use with board_userled() */
 #define BOARD_LD2         0
 #define BOARD_NLEDS       1
 /* LED bits for use with board_userled_all() */
 #define BOARD_LD2_BIT     (1 << BOARD_LD2)
 /* These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is
 * defined.  In that case, the usage by the board port is defined in
 * include/board.h and src/sam_leds.c. The LEDs are used to encode OS-related
 * events as follows when the red LED (PE24) is available:
 *
 *   SYMBOL                Meaning                   LD2
 *   -------------------  -----------------------  -----------
 *   LED_STARTED          NuttX has been started     OFF
 *   LED_HEAPALLOCATE     Heap has been allocated    OFF
 *   LED_IRQSENABLED      Interrupts enabled         OFF
 *   LED_STACKCREATED     Idle stack created         ON
 *   LED_INIRQ            In an interrupt            No change
 *   LED_SIGNAL           In a signal handler        No change
 *   LED_ASSERTION        An assertion failed        No change
 *   LED_PANIC            The system has crashed     Blinking
 *   LED_IDLE             MCU is is sleep mode       Not used
 *
 * Thus if LD2, NuttX has successfully booted and is, apparently, running
 * normally.  If LD2 is flashing at approximately 2Hz, then a fatal error
 * has been detected and the system has halted.
 */
 #define LED_STARTED      0
 #define LED_HEAPALLOCATE 0
 #define LED_IRQSENABLED  0
 #define LED_STACKCREATED 1
 #define LED_INIRQ        2
 #define LED_SIGNAL       2
 #define LED_ASSERTION    2
 #define LED_PANIC        1
 /* Button definitions ***************************************************************/
 /* Buttons
 *
 * B1 USER: the user button is connected to the I/O PC13 (pin 2) of the STM32
 * microcontroller.
 */
 #define BUTTON_USER        0
 #define NUM_BUTTONS        1
 #define BUTTON_USER_BIT    (1 << BUTTON_USER)
 /* Alternate Pin Functions **********************************************************/
 /* USART 1 */
 #define GPIO_USART1_TX           GPIO_USART1_TX_2
 #define GPIO_USART1_RX           GPIO_USART1_RX_2
 /* USART 2 */
 #define GPIO_USART2_TX           GPIO_USART2_TX_3
 #define GPIO_USART2_RX           GPIO_USART2_RX_3
 #endif  /* __CONFIG_NUCLEO_F091RC_INCLUDE_BOARD_H */
@@ -0,0 +1,113 @@
 ############################################################################
 # configs/nucleo-f091rc/nsh/Make.defs
 #
 #   Copyright (C) 2017 Gregory Nutt. All rights reserved.
 #   Author: Gregory Nutt <gnutt@nuttx.org>
 #           Alan Carvalho de Assis <acassis@gmail.com>
 #
 # Redistribution and use in source and binary forms, with or without
 # modification, are permitted provided that the following conditions
 # are met:
 #
 # 1. Redistributions of source code must retain the above copyright
 #    notice, this list of conditions and the following disclaimer.
 # 2. Redistributions in binary form must reproduce the above copyright
 #    notice, this list of conditions and the following disclaimer in
 #    the documentation and/or other materials provided with the
 #    distribution.
 # 3. Neither the name NuttX nor the names of its contributors may be
 #    used to endorse or promote products derived from this software
 #    without specific prior written permission.
 #
 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
 # FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
 # COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
 # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
 # BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
 # OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
 # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 # LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
 # ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 # POSSIBILITY OF SUCH DAMAGE.
 #
 ############################################################################
 include ${TOPDIR}/.config
 include ${TOPDIR}/tools/Config.mk
 include ${TOPDIR}/arch/arm/src/armv6-m/Toolchain.defs
 LDSCRIPT = flash.ld
 ifeq ($(WINTOOL),y)
  # Windows-native toolchains
  DIRLINK = $(TOPDIR)/tools/copydir.sh
  DIRUNLINK = $(TOPDIR)/tools/unlink.sh
  MKDEP = $(TOPDIR)/tools/mkwindeps.sh
  ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}"
  ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}"
  ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}"
 else
  # Linux/Cygwin-native toolchain
  MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT)
  ARCHINCLUDES = -I. -isystem $(TOPDIR)/include
  ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx
  ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)
 endif
 CC = $(CROSSDEV)gcc
 CXX = $(CROSSDEV)g++
 CPP = $(CROSSDEV)gcc -E
 LD = $(CROSSDEV)ld
 AR = $(ARCROSSDEV)ar rcs
 NM = $(ARCROSSDEV)nm
 OBJCOPY = $(CROSSDEV)objcopy
 OBJDUMP = $(CROSSDEV)objdump
 ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'}
 ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1}
 ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
  ARCHOPTIMIZATION = -g
 endif
 ifneq ($(CONFIG_DEBUG_NOOPT),y)
  ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer
 endif
 ARCHCFLAGS = -fno-builtin
 ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -fno-rtti
 ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef
 ARCHWARNINGSXX = -Wall -Wshadow -Wundef
 ARCHDEFINES =
 ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10
 CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe
 CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS)
 CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe
 CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS)
 CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES)
 AFLAGS = $(CFLAGS) -D__ASSEMBLY__
 NXFLATLDFLAGS1 = -r -d -warn-common
 NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections
 LDNXFLATFLAGS = -e main -s 2048
 ASMEXT = .S
 OBJEXT = .o
 LIBEXT = .a
 EXEEXT =
 ifneq ($(CROSSDEV),arm-nuttx-elf-)
  LDFLAGS += -nostartfiles -nodefaultlibs
 endif
 ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
  LDFLAGS += -g
 endif
 HOSTCC = gcc
 HOSTINCLUDES = -I.
 HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe
 HOSTLDFLAGS =
@@ -0,0 +1,127 @@
 /****************************************************************************
 * configs/nucleo-f091rc/scripts/flash.ld
 *
 *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
 *   Author: Gregory Nutt <gnutt@nuttx.org>
 *           Alan Carvalho de Assis <acassis@gmail.com>
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 * 3. Neither the name NuttX nor the names of its contributors may be
 *    used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 *
 ****************************************************************************/
 /* The STM32F091RCT6 has 256Kb of FLASH beginning at address 0x0800:0000 and
 * 32Kb of SRAM at address 0x20000000.
 *
 * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000
 * where the code expects to begin execution by jumping to the entry point in
 * the 0x0800:0000 address range.
 */
 MEMORY
 {
    flash (rx) : ORIGIN = 0x08000000, LENGTH = 256K
    sram (rwx) : ORIGIN = 0x20000000, LENGTH = 32K
 }
 OUTPUT_ARCH(arm)
 EXTERN(_vectors)
 ENTRY(_stext)
 SECTIONS
 {
 	.text :
 	{
 		_stext = ABSOLUTE(.);
 		*(.vectors)
 		*(.text .text.*)
 		*(.fixup)
 		*(.gnu.warning)
 		*(.rodata .rodata.*)
 		*(.gnu.linkonce.t.*)
 		*(.glue_7)
 		*(.glue_7t)
 		*(.got)
 		*(.gcc_except_table)
 		*(.gnu.linkonce.r.*)
 		_etext = ABSOLUTE(.);
 	} > flash
 	.init_section :
 	{
 		_sinit = ABSOLUTE(.);
 		*(.init_array .init_array.*)
 		_einit = ABSOLUTE(.);
 	} > flash
 	.ARM.extab :
 	{
 		*(.ARM.extab*)
 	} > flash
 	__exidx_start = ABSOLUTE(.);
 	.ARM.exidx :
 	{
 		*(.ARM.exidx*)
 	} > flash
 	__exidx_end = ABSOLUTE(.);
 	_eronly = ABSOLUTE(.);
 	.data :
 	{
 		_sdata = ABSOLUTE(.);
 		*(.data .data.*)
 		*(.gnu.linkonce.d.*)
 		CONSTRUCTORS
 		_edata = ABSOLUTE(.);
 	} > sram AT > flash
 	.bss :
 	{
 		_sbss = ABSOLUTE(.);
 		*(.bss .bss.*)
 		*(.gnu.linkonce.b.*)
 		*(COMMON)
 		_ebss = ABSOLUTE(.);
 	} > sram
 	/* Stabs debugging sections. */
 	.stab 0 : { *(.stab) }
 	.stabstr 0 : { *(.stabstr) }
 	.stab.excl 0 : { *(.stab.excl) }
 	.stab.exclstr 0 : { *(.stab.exclstr) }
 	.stab.index 0 : { *(.stab.index) }
 	.stab.indexstr 0 : { *(.stab.indexstr) }
 	.comment 0 : { *(.comment) }
 	.debug_abbrev 0 : { *(.debug_abbrev) }
 	.debug_info 0 : { *(.debug_info) }
 	.debug_line 0 : { *(.debug_line) }
 	.debug_pubnames 0 : { *(.debug_pubnames) }
 	.debug_aranges 0 : { *(.debug_aranges) }
 }
@@ -0,0 +1,2 @@
 /.depend
 /Make.dep
@@ -0,0 +1,56 @@
 ############################################################################
 # configs/nucleo-f091rc/src/Makefile
 #
 #   Copyright (C) 2017 Gregory Nutt. All rights reserved.
 #   Author: Gregory Nutt <gnutt@nuttx.org>
 #           Alan Carvalho de Assis <acassis@gmail.com>
 #
 # Redistribution and use in source and binary forms, with or without
 # modification, are permitted provided that the following conditions
 # are met:
 #
 # 1. Redistributions of source code must retain the above copyright
 #    notice, this list of conditions and the following disclaimer.
 # 2. Redistributions in binary form must reproduce the above copyright
 #    notice, this list of conditions and the following disclaimer in
 #    the documentation and/or other materials provided with the
 #    distribution.
 # 3. Neither the name NuttX nor the names of its contributors may be
 #    used to endorse or promote products derived from this software
 #    without specific prior written permission.
 #
 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
 # FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
 # COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
 # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
 # BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
 # OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
 # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 # LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
 # ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 # POSSIBILITY OF SUCH DAMAGE.
 #
 ############################################################################
 -include $(TOPDIR)/Make.defs
 ASRCS =
 CSRCS = stm32_boot.c stm32_bringup.c
 ifeq ($(CONFIG_ARCH_LEDS),y)
 CSRCS += stm32_autoleds.c
 else
 CSRCS += stm32_userleds.c
 endif
 ifeq ($(CONFIG_ARCH_BUTTONS),y)
 CSRCS += stm32_buttons.c
 endif
 ifeq ($(CONFIG_LIB_BOARDCTL),y)
 CSRCS += stm32_appinit.c
 endif
 include $(TOPDIR)/configs/Board.mk
@@ -0,0 +1,123 @@
 /****************************************************************************
 * configs/nucleo-f091rc/src/nucleo-f091rc.h
 *
 *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
 *   Author: Gregory Nutt <gnutt@nuttx.org>
 *           Alan Carvalho de Assis <acassis@gmail.com>
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 * 3. Neither the name NuttX nor the names of its contributors may be
 *    used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 *
 ****************************************************************************/
 #ifndef __CONFIGS_NUCLEO_F091RC_SRC_NUCLEO_F091RC_H
 #define __CONFIGS_NUCLEO_F091RC_SRC_NUCLEO_F091RC_H
 /****************************************************************************
 * Included Files
 ****************************************************************************/
 #include <nuttx/config.h>
 #include <nuttx/compiler.h>
 #include <stdint.h>
 #include "stm32f0_gpio.h"
 /****************************************************************************
 * Pre-processor Definitions
 ****************************************************************************/
 /* Configuration ************************************************************/
 /* How many SPI modules does this chip support? */
 #if STM32F0_NSPI < 1
 #  undef CONFIG_STM32F0_SPI1
 #  undef CONFIG_STM32F0_SPI2
 #  undef CONFIG_STM32F0_SPI3
 #elif STM32F0_NSPI < 2
 #  undef CONFIG_STM32F0_SPI2
 #  undef CONFIG_STM32F0_SPI3
 #elif STM32F0_NSPI < 3
 #  undef CONFIG_STM32F0_SPI3
 #endif
 /* Nucleo-F091RC GPIOs ******************************************************/
 /* LED.  User LD2: the green LED is a user LED connected to Arduino signal
 * D13 corresponding to MCU I/O PA5 (pin 21) or PB13 (pin 34) depending on
 * the STM32 target.
 *
 * - When the I/O is HIGH value, the LED is on.
 * - When the I/O is LOW, the LED is off.
 */
 #define GPIO_LD2        (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_10MHz | \
                         GPIO_OUTPUT_CLEAR | GPIO_PORTA | GPIO_PIN5)
 /* Button definitions *******************************************************/
 /*   B1 USER: the user button is connected to the I/O PC13 (pin 2) of the STM32
 *   microcontroller.
 */
 #define MIN_IRQBUTTON   BUTTON_USER
 #define MAX_IRQBUTTON   BUTTON_USER
 #define NUM_IRQBUTTONS  1
 #define GPIO_BTN_USER   (GPIO_INPUT | GPIO_FLOAT | GPIO_EXTI | \
                         GPIO_PORTC | GPIO_PIN13)
 /****************************************************************************
 * Public Types
 ****************************************************************************/
 /****************************************************************************
 * Public data
 ****************************************************************************/
 #ifndef __ASSEMBLY__
 /****************************************************************************
 * Public Functions
 ****************************************************************************/
 /****************************************************************************
 * Name: stm32_bringup
 *
 * Description:
 *   Perform architecture-specific initialization
 *
 *   CONFIG_BOARD_INITIALIZE=y :
 *     Called from board_initialize().
 *
 *   CONFIG_BOARD_INITIALIZE=n && CONFIG_LIB_BOARDCTL=y :
 *     Called from the NSH library
 *
 ****************************************************************************/
 int stm32_bringup(void);
 #endif /* __ASSEMBLY__ */
 #endif /* __CONFIGS_NUCLEO_F091RC_SRC_NUCLEO_F091RC_H */
@@ -0,0 +1,87 @@
 /****************************************************************************
 * config/nucleo-f091rc/src/stm32_appinit.c
 *
 *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
 *   Author: Gregory Nutt <gnutt@nuttx.org>
 *           Alan Carvalho de Assis <acassis@gmail.com>
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 * 3. Neither the name NuttX nor the names of its contributors may be
 *    used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 *
 ****************************************************************************/
 /****************************************************************************
 * Included Files
 ****************************************************************************/
 #include <nuttx/config.h>
 #include <stdint.h>
 #include <nuttx/board.h>
 #include "nucleo-f091rc.h"
 /****************************************************************************
 * Public Functions
 ****************************************************************************/
 /****************************************************************************
 * Name: board_app_initialize
 *
 * Description:
 *   Perform application specific initialization.  This function is never
 *   called directly from application code, but only indirectly via the
 *   (non-standard) boardctl() interface using the command BOARDIOC_INIT.
 *
 * Input Parameters:
 *   arg - The boardctl() argument is passed to the board_app_initialize()
 *         implementation without modification.  The argument has no
 *         meaning to NuttX; the meaning of the argument is a contract
 *         between the board-specific initalization logic and the the
 *         matching application logic.  The value cold be such things as a
 *         mode enumeration value, a set of DIP switch switch settings, a
 *         pointer to configuration data read from a file or serial FLASH,
 *         or whatever you would like to do with it.  Every implementation
 *         should accept zero/NULL as a default configuration.
 *
 * Returned Value:
 *   Zero (OK) is returned on success; a negated errno value is returned on
 *   any failure to indicate the nature of the failure.
 *
 ****************************************************************************/
 int board_app_initialize(uintptr_t arg)
 {
  /* Did we already initialize via board_initialize()? */
 #ifndef CONFIG_BOARD_INITIALIZE
  return stm32_bringup();
 #else
  return OK;
 #endif
 }
@@ -0,0 +1,96 @@
 /****************************************************************************
 * configs/nucleo-f091rc/src/stm32_autoleds.c
 *
 *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
 *   Author: Gregory Nutt <gnutt@nuttx.org>
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 * 3. Neither the name NuttX nor the names of its contributors may be
 *    used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 *
 ****************************************************************************/
 /****************************************************************************
 * Included Files
 ****************************************************************************/
 #include <nuttx/config.h>
 #include <stdint.h>
 #include <stdbool.h>
 #include <debug.h>
 #include <nuttx/board.h>
 #include <arch/board/board.h>
 #include "chip.h"
 #include "up_arch.h"
 #include "up_internal.h"
 #include "stm32f0_gpio.h"
 #include "nucleo-f091rc.h"
 #ifdef CONFIG_ARCH_LEDS
 /****************************************************************************
 * Public Functions
 ****************************************************************************/
 /****************************************************************************
 * Name: board_autoled_initialize
 ****************************************************************************/
 void board_autoled_initialize(void)
 {
  /* Configure LD2 GPIO for output */
  stm32f0_configgpio(GPIO_LD2);
 }
 /****************************************************************************
 * Name: board_autoled_on
 ****************************************************************************/
 void board_autoled_on(int led)
 {
  if (led == 1)
    {
      stm32f0_gpiowrite(GPIO_LD2, true);
    }
 }
 /****************************************************************************
 * Name: board_autoled_off
 ****************************************************************************/
 void board_autoled_off(int led)
 {
  if (led == 1)
    {
      stm32f0_gpiowrite(GPIO_LD2, false);
    }
 }
 #endif /* CONFIG_ARCH_LEDS */
@@ -0,0 +1,94 @@
 /************************************************************************************
 * configs/nucleo-f091rc/src/stm32f0_boot.c
 *
 *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
 *   Author: Gregory Nutt <gnutt@nuttx.org>
 *           Alan Carvalho de Assis <acassis@gmail.com>
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 * 3. Neither the name NuttX nor the names of its contributors may be
 *    used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 *
 ************************************************************************************/
 /************************************************************************************
 * Included Files
 ************************************************************************************/
 #include <nuttx/config.h>
 #include <debug.h>
 #include <nuttx/board.h>
 #include <arch/board/board.h>
 #include "up_arch.h"
 #include "nucleo-f091rc.h"
 /************************************************************************************
 * Public Functions
 ************************************************************************************/
 /************************************************************************************
 * Name: stm32f0_boardinitialize
 *
 * Description:
 *   All STM32 architectures must provide the following entry point.  This entry point
 *   is called early in the intitialization -- after all memory has been configured
 *   and mapped but before any devices have been initialized.
 *
 ************************************************************************************/
 void stm32f0_boardinitialize(void)
 {
 #ifdef CONFIG_ARCH_LEDS
  /* Configure on-board LEDs if LED support has been selected. */
  board_autoled_initialize();
 #endif
 }
 /****************************************************************************
 * Name: board_initialize
 *
 * Description:
 *   If CONFIG_BOARD_INITIALIZE is selected, then an additional
 *   initialization call will be performed in the boot-up sequence to a
 *   function called board_initialize().  board_initialize() will be
 *   called immediately after up_initialize() is called and just before the
 *   initial application is started.  This additional initialization phase
 *   may be used, for example, to initialize board-specific device drivers.
 *
 ****************************************************************************/
 #ifdef CONFIG_BOARD_INITIALIZE
 void board_initialize(void)
 {
  /* Perform board-specific initialization here if so configured */
  (void)stm32_bringup();
 }
 #endif
@@ -0,0 +1,82 @@
 /****************************************************************************
 * config/nucleo-f091rc/src/stm32_bringup.c
 *
 *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
 *   Author: Gregory Nutt <gnutt@nuttx.org>
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 * 3. Neither the name NuttX nor the names of its contributors may be
 *    used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 *
 ****************************************************************************/
 /****************************************************************************
 * Included Files
 ****************************************************************************/
 #include <nuttx/config.h>
 #include <sys/mount.h>
 #include <sys/types.h>
 #include <debug.h>
 #include "nucleo-f091rc.h"
 /****************************************************************************
 * Public Functions
 ****************************************************************************/
 /****************************************************************************
 * Name: stm32_bringup
 *
 * Description:
 *   Perform architecture-specific initialization
 *
 *   CONFIG_BOARD_INITIALIZE=y :
 *     Called from board_initialize().
 *
 *   CONFIG_BOARD_INITIALIZE=n && CONFIG_LIB_BOARDCTL=y :
 *     Called from the NSH library
 *
 ****************************************************************************/
 int stm32_bringup(void)
 {
  int ret;
 #ifdef CONFIG_FS_PROCFS
  /* Mount the procfs file system */
  ret = mount(NULL, "/proc", "procfs", 0, NULL);
  if (ret < 0)
    {
      ferr("ERROR: Failed to mount procfs at /proc: %d\n", ret);
    }
 #endif
  UNUSED(ret);
  return OK;
 }
@@ -0,0 +1,128 @@
 /****************************************************************************
 * configs/nucleo-f091rc/src/stm32_buttons.c
 *
 *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
 *   Author: Gregory Nutt <gnutt@nuttx.org>
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 * 3. Neither the name NuttX nor the names of its contributors may be
 *    used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 *
 ****************************************************************************/
 /****************************************************************************
 * Included Files
 ****************************************************************************/
 #include <nuttx/config.h>
 #include <stdint.h>
 #include <stdbool.h>
 #include <errno.h>
 #include <nuttx/arch.h>
 #include <nuttx/board.h>
 #include <arch/board/board.h>
 #include "stm32f0_gpio.h"
 #include "nucleo-f091rc.h"
 #ifdef CONFIG_ARCH_BUTTONS
 /****************************************************************************
 * Public Functions
 ****************************************************************************/
 /****************************************************************************
 * Name: board_button_initialize
 *
 * Description:
 *   board_button_initialize() must be called to initialize button resources.
 *   After that, board_buttons() may be called to collect the current state
 *   of all buttons or board_button_irq() may be called to register button
 *   interrupt handlers.
 *
 ****************************************************************************/
 void board_button_initialize(void)
 {
  /* Configure the single button as an input.  NOTE that EXTI interrupts are
   * also configured for the pin.
   */
  stm32f0_configgpio(GPIO_BTN_USER);
 }
 /****************************************************************************
 * Name: board_buttons
 ****************************************************************************/
 uint32_t board_buttons(void)
 {
  /* Check that state of each USER button. A LOW value means that the key is
   * pressed.
   */
  bool released = stm32f0_gpioread(GPIO_BTN_USER);
  return !released;
 }
 /************************************************************************************
 * Button support.
 *
 * Description:
 *   board_button_initialize() must be called to initialize button resources.  After
 *   that, board_buttons() may be called to collect the current state of all
 *   buttons or board_button_irq() may be called to register button interrupt
 *   handlers.
 *
 *   After board_button_initialize() has been called, board_buttons() may be called to
 *   collect the state of all buttons.  board_buttons() returns an 32-bit bit set
 *   with each bit associated with a button.  See the BUTTON_*_BIT
 *   definitions in board.h for the meaning of each bit.
 *
 *   board_button_irq() may be called to register an interrupt handler that will
 *   be called when a button is depressed or released.  The ID value is a
 *   button enumeration value that uniquely identifies a button resource. See the
 *   BUTTON_* definitions in board.h for the meaning of enumeration
 *   value.
 *
 ************************************************************************************/
 #ifdef CONFIG_ARCH_IRQBUTTONS
 int board_button_irq(int id, xcpt_t irqhandler, FAR void *arg)
 {
  int ret = -EINVAL;
  if (id == BUTTON_USER)
    {
      ret = stm32f0_gpiosetevent(GPIO_BTN_USER, true, true, true, irqhandler, arg);
    }
  return ret;
 }
 #endif
 #endif /* CONFIG_ARCH_BUTTONS */
@@ -0,0 +1,217 @@
 /****************************************************************************
 * configs/nucleo-f091rc/src/stm32_userleds.c
 *
 *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
 *   Author: Gregory Nutt <gnutt@nuttx.org>
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 * 3. Neither the name NuttX nor the names of its contributors may be
 *    used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 *
 ****************************************************************************/
 /****************************************************************************
 * Included Files
 ****************************************************************************/
 #include <nuttx/config.h>
 #include <stdint.h>
 #include <stdbool.h>
 #include <debug.h>
 #include <arch/board/board.h>
 #include <nuttx/power/pm.h>
 #include "chip.h"
 #include "up_arch.h"
 #include "up_internal.h"
 #include "stm32f0_gpio.h"
 #include "nucleo-f091rc.h"
 #ifndef CONFIG_ARCH_LEDS
 /****************************************************************************
 * Private Function Prototypes
 ****************************************************************************/
 /* LED Power Management */
 #ifdef CONFIG_PM
 static void led_pm_notify(struct pm_callback_s *cb, int domain,
                          enum pm_state_e pmstate);
 static int led_pm_prepare(struct pm_callback_s *cb, int domain,
                          enum pm_state_e pmstate);
 #endif
 /****************************************************************************
 * Private Data
 ****************************************************************************/
 #ifdef CONFIG_PM
 static struct pm_callback_s g_ledscb =
 {
  .notify  = led_pm_notify,
  .prepare = led_pm_prepare,
 };
 #endif
 /****************************************************************************
 * Private Functions
 ****************************************************************************/
 /****************************************************************************
 * Name: led_pm_notify
 *
 * Description:
 *   Notify the driver of new power state. This callback is called after
 *   all drivers have had the opportunity to prepare for the new power state.
 *
 ****************************************************************************/
 #ifdef CONFIG_PM
 static void led_pm_notify(struct pm_callback_s *cb, int domain,
                          enum pm_state_e pmstate)
 {
  switch (pmstate)
    {
      case(PM_NORMAL):
        {
          /* Restore normal LEDs operation */
        }
        break;
      case(PM_IDLE):
        {
          /* Entering IDLE mode - Turn leds off */
        }
        break;
      case(PM_STANDBY):
        {
          /* Entering STANDBY mode - Logic for PM_STANDBY goes here */
        }
        break;
      case(PM_SLEEP):
        {
          /* Entering SLEEP mode - Logic for PM_SLEEP goes here */
        }
        break;
      default:
        {
          /* Should not get here */
        }
        break;
    }
 }
 #endif
 /****************************************************************************
 * Name: led_pm_prepare
 *
 * Description:
 *   Request the driver to prepare for a new power state. This is a warning
 *   that the system is about to enter into a new power state. The driver
 *   should begin whatever operations that may be required to enter power
 *   state. The driver may abort the state change mode by returning a
 *   non-zero value from the callback function.
 *
 ****************************************************************************/
 #ifdef CONFIG_PM
 static int led_pm_prepare(struct pm_callback_s *cb, int domain,
                          enum pm_state_e pmstate)
 {
  /* No preparation to change power modes is required by the LEDs driver.
   * We always accept the state change by returning OK.
   */
  return OK;
 }
 #endif
 /****************************************************************************
 * Public Functions
 ****************************************************************************/
 /****************************************************************************
 * Name: board_userled_initialize
 ****************************************************************************/
 void board_userled_initialize(void)
 {
  /* Configure LD2 GPIO for output */
  stm32f0_configgpio(GPIO_LD2);
 }
 /****************************************************************************
 * Name: board_userled
 ****************************************************************************/
 void board_userled(int led, bool ledon)
 {
  if (led == 1)
    {
      stm32f0_gpiowrite(GPIO_LD2, ldeon);
    }
 }
 /****************************************************************************
 * Name: board_userled_all
 ****************************************************************************/
 void board_userled_all(uint8_t ledset)
 {
  if (led == 1)
    {
      stm32f0_gpiowrite(GPIO_LD2, (ledset & BOARD_LD2_BIT) != 0);
    }
 }
 /****************************************************************************
 * Name: stm32f0_led_pminitialize
 ****************************************************************************/
 #ifdef CONFIG_PM
 void stm32f0_led_pminitialize(void)
 {
  /* Register to receive power management callbacks */
  int ret = pm_register(&g_ledscb);
  DEBUGASSERT(ret == OK);
  UNUSED(ret);
 }
 #endif /* CONFIG_PM */
 #endif /* !CONFIG_ARCH_LEDS */
@@ -237,8 +237,14 @@
 #define GPIO_USART1_RX GPIO_USART1_RX_1 /* PA10 */
 #define GPIO_USART1_TX GPIO_USART1_TX_1 /* PA9 */
-/* HRTIM */
+/* COMP */
 /* OPAMP */
 #define OPAMP2_VMSEL OPAMP2_VMSEL_PC5
 #define OPAMP2_VPSEL OPAMP2_VPSEL_PB14
 /* HRTIM */
 /* DMA channels *************************************************************/
 /* ADC */
@@ -202,4 +202,16 @@ int stm32_can_setup(void);
 int stm32_comp_setup(void);
 #endif
 /****************************************************************************
 * Name: stm32_opamp_setup
 *
 * Description:
 *  Initialize OPAMP peripheral for the board.
 *
 ****************************************************************************/
 #ifdef CONFIG_OPAMP
 int stm32_opamp_setup(void);
 #endif
 #endif /* __CONFIGS_NUCLEO_F334R8_SRC_NUCLEO_F334R8_H */
@@ -137,6 +137,16 @@ int board_app_initialize(uintptr_t arg)
    }
 #endif
 #ifdef CONFIG_OPAMP
  /* Initialize OPAMP and register the OPAMP driver. */
  ret = stm32_opamp_setup();
  if (ret < 0)
    {
      syslog(LOG_ERR, "ERROR: stm32_opamp_setup failed: %d\n", ret);
    }
 #endif
  UNUSED(ret);
  return OK;
 }
@@ -0,0 +1,99 @@
 /****************************************************************************
 * configs/nucleo-f334r8/src/stm32_opamp.c
 *
 *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
 *   Author: Mateusz Szafoni <raiden00@railab.me>
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 * 3. Neither the name NuttX nor the names of its contributors may be
 *    used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 *
 ****************************************************************************/
 /****************************************************************************
 * Included Files
 ****************************************************************************/
 #include <nuttx/config.h>
 #include <stdbool.h>
 #include <errno.h>
 #include <debug.h>
 #include <nuttx/board.h>
 #include <nuttx/analog/opamp.h>
 #include "stm32.h"
 #if defined(CONFIG_OPAMP) && defined(CONFIG_STM32_OPAMP2)
 /****************************************************************************
 * Public Functions
 ****************************************************************************/
 /****************************************************************************
 * Name: stm32_opamp_setup
 *
 * Description:
 *   Initialize OPAMP
 *
 ****************************************************************************/
 int stm32_opamp_setup(void)
 {
  static bool initialized = false;
  struct opamp_dev_s* opamp = NULL;
  int ret;
  if (!initialized)
    {
      /* Get the OPAMP interface */
 #ifdef CONFIG_STM32_OPAMP2
      opamp = stm32_opampinitialize(2);
      if (opamp == NULL)
        {
          aerr("ERROR: Failed to get OPAMP%d interface\n", 2);
          return -ENODEV;
        }
 #endif
      /* Register the OPAMP character driver at /dev/opamp0 */
      ret = opamp_register("/dev/opamp0", opamp);
      if (ret < 0)
        {
          aerr("ERROR: opamp_register failed: %d\n", ret);
          return ret;
        }
      initialized = true;
    }
  return OK;
 }
 #endif /* CONFIG_OPAMP && CONFIG_STM32_OPAMP2 */
@@ -6,9 +6,9 @@ NucleoL476RG board from ST Micro.  See
  http://www.st.com/nucleo-l476rg
-NucleoF476RG:
+NucleoL476RG:
-  Microprocessor: 32-bit ARM Cortex M4 at 80MHz STM32F476RGT6
+  Microprocessor: 32-bit ARM Cortex M4 at 80MHz STM32L476RGT6
  Memory:         1024 KB Flash and 96+32 KB SRAM
  ADC:            2×12-bit, 2.4 MSPS A/D converter: up to 24 channels
  DMA:            16-stream DMA controllers with FIFOs and burst support
@@ -34,7 +34,7 @@
 *
 ****************************************************************************/
-/* The STM32F411RE has 512Kb of FLASH beginning at address 0x0800:0000 and
+/* The STM32L476RG has 512Kb of FLASH beginning at address 0x0800:0000 and
 * 128Kb of SRAM beginning at address 0x2000:0000.  When booting from FLASH,
 * FLASH memory is aliased to address 0x0000:0000 where the code expects to
 * begin execution by jumping to the entry point in the 0x0800:0000 address
--- a/Show More
+++ b/Show More