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ieee802154: Adds some missing elements to start support for beacon-enabled networks

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This commit is contained in:
Anthony Merlino
2017-06-20 12:57:24 -04:00
parent 5a8668b362
commit 683bd6e10e
9 changed files with 1106 additions and 587 deletions
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drivers/wireless/ieee802154/mrf24j40.c
+207 -28
View File
@@ -103,6 +103,24 @@
#define MRF24J40_GTS_SLOTS 2
/* Clock configuration macros */
#define MRF24J40_SLPCLKPER_100KHZ ((1000 * 1000 * 1000)/100000) /* 10ns */
#define MRF24J40_SLPCLKPER_32KHZ ((1000 * 1000 * 1000)/32000) /* 31.25ns */
#define MRF24J40_BEACONINTERVAL_NSEC(beaconorder) \
(IEEE802154_BASE_SUPERFRAME_DURATION * (1 << beaconorder) * (16 *1000))
/* For now I am just setting the REMCNT to the maximum while staying in multiples
* of 10000 (100khz period) */
#define MRF24J40_REMCNT 60000
#define MRF24J40_REMCNT_NSEC (MRF24J40_REMCNT * 50)
#define MRF24J40_MAINCNT(bo, clkper) \
((MRF24J40_BEACONINTERVAL_NSEC(bo) - MRF24J40_REMCNT_NSEC) / \
clkper)
/* Formula for calculating default macMaxFrameWaitTime is on pg. 130
*
* For PHYs other than CSS and UWB, the attribute phyMaxFrameDuration is given by:
@@ -197,12 +215,12 @@ static int mrf24j40_interrupt(int irq, FAR void *context, FAR void *arg);
static void mrf24j40_dopoll_csma(FAR void *arg);
static void mrf24j40_dopoll_gts(FAR void *arg);
static int mrf24j40_norm_setup(FAR struct mrf24j40_radio_s *dev,
static void mrf24j40_norm_setup(FAR struct mrf24j40_radio_s *dev,
FAR struct iob_s *frame, bool csma);
static int mrf24j40_gts_setup(FAR struct mrf24j40_radio_s *dev, uint8_t gts,
static void mrf24j40_gts_setup(FAR struct mrf24j40_radio_s *dev, uint8_t gts,
FAR struct iob_s *frame);
static int mrf24j40_setup_fifo(FAR struct mrf24j40_radio_s *dev,
FAR struct iob_s *frame, uint32_t fifo_addr);
static void mrf24j40_setup_fifo(FAR struct mrf24j40_radio_s *dev,
FAR const uint8_t *buf, uint8_t length, uint32_t fifo_addr);
static inline void mrf24j40_norm_trigger(FAR struct mrf24j40_radio_s *dev);
@@ -242,6 +260,12 @@ static int mrf24j40_set_attr(FAR struct ieee802154_radio_s *radio,
static int mrf24j40_rxenable(FAR struct ieee802154_radio_s *dev, bool enable);
static int mrf24j40_req_rxenable(FAR struct ieee802154_radio_s *radio,
FAR struct ieee802154_rxenable_req_s *req);
static int mrf24j40_beaconstart(FAR struct ieee802154_radio_s *radio,
FAR const struct ieee802154_superframespec_s *sf_spec,
FAR struct ieee802154_beaconframe_s *beacon);
static int mrf24j40_beaconupdate(FAR struct ieee802154_radio_s *radio,
FAR struct ieee802154_beaconframe_s *beacon);
static int mrf24j40_beaconstop(FAR struct ieee802154_radio_s *radio);
/****************************************************************************
* Private Data
@@ -518,6 +542,150 @@ static int mrf24j40_req_rxenable(FAR struct ieee802154_radio_s *radio,
return -ENOTTY;
}
static int mrf24j40_beaconstart(FAR struct ieee802154_radio_s *radio,
FAR const struct ieee802154_superframespec_s *sf_spec,
FAR struct ieee802154_beaconframe_s *beacon)
{
FAR struct mrf24j40_radio_s *dev = (FAR struct mrf24j40_radio_s *)radio;
uint32_t maincnt = 0;
uint32_t slpcal = 0;
int reg;
if (sf_spec->pancoord)
{
/* Set the PANCOORD (RXMCR 0x00<3>) bit = 1to configure as PAN coordinator */
reg = mrf24j40_getreg(dev->spi, MRF24J40_RXMCR);
reg |= MRF24J40_RXMCR_PANCOORD;
mrf24j40_setreg(dev->spi, MRF24J40_RXMCR, reg);
/* Set the SLOTTED (TXMCR 0x11<5>) bit = 1 to use Slotted CSMA-CA mode */
reg = mrf24j40_getreg(dev->spi, MRF24J40_TXMCR);
reg |= MRF24J40_TXMCR_SLOTTED;
mrf24j40_setreg(dev->spi, MRF24J40_TXMCR, reg);
/* Load the beacon frame into the TXBFIFO (0x080-0x0FF). */
mrf24j40_setup_fifo(dev, beacon->bf_data, beacon->bf_len, MRF24J40_BEACON_FIFO);
/* Set the TXBMSK (TXBCON1 0x25<7>) bit = 1 to mask the beacon interrupt
* mask
*/
reg = mrf24j40_getreg(dev->spi, MRF24J40_TXBCON1);
reg |= MRF24J40_TXBCON1_TXBMSK;
mrf24j40_setreg(dev->spi, MRF24J40_TXBCON1, reg);
/* Set INTL (WAKECON 0x22<5:0>) value to 0x03. */
reg = mrf24j40_getreg(dev->spi, MRF24J40_WAKECON);
reg &= ~MRF24J40_WAKECON_INTL;
reg |= 0x03 & MRF24J40_WAKECON_INTL;
mrf24j40_setreg(dev->spi, MRF24J40_WAKECON, reg);
/* Program the CAP end slot (ESLOTG1 0x13<3:0>) value. */
reg = mrf24j40_getreg(dev->spi, MRF24J40_ESLOTG1);
reg &= ~MRF24J40_ESLOTG1_CAP;
reg |= sf_spec->final_capslot & MRF24J40_ESLOTG1_CAP;
mrf24j40_setreg(dev->spi, MRF24J40_ESLOTG1, reg);
/* TODO: Add GTS related code. See pg 100 of datasheet */
/* Calibrate the Sleep Clock (SLPCLK) frequency. Refer to Section 3.15.1.2
* “Sleep Clock Calibration”.
*/
/* If the Sleep Clock Selection, SLPCLKSEL (0x207<7:6), is the internal
* oscillator (100 kHz), set SLPCLKDIV to a minimum value of 0x01.
*/
mrf24j40_setreg(dev->spi, MRF24J40_SLPCON1, 0x01);
/* Select the source of SLPCLK (internal 100kHz) */
mrf24j40_setreg(dev->spi, MRF24J40_RFCON7, MRF24J40_RFCON7_SEL_100KHZ);
/* Begin calibration by setting the SLPCALEN bit (SLPCAL2 0x20B<4>) to
* ‘1’. Sixteen samples of the SLPCLK are counted and stored in the
* SLPCAL register. No need to mask, this is the only writable bit
*/
mrf24j40_setreg(dev->spi, MRF24J40_SLPCAL2, MRF24J40_SLPCAL2_SLPCALEN);
/* Calibration is complete when the SLPCALRDY bit (SLPCAL2 0x20B<7>) is
* set to ‘1’.
*/
while (!(mrf24j40_getreg(dev->spi, MRF24J40_SLPCAL2) &
MRF24J40_SLPCAL2_SLPCALRDY))
{
usleep(1);
}
slpcal = mrf24j40_getreg(dev->spi, MRF24J40_SLPCAL0);
slpcal |= (mrf24j40_getreg(dev->spi, MRF24J40_SLPCAL1) << 8);
slpcal |= ((mrf24j40_getreg(dev->spi, MRF24J40_SLPCAL2) << 16) & 0x0F);
/* Set WAKECNT (SLPACK 0x35<6:0>) value = 0x5F to set the main oscillator
* (20 MHz) start-up timer value.
*/
mrf24j40_setreg(dev->spi, MRF24J40_SLPACK, 0x5F);
/* Program the Beacon Interval into the Main Counter, MAINCNT (0x229<1:0>,
* 0x228, 0x227, 0x226), and Remain Counter, REMCNT (0x225, 0x224),
* according to BO and SO values. Refer to Section 3.15.1.3 “Sleep Mode
* Counters”
*/
mrf24j40_setreg(dev->spi, MRF24J40_REMCNTL, (MRF24J40_REMCNT & 0xFF));
mrf24j40_setreg(dev->spi, MRF24J40_REMCNTH, ((MRF24J40_REMCNT >> 8) & 0xFF));
maincnt = MRF24J40_MAINCNT(sf_spec->beaconorder, (slpcal * 50 / 16));
mrf24j40_setreg(dev->spi, MRF24J40_MAINCNT0, (maincnt & 0xFF));
mrf24j40_setreg(dev->spi, MRF24J40_MAINCNT1, ((maincnt >> 8) & 0xFF));
mrf24j40_setreg(dev->spi, MRF24J40_MAINCNT2, ((maincnt >> 16) & 0xFF));
mrf24j40_setreg(dev->spi, MRF24J40_MAINCNT3, ((maincnt >> 24) & 0x03));
/* Enable the SLPIF and WAKEIF flags */
reg = mrf24j40_getreg(dev->spi, MRF24J40_INTCON);
reg &= ~(MRF24J40_INTCON_SLPIE | MRF24J40_INTCON_WAKEIE);
mrf24j40_setreg(dev->spi, MRF24J40_INTCON, reg);
/* Configure the BO (ORDER 0x10<7:4>) and SO (ORDER 0x10<3:0>) values.
* After configuring BO and SO, the beacon frame will be sent immediately.
*/
mrf24j40_setreg(dev->spi, MRF24J40_ORDER,
((sf_spec->beaconorder << 4) & 0xF0) | (sf_spec->sforder & 0x0F));
}
else
{
return -ENOTTY;
}
return OK;
}
static int mrf24j40_beaconupdate(FAR struct ieee802154_radio_s *radio,
FAR struct ieee802154_beaconframe_s *beacon)
{
FAR struct mrf24j40_radio_s *dev = (FAR struct mrf24j40_radio_s *)radio;
mrf24j40_setup_fifo(dev, beacon->bf_data, beacon->bf_len, MRF24J40_BEACON_FIFO);
return OK;
}
static int mrf24j40_beaconstop(FAR struct ieee802154_radio_s *radio)
{
return -ENOTTY;
}
/****************************************************************************
* Internal Functions
****************************************************************************/
@@ -1303,11 +1471,10 @@ static int mrf24j40_energydetect(FAR struct mrf24j40_radio_s *dev,
*
****************************************************************************/
static int mrf24j40_norm_setup(FAR struct mrf24j40_radio_s *dev,
FAR struct iob_s *frame, bool csma)
static void mrf24j40_norm_setup(FAR struct mrf24j40_radio_s *dev,
FAR struct iob_s *frame, bool csma)
{
uint8_t reg;
int ret;
/* Enable tx int */
@@ -1332,7 +1499,7 @@ static int mrf24j40_norm_setup(FAR struct mrf24j40_radio_s *dev,
/* Setup the FIFO */
ret = mrf24j40_setup_fifo(dev, frame, MRF24J40_TXNORM_FIFO);
mrf24j40_setup_fifo(dev, frame->io_data, frame->io_len, MRF24J40_TXNORM_FIFO);
/* If the frame control field contains an acknowledgment request, set the
* TXNACKREQ bit. See IEEE 802.15.4/2003 7.2.1.1 page 112 for info.
@@ -1350,8 +1517,6 @@ static int mrf24j40_norm_setup(FAR struct mrf24j40_radio_s *dev,
}
mrf24j40_setreg(dev->spi, MRF24J40_TXNCON, reg);
return ret;
}
/****************************************************************************
@@ -1381,10 +1546,10 @@ static inline void mrf24j40_norm_trigger(FAR struct mrf24j40_radio_s *dev)
*
****************************************************************************/
static int mrf24j40_gts_setup(FAR struct mrf24j40_radio_s *dev, uint8_t fifo,
FAR struct iob_s *frame)
static void mrf24j40_gts_setup(FAR struct mrf24j40_radio_s *dev, uint8_t fifo,
FAR struct iob_s *frame)
{
return -ENOTTY;
}
/****************************************************************************
@@ -1394,17 +1559,18 @@ static int mrf24j40_gts_setup(FAR struct mrf24j40_radio_s *dev, uint8_t fifo,
*
****************************************************************************/
static int mrf24j40_setup_fifo(FAR struct mrf24j40_radio_s *dev,
FAR struct iob_s *frame, uint32_t fifo_addr)
static void mrf24j40_setup_fifo(FAR struct mrf24j40_radio_s *dev,
FAR const uint8_t *buf, uint8_t length,
uint32_t fifo_addr)
{
int ret;
int hlen = 3; /* Include frame control and seq number */
int hlen = 3; /* Include frame control and seq number */
int i;
uint16_t frame_ctrl;
/* Analyze frame control to compute header length */
frame_ctrl = frame->io_data[0];
frame_ctrl |= (frame->io_data[1] << 8);
frame_ctrl = buf[0];
frame_ctrl |= (buf[1] << 8);
if ((frame_ctrl & IEEE802154_FRAMECTRL_DADDR)== IEEE802154_ADDRMODE_SHORT)
{
@@ -1435,16 +1601,14 @@ static int mrf24j40_setup_fifo(FAR struct mrf24j40_radio_s *dev,
/* Frame length */
mrf24j40_setreg(dev->spi, fifo_addr++, frame->io_len);
mrf24j40_setreg(dev->spi, fifo_addr++, length);
/* Frame data */
for (ret = 0; ret < frame->io_len; ret++) /* this sets the correct val for ret */
for (i = 0; i < length; i++)
{
mrf24j40_setreg(dev->spi, fifo_addr++, frame->io_data[ret]);
mrf24j40_setreg(dev->spi, fifo_addr++, buf[i]);
}
return ret;
}
/****************************************************************************
@@ -1723,7 +1887,8 @@ done:
static void mrf24j40_irqworker(FAR void *arg)
{
FAR struct mrf24j40_radio_s *dev = (FAR struct mrf24j40_radio_s *)arg;
uint8_t intstat, intcon;
uint8_t intstat;
uint8_t reg;
DEBUGASSERT(dev);
DEBUGASSERT(dev->spi);
@@ -1749,9 +1914,9 @@ static void mrf24j40_irqworker(FAR void *arg)
/* Timers are one-shot, so disable the interrupt */
intcon = mrf24j40_getreg(dev->spi, MRF24J40_INTCON);
intcon |= MRF24J40_INTCON_HSYMTMRIE;
mrf24j40_setreg(dev->spi, MRF24J40_INTCON, intcon);
reg = mrf24j40_getreg(dev->spi, MRF24J40_INTCON);
reg |= MRF24J40_INTCON_HSYMTMRIE;
mrf24j40_setreg(dev->spi, MRF24J40_INTCON, reg);
}
if ((intstat & MRF24J40_INTSTAT_RXIF))
@@ -1782,6 +1947,17 @@ static void mrf24j40_irqworker(FAR void *arg)
mrf24j40_irqwork_txgts(dev, 1);
}
if ((intstat & MRF24J40_INTSTAT_SLPIF))
{
dev->radiocb->sfevent(dev->radiocb, IEEE802154_SFEVENT_ENDOFACTIVE);
/* Acknowledge the alert and put the device to sleep */
reg = mrf24j40_getreg(dev->spi, MRF24J40_SLPACK);
reg |= MRF24J40_SLPACK_SLPACK;
mrf24j40_setreg(dev->spi, MRF24J40_SLPACK, reg);
}
/* Unlock the radio device */
sem_post(&dev->exclsem);
@@ -1878,6 +2054,9 @@ FAR struct ieee802154_radio_s *mrf24j40_init(FAR struct spi_dev_s *spi,
dev->radio.set_attr = mrf24j40_set_attr;
dev->radio.rxenable = mrf24j40_rxenable;
dev->radio.req_rxenable = mrf24j40_req_rxenable;
dev->radio.beaconstart = mrf24j40_beaconstart;
dev->radio.beaconupdate = mrf24j40_beaconupdate;
dev->radio.beaconstop = mrf24j40_beaconstop;
dev->lower = lower;
dev->spi = spi;
drivers/wireless/ieee802154/mrf24j40.h
+39
View File
@@ -226,4 +226,43 @@
#define MRF24J40_TXSTAT_X_SHIFT 6
#define MRF24J40_TXSTAT_X_MASK (3 << MRF24J40_TXSTAT_X_SHIFT)
/* TXBCON1 bits */
#define MRF24J40_TXBCON1_RSSINUM 0x30
#define MRF24J40_TXBCON1_NWU_BCN 0x40
#define MRF24J40_TXBCON1_TXBMSK 0x80
/* WAKECON bits */
#define MRF24J40_WAKECON_INTL 0x3F
#define MRF24J40_WAKECON_REGWAKE 0x40
#define MRF24J40_WAKECON_IMMWAKE 0x80
/* WAKECON bits */
#define MRF24J40_WAKECON_INTL 0x3F
#define MRF24J40_WAKECON_REGWAKE 0x40
#define MRF24J40_WAKECON_IMMWAKE 0x80
/* ESLOTG1 bits */
#define MRF24J40_ESLOTG1_CAP 0x0F
#define MRF24J40_ESLOTG1_GTS1 0xF0
/* SLPCAL2 bits */
#define MRF24J40_SLPCAL2_SLPCAL 0x0F
#define MRF24J40_SLPCAL2_SLPCALEN 0x10
#define MRF24J40_SLPCAL2_SLPCALRDY 0x80
/* RFCON7 bits */
#define MRF24J40_RFCON7_SEL_32KHZ 0x40
#define MRF24J40_RFCON7_SEL_100KHZ 0x80
/* SLPACK bits */
#define MRF24J40_SLPACK_WAKECNT0_6 0x7F
#define MRF24J40_SLPACK_SLPACK 0x80
#endif /* __DRIVERS_WIRELESS_IEEE802154_MRF24J40_H */