From 33f7bfa351c4edc9e2420afd5d503bb90046d90a Mon Sep 17 00:00:00 2001 From: David Date: Tue, 14 Mar 2017 21:01:44 +0800 Subject: [PATCH 01/81] ARM: Fix off-by-one interrupt stack allocation (revert missed change in up_initialize.c) --- arch/arm/src/common/up_initialize.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/src/common/up_initialize.c b/arch/arm/src/common/up_initialize.c index ff11e45170d..5182598246a 100644 --- a/arch/arm/src/common/up_initialize.c +++ b/arch/arm/src/common/up_initialize.c @@ -100,7 +100,7 @@ static void up_calibratedelay(void) * ****************************************************************************/ -#if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 7 +#if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 3 static inline void up_color_intstack(void) { uint32_t *ptr = (uint32_t *)&g_intstackalloc; From dc4ac48aad19b791247eef851c3d648cb19a5ada Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 14 Mar 2017 11:56:29 -0600 Subject: [PATCH 02/81] arch/arm/src/xmc4: Initial, partial support for Infineon XMC4xxx --- arch/arm/Kconfig | 16 + arch/arm/src/xmc4/Kconfig | 328 +++++++ arch/arm/src/xmc4/Make.defs | 141 +++ arch/arm/src/xmc4/chip.h | 77 ++ arch/arm/src/xmc4/xmc4_allocateheap.c | 193 +++++ arch/arm/src/xmc4/xmc4_clockconfig.c | 74 ++ arch/arm/src/xmc4/xmc4_clrpend.c | 102 +++ arch/arm/src/xmc4/xmc4_config.h | 198 +++++ arch/arm/src/xmc4/xmc4_dma.c | 0 arch/arm/src/xmc4/xmc4_dma.h | 218 +++++ arch/arm/src/xmc4/xmc4_gpio.c | 0 arch/arm/src/xmc4/xmc4_gpio.h | 0 arch/arm/src/xmc4/xmc4_i2c.c | 0 arch/arm/src/xmc4/xmc4_i2c.h | 87 ++ arch/arm/src/xmc4/xmc4_idle.c | 105 +++ arch/arm/src/xmc4/xmc4_irq.c | 588 +++++++++++++ arch/arm/src/xmc4/xmc4_lowputc.c | 235 +++++ arch/arm/src/xmc4/xmc4_mpuinit.c | 124 +++ arch/arm/src/xmc4/xmc4_mpuinit.h | 78 ++ arch/arm/src/xmc4/xmc4_pwm.c | 0 arch/arm/src/xmc4/xmc4_pwm.h | 100 +++ arch/arm/src/xmc4/xmc4_serial.c | 1146 +++++++++++++++++++++++++ arch/arm/src/xmc4/xmc4_spi.h | 165 ++++ arch/arm/src/xmc4/xmc4_start.c | 355 ++++++++ arch/arm/src/xmc4/xmc4_timerisr.c | 152 ++++ arch/arm/src/xmc4/xmc4_userspace.c | 107 +++ arch/arm/src/xmc4/xmc4_userspace.h | 64 ++ 27 files changed, 4653 insertions(+) create mode 100644 arch/arm/src/xmc4/Kconfig create mode 100644 arch/arm/src/xmc4/Make.defs create mode 100644 arch/arm/src/xmc4/chip.h create mode 100644 arch/arm/src/xmc4/xmc4_allocateheap.c create mode 100644 arch/arm/src/xmc4/xmc4_clockconfig.c create mode 100644 arch/arm/src/xmc4/xmc4_clrpend.c create mode 100644 arch/arm/src/xmc4/xmc4_config.h create mode 100644 arch/arm/src/xmc4/xmc4_dma.c create mode 100644 arch/arm/src/xmc4/xmc4_dma.h create mode 100644 arch/arm/src/xmc4/xmc4_gpio.c create mode 100644 arch/arm/src/xmc4/xmc4_gpio.h create mode 100644 arch/arm/src/xmc4/xmc4_i2c.c create mode 100644 arch/arm/src/xmc4/xmc4_i2c.h create mode 100644 arch/arm/src/xmc4/xmc4_idle.c create mode 100644 arch/arm/src/xmc4/xmc4_irq.c create mode 100644 arch/arm/src/xmc4/xmc4_lowputc.c create mode 100644 arch/arm/src/xmc4/xmc4_mpuinit.c create mode 100644 arch/arm/src/xmc4/xmc4_mpuinit.h create mode 100644 arch/arm/src/xmc4/xmc4_pwm.c create mode 100644 arch/arm/src/xmc4/xmc4_pwm.h create mode 100644 arch/arm/src/xmc4/xmc4_serial.c create mode 100644 arch/arm/src/xmc4/xmc4_spi.h create mode 100644 arch/arm/src/xmc4/xmc4_start.c create mode 100644 arch/arm/src/xmc4/xmc4_timerisr.c create mode 100644 arch/arm/src/xmc4/xmc4_userspace.c create mode 100644 arch/arm/src/xmc4/xmc4_userspace.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index fd44dcff077..21334e71178 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -270,6 +270,19 @@ config ARCH_CHIP_TMS570 ---help--- TI TMS570 family +config ARCH_CHIP_XMC4 + bool "Infineon XMC4xxx" + select ARCH_HAVE_CMNVECTOR + select ARCH_CORTEXM4 + select ARCH_HAVE_MPU + select ARCH_HAVE_RAMFUNCS + select ARCH_HAVE_I2CRESET + select ARM_HAVE_MPU_UNIFIED + select ARMV7M_CMNVECTOR + select ARMV7M_HAVE_STACKCHECK + ---help--- + Infineon XMC4xxx(ARM Cortex-M4) architectures + config ARCH_CHIP_MOXART bool "MoxART" select ARCH_ARM7TDMI @@ -692,6 +705,9 @@ endif if ARCH_CHIP_TMS570 source arch/arm/src/tms570/Kconfig endif +if ARCH_CHIP_XMC4 +source arch/arm/src/xmc4/Kconfig +endif if ARCH_CHIP_MOXART source arch/arm/src/moxart/Kconfig endif diff --git a/arch/arm/src/xmc4/Kconfig b/arch/arm/src/xmc4/Kconfig new file mode 100644 index 00000000000..116d56d14f2 --- /dev/null +++ b/arch/arm/src/xmc4/Kconfig @@ -0,0 +1,328 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +comment "XMC4xxx Configuration Options" + +choice + prompt "XMC4xxx Chip Selection" + default ARCH_CHIP_XMC4500 + depends on ARCH_CHIP_XMC4 + +config ARCH_CHIP_XMC4500 + bool "XMC4500" + +endchoice + +# These "hidden" settings determine is a peripheral option is available for +# the selection MCU + + +# When there are multiple instances of a device, these "hidden" settings +# will automatically be selected and will represent the 'OR' of the +# instances selected. + +config XMC4_USIC + bool + default n + +config XMC4_USCI_UART + bool + default n + select MCU_SERIAL + +config XMC4_USCI_LIN + bool + default n + +config XMC4_USCI_SPI + bool + default n + +config XMC4_USCI_I2C + bool + default n + +config XMC4_USCI_I2S + bool + default n + +# Chip families + +menu "ARCH_CHIP_XMC4 Peripheral Support" + +config XMC4_USIC0 + bool "USIC0" + default n + select XMC4_USIC + ---help--- + Support USIC0 + +config XMC4_USIC1 + bool "USIC1" + default n + ---help--- + Support USIC1 + +config XMC4_USIC2 + bool "USIC3" + default n + select XMC4_USIC + ---help--- + Support USIC2 + +config XMC4_USIC3 + bool "USIC3" + default n + select XMC4_USIC + ---help--- + Support USIC3 + +config XMC4_USIC4 + bool "USIC4" + default n + select XMC4_USIC + ---help--- + Support USIC4 + +config XMC4_USIC5 + bool "USIC5" + default n + select XMC4_USIC + ---help--- + Support USIC5 + +endmenu + +menu "XMC4xxx USIC Configuration" + depends on XMC4_USIC + +choice + prompt "USIC0 Configuration" + default XMC4_USIC0_ISUART + depends on XMC4_USIC0 + +config XMC4_USIC0_ISUART + bool "UART" + select UART0_SERIALDRIVER + select XMC4_USCI_UART + ---help--- + Configure USIC0 as a UART + +config XMC4_USIC0_ISLIN + bool "LIN" + select XMC4_USCI_LIN + ---help--- + Configure USIC0 as a LIN UART + +config XMC4_USIC0_ISSPI + bool "SPI" + select XMC4_USCI_SPI + ---help--- + Configure USIC0 For SPI communications + +config XMC4_USIC0_ISI2C + bool "I2C" + select XMC4_USCI_I2C + ---help--- + Configure USIC0 For I2C communications + +config XMC4_USIC0_ISI2S + bool "I2S" + select XMC4_USCI_I2S + ---help--- + Configure USIC0 For I2S audio + +endchoice # USIC0 Configuration + +choice + prompt "USIC1 Configuration" + default XMC4_USIC1_ISUART + depends on XMC4_USIC1 + +config XMC4_USIC1_ISUART + bool "UART" + select UART1_SERIALDRIVER + select XMC4_USCI_UART + ---help--- + Configure USIC1 as a UART + +config XMC4_USIC1_ISLIN + bool "LIN" + select XMC4_USCI_LIN + ---help--- + Configure USIC1 as a LIN UART + +config XMC4_USIC1_ISSPI + bool "SPI" + select XMC4_USCI_SPI + ---help--- + Configure USIC1 For SPI communications + +config XMC4_USIC1_ISI2C + bool "I2C" + select XMC4_USCI_I2C + ---help--- + Configure USIC1 For I2C communications + +config XMC4_USIC1_ISI2S + bool "I2S" + select XMC4_USCI_I2S + ---help--- + Configure USIC1 For I2S audio + +endchoice # USIC1 Configuration + +choice + prompt "USIC2 Configuration" + default XMC4_USIC2_ISUART + depends on XMC4_USIC2 + +config XMC4_USIC2_ISUART + bool "UART" + select UART2_SERIALDRIVER + select XMC4_USCI_UART + ---help--- + Configure USIC2 as a UART + +config XMC4_USIC2_ISLIN + bool "LIN" + select XMC4_USCI_LIN + ---help--- + Configure USIC2 as a LIN UART + +config XMC4_USIC2_ISSPI + bool "SPI" + select XMC4_USCI_SPI + ---help--- + Configure USIC2 For SPI communications + +config XMC4_USIC2_ISI2C + bool "I2C" + select XMC4_USCI_I2C + ---help--- + Configure USIC2 For I2C communications + +config XMC4_USIC2_ISI2S + bool "I2S" + select XMC4_USCI_I2S + ---help--- + Configure USIC2 For I2S audio + +endchoice # USIC2 Configuration + +choice + prompt "USIC3 Configuration" + default XMC4_USIC3_ISUART + depends on XMC4_USIC3 + +config XMC4_USIC3_ISUART + bool "UART" + select UART3_SERIALDRIVER + select XMC4_USCI_UART + ---help--- + Configure USIC3 as a UART + +config XMC4_USIC3_ISLIN + bool "LIN" + select XMC4_USCI_LIN + ---help--- + Configure USIC3 as a LIN UART + +config XMC4_USIC3_ISSPI + bool "SPI" + select XMC4_USCI_SPI + ---help--- + Configure USIC3 For SPI communications + +config XMC4_USIC3_ISI2C + bool "I2C" + select XMC4_USCI_I2C + ---help--- + Configure USIC3 For I2C communications + +config XMC4_USIC3_ISI2S + bool "I2S" + select XMC4_USCI_I2S + ---help--- + Configure USIC3 For I2S audio + +endchoice # USIC3 Configuration + +choice + prompt "USIC4 Configuration" + default XMC4_USIC4_ISUART + depends on XMC4_USIC4 + +config XMC4_USIC4_ISUART + bool "UART" + select UART4_SERIALDRIVER + select XMC4_USCI_UART + ---help--- + Configure USIC4 as a UART + +config XMC4_USIC4_ISLIN + bool "LIN" + select XMC4_USCI_LIN + ---help--- + Configure USIC4 as a LIN UART + +config XMC4_USIC4_ISSPI + bool "SPI" + select XMC4_USCI_SPI + ---help--- + Configure USIC4 For SPI communications + +config XMC4_USIC4_ISI2C + bool "I2C" + select XMC4_USCI_I2C + ---help--- + Configure USIC4 For I2C communications + +config XMC4_USIC4_ISI2S + bool "I2S" + select XMC4_USCI_I2S + ---help--- + Configure USIC4 For I2S audio + +endchoice # USIC4 Configuration + +choice + prompt "USIC5 Configuration" + default XMC4_USIC5_ISUART + depends on XMC4_USIC5 + +config XMC4_USIC5_ISUART + bool "UART" + select UART0_SERIALDRIVER + select XMC4_USCI_UART + ---help--- + Configure USIC5 as a UART + +config XMC4_USIC5_ISLIN + bool "LIN" + select XMC4_USCI_LIN + ---help--- + Configure USIC5 as a LIN UART + +config XMC4_USIC5_ISSPI + bool "SPI" + select XMC4_USCI_SPI + ---help--- + Configure USIC5 For SPI communications + +config XMC4_USIC5_ISI2C + bool "I2C" + select XMC4_USCI_I2C + ---help--- + Configure USIC5 For I2C communications + +config XMC4_USIC5_ISI2S + bool "I2S" + select XMC4_USCI_I2S + ---help--- + Configure USIC5 For I2S audio + +endchoice # USIC5 Configuration +endmenu # XMC4xxx USIC Configuration diff --git a/arch/arm/src/xmc4/Make.defs b/arch/arm/src/xmc4/Make.defs new file mode 100644 index 00000000000..79497388a49 --- /dev/null +++ b/arch/arm/src/xmc4/Make.defs @@ -0,0 +1,141 @@ +############################################################################ +# arch/arm/src/kinetis/Make.defs +# +# Copyright (C) 2017 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +ifeq ($(CONFIG_ARMV7M_CMNVECTOR),y) +HEAD_ASRC = +else +HEAD_ASRC = xmc4_vectors.S +endif + +CMN_UASRCS = +CMN_UCSRCS = + +CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S +CMN_ASRCS += up_testset.S vfork.S + +CMN_CSRCS = up_assert.c up_blocktask.c up_copyfullstate.c up_createstack.c +CMN_CSRCS += up_mdelay.c up_udelay.c up_exit.c up_initialize.c up_memfault.c +CMN_CSRCS += up_initialstate.c up_interruptcontext.c up_modifyreg8.c +CMN_CSRCS += up_modifyreg16.c up_modifyreg32.c up_releasestack.c +CMN_CSRCS += up_reprioritizertr.c up_schedulesigaction.c up_releasepending.c +CMN_CSRCS += up_sigdeliver.c up_stackframe.c up_unblocktask.c up_usestack.c +CMN_CSRCS += up_doirq.c up_hardfault.c up_svcall.c up_vfork.c +CMN_CSRCS += up_systemreset.c + +ifeq ($(CONFIG_ARMV7M_STACKCHECK),y) +CMN_CSRCS += up_stackcheck.c +endif + +ifeq ($(CONFIG_ARMV7M_CMNVECTOR),y) +ifeq ($(CONFIG_ARMV7M_LAZYFPU),y) +CMN_ASRCS += up_lazyexception.S +else +CMN_ASRCS += up_exception.S +endif +CMN_CSRCS += up_vectors.c +endif + +ifeq ($(CONFIG_ARCH_RAMVECTORS),y) +CMN_CSRCS += up_ramvec_initialize.c up_ramvec_attach.c +endif + +ifeq ($(CONFIG_BUILD_PROTECTED),y) +CMN_CSRCS += up_mpu.c up_task_start.c up_pthread_start.c +ifneq ($(CONFIG_DISABLE_SIGNALS),y) +CMN_CSRCS += up_signal_dispatch.c +CMN_UASRCS += up_signal_handler.S +endif +endif + +ifeq ($(CONFIG_STACK_COLORATION),y) +CMN_CSRCS += up_checkstack.c +endif + +# Use of common/up_etherstub.c is deprecated. The preferred mechanism is to +# use CONFIG_NETDEV_LATEINIT=y to suppress the call to up_netinitialize() in +# up_initialize(). Then this stub would not be needed. + +ifeq ($(CONFIG_NET),y) +ifneq ($(CONFIG_XMC4_ENET),y) +CMN_CSRCS += up_etherstub.c +endif +endif + +ifeq ($(CONFIG_ARCH_FPU),y) +CMN_ASRCS += up_fpu.S +ifneq ($(CONFIG_ARMV7M_CMNVECTOR),y) +CMN_CSRCS += up_copyarmstate.c +else ifeq ($(CONFIG_ARMV7M_LAZYFPU),y) +CMN_CSRCS += up_copyarmstate.c +endif +endif + +ifeq ($(CONFIG_ARMV7M_ITMSYSLOG),y) +CMN_CSRCS += up_itm_syslog.c +endif + +# Required XMC4xxx files + +CHIP_ASRCS = + +CHIP_CSRCS = xmc4_allocateheap.c xmc4_clockconfig.c xmc4_clrpend.c +CHIP_CSRCS += xmc4_idle.c xmc4_irq.c xmc4_lowputc.c xmc4_gpio.c +CHIP_CSRCS += xmc4_serialinit.c xmc4_serial.c xmc4_start.c xmc4_uid.c + +# Configuration-dependent Kinetis files + +ifneq ($(CONFIG_SCHED_TICKLESS),y) +CHIP_CSRCS += xmc4_timerisr.c +endif + +ifeq ($(CONFIG_BUILD_PROTECTED),y) +CHIP_CSRCS += xmc4_userspace.c xmc4_mpuinit.c +endif + +ifeq ($(CONFIG_DEBUG_GPIO_INFO),y) +CHIP_CSRCS += xmc4_pindump.c +endif + +ifeq ($(CONFIG_XMC4_DMA),y) +CHIP_CSRCS += xmc4_dma.c +endif + +ifeq ($(CONFIG_PWM),y) +CHIP_CSRCS += xmc4_pwm.c +endif + +ifeq ($(CONFIG_I2C),y) +CHIP_CSRCS += xmc4_i2c.c +endif diff --git a/arch/arm/src/xmc4/chip.h b/arch/arm/src/xmc4/chip.h new file mode 100644 index 00000000000..ef746cfcc93 --- /dev/null +++ b/arch/arm/src/xmc4/chip.h @@ -0,0 +1,77 @@ +/************************************************************************************ + * arch/arm/src/xmc4/chip.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_XMC4_CHIP_H +#define __ARCH_ARM_SRC_XMC4_CHIP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/* Include the memory map and the chip definitions file. Other chip hardware files + * should then include this file for the proper setup. + */ + +#include +#include +#include "chip/xmc4_memorymap.h" + +/* If the common ARMv7-M vector handling logic is used, then it expects the + * following definition in this file that provides the number of supported external + * interrupts which, for this architecture, is provided in the arch/xmc4/chip.h + * header file. + */ + +#define ARMV7M_PERIPHERAL_INTERRUPTS NR_INTERRUPTS + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_XMC4_CHIP_H */ diff --git a/arch/arm/src/xmc4/xmc4_allocateheap.c b/arch/arm/src/xmc4/xmc4_allocateheap.c new file mode 100644 index 00000000000..cdbc8ef2d18 --- /dev/null +++ b/arch/arm/src/xmc4/xmc4_allocateheap.c @@ -0,0 +1,193 @@ +/**************************************************************************** + * arch/arm/src/xmc4/xmc4_allocateheap.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include + +#include + +#include "mpu.h" +#include "up_arch.h" +#include "up_internal.h" +#include "xmc4_mpuinit.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_allocate_heap + * + * Description: + * This function will be called to dynamically set aside the heap region. + * + * For the kernel build (CONFIG_BUILD_PROTECTED=y) with both kernel- and + * user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function provides the + * size of the unprotected, user-space heap. + * + * If a protected kernel-space heap is provided, the kernel heap must be + * allocated (and protected) by an analogous up_allocate_kheap(). + * + * The following memory map is assumed for the flat build: + * + * .data region. Size determined at link time. + * .bss region Size determined at link time. + * IDLE thread stack. Size determined by CONFIG_IDLETHREAD_STACKSIZE. + * Heap. Extends to the end of SRAM. + * + * The following memory map is assumed for the kernel build: + * + * Kernel .data region. Size determined at link time. + * Kernel .bss region Size determined at link time. + * Kernel IDLE thread stack. Size determined by CONFIG_IDLETHREAD_STACKSIZE. + * Padding for alignment + * User .data region. Size determined at link time. + * User .bss region Size determined at link time. + * Kernel heap. Size determined by CONFIG_MM_KERNEL_HEAPSIZE. + * User heap. Extends to the end of SRAM. + * + ****************************************************************************/ + +void up_allocate_heap(FAR void **heap_start, size_t *heap_size) +{ +#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) + /* Get the unaligned size and position of the user-space heap. + * This heap begins after the user-space .bss section at an offset + * of CONFIG_MM_KERNEL_HEAPSIZE (subject to alignment). + */ + + uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + CONFIG_MM_KERNEL_HEAPSIZE; + size_t usize = CONFIG_RAM_END - ubase; + int log2; + + DEBUGASSERT(ubase < (uintptr_t)CONFIG_RAM_END); + + /* Adjust that size to account for MPU alignment requirements. + * NOTE that there is an implicit assumption that the CONFIG_RAM_END + * is aligned to the MPU requirement. + */ + + log2 = (int)mpu_log2regionfloor(usize); + DEBUGASSERT((CONFIG_RAM_END & ((1 << log2) - 1)) == 0); + + usize = (1 << log2); + ubase = CONFIG_RAM_END - usize; + + /* Return the user-space heap settings */ + + board_autoled_on(LED_HEAPALLOCATE); + *heap_start = (FAR void *)ubase; + *heap_size = usize; + + /* Allow user-mode access to the user heap memory */ + + xmc4_mpu_uheap((uintptr_t)ubase, usize); +#else + + /* Return the heap settings */ + + board_autoled_on(LED_HEAPALLOCATE); + *heap_start = (FAR void *)g_idle_topstack; + *heap_size = CONFIG_RAM_END - g_idle_topstack; +#endif +} + +/**************************************************************************** + * Name: up_allocate_kheap + * + * Description: + * For the kernel build (CONFIG_BUILD_PROTECTED=y) with both kernel- and + * user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function allocates + * (and protects) the kernel-space heap. + * + ****************************************************************************/ + +#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) +void up_allocate_kheap(FAR void **heap_start, size_t *heap_size) +{ + /* Get the unaligned size and position of the user-space heap. + * This heap begins after the user-space .bss section at an offset + * of CONFIG_MM_KERNEL_HEAPSIZE (subject to alignment). + */ + + uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + CONFIG_MM_KERNEL_HEAPSIZE; + size_t usize = CONFIG_RAM_END - ubase; + int log2; + + DEBUGASSERT(ubase < (uintptr_t)CONFIG_RAM_END); + + /* Adjust that size to account for MPU alignment requirements. + * NOTE that there is an implicit assumption that the CONFIG_RAM_END + * is aligned to the MPU requirement. + */ + + log2 = (int)mpu_log2regionfloor(usize); + DEBUGASSERT((CONFIG_RAM_END & ((1 << log2) - 1)) == 0); + + usize = (1 << log2); + ubase = CONFIG_RAM_END - usize; + + /* Return the kernel heap settings (i.e., the part of the heap region + * that was not dedicated to the user heap). + */ + + *heap_start = (FAR void *)USERSPACE->us_bssend; + *heap_size = ubase - (uintptr_t)USERSPACE->us_bssend; +} +#endif diff --git a/arch/arm/src/xmc4/xmc4_clockconfig.c b/arch/arm/src/xmc4/xmc4_clockconfig.c new file mode 100644 index 00000000000..67efe53651d --- /dev/null +++ b/arch/arm/src/xmc4/xmc4_clockconfig.c @@ -0,0 +1,74 @@ +/**************************************************************************** + * arch/arm/src/xmc4/xmc4_clock_config.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "up_arch.h" + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: xmc4_clock_config + * + * Description: + * Called to initialize the XMC4xxx chip. This does whatever setup is + * needed to put the MCU in a usable state. This includes the + * initialization of clocking using the settings in board.h. + * + ****************************************************************************/ + +void xmc4_clock_config(void) +{ +} diff --git a/arch/arm/src/xmc4/xmc4_clrpend.c b/arch/arm/src/xmc4/xmc4_clrpend.c new file mode 100644 index 00000000000..2eab7d6ffa2 --- /dev/null +++ b/arch/arm/src/xmc4/xmc4_clrpend.c @@ -0,0 +1,102 @@ +/**************************************************************************** + * arch/arm/src/xmc4/xmc4_clrpend.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "nvic.h" +#include "up_arch.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: xmc4_clrpend + * + * Description: + * Clear a pending interrupt at the NVIC. This does not seem to be required + * for most interrupts. Don't know why... + * + * I keep it in a separate file so that it will not increase the footprint + * on Kinetis platforms that do not need this function. + * + ****************************************************************************/ + +void xmc4_clrpend(int irq) +{ + /* Check for external interrupt */ + + if (irq >= XMC4_IRQ_FIRST) + { + if (irq < (XMC4_IRQ_FIRST+32)) + { + putreg32(1 << (irq - XMC4_IRQ_FIRST), NVIC_IRQ0_31_CLRPEND); + } + else if (irq < (XMC4_IRQ_FIRST+64)) + { + putreg32(1 << (irq - XMC4_IRQ_FIRST - 32), NVIC_IRQ32_63_CLRPEND); + } + else if (irq < (XMC4_IRQ_FIRST+96)) + { + putreg32(1 << (irq - XMC4_IRQ_FIRST - 64), NVIC_IRQ64_95_CLRPEND); + } + else if (irq < NR_IRQS) + { + putreg32(1 << (irq - XMC4_IRQ_FIRST - 96), NVIC_IRQ96_127_CLRPEND); + } + } +} diff --git a/arch/arm/src/xmc4/xmc4_config.h b/arch/arm/src/xmc4/xmc4_config.h new file mode 100644 index 00000000000..e81932569ec --- /dev/null +++ b/arch/arm/src/xmc4/xmc4_config.h @@ -0,0 +1,198 @@ +/************************************************************************************ + * arch/arm/src/xmc4/xmc4_config.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_XMC4_XMC4_CONFIG_H +#define __ARCH_ARM_SRC_XMC4_XMC4_CONFIG_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include + +#include "chip.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Configuration *********************************************************************/ +/* Make sure that no unsupported UARTs are enabled */ + +#ifndef CONFIG_XMC4_USIC0 +# undef CONFIG_XMC4_USIC0_ISUART +#endif +#ifndef CONFIG_XMC4_USIC1 +# undef CONFIG_XMC4_USIC1_ISUART +#endif +#ifndef CONFIG_XMC4_USIC2 +# undef CONFIG_XMC4_USIC2_ISUART +#endif +#ifndef CONFIG_XMC4_USIC3 +# undef CONFIG_XMC4_USIC3_ISUART +#endif +#ifndef CONFIG_XMC4_USIC4 +# undef CONFIG_XMC4_USIC4_ISUART +#endif +#ifndef CONFIG_XMC4_USIC5 +# undef CONFIG_XMC4_USIC5_ISUART +#endif + +/* Are any UARTs enabled? */ + +#undef HAVE_UART_DEVICE +#if defined(CONFIG_XMC4_USIC0_ISUART) || defined(CONFIG_XMC4_USIC1_ISUART) || \ + defined(CONFIG_XMC4_USIC2_ISUART) || defined(CONFIG_XMC4_USIC3_ISUART) || \ + defined(CONFIG_XMC4_USIC3_ISUART) || defined(CONFIG_XMC4_USIC4_ISUART) +# define HAVE_UART_DEVICE 1 +#endif + +/* Is there a serial console? There should be at most one defined. It could be on + * any UARTn, n=0,1,2,3,4,5 + */ + +#undef HAVE_UART_CONSOLE + +#if defined(CONFIG_CONSOLE_SYSLOG) +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# undef CONFIG_UART5_SERIAL_CONSOLE +#else +# if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_XMC4_USIC0_ISUART) +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# undef CONFIG_UART5_SERIAL_CONSOLE +# define HAVE_UART_CONSOLE 1 +# elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_XMC4_USIC1_ISUART) +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# undef CONFIG_UART5_SERIAL_CONSOLE +# define HAVE_UART_CONSOLE 1 +# elif defined(CONFIG_UART2_SERIAL_CONSOLE) && defined(CONFIG_XMC4_USIC2_ISUART) +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# undef CONFIG_UART5_SERIAL_CONSOLE +# define HAVE_UART_CONSOLE 1 +# elif defined(CONFIG_UART3_SERIAL_CONSOLE) && defined(CONFIG_XMC4_USIC3_ISUART) +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# undef CONFIG_UART5_SERIAL_CONSOLE +# define HAVE_UART_CONSOLE 1 +# elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_XMC4_USIC4_ISUART) +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef CONFIG_UART5_SERIAL_CONSOLE +# define HAVE_UART_CONSOLE 1 +# elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_XMC4_USIC5_ISUART) +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# define HAVE_UART_CONSOLE 1 +# else +# ifdef CONFIG_DEV_CONSOLE +# warning "No valid CONFIG_[LP]UART[n]_SERIAL_CONSOLE Setting" +# endif +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# undef CONFIG_UART5_SERIAL_CONSOLE +# endif +#endif + +/* Check UART flow control (Not yet supported) */ + +# undef CONFIG_UART0_FLOWCONTROL +# undef CONFIG_UART1_FLOWCONTROL +# undef CONFIG_UART2_FLOWCONTROL +# undef CONFIG_UART3_FLOWCONTROL +# undef CONFIG_UART4_FLOWCONTROL +# undef CONFIG_UART5_FLOWCONTROL + +/* UART Default Interrupt Priorities */ + +#ifndef CONFIG_XMC4_UART0PRIO +# define CONFIG_XMC4_UART0PRIO NVIC_SYSH_PRIORITY_DEFAULT +#endif +#ifndef CONFIG_XMC4_UART1PRIO +# define CONFIG_XMC4_UART1PRIO NVIC_SYSH_PRIORITY_DEFAULT +#endif +#ifndef CONFIG_XMC4_UART2PRIO +# define CONFIG_XMC4_UART2PRIO NVIC_SYSH_PRIORITY_DEFAULT +#endif +#ifndef CONFIG_XMC4_UART3PRIO +# define CONFIG_XMC4_UART3PRIO NVIC_SYSH_PRIORITY_DEFAULT +#endif +#ifndef CONFIG_XMC4_UART4PRIO +# define CONFIG_XMC4_UART4PRIO NVIC_SYSH_PRIORITY_DEFAULT +#endif +#ifndef CONFIG_XMC4_UART5PRIO +# define CONFIG_XMC4_UART5PRIO NVIC_SYSH_PRIORITY_DEFAULT +#endif + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Inline Functions + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_XMC4_XMC4_CONFIG_H */ diff --git a/arch/arm/src/xmc4/xmc4_dma.c b/arch/arm/src/xmc4/xmc4_dma.c new file mode 100644 index 00000000000..e69de29bb2d diff --git a/arch/arm/src/xmc4/xmc4_dma.h b/arch/arm/src/xmc4/xmc4_dma.h new file mode 100644 index 00000000000..8f2edba4326 --- /dev/null +++ b/arch/arm/src/xmc4/xmc4_dma.h @@ -0,0 +1,218 @@ +/**************************************************************************** + * arch/arm/src/xmc4/xmc4_dma.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_XMC4_XMC4_DMA_H +#define __ARCH_ARM_SRC_XMC4_XMC4_DMA_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include "chip/xmc4_dma.h" + +/**************************************************************************** + * Pre-processor Declarations + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +typedef FAR void *DMA_HANDLE; +typedef void (*dma_callback_t)(DMA_HANDLE handle, void *arg, int result); + +/* The following is used for sampling DMA registers when CONFIG DEBUG_DMA is selected */ + +#ifdef CONFIG_DEBUG_DMA +struct xmc4_dmaglobalregs_s +{ +#warning "Missing logic" + /* Global Registers */ +}; + +struct xmc4_dmachanregs_s +{ +#warning "Missing logic" + /* Channel Registers */ +}; + +struct xmc4_dmaregs_s +{ + /* Global Registers */ + + struct xmc4_dmaglobalregs_s gbl; + + /* Channel Registers */ + + struct xmc4_dmachanregs_s ch; +}; +#endif + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/**************************************************************************** + * Name: xmc4_dmainitialize + * + * Description: + * Initialize the GPDMA subsystem. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void xmc4_dmainitilaize(void); + +/**************************************************************************** + * Name: xmc4_dmachannel + * + * Description: + * Allocate a DMA channel. This function sets aside a DMA channel and + * gives the caller exclusive access to the DMA channel. + * + * Returned Value: + * One success, this function returns a non-NULL, void* DMA channel + * handle. NULL is returned on any failure. This function can fail only + * if no DMA channel is available. + * + ****************************************************************************/ + +DMA_HANDLE xmc4_dmachannel(void); + +/**************************************************************************** + * Name: xmc4_dmafree + * + * Description: + * Release a DMA channel. NOTE: The 'handle' used in this argument must + * NEVER be used again until xmc4_dmachannel() is called again to re-gain + * a valid handle. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void xmc4_dmafree(DMA_HANDLE handle); + +/**************************************************************************** + * Name: xmc4_dmasetup + * + * Description: + * Configure DMA for one transfer. + * + ****************************************************************************/ + +int xmc4_dmarxsetup(DMA_HANDLE handle, uint32_t control, uint32_t config, + uint32_t srcaddr, uint32_t destaddr, size_t nbytes); + +/**************************************************************************** + * Name: xmc4_dmastart + * + * Description: + * Start the DMA transfer + * + ****************************************************************************/ + +int xmc4_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg); + +/**************************************************************************** + * Name: xmc4_dmastop + * + * Description: + * Cancel the DMA. After xmc4_dmastop() is called, the DMA channel is + * reset and xmc4_dmasetup() must be called before xmc4_dmastart() can be + * called again + * + ****************************************************************************/ + +void xmc4_dmastop(DMA_HANDLE handle); + +/**************************************************************************** + * Name: xmc4_dmasample + * + * Description: + * Sample DMA register contents + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_DMA +void xmc4_dmasample(DMA_HANDLE handle, struct xmc4_dmaregs_s *regs); +#else +# define xmc4_dmasample(handle,regs) +#endif + +/**************************************************************************** + * Name: xmc4_dmadump + * + * Description: + * Dump previously sampled DMA register contents + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_DMA +void xmc4_dmadump(DMA_HANDLE handle, const struct xmc4_dmaregs_s *regs, + const char *msg); +#else +# define xmc4_dmadump(handle,regs,msg) +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_XMC4_XMC4_DMA_H */ diff --git a/arch/arm/src/xmc4/xmc4_gpio.c b/arch/arm/src/xmc4/xmc4_gpio.c new file mode 100644 index 00000000000..e69de29bb2d diff --git a/arch/arm/src/xmc4/xmc4_gpio.h b/arch/arm/src/xmc4/xmc4_gpio.h new file mode 100644 index 00000000000..e69de29bb2d diff --git a/arch/arm/src/xmc4/xmc4_i2c.c b/arch/arm/src/xmc4/xmc4_i2c.c new file mode 100644 index 00000000000..e69de29bb2d diff --git a/arch/arm/src/xmc4/xmc4_i2c.h b/arch/arm/src/xmc4/xmc4_i2c.h new file mode 100644 index 00000000000..f4a167b713d --- /dev/null +++ b/arch/arm/src/xmc4/xmc4_i2c.h @@ -0,0 +1,87 @@ +/**************************************************************************** + * arch/arm/src/xmc4/xmc4_i2c.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_XMC4_XMC4_I2C_H +#define __ARCH_ARM_SRC_XMC4_XMC4_I2C_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include "chip/xmc4_i2c.h" + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: xmc4_i2cbus_initialize + * + * Description: + * Initialize the selected I2C port. And return a unique instance of struct + * struct i2c_master_s. This function may be called to obtain multiple + * instances of the interface, each of which may be set up with a + * different frequency and slave address. + * + * Input Parameter: + * Port number (for hardware that has multiple I2C interfaces) + * + * Returned Value: + * Valid I2C device structure reference on succcess; a NULL on failure + * + ****************************************************************************/ + +FAR struct i2c_master_s *xmc4_i2cbus_initialize(int port); + +/**************************************************************************** + * Name: xmc4_i2cbus_uninitialize + * + * Description: + * De-initialize the selected I2C port, and power down the device. + * + * Input Parameter: + * Device structure as returned by the lpc43_i2cbus_initialize() + * + * Returned Value: + * OK on success, ERROR when internal reference count mismatch or dev + * points to invalid hardware device. + * + ****************************************************************************/ + +int xmc4_i2cbus_uninitialize(FAR struct i2c_master_s *dev); + +#endif /* __ARCH_ARM_SRC_XMC4_XMC4_I2C_H */ diff --git a/arch/arm/src/xmc4/xmc4_idle.c b/arch/arm/src/xmc4/xmc4_idle.c new file mode 100644 index 00000000000..411324311f5 --- /dev/null +++ b/arch/arm/src/xmc4/xmc4_idle.c @@ -0,0 +1,105 @@ +/**************************************************************************** + * arch/arm/src/xmc4/xmc4_idle.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include +#include + +#include "up_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Does the board support an IDLE LED to indicate that the board is in the + * IDLE state? + */ + +#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE) +# define BEGIN_IDLE() board_autoled_on(LED_IDLE) +# define END_IDLE() board_autoled_off(LED_IDLE) +#else +# define BEGIN_IDLE() +# define END_IDLE() +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_idle + * + * Description: + * up_idle() is the logic that will be executed when their is no other + * ready-to-run task. This is processor idle time and will continue until + * some interrupt occurs to cause a context switch from the idle task. + * + * Processing in this state may be processor-specific. e.g., this is where + * power management operations might be performed. + * + ****************************************************************************/ + +void up_idle(void) +{ +#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS) + /* If the system is idle and there are no timer interrupts, then process + * "fake" timer interrupts. Hopefully, something will wake up. + */ + + sched_process_timer(); +#else + + /* Sleep until an interrupt occurs to save power */ + + BEGIN_IDLE(); + asm("WFI"); + END_IDLE(); +#endif +} diff --git a/arch/arm/src/xmc4/xmc4_irq.c b/arch/arm/src/xmc4/xmc4_irq.c new file mode 100644 index 00000000000..17725b8c608 --- /dev/null +++ b/arch/arm/src/xmc4/xmc4_irq.c @@ -0,0 +1,588 @@ +/**************************************************************************** + * arch/arm/src/xmc4/xmc4_irq.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "nvic.h" +#include "ram_vectors.h" +#include "up_arch.h" +#include "up_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Get a 32-bit version of the default priority */ + +#define DEFPRIORITY32 \ + (NVIC_SYSH_PRIORITY_DEFAULT << 24 | \ + NVIC_SYSH_PRIORITY_DEFAULT << 16 | \ + NVIC_SYSH_PRIORITY_DEFAULT << 8 | \ + NVIC_SYSH_PRIORITY_DEFAULT) + +/* Given the address of a NVIC ENABLE register, this is the offset to + * the corresponding CLEAR ENABLE register. + */ + +#define NVIC_ENA_OFFSET (0) +#define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE) + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* g_current_regs[] holds a references to the current interrupt level + * register storage structure. If is non-NULL only during interrupt + * processing. Access to g_current_regs[] must be through the macro + * CURRENT_REGS for portability. + */ + +volatile uint32_t *g_current_regs[1]; + +/* This is the address of the exception vector table (determined by the + * linker script). + */ + +extern uint32_t _vectors[]; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: xmc4_dump_nvic + * + * Description: + * Dump some interesting NVIC registers + * + ****************************************************************************/ + +#if defined(CONFIG_DEBUG_IRQ_INFO) +static void xmc4_dump_nvic(const char *msg, int irq) +{ + irqstate_t flags; + + flags = enter_critical_section(); + + irqinfo("NVIC (%s, irq=%d):\n", msg, irq); + irqinfo(" INTCTRL: %08x VECTAB: %08x\n", + getreg32(NVIC_INTCTRL), getreg32(NVIC_VECTAB)); +#if 0 + irqinfo(" SYSH ENABLE MEMFAULT: %08x BUSFAULT: %08x USGFAULT: %08x SYSTICK: %08x\n", + getreg32(NVIC_SYSHCON_MEMFAULTENA), getreg32(NVIC_SYSHCON_BUSFAULTENA), + getreg32(NVIC_SYSHCON_USGFAULTENA), getreg32(NVIC_SYSTICK_CTRL_ENABLE)); +#endif + irqinfo(" IRQ ENABLE: %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ0_31_ENABLE), getreg32(NVIC_IRQ32_63_ENABLE), + getreg32(NVIC_IRQ64_95_ENABLE), getreg32(NVIC_IRQ96_127_ENABLE)); + irqinfo(" SYSH_PRIO: %08x %08x %08x\n", + getreg32(NVIC_SYSH4_7_PRIORITY), getreg32(NVIC_SYSH8_11_PRIORITY), + getreg32(NVIC_SYSH12_15_PRIORITY)); + irqinfo(" IRQ PRIO: %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ0_3_PRIORITY), getreg32(NVIC_IRQ4_7_PRIORITY), + getreg32(NVIC_IRQ8_11_PRIORITY), getreg32(NVIC_IRQ12_15_PRIORITY)); + irqinfo(" %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ16_19_PRIORITY), getreg32(NVIC_IRQ20_23_PRIORITY), + getreg32(NVIC_IRQ24_27_PRIORITY), getreg32(NVIC_IRQ28_31_PRIORITY)); + irqinfo(" %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ32_35_PRIORITY), getreg32(NVIC_IRQ36_39_PRIORITY), + getreg32(NVIC_IRQ40_43_PRIORITY), getreg32(NVIC_IRQ44_47_PRIORITY)); + irqinfo(" %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ48_51_PRIORITY), getreg32(NVIC_IRQ52_55_PRIORITY), + getreg32(NVIC_IRQ56_59_PRIORITY), getreg32(NVIC_IRQ60_63_PRIORITY)); + irqinfo(" %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ64_67_PRIORITY), getreg32(NVIC_IRQ68_71_PRIORITY), + getreg32(NVIC_IRQ72_75_PRIORITY), getreg32(NVIC_IRQ76_79_PRIORITY)); + irqinfo(" %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ80_83_PRIORITY), getreg32(NVIC_IRQ84_87_PRIORITY), + getreg32(NVIC_IRQ88_91_PRIORITY), getreg32(NVIC_IRQ92_95_PRIORITY)); + irqinfo(" %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ96_99_PRIORITY), getreg32(NVIC_IRQ100_103_PRIORITY), + getreg32(NVIC_IRQ104_107_PRIORITY), getreg32(NVIC_IRQ108_111_PRIORITY)); +#if NR_VECTORS > 111 + irqinfo(" %08x %08x\n", + getreg32(NVIC_IRQ112_115_PRIORITY), getreg32(NVIC_IRQ116_119_PRIORITY)); +#endif + + leave_critical_section(flags); +} +#else +# define xmc4_dump_nvic(msg, irq) +#endif + +/**************************************************************************** + * Name: xmc4_nmi, xmc4_busfault, xmc4_usagefault, xmc4_pendsv, + * xmc4_dbgmonitor, xmc4_pendsv, xmc4_reserved + * + * Description: + * Handlers for various execptions. None are handled and all are fatal + * error conditions. The only advantage these provided over the default + * unexpected interrupt handler is that they provide a diagnostic output. + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_FEATURES +static int xmc4_nmi(int irq, FAR void *context, FAR void *arg) +{ + (void)up_irq_save(); + _err("PANIC!!! NMI received\n"); + PANIC(); + return 0; +} + +static int xmc4_busfault(int irq, FAR void *context, FAR void *arg) +{ + (void)up_irq_save(); + _err("PANIC!!! Bus fault recived\n"); + PANIC(); + return 0; +} + +static int xmc4_usagefault(int irq, FAR void *context, FAR void *arg) +{ + (void)up_irq_save(); + _err("PANIC!!! Usage fault received\n"); + PANIC(); + return 0; +} + +static int xmc4_pendsv(int irq, FAR void *context, FAR void *arg) +{ + (void)up_irq_save(); + _err("PANIC!!! PendSV received\n"); + PANIC(); + return 0; +} + +static int xmc4_dbgmonitor(int irq, FAR void *context, FAR void *arg) +{ + (void)up_irq_save(); + _err("PANIC!!! Debug Monitor received\n"); + PANIC(); + return 0; +} + +static int xmc4_reserved(int irq, FAR void *context, FAR void *arg) +{ + (void)up_irq_save(); + _err("PANIC!!! Reserved interrupt\n"); + PANIC(); + return 0; +} +#endif + +/**************************************************************************** + * Name: xmc4_prioritize_syscall + * + * Description: + * Set the priority of an exception. This function may be needed + * internally even if support for prioritized interrupts is not enabled. + * + ****************************************************************************/ + +#ifdef CONFIG_ARMV7M_USEBASEPRI +static inline void xmc4_prioritize_syscall(int priority) +{ + uint32_t regval; + + /* SVCALL is system handler 11 */ + + regval = getreg32(NVIC_SYSH8_11_PRIORITY); + regval &= ~NVIC_SYSH_PRIORITY_PR11_MASK; + regval |= (priority << NVIC_SYSH_PRIORITY_PR11_SHIFT); + putreg32(regval, NVIC_SYSH8_11_PRIORITY); +} +#endif + +/**************************************************************************** + * Name: xmc4_irqinfo + * + * Description: + * Given an IRQ number, provide the register and bit setting to enable or + * disable the irq. + * + ****************************************************************************/ + +static int xmc4_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, + uintptr_t offset) +{ + DEBUGASSERT(irq >= XMC4_IRQ_NMI && irq < NR_IRQS); + + /* Check for external interrupt */ + + if (irq >= XMC4_IRQ_FIRST) + { + if (irq < (XMC4_IRQ_FIRST+32)) + { + *regaddr = (NVIC_IRQ0_31_ENABLE + offset); + *bit = 1 << (irq - XMC4_IRQ_FIRST); + } + else if (irq < (XMC4_IRQ_FIRST+64)) + { + *regaddr = (NVIC_IRQ32_63_ENABLE + offset); + *bit = 1 << (irq - XMC4_IRQ_FIRST - 32); + } + else if (irq < (XMC4_IRQ_FIRST+96)) + { + *regaddr = (NVIC_IRQ64_95_ENABLE + offset); + *bit = 1 << (irq - XMC4_IRQ_FIRST - 64); + } + else if (irq < NR_IRQS) + { + *regaddr = (NVIC_IRQ96_127_ENABLE + offset); + *bit = 1 << (irq - XMC4_IRQ_FIRST - 96); + } + else + { + return ERROR; /* Invalid irq */ + } + } + + /* Handle processor exceptions. Only a few can be disabled */ + + else + { + *regaddr = NVIC_SYSHCON; + if (irq == XMC4_IRQ_MEMFAULT) + { + *bit = NVIC_SYSHCON_MEMFAULTENA; + } + else if (irq == XMC4_IRQ_BUSFAULT) + { + *bit = NVIC_SYSHCON_BUSFAULTENA; + } + else if (irq == XMC4_IRQ_USAGEFAULT) + { + *bit = NVIC_SYSHCON_USGFAULTENA; + } + else if (irq == XMC4_IRQ_SYSTICK) + { + *regaddr = NVIC_SYSTICK_CTRL; + *bit = NVIC_SYSTICK_CTRL_ENABLE; + } + else + { + return ERROR; /* Invalid or unsupported exception */ + } + } + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_irqinitialize + ****************************************************************************/ + +void up_irqinitialize(void) +{ + uintptr_t regaddr; + int nintlines; + int i; + + /* The NVIC ICTR register (bits 0-4) holds the number of of interrupt + * lines that the NVIC supports, defined in groups of 32. That is, + * the total number of interrupt lines is up to (32*(INTLINESNUM+1)). + * + * 0 -> 32 interrupt lines, 1 enable register, 8 priority registers + * 1 -> 64 " " " ", 2 enable registers, 16 priority registers + * 2 -> 96 " " " ", 3 enable regsiters, 24 priority registers + * ... + */ + + nintlines = (getreg32(NVIC_ICTR) & NVIC_ICTR_INTLINESNUM_MASK) + 1; + + /* Disable all interrupts. There are nintlines interrupt enable + * registers. + */ + + for (i = nintlines, regaddr = NVIC_IRQ0_31_ENABLE; + i > 0; + i--, regaddr += 4) + { + putreg32(0, regaddr); + } + + /* Make sure that we are using the correct vector table. The default + * vector address is 0x0000:0000 but if we are executing code that is + * positioned in SRAM or in external FLASH, then we may need to reset + * the interrupt vector so that it refers to the table in SRAM or in + * external FLASH. + */ + + putreg32((uint32_t)_vectors, NVIC_VECTAB); + +#ifdef CONFIG_ARCH_RAMVECTORS + /* If CONFIG_ARCH_RAMVECTORS is defined, then we are using a RAM-based + * vector table that requires special initialization. + */ + + up_ramvec_initialize(); +#endif + + /* Set all interrupts (and exceptions) to the default priority */ + + putreg32(DEFPRIORITY32, NVIC_SYSH4_7_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_SYSH8_11_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_SYSH12_15_PRIORITY); + + /* Now set all of the interrupt lines to the default priority. There are + * nintlines * 8 priority registers. + */ + + for (i = (nintlines << 3), regaddr = NVIC_IRQ0_3_PRIORITY; + i > 0; + i--, regaddr += 4) + { + putreg32(DEFPRIORITY32, regaddr); + } + + /* currents_regs is non-NULL only while processing an interrupt */ + + CURRENT_REGS = NULL; + + /* Attach the SVCall and Hard Fault exception handlers. The SVCall + * exception is used for performing context switches; The Hard Fault + * must also be caught because a SVCall may show up as a Hard Fault + * under certain conditions. + */ + + irq_attach(XMC4_IRQ_SVCALL, up_svcall, NULL); + irq_attach(XMC4_IRQ_HARDFAULT, up_hardfault, NULL); + + /* Set the priority of the SVCall interrupt */ + +#ifdef CONFIG_ARCH_IRQPRIO + /* up_prioritize_irq(XMC4_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ +#endif +#ifdef CONFIG_ARMV7M_USEBASEPRI + xmc4_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY); +#endif + + /* If the MPU is enabled, then attach and enable the Memory Management + * Fault handler. + */ + +#ifdef CONFIG_ARM_MPU + irq_attach(XMC4_IRQ_MEMFAULT, up_memfault, NULL); + up_enable_irq(XMC4_IRQ_MEMFAULT); +#endif + + /* Attach all other processor exceptions (except reset and sys tick) */ + +#ifdef CONFIG_DEBUG_FEATURES + irq_attach(XMC4_IRQ_NMI, xmc4_nmi, NULL); +#ifndef CONFIG_ARM_MPU + irq_attach(XMC4_IRQ_MEMFAULT, up_memfault, NULL); +#endif + irq_attach(XMC4_IRQ_BUSFAULT, xmc4_busfault, NULL); + irq_attach(XMC4_IRQ_USAGEFAULT, xmc4_usagefault, NULL); + irq_attach(XMC4_IRQ_PENDSV, xmc4_pendsv, NULL); + irq_attach(XMC4_IRQ_DBGMONITOR, xmc4_dbgmonitor, NULL); + irq_attach(XMC4_IRQ_RESERVED, xmc4_reserved, NULL); +#endif + + xmc4_dump_nvic("initial", NR_IRQS); + + /* Initialize logic to support a second level of interrupt decoding for + * configured pin interrupts. + */ + +#ifdef CONFIG_XMC4_GPIOIRQ + xmc4_gpioirq_initialize(); +#endif + + /* And finally, enable interrupts */ + +#ifndef CONFIG_SUPPRESS_INTERRUPTS + up_irq_enable(); +#endif +} + +/**************************************************************************** + * Name: up_disable_irq + * + * Description: + * Disable the IRQ specified by 'irq' + * + ****************************************************************************/ + +void up_disable_irq(int irq) +{ + uintptr_t regaddr; + uint32_t regval; + uint32_t bit; + + if (xmc4_irqinfo(irq, ®addr, &bit, NVIC_CLRENA_OFFSET) == 0) + { + /* Modify the appropriate bit in the register to disable the interrupt. + * For normal interrupts, we need to set the bit in the associated + * Interrupt Clear Enable register. For other exceptions, we need to + * clear the bit in the System Handler Control and State Register. + */ + + if (irq >= XMC4_IRQ_FIRST) + { + putreg32(bit, regaddr); + } + else + { + regval = getreg32(regaddr); + regval &= ~bit; + putreg32(regval, regaddr); + } + } + + xmc4_dump_nvic("disable", irq); +} + +/**************************************************************************** + * Name: up_enable_irq + * + * Description: + * Enable the IRQ specified by 'irq' + * + ****************************************************************************/ + +void up_enable_irq(int irq) +{ + uintptr_t regaddr; + uint32_t regval; + uint32_t bit; + + if (xmc4_irqinfo(irq, ®addr, &bit, NVIC_ENA_OFFSET) == 0) + { + /* Modify the appropriate bit in the register to enable the interrupt. + * For normal interrupts, we need to set the bit in the associated + * Interrupt Set Enable register. For other exceptions, we need to + * set the bit in the System Handler Control and State Register. + */ + + if (irq >= XMC4_IRQ_FIRST) + { + putreg32(bit, regaddr); + } + else + { + regval = getreg32(regaddr); + regval |= bit; + putreg32(regval, regaddr); + } + } + + xmc4_dump_nvic("enable", irq); +} + +/**************************************************************************** + * Name: up_ack_irq + * + * Description: + * Acknowledge the IRQ + * + ****************************************************************************/ + +void up_ack_irq(int irq) +{ +#if 0 /* Does not appear to be necessary in most cases */ + xmc4_clrpend(irq); +#endif +} + +/**************************************************************************** + * Name: up_prioritize_irq + * + * Description: + * Set the priority of an IRQ. + * + * Since this API is not supported on all architectures, it should be + * avoided in common implementations where possible. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQPRIO +int up_prioritize_irq(int irq, int priority) +{ + uint32_t regaddr; + uint32_t regval; + int shift; + + DEBUGASSERT(irq >= XMC4_IRQ_MEMFAULT && irq < NR_IRQS && + (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN); + + if (irq < XMC4_IRQ_FIRST) + { + /* NVIC_SYSH_PRIORITY() maps {0..15} to one of three priority + * registers (0-3 are invalid) + */ + + regaddr = NVIC_SYSH_PRIORITY(irq); + irq -= 4; + } + else + { + /* NVIC_IRQ_PRIORITY() maps {0..} to one of many priority registers */ + + irq -= XMC4_IRQ_FIRST; + regaddr = NVIC_IRQ_PRIORITY(irq); + } + + regval = getreg32(regaddr); + shift = ((irq & 3) << 3); + regval &= ~(0xff << shift); + regval |= (priority << shift); + putreg32(regval, regaddr); + + xmc4_dump_nvic("prioritize", irq); + return OK; +} +#endif diff --git a/arch/arm/src/xmc4/xmc4_lowputc.c b/arch/arm/src/xmc4/xmc4_lowputc.c new file mode 100644 index 00000000000..8fe2f4094b8 --- /dev/null +++ b/arch/arm/src/xmc4/xmc4_lowputc.c @@ -0,0 +1,235 @@ +/**************************************************************************** + * arch/arm/src/xmc4/xmc4_lowputc.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include + +#include "up_internal.h" +#include "up_arch.h" + +#include "xmc4_config.h" +#include "chip/xmc4_uart.h" +#include "chip/xmc4_pinmux.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Select UART parameters for the selected console */ + +#if defined(HAVE_UART_CONSOLE) +# if defined(CONFIG_UART0_SERIAL_CONSOLE) +# define CONSOLE_BASE XMC4_UART0_BASE +# define CONSOLE_FREQ BOARD_CORECLK_FREQ +# define CONSOLE_BAUD CONFIG_UART0_BAUD +# define CONSOLE_BITS CONFIG_UART0_BITS +# define CONSOLE_2STOP CONFIG_UART0_2STOP +# define CONSOLE_PARITY CONFIG_UART0_PARITY +# elif defined(CONFIG_UART1_SERIAL_CONSOLE) +# define CONSOLE_BASE XMC4_UART1_BASE +# define CONSOLE_FREQ BOARD_CORECLK_FREQ +# define CONSOLE_BAUD CONFIG_UART1_BAUD +# define CONSOLE_BITS CONFIG_UART1_BITS +# define CONSOLE_2STOP CONFIG_UART1_2STOP +# define CONSOLE_PARITY CONFIG_UART1_PARITY +# elif defined(CONFIG_UART2_SERIAL_CONSOLE) +# define CONSOLE_BASE XMC4_UART2_BASE +# define CONSOLE_FREQ BOARD_BUS_FREQ +# define CONSOLE_BAUD CONFIG_UART2_BAUD +# define CONSOLE_BITS CONFIG_UART2_BITS +# define CONSOLE_2STOP CONFIG_UART2_2STOP +# define CONSOLE_PARITY CONFIG_UART2_PARITY +# elif defined(CONFIG_UART3_SERIAL_CONSOLE) +# define CONSOLE_BASE XMC4_UART3_BASE +# define CONSOLE_FREQ BOARD_BUS_FREQ +# define CONSOLE_BAUD CONFIG_UART3_BAUD +# define CONSOLE_BITS CONFIG_UART3_BITS +# define CONSOLE_2STOP CONFIG_UART3_2STOP +# define CONSOLE_PARITY CONFIG_UART3_PARITY +# elif defined(CONFIG_UART4_SERIAL_CONSOLE) +# define CONSOLE_BASE XMC4_UART4_BASE +# define CONSOLE_FREQ BOARD_BUS_FREQ +# define CONSOLE_BAUD CONFIG_UART4_BAUD +# define CONSOLE_BITS CONFIG_UART4_BITS +# define CONSOLE_2STOP CONFIG_UART4_2STOP +# define CONSOLE_PARITY CONFIG_UART4_PARITY +# elif defined(CONFIG_UART5_SERIAL_CONSOLE) +# define CONSOLE_BASE XMC4_UART5_BASE +# define CONSOLE_FREQ BOARD_BUS_FREQ +# define CONSOLE_BAUD CONFIG_UART5_BAUD +# define CONSOLE_BITS CONFIG_UART5_BITS +# define CONSOLE_2STOP CONFIG_UART5_2STOP +# define CONSOLE_PARITY CONFIG_UART5_PARITY +# elif defined(HAVE_UART_CONSOLE) +# error "No CONFIG_UARTn_SERIAL_CONSOLE Setting" +# endif +#endif /* HAVE_UART_CONSOLE */ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_lowputc + * + * Description: + * Output one byte on the serial console + * + ****************************************************************************/ + +void up_lowputc(char ch) +{ +#ifdef HAVE_UART_CONSOLE + /* Wait until the transmit data register is "empty" (TDRE). This state + * depends on the TX watermark setting and may not mean that the transmit + * buffer is truly empty. It just means that we can now add another + * character to the transmit buffer without exceeding the watermark. + * + * NOTE: UART0 has an 8-byte deep FIFO; the other UARTs have no FIFOs + * (1-deep). There appears to be no way to know when the FIFO is not + * full (other than reading the FIFO length and comparing the FIFO count). + * Hence, the FIFOs are not used in this implementation and, as a result + * TDRE indeed mean that the single output buffer is available. + * + * Performance on UART0 could be improved by enabling the FIFO and by + * redesigning all of the FIFO status logic. + */ +#warning Missing logic + + /* Then write the character to the UART data register */ + +#warning Missing logic +} + +/**************************************************************************** + * Name: xmc4_lowsetup + * + * Description: + * This performs basic initialization of the UART used for the serial + * console. Its purpose is to get the console output available as soon + * as possible. + * + ****************************************************************************/ + +void xmc4_lowsetup(void) +{ + uint32_t regval; + + /* Enable peripheral clocking for all enabled UARTs. */ +#wanring Missing logic + + /* Configure UART pins for the all enabled UARTs */ + + /* Configure the console (only) now. Other UARTs will be configured + * when the serial driver is opened. + */ + + xmc4_uart_configure(CONSOLE_BASE, CONSOLE_BAUD, CONSOLE_FREQ, \ + CONSOLE_PARITY, CONSOLE_BITS, CONSOLE_2STOP); +#endif /* HAVE_UART_DEVICE */ +} + +/**************************************************************************** + * Name: xmc4_uart_reset + * + * Description: + * Reset a UART. + * + ****************************************************************************/ + +#ifdef HAVE_UART_DEVICE +void xmc4_uart_reset(uintptr_t uart_base) +{ + uint8_t regval; + + /* Just disable the transmitter and receiver */ +#warning Missing logic +} +#endif + +/**************************************************************************** + * Name: xmc4_uart_configure + * + * Description: + * Configure a UART as a RS-232 UART. + * + ****************************************************************************/ + +#ifdef HAVE_UART_DEVICE +void xmc4_uart_configure(uintptr_t uart_base, uint32_t baud, + uint32_t clock, unsigned int parity, + unsigned int nbits, unsigned int stop2) +{ + /* Disable the transmitter and receiver throughout the reconfiguration */ +#warning Missing logic + + /* Configure number of bits, stop bits and parity */ +#warning Missing logic + + /* Check for odd parity */ +#warning Missing logic + + /* Check for even parity */ +#warning Missing logic + + /* Check for 9-bit operation */ +#warning Missing logic + + /* Calculate baud settings (truncating) */ +#warning Missing logic + + /* Configure FIFOs */ +#warning Missing logic + + /* Enable RX and TX FIFOs */ +#warning Missing logic + + /* Now we can (re-)enable the transmitter and receiver */ +#warning Missing logic +} +#endif + diff --git a/arch/arm/src/xmc4/xmc4_mpuinit.c b/arch/arm/src/xmc4/xmc4_mpuinit.c new file mode 100644 index 00000000000..9cd22451be4 --- /dev/null +++ b/arch/arm/src/xmc4/xmc4_mpuinit.c @@ -0,0 +1,124 @@ +/**************************************************************************** + * arch/arm/src/xmc4/xmc4_mpuinit.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +#include "mpu.h" +#include "xmc4_mpuinit.h" + +#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_ARM_MPU) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef MAX +# define MAX(a,b) a > b ? a : b +#endif + +#ifndef MIN +# define MIN(a,b) a < b ? a : b +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: xmc4_mpuinitialize + * + * Description: + * Configure the MPU to permit user-space access to only restricted SAM3U + * resources. + * + ****************************************************************************/ + +void xmc4_mpuinitialize(void) +{ + uintptr_t datastart = MIN(USERSPACE->us_datastart, USERSPACE->us_bssstart); + uintptr_t dataend = MAX(USERSPACE->us_dataend, USERSPACE->us_bssend); + + DEBUGASSERT(USERSPACE->us_textend >= USERSPACE->us_textstart && + dataend >= datastart); + + /* Show MPU information */ + + mpu_showtype(); + + /* Configure user flash and SRAM space */ + + mpu_user_flash(USERSPACE->us_textstart, + USERSPACE->us_textend - USERSPACE->us_textstart); + + mpu_user_intsram(datastart, dataend - datastart); + + /* Then enable the MPU */ + + mpu_control(true, false, true); +} + +/**************************************************************************** + * Name: xmc4_mpu_uheap + * + * Description: + * Map the user-heap region. + * + * This logic may need an extension to handle external SDRAM). + * + ****************************************************************************/ + +void xmc4_mpu_uheap(uintptr_t start, size_t size) +{ + mpu_user_intsram(start, size); +} + +#endif /* CONFIG_BUILD_PROTECTED && CONFIG_ARM_MPU */ + diff --git a/arch/arm/src/xmc4/xmc4_mpuinit.h b/arch/arm/src/xmc4/xmc4_mpuinit.h new file mode 100644 index 00000000000..f318424bad7 --- /dev/null +++ b/arch/arm/src/xmc4/xmc4_mpuinit.h @@ -0,0 +1,78 @@ +/************************************************************************************ + * arch/arm/src/xmc4/xmc4_mpuinit.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_XMC4_XMC4_MPUINIT_H +#define __ARCH_ARM_SRC_XMC4_XMC4_MPUINIT_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/**************************************************************************** + * Name: xmc4_mpuinitialize + * + * Description: + * Configure the MPU to permit user-space access to only unrestricted MCU + * resources. + * + ****************************************************************************/ + +#ifdef CONFIG_BUILD_PROTECTED +void xmc4_mpuinitialize(void); +#else +# define xmc4_mpuinitialize() +#endif + +/**************************************************************************** + * Name: xmc4_mpu_uheap + * + * Description: + * Map the user heap region. + * + ****************************************************************************/ + +#ifdef CONFIG_BUILD_PROTECTED +void xmc4_mpu_uheap(uintptr_t start, size_t size); +#else +# define xmc4_mpu_uheap(start,size) +#endif + +#endif /* __ARCH_ARM_SRC_XMC4_XMC4_MPUINIT_H */ diff --git a/arch/arm/src/xmc4/xmc4_pwm.c b/arch/arm/src/xmc4/xmc4_pwm.c new file mode 100644 index 00000000000..e69de29bb2d diff --git a/arch/arm/src/xmc4/xmc4_pwm.h b/arch/arm/src/xmc4/xmc4_pwm.h new file mode 100644 index 00000000000..4de5b5f56aa --- /dev/null +++ b/arch/arm/src/xmc4/xmc4_pwm.h @@ -0,0 +1,100 @@ +/************************************************************************************ + * arch/arm/src/xmc4/xmc4_pwm.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_XMC4_XMC4_PWM_H +#define __ARCH_ARM_SRC_XMC4_XMC4_PWM_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Configuration ********************************************************************/ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: xmc4_pwm_initialize + * + * Description: + * Initialize one timer for use with the upper_level PWM driver. + * + * Input Parameters: + * timer - A number identifying the timer use. + * + * Returned Value: + * On success, a pointer to the kinetis lower half PWM driver is returned. + * NULL is returned on any failure. + * + ************************************************************************************/ + +FAR struct pwm_lowerhalf_s *xmc4_pwm_initialize(int timer); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* CONFIG_XMC4_FTMx_PWM */ +#endif /* __ARCH_ARM_SRC_XMC4_XMC4_PWM_H */ diff --git a/arch/arm/src/xmc4/xmc4_serial.c b/arch/arm/src/xmc4/xmc4_serial.c new file mode 100644 index 00000000000..b90f1c19ff1 --- /dev/null +++ b/arch/arm/src/xmc4/xmc4_serial.c @@ -0,0 +1,1146 @@ +/**************************************************************************** + * arch/arm/src/xmc4/xmc4_serial.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include + +#include "up_arch.h" +#include "up_internal.h" + +#include "xmc4_config.h" +#include "chip.h" +#include "chip/xmc4_uart.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +/* Some sanity checks *******************************************************/ +/* Is there at least one UART enabled and configured as a RS-232 device? */ + +#ifndef HAVE_UART_DEVICE +# warning "No UARTs enabled" +#endif + +/* If we are not using the serial driver for the console, then we still must + * provide some minimal implementation of up_putc. + */ + +#if defined(HAVE_UART_DEVICE) && defined(USE_SERIALDRIVER) + +/* Which UART with be tty0/console and which tty1-4? The console will always + * be ttyS0. If there is no console then will use the lowest numbered UART. + */ + +/* First pick the console and ttys0. This could be any of UART0-5 */ + +#if defined(CONFIG_UART0_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart0port /* UART0 is console */ +# define TTYS0_DEV g_uart0port /* UART0 is ttyS0 */ +# define UART0_ASSIGNED 1 +#elif defined(CONFIG_UART1_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart1port /* UART1 is console */ +# define TTYS0_DEV g_uart1port /* UART1 is ttyS0 */ +# define UART1_ASSIGNED 1 +#elif defined(CONFIG_UART2_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart2port /* UART2 is console */ +# define TTYS0_DEV g_uart2port /* UART2 is ttyS0 */ +# define UART2_ASSIGNED 1 +#elif defined(CONFIG_UART3_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart3port /* UART3 is console */ +# define TTYS0_DEV g_uart3port /* UART3 is ttyS0 */ +# define UART3_ASSIGNED 1 +#elif defined(CONFIG_UART4_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart4port /* UART4 is console */ +# define TTYS0_DEV g_uart4port /* UART4 is ttyS0 */ +# define UART4_ASSIGNED 1 +#elif defined(CONFIG_UART5_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart5port /* UART5 is console */ +# define TTYS5_DEV g_uart5port /* UART5 is ttyS0 */ +# define UART5_ASSIGNED 1 +#else +# undef CONSOLE_DEV /* No console */ +# if defined(CONFIG_XMC4_USIC0_ISUART) +# define TTYS0_DEV g_uart0port /* UART0 is ttyS0 */ +# define UART0_ASSIGNED 1 +# elif defined(CONFIG_XMC4_USIC1_ISUART) +# define TTYS0_DEV g_uart1port /* UART1 is ttyS0 */ +# define UART1_ASSIGNED 1 +# elif defined(CONFIG_XMC4_USIC2_ISUART) +# define TTYS0_DEV g_uart2port /* UART2 is ttyS0 */ +# define UART2_ASSIGNED 1 +# elif defined(CONFIG_XMC4_USIC3_ISUART) +# define TTYS0_DEV g_uart3port /* UART3 is ttyS0 */ +# define UART3_ASSIGNED 1 +# elif defined(CONFIG_XMC4_USIC4_ISUART) +# define TTYS0_DEV g_uart4port /* UART4 is ttyS0 */ +# define UART4_ASSIGNED 1 +# elif defined(CONFIG_XMC4_USIC5_ISUART) +# define TTYS0_DEV g_uart5port /* UART5 is ttyS0 */ +# define UART5_ASSIGNED 1 +# endif +#endif + +/* Pick ttys1. This could be any of UART0-5 excluding the console UART. */ + +#if defined(CONFIG_XMC4_USIC0_ISUART) && !defined(UART0_ASSIGNED) +# define TTYS1_DEV g_uart0port /* UART0 is ttyS1 */ +# define UART0_ASSIGNED 1 +#elif defined(CONFIG_XMC4_USIC1_ISUART) && !defined(UART1_ASSIGNED) +# define TTYS1_DEV g_uart1port /* UART1 is ttyS1 */ +# define UART1_ASSIGNED 1 +#elif defined(CONFIG_XMC4_USIC2_ISUART) && !defined(UART2_ASSIGNED) +# define TTYS1_DEV g_uart2port /* UART2 is ttyS1 */ +# define UART2_ASSIGNED 1 +#elif defined(CONFIG_XMC4_USIC3_ISUART) && !defined(UART3_ASSIGNED) +# define TTYS1_DEV g_uart3port /* UART3 is ttyS1 */ +# define UART3_ASSIGNED 1 +#elif defined(CONFIG_XMC4_USIC4_ISUART) && !defined(UART4_ASSIGNED) +# define TTYS1_DEV g_uart4port /* UART4 is ttyS1 */ +# define UART4_ASSIGNED 1 +#elif defined(CONFIG_XMC4_USIC5_ISUART) && !defined(UART5_ASSIGNED) +# define TTYS1_DEV g_uart5port /* UART5 is ttyS1 */ +# define UART5_ASSIGNED 1 +#endif + +/* Pick ttys2. This could be one of UART1-5. It can't be UART0 because that + * was either assigned as ttyS0 or ttys1. One of UART 1-5 could also be the + * console. + */ + +#if defined(CONFIG_XMC4_USIC1_ISUART) && !defined(UART1_ASSIGNED) +# define TTYS2_DEV g_uart1port /* UART1 is ttyS2 */ +# define UART1_ASSIGNED 1 +#elif defined(CONFIG_XMC4_USIC2_ISUART) && !defined(UART2_ASSIGNED) +# define TTYS2_DEV g_uart2port /* UART2 is ttyS2 */ +# define UART2_ASSIGNED 1 +#elif defined(CONFIG_XMC4_USIC3_ISUART) && !defined(UART3_ASSIGNED) +# define TTYS2_DEV g_uart3port /* UART3 is ttyS2 */ +# define UART3_ASSIGNED 1 +#elif defined(CONFIG_XMC4_USIC4_ISUART) && !defined(UART4_ASSIGNED) +# define TTYS2_DEV g_uart4port /* UART4 is ttyS2 */ +# define UART4_ASSIGNED 1 +#elif defined(CONFIG_XMC4_USIC5_ISUART) && !defined(UART5_ASSIGNED) +# define TTYS2_DEV g_uart5port /* UART5 is ttyS2 */ +# define UART5_ASSIGNED 1 +#endif + +/* Pick ttys3. This could be one of UART2-5. It can't be UART0-1 because + * those have already been assigned to ttsyS0, 1, or 2. One of + * UART 2-5 could also be the console. + */ + +#if defined(CONFIG_XMC4_USIC2_ISUART) && !defined(UART2_ASSIGNED) +# define TTYS3_DEV g_uart2port /* UART2 is ttyS3 */ +# define UART2_ASSIGNED 1 +#elif defined(CONFIG_XMC4_USIC3_ISUART) && !defined(UART3_ASSIGNED) +# define TTYS3_DEV g_uart3port /* UART3 is ttyS3 */ +# define UART3_ASSIGNED 1 +#elif defined(CONFIG_XMC4_USIC4_ISUART) && !defined(UART4_ASSIGNED) +# define TTYS3_DEV g_uart4port /* UART4 is ttyS3 */ +# define UART4_ASSIGNED 1 +#elif defined(CONFIG_XMC4_USIC5_ISUART) && !defined(UART5_ASSIGNED) +# define TTYS3_DEV g_uart5port /* UART5 is ttyS3 */ +# define UART5_ASSIGNED 1 +#endif + +/* Pick ttys4. This could be one of UART3-5. It can't be UART0-2 because + * those have already been assigned to ttsyS0, 1, 2 or 3. One of + * UART 3-5 could also be the console. + */ + +#if defined(CONFIG_XMC4_USIC3_ISUART) && !defined(UART3_ASSIGNED) +# define TTYS4_DEV g_uart3port /* UART3 is ttyS4 */ +# define UART3_ASSIGNED 1 +#elif defined(CONFIG_XMC4_USIC4_ISUART) && !defined(UART4_ASSIGNED) +# define TTYS4_DEV g_uart4port /* UART4 is ttyS4 */ +# define UART4_ASSIGNED 1 +#elif defined(CONFIG_XMC4_USIC5_ISUART) && !defined(UART5_ASSIGNED) +# define TTYS4_DEV g_uart5port /* UART5 is ttyS4 */ +# define UART5_ASSIGNED 1 +#endif + +/* Pick ttys5. This could be one of UART4-5. It can't be UART0-3 because + * those have already been assigned to ttsyS0, 1, 2, 3 or 4. One of + * UART 4-5 could also be the console. + */ + +#if defined(CONFIG_XMC4_USIC4_ISUART) && !defined(UART4_ASSIGNED) +# define TTYS5_DEV g_uart4port /* UART4 is ttyS5 */ +# define UART4_ASSIGNED 1 +#elif defined(CONFIG_XMC4_USIC5_ISUART) && !defined(UART5_ASSIGNED) +# define TTYS5_DEV g_uart5port /* UART5 is ttyS5 */ +# define UART5_ASSIGNED 1 +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct xmc4_dev_s +{ + uintptr_t uartbase; /* Base address of UART registers */ + uint32_t baud; /* Configured baud */ + uint32_t clock; /* Clocking frequency of the UART module */ + uint8_t irqs; /* Status IRQ associated with this UART (for enable) */ + uint8_t ie; /* Interrupts enabled */ + uint8_t parity; /* 0=none, 1=odd, 2=even */ + uint8_t bits; /* Number of bits (8 or 9) */ + uint8_t stop2; /* Use 2 stop bits */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int xmc4_setup(struct uart_dev_s *dev); +static void xmc4_shutdown(struct uart_dev_s *dev); +static int xmc4_attach(struct uart_dev_s *dev); +static void xmc4_detach(struct uart_dev_s *dev); +static int xmc4_interrupt(int irq, void *context, FAR void *arg); +static int xmc4_ioctl(struct file *filep, int cmd, unsigned long arg); +static int xmc4_receive(struct uart_dev_s *dev, uint32_t *status); +static void xmc4_rxint(struct uart_dev_s *dev, bool enable); +static bool xmc4_rxavailable(struct uart_dev_s *dev); +static void xmc4_send(struct uart_dev_s *dev, int ch); +static void xmc4_txint(struct uart_dev_s *dev, bool enable); +static bool xmc4_txready(struct uart_dev_s *dev); +static bool xmc4_txempty(struct uart_dev_s *dev); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct uart_ops_s g_uart_ops = +{ + .setup = xmc4_setup, + .shutdown = xmc4_shutdown, + .attach = xmc4_attach, + .detach = xmc4_detach, + .ioctl = xmc4_ioctl, + .receive = xmc4_receive, + .rxint = xmc4_rxint, + .rxavailable = xmc4_rxavailable, +#ifdef CONFIG_SERIAL_IFLOWCONTROL + .rxflowcontrol = NULL, +#endif + .send = xmc4_send, + .txint = xmc4_txint, + .txready = xmc4_txready, + .txempty = xmc4_txempty, +}; + +/* I/O buffers */ + +#ifdef CONFIG_XMC4_USIC0_ISUART +static char g_uart0rxbuffer[CONFIG_UART0_RXBUFSIZE]; +static char g_uart0txbuffer[CONFIG_UART0_TXBUFSIZE]; +#endif +#ifdef CONFIG_XMC4_USIC1_ISUART +static char g_uart1rxbuffer[CONFIG_UART1_RXBUFSIZE]; +static char g_uart1txbuffer[CONFIG_UART1_TXBUFSIZE]; +#endif +#ifdef CONFIG_XMC4_USIC2_ISUART +static char g_uart2rxbuffer[CONFIG_UART2_RXBUFSIZE]; +static char g_uart2txbuffer[CONFIG_UART2_TXBUFSIZE]; +#endif +#ifdef CONFIG_XMC4_USIC3_ISUART +static char g_uart3rxbuffer[CONFIG_UART3_RXBUFSIZE]; +static char g_uart3txbuffer[CONFIG_UART3_TXBUFSIZE]; +#endif +#ifdef CONFIG_XMC4_USIC4_ISUART +static char g_uart4rxbuffer[CONFIG_UART4_RXBUFSIZE]; +static char g_uart4txbuffer[CONFIG_UART4_TXBUFSIZE]; +#endif +#ifdef CONFIG_XMC4_USIC5_ISUART +static char g_uart5rxbuffer[CONFIG_UART5_RXBUFSIZE]; +static char g_uart5txbuffer[CONFIG_UART5_TXBUFSIZE]; +#endif + +/* This describes the state of the Kinetis UART0 port. */ + +#ifdef CONFIG_XMC4_USIC0_ISUART +static struct xmc4_dev_s g_uart0priv = +{ + .uartbase = XMC4_UART0_BASE, + .clock = BOARD_CORECLK_FREQ, + .baud = CONFIG_UART0_BAUD, + .irqs = XMC4_IRQ_USIC0, + .parity = CONFIG_UART0_PARITY, + .bits = CONFIG_UART0_BITS, + .stop2 = CONFIG_UART0_2STOP, +}; + +static uart_dev_t g_uart0port = +{ + .recv = + { + .size = CONFIG_UART0_RXBUFSIZE, + .buffer = g_uart0rxbuffer, + }, + .xmit = + { + .size = CONFIG_UART0_TXBUFSIZE, + .buffer = g_uart0txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart0priv, +}; +#endif + +/* This describes the state of the Kinetis UART1 port. */ + +#ifdef CONFIG_XMC4_USIC1_ISUART +static struct xmc4_dev_s g_uart1priv = +{ + .uartbase = XMC4_UART1_BASE, + .clock = BOARD_CORECLK_FREQ, + .baud = CONFIG_UART1_BAUD, + .irqs = XMC4_IRQ_USIC1, + .parity = CONFIG_UART1_PARITY, + .bits = CONFIG_UART1_BITS, + .stop2 = CONFIG_UART1_2STOP, +}; + +static uart_dev_t g_uart1port = +{ + .recv = + { + .size = CONFIG_UART1_RXBUFSIZE, + .buffer = g_uart1rxbuffer, + }, + .xmit = + { + .size = CONFIG_UART1_TXBUFSIZE, + .buffer = g_uart1txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart1priv, +}; +#endif + +/* This describes the state of the Kinetis UART2 port. */ + +#ifdef CONFIG_XMC4_USIC2_ISUART +static struct xmc4_dev_s g_uart2priv = +{ + .uartbase = XMC4_UART2_BASE, + .clock = BOARD_BUS_FREQ, + .baud = CONFIG_UART2_BAUD, + .irqs = XMC4_IRQ_USIC2, + .parity = CONFIG_UART2_PARITY, + .bits = CONFIG_UART2_BITS, + .stop2 = CONFIG_UART2_2STOP, +}; + +static uart_dev_t g_uart2port = +{ + .recv = + { + .size = CONFIG_UART2_RXBUFSIZE, + .buffer = g_uart2rxbuffer, + }, + .xmit = + { + .size = CONFIG_UART2_TXBUFSIZE, + .buffer = g_uart2txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart2priv, +}; +#endif + +/* This describes the state of the Kinetis UART3 port. */ + +#ifdef CONFIG_XMC4_USIC3_ISUART +static struct xmc4_dev_s g_uart3priv = +{ + .uartbase = XMC4_UART3_BASE, + .clock = BOARD_BUS_FREQ, + .baud = CONFIG_UART3_BAUD, + .irqs = XMC4_IRQ_USIC3, + .parity = CONFIG_UART3_PARITY, + .bits = CONFIG_UART3_BITS, + .stop2 = CONFIG_UART3_2STOP, +}; + +static uart_dev_t g_uart3port = +{ + .recv = + { + .size = CONFIG_UART3_RXBUFSIZE, + .buffer = g_uart3rxbuffer, + }, + .xmit = + { + .size = CONFIG_UART3_TXBUFSIZE, + .buffer = g_uart3txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart3priv, +}; +#endif + +/* This describes the state of the Kinetis UART4 port. */ + +#ifdef CONFIG_XMC4_USIC4_ISUART +static struct xmc4_dev_s g_uart4priv = +{ + .uartbase = XMC4_UART4_BASE, + .clock = BOARD_BUS_FREQ, + .baud = CONFIG_UART4_BAUD, + .irqs = XMC4_IRQ_USIC4, + .parity = CONFIG_UART4_PARITY, + .bits = CONFIG_UART4_BITS, + .stop2 = CONFIG_UART4_2STOP, +}; + +static uart_dev_t g_uart4port = +{ + .recv = + { + .size = CONFIG_UART4_RXBUFSIZE, + .buffer = g_uart4rxbuffer, + }, + .xmit = + { + .size = CONFIG_UART4_TXBUFSIZE, + .buffer = g_uart4txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart4priv, +}; +#endif + +/* This describes the state of the Kinetis UART5 port. */ + +#ifdef CONFIG_XMC4_USIC5_ISUART +static struct xmc4_dev_s g_uart5priv = +{ + .uartbase = XMC4_UART5_BASE, + .clock = BOARD_BUS_FREQ, + .baud = CONFIG_UART5_BAUD, + .irqs = XMC4_IRQ_USIC5, + .parity = CONFIG_UART5_PARITY, + .bits = CONFIG_UART5_BITS, + .stop2 = CONFIG_UART5_2STOP, +}; + +static uart_dev_t g_uart5port = +{ + .recv = + { + .size = CONFIG_UART5_RXBUFSIZE, + .buffer = g_uart5rxbuffer, + }, + .xmit = + { + .size = CONFIG_UART5_TXBUFSIZE, + .buffer = g_uart5txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart5priv, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_serialin + ****************************************************************************/ + +static inline uint8_t up_serialin(struct xmc4_dev_s *priv, int offset) +{ + return getreg8(priv->uartbase + offset); +} + +/**************************************************************************** + * Name: up_serialout + ****************************************************************************/ + +static inline void up_serialout(struct xmc4_dev_s *priv, int offset, uint8_t value) +{ + putreg8(value, priv->uartbase + offset); +} + +/**************************************************************************** + * Name: up_setuartint + ****************************************************************************/ + +static void up_setuartint(struct xmc4_dev_s *priv) +{ + irqstate_t flags; + uint8_t regval; + + /* Re-enable/re-disable interrupts corresponding to the state of bits in ie */ +#warning Missing logic + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: up_restoreuartint + ****************************************************************************/ + +static void up_restoreuartint(struct xmc4_dev_s *priv, uint8_t ie) +{ + irqstate_t flags; + + /* Re-enable/re-disable interrupts corresponding to the state of bits in ie */ + + flags = enter_critical_section(); +#warning Missing logic + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: up_disableuartint + ****************************************************************************/ + +static void up_disableuartint(struct xmc4_dev_s *priv, uint8_t *ie) +{ + irqstate_t flags; + + flags = enter_critical_section(); + if (ie) + { + *ie = priv->ie; + } + + up_restoreuartint(priv, 0); + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: xmc4_setup + * + * Description: + * Configure the UART baud, bits, parity, etc. This method is called the + * first time that the serial port is opened. + * + ****************************************************************************/ + +static int xmc4_setup(struct uart_dev_s *dev) +{ +#ifndef CONFIG_SUPPRESS_UART_CONFIG + struct xmc4_dev_s *priv = (struct xmc4_dev_s *)dev->priv; + + /* Configure the UART as an RS-232 UART */ + + xmc4_uart_configure(priv->uartbase, priv->baud, priv->clock, + priv->parity, priv->bits, priv->stop2); +#endif + + /* Make sure that all interrupts are disabled */ + + up_restoreuartint(priv, 0); + return OK; +} + +/**************************************************************************** + * Name: xmc4_shutdown + * + * Description: + * Disable the UART. This method is called when the serial + * port is closed + * + ****************************************************************************/ + +static void xmc4_shutdown(struct uart_dev_s *dev) +{ + struct xmc4_dev_s *priv = (struct xmc4_dev_s *)dev->priv; + + /* Disable interrupts */ + + up_restoreuartint(priv, 0); + + /* Reset hardware and disable Rx and Tx */ + + xmc4_uart_reset(priv->uartbase); +} + +/**************************************************************************** + * Name: xmc4_attach + * + * Description: + * Configure the UART to operation in interrupt driven mode. This method is + * called when the serial port is opened. Normally, this is just after the + * the setup() method is called, however, the serial console may operate in + * a non-interrupt driven mode during the boot phase. + * + * RX and TX interrupts are not enabled when by the attach method (unless the + * hardware supports multiple levels of interrupt enabling). The RX and TX + * interrupts are not enabled until the txint() and rxint() methods are called. + * + ****************************************************************************/ + +static int xmc4_attach(struct uart_dev_s *dev) +{ + struct xmc4_dev_s *priv = (struct xmc4_dev_s *)dev->priv; + int ret; + + /* Attach and enable the IRQ(s). The interrupts are (probably) still + * disabled in the C2 register. + */ + + ret = irq_attach(priv->irqs, xmc4_interrupt, dev); + if (ret == OK) + { + up_enable_irq(priv->irqs); + } + + return ret; +} + +/**************************************************************************** + * Name: xmc4_detach + * + * Description: + * Detach UART interrupts. This method is called when the serial port is + * closed normally just before the shutdown method is called. The exception + * is the serial console which is never shutdown. + * + ****************************************************************************/ + +static void xmc4_detach(struct uart_dev_s *dev) +{ + struct xmc4_dev_s *priv = (struct xmc4_dev_s *)dev->priv; + + /* Disable interrupts */ + + up_restoreuartint(priv, 0); + up_disable_irq(priv->irqs); + + /* Detach from the interrupt(s) */ + + irq_detach(priv->irqs); +} + +/**************************************************************************** + * Name: xmc4_interrupt + * + * Description: + * This is the UART status interrupt handler. It will be invoked when an + * interrupt received on the 'irq' It should call uart_transmitchars or + * uart_receivechar to perform the appropriate data transfers. The + * interrupt handling logic must be able to map the 'irq' number into the + * approprite uart_dev_s structure in order to call these functions. + * + ****************************************************************************/ + +static int xmc4_interrupt(int irq, void *context, FAR void *arg) +{ + struct uart_dev_s *dev = (struct uart_dev_s *)arg; + struct xmc4_dev_s *priv; + int passes; + uint8_t s1; + bool handled; + + DEBUGASSERT(dev != NULL && dev->priv != NULL); + priv = (struct xmc4_dev_s *)dev->priv; + + /* Loop until there are no characters to be transferred or, + * until we have been looping for a long time. + */ + + handled = true; + for (passes = 0; passes < 256 && handled; passes++) + { + handled = false; + + /* Read status register 1 */ + + s1 = up_serialin(priv, XMC4_UART_S1_OFFSET); + + /* Handle incoming, receive bytes */ + + /* Check if the receive data register is full (RDRF). NOTE: If + * FIFOS are enabled, this does not mean that the FIFO is full, + * rather, it means that the number of bytes in the RX FIFO has + * exceeded the watermark setting. There may actually be RX data + * available! + * + * The RDRF status indication is cleared when the data is read from + * the RX data register. + */ + +#warning Missing logic + { + /* Process incoming bytes */ + + uart_recvchars(dev); + handled = true; + } + + /* Handle outgoing, transmit bytes */ + + /* Check if the transmit data register is "empty." NOTE: If FIFOS + * are enabled, this does not mean that the FIFO is empty, rather, + * it means that the number of bytes in the TX FIFO is below the + * watermark setting. There could actually be space for additional TX + * data. + * + * The TDRE status indication is cleared when the data is written to + * the TX data register. + */ + +#warning Missing logic + { + /* Process outgoing bytes */ + + uart_xmitchars(dev); + handled = true; + } + } + + return OK; +} + +/**************************************************************************** + * Name: xmc4_ioctl + * + * Description: + * All ioctl calls will be routed through this method + * + ****************************************************************************/ + +static int xmc4_ioctl(struct file *filep, int cmd, unsigned long arg) +{ +#if 0 /* Reserved for future growth */ + struct inode *inode; + struct uart_dev_s *dev; + struct xmc4_dev_s *priv; + int ret = OK; + + DEBUGASSERT(filep, filep->f_inode); + inode = filep->f_inode; + dev = inode->i_private; + + DEBUGASSERT(dev, dev->priv); + priv = (struct xmc4_dev_s *)dev->priv; + + switch (cmd) + { + case xxx: /* Add commands here */ + break; + + default: + ret = -ENOTTY; + break; + } + + return ret; +#else + return -ENOTTY; +#endif +} + +/**************************************************************************** + * Name: xmc4_receive + * + * Description: + * Called (usually) from the interrupt level to receive one + * character from the UART. Error bits associated with the + * receipt are provided in the return 'status'. + * + ****************************************************************************/ + +static int xmc4_receive(struct uart_dev_s *dev, uint32_t *status) +{ + struct xmc4_dev_s *priv = (struct xmc4_dev_s *)dev->priv; + uint8_t s1; + + /* Get error status information: + * + * FE: Framing error. To clear FE, read S1 with FE set and then read + * read UART data register (D). + * NF: Noise flag. To clear NF, read S1 and then read the UART data + * register (D). + * PF: Parity error flag. To clear PF, read S1 and then read the UART + * data register (D). + */ + + s1 = up_serialin(priv, XMC4_UART_S1_OFFSET); + + /* Return status information */ + + if (status) + { + *status = (uint32_t)s1; + } + + /* Then return the actual received byte. Reading S1 then D clears all + * RX errors. + */ + + return (int)up_serialin(priv, XMC4_UART_D_OFFSET); +} + +/**************************************************************************** + * Name: xmc4_rxint + * + * Description: + * Call to enable or disable RX interrupts + * + ****************************************************************************/ + +static void xmc4_rxint(struct uart_dev_s *dev, bool enable) +{ + struct xmc4_dev_s *priv = (struct xmc4_dev_s *)dev->priv; + irqstate_t flags; + + flags = enter_critical_section(); + if (enable) + { + /* Receive an interrupt when their is anything in the Rx data register (or an Rx + * timeout occurs). + */ + +#ifndef CONFIG_SUPPRESS_SERIAL_INTS + priv->ie |= UART_C2_RIE; + up_setuartint(priv); +#endif + } + else + { +#ifdef CONFIG_DEBUG_FEATURES +# warning "Revisit: How are errors enabled?" + priv->ie &= ~UART_C2_RIE; +#else + priv->ie &= ~UART_C2_RIE; +#endif + up_setuartint(priv); + } + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: xmc4_rxavailable + * + * Description: + * Return true if the receive register is not empty + * + ****************************************************************************/ + +static bool xmc4_rxavailable(struct uart_dev_s *dev) +{ + struct xmc4_dev_s *priv = (struct xmc4_dev_s *)dev->priv; + /* Return true if the receive data register is full (RDRF). NOTE: If + * FIFOS are enabled, this does not mean that the FIFO is full, + * rather, it means that the number of bytes in the RX FIFO has + * exceeded the watermark setting. There may actually be RX data + * available! + */ + + return (up_serialin(priv, XMC4_UART_S1_OFFSET) & UART_S1_RDRF) != 0; +} + +/**************************************************************************** + * Name: xmc4_send + * + * Description: + * This method will send one byte on the UART. + * + ****************************************************************************/ + +static void xmc4_send(struct uart_dev_s *dev, int ch) +{ + struct xmc4_dev_s *priv = (struct xmc4_dev_s *)dev->priv; + up_serialout(priv, XMC4_UART_D_OFFSET, (uint8_t)ch); +} + +/**************************************************************************** + * Name: xmc4_txint + * + * Description: + * Call to enable or disable TX interrupts + * + ****************************************************************************/ + +static void xmc4_txint(struct uart_dev_s *dev, bool enable) +{ + struct xmc4_dev_s *priv = (struct xmc4_dev_s *)dev->priv; + irqstate_t flags; + + flags = enter_critical_section(); + if (enable) + { + /* Enable the TX interrupt */ + +#ifndef CONFIG_SUPPRESS_SERIAL_INTS + priv->ie |= UART_C2_TIE; + up_setuartint(priv); + + /* Fake a TX interrupt here by just calling uart_xmitchars() with + * interrupts disabled (note this may recurse). + */ + + uart_xmitchars(dev); +#endif + } + else + { + /* Disable the TX interrupt */ + + priv->ie &= ~UART_C2_TIE; + up_setuartint(priv); + } + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: xmc4_txready + * + * Description: + * Return true if the tranmsit data register is empty + * + ****************************************************************************/ + +static bool xmc4_txready(struct uart_dev_s *dev) +{ + struct xmc4_dev_s *priv = (struct xmc4_dev_s *)dev->priv; + + /* Return true if the transmit data register is "empty." NOTE: If + * FIFOS are enabled, this does not mean that the FIFO is empty, + * rather, it means that the number of bytes in the TX FIFO is + * below the watermark setting. There may actually be space for + * additional TX data. + */ + + return (up_serialin(priv, XMC4_UART_S1_OFFSET) & UART_S1_TDRE) != 0; +} + +/**************************************************************************** + * Name: xmc4_txempty + * + * Description: + * Return true if the tranmsit data register is empty + * + ****************************************************************************/ + +static bool xmc4_txempty(struct uart_dev_s *dev) +{ + struct xmc4_dev_s *priv = (struct xmc4_dev_s *)dev->priv; + + /* Return true if the transmit buffer/fifo is "empty." */ + + return (up_serialin(priv, XMC4_UART_SFIFO_OFFSET) & UART_SFIFO_TXEMPT) != 0; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: xmc4_earlyserialinit + * + * Description: + * Performs the low level UART initialization early in debug so that the + * serial console will be available during bootup. This must be called + * before up_serialinit. NOTE: This function depends on GPIO pin + * configuration performed in up_consoleinit() and main clock iniialization + * performed in up_clkinitialize(). + * + ****************************************************************************/ + +#if defined(USE_EARLYSERIALINIT) +void xmc4_earlyserialinit(void) +{ + /* Disable interrupts from all UARTS. The console is enabled in + * pic32mx_consoleinit() + */ + + up_restoreuartint(TTYS0_DEV.priv, 0); +#ifdef TTYS1_DEV + up_restoreuartint(TTYS1_DEV.priv, 0); +#endif +#ifdef TTYS2_DEV + up_restoreuartint(TTYS2_DEV.priv, 0); +#endif +#ifdef TTYS3_DEV + up_restoreuartint(TTYS3_DEV.priv, 0); +#endif +#ifdef TTYS4_DEV + up_restoreuartint(TTYS4_DEV.priv, 0); +#endif +#ifdef TTYS5_DEV + up_restoreuartint(TTYS5_DEV.priv, 0); +#endif + + /* Configuration whichever one is the console */ + +#ifdef HAVE_UART_CONSOLE + CONSOLE_DEV.isconsole = true; + xmc4_setup(&CONSOLE_DEV); +#endif +} +#endif + +/**************************************************************************** + * Name: up_serialinit + * + * Description: + * Register serial console and serial ports. This assumes + * that up_earlyserialinit was called previously. + * + * Input Parameters: + * None + * + * Returns Value: + * None + * + ****************************************************************************/ + +void up_serialinit(void) +{ + char devname[] = "/dev/ttySx"; + + /* Register the console */ + +#ifdef HAVE_UART_CONSOLE + (void)uart_register("/dev/console", &CONSOLE_DEV); +#endif + + /* Register all UARTs */ + + (void)uart_register("/dev/ttyS0", &TTYS0_DEV); +#ifdef TTYS1_DEV + devname[(sizeof(devname)/sizeof(devname[0]))-2] = '0' + first++; + (void)uart_register("/dev/ttyS1", &TTYS1_DEV); +#endif +#ifdef TTYS2_DEV + devname[(sizeof(devname)/sizeof(devname[0]))-2] = '0' + first++; + (void)uart_register("/dev/ttyS2", &TTYS2_DEV); +#endif +#ifdef TTYS3_DEV + devname[(sizeof(devname)/sizeof(devname[0]))-2] = '0' + first++; + (void)uart_register("/dev/ttyS3", &TTYS3_DEV); +#endif +#ifdef TTYS4_DEV + devname[(sizeof(devname)/sizeof(devname[0]))-2] = '0' + first++; + (void)uart_register("/dev/ttyS4", &TTYS4_DEV); +#endif +#ifdef TTYS5_DEV + devname[(sizeof(devname)/sizeof(devname[0]))-2] = '0' + first++; + (void)uart_register("/dev/ttyS5", &TTYS5_DEV); +#endif + return first; +} + +/**************************************************************************** + * Name: up_putc + * + * Description: + * Provide priority, low-level access to support OS debug writes + * + ****************************************************************************/ + +#ifdef HAVE_UART_PUTC +int up_putc(int ch) +{ +#ifdef HAVE_UART_CONSOLE + struct xmc4_dev_s *priv = (struct xmc4_dev_s *)CONSOLE_DEV.priv; + uint8_t ie; + + up_disableuartint(priv, &ie); + + /* Check for LF */ + + if (ch == '\n') + { + /* Add CR */ + + up_lowputc('\r'); + } + + up_lowputc(ch); + up_restoreuartint(priv, ie); +#endif + return ch; +} +#endif + +#else /* USE_SERIALDRIVER */ + +/**************************************************************************** + * Name: up_putc + * + * Description: + * Provide priority, low-level access to support OS debug writes + * + ****************************************************************************/ + +#ifdef HAVE_UART_PUTC +int up_putc(int ch) +{ +#ifdef HAVE_UART_CONSOLE + /* Check for LF */ + + if (ch == '\n') + { + /* Add CR */ + + up_lowputc('\r'); + } + + up_lowputc(ch); +#endif + return ch; +} +#endif + +#endif /* HAVE_UART_DEVICE && USE_SERIALDRIVER */ + diff --git a/arch/arm/src/xmc4/xmc4_spi.h b/arch/arm/src/xmc4/xmc4_spi.h new file mode 100644 index 00000000000..0ac514c5cee --- /dev/null +++ b/arch/arm/src/xmc4/xmc4_spi.h @@ -0,0 +1,165 @@ +/**************************************************************************** + * arch/arm/src/xmc4/xmc4_spi.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_XMC4_XMC4_SPI_H +#define __ARCH_ARM_SRC_XMC4_XMC4_SPI_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip/xmc4_spi.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +struct spi_dev_s; +enum spi_dev_e; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/************************************************************************************ + * Name: xmc4_spibus_initialize + * + * Description: + * Initialize the selected SPI bus + * + * Input Parameter: + * bus number (for hardware that has mutiple SPI interfaces) + * + * Returned Value: + * Valid SPI device structure reference on succcess; a NULL on failure + * + ************************************************************************************/ + +FAR struct spi_dev_s *xmc4_spibus_initialize(int bus); + +/************************************************************************************ + * Name: xmc4_spi[n]select, xmc4_spi[n]status, and xmc4_spi[n]cmddata + * + * Description: + * These external functions must be provided by board-specific logic. They are + * implementations of the select, status, and cmddata methods of the SPI interface + * defined by struct spi_ops_s (see include/nuttx/spi/spi.h). All other methods + * including xmc4_spibus_initialize()) are provided by common Kinetis logic. To use + * this common SPI logic on your board: + * + * 1. Provide logic in xmc4_board_initialize() to configure SPI chip select + * pins. + * 2. Provide xmc4_spi[n]select() and xmc4_spi[n]status() functions + * in your board-specific logic. These functions will perform chip selection + * and status operations using GPIOs in the way your board is configured. + * 2. If CONFIG_SPI_CMDDATA is defined in the NuttX configuration, provide + * xmc4_spi[n]cmddata() functions in your board-specific logic. These + * functions will perform cmd/data selection operations using GPIOs in the way + * your board is configured. + * 3. Add a call to xmc4_spibus_initialize() in your low level application + * initialization logic + * 4. The handle returned by xmc4_spibus_initialize() may then be used to bind the + * SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ************************************************************************************/ + +#ifdef CONFIG_XMC4_SPI0 +void xmc4_spi0select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected); +uint8_t xmc4_spi0status(FAR struct spi_dev_s *dev, enum spi_dev_e devid); +#ifdef CONFIG_SPI_CMDDATA +int xmc4_spi0cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd); +#endif +#endif +#ifdef CONFIG_XMC4_SPI1 +void xmc4_spi1select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected); +uint8_t xmc4_spi1status(FAR struct spi_dev_s *dev, enum spi_dev_e devid); +#ifdef CONFIG_SPI_CMDDATA +int xmc4_spi1cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd); +#endif +#endif +#ifdef CONFIG_XMC4_SPI2 +void xmc4_spi2select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected); +uint8_t xmc4_spi2status(FAR struct spi_dev_s *dev, enum spi_dev_e devid); +#ifdef CONFIG_SPI_CMDDATA +int xmc4_spi2cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd); +#endif +#endif + +/**************************************************************************** + * Name: ssp_flush + * + * Description: + * Flush and discard any words left in the RX fifo. This can be called + * from spi[n]select after a device is deselected (if you worry about such + * things). + * + * Input Parameters: + * dev - Device-specific state data + * + * Returned Value: + * None + * + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +} +#endif +#if defined(CONFIG_XMC4_SPI0) || defined(CONFIG_XMC4_SPI1) || defined(CONFIG_XMC4_SPI2) +struct spi_dev_s; +void spi_flush(FAR struct spi_dev_s *dev); +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_XMC4_XMC4_SPI_H */ diff --git a/arch/arm/src/xmc4/xmc4_start.c b/arch/arm/src/xmc4/xmc4_start.c new file mode 100644 index 00000000000..e71722e4be5 --- /dev/null +++ b/arch/arm/src/xmc4/xmc4_start.c @@ -0,0 +1,355 @@ +/**************************************************************************** + * arch/arm/src/xmc4/xmc4_start.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "up_arch.h" +#include "up_internal.h" + +#include "xmc4_userspace.h" + +#ifdef CONFIG_ARCH_FPU +# include "nvic.h" +#endif + +/**************************************************************************** + * Private Function prototypes + ****************************************************************************/ + +#ifdef CONFIG_ARCH_FPU +static inline void xmc4_fpu_config(void); +#endif +#ifdef CONFIG_STACK_COLORATION +static void go_os_start(void *pv, unsigned int nbytes) + __attribute__ ((naked, no_instrument_function, noreturn)); +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +/* Memory Map ***************************************************************/ +/* + * 0x0000:0000 - Beginning of the internal FLASH. Address of vectors. + * Mapped as boot memory address 0x0000:0000 at reset. + * 0x07ff:ffff - End of flash region (assuming the max of 2MiB of FLASH). + * 0x1fff:0000 - Start of internal SRAM and start of .data (_sdata) + * - End of .data (_edata) and start of .bss (_sbss) + * - End of .bss (_ebss) and bottom of idle stack + * - _ebss + CONFIG_IDLETHREAD_STACKSIZE = end of idle stack, + * start of heap. NOTE that the ARM uses a decrement before + * store stack so that the correct initial value is the end of + * the stack + 4; + * 0x2002:ffff - End of internal SRAM and end of heap (a + */ + +#define IDLE_STACK ((uintptr_t)&_ebss+CONFIG_IDLETHREAD_STACKSIZE-4) +#define HEAP_BASE ((uintptr_t)&_ebss+CONFIG_IDLETHREAD_STACKSIZE) + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* g_idle_topstack: _sbss is the start of the BSS region as defined by the + * linker script. _ebss lies at the end of the BSS region. The idle task + * stack starts at the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE. + * The IDLE thread is the thread that the system boots on and, eventually, + * becomes the IDLE, do nothing task that runs only when there is nothing + * else to run. The heap continues from there until the end of memory. + * g_idle_topstack is a read-only variable the provides this computed + * address. + */ +#if defined(CONFIG_ARMV7M_CMNVECTOR) +const uintptr_t g_idle_topstack = HEAP_BASE; +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + + +#ifdef CONFIG_ARMV7M_STACKCHECK +/* we need to get r10 set before we can allow instrumentation calls */ + +void __start(void) __attribute__ ((no_instrument_function)); +#endif + +/**************************************************************************** + * Name: xmc4_fpu_config + * + * Description: + * Configure the FPU. Relative bit settings: + * + * CPACR: Enables access to CP10 and CP11 + * CONTROL.FPCA: Determines whether the FP extension is active in the + * current context: + * FPCCR.ASPEN: Enables automatic FP state preservation, then the + * processor sets this bit to 1 on successful completion of any FP + * instruction. + * FPCCR.LSPEN: Enables lazy context save of FP state. When this is + * done, the processor reserves space on the stack for the FP state, + * but does not save that state information to the stack. + * + * Software must not change the value of the ASPEN bit or LSPEN bit while either: + * - the CPACR permits access to CP10 and CP11, that give access to the FP + * extension, or + * - the CONTROL.FPCA bit is set to 1 + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_FPU +#if defined(CONFIG_ARMV7M_CMNVECTOR) && !defined(CONFIG_ARMV7M_LAZYFPU) + +static inline void xmc4_fpu_config(void) +{ + uint32_t regval; + + /* Set CONTROL.FPCA so that we always get the extended context frame + * with the volatile FP registers stacked above the basic context. + */ + + regval = getcontrol(); + regval |= (1 << 2); + setcontrol(regval); + + /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend + * with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we + * are going to turn on CONTROL.FPCA for all contexts. + */ + + regval = getreg32(NVIC_FPCCR); + regval &= ~((1 << 31) | (1 << 30)); + putreg32(regval, NVIC_FPCCR); + + /* Enable full access to CP10 and CP11 */ + + regval = getreg32(NVIC_CPACR); + regval |= ((3 << (2*10)) | (3 << (2*11))); + putreg32(regval, NVIC_CPACR); +} + +#else + +static inline void xmc4_fpu_config(void) +{ + uint32_t regval; + + /* Clear CONTROL.FPCA so that we do not get the extended context frame + * with the volatile FP registers stacked in the saved context. + */ + + regval = getcontrol(); + regval &= ~(1 << 2); + setcontrol(regval); + + /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend + * with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we + * are going to keep CONTROL.FPCA off for all contexts. + */ + + regval = getreg32(NVIC_FPCCR); + regval &= ~((1 << 31) | (1 << 30)); + putreg32(regval, NVIC_FPCCR); + + /* Enable full access to CP10 and CP11 */ + + regval = getreg32(NVIC_CPACR); + regval |= ((3 << (2*10)) | (3 << (2*11))); + putreg32(regval, NVIC_CPACR); +} + +#endif + +#else +# define xmc4_fpu_config() +#endif + +/**************************************************************************** + * Name: go_os_start + * + * Description: + * Set the IDLE stack to the + * + ****************************************************************************/ + +#ifdef CONFIG_STACK_COLORATION +static void go_os_start(void *pv, unsigned int nbytes) +{ + /* Set the IDLE stack to the stack coloration value then jump to + * os_start(). We take extreme care here because were currently + * executing on this stack. + * + * We want to avoid sneak stack access generated by the compiler. + */ + + __asm__ __volatile__ + ( + "\tmovs r1, r1, lsr #2\n" /* R1 = nwords = nbytes >> 2 */ + "\tbeq 2f\n" /* (should not happen) */ + + "\tbic r0, r0, #3\n" /* R0 = Aligned stackptr */ + "\tmovw r2, #0xbeef\n" /* R2 = STACK_COLOR = 0xdeadbeef */ + "\tmovt r2, #0xdead\n" + + "1:\n" /* Top of the loop */ + "\tsub r1, r1, #1\n" /* R1 nwords-- */ + "\tcmp r1, #0\n" /* Check (nwords == 0) */ + "\tstr r2, [r0], #4\n" /* Save stack color word, increment stackptr */ + "\tbne 1b\n" /* Bottom of the loop */ + + "2:\n" + "\tmov r14, #0\n" /* LR = return address (none) */ + "\tb os_start\n" /* Branch to os_start */ + ); +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: _start + * + * Description: + * This is the reset entry point. + * + ****************************************************************************/ + +void __start(void) +{ + const uint32_t *src; + uint32_t *dest; + +#ifdef CONFIG_ARMV7M_STACKCHECK + /* Set the stack limit before we attempt to call any functions */ + + __asm__ volatile ("sub r10, sp, %0" : : "r" (CONFIG_IDLETHREAD_STACKSIZE - 64) : ); +#endif + + /* Disable the watchdog timer */ + + kinetis_wddisable(); + + /* Clear .bss. We'll do this inline (vs. calling memset) just to be + * certain that there are no issues with the state of global variables. + */ + + for (dest = &_sbss; dest < &_ebss; ) + { + *dest++ = 0; + } + + /* Move the initialized data section from his temporary holding spot in + * FLASH into the correct place in SRAM. The correct place in SRAM is + * give by _sdata and _edata. The temporary location is in FLASH at the + * end of all of the other read-only data (.text, .rodata) at _eronly. + */ + + for (src = &_eronly, dest = &_sdata; dest < &_edata; ) + { + *dest++ = *src++; + } + + /* Copy any necessary code sections from FLASH to RAM. The correct + * destination in SRAM is given by _sramfuncs and _eramfuncs. The + * temporary location is in flash after the data initialization code + * at _framfuncs + */ + +#ifdef CONFIG_ARCH_RAMFUNCS + for (src = &_framfuncs, dest = &_sramfuncs; dest < &_eramfuncs; ) + { + *dest++ = *src++; + } +#endif + + /* Perform clock and Kinetis module initialization (This depends on + * RAM functions having been copied to RAM). + */ + + xmc4_clock_config(); + + /* Configure the uart and perform early serial initialization so that we + * can get debug output as soon as possible (This depends on clock + * configuration). + */ + + xmc4_fpu_config(); + xmc4_lowsetup(); +#ifdef USE_EARLYSERIALINIT + xmc4_earlyserialinit(); +#endif + + /* For the case of the separate user-/kernel-space build, perform whatever + * platform specific initialization of the user memory is required. + * Normally this just means initializing the user space .data and .bss + * segments. + */ + +#ifdef CONFIG_BUILD_PROTECTED + xmc4_userspace(); +#endif + + /* Initialize other on-board resources */ + + xmc4_board_initialize(); + + /* Then start NuttX */ + + os_start(); + + /* Shouldn't get here */ + + for (; ; ); +} diff --git a/arch/arm/src/xmc4/xmc4_timerisr.c b/arch/arm/src/xmc4/xmc4_timerisr.c new file mode 100644 index 00000000000..ba9e98596c8 --- /dev/null +++ b/arch/arm/src/xmc4/xmc4_timerisr.c @@ -0,0 +1,152 @@ +/**************************************************************************** + * arch/arm/src/xmc4/xmc4_timerisr.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "nvic.h" +#include "clock/clock.h" +#include "up_internal.h" +#include "up_arch.h" + +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* The desired timer interrupt frequency is provided by the definition + * CLK_TCK (see include/time.h). CLK_TCK defines the desired number of + * system clock ticks per second. That value is a user configurable setting + * that defaults to 100 (100 ticks per second = 10 MS interval). + * + * The Clock Source: The System Tick Timer's clock source is always the core + * clock + */ + +#define SYSTICK_RELOAD ((BOARD_CORECLK_FREQ / CLK_TCK) - 1) + +/* The size of the reload field is 24 bits. Verify that the reload value + * will fit in the reload register. + */ + +#if SYSTICK_RELOAD > 0x00ffffff +# error SYSTICK_RELOAD exceeds the range of the RELOAD register +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: xmc4_timerisr + * + * Description: + * The timer ISR will perform a variety of services for various portions + * of the systems. + * + ****************************************************************************/ + +static int xmc4_timerisr(int irq, uint32_t *regs, FAR void *arg) +{ + /* Process timer interrupt */ + + sched_process_timer(); + return 0; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: arm_timer_initialize + * + * Description: + * This function is called during start-up to initialize + * the timer interrupt. + * + ****************************************************************************/ + +void arm_timer_initialize(void) +{ + uint32_t regval; + + /* Set the SysTick interrupt to the default priority */ + + regval = getreg32(NVIC_SYSH12_15_PRIORITY); + regval &= ~NVIC_SYSH_PRIORITY_PR15_MASK; + regval |= (NVIC_SYSH_PRIORITY_DEFAULT << NVIC_SYSH_PRIORITY_PR15_SHIFT); + putreg32(regval, NVIC_SYSH12_15_PRIORITY); + + /* Note that is should not be neccesary to set the SYSTICK clock source: + * "The CLKSOURCE bit in SysTick Control and Status register is always set + * to select the core clock." + */ + +#if 0 + regval = getreg32(NVIC_SYSTICK_CTRL); + regval |= NVIC_SYSTICK_CTRL_CLKSOURCE; + putreg32(regval, NVIC_SYSTICK_CTRL); +#endif + + /* Configure SysTick to interrupt at the requested rate */ + + putreg32(SYSTICK_RELOAD, NVIC_SYSTICK_RELOAD); + + /* Attach the timer interrupt vector */ + + (void)irq_attach(XMC4_IRQ_SYSTICK, (xcpt_t)xmc4_timerisr, NULL); + + /* Enable SysTick interrupts */ + + putreg32((NVIC_SYSTICK_CTRL_CLKSOURCE | NVIC_SYSTICK_CTRL_TICKINT | + NVIC_SYSTICK_CTRL_ENABLE), + NVIC_SYSTICK_CTRL); + + /* And enable the timer interrupt */ + + up_enable_irq(XMC4_IRQ_SYSTICK); +} diff --git a/arch/arm/src/xmc4/xmc4_userspace.c b/arch/arm/src/xmc4/xmc4_userspace.c new file mode 100644 index 00000000000..02dc2d2303a --- /dev/null +++ b/arch/arm/src/xmc4/xmc4_userspace.c @@ -0,0 +1,107 @@ +/**************************************************************************** + * arch/arm/src/xmc4/xmc4_userspace.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#include "xmc4_mpuinit.h" +#include "xmc4_userspace.h" + +#ifdef CONFIG_BUILD_PROTECTED + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: xmc4_userspace + * + * Description: + * For the case of the separate user-/kernel-space build, perform whatever + * platform specific initialization of the user memory is required. + * Normally this just means initializing the user space .data and .bss + * segments. + * + ****************************************************************************/ + +void xmc4_userspace(void) +{ + uint8_t *src; + uint8_t *dest; + uint8_t *end; + + /* Clear all of user-space .bss */ + + DEBUGASSERT(USERSPACE->us_bssstart != 0 && USERSPACE->us_bssend != 0 && + USERSPACE->us_bssstart <= USERSPACE->us_bssend); + + dest = (uint8_t *)USERSPACE->us_bssstart; + end = (uint8_t *)USERSPACE->us_bssend; + + while (dest != end) + { + *dest++ = 0; + } + + /* Initialize all of user-space .data */ + + DEBUGASSERT(USERSPACE->us_datasource != 0 && + USERSPACE->us_datastart != 0 && USERSPACE->us_dataend != 0 && + USERSPACE->us_datastart <= USERSPACE->us_dataend); + + src = (uint8_t *)USERSPACE->us_datasource; + dest = (uint8_t *)USERSPACE->us_datastart; + end = (uint8_t *)USERSPACE->us_dataend; + + while (dest != end) + { + *dest++ = *src++; + } + + /* Configure the MPU to permit user-space access to its FLASH and RAM */ + + xmc4_mpuinitialize(); +} + +#endif /* CONFIG_BUILD_PROTECTED */ + diff --git a/arch/arm/src/xmc4/xmc4_userspace.h b/arch/arm/src/xmc4/xmc4_userspace.h new file mode 100644 index 00000000000..661982c8f90 --- /dev/null +++ b/arch/arm/src/xmc4/xmc4_userspace.h @@ -0,0 +1,64 @@ +/************************************************************************************ + * arch/arm/src/xmc4/xmc4_userspace.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_XMC4_XMC4_USERSPACE_H +#define __ARCH_ARM_SRC_XMC4_XMC4_USERSPACE_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/**************************************************************************** + * Name: xmc4_userspace + * + * Description: + * For the case of the separate user-/kernel-space build, perform whatever + * platform specific initialization of the user memory is required. + * Normally this just means initializing the user space .data and .bss + * segments. + * + ****************************************************************************/ + +#ifdef CONFIG_BUILD_PROTECTED +void xmc4_userspace(void); +#endif + +#endif /* __ARCH_ARM_SRC_XMC4_XMC4_USERSPACE_H */ From 2430049e3b5496c91f70ccfaa306c9b0f5878abe Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 14 Mar 2017 13:04:09 -0600 Subject: [PATCH 03/81] arch/arm/include/xmc4: More support for Infineon XMC4xxx arch. Still incomplete. --- arch/arm/include/xmc4/chip.h | 130 ++++++++++++++++ arch/arm/include/xmc4/irq.h | 120 +++++++++++++++ arch/arm/include/xmc4/xmc4500_irq.h | 225 ++++++++++++++++++++++++++++ 3 files changed, 475 insertions(+) create mode 100644 arch/arm/include/xmc4/chip.h create mode 100644 arch/arm/include/xmc4/irq.h create mode 100644 arch/arm/include/xmc4/xmc4500_irq.h diff --git a/arch/arm/include/xmc4/chip.h b/arch/arm/include/xmc4/chip.h new file mode 100644 index 00000000000..7ea5157a736 --- /dev/null +++ b/arch/arm/include/xmc4/chip.h @@ -0,0 +1,130 @@ +/************************************************************************************ + * arch/arm/include/xmc4/chip.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_XM4_CHIP_H +#define __ARCH_ARM_INCLUDE_XM4_CHIP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Get customizations for each supported chip */ + +#if defined(CONFIG_ARCH_XMC4500) +# define XM4_NUSIC 3 /* Three USIC modules: USCI0-2 */ + +#else +# error "Unsupported XMC4000 chip" +#endif + +/* NVIC priority levels *************************************************************/ +/* Each priority field holds a priority value, 0-15. The lower the value, the greater + * the priority of the corresponding interrupt. The XMC4500 implements only + * bits[7:2] of this field, bits[1:0] read as zero and ignore writes. + */ + +#define NVIC_SYSH_PRIORITY_MIN 0xfc /* All bits[7:2] set is minimum priority */ +#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ +#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ +#define NVIC_SYSH_PRIORITY_STEP 0x04 /* Steps between supported priority values */ + +/* If CONFIG_ARMV7M_USEBASEPRI is selected, then interrupts will be disabled + * by setting the BASEPRI register to NVIC_SYSH_DISABLE_PRIORITY so that most + * interrupts will not have execution priority. SVCall must have execution + * priority in all cases. + * + * In the normal cases, interrupts are not nest-able and all interrupts run + * at an execution priority between NVIC_SYSH_PRIORITY_MIN and + * NVIC_SYSH_PRIORITY_MAX (with NVIC_SYSH_PRIORITY_MAX reserved for SVCall). + * + * If, in addition, CONFIG_ARCH_HIPRI_INTERRUPT is defined, then special + * high priority interrupts are supported. These are not "nested" in the + * normal sense of the word. These high priority interrupts can interrupt + * normal processing but execute outside of OS (although they can "get back + * into the game" via a PendSV interrupt). + * + * In the normal course of things, interrupts must occasionally be disabled + * using the up_irq_save() inline function to prevent contention in use of + * resources that may be shared between interrupt level and non-interrupt + * level logic. Now the question arises, if CONFIG_ARCH_HIPRI_INTERRUPT, + * do we disable all interrupts (except SVCall), or do we only disable the + * "normal" interrupts. Since the high priority interrupts cannot interact + * with the OS, you may want to permit the high priority interrupts even if + * interrupts are disabled. The setting CONFIG_ARCH_INT_DISABLEALL can be + * used to select either behavior: + * + * ----------------------------+--------------+---------------------------- + * CONFIG_ARCH_HIPRI_INTERRUPT | NO | YES + * ----------------------------+--------------+--------------+------------- + * CONFIG_ARCH_INT_DISABLEALL | N/A | YES | NO + * ----------------------------+--------------+--------------+------------- + * | | | SVCall + * | SVCall | SVCall | HIGH + * Disable here and below --------> MAXNORMAL ---> HIGH --------> MAXNORMAL + * | | MAXNORMAL | + * ----------------------------+--------------+--------------+------------- + */ + +#if defined(CONFIG_ARCH_HIPRI_INTERRUPT) && defined(CONFIG_ARCH_INT_DISABLEALL) +# define NVIC_SYSH_MAXNORMAL_PRIORITY (NVIC_SYSH_PRIORITY_MAX + 2*NVIC_SYSH_PRIORITY_STEP) +# define NVIC_SYSH_HIGH_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP) +# define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_HIGH_PRIORITY +# define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX +#else +# define NVIC_SYSH_MAXNORMAL_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP) +# define NVIC_SYSH_HIGH_PRIORITY NVIC_SYSH_PRIORITY_MAX +# define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_MAXNORMAL_PRIORITY +# define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX +#endif + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_INCLUDE_XM4_CHIP_H */ diff --git a/arch/arm/include/xmc4/irq.h b/arch/arm/include/xmc4/irq.h new file mode 100644 index 00000000000..65300dcee3b --- /dev/null +++ b/arch/arm/include/xmc4/irq.h @@ -0,0 +1,120 @@ +/**************************************************************************** + * arch/arm/include/xmc4/irq.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* This file should never be included directed but, rather, only indirectly + * through nuttx/irq.h + */ + +#ifndef __ARCH_ARM_INCLUDE_XM4_IRQ_H +#define __ARCH_ARM_INCLUDE_XM4_IRQ_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* IRQ numbers. The IRQ number corresponds vector number and hence map directly to + * bits in the NVIC. This does, however, waste several words of memory in the IRQ + * to handle mapping tables. + */ + +/* Processor Exceptions (vectors 0-15) */ + +#define XM4_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ + /* Vector 0: Reset stack pointer value */ + /* Vector 1: Reset (not handler as an IRQ) */ +#define XM4_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ +#define XM4_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ +#define XM4_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ +#define XM4_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ +#define XM4_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ + /* Vectors 7-10: Reserved */ +#define XM4_IRQ_SVCALL (11) /* Vector 11: SVC call */ +#define XM4_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */ + /* Vector 13: Reserved */ +#define XM4_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ +#define XM4_IRQ_SYSTICK (15) /* Vector 15: System tick */ + +/* External interrupts (vectors >= 16). These definitions are chip-specific */ + +#define XM4_IRQ_FIRST (16) /* Vector number of the first external interrupt */ + +#if defined(CONFIG_ARCH_XMC4500) +# include +#else + /* The interrupt vectors for other parts are defined in other documents and may or + * may not be the same as above (the family members are all very similar) This + * error just means that you have to look at the document and determine for yourself + * if the vectors are the same. + */ + +# error "No IRQ numbers for this XMC4xxx part" +#endif + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#undef EXTERN +#ifdef __cplusplus +} +#endif +#endif + +#endif /* __ARCH_ARM_INCLUDE_XM4_IRQ_H */ + diff --git a/arch/arm/include/xmc4/xmc4500_irq.h b/arch/arm/include/xmc4/xmc4500_irq.h new file mode 100644 index 00000000000..1005adeb495 --- /dev/null +++ b/arch/arm/include/xmc4/xmc4500_irq.h @@ -0,0 +1,225 @@ +/***************************************************************************** + * arch/arm/include/xmc4/xmc4500_.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* This file should never be included directed but, rather, only indirectly + * through nuttx/irq.h + */ + +#ifndef xmc4__ARCH_ARM_INCLUDE_XM4_XM4500_IRQ_H +#define xmc4__ARCH_ARM_INCLUDE_XM4_XM4500_IRQ_H + +/***************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/***************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* IRQ numbers. The IRQ number corresponds vector number and hence map + * directly to bits in the NVIC. This does, however, waste several words of + * memory in the IRQ to handle mapping tables. + * + * Processor Exceptions (vectors 0-15). These common definitions can be found + * in the file nuttx/arch/arm/include/kinets/irq.h which includes this file + * + * External interrupts (vectors >= 16) + * + * Acronyms: + * ADC - Analog to Digital Converter + * CCU - Capture Compare Unit + * DAC - Digital to Analog Converter + * DSD - Delta Sigmoid Demodulator + * ERU - External Request Unit + * FCE - Flexible CRC Engine + * GPDMA - General Purpose DMA + * LEDTS - LED and Touch Sense Control Unit + * PMU - Program Management Unit + * POSIF - Position Interface + * SDMMC - Multi Media Card Interface + * USB - Universal Serial Bus + * USCI - Universal Serial Interface + */ + +#define XM4_IRQ_SCU (XM4_IRQ_FIRST+0) /* 0: System Control */ +#define XM4_IRQ_ERU0_SR0 (XM4_IRQ_FIRST+1) /* 1: ERU0, SR0 */ +#define XM4_IRQ_ERU0_SR1 (XM4_IRQ_FIRST+2) /* 2: ERU0, SR1 */ +#define XM4_IRQ_ERU0_SR2 (XM4_IRQ_FIRST+3) /* 3: ERU0, SR2 */ +#define XM4_IRQ_ERU0_SR3 (XM4_IRQ_FIRST+4) /* 4: ERU0, SR3 */ +#define XM4_IRQ_ERU1_SR0 (XM4_IRQ_FIRST+5) /* 5: ERU1, SR0 */ +#define XM4_IRQ_ERU1_SR1 (XM4_IRQ_FIRST+6) /* 6: ERU1, SR1 */ +#define XM4_IRQ_ERU1_SR2 (XM4_IRQ_FIRST+7) /* 7: ERU1, SR2 */ +#define XM4_IRQ_ERU1_SR3 (XM4_IRQ_FIRST+8) /* 8: ERU1, SR3 */ +#define XM4_IRQ_RESVD009 (XM4_IRQ_FIRST+9) /* 9: Reserved */ +#define XM4_IRQ_RESVD010 (XM4_IRQ_FIRST+10) /* 10: Reserved */ +#define XM4_IRQ_RESVD011 (XM4_IRQ_FIRST+11) /* 11: Reserved */ +#define XM4_IRQ_PMU1_SR0 (XM4_IRQ_FIRST+12) /* 12: PMU, SR0 */ +#define XM4_IRQ_RESVD011 (XM4_IRQ_FIRST+13) /* 13: Reserved */ +#define XM4_IRQ_VADC_COSR0 (XM4_IRQ_FIRST+14) /* 14: ADC Common Block 0 */ +#define XM4_IRQ_VADC_COSR1 (XM4_IRQ_FIRST+15) /* 15: ADC Common Block 1 */ +#define XM4_IRQ_VADC_COSR2 (XM4_IRQ_FIRST+16) /* 16: ADC Common Block 2 */ +#define XM4_IRQ_VADC_COSR3 (XM4_IRQ_FIRST+17) /* 17: ADC Common Block 3 */ +#define XM4_IRQ_VADC_GOSR0 (XM4_IRQ_FIRST+18) /* 18: ADC Group 0, SR0 */ +#define XM4_IRQ_VADC_GOSR1 (XM4_IRQ_FIRST+19) /* 19: ADC Group 0, SR1 */ +#define XM4_IRQ_VADC_GOSR2 (XM4_IRQ_FIRST+20) /* 20: ADC Group 0, SR2 */ +#define XM4_IRQ_VADC_GOSR3 (XM4_IRQ_FIRST+21) /* 21: ADC Group 0, SR3 */ +#define XM4_IRQ_VADC_G1SR0 (XM4_IRQ_FIRST+22) /* 22: ADC Group 1, SR0 */ +#define XM4_IRQ_VADC_G1SR1 (XM4_IRQ_FIRST+23) /* 23: ADC Group 1, SR1 */ +#define XM4_IRQ_VADC_G1SR2 (XM4_IRQ_FIRST+24) /* 24: ADC Group 1, SR2 */ +#define XM4_IRQ_VADC_G1SR3 (XM4_IRQ_FIRST+25) /* 25: ADC Group 1, SR3 */ +#define XM4_IRQ_VADC_G2SR0 (XM4_IRQ_FIRST+26) /* 26: ADC Group 2, SR0 */ +#define XM4_IRQ_VADC_G2SR1 (XM4_IRQ_FIRST+27) /* 27: ADC Group 2, SR1 */ +#define XM4_IRQ_VADC_G2SR2 (XM4_IRQ_FIRST+28) /* 28: ADC Group 2, SR2 */ +#define XM4_IRQ_VADC_G2SR3 (XM4_IRQ_FIRST+29) /* 29: ADC Group 2, SR3 */ +#define XM4_IRQ_VADC_G3SR0 (XM4_IRQ_FIRST+30) /* 30: ADC Group 3, SR0 */ +#define XM4_IRQ_VADC_G3SR1 (XM4_IRQ_FIRST+31) /* 31: ADC Group 3, SR1 */ +#define XM4_IRQ_VADC_G3SR2 (XM4_IRQ_FIRST+32) /* 32: ADC Group 3, SR2 */ +#define XM4_IRQ_VADC_G3SR3 (XM4_IRQ_FIRST+33) /* 33: ADC Group 3, SR3 */ +#define XM4_IRQ_DSD_SRM0 (XM4_IRQ_FIRST+34) /* 34: DSD Main, SRM0 */ +#define XM4_IRQ_DSD_SRM1 (XM4_IRQ_FIRST+35) /* 35: DSD Main, SRM1 */ +#define XM4_IRQ_DSD_SRM2 (XM4_IRQ_FIRST+36) /* 36: DSD Main, SRM2 */ +#define XM4_IRQ_DSD_SRM3 (XM4_IRQ_FIRST+37) /* 37: DSD Main, SRM3 */ +#define XM4_IRQ_DSD_SRA0 (XM4_IRQ_FIRST+38) /* 38: DSD Auxiliary, SRA0 */ +#define XM4_IRQ_DSD_SRA1 (XM4_IRQ_FIRST+39) /* 39: DSD Auxiliary, SRA1 */ +#define XM4_IRQ_DSD_SRA2 (XM4_IRQ_FIRST+40) /* 40: DSD Auxiliary, SRA2 */ +#define XM4_IRQ_DSD_SRA3 (XM4_IRQ_FIRST+41) /* 41: DSD Auxiliary, SRA3 */ +#define XM4_IRQ_DAC_SR0 (XM4_IRQ_FIRST+42) /* 42: DAC, SR0 */ +#define XM4_IRQ_DAC_SR1 (XM4_IRQ_FIRST+43) /* 43: DAC, SR1 */ +#define XM4_IRQ_CCU40_SR0 (XM4_IRQ_FIRST+44) /* 44: CCU4 Module 0, SR0 */ +#define XM4_IRQ_CCU40_SR1 (XM4_IRQ_FIRST+45) /* 45: CCU4 Module 0, SR1 */ +#define XM4_IRQ_CCU40_SR2 (XM4_IRQ_FIRST+46) /* 46: CCU4 Module 0, SR2 */ +#define XM4_IRQ_CCU40_SR3 (XM4_IRQ_FIRST+47) /* 47: CCU4 Module 0, SR3 */ +#define XM4_IRQ_CCU41_SR0 (XM4_IRQ_FIRST+48) /* 48: CCU4 Module 1, SR0 */ +#define XM4_IRQ_CCU41_SR1 (XM4_IRQ_FIRST+49) /* 49: CCU4 Module 1, SR1 */ +#define XM4_IRQ_CCU41_SR2 (XM4_IRQ_FIRST+50) /* 50: CCU4 Module 1, SR2 */ +#define XM4_IRQ_CCU41_SR3 (XM4_IRQ_FIRST+51) /* 51: CCU4 Module 1, SR3 */ +#define XM4_IRQ_CCU42_SR0 (XM4_IRQ_FIRST+52) /* 52: CCU4 Module 2, SR0 */ +#define XM4_IRQ_CCU42_SR1 (XM4_IRQ_FIRST+53) /* 53: CCU4 Module 2, SR1 */ +#define XM4_IRQ_CCU42_SR2 (XM4_IRQ_FIRST+54) /* 54: CCU4 Module 2, SR2 */ +#define XM4_IRQ_CCU42_SR3 (XM4_IRQ_FIRST+55) /* 55: CCU4 Module 2, SR3 */ +#define XM4_IRQ_CCU43_SR0 (XM4_IRQ_FIRST+56) /* 56: CCU4 Module 3, SR0 */ +#define XM4_IRQ_CCU43_SR1 (XM4_IRQ_FIRST+57) /* 57: CCU4 Module 3, SR1 */ +#define XM4_IRQ_CCU43_SR2 (XM4_IRQ_FIRST+58) /* 58: CCU4 Module 3, SR2 */ +#define XM4_IRQ_CCU43_SR3 (XM4_IRQ_FIRST+59) /* 59: CCU4 Module 3, SR3 */ +#define XM4_IRQ_CCU80_SR0 (XM4_IRQ_FIRST+60) /* 60: CCU8 Module 0, SR0 */ +#define XM4_IRQ_CCU80_SR1 (XM4_IRQ_FIRST+61) /* 61: CCU8 Module 0, SR1 */ +#define XM4_IRQ_CCU80_SR2 (XM4_IRQ_FIRST+62) /* 62: CCU8 Module 0, SR2 */ +#define XM4_IRQ_CCU80_SR3 (XM4_IRQ_FIRST+63) /* 63: CCU8 Module 0, SR3 */ +#define XM4_IRQ_CCU81_SR0 (XM4_IRQ_FIRST+64) /* 64: CCU8 Module 1, SR0 */ +#define XM4_IRQ_CCU81_SR1 (XM4_IRQ_FIRST+65) /* 65: CCU8 Module 1, SR1 */ +#define XM4_IRQ_CCU81_SR2 (XM4_IRQ_FIRST+66) /* 66: CCU8 Module 1, SR2 */ +#define XM4_IRQ_CCU81_SR3 (XM4_IRQ_FIRST+67) /* 67: CCU8 Module 1, SR3 */ +#define XM4_IRQ_POSIF0_SR0 (XM4_IRQ_FIRST+68) /* 68: POSIF Module 0, SR0 */ +#define XM4_IRQ_POSIF0_SR1 (XM4_IRQ_FIRST+69) /* 69: POSIF Module 0, SR1 */ +#define XM4_IRQ_POSIF1_SR0 (XM4_IRQ_FIRST+70) /* 70: POSIF Module 1, SR0 */ +#define XM4_IRQ_POSIF1_SR1 (XM4_IRQ_FIRST+71) /* 71: POSIF Module 1, SR1 */ +#define XM4_IRQ_RESVD072 (XM4_IRQ_FIRST+72) /* 72: Reserved */ +#define XM4_IRQ_RESVD073 (XM4_IRQ_FIRST+73) /* 73: Reserved */ +#define XM4_IRQ_RESVD074 (XM4_IRQ_FIRST+74) /* 74: Reserved */ +#define XM4_IRQ_RESVD075 (XM4_IRQ_FIRST+75) /* 75: Reserved */ +#define XM4_IRQ_CAN_SR0 (XM4_IRQ_FIRST+76) /* 76: MultiCAN, SR0 */ +#define XM4_IRQ_CAN_SR1 (XM4_IRQ_FIRST+77) /* 77: MultiCAN, SR1 */ +#define XM4_IRQ_CAN_SR2 (XM4_IRQ_FIRST+78) /* 78: MultiCAN, SR2 */ +#define XM4_IRQ_CAN_SR3 (XM4_IRQ_FIRST+79) /* 79: MultiCAN, SR3 */ +#define XM4_IRQ_CAN_SR4 (XM4_IRQ_FIRST+80) /* 80: MultiCAN, SR4 */ +#define XM4_IRQ_CAN_SR5 (XM4_IRQ_FIRST+81) /* 81: MultiCAN, SR5 */ +#define XM4_IRQ_CAN_SR6 (XM4_IRQ_FIRST+82) /* 82: MultiCAN, SR6 */ +#define XM4_IRQ_CAN_SR7 (XM4_IRQ_FIRST+83) /* 83: MultiCAN, SR7 */ +#define XM4_IRQ_USIC0_SR0 (XM4_IRQ_FIRST+84) /* 84: USIC0 Channel, SR0 */ +#define XM4_IRQ_USIC0_SR1 (XM4_IRQ_FIRST+85) /* 85: USIC0 Channel, SR1 */ +#define XM4_IRQ_USIC0_SR2 (XM4_IRQ_FIRST+86) /* 86: USIC0 Channel, SR2 */ +#define XM4_IRQ_USIC0_SR3 (XM4_IRQ_FIRST+87) /* 87: USIC0 Channel, SR3 */ +#define XM4_IRQ_USIC0_SR4 (XM4_IRQ_FIRST+88) /* 88: USIC0 Channel, SR4 */ +#define XM4_IRQ_USIC0_SR5 (XM4_IRQ_FIRST+89) /* 89: USIC0 Channel, SR5 */ +#define XM4_IRQ_USIC1_SR0 (XM4_IRQ_FIRST+90) /* 90: USIC1 Channel, SR0 */ +#define XM4_IRQ_USIC1_SR1 (XM4_IRQ_FIRST+91) /* 91: USIC1 Channel, SR1 */ +#define XM4_IRQ_USIC1_SR2 (XM4_IRQ_FIRST+92) /* 92: USIC1 Channel, SR2 */ +#define XM4_IRQ_USIC1_SR3 (XM4_IRQ_FIRST+93) /* 93: USIC1 Channel, SR3 */ +#define XM4_IRQ_USIC1_SR4 (XM4_IRQ_FIRST+94) /* 94: USIC1 Channel, SR4 */ +#define XM4_IRQ_USIC1_SR5 (XM4_IRQ_FIRST+95) /* 95: USIC1 Channel, SR5 */ +#define XM4_IRQ_USIC2_SR0 (XM4_IRQ_FIRST+96) /* 96: USIC1 Channel, SR0 */ +#define XM4_IRQ_USIC2_SR1 (XM4_IRQ_FIRST+97) /* 97: USIC1 Channel, SR1 */ +#define XM4_IRQ_USIC2_SR2 (XM4_IRQ_FIRST+98) /* 98: USIC1 Channel, SR2 */ +#define XM4_IRQ_USIC2_SR3 (XM4_IRQ_FIRST+99) /* 99: USIC1 Channel, SR3 */ +#define XM4_IRQ_USIC2_SR4 (XM4_IRQ_FIRST+100) /* 100: USIC1 Channel, SR4 */ +#define XM4_IRQ_USIC2_SR5 (XM4_IRQ_FIRST+101) /* 101: USIC1 Channel, SR5 */ +#define XM4_IRQ_LEDTS0_SR0 (XM4_IRQ_FIRST+102) /* 102: LEDTS0, SR0 */ +#define XM4_IRQ_RESVD103 (XM4_IRQ_FIRST+103) /* 103: Reserved */ +#define XM4_IRQ_FCR_SR0 (XM4_IRQ_FIRST+104) /* 102: FCE, SR0 */ +#define XM4_IRQ_GPCMA0_SR0 (XM4_IRQ_FIRST+105) /* 105: GPDMA0, SR0 */ +#define XM4_IRQ_SDMMC_SR0 (XM4_IRQ_FIRST+106) /* 106: SDMMC, SR0 */ +#define XM4_IRQ_USB0_SR0 (XM4_IRQ_FIRST+107) /* 107: USB, SR0 */ +#define XM4_IRQ_ETH0_SR0 (XM4_IRQ_FIRST+108) /* 108: Ethernet, module 0, SR0 */ +#define XM4_IRQ_RESVD109 (XM4_IRQ_FIRST+109) /* 109: Reserved */ +#define XM4_IRQ_GPCMA1_SR0 (XM4_IRQ_FIRST+110) /* 110: GPDMA1, SR0 */ +#define XM4_IRQ_RESVD111 (XM4_IRQ_FIRST+111) /* 111: Reserved */ + +#define NR_INTERRUPTS 112 /* 112 Non core IRQs*/ +#define NR_VECTORS (XM4_IRQ_FIRST+NR_INTERRUPTS) /* 118 vectors */ + +/* GPIO IRQ interrupts -- To be provided */ + +#define NR_IRQS NR_VECTORS + +/***************************************************************************** + * Public Types + ****************************************************************************/ + +/***************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/***************************************************************************** + * Public Functions + ****************************************************************************/ + +#undef EXTERN +#ifdef __cplusplus +} +#endif +#endif + +#endif /* xmc4__ARCH_ARM_INCLUDE_XM4_XM4500_IRQ_H */ From a635e7df7a94c0ff187921c16c5aec568e86e6fa Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 14 Mar 2017 16:19:30 -0600 Subject: [PATCH 04/81] XMC4xxx: Add SCU header file. --- arch/arm/src/xmc4/chip/xmc4_scu.h | 453 ++++++++++++++++++++++++++++++ 1 file changed, 453 insertions(+) create mode 100644 arch/arm/src/xmc4/chip/xmc4_scu.h diff --git a/arch/arm/src/xmc4/chip/xmc4_scu.h b/arch/arm/src/xmc4/chip/xmc4_scu.h new file mode 100644 index 00000000000..a3e6d116e73 --- /dev/null +++ b/arch/arm/src/xmc4/chip/xmc4_scu.h @@ -0,0 +1,453 @@ +/************************************************************************************ + * arch/arm/src/xmc4/chip/xmc4_scu.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_XMC4_CHIP_XMC4_SCU_H +#define __ARCH_ARM_SRC_XMC4_CHIP_XMC4_SCU_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include "chip/xmc4_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register Offsets *****************************************************************/ + +#define XMC4_GCU_OFFSET 0x0000 /* Offset address of General Control Unit */ +#define XMC4_PCU_OFFSET 0x0200 /* Offset address of Power Control Unit */ +#define XMC4_HCU_OFFSET 0x0300 /* Offset address of Hibernate Control Unit */ +#define XMC4_RCU_OFFSET 0x0400 /* Offset address of Reset Control Unit */ +#define XMC4_CCU_OFFSET 0x0600 /* Offset address of Clock Control Unit */ + +/* General SCU Registers */ + +#define XMC4_GCU_ID_OFFSET 0x0000 /* Module Identification Register */ +#define XMC4_GCU_IDCHIP_OFFSET 0x0004 /* Chip ID */ +#define XMC4_GCU_IDMANUF_OFFSET 0x0008 /* Manufactory ID */ +#define XMC4_GCU_STCON_OFFSET 0x0010 /* Start-up Control */ +#define XMC4_GCU_GPR0_OFFSET 0x002c /* General Purpose Register 0 */ +#define XMC4_GCU_GPR1_OFFSET 0x0030 /* General Purpose Register 1 */ +#define XMC4_GCU_ETH0CON_OFFSET 0x0040 /* Ethernet 0 Port Control */ +#define XMC4_GCU_CCUCON_OFFSET 0x004c /* CCUx Global Start Control Register */ +#define XMC4_GCU_SRSTAT_OFFSET 0x0074 /* Service Request Status */ +#define XMC4_GCU_SRRAW_OFFSET 0x0078 /* RAW Service Request Status */ +#define XMC4_GCU_SRMSK_OFFSET 0x007c /* Service Request Mask */ +#define XMC4_GCU_SRCLR_OFFSET 0x0080 /* Service Request Clear */ +#define XMC4_GCU_SRSET_OFFSET 0x0084 /* Service Request Set */ +#define XMC4_GCU_NMIREQEN_OFFSET 0x0088 /* Enable Promoting Events to NMI Request */ +#define XMC4_GCU_DTSCON_OFFSET 0x008c /* DTS Control */ +#define XMC4_GCU_DTSSTAT_OFFSET 0x0090 /* DTS Status */ +#define XMC4_GCU_SDMMCDEL_OFFSET 0x009c /* SD-MMC Delay Control Register */ +#define XMC4_GCU_G0ORCEN_OFFSET 0x00a0 /* Out-Of-Range Comparator Enable Register 0 */ +#define XMC4_GCU_G1ORCEN_OFFSET 0x00a4 /* Out-Of-Range Comparator Enable Register 1 */ +#define XMC4_GCU_MIRRSTS_OFFSET 0x00c4 /* Mirror Update Status Register */ +#define XMC4_GCU_RMACR_OFFSET 0x00c8 /* Retention Memory Access Control Register */ +#define XMC4_GCU_RMADATA_OFFSET 0x00cc /* Retention Memory Access Data Register */ +#define XMC4_GCU_PEEN_OFFSET 0x013c /* Parity Error Enable Register */ +#define XMC4_GCU_MCHKCON_OFFSET 0x0140 /* Memory Checking Control Register */ +#define XMC4_GCU_PETE_OFFSET 0x0144 /* Parity Error Trap Enable Register */ +#define XMC4_GCU_PERSTEN_OFFSET 0x0148 /* Reset upon Parity Error Enable Register */ +#define XMC4_GCU_PEFLAG_OFFSET 0x0150 /* Parity Error Control Register */ +#define XMC4_GCU_PMTPR_OFFSET 0x0154 /* Parity Memory Test Pattern Register */ +#define XMC4_GCU_PMTSR_OFFSET 0x0158 /* Parity Memory Test Select Register */ +#define XMC4_GCU_TRAPSTAT_OFFSET 0x0160 /* Trap Status Register */ +#define XMC4_GCU_TRAPRAW_OFFSET 0x0164 /* Trap Raw Status Register */ +#define XMC4_GCU_TRAPDIS_OFFSET 0x0168 /* Trap Mask Register */ +#define XMC4_GCU_TRAPCLR_OFFSET 0x016c /* Trap Clear Register */ +#define XMC4_GCU_TRAPSET_OFFSET 0x0170 /* Trap Set Register */ + +/* PCU Registers */ + +#define XMC4_PCU_PWRSTAT_OFFSET 0x0000 /* Power Status Register */ +#define XMC4_PCU_PWRSET_OFFSET 0x0004 /* Power Set Control Register */ +#define XMC4_PCU_PWRCLR_OFFSET 0x0008 /* Power Clear Control Register */ +#define XMC4_PCU_EVRSTAT_OFFSET 0x0010 /* EVR Status Register */ +#define XMC4_PCU_EVRVADCSTAT_OFFSET 0x0014 /* EVR VADC Status Register */ +#define XMC4_PCU_PWRMON_OFFSET 0x002c /* Power Monitor Value */ + +/* HCU Registers */ + +#define XMC4_HCU_HDSTAT_OFFSET 0x0000 /* Hibernate Domain Status Register */ +#define XMC4_HCU_HDCLR_OFFSET 0x0004 /* Hibernate Domain Status Clear Register */ +#define XMC4_HCU_HDSET_OFFSET 0x0008 /* Hibernate Domain Status Set Register */ +#define XMC4_HCU_HDCR_OFFSET 0x000c /* Hibernate Domain Control Register */ +#define XMC4_HCU_OSCSICTRL_OFFSET 0x0014 /* Internal 32.768 kHz Clock Source Control Register */ +#define XMC4_HCU_OSCULSTAT_OFFSET 0x0018 /* OSC_ULP Status Register */ +#define XMC4_HCU_OSCULCTRL_OFFSET 0x001c /* OSC_ULP Control Register */ + +/* RCU Registers */ + +#define XMC4_RCU_RSTSTAT_OFFSET 0x0000 /* System Reset Status */ +#define XMC4_RCU_RSTSET_OFFSET 0x0004 /* Reset Set Register */ +#define XMC4_RCU_RSTCLR_OFFSET 0x0008 /* Reset Clear Register */ +#define XMC4_RCU_PRSTAT0_OFFSET 0x000c /* Peripheral Reset Status Register 0 */ +#define XMC4_RCU_PRSET0_OFFSET 0x0010 /* Peripheral Reset Set Register 0 */ +#define XMC4_RCU_PRCLR0_OFFSET 0x0014 /* Peripheral Reset Clear Register 0 */ +#define XMC4_RCU_PRSTAT1_OFFSET 0x0018 /* Peripheral Reset Status Register 1 */ +#define XMC4_RCU_PRSET1_OFFSET 0x001c /* Peripheral Reset Set Register 1 */ +#define XMC4_RCU_PRCLR1_OFFSET 0x0020 /* Peripheral Reset Clear Register 1 */ +#define XMC4_RCU_PRSTAT2_OFFSET 0x0024 /* Peripheral Reset Status Register 2 */ +#define XMC4_RCU_PRSET2_OFFSET 0x0028 /* Peripheral Reset Set Register 2 */ +#define XMC4_RCU_PRCLR2_OFFSET 0x002c /* Peripheral Reset Clear Register 2 */ +#define XMC4_RCU_PRSTAT3_OFFSET 0x0030 /* Peripheral Reset Status Register 3 */ +#define XMC4_RCU_PRSET3_OFFSET 0x0034 /* Peripheral Reset Set Register 3 */ +#define XMC4_RCU_PRCLR3_OFFSET 0x0038 /* Peripheral Reset Clear Register 3 */ + +/* CCU Registers */ + +#define XMC4_CCU_CLKSTAT_OFFSET 0x0000 /* Clock Status Register */ +#define XMC4_CCU_CLKSET_OFFSET 0x0004 /* Clock Set Control Register */ +#define XMC4_CCU_CLKCLR_OFFSET 0x0008 /* Clock clear Control Register */ +#define XMC4_CCU_SYSCLKCR_OFFSET 0x000c /* System Clock Control */ +#define XMC4_CCU_CPUCLKCR_OFFSET 0x0010 /* CPU Clock Control */ +#define XMC4_CCU_PBCLKCR_OFFSET 0x0014 /* Peripheral Bus Clock Control */ +#define XMC4_CCU_USBCLKCR_OFFSET 0x0018 /* USB Clock Control */ +#define XMC4_CCU_EBUCLKCR_OFFSET 0x001c /* EBU Clock Control */ +#define XMC4_CCU_CCUCLKCR_OFFSET 0x0020 /* CCU Clock Control */ +#define XMC4_CCU_WDTCLKCR_OFFSET 0x0024 /* WDT Clock Control */ +#define XMC4_CCU_EXTCLKCR_OFFSET 0x0028 /* External clock Control Register */ +#define XMC4_CCU_SLEEPCR_OFFSET 0x0030 /* Sleep Control Register */ +#define XMC4_CCU_DSLEEPCR_OFFSET 0x0034 /* Deep Sleep Control Register */ +#define XMC4_CCU_OSCHPSTAT_OFFSET 0x0100 /* OSC_HP Status Register */ +#define XMC4_CCU_OSCHPCTRL_OFFSET 0x0104 /* OSC_HP Control Register */ +#define XMC4_CCU_CLKCALCONST_OFFSET 0x010c /* Clock Calibration Constant Register */ +#define XMC4_CCU_PLLSTAT_OFFSET 0x0110 /* System PLL Status Register */ +#define XMC4_CCU_PLLCON0_OFFSET 0x0114 /* System PLL Configuration 0 Register */ +#define XMC4_CCU_PLLCON1_OFFSET 0x0118 /* System PLL Configuration 1 Register */ +#define XMC4_CCU_PLLCON2_OFFSET 0x011c /* System PLL Configuration 2 Register */ +#define XMC4_CCU_USBPLLSTAT_OFFSET 0x0120 /* USB PLL Status Register */ +#define XMC4_CCU_USBPLLCON_OFFSET 0x0124 /* USB PLL Control Register */ +#define XMC4_CCU_CLKMXSTAT_OFFSET 0x0138 /* Clock Multiplexing Status Register */ + +/* Register Addresses ***************************************************************/ + +#define XMC4_GCU_BASE (XMC4_SCU_BASE+XMC4_GCU_OFFSET) +#define XMC4_PCU_BASE (XMC4_SCU_BASE+XMC4_PCU_OFFSET) +#define XMC4_HCU_BASE (XMC4_SCU_BASE+XMC4_HCU_OFFSET) +#define XMC4_RCU_BASE (XMC4_SCU_BASE+XMC4_RCU_OFFSET) +#define XMC4_CCU_BASE (XMC4_SCU_BASE+XMC4_CCU_OFFSET) + +/* General SCU Registers */ + +#define XMC4_GCU_ID (XMC4_GCU_BASE+XMC4_GCU_ID_OFFSET) +#define XMC4_GCU_IDCHIP (XMC4_GCU_BASE+XMC4_GCU_IDCHIP_OFFSET) +#define XMC4_GCU_IDMANUF (XMC4_GCU_BASE+XMC4_GCU_IDMANUF_OFFSET) +#define XMC4_GCU_STCON (XMC4_GCU_BASE+XMC4_GCU_STCON_OFFSET) +#define XMC4_GCU_GPR0 (XMC4_GCU_BASE+XMC4_GCU_GPR0_OFFSET) +#define XMC4_GCU_GPR1 (XMC4_GCU_BASE+XMC4_GCU_GPR1_OFFSET) +#define XMC4_GCU_ETH0CON (XMC4_GCU_BASE+XMC4_GCU_ETH0CON_OFFSET) +#define XMC4_GCU_CCUCON (XMC4_GCU_BASE+XMC4_GCU_CCUCON_OFFSET) +#define XMC4_GCU_SRSTAT (XMC4_GCU_BASE+XMC4_GCU_SRSTAT_OFFSET) +#define XMC4_GCU_SRRAW (XMC4_GCU_BASE+XMC4_GCU_SRRAW_OFFSET) +#define XMC4_GCU_SRMSK (XMC4_GCU_BASE+XMC4_GCU_SRMSK_OFFSET) +#define XMC4_GCU_SRCLR (XMC4_GCU_BASE+XMC4_GCU_SRCLR_OFFSET) +#define XMC4_GCU_SRSET (XMC4_GCU_BASE+XMC4_GCU_SRSET_OFFSET) +#define XMC4_GCU_NMIREQEN (XMC4_GCU_BASE+XMC4_GCU_NMIREQEN_OFFSET) +#define XMC4_GCU_DTSCON (XMC4_GCU_BASE+XMC4_GCU_DTSCON_OFFSET) +#define XMC4_GCU_DTSSTAT (XMC4_GCU_BASE+XMC4_GCU_DTSSTAT_OFFSET) +#define XMC4_GCU_SDMMCDEL (XMC4_GCU_BASE+XMC4_GCU_SDMMCDEL_OFFSET) +#define XMC4_GCU_G0ORCEN (XMC4_GCU_BASE+XMC4_GCU_G0ORCEN_OFFSET) +#define XMC4_GCU_G1ORCEN (XMC4_GCU_BASE+XMC4_GCU_G1ORCEN_OFFSET) +#define XMC4_GCU_MIRRSTS (XMC4_GCU_BASE+XMC4_GCU_MIRRSTS_OFFSET) +#define XMC4_GCU_RMACR (XMC4_GCU_BASE+XMC4_GCU_RMACR_OFFSET) +#define XMC4_GCU_RMADATA (XMC4_GCU_BASE+XMC4_GCU_RMADATA_OFFSET) +#define XMC4_GCU_PEEN (XMC4_GCU_BASE+XMC4_GCU_PEEN_OFFSET) +#define XMC4_GCU_MCHKCON (XMC4_GCU_BASE+XMC4_GCU_MCHKCON_OFFSET) +#define XMC4_GCU_PETE (XMC4_GCU_BASE+XMC4_GCU_PETE_OFFSET) +#define XMC4_GCU_PERSTEN (XMC4_GCU_BASE+XMC4_GCU_PERSTEN_OFFSET) +#define XMC4_GCU_PEFLAG (XMC4_GCU_BASE+XMC4_GCU_PEFLAG_OFFSET) +#define XMC4_GCU_PMTPR (XMC4_GCU_BASE+XMC4_GCU_PMTPR_OFFSET) +#define XMC4_GCU_PMTSR (XMC4_GCU_BASE+XMC4_GCU_PMTSR_OFFSET) +#define XMC4_GCU_TRAPSTAT (XMC4_GCU_BASE+XMC4_GCU_TRAPSTAT_OFFSET) +#define XMC4_GCU_TRAPRAW (XMC4_GCU_BASE+XMC4_GCU_TRAPRAW_OFFSET) +#define XMC4_GCU_TRAPDIS (XMC4_GCU_BASE+XMC4_GCU_TRAPDIS_OFFSET) +#define XMC4_GCU_TRAPCLR (XMC4_GCU_BASE+XMC4_GCU_TRAPCLR_OFFSET) +#define XMC4_GCU_TRAPSET (XMC4_GCU_BASE+XMC4_GCU_TRAPSET_OFFSET) + +/* PCU Registers */ + +#define XMC4_PCU_PWRSTAT (XMC4_PCU_BASE+XMC4_PCU_PWRSTAT_OFFSET) +#define XMC4_PCU_PWRSET (XMC4_PCU_BASE+XMC4_PCU_PWRSET_OFFSET) +#define XMC4_PCU_PWRCLR (XMC4_PCU_BASE+XMC4_PCU_PWRCLR_OFFSET) +#define XMC4_PCU_EVRSTAT (XMC4_PCU_BASE+XMC4_PCU_EVRSTAT_OFFSET) +#define XMC4_PCU_EVRVADCSTAT (XMC4_PCU_BASE+XMC4_PCU_EVRVADCSTAT_OFFSET) +#define XMC4_PCU_PWRMON (XMC4_PCU_BASE+XMC4_PCU_PWRMON_OFFSET) + +/* HCU Registers */ + +#define XMC4_HCU_HDSTAT (XMC4_HCU_BASE+XMC4_HCU_HDSTAT_OFFSET) +#define XMC4_HCU_HDCLR (XMC4_HCU_BASE+XMC4_HCU_HDCLR_OFFSET) +#define XMC4_HCU_HDSET (XMC4_HCU_BASE+XMC4_HCU_HDSET_OFFSET) +#define XMC4_HCU_HDCR (XMC4_HCU_BASE+XMC4_HCU_HDCR_OFFSET) +#define XMC4_HCU_OSCSICTRL (XMC4_HCU_BASE+XMC4_HCU_OSCSICTRL_OFFSET) +#define XMC4_HCU_OSCULSTAT (XMC4_HCU_BASE+XMC4_HCU_OSCULSTAT_OFFSET) +#define XMC4_HCU_OSCULCTRL (XMC4_HCU_BASE+XMC4_HCU_OSCULCTRL_OFFSET) + +/* RCU Registers */ + +#define XMC4_RCU_RSTSTAT (XMC4_RCU_BASE+XMC4_RCU_RSTSTAT_OFFSET) +#define XMC4_RCU_RSTSET (XMC4_RCU_BASE+XMC4_RCU_RSTSET_OFFSET) +#define XMC4_RCU_RSTCLR (XMC4_RCU_BASE+XMC4_RCU_RSTCLR_OFFSET) +#define XMC4_RCU_PRSTAT0 (XMC4_RCU_BASE+XMC4_RCU_PRSTAT0_OFFSET) +#define XMC4_RCU_PRSET0 (XMC4_RCU_BASE+XMC4_RCU_PRSET0_OFFSET) +#define XMC4_RCU_PRCLR0 (XMC4_RCU_BASE+XMC4_RCU_PRCLR0_OFFSET) +#define XMC4_RCU_PRSTAT1 (XMC4_RCU_BASE+XMC4_RCU_PRSTAT1_OFFSET) +#define XMC4_RCU_PRSET1 (XMC4_RCU_BASE+XMC4_RCU_PRSET1_OFFSET) +#define XMC4_RCU_PRCLR1 (XMC4_RCU_BASE+XMC4_RCU_PRCLR1_OFFSET) +#define XMC4_RCU_PRSTAT2 (XMC4_RCU_BASE+XMC4_RCU_PRSTAT2_OFFSET) +#define XMC4_RCU_PRSET2 (XMC4_RCU_BASE+XMC4_RCU_PRSET2_OFFSET) +#define XMC4_RCU_PRCLR2 (XMC4_RCU_BASE+XMC4_RCU_PRCLR2_OFFSET) +#define XMC4_RCU_PRSTAT3 (XMC4_RCU_BASE+XMC4_RCU_PRSTAT3_OFFSET) +#define XMC4_RCU_PRSET3 (XMC4_RCU_BASE+XMC4_RCU_PRSET3_OFFSET) +#define XMC4_RCU_PRCLR3 (XMC4_RCU_BASE+XMC4_RCU_PRCLR3_OFFSET) + +/* CCU Registers */ + +#define XMC4_CCU_CLKSTAT (XMC4_CCU_BASE+XMC4_CCU_CLKSTAT_OFFSET) +#define XMC4_CCU_CLKSET (XMC4_CCU_BASE+XMC4_CCU_CLKSET_OFFSET) +#define XMC4_CCU_CLKCLR (XMC4_CCU_BASE+XMC4_CCU_CLKCLR_OFFSET) +#define XMC4_CCU_SYSCLKCR (XMC4_CCU_BASE+XMC4_CCU_SYSCLKCR_OFFSET) +#define XMC4_CCU_CPUCLKCR (XMC4_CCU_BASE+XMC4_CCU_CPUCLKCR_OFFSET) +#define XMC4_CCU_PBCLKCR (XMC4_CCU_BASE+XMC4_CCU_PBCLKCR_OFFSET) +#define XMC4_CCU_USBCLKCR (XMC4_CCU_BASE+XMC4_CCU_USBCLKCR_OFFSET) +#define XMC4_CCU_EBUCLKCR (XMC4_CCU_BASE+XMC4_CCU_EBUCLKCR_OFFSET) +#define XMC4_CCU_CCUCLKCR (XMC4_CCU_BASE+XMC4_CCU_CCUCLKCR_OFFSET) +#define XMC4_CCU_WDTCLKCR (XMC4_CCU_BASE+XMC4_CCU_WDTCLKCR_OFFSET) +#define XMC4_CCU_EXTCLKCR (XMC4_CCU_BASE+XMC4_CCU_EXTCLKCR_OFFSET) +#define XMC4_CCU_SLEEPCR (XMC4_CCU_BASE+XMC4_CCU_SLEEPCR_OFFSET) +#define XMC4_CCU_DSLEEPCR (XMC4_CCU_BASE+XMC4_CCU_DSLEEPCR_OFFSET) +#define XMC4_CCU_OSCHPSTAT (XMC4_CCU_BASE+XMC4_CCU_OSCHPSTAT_OFFSET) +#define XMC4_CCU_OSCHPCTRL (XMC4_CCU_BASE+XMC4_CCU_OSCHPCTRL_OFFSET) +#define XMC4_CCU_CLKCALCONST (XMC4_CCU_BASE+XMC4_CCU_CLKCALCONST_OFFSET) +#define XMC4_CCU_PLLSTAT (XMC4_CCU_BASE+XMC4_CCU_PLLSTAT_OFFSET) +#define XMC4_CCU_PLLCON0 (XMC4_CCU_BASE+XMC4_CCU_PLLCON0_OFFSET) +#define XMC4_CCU_PLLCON1 (XMC4_CCU_BASE+XMC4_CCU_PLLCON1_OFFSET) +#define XMC4_CCU_PLLCON2 (XMC4_CCU_BASE+XMC4_CCU_PLLCON2_OFFSET) +#define XMC4_CCU_USBPLLSTAT (XMC4_CCU_BASE+XMC4_CCU_USBPLLSTAT_OFFSET) +#define XMC4_CCU_USBPLLCON (XMC4_CCU_BASE+XMC4_CCU_USBPLLCON_OFFSET) +#define XMC4_CCU_CLKMXSTAT (XMC4_CCU_BASE+XMC4_CCU_CLKMXSTAT_OFFSET) + +/* Register Bit-Field Definitions ***************************************************/ + +/* General SCU Registers */ + +/* Module Identification Register */ +#define GCU_ID_ +/* Chip ID */ +#define GCU_IDCHIP_ +/* Manufactory ID */ +#define GCU_IDMANUF_ +/* Start-up Control */ +#define GCU_STCON_ +/* General Purpose Register 0 */ +#define GCU_GPR0_ +/* General Purpose Register 1 */ +#define GCU_GPR1_ +/* Ethernet 0 Port Control */ +#define GCU_ETH0CON_ +/* CCUx Global Start Control Register */ +#define GCU_CCUCON_ +/* Service Request Status */ +#define GCU_SRSTAT_ +/* RAW Service Request Status */ +#define GCU_SRRAW_ +/* Service Request Mask */ +#define GCU_SRMSK_ +/* Service Request Clear */ +#define GCU_SRCLR_ +/* Service Request Set */ +#define GCU_SRSET_ +/* Enable Promoting Events to NMI Request */ +#define GCU_NMIREQEN_ +/* DTS Control */ +#define GCU_DTSCON_ +/* DTS Status */ +#define GCU_DTSSTAT_ +/* SD-MMC Delay Control Register */ +#define GCU_SDMMCDEL_ +/* Out-Of-Range Comparator Enable Register 0 */ +#define GCU_G0ORCEN_ +/* Out-Of-Range Comparator Enable Register 1 */ +#define GCU_G1ORCEN_ +/* Mirror Update Status Register */ +#define GCU_MIRRSTS_ +/* Retention Memory Access Control Register */ +#define GCU_RMACR_ +/* Retention Memory Access Data Register */ +#define GCU_RMADATA_ +/* Parity Error Enable Register */ +#define GCU_PEEN_ +/* Memory Checking Control Register */ +#define GCU_MCHKCON_ +/* Parity Error Trap Enable Register */ +#define GCU_PETE_ +/* Reset upon Parity Error Enable Register */ +#define GCU_PERSTEN_ +/* Parity Error Control Register */ +#define GCU_PEFLAG_ +/* Parity Memory Test Pattern Register */ +#define GCU_PMTPR_ +/* Parity Memory Test Select Register */ +#define GCU_PMTSR_ +/* Trap Status Register */ +#define GCU_TRAPSTAT_ +/* Trap Raw Status Register */ +#define GCU_TRAPRAW_ +/* Trap Mask Register */ +#define GCU_TRAPDIS_ +/* Trap Clear Register */ +#define GCU_TRAPCLR_ +/* Trap Set Register */ +#define GCU_TRAPSET_ + +/* PCU Registers */ + +/* Power Status Register */ +#define PCU_PWRSTAT_ +/* Power Set Control Register */ +#define PCU_PWRSET_ +/* Power Clear Control Register */ +#define PCU_PWRCLR_ +/* EVR Status Register */ +#define PCU_EVRSTAT_ +/* EVR VADC Status Register */ +#define PCU_EVRVADCSTAT_ +/* Power Monitor Value */ +#define PCU_PWRMON_ + +/* HCU Registers */ + +/* Hibernate Domain Status Register */ +#define HCU_HDSTAT_ +/* Hibernate Domain Status Clear Register */ +#define HCU_HDCLR_ +/* Hibernate Domain Status Set Register */ +#define HCU_HDSET_ +/* Hibernate Domain Control Register */ +#define HCU_HDCR_ +/* Internal 32.768 kHz Clock Source Control Register */ +#define HCU_OSCSICTRL_ +/* OSC_ULP Status Register */ +#define HCU_OSCULSTAT_ +/* OSC_ULP Control Register */ +#define HCU_OSCULCTRL_ + +/* RCU Registers */ + +/* System Reset Status */ +#define RCU_RSTSTAT_ +/* Reset Set Register */ +#define RCU_RSTSET_ +/* Reset Clear Register */ +#define RCU_RSTCLR_ +/* Peripheral Reset Status Register 0 */ +#define RCU_PRSTAT0_ +/* Peripheral Reset Set Register 0 */ +#define RCU_PRSET0_ +/* Peripheral Reset Clear Register 0 */ +#define RCU_PRCLR0_ +/* Peripheral Reset Status Register 1 */ +#define RCU_PRSTAT1_ +/* Peripheral Reset Set Register 1 */ +#define RCU_PRSET1_ +/* Peripheral Reset Clear Register 1 */ +#define RCU_PRCLR1_ +/* Peripheral Reset Status Register 2 */ +#define RCU_PRSTAT2_ +/* Peripheral Reset Set Register 2 */ +#define RCU_PRSET2_ +/* Peripheral Reset Clear Register 2 */ +#define RCU_PRCLR2_ +/* Peripheral Reset Status Register 3 */ +#define RCU_PRSTAT3_ +/* Peripheral Reset Set Register 3 */ +#define RCU_PRSET3_ +/* Peripheral Reset Clear Register 3 */ +#define RCU_PRCLR3_ + +/* CCU Registers */ + +/* Clock Status Register */ +#define CCU_CLKSTAT_ +/* Clock Set Control Register */ +#define CCU_CLKSET_ +/* Clock clear Control Register */ +#define CCU_CLKCLR_ +/* System Clock Control */ +#define CCU_SYSCLKCR_ +/* CPU Clock Control */ +#define CCU_CPUCLKCR_ +/* Peripheral Bus Clock Control */ +#define CCU_PBCLKCR_ +/* USB Clock Control */ +#define CCU_USBCLKCR_ +/* EBU Clock Control */ +#define CCU_EBUCLKCR_ +/* CCU Clock Control */ +#define CCU_CCUCLKCR_ +/* WDT Clock Control */ +#define CCU_WDTCLKCR_ +/* External clock Control Register */ +#define CCU_EXTCLKCR_ +/* Sleep Control Register */ +#define CCU_SLEEPCR_ +/* Deep Sleep Control Register */ +#define CCU_DSLEEPCR_ +/* OSC_HP Status Register */ +#define CCU_OSCHPSTAT_ +/* OSC_HP Control Register */ +#define CCU_OSCHPCTRL_ +/* Clock Calibration Constant Register */ +#define CCU_CLKCALCONST_ +/* System PLL Status Register */ +#define CCU_PLLSTAT_ +/* System PLL Configuration 0 Register */ +#define CCU_PLLCON0_ +/* System PLL Configuration 1 Register */ +#define CCU_PLLCON1_ +/* System PLL Configuration 2 Register */ +#define CCU_PLLCON2_ +/* USB PLL Status Register */ +#define CCU_USBPLLSTAT_ +/* USB PLL Control Register */ +#define CCU_USBPLLCON_ +/* Clock Multiplexing Status Register */ +#define CCU_CLKMXSTAT_ + +#endif /* __ARCH_ARM_SRC_XMC4_CHIP_XMC4_SCU_H */ From 772b3cf21b66b7649b4b1a8e87d70afc081908e6 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 14 Mar 2017 19:07:19 -0600 Subject: [PATCH 05/81] XMC4xxx: Add Peripheral Memory Map header file. --- arch/arm/src/xmc4/chip/xmc4_memorymap.h | 227 ++++++++ arch/arm/src/xmc4/chip/xmc4_scu.h | 728 ++++++++++++++---------- 2 files changed, 654 insertions(+), 301 deletions(-) create mode 100644 arch/arm/src/xmc4/chip/xmc4_memorymap.h diff --git a/arch/arm/src/xmc4/chip/xmc4_memorymap.h b/arch/arm/src/xmc4/chip/xmc4_memorymap.h new file mode 100644 index 00000000000..8cf50174b9a --- /dev/null +++ b/arch/arm/src/xmc4/chip/xmc4_memorymap.h @@ -0,0 +1,227 @@ +/************************************************************************************ + * arch/arm/src/xmc4/chip/xmc4_memorymap.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Reference: XMC4500 Reference Manual V1.5 2014-07 Microcontrollers. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * May include some logic from sample code provided by Infineon: + * + * Copyright (C) 2011-2015 Infineon Technologies AG. All rights reserved. + * + * Infineon Technologies AG (Infineon) is supplying this software for use with + * Infineon's microcontrollers. This file can be freely distributed within + * development tools that are supporting such microcontrollers. + * + * THIS SOFTWARE IS PROVIDED AS IS. NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, + * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_XMC4_CHIP_XMC4_MEMORYMAP_H +#define __ARCH_ARM_SRC_XMC4_CHIP_XMC4_MEMORYMAP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Peripheral Memory Map ************************************************************/ +/* Acronyms: + * ADC - Analog to Digital Converter + * CCU - Capture Compare Unit + * DAC - Digital to Analog Converter + * DSD - Delta Sigmoid Demodulator + * ERU - External Request Unit + * FCE - Flexible CRC Engine + * GPDMA - General Purpose DMA + * LEDTS - LED and Touch Sense Control Unit + * PMU - Program Management Unit + * POSIF - Position Interface + * SDMMC - Multi Media Card Interface + * USB - Universal Serial Bus + * USCI - Universal Serial Interface + */ + +#define XMC4_PBA0_BASE 0x40000000 +#define XMC4_VADC_BASE 0x40004000 +#define XMC4_VADC_G0_BASE 0x40004400 +#define XMC4_VADC_G1_BASE 0x40004800 +#define XMC4_VADC_G2_BASE 0x40004c00 +#define XMC4_VADC_G3_BASE 0x40005000 +#define XMC4_DSD_BASE 0x40008000 +#define XMC4_DSD_CH0_BASE 0x40008100 +#define XMC4_DSD_CH1_BASE 0x40008200 +#define XMC4_DSD_CH2_BASE 0x40008300 +#define XMC4_DSD_CH3_BASE 0x40008400 +#define XMC4_CCU40_BASE 0x4000c000 +#define XMC4_CCU40_CC40_BASE 0x4000c100 +#define XMC4_CCU40_CC41_BASE 0x4000c200 +#define XMC4_CCU40_CC42_BASE 0x4000c300 +#define XMC4_CCU40_CC43_BASE 0x4000c400 +#define XMC4_CCU41_BASE 0x40010000 +#define XMC4_CCU41_CC40_BASE 0x40010100 +#define XMC4_CCU41_CC41_BASE 0x40010200 +#define XMC4_CCU41_CC42_BASE 0x40010300 +#define XMC4_CCU41_CC43_BASE 0x40010400 +#define XMC4_CCU42_BASE 0x40014000 +#define XMC4_CCU42_CC40_BASE 0x40014100 +#define XMC4_CCU42_CC41_BASE 0x40014200 +#define XMC4_CCU42_CC42_BASE 0x40014300 +#define XMC4_CCU42_CC43_BASE 0x40014400 +#define XMC4_CCU80_BASE 0x40020000 +#define XMC4_CCU80_CC80_BASE 0x40020100 +#define XMC4_CCU80_CC81_BASE 0x40020200 +#define XMC4_CCU80_CC82_BASE 0x40020300 +#define XMC4_CCU80_CC83_BASE 0x40020400 +#define XMC4_CCU81_BASE 0x40024000 +#define XMC4_CCU81_CC80_BASE 0x40024100 +#define XMC4_CCU81_CC81_BASE 0x40024200 +#define XMC4_CCU81_CC82_BASE 0x40024300 +#define XMC4_CCU81_CC83_BASE 0x40024400 +#define XMC4_POSIF0_BASE 0x40028000 +#define XMC4_POSIF1_BASE 0x4002c000 +#define XMC4_USIC0_BASE 0x40030008 +#define XMC4_USIC0_CH0_BASE 0x40030000 +#define XMC4_USIC0_CH1_BASE 0x40030200 +#define XMC4_ERU1_BASE 0x40044000 + +#define XMC4_PBA1_BASE 0x48000000 +#define XMC4_CCU43_BASE 0x48004000 +#define XMC4_CCU43_CC40_BASE 0x48004100 +#define XMC4_CCU43_CC41_BASE 0x48004200 +#define XMC4_CCU43_CC42_BASE 0x48004300 +#define XMC4_CCU43_CC43_BASE 0x48004400 +#define XMC4_LEDTS0_BASE 0x48010000 +#define XMC4_CAN_BASE 0x48014000 +#define XMC4_CAN_NODE0_BASE 0x48014200 +#define XMC4_CAN_NODE1_BASE 0x48014300 +#define XMC4_CAN_NODE2_BASE 0x48014400 +#define XMC4_CAN_NODE3_BASE 0x48014500 +#define XMC4_CAN_NODE4_BASE 0x48014600 +#define XMC4_CAN_NODE5_BASE 0x48014700 +#define XMC4_CAN_MO_BASE 0x48015000 +#define XMC4_DAC_BASE 0x48018000 +#define XMC4_SDMMC_BASE 0x4801c000 +#define XMC4_USIC1_CH0_BASE 0x48020000 +#define XMC4_USIC1_BASE 0x48020008 +#define XMC4_USIC1_CH1_BASE 0x48020200 +#define XMC4_USIC2_CH0_BASE 0x48024000 +#define XMC4_USIC2_BASE 0x48024008 +#define XMC4_USIC2_CH1_BASE 0x48024200 +#define XMC4_PORT0_BASE 0x48028000 +#define XMC4_PORT1_BASE 0x48028100 +#define XMC4_PORT2_BASE 0x48028200 +#define XMC4_PORT3_BASE 0x48028300 +#define XMC4_PORT4_BASE 0x48028400 +#define XMC4_PORT5_BASE 0x48028500 +#define XMC4_PORT6_BASE 0x48028600 +#define XMC4_PORT7_BASE 0x48028700 +#define XMC4_PORT8_BASE 0x48028800 +#define XMC4_PORT9_BASE 0x48028900 +#define XMC4_PORT14_BASE 0x48028e00 +#define XMC4_PORT15_BASE 0x48028f00 + +#define XMC4_SCU_GENERAL_BASE 0x50004000 +#define XMC4_ETH0_CON_BASE 0x50004040 +#define XMC4_SCU_INTERRUPT_BASE 0x50004074 +#define XMC4_SDMMC_CON_BASE 0x500040b4 +#define XMC4_SCU_PARITY_BASE 0x5000413c +#define XMC4_SCU_TRAP_BASE 0x50004160 +#define XMC4_SCU_POWER_BASE 0x50004200 +#define XMC4_SCU_HIBERNATE_BASE 0x50004300 +#define XMC4_SCU_RESET_BASE 0x50004400 +#define XMC4_SCU_CLK_BASE 0x50004600 +#define XMC4_SCU_OSC_BASE 0x50004700 +#define XMC4_SCU_PLL_BASE 0x50004710 +#define XMC4_ERU0_BASE 0x50004800 +#define XMC4_DLR_BASE 0x50004900 +#define XMC4_RTC_BASE 0x50004a00 +#define XMC4_WDT_BASE 0x50008000 +#define XMC4_ETH0_BASE 0x5000c000 +#define XMC4_USB0_BASE 0x50040000 +#define XMC4_USB0_CH0_BASE 0x50040500 +#define XMC4_USB0_CH1_BASE 0x50040520 +#define XMC4_USB0_CH2_BASE 0x50040540 +#define XMC4_USB0_CH3_BASE 0x50040560 +#define XMC4_USB0_CH4_BASE 0x50040580 +#define XMC4_USB0_CH5_BASE 0x500405a0 +#define XMC4_USB0_CH6_BASE 0x500405c0 +#define XMC4_USB0_CH7_BASE 0x500405e0 +#define XMC4_USB0_CH8_BASE 0x50040600 +#define XMC4_USB0_CH9_BASE 0x50040620 +#define XMC4_USB0_CH10_BASE 0x50040640 +#define XMC4_USB0_CH11_BASE 0x50040660 +#define XMC4_USB0_CH12_BASE 0x50040680 +#define XMC4_USB0_CH13_BASE 0x500406a0 +#define XMC4_USB_EP_BASE 0x50040900 +#define XMC4_USB0_EP1_BASE 0x50040920 +#define XMC4_USB0_EP2_BASE 0x50040940 +#define XMC4_USB0_EP3_BASE 0x50040960 +#define XMC4_USB0_EP4_BASE 0x50040980 +#define XMC4_USB0_EP5_BASE 0x500409a0 +#define XMC4_USB0_EP6_BASE 0x500409c0 +#define XMC4_GPDMA0_CH0_BASE 0x50014000 +#define XMC4_GPDMA0_CH1_BASE 0x50014058 +#define XMC4_GPDMA0_CH2_BASE 0x500140b0 +#define XMC4_GPDMA0_CH3_BASE 0x50014108 +#define XMC4_GPDMA0_CH4_BASE 0x50014160 +#define XMC4_GPDMA0_CH5_BASE 0x500141b8 +#define XMC4_GPDMA0_CH6_BASE 0x50014210 +#define XMC4_GPDMA0_CH7_BASE 0x50014268 +#define XMC4_GPDMA0_BASE 0x500142c0 +#define XMC4_GPDMA1_CH0_BASE 0x50018000 +#define XMC4_GPDMA1_CH1_BASE 0x50018058 +#define XMC4_GPDMA1_CH2_BASE 0x500180b0 +#define XMC4_GPDMA1_CH3_BASE 0x50018108 +#define XMC4_GPDMA1_BASE 0x500182c0 +#define XMC4_FCE_BASE 0x50020000 +#define XMC4_FCE_KE0_BASE 0x50020020 +#define XMC4_FCE_KE1_BASE 0x50020040 +#define XMC4_FCE_KE2_BASE 0x50020060 +#define XMC4_FCE_KE3_BASE 0x50020080 + +#define XMC4_PMU0_BASE 0x58000508 +#define XMC4_FLASH0_BASE 0x58001000 +#define XMC4_PREF_BASE 0x58004000 +#define XMC4_EBU_BASE 0x58008000 + +#define XMC4_PPB_BASE 0xe000e000 + +#endif /* __ARCH_ARM_SRC_XMC4_CHIP_XMC4_SCU_H */ diff --git a/arch/arm/src/xmc4/chip/xmc4_scu.h b/arch/arm/src/xmc4/chip/xmc4_scu.h index a3e6d116e73..ab5b7719953 100644 --- a/arch/arm/src/xmc4/chip/xmc4_scu.h +++ b/arch/arm/src/xmc4/chip/xmc4_scu.h @@ -4,6 +4,8 @@ * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * + * Reference: XMC4500 Reference Manual V1.5 2014-07 Microcontrollers. + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: @@ -31,6 +33,20 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * + * May include some logic from sample code provided by Infineon: + * + * Copyright (C) 2011-2015 Infineon Technologies AG. All rights reserved. + * + * Infineon Technologies AG (Infineon) is supplying this software for use with + * Infineon's microcontrollers. This file can be freely distributed within + * development tools that are supporting such microcontrollers. + * + * THIS SOFTWARE IS PROVIDED AS IS. NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, + * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * ************************************************************************************/ #ifndef __ARCH_ARM_SRC_XMC4_CHIP_XMC4_SCU_H @@ -48,406 +64,516 @@ ************************************************************************************/ /* Register Offsets *****************************************************************/ - -#define XMC4_GCU_OFFSET 0x0000 /* Offset address of General Control Unit */ -#define XMC4_PCU_OFFSET 0x0200 /* Offset address of Power Control Unit */ -#define XMC4_HCU_OFFSET 0x0300 /* Offset address of Hibernate Control Unit */ -#define XMC4_RCU_OFFSET 0x0400 /* Offset address of Reset Control Unit */ -#define XMC4_CCU_OFFSET 0x0600 /* Offset address of Clock Control Unit */ - /* General SCU Registers */ -#define XMC4_GCU_ID_OFFSET 0x0000 /* Module Identification Register */ -#define XMC4_GCU_IDCHIP_OFFSET 0x0004 /* Chip ID */ -#define XMC4_GCU_IDMANUF_OFFSET 0x0008 /* Manufactory ID */ -#define XMC4_GCU_STCON_OFFSET 0x0010 /* Start-up Control */ -#define XMC4_GCU_GPR0_OFFSET 0x002c /* General Purpose Register 0 */ -#define XMC4_GCU_GPR1_OFFSET 0x0030 /* General Purpose Register 1 */ -#define XMC4_GCU_ETH0CON_OFFSET 0x0040 /* Ethernet 0 Port Control */ -#define XMC4_GCU_CCUCON_OFFSET 0x004c /* CCUx Global Start Control Register */ -#define XMC4_GCU_SRSTAT_OFFSET 0x0074 /* Service Request Status */ -#define XMC4_GCU_SRRAW_OFFSET 0x0078 /* RAW Service Request Status */ -#define XMC4_GCU_SRMSK_OFFSET 0x007c /* Service Request Mask */ -#define XMC4_GCU_SRCLR_OFFSET 0x0080 /* Service Request Clear */ -#define XMC4_GCU_SRSET_OFFSET 0x0084 /* Service Request Set */ -#define XMC4_GCU_NMIREQEN_OFFSET 0x0088 /* Enable Promoting Events to NMI Request */ -#define XMC4_GCU_DTSCON_OFFSET 0x008c /* DTS Control */ -#define XMC4_GCU_DTSSTAT_OFFSET 0x0090 /* DTS Status */ -#define XMC4_GCU_SDMMCDEL_OFFSET 0x009c /* SD-MMC Delay Control Register */ -#define XMC4_GCU_G0ORCEN_OFFSET 0x00a0 /* Out-Of-Range Comparator Enable Register 0 */ -#define XMC4_GCU_G1ORCEN_OFFSET 0x00a4 /* Out-Of-Range Comparator Enable Register 1 */ -#define XMC4_GCU_MIRRSTS_OFFSET 0x00c4 /* Mirror Update Status Register */ -#define XMC4_GCU_RMACR_OFFSET 0x00c8 /* Retention Memory Access Control Register */ -#define XMC4_GCU_RMADATA_OFFSET 0x00cc /* Retention Memory Access Data Register */ -#define XMC4_GCU_PEEN_OFFSET 0x013c /* Parity Error Enable Register */ -#define XMC4_GCU_MCHKCON_OFFSET 0x0140 /* Memory Checking Control Register */ -#define XMC4_GCU_PETE_OFFSET 0x0144 /* Parity Error Trap Enable Register */ -#define XMC4_GCU_PERSTEN_OFFSET 0x0148 /* Reset upon Parity Error Enable Register */ -#define XMC4_GCU_PEFLAG_OFFSET 0x0150 /* Parity Error Control Register */ -#define XMC4_GCU_PMTPR_OFFSET 0x0154 /* Parity Memory Test Pattern Register */ -#define XMC4_GCU_PMTSR_OFFSET 0x0158 /* Parity Memory Test Select Register */ -#define XMC4_GCU_TRAPSTAT_OFFSET 0x0160 /* Trap Status Register */ -#define XMC4_GCU_TRAPRAW_OFFSET 0x0164 /* Trap Raw Status Register */ -#define XMC4_GCU_TRAPDIS_OFFSET 0x0168 /* Trap Mask Register */ -#define XMC4_GCU_TRAPCLR_OFFSET 0x016c /* Trap Clear Register */ -#define XMC4_GCU_TRAPSET_OFFSET 0x0170 /* Trap Set Register */ +#define XMC4_SCU_ID_OFFSET 0x0000 /* Module Identification Register */ +#define XMC4_SCU_IDCHIP_OFFSET 0x0004 /* Chip ID */ +#define XMC4_SCU_IDMANUF_OFFSET 0x0008 /* Manufactory ID */ +#define XMC4_SCU_STCON_OFFSET 0x0010 /* Start-up Control */ +#define XMC4_SCU_GPR0_OFFSET 0x002c /* General Purpose Register 0 */ +#define XMC4_SCU_GPR1_OFFSET 0x0030 /* General Purpose Register 1 */ +#define XMC4_SCU_ETH0CON_OFFSET 0x0040 /* Ethernet 0 Port Control */ +#define XMC4_SCU_CCUCON_OFFSET 0x004c /* CCUx Global Start Control Register */ +#define XMC4_SCU_DTSCON_OFFSET 0x008c /* DTS Control */ +#define XMC4_SCU_DTSSTAT_OFFSET 0x0090 /* DTS Status */ +#define XMC4_SCU_SDMMCDEL_OFFSET 0x009c /* SD-MMC Delay Control Register */ +#define XMC4_SCU_G0ORCEN_OFFSET 0x00a0 /* Out-Of-Range Comparator Enable Register 0 */ +#define XMC4_SCU_G1ORCEN_OFFSET 0x00a4 /* Out-Of-Range Comparator Enable Register 1 */ +#define XMC4_SCU_MIRRSTS_OFFSET 0x00c4 /* Mirror Update Status Register */ +#define XMC4_SCU_RMACR_OFFSET 0x00c8 /* Retention Memory Access Control Register */ +#define XMC4_SCU_RMADATA_OFFSET 0x00cc /* Retention Memory Access Data Register */ -/* PCU Registers */ +/* Ethernet Control SCU Resters */ -#define XMC4_PCU_PWRSTAT_OFFSET 0x0000 /* Power Status Register */ -#define XMC4_PCU_PWRSET_OFFSET 0x0004 /* Power Set Control Register */ -#define XMC4_PCU_PWRCLR_OFFSET 0x0008 /* Power Clear Control Register */ -#define XMC4_PCU_EVRSTAT_OFFSET 0x0010 /* EVR Status Register */ -#define XMC4_PCU_EVRVADCSTAT_OFFSET 0x0014 /* EVR VADC Status Register */ -#define XMC4_PCU_PWRMON_OFFSET 0x002c /* Power Monitor Value */ +#define XMC4_SCU_ETHCON_OFFSET 0x0000 /* Ethernet 0 Port Control Register */ -/* HCU Registers */ +/* Interrupt Control SCU Registers */ -#define XMC4_HCU_HDSTAT_OFFSET 0x0000 /* Hibernate Domain Status Register */ -#define XMC4_HCU_HDCLR_OFFSET 0x0004 /* Hibernate Domain Status Clear Register */ -#define XMC4_HCU_HDSET_OFFSET 0x0008 /* Hibernate Domain Status Set Register */ -#define XMC4_HCU_HDCR_OFFSET 0x000c /* Hibernate Domain Control Register */ -#define XMC4_HCU_OSCSICTRL_OFFSET 0x0014 /* Internal 32.768 kHz Clock Source Control Register */ -#define XMC4_HCU_OSCULSTAT_OFFSET 0x0018 /* OSC_ULP Status Register */ -#define XMC4_HCU_OSCULCTRL_OFFSET 0x001c /* OSC_ULP Control Register */ +#define XMC4_SCU_SRSTAT_OFFSET 0x0000 /* Service Request Status */ +#define XMC4_SCU_SRRAW_OFFSET 0x0004 /* RAW Service Request Status */ +#define XMC4_SCU_SRMSK_OFFSET 0x0008 /* Service Request Mask */ +#define XMC4_SCU_SRCLR_OFFSET 0x000c /* Service Request Clear */ +#define XMC4_SCU_SRSET_OFFSET 0x0010 /* Service Request Set */ +#define XMC4_SCU_NMIREQEN_OFFSET 0x0014 /* Enable Promoting Events to NMI Request */ -/* RCU Registers */ +/* SDMMC Control SCU Registers */ -#define XMC4_RCU_RSTSTAT_OFFSET 0x0000 /* System Reset Status */ -#define XMC4_RCU_RSTSET_OFFSET 0x0004 /* Reset Set Register */ -#define XMC4_RCU_RSTCLR_OFFSET 0x0008 /* Reset Clear Register */ -#define XMC4_RCU_PRSTAT0_OFFSET 0x000c /* Peripheral Reset Status Register 0 */ -#define XMC4_RCU_PRSET0_OFFSET 0x0010 /* Peripheral Reset Set Register 0 */ -#define XMC4_RCU_PRCLR0_OFFSET 0x0014 /* Peripheral Reset Clear Register 0 */ -#define XMC4_RCU_PRSTAT1_OFFSET 0x0018 /* Peripheral Reset Status Register 1 */ -#define XMC4_RCU_PRSET1_OFFSET 0x001c /* Peripheral Reset Set Register 1 */ -#define XMC4_RCU_PRCLR1_OFFSET 0x0020 /* Peripheral Reset Clear Register 1 */ -#define XMC4_RCU_PRSTAT2_OFFSET 0x0024 /* Peripheral Reset Status Register 2 */ -#define XMC4_RCU_PRSET2_OFFSET 0x0028 /* Peripheral Reset Set Register 2 */ -#define XMC4_RCU_PRCLR2_OFFSET 0x002c /* Peripheral Reset Clear Register 2 */ -#define XMC4_RCU_PRSTAT3_OFFSET 0x0030 /* Peripheral Reset Status Register 3 */ -#define XMC4_RCU_PRSET3_OFFSET 0x0034 /* Peripheral Reset Set Register 3 */ -#define XMC4_RCU_PRCLR3_OFFSET 0x0038 /* Peripheral Reset Clear Register 3 */ +#define XMC4_SCU_SDMMCCON_OFFSET 0x0000 /* SDMMC Configuration */ -/* CCU Registers */ +/* Parity Control Registers */ -#define XMC4_CCU_CLKSTAT_OFFSET 0x0000 /* Clock Status Register */ -#define XMC4_CCU_CLKSET_OFFSET 0x0004 /* Clock Set Control Register */ -#define XMC4_CCU_CLKCLR_OFFSET 0x0008 /* Clock clear Control Register */ -#define XMC4_CCU_SYSCLKCR_OFFSET 0x000c /* System Clock Control */ -#define XMC4_CCU_CPUCLKCR_OFFSET 0x0010 /* CPU Clock Control */ -#define XMC4_CCU_PBCLKCR_OFFSET 0x0014 /* Peripheral Bus Clock Control */ -#define XMC4_CCU_USBCLKCR_OFFSET 0x0018 /* USB Clock Control */ -#define XMC4_CCU_EBUCLKCR_OFFSET 0x001c /* EBU Clock Control */ -#define XMC4_CCU_CCUCLKCR_OFFSET 0x0020 /* CCU Clock Control */ -#define XMC4_CCU_WDTCLKCR_OFFSET 0x0024 /* WDT Clock Control */ -#define XMC4_CCU_EXTCLKCR_OFFSET 0x0028 /* External clock Control Register */ -#define XMC4_CCU_SLEEPCR_OFFSET 0x0030 /* Sleep Control Register */ -#define XMC4_CCU_DSLEEPCR_OFFSET 0x0034 /* Deep Sleep Control Register */ -#define XMC4_CCU_OSCHPSTAT_OFFSET 0x0100 /* OSC_HP Status Register */ -#define XMC4_CCU_OSCHPCTRL_OFFSET 0x0104 /* OSC_HP Control Register */ -#define XMC4_CCU_CLKCALCONST_OFFSET 0x010c /* Clock Calibration Constant Register */ -#define XMC4_CCU_PLLSTAT_OFFSET 0x0110 /* System PLL Status Register */ -#define XMC4_CCU_PLLCON0_OFFSET 0x0114 /* System PLL Configuration 0 Register */ -#define XMC4_CCU_PLLCON1_OFFSET 0x0118 /* System PLL Configuration 1 Register */ -#define XMC4_CCU_PLLCON2_OFFSET 0x011c /* System PLL Configuration 2 Register */ -#define XMC4_CCU_USBPLLSTAT_OFFSET 0x0120 /* USB PLL Status Register */ -#define XMC4_CCU_USBPLLCON_OFFSET 0x0124 /* USB PLL Control Register */ -#define XMC4_CCU_CLKMXSTAT_OFFSET 0x0138 /* Clock Multiplexing Status Register */ +#define XMC4_SCU_PEEN_OFFSET 0x0000 /* Parity Error Enable Register */ +#define XMC4_SCU_MCHKCON_OFFSET 0x0004 /* Memory Checking Control Register */ +#define XMC4_SCU_PETE_OFFSET 0x0008 /* Parity Error Trap Enable Register */ +#define XMC4_SCU_PERSTEN_OFFSET 0x000c /* Reset upon Parity Error Enable Register */ +#define XMC4_SCU_PEFLAG_OFFSET 0x0014 /* Parity Error Control Register */ +#define XMC4_SCU_PMTPR_OFFSET 0x0018 /* Parity Memory Test Pattern Register */ +#define XMC4_SCU_PMTSR_OFFSET 0x001c /* Parity Memory Test Select Register */ + +/* Trap Control Registers */ + +#define XMC4_SCU_TRAPSTAT_OFFSET 0x0000 /* Trap Status Register */ +#define XMC4_SCU_TRAPRAW_OFFSET 0x0004 /* Trap Raw Status Register */ +#define XMC4_SCU_TRAPDIS_OFFSET 0x0008 /* Trap Mask Register */ +#define XMC4_SCU_TRAPCLR_OFFSET 0x000c /* Trap Clear Register */ +#define XMC4_SCU_TRAPSET_OFFSET 0x0010 /* Trap Set Register */ + +/* Power Control SCU Registers */ + +#define XMC4_SCU_PWRSTAT_OFFSET 0x0000 /* Power Status Register */ +#define XMC4_SCU_PWRSET_OFFSET 0x0004 /* Power Set Control Register */ +#define XMC4_SCU_PWRCLR_OFFSET 0x0008 /* Power Clear Control Register */ +#define XMC4_SCU_EVRSTAT_OFFSET 0x0010 /* EVR Status Register */ +#define XMC4_SCU_EVRVADCSTAT_OFFSET 0x0014 /* EVR VADC Status Register */ +#define XMC4_SCU_PWRMON_OFFSET 0x002c /* Power Monitor Value */ + +/* Hibernation SCU Registers */ + +#define XMC4_SCU_HDSTAT_OFFSET 0x0000 /* Hibernate Domain Status Register */ +#define XMC4_SCU_HDCLR_OFFSET 0x0004 /* Hibernate Domain Status Clear Register */ +#define XMC4_SCU_HDSET_OFFSET 0x0008 /* Hibernate Domain Status Set Register */ +#define XMC4_SCU_HDCR_OFFSET 0x000c /* Hibernate Domain Control Register */ +#define XMC4_SCU_OSCSICTRL_OFFSET 0x0014 /* Internal 32.768 kHz Clock Source Control Register */ +#define XMC4_SCU_OSCULSTAT_OFFSET 0x0018 /* OSC_ULP Status Register */ +#define XMC4_SCU_OSCULCTRL_OFFSET 0x001c /* OSC_ULP Control Register */ + +/* Reset SCU Registers */ + +#define XMC4_SCU_RSTSTAT_OFFSET 0x0000 /* System Reset Status */ +#define XMC4_SCU_RSTSET_OFFSET 0x0004 /* Reset Set Register */ +#define XMC4_SCU_RSTCLR_OFFSET 0x0008 /* Reset Clear Register */ +#define XMC4_SCU_PRSTAT0_OFFSET 0x000c /* Peripheral Reset Status Register 0 */ +#define XMC4_SCU_PRSET0_OFFSET 0x0010 /* Peripheral Reset Set Register 0 */ +#define XMC4_SCU_PRCLR0_OFFSET 0x0014 /* Peripheral Reset Clear Register 0 */ +#define XMC4_SCU_PRSTAT1_OFFSET 0x0018 /* Peripheral Reset Status Register 1 */ +#define XMC4_SCU_PRSET1_OFFSET 0x001c /* Peripheral Reset Set Register 1 */ +#define XMC4_SCU_PRCLR1_OFFSET 0x0020 /* Peripheral Reset Clear Register 1 */ +#define XMC4_SCU_PRSTAT2_OFFSET 0x0024 /* Peripheral Reset Status Register 2 */ +#define XMC4_SCU_PRSET2_OFFSET 0x0028 /* Peripheral Reset Set Register 2 */ +#define XMC4_SCU_PRCLR2_OFFSET 0x002c /* Peripheral Reset Clear Register 2 */ +#define XMC4_SCU_PRSTAT3_OFFSET 0x0030 /* Peripheral Reset Status Register 3 */ +#define XMC4_SCU_PRSET3_OFFSET 0x0034 /* Peripheral Reset Set Register 3 */ +#define XMC4_SCU_PRCLR3_OFFSET 0x0038 /* Peripheral Reset Clear Register 3 */ + +/* Clock Control SCU Registers */ + +#define XMC4_SCU_CLKSTAT_OFFSET 0x0000 /* Clock Status Register */ +#define XMC4_SCU_CLKSET_OFFSET 0x0004 /* Clock Set Control Register */ +#define XMC4_SCU_CLKCLR_OFFSET 0x0008 /* Clock clear Control Register */ +#define XMC4_SCU_SYSCLKCR_OFFSET 0x000c /* System Clock Control */ +#define XMC4_SCU_CPUCLKCR_OFFSET 0x0010 /* CPU Clock Control */ +#define XMC4_SCU_PBCLKCR_OFFSET 0x0014 /* Peripheral Bus Clock Control */ +#define XMC4_SCU_USBCLKCR_OFFSET 0x0018 /* USB Clock Control */ +#define XMC4_SCU_EBUCLKCR_OFFSET 0x001c /* EBU Clock Control */ +#define XMC4_SCU_CCUCLKCR_OFFSET 0x0020 /* CCU Clock Control */ +#define XMC4_SCU_WDTCLKCR_OFFSET 0x0024 /* WDT Clock Control */ +#define XMC4_SCU_EXTCLKCR_OFFSET 0x0028 /* External clock Control Register */ +#define XMC4_SCU_SLEEPCR_OFFSET 0x0030 /* Sleep Control Register */ +#define XMC4_SCU_DSLEEPCR_OFFSET 0x0034 /* Deep Sleep Control Register */ +#define XMC4_SCU_CGATSTAT0_OFFSET 0x0040 /* Peripheral 0 Clock Gating Status */ +#define XMC4_SCU_CGATSET0_OFFSET 0x0044 /* Peripheral 0 Clock Gating Set */ +#define XMC4_SCU_CGATCLR0_OFFSET 0x0048 /* Peripheral 0 Clock Gating Clear */ +#define XMC4_SCU_CGATSTAT1_OFFSET 0x004c /* Peripheral 1 Clock Gating Status */ +#define XMC4_SCU_CGATSET1_OFFSET 0x0050 /* Peripheral 1 Clock Gating Set */ +#define XMC4_SCU_CGATCLR1_OFFSET 0x0054 /* Peripheral 1 Clock Gating Clear */ +#define XMC4_SCU_CGATSTAT2_OFFSET 0x0058 /* Peripheral 2 Clock Gating Status */ +#define XMC4_SCU_CGATSET2_OFFSET 0x005c /* Peripheral 2 Clock Gating Set */ +#define XMC4_SCU_CGATCLR2_OFFSET 0x0060 /* Peripheral 2 Clock Gating Clear */ +#define XMC4_SCU_CGATSTAT3_OFFSET 0x0064 /* Peripheral 3 Clock Gating Status */ +#define XMC4_SCU_CGATSET3_OFFSET 0x0068 /* Peripheral 3 Clock Gating Set */ +#define XMC4_SCU_CGATCLR3_OFFSET 0x006c /* Peripheral 3 Clock Gating Clear */ + +/* Oscillator Control SCU Registers */ + +#define XMC4_OCU_OSCHPSTAT_OFFSET 0x0000 /* OSC_HP Status Register */ +#define XMC4_OCU_OSCHPCTRL_OFFSET 0x0004 /* OSC_HP Control Register */ +#define XMC4_OCU_CLKCALCONST_OFFSET 0x000c /* Clock Calibration Constant Register */ + +/* PLL Control SCU Registers */ + +#define XMC4_SCU_PLLSTAT_OFFSET 0x0000 /* System PLL Status Register */ +#define XMC4_SCU_PLLCON0_OFFSET 0x0004 /* System PLL Configuration 0 Register */ +#define XMC4_SCU_PLLCON1_OFFSET 0x0008 /* System PLL Configuration 1 Register */ +#define XMC4_SCU_PLLCON2_OFFSET 0x000c /* System PLL Configuration 2 Register */ +#define XMC4_SCU_USBPLLSTAT_OFFSET 0x0010 /* USB PLL Status Register */ +#define XMC4_SCU_USBPLLCON_OFFSET 0x0014 /* USB PLL Control Register */ +#define XMC4_SCU_CLKMXSTAT_OFFSET 0x0028 /* Clock Multiplexing Status Register */ /* Register Addresses ***************************************************************/ - -#define XMC4_GCU_BASE (XMC4_SCU_BASE+XMC4_GCU_OFFSET) -#define XMC4_PCU_BASE (XMC4_SCU_BASE+XMC4_PCU_OFFSET) -#define XMC4_HCU_BASE (XMC4_SCU_BASE+XMC4_HCU_OFFSET) -#define XMC4_RCU_BASE (XMC4_SCU_BASE+XMC4_RCU_OFFSET) -#define XMC4_CCU_BASE (XMC4_SCU_BASE+XMC4_CCU_OFFSET) - /* General SCU Registers */ -#define XMC4_GCU_ID (XMC4_GCU_BASE+XMC4_GCU_ID_OFFSET) -#define XMC4_GCU_IDCHIP (XMC4_GCU_BASE+XMC4_GCU_IDCHIP_OFFSET) -#define XMC4_GCU_IDMANUF (XMC4_GCU_BASE+XMC4_GCU_IDMANUF_OFFSET) -#define XMC4_GCU_STCON (XMC4_GCU_BASE+XMC4_GCU_STCON_OFFSET) -#define XMC4_GCU_GPR0 (XMC4_GCU_BASE+XMC4_GCU_GPR0_OFFSET) -#define XMC4_GCU_GPR1 (XMC4_GCU_BASE+XMC4_GCU_GPR1_OFFSET) -#define XMC4_GCU_ETH0CON (XMC4_GCU_BASE+XMC4_GCU_ETH0CON_OFFSET) -#define XMC4_GCU_CCUCON (XMC4_GCU_BASE+XMC4_GCU_CCUCON_OFFSET) -#define XMC4_GCU_SRSTAT (XMC4_GCU_BASE+XMC4_GCU_SRSTAT_OFFSET) -#define XMC4_GCU_SRRAW (XMC4_GCU_BASE+XMC4_GCU_SRRAW_OFFSET) -#define XMC4_GCU_SRMSK (XMC4_GCU_BASE+XMC4_GCU_SRMSK_OFFSET) -#define XMC4_GCU_SRCLR (XMC4_GCU_BASE+XMC4_GCU_SRCLR_OFFSET) -#define XMC4_GCU_SRSET (XMC4_GCU_BASE+XMC4_GCU_SRSET_OFFSET) -#define XMC4_GCU_NMIREQEN (XMC4_GCU_BASE+XMC4_GCU_NMIREQEN_OFFSET) -#define XMC4_GCU_DTSCON (XMC4_GCU_BASE+XMC4_GCU_DTSCON_OFFSET) -#define XMC4_GCU_DTSSTAT (XMC4_GCU_BASE+XMC4_GCU_DTSSTAT_OFFSET) -#define XMC4_GCU_SDMMCDEL (XMC4_GCU_BASE+XMC4_GCU_SDMMCDEL_OFFSET) -#define XMC4_GCU_G0ORCEN (XMC4_GCU_BASE+XMC4_GCU_G0ORCEN_OFFSET) -#define XMC4_GCU_G1ORCEN (XMC4_GCU_BASE+XMC4_GCU_G1ORCEN_OFFSET) -#define XMC4_GCU_MIRRSTS (XMC4_GCU_BASE+XMC4_GCU_MIRRSTS_OFFSET) -#define XMC4_GCU_RMACR (XMC4_GCU_BASE+XMC4_GCU_RMACR_OFFSET) -#define XMC4_GCU_RMADATA (XMC4_GCU_BASE+XMC4_GCU_RMADATA_OFFSET) -#define XMC4_GCU_PEEN (XMC4_GCU_BASE+XMC4_GCU_PEEN_OFFSET) -#define XMC4_GCU_MCHKCON (XMC4_GCU_BASE+XMC4_GCU_MCHKCON_OFFSET) -#define XMC4_GCU_PETE (XMC4_GCU_BASE+XMC4_GCU_PETE_OFFSET) -#define XMC4_GCU_PERSTEN (XMC4_GCU_BASE+XMC4_GCU_PERSTEN_OFFSET) -#define XMC4_GCU_PEFLAG (XMC4_GCU_BASE+XMC4_GCU_PEFLAG_OFFSET) -#define XMC4_GCU_PMTPR (XMC4_GCU_BASE+XMC4_GCU_PMTPR_OFFSET) -#define XMC4_GCU_PMTSR (XMC4_GCU_BASE+XMC4_GCU_PMTSR_OFFSET) -#define XMC4_GCU_TRAPSTAT (XMC4_GCU_BASE+XMC4_GCU_TRAPSTAT_OFFSET) -#define XMC4_GCU_TRAPRAW (XMC4_GCU_BASE+XMC4_GCU_TRAPRAW_OFFSET) -#define XMC4_GCU_TRAPDIS (XMC4_GCU_BASE+XMC4_GCU_TRAPDIS_OFFSET) -#define XMC4_GCU_TRAPCLR (XMC4_GCU_BASE+XMC4_GCU_TRAPCLR_OFFSET) -#define XMC4_GCU_TRAPSET (XMC4_GCU_BASE+XMC4_GCU_TRAPSET_OFFSET) +#define XMC4_SCU_ID (XMC4_SCU_GENERAL_BASE+XMC4_SCU_ID_OFFSET) +#define XMC4_SCU_IDCHIP (XMC4_SCU_GENERAL_BASE+XMC4_SCU_IDCHIP_OFFSET) +#define XMC4_SCU_IDMANUF (XMC4_SCU_GENERAL_BASE+XMC4_SCU_IDMANUF_OFFSET) +#define XMC4_SCU_STCON (XMC4_SCU_GENERAL_BASE+XMC4_SCU_STCON_OFFSET) +#define XMC4_SCU_GPR0 (XMC4_SCU_GENERAL_BASE+XMC4_SCU_GPR0_OFFSET) +#define XMC4_SCU_GPR1 (XMC4_SCU_GENERAL_BASE+XMC4_SCU_GPR1_OFFSET) +#define XMC4_SCU_ETH0CON (XMC4_SCU_GENERAL_BASE+XMC4_SCU_ETH0CON_OFFSET) +#define XMC4_SCU_CCUCON (XMC4_SCU_GENERAL_BASE+XMC4_SCU_CCUCON_OFFSET) +#define XMC4_SCU_DTSCON (XMC4_SCU_GENERAL_BASE+XMC4_SCU_DTSCON_OFFSET) +#define XMC4_SCU_DTSSTAT (XMC4_SCU_GENERAL_BASE+XMC4_SCU_DTSSTAT_OFFSET) +#define XMC4_SCU_SDMMCDEL (XMC4_SCU_GENERAL_BASE+XMC4_SCU_SDMMCDEL_OFFSET) +#define XMC4_SCU_G0ORCEN (XMC4_SCU_GENERAL_BASE+XMC4_SCU_G0ORCEN_OFFSET) +#define XMC4_SCU_G1ORCEN (XMC4_SCU_GENERAL_BASE+XMC4_SCU_G1ORCEN_OFFSET) +#define XMC4_SCU_MIRRSTS (XMC4_SCU_GENERAL_BASE+XMC4_SCU_MIRRSTS_OFFSET) +#define XMC4_SCU_RMACR (XMC4_SCU_GENERAL_BASE+XMC4_SCU_RMACR_OFFSET) +#define XMC4_SCU_RMADATA (XMC4_SCU_GENERAL_BASE+XMC4_SCU_RMADATA_OFFSET) -/* PCU Registers */ +/* Ethernet Control SCU Registers */ -#define XMC4_PCU_PWRSTAT (XMC4_PCU_BASE+XMC4_PCU_PWRSTAT_OFFSET) -#define XMC4_PCU_PWRSET (XMC4_PCU_BASE+XMC4_PCU_PWRSET_OFFSET) -#define XMC4_PCU_PWRCLR (XMC4_PCU_BASE+XMC4_PCU_PWRCLR_OFFSET) -#define XMC4_PCU_EVRSTAT (XMC4_PCU_BASE+XMC4_PCU_EVRSTAT_OFFSET) -#define XMC4_PCU_EVRVADCSTAT (XMC4_PCU_BASE+XMC4_PCU_EVRVADCSTAT_OFFSET) -#define XMC4_PCU_PWRMON (XMC4_PCU_BASE+XMC4_PCU_PWRMON_OFFSET) +#define XMC4_SCU_ETHCON (XMC4_ETH0_CON_BASE+XMC4_SCU_ETHCON_OFFSET) -/* HCU Registers */ +/* Parity Control Registers */ -#define XMC4_HCU_HDSTAT (XMC4_HCU_BASE+XMC4_HCU_HDSTAT_OFFSET) -#define XMC4_HCU_HDCLR (XMC4_HCU_BASE+XMC4_HCU_HDCLR_OFFSET) -#define XMC4_HCU_HDSET (XMC4_HCU_BASE+XMC4_HCU_HDSET_OFFSET) -#define XMC4_HCU_HDCR (XMC4_HCU_BASE+XMC4_HCU_HDCR_OFFSET) -#define XMC4_HCU_OSCSICTRL (XMC4_HCU_BASE+XMC4_HCU_OSCSICTRL_OFFSET) -#define XMC4_HCU_OSCULSTAT (XMC4_HCU_BASE+XMC4_HCU_OSCULSTAT_OFFSET) -#define XMC4_HCU_OSCULCTRL (XMC4_HCU_BASE+XMC4_HCU_OSCULCTRL_OFFSET) +#define XMC4_SCU_PEEN (XMC4_SCU_PARITY_BASE+XMC4_SCU_PEEN_OFFSET) +#define XMC4_SCU_MCHKCON (XMC4_SCU_PARITY_BASE+XMC4_SCU_MCHKCON_OFFSET) +#define XMC4_SCU_PETE (XMC4_SCU_PARITY_BASE+XMC4_SCU_PETE_OFFSET) +#define XMC4_SCU_PERSTEN (XMC4_SCU_PARITY_BASE+XMC4_SCU_PERSTEN_OFFSET) +#define XMC4_SCU_PEFLAG (XMC4_SCU_PARITY_BASE+XMC4_SCU_PEFLAG_OFFSET) +#define XMC4_SCU_PMTPR (XMC4_SCU_PARITY_BASE+XMC4_SCU_PMTPR_OFFSET) +#define XMC4_SCU_PMTSR (XMC4_SCU_PARITY_BASE+XMC4_SCU_PMTSR_OFFSET) -/* RCU Registers */ +/* Trap Control Registers */ -#define XMC4_RCU_RSTSTAT (XMC4_RCU_BASE+XMC4_RCU_RSTSTAT_OFFSET) -#define XMC4_RCU_RSTSET (XMC4_RCU_BASE+XMC4_RCU_RSTSET_OFFSET) -#define XMC4_RCU_RSTCLR (XMC4_RCU_BASE+XMC4_RCU_RSTCLR_OFFSET) -#define XMC4_RCU_PRSTAT0 (XMC4_RCU_BASE+XMC4_RCU_PRSTAT0_OFFSET) -#define XMC4_RCU_PRSET0 (XMC4_RCU_BASE+XMC4_RCU_PRSET0_OFFSET) -#define XMC4_RCU_PRCLR0 (XMC4_RCU_BASE+XMC4_RCU_PRCLR0_OFFSET) -#define XMC4_RCU_PRSTAT1 (XMC4_RCU_BASE+XMC4_RCU_PRSTAT1_OFFSET) -#define XMC4_RCU_PRSET1 (XMC4_RCU_BASE+XMC4_RCU_PRSET1_OFFSET) -#define XMC4_RCU_PRCLR1 (XMC4_RCU_BASE+XMC4_RCU_PRCLR1_OFFSET) -#define XMC4_RCU_PRSTAT2 (XMC4_RCU_BASE+XMC4_RCU_PRSTAT2_OFFSET) -#define XMC4_RCU_PRSET2 (XMC4_RCU_BASE+XMC4_RCU_PRSET2_OFFSET) -#define XMC4_RCU_PRCLR2 (XMC4_RCU_BASE+XMC4_RCU_PRCLR2_OFFSET) -#define XMC4_RCU_PRSTAT3 (XMC4_RCU_BASE+XMC4_RCU_PRSTAT3_OFFSET) -#define XMC4_RCU_PRSET3 (XMC4_RCU_BASE+XMC4_RCU_PRSET3_OFFSET) -#define XMC4_RCU_PRCLR3 (XMC4_RCU_BASE+XMC4_RCU_PRCLR3_OFFSET) +#define XMC4_SCU_TRAPSTAT (XMC4_SCU_TRAP_BASE+XMC4_SCU_TRAPSTAT_OFFSET) +#define XMC4_SCU_TRAPRAW (XMC4_SCU_TRAP_BASE+XMC4_SCU_TRAPRAW_OFFSET) +#define XMC4_SCU_TRAPDIS (XMC4_SCU_TRAP_BASE+XMC4_SCU_TRAPDIS_OFFSET) +#define XMC4_SCU_TRAPCLR (XMC4_SCU_TRAP_BASE+XMC4_SCU_TRAPCLR_OFFSET) +#define XMC4_SCU_TRAPSET (XMC4_SCU_TRAP_BASE+XMC4_SCU_TRAPSET_OFFSET) -/* CCU Registers */ +/* Ethernet Control SCU Resters */ -#define XMC4_CCU_CLKSTAT (XMC4_CCU_BASE+XMC4_CCU_CLKSTAT_OFFSET) -#define XMC4_CCU_CLKSET (XMC4_CCU_BASE+XMC4_CCU_CLKSET_OFFSET) -#define XMC4_CCU_CLKCLR (XMC4_CCU_BASE+XMC4_CCU_CLKCLR_OFFSET) -#define XMC4_CCU_SYSCLKCR (XMC4_CCU_BASE+XMC4_CCU_SYSCLKCR_OFFSET) -#define XMC4_CCU_CPUCLKCR (XMC4_CCU_BASE+XMC4_CCU_CPUCLKCR_OFFSET) -#define XMC4_CCU_PBCLKCR (XMC4_CCU_BASE+XMC4_CCU_PBCLKCR_OFFSET) -#define XMC4_CCU_USBCLKCR (XMC4_CCU_BASE+XMC4_CCU_USBCLKCR_OFFSET) -#define XMC4_CCU_EBUCLKCR (XMC4_CCU_BASE+XMC4_CCU_EBUCLKCR_OFFSET) -#define XMC4_CCU_CCUCLKCR (XMC4_CCU_BASE+XMC4_CCU_CCUCLKCR_OFFSET) -#define XMC4_CCU_WDTCLKCR (XMC4_CCU_BASE+XMC4_CCU_WDTCLKCR_OFFSET) -#define XMC4_CCU_EXTCLKCR (XMC4_CCU_BASE+XMC4_CCU_EXTCLKCR_OFFSET) -#define XMC4_CCU_SLEEPCR (XMC4_CCU_BASE+XMC4_CCU_SLEEPCR_OFFSET) -#define XMC4_CCU_DSLEEPCR (XMC4_CCU_BASE+XMC4_CCU_DSLEEPCR_OFFSET) -#define XMC4_CCU_OSCHPSTAT (XMC4_CCU_BASE+XMC4_CCU_OSCHPSTAT_OFFSET) -#define XMC4_CCU_OSCHPCTRL (XMC4_CCU_BASE+XMC4_CCU_OSCHPCTRL_OFFSET) -#define XMC4_CCU_CLKCALCONST (XMC4_CCU_BASE+XMC4_CCU_CLKCALCONST_OFFSET) -#define XMC4_CCU_PLLSTAT (XMC4_CCU_BASE+XMC4_CCU_PLLSTAT_OFFSET) -#define XMC4_CCU_PLLCON0 (XMC4_CCU_BASE+XMC4_CCU_PLLCON0_OFFSET) -#define XMC4_CCU_PLLCON1 (XMC4_CCU_BASE+XMC4_CCU_PLLCON1_OFFSET) -#define XMC4_CCU_PLLCON2 (XMC4_CCU_BASE+XMC4_CCU_PLLCON2_OFFSET) -#define XMC4_CCU_USBPLLSTAT (XMC4_CCU_BASE+XMC4_CCU_USBPLLSTAT_OFFSET) -#define XMC4_CCU_USBPLLCON (XMC4_CCU_BASE+XMC4_CCU_USBPLLCON_OFFSET) -#define XMC4_CCU_CLKMXSTAT (XMC4_CCU_BASE+XMC4_CCU_CLKMXSTAT_OFFSET) +#define XMC4_SCU_ETHCON_OFFSET 0x0000 /* Ethernet 0 Port Control Register */ +#define XMC4_SCU_ETHCON_OFFSET 0x0000 /* Ethernet 0 Port Control Register */ + +/* Interrupt Control SCU Registers */ + +#define XMC4_SCU_SRSTAT (XMC4_SCU_INTERRUPT_BASE+XMC4_SCU_SRSTAT_OFFSET) +#define XMC4_SCU_SRRAW (XMC4_SCU_INTERRUPT_BASE+XMC4_SCU_SRRAW_OFFSET) +#define XMC4_SCU_SRMSK (XMC4_SCU_INTERRUPT_BASE+XMC4_SCU_SRMSK_OFFSET) +#define XMC4_SCU_SRCLR (XMC4_SCU_INTERRUPT_BASE+XMC4_SCU_SRCLR_OFFSET) +#define XMC4_SCU_SRSET (XMC4_SCU_INTERRUPT_BASE+XMC4_SCU_SRSET_OFFSET) +#define XMC4_SCU_NMIREQEN (XMC4_SCU_INTERRUPT_BASE+XMC4_SCU_NMIREQEN_OFFSET) + +/* SDMMC Control SCU Registers */ + +#define XMC4_SCU_SDMMCCON (XMC4_SDMMC_CON_BASE+XMC4_SCU_SDMMCCON_OFFSET) + +/* Power control SCU Registers */ + +#define XMC4_SCU_PWRSTAT (XMC4_SCU_POWER_BASE+XMC4_SCU_PWRSTAT_OFFSET) +#define XMC4_SCU_PWRSET (XMC4_SCU_POWER_BASE+XMC4_SCU_PWRSET_OFFSET) +#define XMC4_SCU_PWRCLR (XMC4_SCU_POWER_BASE+XMC4_SCU_PWRCLR_OFFSET) +#define XMC4_SCU_EVRSTAT (XMC4_SCU_POWER_BASE+XMC4_SCU_EVRSTAT_OFFSET) +#define XMC4_SCU_EVRVADCSTAT (XMC4_SCU_POWER_BASE+XMC4_SCU_EVRVADCSTAT_OFFSET) +#define XMC4_SCU_PWRMON (XMC4_SCU_POWER_BASE+XMC4_SCU_PWRMON_OFFSET) + +/* Hibernation SCU Registers */ + +#define XMC4_SCU_HDSTAT (XMC4_SCU_HIBERNATE_BASE+XMC4_SCU_HDSTAT_OFFSET) +#define XMC4_SCU_HDCLR (XMC4_SCU_HIBERNATE_BASE+XMC4_SCU_HDCLR_OFFSET) +#define XMC4_SCU_HDSET (XMC4_SCU_HIBERNATE_BASE+XMC4_SCU_HDSET_OFFSET) +#define XMC4_SCU_HDCR (XMC4_SCU_HIBERNATE_BASE+XMC4_SCU_HDCR_OFFSET) +#define XMC4_SCU_OSCSICTRL (XMC4_SCU_HIBERNATE_BASE+XMC4_SCU_OSCSICTRL_OFFSET) +#define XMC4_SCU_OSCULSTAT (XMC4_SCU_HIBERNATE_BASE+XMC4_SCU_OSCULSTAT_OFFSET) +#define XMC4_SCU_OSCULCTRL (XMC4_SCU_HIBERNATE_BASE+XMC4_SCU_OSCULCTRL_OFFSET) + +/* Reset SCU Registers */ + +#define XMC4_SCU_RSTSTAT (XMC4_SCU_RESET_BASE+XMC4_SCU_RSTSTAT_OFFSET) +#define XMC4_SCU_RSTSET (XMC4_SCU_RESET_BASE+XMC4_SCU_RSTSET_OFFSET) +#define XMC4_SCU_RSTCLR (XMC4_SCU_RESET_BASE+XMC4_SCU_RSTCLR_OFFSET) +#define XMC4_SCU_PRSTAT0 (XMC4_SCU_RESET_BASE+XMC4_SCU_PRSTAT0_OFFSET) +#define XMC4_SCU_PRSET0 (XMC4_SCU_RESET_BASE+XMC4_SCU_PRSET0_OFFSET) +#define XMC4_SCU_PRCLR0 (XMC4_SCU_RESET_BASE+XMC4_SCU_PRCLR0_OFFSET) +#define XMC4_SCU_PRSTAT1 (XMC4_SCU_RESET_BASE+XMC4_SCU_PRSTAT1_OFFSET) +#define XMC4_SCU_PRSET1 (XMC4_SCU_RESET_BASE+XMC4_SCU_PRSET1_OFFSET) +#define XMC4_SCU_PRCLR1 (XMC4_SCU_RESET_BASE+XMC4_SCU_PRCLR1_OFFSET) +#define XMC4_SCU_PRSTAT2 (XMC4_SCU_RESET_BASE+XMC4_SCU_PRSTAT2_OFFSET) +#define XMC4_SCU_PRSET2 (XMC4_SCU_RESET_BASE+XMC4_SCU_PRSET2_OFFSET) +#define XMC4_SCU_PRCLR2 (XMC4_SCU_RESET_BASE+XMC4_SCU_PRCLR2_OFFSET) +#define XMC4_SCU_PRSTAT3 (XMC4_SCU_RESET_BASE+XMC4_SCU_PRSTAT3_OFFSET) +#define XMC4_SCU_PRSET3 (XMC4_SCU_RESET_BASE+XMC4_SCU_PRSET3_OFFSET) +#define XMC4_SCU_PRCLR3 (XMC4_SCU_RESET_BASE+XMC4_SCU_PRCLR3_OFFSET) + +/* Clock Control SCU Registers */ + +#define XMC4_SCU_CLKSTAT (XMC4_SCU_CLK_BASE+XMC4_SCU_CLKSTAT_OFFSET) +#define XMC4_SCU_CLKSET (XMC4_SCU_CLK_BASE+XMC4_SCU_CLKSET_OFFSET) +#define XMC4_SCU_CLKCLR (XMC4_SCU_CLK_BASE+XMC4_SCU_CLKCLR_OFFSET) +#define XMC4_SCU_SYSCLKCR (XMC4_SCU_CLK_BASE+XMC4_SCU_SYSCLKCR_OFFSET) +#define XMC4_SCU_CPUCLKCR (XMC4_SCU_CLK_BASE+XMC4_SCU_CPUCLKCR_OFFSET) +#define XMC4_SCU_PBCLKCR (XMC4_SCU_CLK_BASE+XMC4_SCU_PBCLKCR_OFFSET) +#define XMC4_SCU_USBCLKCR (XMC4_SCU_CLK_BASE+XMC4_SCU_USBCLKCR_OFFSET) +#define XMC4_SCU_EBUCLKCR (XMC4_SCU_CLK_BASE+XMC4_SCU_EBUCLKCR_OFFSET) +#define XMC4_SCU_CCUCLKCR (XMC4_SCU_CLK_BASE+XMC4_SCU_CCUCLKCR_OFFSET) +#define XMC4_SCU_WDTCLKCR (XMC4_SCU_CLK_BASE+XMC4_SCU_WDTCLKCR_OFFSET) +#define XMC4_SCU_EXTCLKCR (XMC4_SCU_CLK_BASE+XMC4_SCU_EXTCLKCR_OFFSET) +#define XMC4_SCU_SLEEPCR (XMC4_SCU_CLK_BASE+XMC4_SCU_SLEEPCR_OFFSET) +#define XMC4_SCU_DSLEEPCR (XMC4_SCU_CLK_BASE+XMC4_SCU_DSLEEPCR_OFFSET) +#define XMC4_SCU_CGATSTAT0 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATSTAT0_OFFSET) +#define XMC4_SCU_CGATSET0 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATSET0_OFFSET) +#define XMC4_SCU_CGATCLR0 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATCLR0_OFFSET) +#define XMC4_SCU_CGATSTAT1 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATSTAT1_OFFSET) +#define XMC4_SCU_CGATSET1 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATSET1_OFFSET) +#define XMC4_SCU_CGATCLR1 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATCLR1_OFFSET) +#define XMC4_SCU_CGATSTAT2 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATSTAT2_OFFSET) +#define XMC4_SCU_CGATSET2 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATSET2_OFFSET +#define XMC4_SCU_CGATCLR2 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATCLR2_OFFSET +#define XMC4_SCU_CGATSTAT3 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATSTAT3_OFFSET +#define XMC4_SCU_CGATSET3 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATSET3_OFFSET +#define XMC4_SCU_CGATCLR3 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATCLR3_OFFSET_ + +/* Oscillator Control SCU Registers */ + +#define XMC4_OSCU_OSCHPSTAT (XMC4_SCU_OSC_BASE+XMC4_OSCU_OSCHPSTAT_OFFSET) +#define XMC4_OSCU_OSCHPCTRL (XMC4_SCU_OSC_BASE+XMC4_OSCU_OSCHPCTRL_OFFSET) +#define XMC4_OSCU_CLKCALCONST (XMC4_SCU_OSC_BASE+XMC4_OSCU_CLKCALCONST_OFFSET) + +/* PLL Control SCU Registers */ + +#define XMC4_SCU_PLLSTAT (XMC4_SCU_PLL_BASE+XMC4_SCU_PLLSTAT_OFFSET) +#define XMC4_SCU_PLLCON0 (XMC4_SCU_PLL_BASE+XMC4_SCU_PLLCON0_OFFSET) +#define XMC4_SCU_PLLCON1 (XMC4_SCU_PLL_BASE+XMC4_SCU_PLLCON1_OFFSET) +#define XMC4_SCU_PLLCON2 (XMC4_SCU_PLL_BASE+XMC4_SCU_PLLCON2_OFFSET) +#define XMC4_SCU_USBPLLSTAT (XMC4_SCU_PLL_BASE+XMC4_SCU_USBPLLSTAT_OFFSET) +#define XMC4_SCU_USBPLLCON (XMC4_SCU_PLL_BASE+XMC4_SCU_USBPLLCON_OFFSET) +#define XMC4_SCU_CLKMXSTAT (XMC4_SCU_PLL_BASE+XMC4_SCU_CLKMXSTAT_OFFSET) /* Register Bit-Field Definitions ***************************************************/ /* General SCU Registers */ /* Module Identification Register */ -#define GCU_ID_ +#define SCU_ID_ /* Chip ID */ -#define GCU_IDCHIP_ +#define SCU_IDCHIP_ /* Manufactory ID */ -#define GCU_IDMANUF_ +#define SCU_IDMANUF_ /* Start-up Control */ -#define GCU_STCON_ +#define SCU_STCON_ /* General Purpose Register 0 */ -#define GCU_GPR0_ +#define SCU_GPR0_ /* General Purpose Register 1 */ -#define GCU_GPR1_ +#define SCU_GPR1_ /* Ethernet 0 Port Control */ -#define GCU_ETH0CON_ +#define SCU_ETH0CON_ /* CCUx Global Start Control Register */ -#define GCU_CCUCON_ -/* Service Request Status */ -#define GCU_SRSTAT_ -/* RAW Service Request Status */ -#define GCU_SRRAW_ -/* Service Request Mask */ -#define GCU_SRMSK_ -/* Service Request Clear */ -#define GCU_SRCLR_ -/* Service Request Set */ -#define GCU_SRSET_ -/* Enable Promoting Events to NMI Request */ -#define GCU_NMIREQEN_ +#define SCU_CCUCON_ /* DTS Control */ -#define GCU_DTSCON_ +#define SCU_DTSCON_ /* DTS Status */ -#define GCU_DTSSTAT_ -/* SD-MMC Delay Control Register */ -#define GCU_SDMMCDEL_ +#define SCU_DTSSTAT_ +/* SD-MMC Delay Control Register */ +#define SCU_SDMMCDEL_ /* Out-Of-Range Comparator Enable Register 0 */ -#define GCU_G0ORCEN_ +#define SCU_G0ORCEN_ /* Out-Of-Range Comparator Enable Register 1 */ -#define GCU_G1ORCEN_ +#define SCU_G1ORCEN_ /* Mirror Update Status Register */ -#define GCU_MIRRSTS_ -/* Retention Memory Access Control Register */ -#define GCU_RMACR_ -/* Retention Memory Access Data Register */ -#define GCU_RMADATA_ -/* Parity Error Enable Register */ -#define GCU_PEEN_ -/* Memory Checking Control Register */ -#define GCU_MCHKCON_ -/* Parity Error Trap Enable Register */ -#define GCU_PETE_ -/* Reset upon Parity Error Enable Register */ -#define GCU_PERSTEN_ -/* Parity Error Control Register */ -#define GCU_PEFLAG_ -/* Parity Memory Test Pattern Register */ -#define GCU_PMTPR_ -/* Parity Memory Test Select Register */ -#define GCU_PMTSR_ -/* Trap Status Register */ -#define GCU_TRAPSTAT_ -/* Trap Raw Status Register */ -#define GCU_TRAPRAW_ -/* Trap Mask Register */ -#define GCU_TRAPDIS_ -/* Trap Clear Register */ -#define GCU_TRAPCLR_ -/* Trap Set Register */ -#define GCU_TRAPSET_ +#define SCU_MIRRSTS_ -/* PCU Registers */ +/* Ethernet Control SCU Resters */ + +/* Ethernet 0 Port Control Register */ +#define SCU_ETHCON_ + +/* Interrupt Control SCU Registers */ + +/* Service Request Status */ +#define SCU_SRSTAT_ +/* RAW Service Request Status */ +#define SCU_SRRAW_ +/* Service Request Mask */ +#define SCU_SRMSK_ +/* Service Request Clear */ +#define SCU_SRCLR_ +/* Service Request Set */ +#define SCU_SRSET_ +/* Enable Promoting Events to NMI Request */ +#define SCU_NMIREQEN_ +/* Retention Memory Access Control Register */ +#define SCU_RMACR_ +/* Retention Memory Access Data Register */ +#define SCU_RMADATA_ +/* Parity Error Enable Register */ + +/* SDMMC Control SCU Registers */ + +/* SDMMC Configuration */ +#define SCU_SDMMCCON_ + +/* Parity Control Registers */ + +#define SCU_PEEN_ +/* Memory Checking Control Register */ +#define SCU_MCHKCON_ +/* Parity Error Trap Enable Register */ +#define SCU_PETE_ +/* Reset upon Parity Error Enable Register */ +#define SCU_PERSTEN_ +/* Parity Error Control Register */ +#define SCU_PEFLAG_ +/* Parity Memory Test Pattern Register */ +#define SCU_PMTPR_ +/* Parity Memory Test Select Register */ +#define SCU_PMTSR_ + +/* Trap Control Registers */ + +/* Trap Status Register */ +#define SCU_TRAPSTAT_ +/* Trap Raw Status Register */ +#define SCU_TRAPRAW_ +/* Trap Mask Register */ +#define SCU_TRAPDIS_ +/* Trap Clear Register */ +#define SCU_TRAPCLR_ +/* Trap Set Register */ +#define SCU_TRAPSET_ + +/* Power Control SCU Registers */ /* Power Status Register */ -#define PCU_PWRSTAT_ +#define SCU_PWRSTAT_ /* Power Set Control Register */ -#define PCU_PWRSET_ +#define SCU_PWRSET_ /* Power Clear Control Register */ -#define PCU_PWRCLR_ +#define SCU_PWRCLR_ /* EVR Status Register */ -#define PCU_EVRSTAT_ +#define SCU_EVRSTAT_ /* EVR VADC Status Register */ -#define PCU_EVRVADCSTAT_ +#define SCU_EVRVADCSTAT_ /* Power Monitor Value */ -#define PCU_PWRMON_ +#define SCU_PWRMON_ /* HCU Registers */ /* Hibernate Domain Status Register */ -#define HCU_HDSTAT_ +#define SCU_HDSTAT_ /* Hibernate Domain Status Clear Register */ -#define HCU_HDCLR_ +#define SCU_HDCLR_ /* Hibernate Domain Status Set Register */ -#define HCU_HDSET_ +#define SCU_HDSET_ /* Hibernate Domain Control Register */ -#define HCU_HDCR_ +#define SCU_HDCR_ /* Internal 32.768 kHz Clock Source Control Register */ -#define HCU_OSCSICTRL_ +#define SCU_OSCSICTRL_ /* OSC_ULP Status Register */ -#define HCU_OSCULSTAT_ +#define SCU_OSCULSTAT_ /* OSC_ULP Control Register */ -#define HCU_OSCULCTRL_ +#define SCU_OSCULCTRL_ -/* RCU Registers */ +/* Reset SCU Registers */ /* System Reset Status */ -#define RCU_RSTSTAT_ +#define SCU_RSTSTAT_ /* Reset Set Register */ -#define RCU_RSTSET_ +#define SCU_RSTSET_ /* Reset Clear Register */ -#define RCU_RSTCLR_ +#define SCU_RSTCLR_ /* Peripheral Reset Status Register 0 */ -#define RCU_PRSTAT0_ +#define SCU_PRSTAT0_ /* Peripheral Reset Set Register 0 */ -#define RCU_PRSET0_ +#define SCU_PRSET0_ /* Peripheral Reset Clear Register 0 */ -#define RCU_PRCLR0_ +#define SCU_PRCLR0_ /* Peripheral Reset Status Register 1 */ -#define RCU_PRSTAT1_ +#define SCU_PRSTAT1_ /* Peripheral Reset Set Register 1 */ -#define RCU_PRSET1_ +#define SCU_PRSET1_ /* Peripheral Reset Clear Register 1 */ -#define RCU_PRCLR1_ +#define SCU_PRCLR1_ /* Peripheral Reset Status Register 2 */ -#define RCU_PRSTAT2_ +#define SCU_PRSTAT2_ /* Peripheral Reset Set Register 2 */ -#define RCU_PRSET2_ +#define SCU_PRSET2_ /* Peripheral Reset Clear Register 2 */ -#define RCU_PRCLR2_ +#define SCU_PRCLR2_ /* Peripheral Reset Status Register 3 */ -#define RCU_PRSTAT3_ +#define SCU_PRSTAT3_ /* Peripheral Reset Set Register 3 */ -#define RCU_PRSET3_ +#define SCU_PRSET3_ /* Peripheral Reset Clear Register 3 */ -#define RCU_PRCLR3_ +#define SCU_PRCLR3_ -/* CCU Registers */ +/* Clock Control SCU Registers */ /* Clock Status Register */ -#define CCU_CLKSTAT_ +#define SCU_CLKSTAT_ /* Clock Set Control Register */ -#define CCU_CLKSET_ +#define SCU_CLKSET_ /* Clock clear Control Register */ -#define CCU_CLKCLR_ +#define SCU_CLKCLR_ /* System Clock Control */ -#define CCU_SYSCLKCR_ +#define SCU_SYSCLKCR_ /* CPU Clock Control */ -#define CCU_CPUCLKCR_ +#define SCU_CPUCLKCR_ /* Peripheral Bus Clock Control */ -#define CCU_PBCLKCR_ +#define SCU_PBCLKCR_ /* USB Clock Control */ -#define CCU_USBCLKCR_ +#define SCU_USBCLKCR_ /* EBU Clock Control */ -#define CCU_EBUCLKCR_ +#define SCU_EBUCLKCR_ /* CCU Clock Control */ -#define CCU_CCUCLKCR_ +#define SCU_CCUCLKCR_ /* WDT Clock Control */ -#define CCU_WDTCLKCR_ +#define SCU_WDTCLKCR_ /* External clock Control Register */ -#define CCU_EXTCLKCR_ +#define SCU_EXTCLKCR_ /* Sleep Control Register */ -#define CCU_SLEEPCR_ +#define SCU_SLEEPCR_ /* Deep Sleep Control Register */ -#define CCU_DSLEEPCR_ +#define SCU_DSLEEPCR_ +/* Peripheral 0 Clock Gating Status */ +#define SCU_CGATSTAT0_ +/* Peripheral 0 Clock Gating Set */ +#define SCU_CGATSET0_ +/* Peripheral 0 Clock Gating Clear */ +#define SCU_CGATCLR0_ +/* Peripheral 1 Clock Gating Status */ +#define SCU_CGATSTAT1_ +/* Peripheral 1 Clock Gating Set */ +#define SCU_CGATSET1_ +/* Peripheral 1 Clock Gating Clear */ +#define SCU_CGATCLR1_ +/* Peripheral 2 Clock Gating Status */ +#define SCU_CGATSTAT2_ +/* Peripheral 2 Clock Gating Set */ +#define SCU_CGATSET2_ +/* Peripheral 2 Clock Gating Clear */ +#define SCU_CGATCLR2_ +/* Peripheral 3 Clock Gating Status */ +#define SCU_CGATSTAT3_ +/* Peripheral 3 Clock Gating Set */ +#define SCU_CGATSET3_ +/* Peripheral 3 Clock Gating Clear */ +#define SCU_CGATCLR3_ + +/* Oscillator Control SCU Registers */ + /* OSC_HP Status Register */ -#define CCU_OSCHPSTAT_ +#define OSCU_OSCHPSTAT_ /* OSC_HP Control Register */ -#define CCU_OSCHPCTRL_ +#define OSCU_OSCHPCTRL_ /* Clock Calibration Constant Register */ -#define CCU_CLKCALCONST_ +#define OSCU_CLKCALCONST_ + +/* PLL Control SCU Registers */ + /* System PLL Status Register */ -#define CCU_PLLSTAT_ +#define SCU_PLLSTAT_ /* System PLL Configuration 0 Register */ -#define CCU_PLLCON0_ +#define SCU_PLLCON0_ /* System PLL Configuration 1 Register */ -#define CCU_PLLCON1_ +#define SCU_PLLCON1_ /* System PLL Configuration 2 Register */ -#define CCU_PLLCON2_ +#define SCU_PLLCON2_ /* USB PLL Status Register */ -#define CCU_USBPLLSTAT_ +#define SCU_USBPLLSTAT_ /* USB PLL Control Register */ -#define CCU_USBPLLCON_ +#define SCU_USBPLLCON_ /* Clock Multiplexing Status Register */ -#define CCU_CLKMXSTAT_ +#define SCU_CLKMXSTAT_ #endif /* __ARCH_ARM_SRC_XMC4_CHIP_XMC4_SCU_H */ From 77f244ed7b848195b24556f4cfc070fe42a108e8 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 15 Mar 2017 10:22:24 -0600 Subject: [PATCH 06/81] XMC4xx: Add logic to get the CPU frequency. --- arch/arm/src/xmc4/chip/xmc4_scu.h | 52 ++++++++- arch/arm/src/xmc4/xmc4_clockconfig.c | 110 +++++++++++++++++-- arch/arm/src/xmc4/xmc4_clockconfig.h | 79 ++++++++++++++ arch/arm/src/xmc4/xmc4_start.c | 4 +- arch/arm/src/xmc4/xmc4_start.h | 61 +++++++++++ configs/xmc4500-relax/include/board.h | 150 ++++++++++++++++++++++++++ 6 files changed, 442 insertions(+), 14 deletions(-) create mode 100644 arch/arm/src/xmc4/xmc4_clockconfig.h create mode 100644 arch/arm/src/xmc4/xmc4_start.h create mode 100644 configs/xmc4500-relax/include/board.h diff --git a/arch/arm/src/xmc4/chip/xmc4_scu.h b/arch/arm/src/xmc4/chip/xmc4_scu.h index ab5b7719953..e9370565ba9 100644 --- a/arch/arm/src/xmc4/chip/xmc4_scu.h +++ b/arch/arm/src/xmc4/chip/xmc4_scu.h @@ -505,10 +505,21 @@ #define SCU_CLKSET_ /* Clock clear Control Register */ #define SCU_CLKCLR_ + /* System Clock Control */ -#define SCU_SYSCLKCR_ + +#define SCU_SYSCLKCR_SYSDIV_SHIFT (0) /* Bits 0-7: System Clock Division Value */ +#define SCU_SYSCLKCR_SYSDIV_MASK (0xff << SCU_CLK_SYSCLKCR_SYSDIV_SHIFT) +# define SCU_SYSCLKCR_SYSDIV(n) ((uint32_t)((n)-1) << SCU_CLK_SYSCLKCR_SYSDIV_SHIFT) + +#define SCU_SYSCLKCR_SYSSEL (1 << 16) /* Bit 16: System Clock Selection Value */ +# define SCU_SYSCLKCR_SYSSEL_OFI (0) /* 0=OFI clock */ +# define SCU_SYSCLKCR_SYSSEL_PLL (1 << 16) /* 1=PLL clock */ + /* CPU Clock Control */ -#define SCU_CPUCLKCR_ + +#define SCU_CPUCLKCR_CPUDIV (1 << 0) /* Bit 0: CPU Clock Divider Enable */ + /* Peripheral Bus Clock Control */ #define SCU_PBCLKCR_ /* USB Clock Control */ @@ -562,13 +573,44 @@ /* PLL Control SCU Registers */ /* System PLL Status Register */ -#define SCU_PLLSTAT_ + +#define SCU_PLLSTAT_VCOBYST (1 << 0) /* Bit 0: VCO Bypass Status */ +#define SCU_PLLSTAT_PWDSTAT (1 << 1) /* Bit 1: PLL Power-saving Mode Status */ +#define SCU_PLLSTAT_VCOLOCK (1 << 2) /* Bit 2: PLL LOCK Status */ +#define SCU_PLLSTAT_K1RDY (1 << 4) /* Bit 4: K1 Divider Ready Status */ +#define SCU_PLLSTAT_K2RDY (1 << 5) /* Bit 5: K2 Divider Ready Status */ +#define SCU_PLLSTAT_BY (1 << 6) /* Bit 6: Bypass Mode Status */ +#define SCU_PLLSTAT_PLLLV (1 << 7) /* Bit 7: Oscillator for PLL Valid Low Status */ +#define SCU_PLLSTAT_PLLHV (1 << 8) /* Bit 8: Oscillator for PLL Valid High Status */ +#define SCU_PLLSTAT_PLLSP (1 << 9) /* Bit 9: Oscillator for PLL Valid Spike Status */ + /* System PLL Configuration 0 Register */ #define SCU_PLLCON0_ + /* System PLL Configuration 1 Register */ -#define SCU_PLLCON1_ + +#define SCU_PLLCON1_K1DIV_SHIFT (0) /* Bits 0-6: K1-Divider Value */ +#define SCU_PLLCON1_K1DIV_MASK (0x7f << SCU_PLLCON1_K1DIV_SHIFT) +# define SCU_PLLCON1_K1DIV(n) ((uint32_t)((n)-1) << SCU_PLLCON1_K1DIV_SHIFT) +#define SCU_PLLCON1_NDIV_SHIFT (8) /* Bits 8-14: N-Divider Value */ +#define SCU_PLLCON1_NDIV_MASK (0x7f << SCU_PLLCON1_NDIV_SHIFT) +# define SCU_PLLCON1_NDIV(n) ((uint32_t)((n)-1) << SCU_PLLCON1_NDIV_SHIFT) +#define SCU_PLLCON1_K2DIV_SHIFT (16) /* Bit 16-22: K2-Divider Value */ +#define SCU_PLLCON1_K2DIV_MASK (0x7f << SCU_PLLCON1_K2DIV_SHIFT) +# define SCU_PLLCON1_K2DIV(n) ((uint32_t)((n)-1) << SCU_PLLCON1_K2DIV_SHIFT) +#define SCU_PLLCON1_PDIV_SHIFT (24) /* Bits 24-27: P-Divider Value */ +#define SCU_PLLCON1_PDIV_MASK (0x7f << SCU_PLLCON1_PDIV_SHIFT) +# define SCU_PLLCON1_PDIV(n) ((uint32_t)((n)-1) << SCU_PLLCON1_PDIV_SHIFT) + /* System PLL Configuration 2 Register */ -#define SCU_PLLCON2_ + +#define SCU_PLLCON2_PINSEL (1 << 0) /* Bit 0: P-Divider Input Selection */ +# define SCU_PLLCON2_PINSEL_PLL (0) /* 0=PLL external oscillator selected */ +# define SCU_PLLCON2_PINSEL_OFI (1 << 0) /* 1=Backup clock source selected */ +#define SCU_PLLCON2_K1INSEL (1 << 8) /* Bit 8: K1-Divider Input */ +# define SCU_PLLCON2_K1INSEL_PLL (0) /* 0=PLL external oscillator selected */ +# define SCU_PLLCON2_K1INSEL_OFI (1 << 8) /* 1=Backup clock source selected */ + /* USB PLL Status Register */ #define SCU_USBPLLSTAT_ /* USB PLL Control Register */ diff --git a/arch/arm/src/xmc4/xmc4_clockconfig.c b/arch/arm/src/xmc4/xmc4_clockconfig.c index 67efe53651d..d7d5a8bc7df 100644 --- a/arch/arm/src/xmc4/xmc4_clockconfig.c +++ b/arch/arm/src/xmc4/xmc4_clockconfig.c @@ -1,9 +1,11 @@ /**************************************************************************** - * arch/arm/src/xmc4/xmc4_clock_config.c + * arch/arm/src/xmc4/xmc4_clockconfig.c * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Authors: Gregory Nutt * + * Reference: XMC4500 Reference Manual V1.5 2014-07 Microcontrollers. + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: @@ -31,6 +33,20 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * + * May include some logic from sample code provided by Infineon: + * + * Copyright (C) 2011-2015 Infineon Technologies AG. All rights reserved. + * + * Infineon Technologies AG (Infineon) is supplying this software for use with + * Infineon's microcontrollers. This file can be freely distributed within + * development tools that are supporting such microcontrollers. + * + * THIS SOFTWARE IS PROVIDED AS IS. NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, + * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * ****************************************************************************/ /**************************************************************************** @@ -47,10 +63,6 @@ * Pre-processor Definitions ****************************************************************************/ -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - /**************************************************************************** * Private Functions ****************************************************************************/ @@ -60,7 +72,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: xmc4_clock_config + * Name: xmc4_clock_configure * * Description: * Called to initialize the XMC4xxx chip. This does whatever setup is @@ -69,6 +81,90 @@ * ****************************************************************************/ -void xmc4_clock_config(void) +void xmc4_clock_configure(void) { } + +/**************************************************************************** + * Name: xmc4_get_coreclock + * + * Description: + * Return the current core clock frequency (fCPU). + * + ****************************************************************************/ + +uint32_t xmc4_get_coreclock(void) +{ + uint32_t pdiv; + uint32_t ndiv; + uint32_t kdiv; + uint32_t sysdiv; + uint32_t regval; + uint32_t temp; + + if ((getreg32(XMC4_SCU_SYSCLKCR) & SCU_SYSCLKCR_SYSSEL) != 0) + { + /* fPLL is clock source for fSYS */ + + if ((getreg32(XMC4_SCU_PLLCON2) & SCU_PLLCON2_PINSEL) != 0) + { + /* PLL input clock is the backup clock (fOFI) */ + + temp = OFI_FREQUENCY; + } + else + { + /* PLL input clock is the high performance oscillator (fOSCHP); + * Only board specific logic knows this value. + */ + + temp = BOARD_XTAL_FREQUENCY; + } + + /* Check if PLL is locked */ + + regval = getreg32(XMC4_SCU_PLLSTAT); + if ((regval & SCU_PLLSTAT_VCOLOCK) != 0) + { + /* PLL normal mode */ + + regval = getreg32(XMC4_SCU_PLLCON1); + pdiv = ((regval & SCU_PLLCON1_PDIV_MASK) >> SCU_PLLCON1_PDIV_SHIFT) + 1; + ndiv = ((regval & SCU_PLLCON1_NDIV_MASK) >> SCU_PLLCON1_NDIV_SHIFT) + 1; + kdiv = ((regval & SCU_PLLCON1_K2DIV_MASK) >> SCU_PLLCON1_K2DIV_SHIFT) + 1; + + temp = (temp / (pdiv * kdiv)) * ndiv; + } + else + { + /* PLL prescalar mode */ + + regval = getreg32(XMC4_SCU_PLLCON1); + kdiv = ((regval & SCU_PLLCON1_K1DIV_MASK) >> SCU_PLLCON1_K1DIV_SHIFT) + 1; + + temp = (temp / kdiv); + } + } + else + { + /* fOFI is clock source for fSYS */ + + temp = OFI_FREQUENCY; + } + + /* Divide by SYSDIV to get fSYS */ + + regval = getreg32(XMC4_SCU_SYSCLKCR); + sysdiv = ((regval & SCU_SYSCLKCR_SYSDIV_MASK) >> SCU_SYSCLKCR_SYSDIV_SHIFT) + 1; + temp = temp / sysdiv; + + /* Check if the fSYS clock is divided by two to produce fCPU clock. */ + + regval = getreg32(CPUCLKCR); + if ((regval & SCU_CPUCLKCR_CPUDIV) != 0) + { + temp = temp >> 1; + } + + return temp; +} diff --git a/arch/arm/src/xmc4/xmc4_clockconfig.h b/arch/arm/src/xmc4/xmc4_clockconfig.h new file mode 100644 index 00000000000..6e03989cad0 --- /dev/null +++ b/arch/arm/src/xmc4/xmc4_clockconfig.h @@ -0,0 +1,79 @@ +/************************************************************************************ + * arch/arm/src/xmc4/xmc4_clockconfig.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_XMC4_XMC4_CLOCKCONFIG_H +#define __ARCH_ARM_SRC_XMC4_XMC4_CLOCKCONFIG_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include + +/************************************************************************************ + * Preprocessor Definitions + ************************************************************************************/ + +#define OFI_FREQUENCY 24000000 /* Frequency of internal Backup Clock Source */ +#define OSI_FREQUENCY 32768 /* Frequency of internal Slow Clock Source */ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/**************************************************************************** + * Name: xmc4_clock_configure + * + * Description: + * Called to initialize the XMC4xxx chip. This does whatever setup is + * needed to put the MCU in a usable state. This includes the + * initialization of clocking using the settings in board.h. + * + ****************************************************************************/ + +void xmc4_clock_configure(void); + +/**************************************************************************** + * Name: xmc4_get_coreclock + * + * Description: + * Return the current core clock frequency. + * + ****************************************************************************/ + +uint32_t xmc4_get_coreclock(void); + +#endif /* __ARCH_ARM_SRC_XMC4_XMC4_CLOCKCONFIG_H */ diff --git a/arch/arm/src/xmc4/xmc4_start.c b/arch/arm/src/xmc4/xmc4_start.c index e71722e4be5..77e792847e9 100644 --- a/arch/arm/src/xmc4/xmc4_start.c +++ b/arch/arm/src/xmc4/xmc4_start.c @@ -279,7 +279,7 @@ void __start(void) /* Disable the watchdog timer */ - kinetis_wddisable(); + xmc4_wddisable(); /* Clear .bss. We'll do this inline (vs. calling memset) just to be * certain that there are no issues with the state of global variables. @@ -318,7 +318,7 @@ void __start(void) * RAM functions having been copied to RAM). */ - xmc4_clock_config(); + xmc4_clock_configure(); /* Configure the uart and perform early serial initialization so that we * can get debug output as soon as possible (This depends on clock diff --git a/arch/arm/src/xmc4/xmc4_start.h b/arch/arm/src/xmc4/xmc4_start.h new file mode 100644 index 00000000000..2be470640bf --- /dev/null +++ b/arch/arm/src/xmc4/xmc4_start.h @@ -0,0 +1,61 @@ +/************************************************************************************ + * arch/arm/src/xmc4/xmc4_start.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_XMC4_XMC4_CLOCKCONFIG_H +#define __ARCH_ARM_SRC_XMC4_XMC4_CLOCKCONFIG_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: xmc4_board_initialize + * + * Description: + * All XMC4xxx architectures must provide the following entry point. This entry + * point is called early in the initialization -- after all memory has been + * configured and mapped but before any devices have been initialized. + * + ************************************************************************************/ + +void xmc4_board_initialize(void); + +#endif /* __ARCH_ARM_SRC_XMC4_XMC4_CLOCKCONFIG_H */ diff --git a/configs/xmc4500-relax/include/board.h b/configs/xmc4500-relax/include/board.h new file mode 100644 index 00000000000..a448469bca7 --- /dev/null +++ b/configs/xmc4500-relax/include/board.h @@ -0,0 +1,150 @@ +/************************************************************************************ + * configs/xmc4500-relax/include/board.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __CONFIG_XMC4500_RELAX_INCLUDE_BOARD_H +#define __CONFIG_XMC4500_RELAX_INCLUDE_BOARD_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +# include +#endif + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Clocking *************************************************************************/ +/* Default clock initialization + * fPLL = 288MHz => fSYS = 288MHz => fCPU = 144MHz + * => fPB = 144MHz + * => fCCU = 144MHz + * => fETH = 72MHz + * => fUSB = 48MHz + * => fEBU = 72MHz + * + * fUSBPLL Disabled, only enabled if SCU_CLK_USBCLKCR_USBSEL_USBPLL is selected + * + * fOFI = 24MHz => fWDT = 24MHz + */ + +/* On-board crystals + * + * NOTE: Only the XMC4500 Relax Kit-V1 provides the 32.768KHz RTC crystal. It + * is not available on XMC4500 Relax Lite Kit-V1. + */ + +#define BOARD_XTAL_FREQUENCY 12000000 /* 12MHz XTAL */ +#undef BOARD_RTC_XTAL_FRQUENCY /* 32.768KHz RTC XTAL not available */ + +/* Select the external crystal as the PLL clock source */ + +#define BOARD_PLL_CLOCKSRC_XTAL 1 /* PLL Clock source == extnernal crystal */ +#undef BOARD_PLL_CLOCKSRC_OFI /* PLL Clock source != internal fast oscillator */ + +/* PLL Configuration: + * + * fPLL = (fPLLSRC / (pdiv * k2div) * ndiv + * + * fPLL = (12000000 / (2 * 1)) * 48 + * = 288MHz + */ + +#define BOARD_PLL_PDIV 2 +#define BOARD_PLL_NDIV 48 +#define BOARD_PLL_K2DIV 1 +#define BOARD_PLL_FREQUENCY 288000000 + +/* System frequency is divided down from PLL output */ + +#define BOARD_SYSDIV 1 /* PLL Output divider to get fSYS */ +#define BOARD_SYS_FREQUENCY 288000000 + +/* CPU frequency may be divided down from system frequency */ + +#define BOARD_CPUDIV_ENABLE 1 /* Enable PLL dive by 2 for fCPU */ +#define BOARD_CPU_FREQUENCY 144000000 + +/* Standby clock source selection + * + * BOARD_STDBY_CLOCKSRC_OSI - Internal slow oscillator (32768Hz) + * BOARD_STDBY_CLOCKSRC_OSCULP - External 32.768KHz crystal + */ + +#define BOARD_STDBY_CLOCKSRC_OSI 1 +#undef BOARD_STDBY_CLOCKSRC_OSCULP + +/* USB PLL settings. + * + * fUSBPLL = 48MHz and fUSBPLLVCO = 384 MHz + * + * Note: Implicit divider of 2 and fUSBPLLVCO >= 260 MHz and + * fUSBPLLVCO <= 520 MHz + */ + +#define BOARD_USB_PDIV 2 +#define BOARD_USB_NDIV 64 + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __CONFIG_XMC4500_RELAX_INCLUDE_BOARD_H */ From 519f14fbb5bd981966148623b430144d4ba135c2 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 15 Mar 2017 11:43:58 -0600 Subject: [PATCH 07/81] XMC4xxx: A few more SCU register bit definitions. --- arch/arm/src/xmc4/chip/xmc4_scu.h | 78 +++++++++++++++++++++++-------- 1 file changed, 58 insertions(+), 20 deletions(-) diff --git a/arch/arm/src/xmc4/chip/xmc4_scu.h b/arch/arm/src/xmc4/chip/xmc4_scu.h index e9370565ba9..87b11f3753e 100644 --- a/arch/arm/src/xmc4/chip/xmc4_scu.h +++ b/arch/arm/src/xmc4/chip/xmc4_scu.h @@ -421,25 +421,30 @@ /* Trap Control Registers */ -/* Trap Status Register */ -#define SCU_TRAPSTAT_ -/* Trap Raw Status Register */ -#define SCU_TRAPRAW_ -/* Trap Mask Register */ -#define SCU_TRAPDIS_ -/* Trap Clear Register */ -#define SCU_TRAPCLR_ -/* Trap Set Register */ -#define SCU_TRAPSET_ +/* Trap Status Register, Trap Raw Status Register, Trap Mask Register, Trap Clear + * Register, and Trap Set Register + */ + +#define SCU_TRAP_SOSCWDGT (1 << 0) /* Bit 0: OSC_HP Oscillator Watchdog Trap */ +#define SCU_TRAP_SVCOLCKT (1 << 2) /* Bit 2: System VCO Lock Trap */ +#define SCU_TRAP_UVCOLCKT (1 << 3) /* Bit 3: USB VCO Lock Trap */ +#define SCU_TRAP_PET (1 << 4) /* Bit 4: Parity Error Trap */ +#define SCU_TRAP_BRWNT (1 << 5) /* Bit 5: Brown Out Trap */ +#define SCU_TRAP_ULPWDGT (1 << 6) /* Bit 6: OSC_ULP Oscillator Watchdog Trap */ +#define SCU_TRAP_BWERR0T (1 << 7) /* Bit 7: Peripheral Bridge 0 Trap */ +#define SCU_TRAP_BWERR1T (1 << 8) /* Bit 8: Peripheral Bridge 1 Trap */ /* Power Control SCU Registers */ -/* Power Status Register */ -#define SCU_PWRSTAT_ -/* Power Set Control Register */ -#define SCU_PWRSET_ -/* Power Clear Control Register */ -#define SCU_PWRCLR_ +/* Power Status Register, Power Set Control Register, and Power Clear + * Control Register + */ + +#define SCU_PWR_HIBEN (1 << 0) /* Bit 0: Hibernate Domain Enable State */ +#define SCU_PWR_USBPHYPDQ (1 << 16) /* Bit 16: USB PHY Transceiver State */ +#define SCU_PWR_USBOTGEN (1 << 17) /* Bit 17: USB On-The-Go Comparators State */ +#define SCU_PWR_USBPUWQ (1 << 18) /* Bit 18: USB Weak Pull-Up at PADN State */ + /* EVR Status Register */ #define SCU_EVRSTAT_ /* EVR VADC Status Register */ @@ -467,11 +472,34 @@ /* Reset SCU Registers */ /* System Reset Status */ -#define SCU_RSTSTAT_ + +#define SCU_RSTSTAT_RSTSTAT_SHIFT (0) /* Bits 0-7: Reset Status Information */ +#define SCU_RSTSTAT_RSTSTAT_MASK (0xff << SCU_RSTSTAT_RSTSTAT_SHIFT) +# define SCU_RSTSTAT_RSTSTAT_PORST (1 << SCU_RSTSTAT_RSTSTAT_SHIFT) /* PORST reset */ +# define SCU_RSTSTAT_RSTSTAT_SWD (2 << SCU_RSTSTAT_RSTSTAT_SHIFT) /* SWD reset */ +# define SCU_RSTSTAT_RSTSTAT_PV (4 << SCU_RSTSTAT_RSTSTAT_SHIFT) /* PV reset */ +# define SCU_RSTSTAT_RSTSTAT_CPUSYS (8 << SCU_RSTSTAT_RSTSTAT_SHIFT) /* CPU system reset */ +# define SCU_RSTSTAT_RSTSTAT_CPULOCK (16 << SCU_RSTSTAT_RSTSTAT_SHIFT) /* CPU lockup reset */ +# define SCU_RSTSTAT_RSTSTAT_WDT (32 << SCU_RSTSTAT_RSTSTAT_SHIFT) /* WDT reset */ +# define SCU_RSTSTAT_RSTSTAT_PERR (128 << SCU_RSTSTAT_RSTSTAT_SHIFT) /* Parity Error reset */ + +#define SCU_RSTSTAT_HIBWK (1 << 8) /* Bit 8: Hibernate Wake-up Status */ +#define SCU_RSTSTAT_HIBRS (1 << 9) /* Bit 9: Hibernate Reset Status */ +#define SCU_RSTSTAT_LCKEN (1 << 10) /* Bit 10: Enable Lockup Status */ + /* Reset Set Register */ -#define SCU_RSTSET_ + +#define SCU_RSTSET_HIBWK (1 << 8) /* Bit 8: Hibernate Wake-up Reset Status */ +#define SCU_RSTSET_HIBRS (1 << 9) /* Bit 9: Hibernate Reset Reset Status */ +#define SCU_RSTSET_LCKEN (1 << 10) /* Bit 10: Enable Lockup Reset Status */ + /* Reset Clear Register */ -#define SCU_RSTCLR_ + +#define SCU_RSTCLR_RSCLR (1 << 0) /* Bit 0: Clear Reset Status */ +#define SCU_RSTCLR_HIBWK (1 << 8) /* Bit 8: Clear Hibernate Wake-up Reset Status */ +#define SCU_RSTCLR_HIBRS (1 << 9) /* Bit 9: Clear Hibernate Reset */ +#define SCU_RSTCLR_LCKEN (1 << 10) /* Bit 10: Clear Hibernate Reset */ + /* Peripheral Reset Status Register 0 */ #define SCU_PRSTAT0_ /* Peripheral Reset Set Register 0 */ @@ -585,7 +613,17 @@ #define SCU_PLLSTAT_PLLSP (1 << 9) /* Bit 9: Oscillator for PLL Valid Spike Status */ /* System PLL Configuration 0 Register */ -#define SCU_PLLCON0_ + +#define SCU_PLLCON0_VCOBYP (1 << 0) /* Bit 0: VCO Bypass */ +#define SCU_PLLCON0_VCOPWD (1 << 1) /* Bit 1: VCO Power Saving Mode */ +#define SCU_PLLCON0_VCOTR (1 << 2) /* Bit 2: VCO Trim Control */ +#define SCU_PLLCON0_FINDIS (1 << 4) /* Bit 4: Disconnect Oscillator from VCO */ +#define SCU_PLLCON0_OSCDISCDIS (1 << 6) /* Bit 6: Oscillator Disconnect Disable */ +#define SCU_PLLCON0_PLLPWD (1 << 16) /* Bit 16: PLL Power Saving Mode */ +#define SCU_PLLCON0_OSCRES (1 << 17) /* Bit 17: Oscillator Watchdog Reset */ +#define SCU_PLLCON0_RESLD (1 << 18) /* Bit 18: Restart VCO Lock Detection */ +#define SCU_PLLCON0_AOTREN (1 << 19) /* Bit 19: Automatic Oscillator Calibration Enable */ +#define SCU_PLLCON0_FOTR (1 << 20) /* Bit 20: Factory Oscillator Calibration */ /* System PLL Configuration 1 Register */ From 059e398185c3861406a9e4350ff719f1fb226e53 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 15 Mar 2017 18:50:48 -0600 Subject: [PATCH 08/81] XMC4xxx: A few more SCU register bit definitions. --- arch/arm/src/xmc4/chip/xmc4_scu.h | 132 ++++++++++++++++++++++++++---- 1 file changed, 117 insertions(+), 15 deletions(-) diff --git a/arch/arm/src/xmc4/chip/xmc4_scu.h b/arch/arm/src/xmc4/chip/xmc4_scu.h index 87b11f3753e..8f6f89cc4a9 100644 --- a/arch/arm/src/xmc4/chip/xmc4_scu.h +++ b/arch/arm/src/xmc4/chip/xmc4_scu.h @@ -326,9 +326,9 @@ /* Oscillator Control SCU Registers */ -#define XMC4_OSCU_OSCHPSTAT (XMC4_SCU_OSC_BASE+XMC4_OSCU_OSCHPSTAT_OFFSET) -#define XMC4_OSCU_OSCHPCTRL (XMC4_SCU_OSC_BASE+XMC4_OSCU_OSCHPCTRL_OFFSET) -#define XMC4_OSCU_CLKCALCONST (XMC4_SCU_OSC_BASE+XMC4_OSCU_CLKCALCONST_OFFSET) +#define XMC4_SCU_OSCHPSTAT (XMC4_SCU_OSC_BASE+XMC4_SCU_OSCHPSTAT_OFFSET) +#define XMC4_SCU_OSCHPCTRL (XMC4_SCU_OSC_BASE+XMC4_SCU_OSCHPCTRL_OFFSET) +#define XMC4_SCU_CLKCALCONST (XMC4_SCU_OSC_BASE+XMC4_SCU_CLKCALCONST_OFFSET) /* PLL Control SCU Registers */ @@ -370,8 +370,23 @@ #define SCU_G0ORCEN_ /* Out-Of-Range Comparator Enable Register 1 */ #define SCU_G1ORCEN_ + /* Mirror Update Status Register */ -#define SCU_MIRRSTS_ + +#define SCU_MIRRSTS_HDCLR (1 << 1) /* Bit 1: HDCLR Mirror Register Write Status */ +#define SCU_MIRRSTS_HDSET (1 << 2) /* Bit 2: HDSET Mirror Register Write Status */ +#define SCU_MIRRSTS_HDCR (1 << 3) /* Bit 3: HDCR Mirror Register Write Status */ +#define SCU_MIRRSTS_OSCSICTRL (1 << 5) /* Bit 5: OSCSICTRL Mirror Register Write Status */ +#define SCU_MIRRSTS_OSCULSTAT (1 << 6) /* Bit 6: OSCULSTAT Mirror Register Write Status */ +#define SCU_MIRRSTS_OSCULCTRL (1 << 7) /* Bit 7: OSCULCTRL Mirror Register Write Status */ +#define SCU_MIRRSTS_RTC_CTR (1 << 8) /* Bit 8: RTC CTR Mirror Register Write Status */ +#define SCU_MIRRSTS_RTC_ATIM0 (1 << 9) /* Bit 9: RTC ATIM0 Mirror Register Write Status */ +#define SCU_MIRRSTS_RTC_ATIM1 (1 << 10) /* Bit 10: RTC ATIM1 Mirror Register Write Status */ +#define SCU_MIRRSTS_RTC_TIM0 (1 << 11) /* Bit 11: RTC TIM0 Mirror Register Write Status */ +#define SCU_MIRRSTS_RTC_TIM1 (1 << 12) /* Bit 12: RTC TIM1 Mirror Register Write Status */ +#define SCU_MIRRSTS_RMX (1 << 13) /* Bit 13: Retention Memory Access Register Update Status */ +#define SCU_MIRRSTS_RTC_MSKSR (1 << 14) /* Bit 14: RTC MSKSSR Mirror Register Write Status */ +#define SCU_MIRRSTS_RTC_CLRSR (1 << 15) /* Bit 15: RTC CLRSR Mirror Register Write Status */ /* Ethernet Control SCU Resters */ @@ -452,22 +467,93 @@ /* Power Monitor Value */ #define SCU_PWRMON_ -/* HCU Registers */ - +/* Hibernation SCU Registers */ /* Hibernate Domain Status Register */ -#define SCU_HDSTAT_ + +#define SCU_HDSTAT_EPEV (1 << 0) /* Bit 0: Wake-up Pin Event Positive Edge Status */ +#define SCU_HDSTAT_ENEV (1 << 1) /* Bit 1: Wake-up Pin Event Negative Edge Status */ +#define SCU_HDSTAT_RTCEV (1 << 2) /* Bit 2: RTC Event Status */ +#define SCU_HDSTAT_ULPWDG (1 << 3) /* Bit 3: ULP WDG Alarm Status */ +#define SCU_HDSTAT_HIBNOUT (1 << 4) /* Bit 3: Hibernate Control Status */ + /* Hibernate Domain Status Clear Register */ -#define SCU_HDCLR_ + +#define SCU_HDCLR_EPEV (1 << 0) /* Bit 0: Wake-up Pin Event Positive Edge Clear */ +#define SCU_HDCLR_ENEV (1 << 1) /* Bit 1: Wake-up Pin Event Negative Edge Clear */ +#define SCU_HDCLR_RTCEV (1 << 2) /* Bit 2: RTC Event Clear */ +#define SCU_HDCLR_ULPWDG (1 << 3) /* Bit 3: ULP WDG Alarm Clear */ + /* Hibernate Domain Status Set Register */ -#define SCU_HDSET_ + +#define SCU_HDSET_EPEV (1 << 0) /* Bit 0: Wake-up Pin Event Positive Edge Set */ +#define SCU_HDSET_ENEV (1 << 1) /* Bit 1: Wake-up Pin Event Negative Edge Set */ +#define SCU_HDSET_RTCEV (1 << 2) /* Bit 2: RTC Event Set */ +#define SCU_HDSET_ULPWDG (1 << 3) /* Bit 3: ULP WDG Alarm Set */ + /* Hibernate Domain Control Register */ -#define SCU_HDCR_ + +#define SCU_HDCR_WKPEP (1 << 0) /* Bit 0: Wake-Up on Pin Event Positive Edge Enable */ +#define SCU_HDCR_WKPEN (1 << 1) /* Bit 1: Wake-up on Pin Event Negative Edge Enable */ +#define SCU_HDCR_RTCE (1 << 2) /* Bit 2: Wake-up on RTC Event Enable */ +#define SCU_HDCR_ULPWDGEN (1 << 3) /* Bit 3: ULP WDG Alarm Enable */ +#define SCU_HDCR_HIB (1 << 4) /* Bit 4: Hibernate Request Value Set */ +#define SCU_HDCR_RCS (1 << 6) /* Bit 6: fRTC Clock Selection */ +# define SCU_HDCR_RCS_OSI (0) /* 0=fOSI */ +# define SCU_HDCR_RCS_ULP (1 << 6) /* 1=fULP */ +#define SCU_HDCR_STDBYSEL (1 << 7) /* Bit 7: fSTDBY Clock Selection */ +# define SCU_HDCR_STDBYSEL_OSI (0) /* 0=fOSI */ +# define SCU_HDCR_STDBYSEL_ULP (1 << 7) /* 1=fULP */ +#define SCU_HDCR_WKUPSEL (1 << 8) /* Bit 8: Wake-Up from Hibernate Trigger Input Select */ +# define SCU_HDCR_WKUPSEL_HIBIO1 (0) /* 0=HIB_IO_1 pin selected */ +# define SCU_HDCR_WKUPSEL_HIBIO0 (1 << 8) /* 1=HIB_IO_0 pin selected */ +#define SCU_HDCR_GPI0SEL (1 << 10) /* Bit 10: General Purpose Input 0 Selection */ +# define SCU_HDCR_GPIOSEL_HIBIO1 (0) /* 0=HIB_IO_1 pin selected */ +# define SCU_HDCR_GPIOSEL_HIBIO0 (1 << 10) /* 1=HIB_IO_0 pin selected */ +#define SCU_HDCR_HIBIO0POL (1 << 12) /* Bit 12: HIBIO0 Polarity Set */ +# define SCU_HDCR_HIBIO0POL_DIR (0) /* 0=Direct */ +# define SCU_HDCR_HIBIO0POL_INV (1 << 12) /* 1=Inverted */ +#define SCU_HDCR_HIBIO1POL (1 << 13) /* Bit 13: HIBIO1 Polarity Set */ +# define SCU_HDCR_HIBIO1POL_DIR (0) /* 0=Direct */ +# define SCU_HDCR_HIBIO1POL_INV (1 << 13) /* 1=Inverted */ +#define SCU_HDCR_HIBIO0SEL_SHIFT (16) /* Bits 16-19: HIB_IO_0 Pin I/O Control */ +#define SCU_HDCR_HIBIO0SEL_MASK (15 << SCU_HDCR_HIBIO0SEL_SHIFT) +# define SCU_HDCR_HIBIO0SEL_DIR (0 << SCU_HDCR_HIBIO0SEL_SHIFT) /* Direct input */ +# define SCU_HDCR_HIBIO0SEL_DIRPD (1 << SCU_HDCR_HIBIO0SEL_SHIFT) /* Direct input, Input pull-down */ +# define SCU_HDCR_HIBIO0SEL_DIRPU (2 << SCU_HDCR_HIBIO0SEL_SHIFT) /* Direct input, Input pull-up */ +# define SCU_HDCR_HIBIO0SEL_PP (8 << SCU_HDCR_HIBIO0SEL_SHIFT) /* Push-pull HIB Control output */ +# define SCU_HDCR_HIBIO0SEL_PPWDT (9 << SCU_HDCR_HIBIO0SEL_SHIFT) /* Push-pull WDT service output */ +# define SCU_HDCR_HIBIO0SEL_PPGPIO (10 << SCU_HDCR_HIBIO0SEL_SHIFT) /* Push-pull GPIO output */ +# define SCU_HDCR_HIBIO0SEL_OD (12 << SCU_HDCR_HIBIO0SEL_SHIFT) /* Open-drain HIB Control output */ +# define SCU_HDCR_HIBIO0SEL_ODWDT (13 << SCU_HDCR_HIBIO0SEL_SHIFT) /* Open-drain WDT service output */ +# define SCU_HDCR_HIBIO0SEL_ODGPIO (14 << SCU_HDCR_HIBIO0SEL_SHIFT) /* Open-drain GPIO output */ +#define SCU_HDCR_HIBIO1SEL_SHIFT (20) /* Bits 20-23: HIB_IO_1 Pin I/O Control */ +#define SCU_HDCR_HIBIO1SEL_MASK (15 << SCU_HDCR_HIBIO1SEL_SHIFT) +# define SCU_HDCR_HIBIO1SEL_DIR (0 << SCU_HDCR_HIBIO1SEL_SHIFT) /* Direct input */ +# define SCU_HDCR_HIBIO1SEL_DIRPD (1 << SCU_HDCR_HIBIO1SEL_SHIFT) /* Direct input, Input pull-down */ +# define SCU_HDCR_HIBIO1SEL_DIRPU (2 << SCU_HDCR_HIBIO1SEL_SHIFT) /* Direct input, Input pull-up */ +# define SCU_HDCR_HIBIO1SEL_PP (8 << SCU_HDCR_HIBIO1SEL_SHIFT) /* Push-pull HIB Control output */ +# define SCU_HDCR_HIBIO1SEL_PPWDT (9 << SCU_HDCR_HIBIO1SEL_SHIFT) /* Push-pull WDT service output */ +# define SCU_HDCR_HIBIO1SEL_PPGPIO (10 << SCU_HDCR_HIBIO1SEL_SHIFT) /* Push-pull GPIO output */ +# define SCU_HDCR_HIBIO1SEL_OD (12 << SCU_HDCR_HIBIO1SEL_SHIFT) /* Open-drain HIB Control output */ +# define SCU_HDCR_HIBIO1SEL_ODWDT (13 << SCU_HDCR_HIBIO1SEL_SHIFT) /* Open-drain WDT service output */ +# define SCU_HDCR_HIBIO1SEL_ODGPIO (14 << SCU_HDCR_HIBIO1SEL_SHIFT) /* Open-drain GPIO output */ + /* Internal 32.768 kHz Clock Source Control Register */ #define SCU_OSCSICTRL_ + /* OSC_ULP Status Register */ -#define SCU_OSCULSTAT_ + +#define SCU_OSCULSTAT_X1D (1 << 0) /* Bit 0: XTAL1 Data Value */ + /* OSC_ULP Control Register */ -#define SCU_OSCULCTRL_ + +#define SCU_OSCULCTRL_X1DEN (1 << 0) /* Bit 0: XTAL1 Data General Purpose Input Enable */ +#define SCU_OSCULCTRL_MODE_SHIFT (4) /* Bits 4-5: Oscillator Mode */ +#define SCU_OSCULCTRL_MODE_MASK (3 << SCU_OSCULCTRL_MODE_SHIFT) +# define SCU_OSCULCTRL_MODE_OPER (0 << SCU_OSCULCTRL_MODE_SHIFT) /* OSC enabled in operation */ +# define SCU_OSCULCTRL_MODE_BYPASS (1 << SCU_OSCULCTRL_MODE_SHIFT) /* OSC enabled in bypass */ +# define SCU_OSCULCTRL_MODE_PDN (2 << SCU_OSCULCTRL_MODE_SHIFT) /* OSC power down */ +# define SCU_OSCULCTRL_MODE_PDNGPI (3 << SCU_OSCULCTRL_MODE_SHIFT) /* OSC power down, GPI possible */ /* Reset SCU Registers */ @@ -592,11 +678,27 @@ /* Oscillator Control SCU Registers */ /* OSC_HP Status Register */ -#define OSCU_OSCHPSTAT_ +#define SCU_OSCHPSTAT_ + /* OSC_HP Control Register */ -#define OSCU_OSCHPCTRL_ + +#define SCU_OSCHPCTRL_X1DEN (1 << 0) /* Bit 0: XTAL1 Data Enable */ +#define SCU_OSCHPCTRL_SHBY (1 << 1) /* Bit 1: Shaper Bypass */ +#define SCU_OSCHPCTRL_GAINSEL_SHIFT (2) /* Bits 2-3: */ +#define SCU_OSCHPCTRL_GAINSEL_MASK (3 << SCU_OSCHPCTRL_GAINSEL_SHIFT) +# define SCU_OSCHPCTRL_GAINSEL(n) ((uint32_t)(n) << SCU_OSCHPCTRL_GAINSEL_SHIFT) +#define SCU_OSCHPCTRL_MODE_SHIFT (4) +#define SCU_OSCHPCTRL_MODE_MASK (3 << SCU_OSCHPCTRL_MODE_SHIFT) +# define SCU_OSCHPCTRL_MODE_XTAL (0 << SCU_OSCHPCTRL_MODE_SHIFT) /* External Crystal Mode */ +# define SCU_OSCHPCTRL_MODE_DIS (1 << SCU_OSCHPCTRL_MODE_SHIFT) /* OSC is disabled */ +# define SCU_OSCHPCTRL_MODE_EXTIN (2 << SCU_OSCHPCTRL_MODE_SHIFT) /* External Input Clock Mode */ +# define SCU_OSCHPCTRL_MODE_DISPSM (3 << SCU_OSCHPCTRL_MODE_SHIFT) /* OSC is disabled, Power-Saving Mode */ +#define SCU_OSCHPCTRL_OSCVAL_SHIFT (16) +#define SCU_OSCHPCTRL_OSCVAL_MASK (15 << SCU_OSCHPCTRL_OSCVAL_SHIFT) +# define SCU_OSCHPCTRL_OSCVAL(n) ((uint32_t)((n)-1) << SCU_OSCHPCTRL_OSCVAL_SHIFT) + /* Clock Calibration Constant Register */ -#define OSCU_CLKCALCONST_ +#define SCU_CLKCALCONST_ /* PLL Control SCU Registers */ From 3cc2a4f7c9bb495da6c59f373f8d0e7672e4ee13 Mon Sep 17 00:00:00 2001 From: David Sidrane Date: Wed, 15 Mar 2017 14:02:55 -1000 Subject: [PATCH 09/81] sem_holder: Fixes improper restoration of base_priority in the case of CONFIG_SEM_PREALLOCHOLDERS=0 The call to sem_restorebaseprio_task context switches in the sem_foreachholder(sem, sem_restoreholderprioB, stcb); call prior to releasing the holder. So the running task is left as a holder as is the started task. Leaving both slots filled Thus failing to perforem the boost/or restoration on the correct tcb. This PR fixes this by releasing the running task slot prior to reprioritization that can lead to the context switch. To faclitate this, the interface to sem_restorebaseprio needed to take the tcb from the holder prior to the holder being freed. In the failure case where sched_verifytcb fails it added the overhead of looking up the holder. There is also the adfitinal thunking on the foreach to get from holer to holder->tcb. An alternate approach could be to leve the interface the same and allocate a holder on the stack of sem_restoreholderprioB copy the sem's holder to it, free it as is done in this pr and and then pass that address sem_restoreholderprio as the holder. It could then get the holder's tcb but we would keep the same sem_findholder in sched_verifytcb. --- sched/semaphore/sem_holder.c | 71 +++++++++++++++++++++++++++--------- 1 file changed, 53 insertions(+), 18 deletions(-) diff --git a/sched/semaphore/sem_holder.c b/sched/semaphore/sem_holder.c index eaf443342db..bca4b4429bf 100644 --- a/sched/semaphore/sem_holder.c +++ b/sched/semaphore/sem_holder.c @@ -235,6 +235,24 @@ static inline void sem_freeholder(sem_t *sem, FAR struct semholder_s *pholder) #endif } +/**************************************************************************** + * Name: sem_findandfreeholder + ****************************************************************************/ + +static inline void sem_findandfreeholder(sem_t *sem, FAR struct tcb_s *htcb) +{ + FAR struct semholder_s *pholder = sem_findholder(sem, htcb); + + /* When no more counts are held, remove the holder from the list. The + * count was decremented in sem_releaseholder. + */ + + if (pholder != NULL && pholder->counts <= 0) + { + sem_freeholder(sem, pholder); + } +} + /**************************************************************************** * Name: sem_foreachholder ****************************************************************************/ @@ -460,10 +478,10 @@ static int sem_dumpholder(FAR struct semholder_s *pholder, FAR sem_t *sem, * Name: sem_restoreholderprio ****************************************************************************/ -static int sem_restoreholderprio(FAR struct semholder_s *pholder, +static int sem_restoreholderprio(FAR struct tcb_s *htcb, FAR sem_t *sem, FAR void *arg) { - FAR struct tcb_s *htcb = (FAR struct tcb_s *)pholder->htcb; + FAR struct semholder_s *pholder = 0; #if CONFIG_SEM_NNESTPRIO > 0 FAR struct tcb_s *stcb = (FAR struct tcb_s *)arg; int rpriority; @@ -481,7 +499,11 @@ static int sem_restoreholderprio(FAR struct semholder_s *pholder, { serr("ERROR: TCB 0x%08x is a stale handle, counts lost\n", htcb); DEBUGASSERT(!sched_verifytcb(htcb)); - sem_freeholder(sem, pholder); + pholder = sem_findholder(sem, htcb); + if (pholder != NULL) + { + sem_freeholder(sem, pholder); + } } /* Was the priority of the holder thread boosted? If so, then drop its @@ -600,6 +622,20 @@ static int sem_restoreholderprio(FAR struct semholder_s *pholder, return 0; } +/**************************************************************************** + * Name: sem_restoreholderprioall + * + * Description: + * Reprioritize all holders + * + ****************************************************************************/ + +static int sem_restoreholderprioall(FAR struct semholder_s *pholder, + FAR sem_t *sem, FAR void *arg) +{ + return sem_restoreholderprio(pholder->htcb, sem, arg); +} + /**************************************************************************** * Name: sem_restoreholderprioA * @@ -614,7 +650,7 @@ static int sem_restoreholderprioA(FAR struct semholder_s *pholder, FAR struct tcb_s *rtcb = this_task(); if (pholder->htcb != rtcb) { - return sem_restoreholderprio(pholder, sem, arg); + return sem_restoreholderprio(pholder->htcb, sem, arg); } return 0; @@ -632,9 +668,18 @@ static int sem_restoreholderprioB(FAR struct semholder_s *pholder, FAR sem_t *sem, FAR void *arg) { FAR struct tcb_s *rtcb = this_task(); + if (pholder->htcb == rtcb) { - (void)sem_restoreholderprio(pholder, sem, arg); + + /* The running task has given up a count on the semaphore + * Release the holder if all counts have been given up. + * before reprioritizing causes a context switch. + */ + + sem_findandfreeholder(sem, rtcb); + + (void)sem_restoreholderprio(rtcb, sem, arg); return 1; } @@ -687,7 +732,7 @@ static inline void sem_restorebaseprio_irq(FAR struct tcb_s *stcb, { /* Drop the priority of all holder threads */ - (void)sem_foreachholder(sem, sem_restoreholderprio, stcb); + (void)sem_foreachholder(sem, sem_restoreholderprioall, stcb); } /* If there are no tasks waiting for available counts, then all holders @@ -781,18 +826,8 @@ static inline void sem_restorebaseprio_task(FAR struct tcb_s *stcb, * counts, then we need to remove it from the list of holders. */ - pholder = sem_findholder(sem, rtcb); - if (pholder != NULL) - { - /* When no more counts are held, remove the holder from the list. The - * count was decremented in sem_releaseholder. - */ + sem_findandfreeholder(sem, rtcb); - if (pholder->counts <= 0) - { - sem_freeholder(sem, pholder); - } - } } /**************************************************************************** @@ -1097,7 +1132,7 @@ void sem_canceled(FAR struct tcb_s *stcb, FAR sem_t *sem) /* Adjust the priority of every holder as necessary */ - (void)sem_foreachholder(sem, sem_restoreholderprio, stcb); + (void)sem_foreachholder(sem, sem_restoreholderprioall, stcb); } #endif From 66d001d0e1ebb8f19deb393666e596715256ac6a Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 16 Mar 2017 09:48:57 -0600 Subject: [PATCH 10/81] XMC4xxx: Initial clock configuration logic. --- arch/arm/src/xmc4/chip/xmc4_flash.h | 203 +++++++++++ arch/arm/src/xmc4/chip/xmc4_memorymap.h | 454 ++++++++++++------------ arch/arm/src/xmc4/chip/xmc4_scu.h | 48 ++- arch/arm/src/xmc4/xmc4_clockconfig.c | 445 +++++++++++++++++++++++ arch/arm/src/xmc4/xmc4_start.c | 46 +++ configs/xmc4500-relax/include/board.h | 8 + 6 files changed, 969 insertions(+), 235 deletions(-) create mode 100644 arch/arm/src/xmc4/chip/xmc4_flash.h diff --git a/arch/arm/src/xmc4/chip/xmc4_flash.h b/arch/arm/src/xmc4/chip/xmc4_flash.h new file mode 100644 index 00000000000..e68e7078e9c --- /dev/null +++ b/arch/arm/src/xmc4/chip/xmc4_flash.h @@ -0,0 +1,203 @@ +/************************************************************************************ + * arch/arm/src/xmc4/chip/xmc4_flash.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Reference: XMC4500 Reference Manual V1.5 2014-07 Microcontrollers. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * May include some logic from sample code provided by Infineon: + * + * Copyright (C) 2011-2015 Infineon Technologies AG. All rights reserved. + * + * Infineon Technologies AG (Infineon) is supplying this software for use with + * Infineon's microcontrollers. This file can be freely distributed within + * development tools that are supporting such microcontrollers. + * + * THIS SOFTWARE IS PROVIDED AS IS. NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, + * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_XMC4_CHIP_XMC4_FLASH_H +#define __ARCH_ARM_SRC_XMC4_CHIP_XMC4_FLASH_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register Offsets *****************************************************************/ + +/* PMU Registers -- See ID register */ +/* Prefetch Registers -- See PCON register */ + +/* FLASH Registers */ + +#define XMC4_FLASH_ID_OFFSET 0x1008 /* Flash Module Identification Register */ +#define XMC4_FLASH_FSR_OFFSET 0x1010 /* Flash Status Register */ +#define XMC4_FLASH_FCON_OFFSET 0x1014 /* Flash Configuration Register */ +#define XMC4_FLASH_MARP_OFFSET 0x1018 /* Flash Margin Control Register PFLASH */ +#define XMC4_FLASH_PROCON0_OFFSET 0x1020 /* Flash Protection Configuration User 0 */ +#define XMC4_FLASH_PROCON1_OFFSET 0x1024 /* Flash Protection Configuration User 1 */ +#define XMC4_FLASH_PROCON2_OFFSET 0x1028 /* Flash Protection Configuration User 2 */ + +/* Register Addresses ****************************************************************/ + +/* FLASH Registers */ + +#define XMC4_FLASH_ID (XMC4_FLASH0_BASE+XMC4_FLASH_ID_OFFSET) +#define XMC4_FLASH_FSR (XMC4_FLASH0_BASE+XMC4_FLASH_FSR_OFFSET) +#define XMC4_FLASH_FCON (XMC4_FLASH0_BASE+XMC4_FLASH_FCON_OFFSET) +#define XMC4_FLASH_MARP (XMC4_FLASH0_BASE+XMC4_FLASH_MARP_OFFSET) +#define XMC4_FLASH_PROCON0 (XMC4_FLASH0_BASE+XMC4_FLASH_PROCON0_OFFSET) +#define XMC4_FLASH_PROCON1 (XMC4_FLASH0_BASE+XMC4_FLASH_PROCON1_OFFSET) +#define XMC4_FLASH_PROCON2 (XMC4_FLASH0_BASE+XMC4_FLASH_PROCON2_OFFSET) + +/* Register Bit-Field Definitions **************************************************/ + +/* FLASH Registers */ + +/* Flash Module Identification Register */ + +#define FLASH_ID_MOD_REV_SHIFT (0) /* Bits 0-7: Module Revision Number */ +#define FLASH_ID_MOD_REV_MASK (0xff << FLASH_ID_MOD_REV_SHIFT) +#define FLASH_ID_MOD_TYPE_SHIFT (8) /* Bits 8-15: Module Type */ +#define FLASH_ID_MOD_TYPE_MASK (0xff << FLASH_ID_MOD_REV_SHIFT) +#define FLASH_ID_MOD_NUMBER_SHIFT (16) /* Bits 16-31: Module Number Value */ +#define FLASH_ID_MOD_NUMBER_MASK (0xffff << FLASH_ID_MOD_NUMBER_SHIFT) + +/* Flash Status Register */ + +#define FLASH_FSR_PBUSY (1 << 0) /* Bit 0: Program Flash Busy */ +#define FLASH_FSR_FABUSY (1 << 1) /* Bit 1: Flash Array Busy */ +#define FLASH_FSR_PROG (1 << 4) /* Bit 4: Programming State */ +#define FLASH_FSR_ERASE (1 << 5) /* Bit 5: Erase State */ +#define FLASH_FSR_PFPAGE (1 << 6) /* Bit 6: Program Flash in Page Mode */ +#define FLASH_FSR_PFOPER (1 << 8) /* Bit 8: Program Flash Operation Error */ +#define FLASH_FSR_SQER (1 << 10) /* Bit 10: Command Sequence Error */ +#define FLASH_FSR_PROER (1 << 11) /* Bit 11: Protection Error */ +#define FLASH_FSR_PFSBER (1 << 12) /* Bit 12: PFLASH Single-Bit Error and Correction */ +#define FLASH_FSR_PFDBER (1 << 14) /* Bit 14: PFLASH Double-Bit Error */ +#define FLASH_FSR_PROIN (1 << 16) /* Bit 16: Protection Installed */ +#define FLASH_FSR_RPROIN (1 << 18) /* Bit 18: Read Protection Installed */ +#define FLASH_FSR_RPRODIS (1 << 19) /* Bit 19: Read Protection Disable State */ +#define FLASH_FSR_WPROIN0 (1 << 21) /* Bit 21: Sector Write Protection Installed for User 0 */ +#define FLASH_FSR_WPROIN1 (1 << 22) /* Bit 22: Sector Write Protection Installed for User 1 */ +#define FLASH_FSR_WPROIN2 (1 << 23) /* Bit 23: Sector Write Protection Installed for User 2 */ +#define FLASH_FSR_WPRODIS0 (1 << 25) /* Bit 25: Sector Write Protection Disabled for User 0 */ +#define FLASH_FSR_WPRODIS1 (1 << 26) /* Bit 26: Sector Write Protection Disabled for User 1 */ +#define FLASH_FSR_SLM (1 << 28) /* Bit 28: Flash Sleep Mode */ +#define FLASH_FSR_VER (1 << 31) /* Bit 31: Verify Error */ + +/* Flash Configuration Register */ + +#define FLASH_FCON_WSPFLASH_SHIFT (0) /* Bits 0-3: Wait States for read access to PFLASH */ +#define FLASH_FCON_WSPFLASH_MASK (15 << FLASH_FCON_WSPFLASH_SHIFT) +# define FLASH_FCON_WSPFLASH(n) ((uint32_t)((n)-1) << FLASH_FCON_WSPFLASH_SHIFT) +#define FLASH_FCON_WSECPF (1 << 4) /* Bit 4: Wait State for Error Correction of PFLASH */ +#define FLASH_FCON_IDLE (1 << 13) /* Bit 13: Dynamic Flash Idle */ +#define FLASH_FCON_ESLDIS (1 << 14) /* Bit 14: External Sleep Request Disable */ +#define FLASH_FCON_SLEEP (1 << 15) /* Bit 15: Flash SLEEP */ +#define FLASH_FCON_RPA (1 << 16) /* Bit 16: Read Protection Activated */ +#define FLASH_FCON_DCF (1 << 17) /* Bit 17: Disable Code Fetch from Flash Memory */ +#define FLASH_FCON_DDF (1 << 18) /* Bit 18: Disable Any Data Fetch from Flash */ +#define FLASH_FCON_VOPERM (1 << 24) /* Bit 24: Verify and Operation Error Interrupt Mask */ +#define FLASH_FCON_SQERM (1 << 25) /* Bit 25: Command Sequence Error Interrupt Mask */ +#define FLASH_FCON_PROERM (1 << 26) /* Bit 26: Protection Error Interrupt Mask */ +#define FLASH_FCON_PFSBERM (1 << 27) /* Bit 27: PFLASH Single-Bit Error Interrupt Mask */ +#define FLASH_FCON_PFDBERM (1 << 29) /* Bit 29: PFLASH Double-Bit Error Interrupt Mask */ +#define FLASH_FCON_EOBM (1 << 31) /* Bit 31: End of Busy Interrupt Mask */ + +/* Flash Margin Control Register PFLASH */ + +#define FLASH_MARP_MARGIN_SHIFT (0) /* Bits 0-3: PFLASH Margin Selection */ +#define FLASH_MARP_MARGIN_MASK (15 << FLASH_MARP_MARGIN_SHIFT) +#define FLASH_MARP_TRAPDIS (1 << 15) /* Bit 15: PFLASH Double-Bit Error Trap Disable */ + +/* Flash Protection Configuration User 0 */ + +#define FLASH_PROCON0_S0L (1 << 0) /* Bit 0: Sector 0 Locked for Write Protection by User 0 */ +#define FLASH_PROCON0_S1L (1 << 1) /* Bit 1: Sector 1 Locked for Write Protection by User 0 */ +#define FLASH_PROCON0_S2L (1 << 2) /* Bit 2: Sector 2 Locked for Write Protection by User 0 */ +#define FLASH_PROCON0_S3L (1 << 3) /* Bit 3: Sector 3 Locked for Write Protection by User 0 */ +#define FLASH_PROCON0_S4L (1 << 4) /* Bit 4: Sector 4 Locked for Write Protection by User 0 */ +#define FLASH_PROCON0_S5L (1 << 5) /* Bit 5: Sector 5 Locked for Write Protection by User 0 */ +#define FLASH_PROCON0_S6L (1 << 6) /* Bit 6: Sector 6 Locked for Write Protection by User 0 */ +#define FLASH_PROCON0_S7L (1 << 7) /* Bit 7: Sector 7 Locked for Write Protection by User 0 */ +#define FLASH_PROCON0_S8L (1 << 8) /* Bit 8: Sector 8 Locked for Write Protection by User 0 */ +#define FLASH_PROCON0_S9L (1 << 9) /* Bit 9: Sector 9 Locked for Write Protection by User 0 */ +#define FLASH_PROCON0_S10_S11L (1 << 10) /* Bit 10: Sectors 10 and 11 Locked for Write Protection by User 0 */ +#define FLASH_PROCON0_S12_S13L (1 << 11) /* Bit 11: Sectors 12 and 13 Locked for Write Protection by User 0 */ +#define FLASH_PROCON0_S14_S15L (1 << 12) /* Bit 12: Sectors 14 and 15 Locked for Write Protection by User 0 */ +#define FLASH_PROCON0_RPRO (1 << 15) /* Bit 15: Read Protection Configuration */ + +/* Flash Protection Configuration User 1 */ + +#define FLASH_PROCON1_S0L (1 << 0) /* Bit 0: Sector 0 Locked for Write Protection by User 1 */ +#define FLASH_PROCON1_S1L (1 << 1) /* Bit 1: Sector 1 Locked for Write Protection by User 1 */ +#define FLASH_PROCON1_S2L (1 << 2) /* Bit 2: Sector 2 Locked for Write Protection by User 1 */ +#define FLASH_PROCON1_S3L (1 << 3) /* Bit 3: Sector 3 Locked for Write Protection by User 1 */ +#define FLASH_PROCON1_S4L (1 << 4) /* Bit 4: Sector 4 Locked for Write Protection by User 1 */ +#define FLASH_PROCON1_S5L (1 << 5) /* Bit 5: Sector 5 Locked for Write Protection by User 1 */ +#define FLASH_PROCON1_S6L (1 << 6) /* Bit 6: Sector 6 Locked for Write Protection by User 1 */ +#define FLASH_PROCON1_S7L (1 << 7) /* Bit 7: Sector 7 Locked for Write Protection by User 1 */ +#define FLASH_PROCON1_S8L (1 << 8) /* Bit 8: Sector 8 Locked for Write Protection by User 1 */ +#define FLASH_PROCON1_S9L (1 << 9) /* Bit 9: Sector 9 Locked for Write Protection by User 1 */ +#define FLASH_PROCON1_S10_S11L (1 << 10) /* Bit 10: Sectors 10 and 11 Locked for Write Protection by User 1 */ +#define FLASH_PROCON1_S12_S13L (1 << 11) /* Bit 11: Sectors 12 and 13 Locked for Write Protection by User 1 */ +#define FLASH_PROCON1_S14_S15L (1 << 12) /* Bit 12: Sectors 14 and 15 Locked for Write Protection by User 1 */ +#define FLASH_PROCON1_PSR (1 << 16) /* Bit 16: */ + +/* Flash Protection Configuration User 2 */ + +#define FLASH_PROCON2_S0ROM (1 << 0) /* Bit 0: Sector 0 Locked Forever by User 2 */ +#define FLASH_PROCON2_S1ROM (1 << 1) /* Bit 1: Sector 1 Locked Forever by User 2 */ +#define FLASH_PROCON2_S2ROM (1 << 2) /* Bit 2: Sector 2 Locked Forever by User 2 */ +#define FLASH_PROCON2_S3ROM (1 << 3) /* Bit 3: Sector 3 Locked Forever by User 2 */ +#define FLASH_PROCON2_S4ROM (1 << 4) /* Bit 4: Sector 4 Locked Forever by User 2 */ +#define FLASH_PROCON2_S5ROM (1 << 5) /* Bit 5: Sector 5 Locked Forever by User 2 */ +#define FLASH_PROCON2_S6ROM (1 << 6) /* Bit 6: Sector 6 Locked Forever by User 2 */ +#define FLASH_PROCON2_S7ROM (1 << 7) /* Bit 7: Sector 7 Locked Forever by User 2 */ +#define FLASH_PROCON2_S8ROM (1 << 8) /* Bit 8: Sector 8 Locked Forever by User 2 */ +#define FLASH_PROCON2_S9ROM (1 << 9) /* Bit 9: Sector 9 Locked Forever by User 2 */ +#define FLASH_PROCON2_S10_S11ROM (1 << 10) /* Bit 10: Sectors 10 and 11 Locked Forever by User 2 */ +#define FLASH_PROCON2_S12_S13ROM (1 << 11) /* Bit 11: Sectors 12 and 13 Locked Forever by User 2 */ +#define FLASH_PROCON2_S14_S15ROM (1 << 12) /* Bit 12: Sectors 14 and 15 Locked Forever by User 2 */ + +#endif /* __ARCH_ARM_SRC_XMC4_CHIP_XMC4_SCU_H */ diff --git a/arch/arm/src/xmc4/chip/xmc4_memorymap.h b/arch/arm/src/xmc4/chip/xmc4_memorymap.h index 8cf50174b9a..19dd637ab59 100644 --- a/arch/arm/src/xmc4/chip/xmc4_memorymap.h +++ b/arch/arm/src/xmc4/chip/xmc4_memorymap.h @@ -1,227 +1,227 @@ -/************************************************************************************ - * arch/arm/src/xmc4/chip/xmc4_memorymap.h - * - * Copyright (C) 2017 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Reference: XMC4500 Reference Manual V1.5 2014-07 Microcontrollers. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * May include some logic from sample code provided by Infineon: - * - * Copyright (C) 2011-2015 Infineon Technologies AG. All rights reserved. - * - * Infineon Technologies AG (Infineon) is supplying this software for use with - * Infineon's microcontrollers. This file can be freely distributed within - * development tools that are supporting such microcontrollers. - * - * THIS SOFTWARE IS PROVIDED AS IS. NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, - * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_XMC4_CHIP_XMC4_MEMORYMAP_H -#define __ARCH_ARM_SRC_XMC4_CHIP_XMC4_MEMORYMAP_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Peripheral Memory Map ************************************************************/ -/* Acronyms: - * ADC - Analog to Digital Converter - * CCU - Capture Compare Unit - * DAC - Digital to Analog Converter - * DSD - Delta Sigmoid Demodulator - * ERU - External Request Unit - * FCE - Flexible CRC Engine - * GPDMA - General Purpose DMA - * LEDTS - LED and Touch Sense Control Unit - * PMU - Program Management Unit - * POSIF - Position Interface - * SDMMC - Multi Media Card Interface - * USB - Universal Serial Bus - * USCI - Universal Serial Interface - */ - -#define XMC4_PBA0_BASE 0x40000000 -#define XMC4_VADC_BASE 0x40004000 -#define XMC4_VADC_G0_BASE 0x40004400 -#define XMC4_VADC_G1_BASE 0x40004800 -#define XMC4_VADC_G2_BASE 0x40004c00 -#define XMC4_VADC_G3_BASE 0x40005000 -#define XMC4_DSD_BASE 0x40008000 -#define XMC4_DSD_CH0_BASE 0x40008100 -#define XMC4_DSD_CH1_BASE 0x40008200 -#define XMC4_DSD_CH2_BASE 0x40008300 -#define XMC4_DSD_CH3_BASE 0x40008400 -#define XMC4_CCU40_BASE 0x4000c000 -#define XMC4_CCU40_CC40_BASE 0x4000c100 -#define XMC4_CCU40_CC41_BASE 0x4000c200 -#define XMC4_CCU40_CC42_BASE 0x4000c300 -#define XMC4_CCU40_CC43_BASE 0x4000c400 -#define XMC4_CCU41_BASE 0x40010000 -#define XMC4_CCU41_CC40_BASE 0x40010100 -#define XMC4_CCU41_CC41_BASE 0x40010200 -#define XMC4_CCU41_CC42_BASE 0x40010300 -#define XMC4_CCU41_CC43_BASE 0x40010400 -#define XMC4_CCU42_BASE 0x40014000 -#define XMC4_CCU42_CC40_BASE 0x40014100 -#define XMC4_CCU42_CC41_BASE 0x40014200 -#define XMC4_CCU42_CC42_BASE 0x40014300 -#define XMC4_CCU42_CC43_BASE 0x40014400 -#define XMC4_CCU80_BASE 0x40020000 -#define XMC4_CCU80_CC80_BASE 0x40020100 -#define XMC4_CCU80_CC81_BASE 0x40020200 -#define XMC4_CCU80_CC82_BASE 0x40020300 -#define XMC4_CCU80_CC83_BASE 0x40020400 -#define XMC4_CCU81_BASE 0x40024000 -#define XMC4_CCU81_CC80_BASE 0x40024100 -#define XMC4_CCU81_CC81_BASE 0x40024200 -#define XMC4_CCU81_CC82_BASE 0x40024300 -#define XMC4_CCU81_CC83_BASE 0x40024400 -#define XMC4_POSIF0_BASE 0x40028000 -#define XMC4_POSIF1_BASE 0x4002c000 -#define XMC4_USIC0_BASE 0x40030008 -#define XMC4_USIC0_CH0_BASE 0x40030000 -#define XMC4_USIC0_CH1_BASE 0x40030200 -#define XMC4_ERU1_BASE 0x40044000 - -#define XMC4_PBA1_BASE 0x48000000 -#define XMC4_CCU43_BASE 0x48004000 -#define XMC4_CCU43_CC40_BASE 0x48004100 -#define XMC4_CCU43_CC41_BASE 0x48004200 -#define XMC4_CCU43_CC42_BASE 0x48004300 -#define XMC4_CCU43_CC43_BASE 0x48004400 -#define XMC4_LEDTS0_BASE 0x48010000 -#define XMC4_CAN_BASE 0x48014000 -#define XMC4_CAN_NODE0_BASE 0x48014200 -#define XMC4_CAN_NODE1_BASE 0x48014300 -#define XMC4_CAN_NODE2_BASE 0x48014400 -#define XMC4_CAN_NODE3_BASE 0x48014500 -#define XMC4_CAN_NODE4_BASE 0x48014600 -#define XMC4_CAN_NODE5_BASE 0x48014700 -#define XMC4_CAN_MO_BASE 0x48015000 -#define XMC4_DAC_BASE 0x48018000 -#define XMC4_SDMMC_BASE 0x4801c000 -#define XMC4_USIC1_CH0_BASE 0x48020000 -#define XMC4_USIC1_BASE 0x48020008 -#define XMC4_USIC1_CH1_BASE 0x48020200 -#define XMC4_USIC2_CH0_BASE 0x48024000 -#define XMC4_USIC2_BASE 0x48024008 -#define XMC4_USIC2_CH1_BASE 0x48024200 -#define XMC4_PORT0_BASE 0x48028000 -#define XMC4_PORT1_BASE 0x48028100 -#define XMC4_PORT2_BASE 0x48028200 -#define XMC4_PORT3_BASE 0x48028300 -#define XMC4_PORT4_BASE 0x48028400 -#define XMC4_PORT5_BASE 0x48028500 -#define XMC4_PORT6_BASE 0x48028600 -#define XMC4_PORT7_BASE 0x48028700 -#define XMC4_PORT8_BASE 0x48028800 -#define XMC4_PORT9_BASE 0x48028900 -#define XMC4_PORT14_BASE 0x48028e00 -#define XMC4_PORT15_BASE 0x48028f00 - -#define XMC4_SCU_GENERAL_BASE 0x50004000 -#define XMC4_ETH0_CON_BASE 0x50004040 -#define XMC4_SCU_INTERRUPT_BASE 0x50004074 -#define XMC4_SDMMC_CON_BASE 0x500040b4 -#define XMC4_SCU_PARITY_BASE 0x5000413c -#define XMC4_SCU_TRAP_BASE 0x50004160 -#define XMC4_SCU_POWER_BASE 0x50004200 -#define XMC4_SCU_HIBERNATE_BASE 0x50004300 -#define XMC4_SCU_RESET_BASE 0x50004400 -#define XMC4_SCU_CLK_BASE 0x50004600 -#define XMC4_SCU_OSC_BASE 0x50004700 -#define XMC4_SCU_PLL_BASE 0x50004710 -#define XMC4_ERU0_BASE 0x50004800 -#define XMC4_DLR_BASE 0x50004900 -#define XMC4_RTC_BASE 0x50004a00 -#define XMC4_WDT_BASE 0x50008000 -#define XMC4_ETH0_BASE 0x5000c000 -#define XMC4_USB0_BASE 0x50040000 -#define XMC4_USB0_CH0_BASE 0x50040500 -#define XMC4_USB0_CH1_BASE 0x50040520 -#define XMC4_USB0_CH2_BASE 0x50040540 -#define XMC4_USB0_CH3_BASE 0x50040560 -#define XMC4_USB0_CH4_BASE 0x50040580 -#define XMC4_USB0_CH5_BASE 0x500405a0 -#define XMC4_USB0_CH6_BASE 0x500405c0 -#define XMC4_USB0_CH7_BASE 0x500405e0 -#define XMC4_USB0_CH8_BASE 0x50040600 -#define XMC4_USB0_CH9_BASE 0x50040620 -#define XMC4_USB0_CH10_BASE 0x50040640 -#define XMC4_USB0_CH11_BASE 0x50040660 -#define XMC4_USB0_CH12_BASE 0x50040680 -#define XMC4_USB0_CH13_BASE 0x500406a0 -#define XMC4_USB_EP_BASE 0x50040900 -#define XMC4_USB0_EP1_BASE 0x50040920 -#define XMC4_USB0_EP2_BASE 0x50040940 -#define XMC4_USB0_EP3_BASE 0x50040960 -#define XMC4_USB0_EP4_BASE 0x50040980 -#define XMC4_USB0_EP5_BASE 0x500409a0 -#define XMC4_USB0_EP6_BASE 0x500409c0 -#define XMC4_GPDMA0_CH0_BASE 0x50014000 -#define XMC4_GPDMA0_CH1_BASE 0x50014058 -#define XMC4_GPDMA0_CH2_BASE 0x500140b0 -#define XMC4_GPDMA0_CH3_BASE 0x50014108 -#define XMC4_GPDMA0_CH4_BASE 0x50014160 -#define XMC4_GPDMA0_CH5_BASE 0x500141b8 -#define XMC4_GPDMA0_CH6_BASE 0x50014210 -#define XMC4_GPDMA0_CH7_BASE 0x50014268 -#define XMC4_GPDMA0_BASE 0x500142c0 -#define XMC4_GPDMA1_CH0_BASE 0x50018000 -#define XMC4_GPDMA1_CH1_BASE 0x50018058 -#define XMC4_GPDMA1_CH2_BASE 0x500180b0 -#define XMC4_GPDMA1_CH3_BASE 0x50018108 -#define XMC4_GPDMA1_BASE 0x500182c0 -#define XMC4_FCE_BASE 0x50020000 -#define XMC4_FCE_KE0_BASE 0x50020020 -#define XMC4_FCE_KE1_BASE 0x50020040 -#define XMC4_FCE_KE2_BASE 0x50020060 -#define XMC4_FCE_KE3_BASE 0x50020080 - -#define XMC4_PMU0_BASE 0x58000508 -#define XMC4_FLASH0_BASE 0x58001000 -#define XMC4_PREF_BASE 0x58004000 -#define XMC4_EBU_BASE 0x58008000 - -#define XMC4_PPB_BASE 0xe000e000 - -#endif /* __ARCH_ARM_SRC_XMC4_CHIP_XMC4_SCU_H */ +/************************************************************************************ + * arch/arm/src/xmc4/chip/xmc4_memorymap.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Reference: XMC4500 Reference Manual V1.5 2014-07 Microcontrollers. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * May include some logic from sample code provided by Infineon: + * + * Copyright (C) 2011-2015 Infineon Technologies AG. All rights reserved. + * + * Infineon Technologies AG (Infineon) is supplying this software for use with + * Infineon's microcontrollers. This file can be freely distributed within + * development tools that are supporting such microcontrollers. + * + * THIS SOFTWARE IS PROVIDED AS IS. NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, + * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_XMC4_CHIP_XMC4_MEMORYMAP_H +#define __ARCH_ARM_SRC_XMC4_CHIP_XMC4_MEMORYMAP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Peripheral Memory Map ************************************************************/ +/* Acronyms: + * ADC - Analog to Digital Converter + * CCU - Capture Compare Unit + * DAC - Digital to Analog Converter + * DSD - Delta Sigmoid Demodulator + * ERU - External Request Unit + * FCE - Flexible CRC Engine + * GPDMA - General Purpose DMA + * LEDTS - LED and Touch Sense Control Unit + * PMU - Program Management Unit + * POSIF - Position Interface + * SDMMC - Multi Media Card Interface + * USB - Universal Serial Bus + * USCI - Universal Serial Interface + */ + +#define XMC4_PBA0_BASE 0x40000000 +#define XMC4_VADC_BASE 0x40004000 +#define XMC4_VADC_G0_BASE 0x40004400 +#define XMC4_VADC_G1_BASE 0x40004800 +#define XMC4_VADC_G2_BASE 0x40004c00 +#define XMC4_VADC_G3_BASE 0x40005000 +#define XMC4_DSD_BASE 0x40008000 +#define XMC4_DSD_CH0_BASE 0x40008100 +#define XMC4_DSD_CH1_BASE 0x40008200 +#define XMC4_DSD_CH2_BASE 0x40008300 +#define XMC4_DSD_CH3_BASE 0x40008400 +#define XMC4_CCU40_BASE 0x4000c000 +#define XMC4_CCU40_CC40_BASE 0x4000c100 +#define XMC4_CCU40_CC41_BASE 0x4000c200 +#define XMC4_CCU40_CC42_BASE 0x4000c300 +#define XMC4_CCU40_CC43_BASE 0x4000c400 +#define XMC4_CCU41_BASE 0x40010000 +#define XMC4_CCU41_CC40_BASE 0x40010100 +#define XMC4_CCU41_CC41_BASE 0x40010200 +#define XMC4_CCU41_CC42_BASE 0x40010300 +#define XMC4_CCU41_CC43_BASE 0x40010400 +#define XMC4_CCU42_BASE 0x40014000 +#define XMC4_CCU42_CC40_BASE 0x40014100 +#define XMC4_CCU42_CC41_BASE 0x40014200 +#define XMC4_CCU42_CC42_BASE 0x40014300 +#define XMC4_CCU42_CC43_BASE 0x40014400 +#define XMC4_CCU80_BASE 0x40020000 +#define XMC4_CCU80_CC80_BASE 0x40020100 +#define XMC4_CCU80_CC81_BASE 0x40020200 +#define XMC4_CCU80_CC82_BASE 0x40020300 +#define XMC4_CCU80_CC83_BASE 0x40020400 +#define XMC4_CCU81_BASE 0x40024000 +#define XMC4_CCU81_CC80_BASE 0x40024100 +#define XMC4_CCU81_CC81_BASE 0x40024200 +#define XMC4_CCU81_CC82_BASE 0x40024300 +#define XMC4_CCU81_CC83_BASE 0x40024400 +#define XMC4_POSIF0_BASE 0x40028000 +#define XMC4_POSIF1_BASE 0x4002c000 +#define XMC4_USIC0_BASE 0x40030008 +#define XMC4_USIC0_CH0_BASE 0x40030000 +#define XMC4_USIC0_CH1_BASE 0x40030200 +#define XMC4_ERU1_BASE 0x40044000 + +#define XMC4_PBA1_BASE 0x48000000 +#define XMC4_CCU43_BASE 0x48004000 +#define XMC4_CCU43_CC40_BASE 0x48004100 +#define XMC4_CCU43_CC41_BASE 0x48004200 +#define XMC4_CCU43_CC42_BASE 0x48004300 +#define XMC4_CCU43_CC43_BASE 0x48004400 +#define XMC4_LEDTS0_BASE 0x48010000 +#define XMC4_CAN_BASE 0x48014000 +#define XMC4_CAN_NODE0_BASE 0x48014200 +#define XMC4_CAN_NODE1_BASE 0x48014300 +#define XMC4_CAN_NODE2_BASE 0x48014400 +#define XMC4_CAN_NODE3_BASE 0x48014500 +#define XMC4_CAN_NODE4_BASE 0x48014600 +#define XMC4_CAN_NODE5_BASE 0x48014700 +#define XMC4_CAN_MO_BASE 0x48015000 +#define XMC4_DAC_BASE 0x48018000 +#define XMC4_SDMMC_BASE 0x4801c000 +#define XMC4_USIC1_CH0_BASE 0x48020000 +#define XMC4_USIC1_BASE 0x48020008 +#define XMC4_USIC1_CH1_BASE 0x48020200 +#define XMC4_USIC2_CH0_BASE 0x48024000 +#define XMC4_USIC2_BASE 0x48024008 +#define XMC4_USIC2_CH1_BASE 0x48024200 +#define XMC4_PORT0_BASE 0x48028000 +#define XMC4_PORT1_BASE 0x48028100 +#define XMC4_PORT2_BASE 0x48028200 +#define XMC4_PORT3_BASE 0x48028300 +#define XMC4_PORT4_BASE 0x48028400 +#define XMC4_PORT5_BASE 0x48028500 +#define XMC4_PORT6_BASE 0x48028600 +#define XMC4_PORT7_BASE 0x48028700 +#define XMC4_PORT8_BASE 0x48028800 +#define XMC4_PORT9_BASE 0x48028900 +#define XMC4_PORT14_BASE 0x48028e00 +#define XMC4_PORT15_BASE 0x48028f00 + +#define XMC4_SCU_GENERAL_BASE 0x50004000 +#define XMC4_ETH0_CON_BASE 0x50004040 +#define XMC4_SCU_INTERRUPT_BASE 0x50004074 +#define XMC4_SDMMC_CON_BASE 0x500040b4 +#define XMC4_SCU_PARITY_BASE 0x5000413c +#define XMC4_SCU_TRAP_BASE 0x50004160 +#define XMC4_SCU_POWER_BASE 0x50004200 +#define XMC4_SCU_HIBERNATE_BASE 0x50004300 +#define XMC4_SCU_RESET_BASE 0x50004400 +#define XMC4_SCU_CLK_BASE 0x50004600 +#define XMC4_SCU_OSC_BASE 0x50004700 +#define XMC4_SCU_PLL_BASE 0x50004710 +#define XMC4_ERU0_BASE 0x50004800 +#define XMC4_DLR_BASE 0x50004900 +#define XMC4_RTC_BASE 0x50004a00 +#define XMC4_WDT_BASE 0x50008000 +#define XMC4_ETH0_BASE 0x5000c000 +#define XMC4_USB0_BASE 0x50040000 +#define XMC4_USB0_CH0_BASE 0x50040500 +#define XMC4_USB0_CH1_BASE 0x50040520 +#define XMC4_USB0_CH2_BASE 0x50040540 +#define XMC4_USB0_CH3_BASE 0x50040560 +#define XMC4_USB0_CH4_BASE 0x50040580 +#define XMC4_USB0_CH5_BASE 0x500405a0 +#define XMC4_USB0_CH6_BASE 0x500405c0 +#define XMC4_USB0_CH7_BASE 0x500405e0 +#define XMC4_USB0_CH8_BASE 0x50040600 +#define XMC4_USB0_CH9_BASE 0x50040620 +#define XMC4_USB0_CH10_BASE 0x50040640 +#define XMC4_USB0_CH11_BASE 0x50040660 +#define XMC4_USB0_CH12_BASE 0x50040680 +#define XMC4_USB0_CH13_BASE 0x500406a0 +#define XMC4_USB_EP_BASE 0x50040900 +#define XMC4_USB0_EP1_BASE 0x50040920 +#define XMC4_USB0_EP2_BASE 0x50040940 +#define XMC4_USB0_EP3_BASE 0x50040960 +#define XMC4_USB0_EP4_BASE 0x50040980 +#define XMC4_USB0_EP5_BASE 0x500409a0 +#define XMC4_USB0_EP6_BASE 0x500409c0 +#define XMC4_GPDMA0_CH0_BASE 0x50014000 +#define XMC4_GPDMA0_CH1_BASE 0x50014058 +#define XMC4_GPDMA0_CH2_BASE 0x500140b0 +#define XMC4_GPDMA0_CH3_BASE 0x50014108 +#define XMC4_GPDMA0_CH4_BASE 0x50014160 +#define XMC4_GPDMA0_CH5_BASE 0x500141b8 +#define XMC4_GPDMA0_CH6_BASE 0x50014210 +#define XMC4_GPDMA0_CH7_BASE 0x50014268 +#define XMC4_GPDMA0_BASE 0x500142c0 +#define XMC4_GPDMA1_CH0_BASE 0x50018000 +#define XMC4_GPDMA1_CH1_BASE 0x50018058 +#define XMC4_GPDMA1_CH2_BASE 0x500180b0 +#define XMC4_GPDMA1_CH3_BASE 0x50018108 +#define XMC4_GPDMA1_BASE 0x500182c0 +#define XMC4_FCE_BASE 0x50020000 +#define XMC4_FCE_KE0_BASE 0x50020020 +#define XMC4_FCE_KE1_BASE 0x50020040 +#define XMC4_FCE_KE2_BASE 0x50020060 +#define XMC4_FCE_KE3_BASE 0x50020080 + +#define XMC4_PMU0_BASE 0x58000500 +#define XMC4_FLASH0_BASE 0x58001000 +#define XMC4_PREF_BASE 0x58004000 +#define XMC4_EBU_BASE 0x58008000 + +#define XMC4_PPB_BASE 0xe000e000 + +#endif /* __ARCH_ARM_SRC_XMC4_CHIP_XMC4_SCU_H */ diff --git a/arch/arm/src/xmc4/chip/xmc4_scu.h b/arch/arm/src/xmc4/chip/xmc4_scu.h index 8f6f89cc4a9..e08a64a48c0 100644 --- a/arch/arm/src/xmc4/chip/xmc4_scu.h +++ b/arch/arm/src/xmc4/chip/xmc4_scu.h @@ -626,18 +626,26 @@ #define SCU_SYSCLKCR_SYSDIV_MASK (0xff << SCU_CLK_SYSCLKCR_SYSDIV_SHIFT) # define SCU_SYSCLKCR_SYSDIV(n) ((uint32_t)((n)-1) << SCU_CLK_SYSCLKCR_SYSDIV_SHIFT) -#define SCU_SYSCLKCR_SYSSEL (1 << 16) /* Bit 16: System Clock Selection Value */ -# define SCU_SYSCLKCR_SYSSEL_OFI (0) /* 0=OFI clock */ -# define SCU_SYSCLKCR_SYSSEL_PLL (1 << 16) /* 1=PLL clock */ +#define SCU_SYSCLKCR_SYSSEL (1 << 16) /* Bit 16: System Clock Selection Value */ +# define SCU_SYSCLKCR_SYSSEL_OFI (0) /* 0=OFI clock */ +# define SCU_SYSCLKCR_SYSSEL_PLL (1 << 16) /* 1=PLL clock */ /* CPU Clock Control */ -#define SCU_CPUCLKCR_CPUDIV (1 << 0) /* Bit 0: CPU Clock Divider Enable */ +#define SCU_CPUCLKCR_CPUDIV (1 << 0) /* Bit 0: CPU Clock Divider Enable */ /* Peripheral Bus Clock Control */ #define SCU_PBCLKCR_ + /* USB Clock Control */ -#define SCU_USBCLKCR_ + +#define SCU_USBCLKCR_USBDIV_SHIFT (0) /* Bits 0-2: USB Clock Divider Value */ +#define SCU_USBCLKCR_USBDIV_MASK (7 << SCU_CLK_USBCLKCR_USBDIV_SHIFT) +# define SCU_SYSCLKCR_USBDIV(n) ((uint32_t)((n)-1) << SCU_CLK_USBCLKCR_USBDIV_SHIFT) +#define SCU_USBCLKCR_USBSEL (1 << 16) /* Bit 16: USB Clock Selection Value */ +# define SCU_USBCLKCR_USBSEL_USBPLL (0) /* 0=USB PLL Clock */ +# define SCU_USBCLKCR_USBSEL_PLL (1 << 16) /* 1= PLL Clock */ + /* EBU Clock Control */ #define SCU_EBUCLKCR_ /* CCU Clock Control */ @@ -752,10 +760,34 @@ # define SCU_PLLCON2_K1INSEL_OFI (1 << 8) /* 1=Backup clock source selected */ /* USB PLL Status Register */ -#define SCU_USBPLLSTAT_ + +#define SCU_USBPLLSTAT_VCOBYST (1 << 0) /* Bit 0: VCO Bypass Status */ +#define SCU_USBPLLSTAT_PWDSTAT (1 << 1) /* Bit 1: PLL Power-saving Mode Status */ +#define SCU_USBPLLSTAT_VCOLOCK (1 << 2) /* Bit 2: PLL VCO Lock Status */ +#define SCU_USBPLLSTAT_BY (1 << 6) /* Bit 6: Bypass Mode Status */ +#define SCU_USBPLLSTAT_VCOLOCKED (1 << 7) /* Bit 7: PLL LOCK Status */ + /* USB PLL Control Register */ -#define SCU_USBPLLCON_ + +#define SCU_USBPLLCON_VCOBYP (1 << 0) /* Bit 0: VCO Bypass */ +#define SCU_USBPLLCON_VCOPWD (1 << 1) /* Bit 1: VCO Power Saving Mode */ +#define SCU_USBPLLCON_VCOTR (1 << 2) /* Bit 2: VCO Trim Control */ +#define SCU_USBPLLCON_FINDIS (1 << 4) /* Bit 4: Disconnect Oscillator from VCO */ +#define SCU_USBPLLCON_OSCDISCDIS (1 << 6) /* Bit 6: Oscillator Disconnect Disable */ +#define SCU_USBPLLCON_NDIV_SHIFT (8) /* Bits 8-14: N-Divider Val */ +#define SCU_USBPLLCON_NDIV_MASK (0x7f << SCU_USBPLLCON_NDIV_SHIFT) +# define SCU_USBPLLCON_NDIV(n) ((uint32_t)((n)-1) << SCU_USBPLLCON_NDIV_SHIFT) +#define SCU_USBPLLCON_PLLPWD (1 << 16) /* Bit 16: PLL Power Saving Mode */ +#define SCU_USBPLLCON_RESLD (1 << 18) /* Bit 18: Restart VCO Lock Detection */ +#define SCU_USBPLLCON_PDIV_SHIFT (24) /* Bits 24-27: P-Divider Value */ +#define SCU_USBPLLCON_PDIV_MASK (15 << SCU_USBPLLCON_PDIV_SHIFT) +# define SCU_USBPLLCON_PDIV(n) ((uint32_t)((n)-1) << SCU_USBPLLCON_PDIV_SHIFT) + /* Clock Multiplexing Status Register */ -#define SCU_CLKMXSTAT_ + +#define SCU_CLKMXSTAT_SYSCLKMUX_SHIFT (0) /* Bits 0-1: System Clock Multiplexing Status */ +#define SCU_CLKMXSTAT_SYSCLKMUX_MASK (3 << SCU_CLKMXSTAT_SYSCLKMUX_SHIFT) +# define SCU_CLKMXSTAT_SYSCLKMUX_OFI (1 << SCU_CLKMXSTAT_SYSCLKMUX_SHIFT) +# define SCU_CLKMXSTAT_SYSCLKMUX_PLL (2 << SCU_CLKMXSTAT_SYSCLKMUX_SHIFT) #endif /* __ARCH_ARM_SRC_XMC4_CHIP_XMC4_SCU_H */ diff --git a/arch/arm/src/xmc4/xmc4_clockconfig.c b/arch/arm/src/xmc4/xmc4_clockconfig.c index d7d5a8bc7df..6667ceca861 100644 --- a/arch/arm/src/xmc4/xmc4_clockconfig.c +++ b/arch/arm/src/xmc4/xmc4_clockconfig.c @@ -56,6 +56,7 @@ #include #include "up_arch.h" +#include "chip/xmc4_scu.h" #include @@ -63,10 +64,77 @@ * Pre-processor Definitions ****************************************************************************/ +/* Oscilator reference frequency */ + +#define FOSCREF (2500000U) + +/* Loop delays at different CPU frequencies */ + +#define DELAY_CNT_50US_50MHZ (2500) +#define DELAY_CNT_150US_50MHZ (7500) +#define DELAY_CNT_50US_48MHZ (2400) +#define DELAY_CNT_50US_72MHZ (3600) +#define DELAY_CNT_50US_96MHZ (4800) +#define DELAY_CNT_50US_120MHZ (6000) +#define DELAY_CNT_50US_144MHZ (7200) + +/* PLL settings */ + +#define SCU_PLLSTAT_OSC_USABLE \ + (SCU_PLLSTAT_PLLHV | SCU_PLLSTAT_PLLLV | SCU_PLLSTAT_PLLSP) + +#ifndef BOARD_PLL_CLOCKSRC_XTAL +# define VCO ((BOARD_XTAL_FREQUENCY / BOARD_PLL_PDIV) * BOARD_PLL_NDIV) +#else /* BOARD_PLL_CLOCKSRC_XTAL */ + +# define BOARD_PLL_PDIV 2 +# define BOARD_PLL_NDIV 24 +# define BOARD_PLL_K2DIV 1 + +# define VCO ((OFI_FREQUENCY / BOARD_PLL_PDIV) * BOARD_PLL_NDIV) + +#endif /* !BOARD_PLL_CLOCKSRC_XTAL */ + +#define PLL_K2DIV_24MHZ (VCO / OFI_FREQUENCY) +#define PLL_K2DIV_48MHZ (VCO / 48000000) +#define PLL_K2DIV_72MHZ (VCO / 72000000) +#define PLL_K2DIV_96MHZ (VCO / 96000000) +#define PLL_K2DIV_120MHZ (VCO / 120000000) + +#define CLKSET_VALUE (0x00000000) +#define SYSCLKCR_VALUE (0x00010001) +#define CPUCLKCR_VALUE (0x00000000) +#define PBCLKCR_VALUE (0x00000000) +#define CCUCLKCR_VALUE (0x00000000) +#define WDTCLKCR_VALUE (0x00000000) +#define EBUCLKCR_VALUE (0x00000003) +#define USBCLKCR_VALUE (0x00010000) +#define EXTCLKCR_VALUE (0x01200003) + +#if ((USBCLKCR_VALUE & SCU_USBCLKCR_USBSEL) == SCU_USBCLKCR_USBSEL_USBPLL) +# define USB_DIV 3 +#else +# define USB_DIV 5 +#endif + /**************************************************************************** * Private Functions ****************************************************************************/ +/**************************************************************************** + * Name: delay + ****************************************************************************/ + +static void delay(uint32_t cycles) +{ + volatile uint32_t i; + + for (i = 0; i < cycles ;++i) + { + __asm__ __volatile__ ("nop"); + } +} + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -83,6 +151,383 @@ void xmc4_clock_configure(void) { + uint32_t regval; + uint32_t bitset; + + /* Disable and clear OSC_HP Oscillator Watchdog, System VCO Lock, USB VCO + * Lock, and OSC_ULP Oscillator Watchdog traps. + */ + + bitset = SCU_TRAP_SOSCWDGT | SCU_TRAP_SVCOLCKT | SCU_TRAP_UVCOLCKT | + SCU_TRAP_ULPWDGT; + + regval = getreg32(XMC4_SCU_TRAPDIS); + regval |= bitset; + putreg32(regval, XMC4_SCU_TRAPDIS); + putreg32(bitset, XMC4_SCU_TRAPCLR); + +#ifdef BOARD_FOFI_CALIBRATION + /* Enable factory calibration */ + + regval = getreg32(XMC4_SCU_PLLCON0); + regval |= SCU_PLLCON0_FOTR; + putreg(regval, XMC4_SCU_PLLCON0); +#else + /* Automatic calibration uses the fSTDBY */ + + /* Enable HIB domain */ + /* Power up HIB domain if and only if it is currently powered down */ + + regval = getreg32(XMC4_SCU_PWRSTAT); + if ((regval & SCU_PWR_HIBEN) == 0) + { + regval = getreg32(XMC4_SCU_PWRSET); + regval |= SCU_PWR_HIBEN; + putreg32(regval, XMC4_SCU_PWRSTAT); + + /* Wait until HIB domain is enabled */ + + while((getreg32(XMC4_SCU_PWRSTAT) & SCU_PWR_HIBEN) == 0) + { + } + } + + /* Remove the reset only if HIB domain were in a state of reset */ + + regval = getreg32(XMC4_SCU_RSTSTAT); + if ((regval & SCU_RSTSTAT_HIBRS) ! = 0) + { + regval = getreg32(XMC4_SCU_RSTSTAT); + SCU_RESET->RSTCLR |= SCU_RESET_RSTCLR_HIBRS_Msk; + delay(DELAY_CNT_150US_50MHZ); + } + +#ifdef BOARD_STDBY_CLOCKSRC_OSCULP + /* Enable OSC_ULP */ + + regval = getreg32(XMC4_SCU_OSCULCTRL); + if ((regval & SCU_OSCULCTRL_MODE_MASK) != 0) + { + /* Check SCU_MIRRSTS to ensure that no transfer over serial interface + * is pending. + */ + + while ((getreg32(XMC4_SCU_MIRRSTS) & SCU_MIRRSTS_OSCULCTRL) != 0) + { + } + + /* Enable OSC_ULP */ + + regval &= ~SCU_OSCULCTRL_MODE_MASK; + putreg32(regval, XMC4_SCU_OSCULCTRL); + + /* Check if the clock is OK using OSCULP Oscillator Watchdog */ + + while ((getreg32(XMC4_SCU_MIRRSTS) & SCU_MIRRSTS_HDCR) != 0) + { + } + + regval = getreg32(XMC4_SCU_HDCR); + regval |= SCU_HDCR_ULPWDGEN; + putreg32(regval, XMC4_SCU_HDCR) + + /* Wait till clock is stable */ + + do + { + /* Check SCU_MIRRSTS to ensure that no transfer over serial interface + * is pending. + */ + + while ((getreg32(XMC4_SCU_MIRRSTS) & SCU_MIRRSTS_HDCLR) != 0) + { + } + + putreg32(SCU_HDCLR_ULPWDG, XMC4_SCU_HDCLR) + delay(DELAY_CNT_50US_50MHZ); + } + while ((getreg32(XMC4_SCU_HDSTAT) & SCU_HDSTAT_ULPWDG) != 0); + } + + /* Now OSC_ULP is running and can be used */ + + while ((getreg32(XMC4_SCU_MIRRSTS) & SCU_MIRRSTS_HDCR) != 0) + { + } + + /* Select OSC_ULP as the clock source for RTC and STDBY */ + + regval = getreg32(XMC4_SCU_HDCR); + regval |= (SCU_HDCR_RCS_ULP | SCU_HDCR_STDBYSEL_ULP); + putreg32(regval, XMC4_SCU_HDCR) + + regval = getreg32(XMC4_SCU_TRAPDIS); + regval &= ~SCU_TRAP_ULPWDGT; + putreg32(regval, XMC4_SCU_TRAPDIS); + +#endif /* BOARD_STDBY_CLOCKSRC_OSCULP */ + + /* Enable automatic calibration of internal fast oscillator */ + + regval = getreg32(XMC4_SCU_PLLCON0); + regval |= SCU_PLLCON0_AOTREN; + putreg(regval, XMC4_SCU_PLLCON0); + +#endif /* BOARD_FOFI_CALIBRATION */ + + delay(DELAY_CNT_50US_50MHZ); + +#if BOARD_ENABLE_PLL + + /* Enable PLL */ + + regval = getreg32(XMC4_SCU_PLLCON0); + regval &= ~(SCU_PLLCON0_VCOPWD | SCU_PLLCON0_PLLPWD); + putreg(regval, XMC4_SCU_PLLCON0); + +#ifdef BOARD_PLL_CLOCKSRC_XTAL + /* Enable OSC_HP */ + + if ((getreg32(XMC4_SCU_OSCHPCTRL) & SCU_OSCHPCTRL_MODE_MASK) != 0U) + { + regval = getreg32(XMC4_SCU_OSCHPCTRL); + regval &= ~(SCU_OSCHPCTRL_MODE_MASK | SCU_OSCHPCTRL_OSCVAL_MASK); + regval |= ((OSCHP_GetFrequency() / FOSCREF) - 1) << SCU_OSCHPCTRL_OSCVAL_SHIFT; + putreg32(regval, XMC4_SCU_OSCHPCTRL); + + /* Select OSC_HP clock as PLL input */ + + regval = getreg32(XMC4_SCU_PLLCON2); + regval &= ~SCU_PLLCON2_PINSEL; + putreg32(regval, XMC4_SCU_PLLCON2); + + /* Restart OSC Watchdog */ + + regval = getreg32(XMC4_SCU_PLLCON0); + regval &= ~SCU_PLLCON0_OSCRES; + putreg(regval, XMC4_SCU_PLLCON0); + + /* Wait till OSC_HP output frequency is usable */ + + while ((getreg32(XMC4_SCU_PLLSTAT) & SCU_PLLSTAT_OSC_USABLE) != SCU_PLLSTAT_OSC_USABLE) + { + } + + regval = getreg32(SCU_TRAP_SOSCWDGT); + regval &= ~bitset; + putreg32(regval, SCU_TRAP_SOSCWDGT); + } +#else /* BOARD_PLL_CLOCKSRC_XTAL */ + + /* Select backup clock as PLL input */ + + regval = getreg32(XMC4_SCU_PLLCON2); + regval |= SCU_PLLCON2_PINSEL; + putreg32(regval, XMC4_SCU_PLLCON2); +#endif + + /* Go to bypass the Main PLL */ + + regval = getreg32(XMC4_SCU_PLLCON0); + regval |= SCU_PLLCON0_VCOBYP; + putreg(regval, XMC4_SCU_PLLCON0); + + /* Disconnect Oscillator from PLL */ + + regval |= SCU_PLLCON0_FINDIS; + putreg(regval, XMC4_SCU_PLLCON0); + + /* Setup divider settings for main PLL */ + + regval = (SCU_PLLCON1_NDIV(BOARD_PLL_NDIV) | + SCU_PLLCON1_K2DIV(PLL_K2DIV_24MHZ) | + SCU_PLLCON1_PDIV(BOARD_PLL_PDIV); + putreg32(regval, XMC4_SCU_PLLCON1); + + /* Set OSCDISCDIS */ + + regval = getreg32(XMC4_SCU_PLLCON0); + regval |= SCU_PLLCON0_OSCDISCDIS; + putreg(regval, XMC4_SCU_PLLCON0); + + /* Connect Oscillator to PLL */ + + regval = getreg32(XMC4_SCU_PLLCON0); + regval &= ~SCU_PLLCON0_FINDIS; + putreg(regval, XMC4_SCU_PLLCON0); + + /* Restart PLL Lock detection */ + + regval |= SCU_PLLCON0_RESLD; + putreg(regval, XMC4_SCU_PLLCON0); + + /* wait for PLL Lock at 24MHz*/ + + while ((getreg32(XMC4_SCU_PLLSTAT) & SCU_PLLSTAT_VCOLOCK) == 0) + { + } + + /* Disable bypass- put PLL clock back */ + + regval = getreg32(XMC4_SCU_PLLCON0); + regval &= ~SCU_PLLCON0_VCOBYP; + putreg(regval, XMC4_SCU_PLLCON0); + + /* Wait for normal mode */ + + while ((getreg32(XMC4_SCU_PLLSTAT) & SCU_PLLSTAT_VCOBYST) != 0) + { + } + + regval = getreg32(XMC4_SCU_TRAPDIS); + regval &= ~SCU_TRAP_UVCOLCKT; + putreg32(regval, XMC4_SCU_TRAPDIS); +#endif /* BOARD_ENABLE_PLL */ + + /* Before scaling to final frequency we need to setup the clock dividers */ + + putreg32(SYSCLKCR_VALUE, XMC4_SCU_SYSCLKCR); + putreg32(PBCLKCR_VALUE, XMC4_SCU_PBCLKCR); + putreg32(CPUCLKCR_VALUE, XMC4_SCU_CPUCLKCR); + putreg32(CCUCLKCR_VALUE, XMC4_SCU_CCUCLKCR); + putreg32(WDTCLKCR_VALUE, XMC4_SCU_WDTCLKCR); + putreg32(EBUCLKCR_VALUE, XMC4_SCU_EBUCLKCR); + putreg32(USBCLKCR_VALUE | USB_DIV, XMC4_SCU_USBCLKCR); + putreg32(EXTCLKCR_VALUE, EXTCLKCR); + +#if BOARD_ENABLE_PLL + /* PLL frequency stepping...*/ + /* Reset OSCDISCDIS */ + + regval = getreg32(XMC4_SCU_PLLCON0); + regval &= ~SCU_PLLCON0_OSCDISCDIS; + putreg(regval, XMC4_SCU_PLLCON0); + + regval = (SCU_PLLCON1_NDIV(BOARD_PLL_NDIV) | + SCU_PLLCON1_K2DIV(PLL_K2DIV_48MHZ) | + SCU_PLLCON1_PDIV(BOARD_PLL_PDIV)); + putreg32(regval, XMC4_SCU_PLLCON1); + + delay(DELAY_CNT_50US_48MHZ); + + regval = (SCU_PLLCON1_NDIV(BOARD_PLL_NDIV) | + SCU_PLLCON1_K2DIV(PLL_K2DIV_72MHZ) | + SCU_PLLCON1_PDIV(BOARD_PLL_PDIV)); + putreg32(regval, XMC4_SCU_PLLCON1); + + delay(DELAY_CNT_50US_72MHZ); + + regval = (SCU_PLLCON1_NDIV(BOARD_PLL_NDIV) | + SCU_PLLCON1_K2DIV(PLL_K2DIV_96MHZ) | + SCU_PLLCON1_PDIV(BOARD_PLL_PDIV)); + putreg32(regval, XMC4_SCU_PLLCON1); + + delay(DELAY_CNT_50US_96MHZ); + + regval = (SCU_PLLCON1_NDIV(BOARD_PLL_NDIV) | + SCU_PLLCON1_K2DIV(PLL_K2DIV_120MHZ) | + SCU_PLLCON1_PDIV(BOARD_PLL_PDIV)); + putreg32(regval, XMC4_SCU_PLLCON1); + + delay(DELAY_CNT_50US_120MHZ); + + regval = (SCU_PLLCON1_NDIV(BOARD_PLL_NDIV) | + SCU_PLLCON1_K2DIV(BOARD_PLL_K2DIV) | + SCU_PLLCON1_PDIV(BOARD_PLL_PDIV)); + putreg32(regval, XMC4_SCU_PLLCON1); + + delay(DELAY_CNT_50US_144MHZ); + +#endif /* BOARD_ENABLE_PLL */ + +#if BOARD_ENABLE_USBPLL + /* Enable USB PLL first */ + + regval = getreg32(XMC4_SCU_USBPLLCON); + regval &= ~(SCU_USBPLLCON_VCOPWD | SCU_USBPLLCON_PLLPWD); + getreg32(regval, XMC4_SCU_USBPLLCON); + + /* USB PLL uses as clock input the OSC_HP */ + /* check and if not already running enable OSC_HP */ + + if ((getreg32(XMC4_SCU_OSCHPCTRL) & SCU_OSCHPCTRL_MODE_MASK) != 0U) + { + /* Check if Main PLL is switched on for OSC WDG */ + + regval = getreg32(XMC4_SCU_PLLCON0); + if ((regval & (SCU_PLLCON0_VCOPWD | SCU_PLLCON0_PLLPWD)) != 0) + { + /* Enable PLL first */ + + regval = getreg32(XMC4_SCU_PLLCON0); + regval &= ~(SCU_PLLCON0_VCOPWD | SCU_PLLCON0_PLLPWD); + putreg(regval, XMC4_SCU_PLLCON0); + } + + regval = getreg32(XMC4_SCU_OSCHPCTRL); + regval &= ~(SCU_OSCHPCTRL_MODE_MASK | SCU_OSCHPCTRL_OSCVAL_MASK); + regval |= ((OSCHP_GetFrequency() / FOSCREF) - 1) << SCU_OSCHPCTRL_OSCVAL_SHIFT; + putreg32(regval, XMC4_SCU_OSCHPCTRL); + + /* Restart OSC Watchdog */ + + regval = getreg32(XMC4_SCU_PLLCON0); + regval &= ~SCU_PLLCON0_OSCRES; + putreg(regval, XMC4_SCU_PLLCON0); + + /* Wait till OSC_HP output frequency is usable */ + + while ((getreg32(XMC4_SCU_PLLSTAT) & SCU_PLLSTAT_OSC_USABLE) != SCU_PLLSTAT_OSC_USABLE) + { + } + } + + /* Setup USB PLL */ + /* Go to bypass the USB PLL */ + + regval = getreg32(XMC4_SCU_USBPLLCON); + regval |= SCU_USBPLLCON_VCOBYP; + putreg32(regval, XMC4_SCU_USBPLLCON); + + /* Disconnect Oscillator from USB PLL */ + + regval |= SCU_USBPLLCON_FINDIS; + putreg32(regval, XMC4_SCU_USBPLLCON); + + /* Setup Divider settings for USB PLL */ + + regval = (SCU_USBPLLCON_NDIV(BOARD_USB_NDIV) | SCU_USBPLLCON_PDIV(BOARD_USB_PDIV)); + putreg32(regval, XMC4_SCU_USBPLLCON); + + /* Set OSCDISCDIS */ + + regval |= SCU_USBPLLCON_OSCDISCDIS; + putreg32(regval, XMC4_SCU_USBPLLCON); + + /* Connect Oscillator to USB PLL */ + + regval &= ~SCU_USBPLLCON_FINDIS; + putreg32(regval, XMC4_SCU_USBPLLCON); + + /* Restart PLL Lock detection */ + + regval |= SCU_USBPLLCON_RESLD; + putreg32(regval, XMC4_SCU_USBPLLCON); + + /* Wait for PLL Lock */ + + while ((getreg32(XMC4_SCU_USBPLLSTAT) & SCU_USBPLLSTAT_VCOLOCK) == 0) + { + } + + regval = getreg32(XMC4_SCU_TRAPDIS); + regval &= ~SCU_TRAP_UVCOLCKT; + putreg32(regval, XMC4_SCU_TRAPDIS); +#endif + + /* Enable selected clocks */ + + putreg32(CLKSET_VALUE, XMC4_SCU_CLKSET) } /**************************************************************************** diff --git a/arch/arm/src/xmc4/xmc4_start.c b/arch/arm/src/xmc4/xmc4_start.c index 77e792847e9..e712f97dd37 100644 --- a/arch/arm/src/xmc4/xmc4_start.c +++ b/arch/arm/src/xmc4/xmc4_start.c @@ -48,6 +48,7 @@ #include "up_arch.h" #include "up_internal.h" +#include "chip/xmc4_flash.h" #include "xmc4_userspace.h" @@ -62,6 +63,8 @@ #ifdef CONFIG_ARCH_FPU static inline void xmc4_fpu_config(void); #endif +static inline void xmc4_unaligned(void); +static inline void xmc4_flash_waitstates(void); #ifdef CONFIG_STACK_COLORATION static void go_os_start(void *pv, unsigned int nbytes) __attribute__ ((naked, no_instrument_function, noreturn)); @@ -214,6 +217,41 @@ static inline void xmc4_fpu_config(void) # define xmc4_fpu_config() #endif +/**************************************************************************** + * Name: xmc4_unaligned + * + * Description: + * Enable unaligned memory access by setting SCB_CCR.UNALIGN_TRP = 0 + * + ****************************************************************************/ + +static inline void xmc4_unaligned(void) +{ + uint32_t regval; + + regval = getreg32(NVIC_CFGCON); + regval &= ~NVIC_CFGCON_UNALIGNTRP; + putreg32(regval, NVIC_CFGCON); +} + +/**************************************************************************** + * Name: xmc4_flash_waitstates + * + * Description: + * Enable unaligned memory access by setting SCB_CCR.UNALIGN_TRP = 0 + * + ****************************************************************************/ + +static inline void xmc4_flash_waitstates(void) +{ + uint32_t regval; + + regval = getreg32(XMC4_FLASH_FCON); + regval &= ~FLASH_FCON_WSPFLASH_MASK; + regval |= FLASH_FCON_WSPFLASH(BOARD_FLASH_WS); + putreg32(regval, XMC4_FLASH_FCON); +} + /**************************************************************************** * Name: go_os_start * @@ -281,6 +319,10 @@ void __start(void) xmc4_wddisable(); + /* Enable unaligned memory access */ + + xmc4_unaligned(); + /* Clear .bss. We'll do this inline (vs. calling memset) just to be * certain that there are no issues with the state of global variables. */ @@ -314,6 +356,10 @@ void __start(void) } #endif + /* Set FLASH wait states prior to the configuration of clocking */ + + xmc4_flash_waitstates(); + /* Perform clock and Kinetis module initialization (This depends on * RAM functions having been copied to RAM). */ diff --git a/configs/xmc4500-relax/include/board.h b/configs/xmc4500-relax/include/board.h index a448469bca7..f3616a21e2c 100644 --- a/configs/xmc4500-relax/include/board.h +++ b/configs/xmc4500-relax/include/board.h @@ -65,6 +65,8 @@ * fOFI = 24MHz => fWDT = 24MHz */ +#undef BOARD_FOFI_CALIBRATION /* Enable factory calibration */ + /* On-board crystals * * NOTE: Only the XMC4500 Relax Kit-V1 provides the 32.768KHz RTC crystal. It @@ -87,6 +89,7 @@ * = 288MHz */ +#define BOARD_ENABLE_PLL 1 #define BOARD_PLL_PDIV 2 #define BOARD_PLL_NDIV 48 #define BOARD_PLL_K2DIV 1 @@ -119,9 +122,14 @@ * fUSBPLLVCO <= 520 MHz */ +#undef BOARD_ENABLE_USBPLL #define BOARD_USB_PDIV 2 #define BOARD_USB_NDIV 64 +/* FLASH wait states */ + +#define BOARD_FLASH_WS 5 + /************************************************************************************ * Public Data ************************************************************************************/ From fe610e7a1d793919f14aaa7f01b69659c51220ec Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 16 Mar 2017 10:52:01 -0600 Subject: [PATCH 11/81] XMC4500 Relax: Add basic board support infrastructure of Infineon XMC4500 Relax Lite v1 --- arch/arm/Kconfig | 25 +- arch/arm/src/xmc4/Kconfig | 2 +- configs/Kconfig | 13 + configs/README.txt | 3 + configs/xmc4500-relax/Kconfig | 4 + configs/xmc4500-relax/nsh/Make.defs | 128 +++ configs/xmc4500-relax/nsh/defconfig | 1038 +++++++++++++++++++++ configs/xmc4500-relax/nsh/setenv.sh | 77 ++ configs/xmc4500-relax/src/Makefile | 55 ++ configs/xmc4500-relax/src/xmc4500-relax.h | 78 ++ configs/xmc4500-relax/src/xmc4_appinit.c | 80 ++ configs/xmc4500-relax/src/xmc4_autoleds.c | 80 ++ configs/xmc4500-relax/src/xmc4_boot.c | 91 ++ configs/xmc4500-relax/src/xmc4_bringup.c | 65 ++ configs/xmc4500-relax/src/xmc4_buttons.c | 78 ++ configs/xmc4500-relax/src/xmc4_userleds.c | 75 ++ 16 files changed, 1879 insertions(+), 13 deletions(-) create mode 100644 configs/xmc4500-relax/Kconfig create mode 100644 configs/xmc4500-relax/nsh/Make.defs create mode 100644 configs/xmc4500-relax/nsh/defconfig create mode 100644 configs/xmc4500-relax/nsh/setenv.sh create mode 100644 configs/xmc4500-relax/src/Makefile create mode 100644 configs/xmc4500-relax/src/xmc4500-relax.h create mode 100644 configs/xmc4500-relax/src/xmc4_appinit.c create mode 100644 configs/xmc4500-relax/src/xmc4_autoleds.c create mode 100644 configs/xmc4500-relax/src/xmc4_boot.c create mode 100644 configs/xmc4500-relax/src/xmc4_bringup.c create mode 100644 configs/xmc4500-relax/src/xmc4_buttons.c create mode 100644 configs/xmc4500-relax/src/xmc4_userleds.c diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 21334e71178..ce6fc7f2af3 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -151,6 +151,14 @@ config ARCH_CHIP_LPC43XX ---help--- NPX LPC43XX architectures (ARM Cortex-M4). +config ARCH_CHIP_MOXART + bool "MoxART" + select ARCH_ARM7TDMI + select ARCH_HAVE_RESET + select ARCH_HAVE_SERIAL_TERMIOS + ---help--- + MoxART family + config ARCH_CHIP_NUC1XX bool "Nuvoton NUC100/120" select ARCH_CORTEXM0 @@ -283,14 +291,6 @@ config ARCH_CHIP_XMC4 ---help--- Infineon XMC4xxx(ARM Cortex-M4) architectures -config ARCH_CHIP_MOXART - bool "MoxART" - select ARCH_ARM7TDMI - select ARCH_HAVE_RESET - select ARCH_HAVE_SERIAL_TERMIOS - ---help--- - MoxART family - endchoice config ARCH_ARM7TDMI @@ -434,6 +434,7 @@ config ARCH_CHIP default "lpc2378" if ARCH_CHIP_LPC2378 default "lpc31xx" if ARCH_CHIP_LPC31XX default "lpc43xx" if ARCH_CHIP_LPC43XX + default "moxart" if ARCH_CHIP_MOXART default "nuc1xx" if ARCH_CHIP_NUC1XX default "sama5" if ARCH_CHIP_SAMA5 default "samdl" if ARCH_CHIP_SAMD || ARCH_CHIP_SAML @@ -444,7 +445,7 @@ config ARCH_CHIP default "stm32l4" if ARCH_CHIP_STM32L4 default "str71x" if ARCH_CHIP_STR71X default "tms570" if ARCH_CHIP_TMS570 - default "moxart" if ARCH_CHIP_MOXART + default "xmc4" if ARCH_CHIP_XMC4 config ARM_TOOLCHAIN_IAR bool @@ -675,6 +676,9 @@ endif if ARCH_CHIP_LPC43XX source arch/arm/src/lpc43xx/Kconfig endif +if ARCH_CHIP_MOXART +source arch/arm/src/moxart/Kconfig +endif if ARCH_CHIP_NUC1XX source arch/arm/src/nuc1xx/Kconfig endif @@ -708,8 +712,5 @@ endif if ARCH_CHIP_XMC4 source arch/arm/src/xmc4/Kconfig endif -if ARCH_CHIP_MOXART -source arch/arm/src/moxart/Kconfig -endif endif # ARCH_ARM diff --git a/arch/arm/src/xmc4/Kconfig b/arch/arm/src/xmc4/Kconfig index 116d56d14f2..096a65fb858 100644 --- a/arch/arm/src/xmc4/Kconfig +++ b/arch/arm/src/xmc4/Kconfig @@ -50,7 +50,7 @@ config XMC4_USCI_I2S # Chip families -menu "ARCH_CHIP_XMC4 Peripheral Support" +menu "XMC4xxx Peripheral Support" config XMC4_USIC0 bool "USIC0" diff --git a/configs/Kconfig b/configs/Kconfig index d5016d9b7ce..d4bb9fe5bd0 100644 --- a/configs/Kconfig +++ b/configs/Kconfig @@ -1270,6 +1270,15 @@ config ARCH_BOARD_VIEWTOOL_STM32F107 board may be fitted with either: (1) STM32F107VCT6 or (2) STM32F103VCT6. See http://www.viewtool.com/ for further information. +config ARCH_BOARD_XMC4500RELAX + bool "Infineon XMC4500 Relax" + depends on ARCH_CHIP_XMC4500 + select ARCH_HAVE_LEDS + select ARCH_HAVE_BUTTONS + select ARCH_HAVE_IRQBUTTONS + ---help--- + Infineon XMC4000 Relax Lite v1 + config ARCH_BOARD_XTRS bool "XTRS TRS80 Model 3 emulation" depends on ARCH_CHIP_Z80 @@ -1531,6 +1540,7 @@ config ARCH_BOARD default "ubw32" if ARCH_BOARD_UBW32 default "us7032evb1" if ARCH_BOARD_US7032EVB1 default "viewtool-stm32f107" if ARCH_BOARD_VIEWTOOL_STM32F107 + default "xmc4500-relax" if ARCH_BOARD_XMC4500RELAX default "xtrs" if ARCH_BOARD_XTRS default "z16f2800100zcog" if ARCH_BOARD_Z16F2800100ZCOG default "z80sim" if ARCH_BOARD_Z80SIM @@ -1936,6 +1946,9 @@ endif if ARCH_BOARD_VIEWTOOL_STM32F107 source "configs/viewtool-stm32f107/Kconfig" endif +if ARCH_BOARD_XMC4500RELAX +source "configs/xmc4500-relax/Kconfig" +endif if ARCH_BOARD_XTRS source "configs/xtrs/Kconfig" endif diff --git a/configs/README.txt b/configs/README.txt index b883163e718..316108f8774 100644 --- a/configs/README.txt +++ b/configs/README.txt @@ -763,6 +763,9 @@ configs/viewtool-stm32f107 board may be fitted with either: (1) STM32F107VCT6 or (2) STM32F103VCT6. See http://www.viewtool.com/ for further information. +config/xmc4500-relax + Infineon XMC4000 Relax Lite v1 + configs/xtrs TRS80 Model 3. This port uses a vintage computer based on the Z80. An emulator for this computer is available to run TRS80 programs on a diff --git a/configs/xmc4500-relax/Kconfig b/configs/xmc4500-relax/Kconfig new file mode 100644 index 00000000000..f72f3c094ce --- /dev/null +++ b/configs/xmc4500-relax/Kconfig @@ -0,0 +1,4 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# diff --git a/configs/xmc4500-relax/nsh/Make.defs b/configs/xmc4500-relax/nsh/Make.defs new file mode 100644 index 00000000000..2d795a8ee1d --- /dev/null +++ b/configs/xmc4500-relax/nsh/Make.defs @@ -0,0 +1,128 @@ +############################################################################ +# configs/xmc4500-relax/nsh/Make.defs +# +# Copyright (C) 2017 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +include ${TOPDIR}/.config +include ${TOPDIR}/tools/Config.mk +include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs + +ifeq ($(CONFIG_ARMV7M_DTCM),y) + LDSCRIPT = flash-dtcm.ld +else + LDSCRIPT = flash-sram.ld +endif + +ifeq ($(WINTOOL),y) + # Windows-native toolchains + DIRLINK = $(TOPDIR)/tools/copydir.sh + DIRUNLINK = $(TOPDIR)/tools/unlink.sh + MKDEP = $(TOPDIR)/tools/mkwindeps.sh + ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" + ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" + ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}" +else + # Linux/Cygwin-native toolchain + MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT) + ARCHINCLUDES = -I. -isystem $(TOPDIR)/include + ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx + ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT) +endif + +CC = $(CROSSDEV)gcc +CXX = $(CROSSDEV)g++ +CPP = $(CROSSDEV)gcc -E +LD = $(CROSSDEV)ld +AR = $(CROSSDEV)ar rcs +NM = $(CROSSDEV)nm +OBJCOPY = $(CROSSDEV)objcopy +OBJDUMP = $(CROSSDEV)objdump + +ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'} +ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1} + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g +endif + +ifneq ($(CONFIG_DEBUG_NOOPT),y) + ARCHOPTIMIZATION += $(MAXOPTIMIZATION) +endif + +ARCHCFLAGS = -fno-builtin +ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -fno-rtti +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -fno-strict-aliasing +ARCHWARNINGSXX = -Wall -Wshadow -Wundef +ARCHDEFINES = +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) +AFLAGS = $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +# Loadable module definitions + +CMODULEFLAGS = $(CFLAGS) -mlong-calls # --target1-abs + +LDMODULEFLAGS = -r -e module_initialize +ifeq ($(WINTOOL),y) + LDMODULEFLAGS += -T "${shell cygpath -w $(TOPDIR)/libc/modlib/gnu-elf.ld}" +else + LDMODULEFLAGS += -T $(TOPDIR)/libc/modlib/gnu-elf.ld +endif + +ASMEXT = .S +OBJEXT = .o +LIBEXT = .a +EXEEXT = + +ifneq ($(CROSSDEV),arm-nuttx-elf-) + LDFLAGS += -nostartfiles -nodefaultlibs +endif +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + LDFLAGS += -g +endif + + +HOSTCC = gcc +HOSTINCLUDES = -I. +HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe +HOSTLDFLAGS = + diff --git a/configs/xmc4500-relax/nsh/defconfig b/configs/xmc4500-relax/nsh/defconfig new file mode 100644 index 00000000000..54bd16a3928 --- /dev/null +++ b/configs/xmc4500-relax/nsh/defconfig @@ -0,0 +1,1038 @@ +# +# Automatically generated file; DO NOT EDIT. +# Nuttx/ Configuration +# + +# +# Build Setup +# +# CONFIG_EXPERIMENTAL is not set +# CONFIG_DEFAULT_SMALL is not set +# CONFIG_HOST_LINUX is not set +# CONFIG_HOST_OSX is not set +CONFIG_HOST_WINDOWS=y +# CONFIG_HOST_OTHER is not set +CONFIG_TOOLCHAIN_WINDOWS=y +# CONFIG_WINDOWS_NATIVE is not set +CONFIG_WINDOWS_CYGWIN=y +# CONFIG_WINDOWS_UBUNTU is not set +# CONFIG_WINDOWS_MSYS is not set +# CONFIG_WINDOWS_OTHER is not set + +# +# Build Configuration +# +# CONFIG_APPS_DIR="../apps" +CONFIG_BUILD_FLAT=y +# CONFIG_BUILD_2PASS is not set + +# +# Binary Output Formats +# +# CONFIG_RRLOAD_BINARY is not set +# CONFIG_INTELHEX_BINARY is not set +# CONFIG_MOTOROLA_SREC is not set +CONFIG_RAW_BINARY=y +# CONFIG_UBOOT_UIMAGE is not set + +# +# Customize Header Files +# +# CONFIG_ARCH_STDINT_H is not set +# CONFIG_ARCH_STDBOOL_H is not set +# CONFIG_ARCH_MATH_H is not set +# CONFIG_ARCH_FLOAT_H is not set +# CONFIG_ARCH_STDARG_H is not set +# CONFIG_ARCH_DEBUG_H is not set + +# +# Debug Options +# +CONFIG_DEBUG_ALERT=y +# CONFIG_DEBUG_FEATURES is not set +CONFIG_ARCH_HAVE_STACKCHECK=y +# CONFIG_STACK_COLORATION is not set +# CONFIG_ARCH_HAVE_HEAPCHECK is not set +# CONFIG_DEBUG_SYMBOLS is not set +CONFIG_ARCH_HAVE_CUSTOMOPT=y +# CONFIG_DEBUG_NOOPT is not set +# CONFIG_DEBUG_CUSTOMOPT is not set +CONFIG_DEBUG_FULLOPT=y + +# +# System Type +# +CONFIG_ARCH_ARM=y +# CONFIG_ARCH_AVR is not set +# CONFIG_ARCH_HC is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set +# CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set +# CONFIG_ARCH_SIM is not set +# CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set +# CONFIG_ARCH_Z16 is not set +# CONFIG_ARCH_Z80 is not set +CONFIG_ARCH="arm" + +# +# ARM Options +# +# CONFIG_ARCH_CHIP_A1X is not set +# CONFIG_ARCH_CHIP_C5471 is not set +# CONFIG_ARCH_CHIP_DM320 is not set +# CONFIG_ARCH_CHIP_EFM32 is not set +# CONFIG_ARCH_CHIP_IMX1 is not set +# CONFIG_ARCH_CHIP_IMX6 is not set +# CONFIG_ARCH_CHIP_KINETIS is not set +# CONFIG_ARCH_CHIP_KL is not set +# CONFIG_ARCH_CHIP_LM is not set +# CONFIG_ARCH_CHIP_TIVA is not set +# CONFIG_ARCH_CHIP_LPC11XX is not set +# CONFIG_ARCH_CHIP_LPC17XX is not set +# CONFIG_ARCH_CHIP_LPC214X is not set +# CONFIG_ARCH_CHIP_LPC2378 is not set +# CONFIG_ARCH_CHIP_LPC31XX is not set +# CONFIG_ARCH_CHIP_LPC43XX is not set +# CONFIG_ARCH_CHIP_MOXART is not set +# CONFIG_ARCH_CHIP_NUC1XX is not set +# CONFIG_ARCH_CHIP_SAMA5 is not set +# CONFIG_ARCH_CHIP_SAMD is not set +# CONFIG_ARCH_CHIP_SAML is not set +# CONFIG_ARCH_CHIP_SAM34 is not set +# CONFIG_ARCH_CHIP_SAMV7 is not set +# CONFIG_ARCH_CHIP_STM32 is not set +# CONFIG_ARCH_CHIP_STM32F7 is not set +# CONFIG_ARCH_CHIP_STM32L4 is not set +# CONFIG_ARCH_CHIP_STR71X is not set +# CONFIG_ARCH_CHIP_TMS570 is not set +CONFIG_ARCH_CHIP_XMC4=y +# CONFIG_ARCH_ARM7TDMI is not set +# CONFIG_ARCH_ARM926EJS is not set +# CONFIG_ARCH_ARM920T is not set +# CONFIG_ARCH_CORTEXM0 is not set +# CONFIG_ARCH_CORTEXM23 is not set +# CONFIG_ARCH_CORTEXM3 is not set +# CONFIG_ARCH_CORTEXM33 is not set +CONFIG_ARCH_CORTEXM4=y +# CONFIG_ARCH_CORTEXM7 is not set +# CONFIG_ARCH_CORTEXA5 is not set +# CONFIG_ARCH_CORTEXA8 is not set +# CONFIG_ARCH_CORTEXA9 is not set +# CONFIG_ARCH_CORTEXR4 is not set +# CONFIG_ARCH_CORTEXR4F is not set +# CONFIG_ARCH_CORTEXR5 is not set +# CONFIG_ARCH_CORTEX5F is not set +# CONFIG_ARCH_CORTEXR7 is not set +# CONFIG_ARCH_CORTEXR7F is not set +CONFIG_ARCH_FAMILY="armv7-m" +CONFIG_ARCH_CHIP="xmc4" +# CONFIG_ARM_TOOLCHAIN_IAR is not set +CONFIG_ARM_TOOLCHAIN_GNU=y +# CONFIG_ARMV7M_USEBASEPRI is not set +CONFIG_ARCH_HAVE_CMNVECTOR=y +CONFIG_ARMV7M_CMNVECTOR=y +CONFIG_ARMV7M_LAZYFPU=y +# CONFIG_ARCH_HAVE_FPU is not set +# CONFIG_ARCH_HAVE_DPFPU is not set +# CONFIG_ARCH_HAVE_TRUSTZONE is not set +CONFIG_ARM_HAVE_MPU_UNIFIED=y +# CONFIG_ARM_MPU is not set + +# +# ARMV7M Configuration Options +# +# CONFIG_ARMV7M_HAVE_ICACHE is not set +# CONFIG_ARMV7M_HAVE_DCACHE is not set +# CONFIG_ARMV7M_HAVE_ITCM is not set +# CONFIG_ARMV7M_HAVE_DTCM is not set +# CONFIG_ARMV7M_TOOLCHAIN_IARW is not set +# CONFIG_ARMV7M_TOOLCHAIN_ATOLLIC is not set +# CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT is not set +# CONFIG_ARMV7M_TOOLCHAIN_CODEREDW is not set +# CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW is not set +# CONFIG_ARMV7M_TOOLCHAIN_DEVKITARM is not set +# CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL is not set +CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIW=y +# CONFIG_ARMV7M_TOOLCHAIN_RAISONANCE is not set +CONFIG_ARMV7M_HAVE_STACKCHECK=y +# CONFIG_ARMV7M_STACKCHECK is not set +# CONFIG_ARMV7M_ITMSYSLOG is not set + +# +# XMC4xxx Configuration Options +# +CONFIG_ARCH_CHIP_XMC4500=y +CONFIG_XMC4_USIC=y +CONFIG_XMC4_USCI_UART=y +# CONFIG_XMC4_USCI_LIN is not set +# CONFIG_XMC4_USCI_SPI is not set +# CONFIG_XMC4_USCI_I2C is not set +# CONFIG_XMC4_USCI_I2S is not set + +# +# XMC4xxx Peripheral Support +# +CONFIG_XMC4_USIC0=y +# CONFIG_XMC4_USIC1 is not set +# CONFIG_XMC4_USIC2 is not set +# CONFIG_XMC4_USIC3 is not set +# CONFIG_XMC4_USIC4 is not set +# CONFIG_XMC4_USIC5 is not set + +# +# XMC4xxx USIC Configuration +# +CONFIG_XMC4_USIC0_ISUART=y +# CONFIG_XMC4_USIC0_ISLIN is not set +# CONFIG_XMC4_USIC0_ISSPI is not set +# CONFIG_XMC4_USIC0_ISI2C is not set +# CONFIG_XMC4_USIC0_ISI2S is not set + +# +# Architecture Options +# +# CONFIG_ARCH_NOINTC is not set +# CONFIG_ARCH_VECNOTIRQ is not set +# CONFIG_ARCH_DMA is not set +CONFIG_ARCH_HAVE_IRQPRIO=y +# CONFIG_ARCH_L2CACHE is not set +# CONFIG_ARCH_HAVE_COHERENT_DCACHE is not set +# CONFIG_ARCH_HAVE_ADDRENV is not set +# CONFIG_ARCH_NEED_ADDRENV_MAPPING is not set +# CONFIG_ARCH_HAVE_MULTICPU is not set +CONFIG_ARCH_HAVE_VFORK=y +# CONFIG_ARCH_HAVE_MMU is not set +CONFIG_ARCH_HAVE_MPU=y +# CONFIG_ARCH_NAND_HWECC is not set +# CONFIG_ARCH_HAVE_EXTCLK is not set +# CONFIG_ARCH_HAVE_POWEROFF is not set +CONFIG_ARCH_HAVE_RESET=y +# CONFIG_ARCH_USE_MPU is not set +# CONFIG_ARCH_IRQPRIO is not set +CONFIG_ARCH_STACKDUMP=y +# CONFIG_ENDIAN_BIG is not set +# CONFIG_ARCH_IDLE_CUSTOM is not set +CONFIG_ARCH_HAVE_RAMFUNCS=y +# CONFIG_ARCH_RAMFUNCS is not set +CONFIG_ARCH_HAVE_RAMVECTORS=y +# CONFIG_ARCH_RAMVECTORS is not set +# CONFIG_ARCH_MINIMAL_VECTORTABLE is not set + +# +# Board Settings +# +CONFIG_BOARD_LOOPSPERMSEC=8000 +# CONFIG_ARCH_CALIBRATION is not set + +# +# Interrupt options +# +CONFIG_ARCH_HAVE_INTERRUPTSTACK=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_HAVE_HIPRI_INTERRUPT=y +# CONFIG_ARCH_HIPRI_INTERRUPT is not set + +# +# Boot options +# +# CONFIG_BOOT_RUNFROMEXTSRAM is not set +CONFIG_BOOT_RUNFROMFLASH=y +# CONFIG_BOOT_RUNFROMISRAM is not set +# CONFIG_BOOT_RUNFROMSDRAM is not set +# CONFIG_BOOT_COPYTORAM is not set + +# +# Boot Memory Configuration +# +CONFIG_RAM_START=0x20400000 +CONFIG_RAM_SIZE=393216 +# CONFIG_ARCH_HAVE_SDRAM is not set + +# +# Board Selection +# +CONFIG_ARCH_BOARD_XMC4500RELAX=y +# CONFIG_ARCH_BOARD_CUSTOM is not set +CONFIG_ARCH_BOARD="xmc4500-relax" + +# +# Common Board Options +# +CONFIG_ARCH_HAVE_LEDS=y +CONFIG_ARCH_LEDS=y +CONFIG_ARCH_HAVE_BUTTONS=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_HAVE_IRQBUTTONS=y +CONFIG_ARCH_IRQBUTTONS=y + +# +# Board-Specific Options +# +# CONFIG_BOARD_CRASHDUMP is not set +CONFIG_LIB_BOARDCTL=y +# CONFIG_BOARDCTL_RESET is not set +# CONFIG_BOARDCTL_UNIQUEID is not set +# CONFIG_BOARDCTL_TSCTEST is not set +# CONFIG_BOARDCTL_GRAPHICS is not set +# CONFIG_BOARDCTL_IOCTL is not set + +# +# RTOS Features +# +CONFIG_DISABLE_OS_API=y +# CONFIG_DISABLE_POSIX_TIMERS is not set +# CONFIG_DISABLE_PTHREAD is not set +# CONFIG_DISABLE_SIGNALS is not set +# CONFIG_DISABLE_MQUEUE is not set +# CONFIG_DISABLE_ENVIRON is not set + +# +# Clocks and Timers +# +CONFIG_USEC_PER_TICK=10000 +# CONFIG_SYSTEM_TIME64 is not set +# CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set +# CONFIG_JULIAN_TIME is not set +CONFIG_START_YEAR=2014 +CONFIG_START_MONTH=3 +CONFIG_START_DAY=10 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_PREALLOC_WDOGS=32 +CONFIG_WDOG_INTRESERVE=4 +CONFIG_PREALLOC_TIMERS=4 + +# +# Tasks and Scheduling +# +# CONFIG_SPINLOCK is not set +# CONFIG_INIT_NONE is not set +CONFIG_INIT_ENTRYPOINT=y +# CONFIG_INIT_FILEPATH is not set +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_RR_INTERVAL=200 +# CONFIG_SCHED_SPORADIC is not set +CONFIG_TASK_NAME_SIZE=31 +CONFIG_MAX_TASKS=16 +# CONFIG_SCHED_HAVE_PARENT is not set +CONFIG_SCHED_WAITPID=y + +# +# Pthread Options +# +# CONFIG_MUTEX_TYPES is not set +CONFIG_NPTHREAD_KEYS=4 +# CONFIG_PTHREAD_CLEANUP is not set +# CONFIG_CANCELLATION_POINTS is not set + +# +# Performance Monitoring +# +# CONFIG_SCHED_CPULOAD is not set +# CONFIG_SCHED_INSTRUMENTATION is not set + +# +# Files and I/O +# +CONFIG_DEV_CONSOLE=y +# CONFIG_FDCLONE_DISABLE is not set +# CONFIG_FDCLONE_STDIO is not set +CONFIG_SDCLONE_DISABLE=y +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NAME_MAX=32 +# CONFIG_PRIORITY_INHERITANCE is not set + +# +# RTOS hooks +# +# CONFIG_BOARD_INITIALIZE is not set +# CONFIG_SCHED_STARTHOOK is not set +# CONFIG_SCHED_ATEXIT is not set +# CONFIG_SCHED_ONEXIT is not set +# CONFIG_SIG_EVTHREAD is not set + +# +# Signal Numbers +# +CONFIG_SIG_SIGUSR1=1 +CONFIG_SIG_SIGUSR2=2 +CONFIG_SIG_SIGALARM=3 +CONFIG_SIG_SIGCONDTIMEDOUT=16 +CONFIG_SIG_SIGWORK=17 + +# +# POSIX Message Queue Options +# +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_MQ_MAXMSGSIZE=32 +# CONFIG_MODULE is not set + +# +# Work queue support +# +CONFIG_SCHED_WORKQUEUE=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=224 +CONFIG_SCHED_HPWORKPERIOD=50000 +CONFIG_SCHED_HPWORKSTACKSIZE=2048 +# CONFIG_SCHED_LPWORK is not set + +# +# Stack and heap information +# +CONFIG_IDLETHREAD_STACKSIZE=1024 +CONFIG_USERMAIN_STACKSIZE=2048 +CONFIG_PTHREAD_STACK_MIN=256 +CONFIG_PTHREAD_STACK_DEFAULT=2048 +# CONFIG_LIB_SYSCALL is not set + +# +# Device Drivers +# +CONFIG_DISABLE_POLL=y +CONFIG_DEV_NULL=y +# CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set +# CONFIG_DEV_LOOP is not set + +# +# Buffering +# +# CONFIG_DRVR_WRITEBUFFER is not set +# CONFIG_DRVR_READAHEAD is not set +# CONFIG_RAMDISK is not set +# CONFIG_CAN is not set +# CONFIG_ARCH_HAVE_PWM_PULSECOUNT is not set +# CONFIG_ARCH_HAVE_PWM_MULTICHAN is not set +# CONFIG_PWM is not set +CONFIG_ARCH_HAVE_I2CRESET=y +CONFIG_I2C=y +# CONFIG_I2C_SLAVE is not set +# CONFIG_I2C_POLLED is not set +CONFIG_I2C_RESET=y +# CONFIG_I2C_TRACE is not set +CONFIG_I2C_DRIVER=y +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set +CONFIG_SPI=y +# CONFIG_SPI_SLAVE is not set +CONFIG_SPI_EXCHANGE=y +# CONFIG_SPI_CMDDATA is not set +# CONFIG_SPI_CALLBACK is not set +# CONFIG_SPI_HWFEATURES is not set +# CONFIG_SPI_CS_DELAY_CONTROL is not set +# CONFIG_SPI_DRIVER is not set +# CONFIG_SPI_BITBANG is not set +# CONFIG_I2S is not set + +# +# Timer Driver Support +# +# CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set +# CONFIG_RTC is not set +# CONFIG_WATCHDOG is not set +# CONFIG_TIMERS_CS2100CP is not set +# CONFIG_ANALOG is not set +# CONFIG_AUDIO_DEVICES is not set +# CONFIG_VIDEO_DEVICES is not set +# CONFIG_BCH is not set +# CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# +# CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set + +# +# LCD Driver Support +# +# CONFIG_LCD is not set +# CONFIG_SLCD is not set + +# +# LED Support +# +# CONFIG_USERLED is not set +# CONFIG_RGBLED is not set +# CONFIG_PCA9635PW is not set +# CONFIG_NCP5623C is not set +CONFIG_MMCSD=y +CONFIG_MMCSD_NSLOTS=1 +# CONFIG_MMCSD_READONLY is not set +CONFIG_MMCSD_MULTIBLOCK_DISABLE=y +# CONFIG_MMCSD_MMCSUPPORT is not set +CONFIG_MMCSD_HAVECARDDETECT=y +# CONFIG_MMCSD_SPI is not set +# CONFIG_ARCH_HAVE_SDIO is not set +# CONFIG_SDIO_DMA is not set +# CONFIG_ARCH_HAVE_SDIOWAIT_WRCOMPLETE is not set +# CONFIG_MODEM is not set +CONFIG_MTD=y + +# +# MTD Configuration +# +# CONFIG_MTD_PARTITION is not set +# CONFIG_MTD_SECT512 is not set +# CONFIG_MTD_BYTE_WRITE is not set +# CONFIG_MTD_PROGMEM is not set +CONFIG_MTD_CONFIG=y +# CONFIG_MTD_CONFIG_RAM_CONSOLIDATE is not set +CONFIG_MTD_CONFIG_ERASEDVALUE=0xff + +# +# MTD Device Drivers +# +# CONFIG_MTD_NAND is not set +# CONFIG_RAMMTD is not set +# CONFIG_FILEMTD is not set +CONFIG_MTD_AT24XX=y +# CONFIG_AT24XX_MULTI is not set +CONFIG_AT24XX_SIZE=2 +CONFIG_AT24XX_ADDR=0x57 +CONFIG_AT24XX_EXTENDED=y +CONFIG_AT24XX_EXTSIZE=160 +CONFIG_AT24XX_FREQUENCY=100000 +CONFIG_MTD_AT25=y +CONFIG_AT25_SPIMODE=0 +CONFIG_AT25_SPIFREQUENCY=20000000 +# CONFIG_MTD_AT45DB is not set +# CONFIG_MTD_IS25XP is not set +# CONFIG_MTD_M25P is not set +# CONFIG_MTD_MX25L is not set +# CONFIG_MTD_S25FL1 is not set +# CONFIG_MTD_N25QXXX is not set +# CONFIG_MTD_SMART is not set +# CONFIG_MTD_RAMTRON is not set +# CONFIG_MTD_SST25 is not set +# CONFIG_MTD_SST25XX is not set +# CONFIG_MTD_SST26 is not set +# CONFIG_MTD_SST39FV is not set +# CONFIG_MTD_W25 is not set +# CONFIG_EEPROM is not set +# CONFIG_PIPES is not set +# CONFIG_PM is not set +# CONFIG_POWER is not set +# CONFIG_SENSORS is not set +CONFIG_SERIAL=y +# CONFIG_DEV_LOWCONSOLE is not set +# CONFIG_SERIAL_REMOVABLE is not set +CONFIG_SERIAL_CONSOLE=y +# CONFIG_16550_UART is not set +# CONFIG_UART_SERIALDRIVER is not set +CONFIG_UART0_SERIALDRIVER=y +# CONFIG_UART1_SERIALDRIVER is not set +# CONFIG_UART2_SERIALDRIVER is not set +# CONFIG_UART3_SERIALDRIVER is not set +# CONFIG_UART4_SERIALDRIVER is not set +# CONFIG_UART5_SERIALDRIVER is not set +# CONFIG_UART6_SERIALDRIVER is not set +# CONFIG_UART7_SERIALDRIVER is not set +# CONFIG_UART8_SERIALDRIVER is not set +# CONFIG_SCI0_SERIALDRIVER is not set +# CONFIG_SCI1_SERIALDRIVER is not set +# CONFIG_USART0_SERIALDRIVER is not set +# CONFIG_USART1_SERIALDRIVER is not set +# CONFIG_USART2_SERIALDRIVER is not set +# CONFIG_USART3_SERIALDRIVER is not set +# CONFIG_USART4_SERIALDRIVER is not set +# CONFIG_USART5_SERIALDRIVER is not set +# CONFIG_USART6_SERIALDRIVER is not set +# CONFIG_USART7_SERIALDRIVER is not set +# CONFIG_USART8_SERIALDRIVER is not set +# CONFIG_OTHER_UART_SERIALDRIVER is not set +CONFIG_MCU_SERIAL=y +CONFIG_STANDARD_SERIAL=y +# CONFIG_SERIAL_IFLOWCONTROL is not set +# CONFIG_SERIAL_OFLOWCONTROL is not set +# CONFIG_SERIAL_DMA is not set +# CONFIG_ARCH_HAVE_SERIAL_TERMIOS is not set +CONFIG_UART0_SERIAL_CONSOLE=y +# CONFIG_OTHER_SERIAL_CONSOLE is not set +# CONFIG_NO_SERIAL_CONSOLE is not set + +# +# UART0 Configuration +# +CONFIG_UART0_RXBUFSIZE=256 +CONFIG_UART0_TXBUFSIZE=256 +CONFIG_UART0_BAUD=115200 +CONFIG_UART0_BITS=8 +CONFIG_UART0_PARITY=0 +CONFIG_UART0_2STOP=0 +# CONFIG_UART0_IFLOWCONTROL is not set +# CONFIG_UART0_OFLOWCONTROL is not set +# CONFIG_UART0_DMA is not set +# CONFIG_PSEUDOTERM is not set +# CONFIG_USBDEV is not set +# CONFIG_USBHOST is not set +# CONFIG_HAVE_USBTRACE is not set +# CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set + +# +# System Logging +# +# CONFIG_ARCH_SYSLOG is not set +# CONFIG_RAMLOG is not set +# CONFIG_SYSLOG_INTBUFFER is not set +# CONFIG_SYSLOG_TIMESTAMP is not set +CONFIG_SYSLOG_SERIAL_CONSOLE=y +# CONFIG_SYSLOG_CHAR is not set +CONFIG_SYSLOG_CONSOLE=y +# CONFIG_SYSLOG_NONE is not set +# CONFIG_SYSLOG_FILE is not set +# CONFIG_SYSLOG_CHARDEV is not set + +# +# Networking Support +# +# CONFIG_ARCH_HAVE_NET is not set +# CONFIG_ARCH_HAVE_PHY is not set +# CONFIG_NET is not set + +# +# Crypto API +# +# CONFIG_CRYPTO is not set + +# +# File Systems +# + +# +# File system configuration +# +# CONFIG_DISABLE_MOUNTPOINT is not set +# CONFIG_FS_AUTOMOUNTER is not set +# CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set +# CONFIG_PSEUDOFS_SOFTLINKS is not set +CONFIG_FS_READABLE=y +CONFIG_FS_WRITABLE=y +# CONFIG_FS_NAMED_SEMAPHORES is not set +CONFIG_FS_MQUEUE_MPATH="/var/mqueue" +# CONFIG_FS_RAMMAP is not set +CONFIG_FS_FAT=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FAT_MAXFNAME=32 +# CONFIG_FS_FATTIME is not set +# CONFIG_FAT_FORCE_INDIRECT is not set +# CONFIG_FAT_DMAMEMORY is not set +# CONFIG_FAT_DIRECT_RETRY is not set +# CONFIG_FS_NXFFS is not set +# CONFIG_FS_ROMFS is not set +# CONFIG_FS_TMPFS is not set +# CONFIG_FS_SMARTFS is not set +# CONFIG_FS_BINFS is not set +CONFIG_FS_PROCFS=y +# CONFIG_FS_PROCFS_REGISTER is not set + +# +# Exclude individual procfs entries +# +# CONFIG_FS_PROCFS_EXCLUDE_PROCESS is not set +# CONFIG_FS_PROCFS_EXCLUDE_UPTIME is not set +# CONFIG_FS_PROCFS_EXCLUDE_MOUNTS is not set +# CONFIG_FS_PROCFS_EXCLUDE_MTD is not set +# CONFIG_FS_UNIONFS is not set + +# +# Graphics Support +# +# CONFIG_NX is not set + +# +# Memory Management +# +# CONFIG_MM_SMALL is not set +CONFIG_MM_REGIONS=1 +# CONFIG_ARCH_HAVE_HEAP2 is not set +# CONFIG_GRAN is not set + +# +# Audio Support +# +# CONFIG_AUDIO is not set + +# +# Wireless Support +# + +# +# Binary Loader +# +# CONFIG_BINFMT_DISABLE is not set +# CONFIG_BINFMT_EXEPATH is not set +# CONFIG_NXFLAT is not set +# CONFIG_ELF is not set +CONFIG_BUILTIN=y +# CONFIG_PIC is not set +# CONFIG_SYMTAB_ORDEREDBYNAME is not set + +# +# Library Routines +# + +# +# Standard C Library Options +# + +# +# Standard C I/O +# +# CONFIG_STDIO_DISABLE_BUFFERING is not set +CONFIG_STDIO_BUFFER_SIZE=64 +CONFIG_STDIO_LINEBUFFER=y +CONFIG_NUNGET_CHARS=2 +# CONFIG_NOPRINTF_FIELDWIDTH is not set +# CONFIG_LIBC_FLOATINGPOINT is not set +CONFIG_LIBC_LONG_LONG=y +# CONFIG_LIBC_SCANSET is not set +# CONFIG_EOL_IS_CR is not set +# CONFIG_EOL_IS_LF is not set +# CONFIG_EOL_IS_BOTH_CRLF is not set +CONFIG_EOL_IS_EITHER_CRLF=y +# CONFIG_MEMCPY_VIK is not set +# CONFIG_LIBM is not set + +# +# Architecture-Specific Support +# +CONFIG_ARCH_LOWPUTC=y +# CONFIG_ARCH_ROMGETC is not set +# CONFIG_LIBC_ARCH_MEMCPY is not set +# CONFIG_LIBC_ARCH_MEMCMP is not set +# CONFIG_LIBC_ARCH_MEMMOVE is not set +# CONFIG_LIBC_ARCH_MEMSET is not set +# CONFIG_LIBC_ARCH_STRCHR is not set +# CONFIG_LIBC_ARCH_STRCMP is not set +# CONFIG_LIBC_ARCH_STRCPY is not set +# CONFIG_LIBC_ARCH_STRNCPY is not set +# CONFIG_LIBC_ARCH_STRLEN is not set +# CONFIG_LIBC_ARCH_STRNLEN is not set +# CONFIG_LIBC_ARCH_ELF is not set +# CONFIG_ARMV7M_MEMCPY is not set + +# +# stdlib Options +# +CONFIG_LIB_RAND_ORDER=1 +CONFIG_LIB_HOMEDIR="/" +CONFIG_LIBC_TMPDIR="/tmp" +CONFIG_LIBC_MAX_TMPFILE=32 + +# +# Program Execution Options +# +# CONFIG_LIBC_EXECFUNCS is not set +CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=1024 +CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=2048 + +# +# errno Decode Support +# +# CONFIG_LIBC_STRERROR is not set +# CONFIG_LIBC_PERROR_STDOUT is not set + +# +# memcpy/memset Options +# +# CONFIG_MEMSET_OPTSPEED is not set +# CONFIG_LIBC_DLLFCN is not set +# CONFIG_LIBC_MODLIB is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set + +# +# Time/Time Zone Support +# +# CONFIG_LIBC_LOCALTIME is not set +# CONFIG_TIME_EXTENDED is not set +CONFIG_ARCH_HAVE_TLS=y + +# +# Thread Local Storage (TLS) +# +# CONFIG_TLS is not set + +# +# Network-Related Options +# +# CONFIG_LIBC_IPv4_ADDRCONV is not set +# CONFIG_LIBC_IPv6_ADDRCONV is not set +# CONFIG_LIBC_NETDB is not set + +# +# NETDB Support +# +# CONFIG_NETDB_HOSTFILE is not set +# CONFIG_LIBC_IOCTL_VARIADIC is not set +CONFIG_LIB_SENDFILE_BUFSIZE=512 + +# +# Non-standard Library Support +# +# CONFIG_LIB_CRC64_FAST is not set +# CONFIG_LIB_KBDCODEC is not set +# CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set + +# +# Basic CXX Support +# +# CONFIG_C99_BOOL8 is not set +# CONFIG_HAVE_CXX is not set + +# +# Application Configuration +# + +# +# Built-In Applications +# +CONFIG_BUILTIN_PROXY_STACKSIZE=1024 + +# +# CAN Utilities +# + +# +# Examples +# +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set +# CONFIG_EXAMPLES_CHAT is not set +# CONFIG_EXAMPLES_CONFIGDATA is not set +# CONFIG_EXAMPLES_DHCPD is not set +# CONFIG_EXAMPLES_ELF is not set +# CONFIG_EXAMPLES_FSTEST is not set +# CONFIG_EXAMPLES_FTPC is not set +# CONFIG_EXAMPLES_FTPD is not set +# CONFIG_EXAMPLES_HELLO is not set +# CONFIG_EXAMPLES_HIDKBD is not set +# CONFIG_EXAMPLES_IGMP is not set +# CONFIG_EXAMPLES_JSON is not set +# CONFIG_EXAMPLES_KEYPADTEST is not set +# CONFIG_EXAMPLES_MEDIA is not set +# CONFIG_EXAMPLES_MM is not set +# CONFIG_EXAMPLES_MODBUS is not set +# CONFIG_EXAMPLES_MOUNT is not set +CONFIG_EXAMPLES_NSH=y +# CONFIG_EXAMPLES_NULL is not set +# CONFIG_EXAMPLES_NX is not set +# CONFIG_EXAMPLES_NXFFS is not set +# CONFIG_EXAMPLES_NXHELLO is not set +# CONFIG_EXAMPLES_NXIMAGE is not set +# CONFIG_EXAMPLES_NXLINES is not set +# CONFIG_EXAMPLES_NXTERM is not set +# CONFIG_EXAMPLES_NXTEXT is not set +# CONFIG_EXAMPLES_OSTEST is not set +# CONFIG_EXAMPLES_PCA9635 is not set +# CONFIG_EXAMPLES_POSIXSPAWN is not set +# CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set +# CONFIG_EXAMPLES_RGBLED is not set +# CONFIG_EXAMPLES_SENDMAIL is not set +# CONFIG_EXAMPLES_SERIALBLASTER is not set +# CONFIG_EXAMPLES_SERIALRX is not set +# CONFIG_EXAMPLES_SERLOOP is not set +# CONFIG_EXAMPLES_SLCD is not set +# CONFIG_EXAMPLES_SMART is not set +# CONFIG_EXAMPLES_SMART_TEST is not set +# CONFIG_EXAMPLES_SMP is not set +# CONFIG_EXAMPLES_STAT is not set +# CONFIG_EXAMPLES_TCPECHO is not set +# CONFIG_EXAMPLES_TELNETD is not set +# CONFIG_EXAMPLES_TIFF is not set +# CONFIG_EXAMPLES_TOUCHSCREEN is not set +# CONFIG_EXAMPLES_USBSERIAL is not set +# CONFIG_EXAMPLES_WATCHDOG is not set +# CONFIG_EXAMPLES_WEBSERVER is not set + +# +# File System Utilities +# +# CONFIG_FSUTILS_FLASH_ERASEALL is not set +# CONFIG_FSUTILS_INIFILE is not set +# CONFIG_FSUTILS_PASSWD is not set + +# +# GPS Utilities +# +# CONFIG_GPSUTILS_MINMEA_LIB is not set + +# +# Graphics Support +# +# CONFIG_TIFF is not set +# CONFIG_GRAPHICS_TRAVELER is not set + +# +# Interpreters +# +# CONFIG_INTERPRETERS_BAS is not set +# CONFIG_INTERPRETERS_FICL is not set +# CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set +# CONFIG_INTERPRETERS_PCODE is not set + +# +# FreeModBus +# +# CONFIG_MODBUS is not set + +# +# Network Utilities +# +# CONFIG_NETUTILS_CODECS is not set +# CONFIG_NETUTILS_ESP8266 is not set +# CONFIG_NETUTILS_FTPC is not set +# CONFIG_NETUTILS_JSON is not set +# CONFIG_NETUTILS_SMTP is not set + +# +# NSH Library +# +CONFIG_NSH_LIBRARY=y +# CONFIG_NSH_MOTD is not set + +# +# Command Line Configuration +# +CONFIG_NSH_READLINE=y +# CONFIG_NSH_CLE is not set +CONFIG_NSH_LINELEN=64 +# CONFIG_NSH_DISABLE_SEMICOLON is not set +CONFIG_NSH_CMDPARMS=y +CONFIG_NSH_MAXARGUMENTS=6 +CONFIG_NSH_ARGCAT=y +CONFIG_NSH_NESTDEPTH=3 +# CONFIG_NSH_DISABLEBG is not set +CONFIG_NSH_BUILTIN_APPS=y + +# +# Disable Individual commands +# +# CONFIG_NSH_DISABLE_ADDROUTE is not set +# CONFIG_NSH_DISABLE_BASENAME is not set +# CONFIG_NSH_DISABLE_CAT is not set +# CONFIG_NSH_DISABLE_CD is not set +# CONFIG_NSH_DISABLE_CP is not set +# CONFIG_NSH_DISABLE_CMP is not set +CONFIG_NSH_DISABLE_DATE=y +# CONFIG_NSH_DISABLE_DD is not set +# CONFIG_NSH_DISABLE_DF is not set +# CONFIG_NSH_DISABLE_DELROUTE is not set +# CONFIG_NSH_DISABLE_DIRNAME is not set +# CONFIG_NSH_DISABLE_ECHO is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_FREE is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HELP is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_IFUPDOWN is not set +# CONFIG_NSH_DISABLE_KILL is not set +# CONFIG_NSH_DISABLE_LOSETUP is not set +CONFIG_NSH_DISABLE_LOSMART=y +# CONFIG_NSH_DISABLE_LS is not set +# CONFIG_NSH_DISABLE_MB is not set +# CONFIG_NSH_DISABLE_MKDIR is not set +# CONFIG_NSH_DISABLE_MKFATFS is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_MH is not set +# CONFIG_NSH_DISABLE_MOUNT is not set +# CONFIG_NSH_DISABLE_MV is not set +# CONFIG_NSH_DISABLE_MW is not set +CONFIG_NSH_DISABLE_PRINTF=y +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_PWD is not set +# CONFIG_NSH_DISABLE_RM is not set +# CONFIG_NSH_DISABLE_RMDIR is not set +# CONFIG_NSH_DISABLE_SET is not set +# CONFIG_NSH_DISABLE_SH is not set +# CONFIG_NSH_DISABLE_SLEEP is not set +# CONFIG_NSH_DISABLE_TIME is not set +# CONFIG_NSH_DISABLE_TEST is not set +# CONFIG_NSH_DISABLE_UMOUNT is not set +# CONFIG_NSH_DISABLE_UNAME is not set +# CONFIG_NSH_DISABLE_UNSET is not set +# CONFIG_NSH_DISABLE_USLEEP is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_MMCSDMINOR=0 +CONFIG_NSH_MMCSDSLOTNO=0 + +# +# Configure Command Options +# +# CONFIG_NSH_CMDOPT_DF_H is not set +# CONFIG_NSH_CMDOPT_DD_STATS is not set +CONFIG_NSH_CODECS_BUFSIZE=128 +CONFIG_NSH_CMDOPT_HEXDUMP=y +CONFIG_NSH_PROC_MOUNTPOINT="/proc" +CONFIG_NSH_FILEIOSIZE=512 + +# +# Scripting Support +# +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_ITEF is not set +# CONFIG_NSH_DISABLE_LOOPS is not set + +# +# Console Configuration +# +CONFIG_NSH_CONSOLE=y +# CONFIG_NSH_ALTCONDEV is not set +CONFIG_NSH_ARCHINIT=y +# CONFIG_NSH_LOGIN is not set +# CONFIG_NSH_CONSOLE_LOGIN is not set + +# +# NxWidgets/NxWM +# + +# +# Platform-specific Support +# +# CONFIG_PLATFORM_CONFIGDATA is not set + +# +# System Libraries and NSH Add-Ons +# +# CONFIG_SYSTEM_CLE is not set +# CONFIG_SYSTEM_CUTERM is not set +# CONFIG_SYSTEM_FLASH_ERASEALL is not set +# CONFIG_SYSTEM_FREE is not set +# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_SYSTEM_HEXED is not set +CONFIG_SYSTEM_I2CTOOL=y +CONFIG_I2CTOOL_MINBUS=0 +CONFIG_I2CTOOL_MAXBUS=0 +CONFIG_I2CTOOL_MINADDR=0x03 +CONFIG_I2CTOOL_MAXADDR=0x77 +CONFIG_I2CTOOL_MAXREGADDR=0xff +CONFIG_I2CTOOL_DEFFREQ=400000 +# CONFIG_SYSTEM_INSTALL is not set +CONFIG_SYSTEM_RAMTEST=y +CONFIG_READLINE_HAVE_EXTMATCH=y +CONFIG_SYSTEM_READLINE=y +CONFIG_READLINE_ECHO=y +# CONFIG_READLINE_TABCOMPLETION is not set +# CONFIG_READLINE_CMD_HISTORY is not set +# CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set +# CONFIG_SYSTEM_UBLOXMODEM is not set +# CONFIG_SYSTEM_VI is not set +# CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/xmc4500-relax/nsh/setenv.sh b/configs/xmc4500-relax/nsh/setenv.sh new file mode 100644 index 00000000000..2116ba35be3 --- /dev/null +++ b/configs/xmc4500-relax/nsh/setenv.sh @@ -0,0 +1,77 @@ +#!/bin/bash +# configs/xmc4500-relax/nsh/Make.defs +# +# Copyright (C) 2017 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +if [ "$_" = "$0" ] ; then + echo "You must source this script, not run it!" 1>&2 + exit 1 +fi + +WD=`pwd` +if [ ! -x "setenv.sh" ]; then + echo "This script must be executed from the top-level NuttX build directory" + exit 1 +fi + +if [ -z "${PATH_ORIG}" ]; then + export PATH_ORIG="${PATH}" +fi + +# This is the Cygwin path to the location where I installed the Atmel GCC +# toolchain under Windows. You will also have to edit this if you install +# this toolchain in any other location +#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/Atmel/Atmel Toolchain/ARM GCC/Native/4.7.3.99/arm-gnu-toolchain/bin" + +# This is the Cygwin path to the location where I installed the CodeSourcery +# toolchain under windows. You will also have to edit this if you install +# the CodeSourcery toolchain in any other location +#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin" +#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery_CodeBench_Lite_for_ARM_EABI/bin" +# export TOOLCHAIN_BIN="/cygdrive/c/Users/MyName/MentorGraphics/Sourcery_CodeBench_Lite_for_ARM_EABI/bin" + +# This is the location where I installed the ARM "GNU Tools for ARM Embedded Processors" +# You can this free toolchain here https://launchpad.net/gcc-arm-embedded +export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/GNU Tools ARM Embedded/4.9 2015q2/bin" + +# This is the path to the location where I installed the devkitARM toolchain +# You can get this free toolchain from http://devkitpro.org/ or http://sourceforge.net/projects/devkitpro/ +#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/devkitARM/bin" + +# This is the Cygwin path to the location where I build the buildroot +# toolchain. +# export TOOLCHAIN_BIN="${WD}/../buildroot/build_arm_nofpu/staging_dir/bin" + +# Add the path to the toolchain to the PATH varialble +export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}" + +echo "PATH : ${PATH}" diff --git a/configs/xmc4500-relax/src/Makefile b/configs/xmc4500-relax/src/Makefile new file mode 100644 index 00000000000..d609e49ac8e --- /dev/null +++ b/configs/xmc4500-relax/src/Makefile @@ -0,0 +1,55 @@ +############################################################################ +# configs/xmc4500-relax/src/Makefile +# +# Copyright (C) 2017 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +-include $(TOPDIR)/Make.defs + +ASRCS = +CSRCS = xmc4_boot.c xmc4_bringup.c + +ifeq ($(CONFIG_BUTTONS),y) +CSRCS += xmc4_buttons.c +endif + +ifeq ($(CONFIG_USERLED),y) +CSRCS += xmc4_autoleds.c +else +CSRCS += xmc4_userleds.c +endif + +ifeq ($(CONFIG_LIB_BOARDCTL),y) +CSRCS += xmc4_appinit.c +endif + +include $(TOPDIR)/configs/Board.mk diff --git a/configs/xmc4500-relax/src/xmc4500-relax.h b/configs/xmc4500-relax/src/xmc4500-relax.h new file mode 100644 index 00000000000..6a004c82448 --- /dev/null +++ b/configs/xmc4500-relax/src/xmc4500-relax.h @@ -0,0 +1,78 @@ +/**************************************************************************** + * configs/xmc4500-relax/src/xmc4500-relax.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __CONFIGS_XMC4500_RELAX_SRC_XMC4500_RELAX_H +#define __CONFIGS_XMC4500_RELAX_SRC_XMC4500_RELAX_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* LEDs */ + +/* BUTTONS */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: xmc4_bringup + * + * Description: + * Bring up board features + * + ****************************************************************************/ + +int xmc4_bringup(void); + +#endif /* __ASSEMBLY__ */ +#endif /* __CONFIGS_XMC4500_RELAX_SRC_XMC4500_RELAX_H */ diff --git a/configs/xmc4500-relax/src/xmc4_appinit.c b/configs/xmc4500-relax/src/xmc4_appinit.c new file mode 100644 index 00000000000..8e1fa87efe0 --- /dev/null +++ b/configs/xmc4500-relax/src/xmc4_appinit.c @@ -0,0 +1,80 @@ +/**************************************************************************** + * config/xmc4500-relax/src/xmc4_appinit.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_app_initialize + * + * Description: + * Perform application specific initialization. This function is never + * called directly from application code, but only indirectly via the + * (non-standard) boardctl() interface using the command BOARDIOC_INIT. + * + * Input Parameters: + * arg - The boardctl() argument is passed to the board_app_initialize() + * implementation without modification. The argument has no + * meaning to NuttX; the meaning of the argument is a contract + * between the board-specific initalization logic and the the + * matching application logic. The value cold be such things as a + * mode enumeration value, a set of DIP switch switch settings, a + * pointer to configuration data read from a file or serial FLASH, + * or whatever you would like to do with it. Every implementation + * should accept zero/NULL as a default configuration. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure to indicate the nature of the failure. + * + ****************************************************************************/ + +int board_app_initialize(uintptr_t arg) +{ +#ifndef CONFIG_BOARD_INITIALIZE + /* Perform board initialization */ + + return xmc4_bringup(); +#else + return OK; +#endif /* CONFIG_BOARD_INITIALIZE */ +} diff --git a/configs/xmc4500-relax/src/xmc4_autoleds.c b/configs/xmc4500-relax/src/xmc4_autoleds.c new file mode 100644 index 00000000000..7fd88f7866b --- /dev/null +++ b/configs/xmc4500-relax/src/xmc4_autoleds.c @@ -0,0 +1,80 @@ +/**************************************************************************** + * configs/xmc4500-relax/include/xmc4_autoleds.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "xmc4500-relax.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ +#warning Missing logic +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ +#warning Missing logic +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ +#warning Missing logic +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/configs/xmc4500-relax/src/xmc4_boot.c b/configs/xmc4500-relax/src/xmc4_boot.c new file mode 100644 index 00000000000..994cdf86c6a --- /dev/null +++ b/configs/xmc4500-relax/src/xmc4_boot.c @@ -0,0 +1,91 @@ +/************************************************************************************ + * configs/xmc4500-relax/src/xmc4_boot.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include +#include + +#include "xmc4500-relax.h" + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: xmc4_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This entry point + * is called early in the initialization -- after all memory has been configured + * and mapped but before any devices have been initialized. + * + ************************************************************************************/ + +void xmc4_boardinitialize(void) +{ +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_initialize + * + * Description: + * If CONFIG_BOARD_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_initialize(). board_initialize() will be + * called immediately after up_intitialize() is called and just before the + * initial application is started. This additional initialization phase + * may be used, for example, to initialize board-specific device drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_INITIALIZE +void board_initialize(void) +{ + /* Perform board initialization */ + + (void)xmc4_bringup(); +} +#endif /* CONFIG_BOARD_INITIALIZE */ + diff --git a/configs/xmc4500-relax/src/xmc4_bringup.c b/configs/xmc4500-relax/src/xmc4_bringup.c new file mode 100644 index 00000000000..ae7b5a593eb --- /dev/null +++ b/configs/xmc4500-relax/src/xmc4_bringup.c @@ -0,0 +1,65 @@ +/**************************************************************************** + * config/samv71-xult/src/xmc4_bringup.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: xmc4_bringup + * + * Description: + * Bring up board features + * + ****************************************************************************/ + +int xmc4_bringup(void) +{ + return OK; +} diff --git a/configs/xmc4500-relax/src/xmc4_buttons.c b/configs/xmc4500-relax/src/xmc4_buttons.c new file mode 100644 index 00000000000..24f9e05a206 --- /dev/null +++ b/configs/xmc4500-relax/src/xmc4_buttons.c @@ -0,0 +1,78 @@ +/**************************************************************************** + * configs/xmc4500-relax/src/xmc4_buttons.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include "xmc4500-relax.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + ****************************************************************************/ + +void board_button_initialize(void) +{ +#warning Missing logic +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint8_t board_buttons(void) +{ +#warning Missing logic + return 0; +} + +/**************************************************************************** + * Name: board_button_irq + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) +{ +#warning Missing logic + return -ENOSYS; +} +#endif /* CONFIG_ARCH_IRQBUTTONS */ diff --git a/configs/xmc4500-relax/src/xmc4_userleds.c b/configs/xmc4500-relax/src/xmc4_userleds.c new file mode 100644 index 00000000000..8bb69336f7e --- /dev/null +++ b/configs/xmc4500-relax/src/xmc4_userleds.c @@ -0,0 +1,75 @@ +/**************************************************************************** + * configs/xmc4500-relax/src/xmc4_userleds.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include +#include "xmc4500-relax.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +void board_userled_initialize(void) +{ +#warning Missing logic +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ +#warning Missing logic +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint8_t ledset) +{ +#warning Missing logic +} From 5693f26a5ed42d2120fa2adb222c38696965dc36 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 16 Mar 2017 11:30:02 -0600 Subject: [PATCH 12/81] XMC4xx: Fix several early compilation problems. --- arch/arm/include/xmc4/chip.h | 4 +- arch/arm/include/xmc4/irq.h | 38 ++-- arch/arm/include/xmc4/xmc4500_irq.h | 236 +++++++++++----------- arch/arm/src/xmc4/chip/xmc4_scu.h | 14 +- arch/arm/src/xmc4/xmc4_clockconfig.c | 50 ++--- arch/arm/src/xmc4/xmc4_irq.c | 1 + configs/xmc4500-relax/include/board.h | 62 ++++++ configs/xmc4500-relax/src/xmc4500-relax.h | 16 +- 8 files changed, 248 insertions(+), 173 deletions(-) diff --git a/arch/arm/include/xmc4/chip.h b/arch/arm/include/xmc4/chip.h index 7ea5157a736..019c1078230 100644 --- a/arch/arm/include/xmc4/chip.h +++ b/arch/arm/include/xmc4/chip.h @@ -48,11 +48,11 @@ /* Get customizations for each supported chip */ -#if defined(CONFIG_ARCH_XMC4500) +#if defined(CONFIG_ARCH_CHIP_XMC4500) # define XM4_NUSIC 3 /* Three USIC modules: USCI0-2 */ #else -# error "Unsupported XMC4000 chip" +# error "Unsupported XMC4xxx chip" #endif /* NVIC priority levels *************************************************************/ diff --git a/arch/arm/include/xmc4/irq.h b/arch/arm/include/xmc4/irq.h index 65300dcee3b..10fc176a43c 100644 --- a/arch/arm/include/xmc4/irq.h +++ b/arch/arm/include/xmc4/irq.h @@ -37,8 +37,8 @@ * through nuttx/irq.h */ -#ifndef __ARCH_ARM_INCLUDE_XM4_IRQ_H -#define __ARCH_ARM_INCLUDE_XM4_IRQ_H +#ifndef __ARCH_ARM_INCLUDE_XMC4_IRQ_H +#define __ARCH_ARM_INCLUDE_XMC4_IRQ_H /************************************************************************************ * Included Files @@ -58,26 +58,26 @@ /* Processor Exceptions (vectors 0-15) */ -#define XM4_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ - /* Vector 0: Reset stack pointer value */ - /* Vector 1: Reset (not handler as an IRQ) */ -#define XM4_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ -#define XM4_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ -#define XM4_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ -#define XM4_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ -#define XM4_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ - /* Vectors 7-10: Reserved */ -#define XM4_IRQ_SVCALL (11) /* Vector 11: SVC call */ -#define XM4_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */ - /* Vector 13: Reserved */ -#define XM4_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ -#define XM4_IRQ_SYSTICK (15) /* Vector 15: System tick */ +#define XMC4_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ + /* Vector 0: Reset stack pointer value */ + /* Vector 1: Reset (not handler as an IRQ) */ +#define XMC4_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ +#define XMC4_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ +#define XMC4_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ +#define XMC4_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ +#define XMC4_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ + /* Vectors 7-10: Reserved */ +#define XMC4_IRQ_SVCALL (11) /* Vector 11: SVC call */ +#define XMC4_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */ + /* Vector 13: Reserved */ +#define XMC4_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ +#define XMC4_IRQ_SYSTICK (15) /* Vector 15: System tick */ /* External interrupts (vectors >= 16). These definitions are chip-specific */ -#define XM4_IRQ_FIRST (16) /* Vector number of the first external interrupt */ +#define XMC4_IRQ_FIRST (16) /* Vector number of the first external interrupt */ -#if defined(CONFIG_ARCH_XMC4500) +#if defined(CONFIG_ARCH_CHIP_XMC4500) # include #else /* The interrupt vectors for other parts are defined in other documents and may or @@ -116,5 +116,5 @@ extern "C" #endif #endif -#endif /* __ARCH_ARM_INCLUDE_XM4_IRQ_H */ +#endif /* __ARCH_ARM_INCLUDE_XMC4_IRQ_H */ diff --git a/arch/arm/include/xmc4/xmc4500_irq.h b/arch/arm/include/xmc4/xmc4500_irq.h index 1005adeb495..dfd21d6c21d 100644 --- a/arch/arm/include/xmc4/xmc4500_irq.h +++ b/arch/arm/include/xmc4/xmc4500_irq.h @@ -37,8 +37,8 @@ * through nuttx/irq.h */ -#ifndef xmc4__ARCH_ARM_INCLUDE_XM4_XM4500_IRQ_H -#define xmc4__ARCH_ARM_INCLUDE_XM4_XM4500_IRQ_H +#ifndef xmc4__ARCH_ARM_INCLUDE_XMC4_XM4500_IRQ_H +#define xmc4__ARCH_ARM_INCLUDE_XMC4_XM4500_IRQ_H /***************************************************************************** * Included Files @@ -75,125 +75,125 @@ * USCI - Universal Serial Interface */ -#define XM4_IRQ_SCU (XM4_IRQ_FIRST+0) /* 0: System Control */ -#define XM4_IRQ_ERU0_SR0 (XM4_IRQ_FIRST+1) /* 1: ERU0, SR0 */ -#define XM4_IRQ_ERU0_SR1 (XM4_IRQ_FIRST+2) /* 2: ERU0, SR1 */ -#define XM4_IRQ_ERU0_SR2 (XM4_IRQ_FIRST+3) /* 3: ERU0, SR2 */ -#define XM4_IRQ_ERU0_SR3 (XM4_IRQ_FIRST+4) /* 4: ERU0, SR3 */ -#define XM4_IRQ_ERU1_SR0 (XM4_IRQ_FIRST+5) /* 5: ERU1, SR0 */ -#define XM4_IRQ_ERU1_SR1 (XM4_IRQ_FIRST+6) /* 6: ERU1, SR1 */ -#define XM4_IRQ_ERU1_SR2 (XM4_IRQ_FIRST+7) /* 7: ERU1, SR2 */ -#define XM4_IRQ_ERU1_SR3 (XM4_IRQ_FIRST+8) /* 8: ERU1, SR3 */ -#define XM4_IRQ_RESVD009 (XM4_IRQ_FIRST+9) /* 9: Reserved */ -#define XM4_IRQ_RESVD010 (XM4_IRQ_FIRST+10) /* 10: Reserved */ -#define XM4_IRQ_RESVD011 (XM4_IRQ_FIRST+11) /* 11: Reserved */ -#define XM4_IRQ_PMU1_SR0 (XM4_IRQ_FIRST+12) /* 12: PMU, SR0 */ -#define XM4_IRQ_RESVD011 (XM4_IRQ_FIRST+13) /* 13: Reserved */ -#define XM4_IRQ_VADC_COSR0 (XM4_IRQ_FIRST+14) /* 14: ADC Common Block 0 */ -#define XM4_IRQ_VADC_COSR1 (XM4_IRQ_FIRST+15) /* 15: ADC Common Block 1 */ -#define XM4_IRQ_VADC_COSR2 (XM4_IRQ_FIRST+16) /* 16: ADC Common Block 2 */ -#define XM4_IRQ_VADC_COSR3 (XM4_IRQ_FIRST+17) /* 17: ADC Common Block 3 */ -#define XM4_IRQ_VADC_GOSR0 (XM4_IRQ_FIRST+18) /* 18: ADC Group 0, SR0 */ -#define XM4_IRQ_VADC_GOSR1 (XM4_IRQ_FIRST+19) /* 19: ADC Group 0, SR1 */ -#define XM4_IRQ_VADC_GOSR2 (XM4_IRQ_FIRST+20) /* 20: ADC Group 0, SR2 */ -#define XM4_IRQ_VADC_GOSR3 (XM4_IRQ_FIRST+21) /* 21: ADC Group 0, SR3 */ -#define XM4_IRQ_VADC_G1SR0 (XM4_IRQ_FIRST+22) /* 22: ADC Group 1, SR0 */ -#define XM4_IRQ_VADC_G1SR1 (XM4_IRQ_FIRST+23) /* 23: ADC Group 1, SR1 */ -#define XM4_IRQ_VADC_G1SR2 (XM4_IRQ_FIRST+24) /* 24: ADC Group 1, SR2 */ -#define XM4_IRQ_VADC_G1SR3 (XM4_IRQ_FIRST+25) /* 25: ADC Group 1, SR3 */ -#define XM4_IRQ_VADC_G2SR0 (XM4_IRQ_FIRST+26) /* 26: ADC Group 2, SR0 */ -#define XM4_IRQ_VADC_G2SR1 (XM4_IRQ_FIRST+27) /* 27: ADC Group 2, SR1 */ -#define XM4_IRQ_VADC_G2SR2 (XM4_IRQ_FIRST+28) /* 28: ADC Group 2, SR2 */ -#define XM4_IRQ_VADC_G2SR3 (XM4_IRQ_FIRST+29) /* 29: ADC Group 2, SR3 */ -#define XM4_IRQ_VADC_G3SR0 (XM4_IRQ_FIRST+30) /* 30: ADC Group 3, SR0 */ -#define XM4_IRQ_VADC_G3SR1 (XM4_IRQ_FIRST+31) /* 31: ADC Group 3, SR1 */ -#define XM4_IRQ_VADC_G3SR2 (XM4_IRQ_FIRST+32) /* 32: ADC Group 3, SR2 */ -#define XM4_IRQ_VADC_G3SR3 (XM4_IRQ_FIRST+33) /* 33: ADC Group 3, SR3 */ -#define XM4_IRQ_DSD_SRM0 (XM4_IRQ_FIRST+34) /* 34: DSD Main, SRM0 */ -#define XM4_IRQ_DSD_SRM1 (XM4_IRQ_FIRST+35) /* 35: DSD Main, SRM1 */ -#define XM4_IRQ_DSD_SRM2 (XM4_IRQ_FIRST+36) /* 36: DSD Main, SRM2 */ -#define XM4_IRQ_DSD_SRM3 (XM4_IRQ_FIRST+37) /* 37: DSD Main, SRM3 */ -#define XM4_IRQ_DSD_SRA0 (XM4_IRQ_FIRST+38) /* 38: DSD Auxiliary, SRA0 */ -#define XM4_IRQ_DSD_SRA1 (XM4_IRQ_FIRST+39) /* 39: DSD Auxiliary, SRA1 */ -#define XM4_IRQ_DSD_SRA2 (XM4_IRQ_FIRST+40) /* 40: DSD Auxiliary, SRA2 */ -#define XM4_IRQ_DSD_SRA3 (XM4_IRQ_FIRST+41) /* 41: DSD Auxiliary, SRA3 */ -#define XM4_IRQ_DAC_SR0 (XM4_IRQ_FIRST+42) /* 42: DAC, SR0 */ -#define XM4_IRQ_DAC_SR1 (XM4_IRQ_FIRST+43) /* 43: DAC, SR1 */ -#define XM4_IRQ_CCU40_SR0 (XM4_IRQ_FIRST+44) /* 44: CCU4 Module 0, SR0 */ -#define XM4_IRQ_CCU40_SR1 (XM4_IRQ_FIRST+45) /* 45: CCU4 Module 0, SR1 */ -#define XM4_IRQ_CCU40_SR2 (XM4_IRQ_FIRST+46) /* 46: CCU4 Module 0, SR2 */ -#define XM4_IRQ_CCU40_SR3 (XM4_IRQ_FIRST+47) /* 47: CCU4 Module 0, SR3 */ -#define XM4_IRQ_CCU41_SR0 (XM4_IRQ_FIRST+48) /* 48: CCU4 Module 1, SR0 */ -#define XM4_IRQ_CCU41_SR1 (XM4_IRQ_FIRST+49) /* 49: CCU4 Module 1, SR1 */ -#define XM4_IRQ_CCU41_SR2 (XM4_IRQ_FIRST+50) /* 50: CCU4 Module 1, SR2 */ -#define XM4_IRQ_CCU41_SR3 (XM4_IRQ_FIRST+51) /* 51: CCU4 Module 1, SR3 */ -#define XM4_IRQ_CCU42_SR0 (XM4_IRQ_FIRST+52) /* 52: CCU4 Module 2, SR0 */ -#define XM4_IRQ_CCU42_SR1 (XM4_IRQ_FIRST+53) /* 53: CCU4 Module 2, SR1 */ -#define XM4_IRQ_CCU42_SR2 (XM4_IRQ_FIRST+54) /* 54: CCU4 Module 2, SR2 */ -#define XM4_IRQ_CCU42_SR3 (XM4_IRQ_FIRST+55) /* 55: CCU4 Module 2, SR3 */ -#define XM4_IRQ_CCU43_SR0 (XM4_IRQ_FIRST+56) /* 56: CCU4 Module 3, SR0 */ -#define XM4_IRQ_CCU43_SR1 (XM4_IRQ_FIRST+57) /* 57: CCU4 Module 3, SR1 */ -#define XM4_IRQ_CCU43_SR2 (XM4_IRQ_FIRST+58) /* 58: CCU4 Module 3, SR2 */ -#define XM4_IRQ_CCU43_SR3 (XM4_IRQ_FIRST+59) /* 59: CCU4 Module 3, SR3 */ -#define XM4_IRQ_CCU80_SR0 (XM4_IRQ_FIRST+60) /* 60: CCU8 Module 0, SR0 */ -#define XM4_IRQ_CCU80_SR1 (XM4_IRQ_FIRST+61) /* 61: CCU8 Module 0, SR1 */ -#define XM4_IRQ_CCU80_SR2 (XM4_IRQ_FIRST+62) /* 62: CCU8 Module 0, SR2 */ -#define XM4_IRQ_CCU80_SR3 (XM4_IRQ_FIRST+63) /* 63: CCU8 Module 0, SR3 */ -#define XM4_IRQ_CCU81_SR0 (XM4_IRQ_FIRST+64) /* 64: CCU8 Module 1, SR0 */ -#define XM4_IRQ_CCU81_SR1 (XM4_IRQ_FIRST+65) /* 65: CCU8 Module 1, SR1 */ -#define XM4_IRQ_CCU81_SR2 (XM4_IRQ_FIRST+66) /* 66: CCU8 Module 1, SR2 */ -#define XM4_IRQ_CCU81_SR3 (XM4_IRQ_FIRST+67) /* 67: CCU8 Module 1, SR3 */ -#define XM4_IRQ_POSIF0_SR0 (XM4_IRQ_FIRST+68) /* 68: POSIF Module 0, SR0 */ -#define XM4_IRQ_POSIF0_SR1 (XM4_IRQ_FIRST+69) /* 69: POSIF Module 0, SR1 */ -#define XM4_IRQ_POSIF1_SR0 (XM4_IRQ_FIRST+70) /* 70: POSIF Module 1, SR0 */ -#define XM4_IRQ_POSIF1_SR1 (XM4_IRQ_FIRST+71) /* 71: POSIF Module 1, SR1 */ -#define XM4_IRQ_RESVD072 (XM4_IRQ_FIRST+72) /* 72: Reserved */ -#define XM4_IRQ_RESVD073 (XM4_IRQ_FIRST+73) /* 73: Reserved */ -#define XM4_IRQ_RESVD074 (XM4_IRQ_FIRST+74) /* 74: Reserved */ -#define XM4_IRQ_RESVD075 (XM4_IRQ_FIRST+75) /* 75: Reserved */ -#define XM4_IRQ_CAN_SR0 (XM4_IRQ_FIRST+76) /* 76: MultiCAN, SR0 */ -#define XM4_IRQ_CAN_SR1 (XM4_IRQ_FIRST+77) /* 77: MultiCAN, SR1 */ -#define XM4_IRQ_CAN_SR2 (XM4_IRQ_FIRST+78) /* 78: MultiCAN, SR2 */ -#define XM4_IRQ_CAN_SR3 (XM4_IRQ_FIRST+79) /* 79: MultiCAN, SR3 */ -#define XM4_IRQ_CAN_SR4 (XM4_IRQ_FIRST+80) /* 80: MultiCAN, SR4 */ -#define XM4_IRQ_CAN_SR5 (XM4_IRQ_FIRST+81) /* 81: MultiCAN, SR5 */ -#define XM4_IRQ_CAN_SR6 (XM4_IRQ_FIRST+82) /* 82: MultiCAN, SR6 */ -#define XM4_IRQ_CAN_SR7 (XM4_IRQ_FIRST+83) /* 83: MultiCAN, SR7 */ -#define XM4_IRQ_USIC0_SR0 (XM4_IRQ_FIRST+84) /* 84: USIC0 Channel, SR0 */ -#define XM4_IRQ_USIC0_SR1 (XM4_IRQ_FIRST+85) /* 85: USIC0 Channel, SR1 */ -#define XM4_IRQ_USIC0_SR2 (XM4_IRQ_FIRST+86) /* 86: USIC0 Channel, SR2 */ -#define XM4_IRQ_USIC0_SR3 (XM4_IRQ_FIRST+87) /* 87: USIC0 Channel, SR3 */ -#define XM4_IRQ_USIC0_SR4 (XM4_IRQ_FIRST+88) /* 88: USIC0 Channel, SR4 */ -#define XM4_IRQ_USIC0_SR5 (XM4_IRQ_FIRST+89) /* 89: USIC0 Channel, SR5 */ -#define XM4_IRQ_USIC1_SR0 (XM4_IRQ_FIRST+90) /* 90: USIC1 Channel, SR0 */ -#define XM4_IRQ_USIC1_SR1 (XM4_IRQ_FIRST+91) /* 91: USIC1 Channel, SR1 */ -#define XM4_IRQ_USIC1_SR2 (XM4_IRQ_FIRST+92) /* 92: USIC1 Channel, SR2 */ -#define XM4_IRQ_USIC1_SR3 (XM4_IRQ_FIRST+93) /* 93: USIC1 Channel, SR3 */ -#define XM4_IRQ_USIC1_SR4 (XM4_IRQ_FIRST+94) /* 94: USIC1 Channel, SR4 */ -#define XM4_IRQ_USIC1_SR5 (XM4_IRQ_FIRST+95) /* 95: USIC1 Channel, SR5 */ -#define XM4_IRQ_USIC2_SR0 (XM4_IRQ_FIRST+96) /* 96: USIC1 Channel, SR0 */ -#define XM4_IRQ_USIC2_SR1 (XM4_IRQ_FIRST+97) /* 97: USIC1 Channel, SR1 */ -#define XM4_IRQ_USIC2_SR2 (XM4_IRQ_FIRST+98) /* 98: USIC1 Channel, SR2 */ -#define XM4_IRQ_USIC2_SR3 (XM4_IRQ_FIRST+99) /* 99: USIC1 Channel, SR3 */ -#define XM4_IRQ_USIC2_SR4 (XM4_IRQ_FIRST+100) /* 100: USIC1 Channel, SR4 */ -#define XM4_IRQ_USIC2_SR5 (XM4_IRQ_FIRST+101) /* 101: USIC1 Channel, SR5 */ -#define XM4_IRQ_LEDTS0_SR0 (XM4_IRQ_FIRST+102) /* 102: LEDTS0, SR0 */ -#define XM4_IRQ_RESVD103 (XM4_IRQ_FIRST+103) /* 103: Reserved */ -#define XM4_IRQ_FCR_SR0 (XM4_IRQ_FIRST+104) /* 102: FCE, SR0 */ -#define XM4_IRQ_GPCMA0_SR0 (XM4_IRQ_FIRST+105) /* 105: GPDMA0, SR0 */ -#define XM4_IRQ_SDMMC_SR0 (XM4_IRQ_FIRST+106) /* 106: SDMMC, SR0 */ -#define XM4_IRQ_USB0_SR0 (XM4_IRQ_FIRST+107) /* 107: USB, SR0 */ -#define XM4_IRQ_ETH0_SR0 (XM4_IRQ_FIRST+108) /* 108: Ethernet, module 0, SR0 */ -#define XM4_IRQ_RESVD109 (XM4_IRQ_FIRST+109) /* 109: Reserved */ -#define XM4_IRQ_GPCMA1_SR0 (XM4_IRQ_FIRST+110) /* 110: GPDMA1, SR0 */ -#define XM4_IRQ_RESVD111 (XM4_IRQ_FIRST+111) /* 111: Reserved */ +#define XMC4_IRQ_SCU (XMC4_IRQ_FIRST+0) /* 0: System Control */ +#define XMC4_IRQ_ERU0_SR0 (XMC4_IRQ_FIRST+1) /* 1: ERU0, SR0 */ +#define XMC4_IRQ_ERU0_SR1 (XMC4_IRQ_FIRST+2) /* 2: ERU0, SR1 */ +#define XMC4_IRQ_ERU0_SR2 (XMC4_IRQ_FIRST+3) /* 3: ERU0, SR2 */ +#define XMC4_IRQ_ERU0_SR3 (XMC4_IRQ_FIRST+4) /* 4: ERU0, SR3 */ +#define XMC4_IRQ_ERU1_SR0 (XMC4_IRQ_FIRST+5) /* 5: ERU1, SR0 */ +#define XMC4_IRQ_ERU1_SR1 (XMC4_IRQ_FIRST+6) /* 6: ERU1, SR1 */ +#define XMC4_IRQ_ERU1_SR2 (XMC4_IRQ_FIRST+7) /* 7: ERU1, SR2 */ +#define XMC4_IRQ_ERU1_SR3 (XMC4_IRQ_FIRST+8) /* 8: ERU1, SR3 */ +#define XMC4_IRQ_RESVD009 (XMC4_IRQ_FIRST+9) /* 9: Reserved */ +#define XMC4_IRQ_RESVD010 (XMC4_IRQ_FIRST+10) /* 10: Reserved */ +#define XMC4_IRQ_RESVD011 (XMC4_IRQ_FIRST+11) /* 11: Reserved */ +#define XMC4_IRQ_PMU1_SR0 (XMC4_IRQ_FIRST+12) /* 12: PMU, SR0 */ +#define XMC4_IRQ_RESVD011 (XMC4_IRQ_FIRST+13) /* 13: Reserved */ +#define XMC4_IRQ_VADC_COSR0 (XMC4_IRQ_FIRST+14) /* 14: ADC Common Block 0 */ +#define XMC4_IRQ_VADC_COSR1 (XMC4_IRQ_FIRST+15) /* 15: ADC Common Block 1 */ +#define XMC4_IRQ_VADC_COSR2 (XMC4_IRQ_FIRST+16) /* 16: ADC Common Block 2 */ +#define XMC4_IRQ_VADC_COSR3 (XMC4_IRQ_FIRST+17) /* 17: ADC Common Block 3 */ +#define XMC4_IRQ_VADC_GOSR0 (XMC4_IRQ_FIRST+18) /* 18: ADC Group 0, SR0 */ +#define XMC4_IRQ_VADC_GOSR1 (XMC4_IRQ_FIRST+19) /* 19: ADC Group 0, SR1 */ +#define XMC4_IRQ_VADC_GOSR2 (XMC4_IRQ_FIRST+20) /* 20: ADC Group 0, SR2 */ +#define XMC4_IRQ_VADC_GOSR3 (XMC4_IRQ_FIRST+21) /* 21: ADC Group 0, SR3 */ +#define XMC4_IRQ_VADC_G1SR0 (XMC4_IRQ_FIRST+22) /* 22: ADC Group 1, SR0 */ +#define XMC4_IRQ_VADC_G1SR1 (XMC4_IRQ_FIRST+23) /* 23: ADC Group 1, SR1 */ +#define XMC4_IRQ_VADC_G1SR2 (XMC4_IRQ_FIRST+24) /* 24: ADC Group 1, SR2 */ +#define XMC4_IRQ_VADC_G1SR3 (XMC4_IRQ_FIRST+25) /* 25: ADC Group 1, SR3 */ +#define XMC4_IRQ_VADC_G2SR0 (XMC4_IRQ_FIRST+26) /* 26: ADC Group 2, SR0 */ +#define XMC4_IRQ_VADC_G2SR1 (XMC4_IRQ_FIRST+27) /* 27: ADC Group 2, SR1 */ +#define XMC4_IRQ_VADC_G2SR2 (XMC4_IRQ_FIRST+28) /* 28: ADC Group 2, SR2 */ +#define XMC4_IRQ_VADC_G2SR3 (XMC4_IRQ_FIRST+29) /* 29: ADC Group 2, SR3 */ +#define XMC4_IRQ_VADC_G3SR0 (XMC4_IRQ_FIRST+30) /* 30: ADC Group 3, SR0 */ +#define XMC4_IRQ_VADC_G3SR1 (XMC4_IRQ_FIRST+31) /* 31: ADC Group 3, SR1 */ +#define XMC4_IRQ_VADC_G3SR2 (XMC4_IRQ_FIRST+32) /* 32: ADC Group 3, SR2 */ +#define XMC4_IRQ_VADC_G3SR3 (XMC4_IRQ_FIRST+33) /* 33: ADC Group 3, SR3 */ +#define XMC4_IRQ_DSD_SRM0 (XMC4_IRQ_FIRST+34) /* 34: DSD Main, SRM0 */ +#define XMC4_IRQ_DSD_SRM1 (XMC4_IRQ_FIRST+35) /* 35: DSD Main, SRM1 */ +#define XMC4_IRQ_DSD_SRM2 (XMC4_IRQ_FIRST+36) /* 36: DSD Main, SRM2 */ +#define XMC4_IRQ_DSD_SRM3 (XMC4_IRQ_FIRST+37) /* 37: DSD Main, SRM3 */ +#define XMC4_IRQ_DSD_SRA0 (XMC4_IRQ_FIRST+38) /* 38: DSD Auxiliary, SRA0 */ +#define XMC4_IRQ_DSD_SRA1 (XMC4_IRQ_FIRST+39) /* 39: DSD Auxiliary, SRA1 */ +#define XMC4_IRQ_DSD_SRA2 (XMC4_IRQ_FIRST+40) /* 40: DSD Auxiliary, SRA2 */ +#define XMC4_IRQ_DSD_SRA3 (XMC4_IRQ_FIRST+41) /* 41: DSD Auxiliary, SRA3 */ +#define XMC4_IRQ_DAC_SR0 (XMC4_IRQ_FIRST+42) /* 42: DAC, SR0 */ +#define XMC4_IRQ_DAC_SR1 (XMC4_IRQ_FIRST+43) /* 43: DAC, SR1 */ +#define XMC4_IRQ_CCU40_SR0 (XMC4_IRQ_FIRST+44) /* 44: CCU4 Module 0, SR0 */ +#define XMC4_IRQ_CCU40_SR1 (XMC4_IRQ_FIRST+45) /* 45: CCU4 Module 0, SR1 */ +#define XMC4_IRQ_CCU40_SR2 (XMC4_IRQ_FIRST+46) /* 46: CCU4 Module 0, SR2 */ +#define XMC4_IRQ_CCU40_SR3 (XMC4_IRQ_FIRST+47) /* 47: CCU4 Module 0, SR3 */ +#define XMC4_IRQ_CCU41_SR0 (XMC4_IRQ_FIRST+48) /* 48: CCU4 Module 1, SR0 */ +#define XMC4_IRQ_CCU41_SR1 (XMC4_IRQ_FIRST+49) /* 49: CCU4 Module 1, SR1 */ +#define XMC4_IRQ_CCU41_SR2 (XMC4_IRQ_FIRST+50) /* 50: CCU4 Module 1, SR2 */ +#define XMC4_IRQ_CCU41_SR3 (XMC4_IRQ_FIRST+51) /* 51: CCU4 Module 1, SR3 */ +#define XMC4_IRQ_CCU42_SR0 (XMC4_IRQ_FIRST+52) /* 52: CCU4 Module 2, SR0 */ +#define XMC4_IRQ_CCU42_SR1 (XMC4_IRQ_FIRST+53) /* 53: CCU4 Module 2, SR1 */ +#define XMC4_IRQ_CCU42_SR2 (XMC4_IRQ_FIRST+54) /* 54: CCU4 Module 2, SR2 */ +#define XMC4_IRQ_CCU42_SR3 (XMC4_IRQ_FIRST+55) /* 55: CCU4 Module 2, SR3 */ +#define XMC4_IRQ_CCU43_SR0 (XMC4_IRQ_FIRST+56) /* 56: CCU4 Module 3, SR0 */ +#define XMC4_IRQ_CCU43_SR1 (XMC4_IRQ_FIRST+57) /* 57: CCU4 Module 3, SR1 */ +#define XMC4_IRQ_CCU43_SR2 (XMC4_IRQ_FIRST+58) /* 58: CCU4 Module 3, SR2 */ +#define XMC4_IRQ_CCU43_SR3 (XMC4_IRQ_FIRST+59) /* 59: CCU4 Module 3, SR3 */ +#define XMC4_IRQ_CCU80_SR0 (XMC4_IRQ_FIRST+60) /* 60: CCU8 Module 0, SR0 */ +#define XMC4_IRQ_CCU80_SR1 (XMC4_IRQ_FIRST+61) /* 61: CCU8 Module 0, SR1 */ +#define XMC4_IRQ_CCU80_SR2 (XMC4_IRQ_FIRST+62) /* 62: CCU8 Module 0, SR2 */ +#define XMC4_IRQ_CCU80_SR3 (XMC4_IRQ_FIRST+63) /* 63: CCU8 Module 0, SR3 */ +#define XMC4_IRQ_CCU81_SR0 (XMC4_IRQ_FIRST+64) /* 64: CCU8 Module 1, SR0 */ +#define XMC4_IRQ_CCU81_SR1 (XMC4_IRQ_FIRST+65) /* 65: CCU8 Module 1, SR1 */ +#define XMC4_IRQ_CCU81_SR2 (XMC4_IRQ_FIRST+66) /* 66: CCU8 Module 1, SR2 */ +#define XMC4_IRQ_CCU81_SR3 (XMC4_IRQ_FIRST+67) /* 67: CCU8 Module 1, SR3 */ +#define XMC4_IRQ_POSIF0_SR0 (XMC4_IRQ_FIRST+68) /* 68: POSIF Module 0, SR0 */ +#define XMC4_IRQ_POSIF0_SR1 (XMC4_IRQ_FIRST+69) /* 69: POSIF Module 0, SR1 */ +#define XMC4_IRQ_POSIF1_SR0 (XMC4_IRQ_FIRST+70) /* 70: POSIF Module 1, SR0 */ +#define XMC4_IRQ_POSIF1_SR1 (XMC4_IRQ_FIRST+71) /* 71: POSIF Module 1, SR1 */ +#define XMC4_IRQ_RESVD072 (XMC4_IRQ_FIRST+72) /* 72: Reserved */ +#define XMC4_IRQ_RESVD073 (XMC4_IRQ_FIRST+73) /* 73: Reserved */ +#define XMC4_IRQ_RESVD074 (XMC4_IRQ_FIRST+74) /* 74: Reserved */ +#define XMC4_IRQ_RESVD075 (XMC4_IRQ_FIRST+75) /* 75: Reserved */ +#define XMC4_IRQ_CAN_SR0 (XMC4_IRQ_FIRST+76) /* 76: MultiCAN, SR0 */ +#define XMC4_IRQ_CAN_SR1 (XMC4_IRQ_FIRST+77) /* 77: MultiCAN, SR1 */ +#define XMC4_IRQ_CAN_SR2 (XMC4_IRQ_FIRST+78) /* 78: MultiCAN, SR2 */ +#define XMC4_IRQ_CAN_SR3 (XMC4_IRQ_FIRST+79) /* 79: MultiCAN, SR3 */ +#define XMC4_IRQ_CAN_SR4 (XMC4_IRQ_FIRST+80) /* 80: MultiCAN, SR4 */ +#define XMC4_IRQ_CAN_SR5 (XMC4_IRQ_FIRST+81) /* 81: MultiCAN, SR5 */ +#define XMC4_IRQ_CAN_SR6 (XMC4_IRQ_FIRST+82) /* 82: MultiCAN, SR6 */ +#define XMC4_IRQ_CAN_SR7 (XMC4_IRQ_FIRST+83) /* 83: MultiCAN, SR7 */ +#define XMC4_IRQ_USIC0_SR0 (XMC4_IRQ_FIRST+84) /* 84: USIC0 Channel, SR0 */ +#define XMC4_IRQ_USIC0_SR1 (XMC4_IRQ_FIRST+85) /* 85: USIC0 Channel, SR1 */ +#define XMC4_IRQ_USIC0_SR2 (XMC4_IRQ_FIRST+86) /* 86: USIC0 Channel, SR2 */ +#define XMC4_IRQ_USIC0_SR3 (XMC4_IRQ_FIRST+87) /* 87: USIC0 Channel, SR3 */ +#define XMC4_IRQ_USIC0_SR4 (XMC4_IRQ_FIRST+88) /* 88: USIC0 Channel, SR4 */ +#define XMC4_IRQ_USIC0_SR5 (XMC4_IRQ_FIRST+89) /* 89: USIC0 Channel, SR5 */ +#define XMC4_IRQ_USIC1_SR0 (XMC4_IRQ_FIRST+90) /* 90: USIC1 Channel, SR0 */ +#define XMC4_IRQ_USIC1_SR1 (XMC4_IRQ_FIRST+91) /* 91: USIC1 Channel, SR1 */ +#define XMC4_IRQ_USIC1_SR2 (XMC4_IRQ_FIRST+92) /* 92: USIC1 Channel, SR2 */ +#define XMC4_IRQ_USIC1_SR3 (XMC4_IRQ_FIRST+93) /* 93: USIC1 Channel, SR3 */ +#define XMC4_IRQ_USIC1_SR4 (XMC4_IRQ_FIRST+94) /* 94: USIC1 Channel, SR4 */ +#define XMC4_IRQ_USIC1_SR5 (XMC4_IRQ_FIRST+95) /* 95: USIC1 Channel, SR5 */ +#define XMC4_IRQ_USIC2_SR0 (XMC4_IRQ_FIRST+96) /* 96: USIC1 Channel, SR0 */ +#define XMC4_IRQ_USIC2_SR1 (XMC4_IRQ_FIRST+97) /* 97: USIC1 Channel, SR1 */ +#define XMC4_IRQ_USIC2_SR2 (XMC4_IRQ_FIRST+98) /* 98: USIC1 Channel, SR2 */ +#define XMC4_IRQ_USIC2_SR3 (XMC4_IRQ_FIRST+99) /* 99: USIC1 Channel, SR3 */ +#define XMC4_IRQ_USIC2_SR4 (XMC4_IRQ_FIRST+100) /* 100: USIC1 Channel, SR4 */ +#define XMC4_IRQ_USIC2_SR5 (XMC4_IRQ_FIRST+101) /* 101: USIC1 Channel, SR5 */ +#define XMC4_IRQ_LEDTS0_SR0 (XMC4_IRQ_FIRST+102) /* 102: LEDTS0, SR0 */ +#define XMC4_IRQ_RESVD103 (XMC4_IRQ_FIRST+103) /* 103: Reserved */ +#define XMC4_IRQ_FCR_SR0 (XMC4_IRQ_FIRST+104) /* 102: FCE, SR0 */ +#define XMC4_IRQ_GPCMA0_SR0 (XMC4_IRQ_FIRST+105) /* 105: GPDMA0, SR0 */ +#define XMC4_IRQ_SDMMC_SR0 (XMC4_IRQ_FIRST+106) /* 106: SDMMC, SR0 */ +#define XMC4_IRQ_USB0_SR0 (XMC4_IRQ_FIRST+107) /* 107: USB, SR0 */ +#define XMC4_IRQ_ETH0_SR0 (XMC4_IRQ_FIRST+108) /* 108: Ethernet, module 0, SR0 */ +#define XMC4_IRQ_RESVD109 (XMC4_IRQ_FIRST+109) /* 109: Reserved */ +#define XMC4_IRQ_GPCMA1_SR0 (XMC4_IRQ_FIRST+110) /* 110: GPDMA1, SR0 */ +#define XMC4_IRQ_RESVD111 (XMC4_IRQ_FIRST+111) /* 111: Reserved */ -#define NR_INTERRUPTS 112 /* 112 Non core IRQs*/ -#define NR_VECTORS (XM4_IRQ_FIRST+NR_INTERRUPTS) /* 118 vectors */ +#define NR_INTERRUPTS 112 /* 112 Non core IRQs*/ +#define NR_VECTORS (XMC4_IRQ_FIRST+NR_INTERRUPTS) /* 118 vectors */ /* GPIO IRQ interrupts -- To be provided */ -#define NR_IRQS NR_VECTORS +#define NR_IRQS NR_VECTORS /***************************************************************************** * Public Types @@ -222,4 +222,4 @@ extern "C" #endif #endif -#endif /* xmc4__ARCH_ARM_INCLUDE_XM4_XM4500_IRQ_H */ +#endif /* xmc4__ARCH_ARM_INCLUDE_XMC4_XM4500_IRQ_H */ diff --git a/arch/arm/src/xmc4/chip/xmc4_scu.h b/arch/arm/src/xmc4/chip/xmc4_scu.h index e08a64a48c0..7e706f501bd 100644 --- a/arch/arm/src/xmc4/chip/xmc4_scu.h +++ b/arch/arm/src/xmc4/chip/xmc4_scu.h @@ -185,9 +185,9 @@ /* Oscillator Control SCU Registers */ -#define XMC4_OCU_OSCHPSTAT_OFFSET 0x0000 /* OSC_HP Status Register */ -#define XMC4_OCU_OSCHPCTRL_OFFSET 0x0004 /* OSC_HP Control Register */ -#define XMC4_OCU_CLKCALCONST_OFFSET 0x000c /* Clock Calibration Constant Register */ +#define XMC4_SCU_OSCHPSTAT_OFFSET 0x0000 /* OSC_HP Status Register */ +#define XMC4_SCU_OSCHPCTRL_OFFSET 0x0004 /* OSC_HP Control Register */ +#define XMC4_SCU_CLKCALCONST_OFFSET 0x000c /* Clock Calibration Constant Register */ /* PLL Control SCU Registers */ @@ -623,8 +623,8 @@ /* System Clock Control */ #define SCU_SYSCLKCR_SYSDIV_SHIFT (0) /* Bits 0-7: System Clock Division Value */ -#define SCU_SYSCLKCR_SYSDIV_MASK (0xff << SCU_CLK_SYSCLKCR_SYSDIV_SHIFT) -# define SCU_SYSCLKCR_SYSDIV(n) ((uint32_t)((n)-1) << SCU_CLK_SYSCLKCR_SYSDIV_SHIFT) +#define SCU_SYSCLKCR_SYSDIV_MASK (0xff << SCU_SYSCLKCR_SYSDIV_SHIFT) +# define SCU_SYSCLKCR_SYSDIV(n) ((uint32_t)((n)-1) << SCU_SYSCLKCR_SYSDIV_SHIFT) #define SCU_SYSCLKCR_SYSSEL (1 << 16) /* Bit 16: System Clock Selection Value */ # define SCU_SYSCLKCR_SYSSEL_OFI (0) /* 0=OFI clock */ @@ -640,8 +640,8 @@ /* USB Clock Control */ #define SCU_USBCLKCR_USBDIV_SHIFT (0) /* Bits 0-2: USB Clock Divider Value */ -#define SCU_USBCLKCR_USBDIV_MASK (7 << SCU_CLK_USBCLKCR_USBDIV_SHIFT) -# define SCU_SYSCLKCR_USBDIV(n) ((uint32_t)((n)-1) << SCU_CLK_USBCLKCR_USBDIV_SHIFT) +#define SCU_USBCLKCR_USBDIV_MASK (7 << SCU_USBCLKCR_USBDIV_SHIFT) +# define SCU_SYSCLKCR_USBDIV(n) ((uint32_t)((n)-1) << SCU_USBCLKCR_USBDIV_SHIFT) #define SCU_USBCLKCR_USBSEL (1 << 16) /* Bit 16: USB Clock Selection Value */ # define SCU_USBCLKCR_USBSEL_USBPLL (0) /* 0=USB PLL Clock */ # define SCU_USBCLKCR_USBSEL_PLL (1 << 16) /* 1= PLL Clock */ diff --git a/arch/arm/src/xmc4/xmc4_clockconfig.c b/arch/arm/src/xmc4/xmc4_clockconfig.c index 6667ceca861..26608a85b84 100644 --- a/arch/arm/src/xmc4/xmc4_clockconfig.c +++ b/arch/arm/src/xmc4/xmc4_clockconfig.c @@ -57,6 +57,7 @@ #include "up_arch.h" #include "chip/xmc4_scu.h" +#include "xmc4_clockconfig.h" #include @@ -83,7 +84,7 @@ #define SCU_PLLSTAT_OSC_USABLE \ (SCU_PLLSTAT_PLLHV | SCU_PLLSTAT_PLLLV | SCU_PLLSTAT_PLLSP) -#ifndef BOARD_PLL_CLOCKSRC_XTAL +#ifdef BOARD_PLL_CLOCKSRC_XTAL # define VCO ((BOARD_XTAL_FREQUENCY / BOARD_PLL_PDIV) * BOARD_PLL_NDIV) #else /* BOARD_PLL_CLOCKSRC_XTAL */ @@ -171,7 +172,7 @@ void xmc4_clock_configure(void) regval = getreg32(XMC4_SCU_PLLCON0); regval |= SCU_PLLCON0_FOTR; - putreg(regval, XMC4_SCU_PLLCON0); + putreg32(regval, XMC4_SCU_PLLCON0); #else /* Automatic calibration uses the fSTDBY */ @@ -195,10 +196,9 @@ void xmc4_clock_configure(void) /* Remove the reset only if HIB domain were in a state of reset */ regval = getreg32(XMC4_SCU_RSTSTAT); - if ((regval & SCU_RSTSTAT_HIBRS) ! = 0) + if ((regval & SCU_RSTSTAT_HIBRS) != 0) { - regval = getreg32(XMC4_SCU_RSTSTAT); - SCU_RESET->RSTCLR |= SCU_RESET_RSTCLR_HIBRS_Msk; + regval = putreg32(SCU_RSTCLR_HIBRS, XMC4_SCU_RSTCLR); delay(DELAY_CNT_150US_50MHZ); } @@ -271,19 +271,19 @@ void xmc4_clock_configure(void) regval = getreg32(XMC4_SCU_PLLCON0); regval |= SCU_PLLCON0_AOTREN; - putreg(regval, XMC4_SCU_PLLCON0); + putreg32(regval, XMC4_SCU_PLLCON0); #endif /* BOARD_FOFI_CALIBRATION */ delay(DELAY_CNT_50US_50MHZ); -#if BOARD_ENABLE_PLL +#ifdef BOARD_ENABLE_PLL /* Enable PLL */ regval = getreg32(XMC4_SCU_PLLCON0); regval &= ~(SCU_PLLCON0_VCOPWD | SCU_PLLCON0_PLLPWD); - putreg(regval, XMC4_SCU_PLLCON0); + putreg32(regval, XMC4_SCU_PLLCON0); #ifdef BOARD_PLL_CLOCKSRC_XTAL /* Enable OSC_HP */ @@ -292,7 +292,7 @@ void xmc4_clock_configure(void) { regval = getreg32(XMC4_SCU_OSCHPCTRL); regval &= ~(SCU_OSCHPCTRL_MODE_MASK | SCU_OSCHPCTRL_OSCVAL_MASK); - regval |= ((OSCHP_GetFrequency() / FOSCREF) - 1) << SCU_OSCHPCTRL_OSCVAL_SHIFT; + regval |= ((BOARD_XTAL_FREQUENCY / FOSCREF) - 1) << SCU_OSCHPCTRL_OSCVAL_SHIFT; putreg32(regval, XMC4_SCU_OSCHPCTRL); /* Select OSC_HP clock as PLL input */ @@ -305,7 +305,7 @@ void xmc4_clock_configure(void) regval = getreg32(XMC4_SCU_PLLCON0); regval &= ~SCU_PLLCON0_OSCRES; - putreg(regval, XMC4_SCU_PLLCON0); + putreg32(regval, XMC4_SCU_PLLCON0); /* Wait till OSC_HP output frequency is usable */ @@ -330,36 +330,36 @@ void xmc4_clock_configure(void) regval = getreg32(XMC4_SCU_PLLCON0); regval |= SCU_PLLCON0_VCOBYP; - putreg(regval, XMC4_SCU_PLLCON0); + putreg32(regval, XMC4_SCU_PLLCON0); /* Disconnect Oscillator from PLL */ regval |= SCU_PLLCON0_FINDIS; - putreg(regval, XMC4_SCU_PLLCON0); + putreg32(regval, XMC4_SCU_PLLCON0); /* Setup divider settings for main PLL */ regval = (SCU_PLLCON1_NDIV(BOARD_PLL_NDIV) | SCU_PLLCON1_K2DIV(PLL_K2DIV_24MHZ) | - SCU_PLLCON1_PDIV(BOARD_PLL_PDIV); + SCU_PLLCON1_PDIV(BOARD_PLL_PDIV)); putreg32(regval, XMC4_SCU_PLLCON1); /* Set OSCDISCDIS */ regval = getreg32(XMC4_SCU_PLLCON0); regval |= SCU_PLLCON0_OSCDISCDIS; - putreg(regval, XMC4_SCU_PLLCON0); + putreg32(regval, XMC4_SCU_PLLCON0); /* Connect Oscillator to PLL */ regval = getreg32(XMC4_SCU_PLLCON0); regval &= ~SCU_PLLCON0_FINDIS; - putreg(regval, XMC4_SCU_PLLCON0); + putreg32(regval, XMC4_SCU_PLLCON0); /* Restart PLL Lock detection */ regval |= SCU_PLLCON0_RESLD; - putreg(regval, XMC4_SCU_PLLCON0); + putreg32(regval, XMC4_SCU_PLLCON0); /* wait for PLL Lock at 24MHz*/ @@ -371,7 +371,7 @@ void xmc4_clock_configure(void) regval = getreg32(XMC4_SCU_PLLCON0); regval &= ~SCU_PLLCON0_VCOBYP; - putreg(regval, XMC4_SCU_PLLCON0); + putreg32(regval, XMC4_SCU_PLLCON0); /* Wait for normal mode */ @@ -393,7 +393,7 @@ void xmc4_clock_configure(void) putreg32(WDTCLKCR_VALUE, XMC4_SCU_WDTCLKCR); putreg32(EBUCLKCR_VALUE, XMC4_SCU_EBUCLKCR); putreg32(USBCLKCR_VALUE | USB_DIV, XMC4_SCU_USBCLKCR); - putreg32(EXTCLKCR_VALUE, EXTCLKCR); + putreg32(EXTCLKCR_VALUE, XMC4_SCU_EXTCLKCR); #if BOARD_ENABLE_PLL /* PLL frequency stepping...*/ @@ -401,7 +401,7 @@ void xmc4_clock_configure(void) regval = getreg32(XMC4_SCU_PLLCON0); regval &= ~SCU_PLLCON0_OSCDISCDIS; - putreg(regval, XMC4_SCU_PLLCON0); + putreg32(regval, XMC4_SCU_PLLCON0); regval = (SCU_PLLCON1_NDIV(BOARD_PLL_NDIV) | SCU_PLLCON1_K2DIV(PLL_K2DIV_48MHZ) | @@ -440,7 +440,7 @@ void xmc4_clock_configure(void) #endif /* BOARD_ENABLE_PLL */ -#if BOARD_ENABLE_USBPLL +#ifdef BOARD_ENABLE_USBPLL /* Enable USB PLL first */ regval = getreg32(XMC4_SCU_USBPLLCON); @@ -461,19 +461,19 @@ void xmc4_clock_configure(void) regval = getreg32(XMC4_SCU_PLLCON0); regval &= ~(SCU_PLLCON0_VCOPWD | SCU_PLLCON0_PLLPWD); - putreg(regval, XMC4_SCU_PLLCON0); + putreg32(regval, XMC4_SCU_PLLCON0); } regval = getreg32(XMC4_SCU_OSCHPCTRL); regval &= ~(SCU_OSCHPCTRL_MODE_MASK | SCU_OSCHPCTRL_OSCVAL_MASK); - regval |= ((OSCHP_GetFrequency() / FOSCREF) - 1) << SCU_OSCHPCTRL_OSCVAL_SHIFT; + regval |= ((BOARD_XTAL_FREQUENCY / FOSCREF) - 1) << SCU_OSCHPCTRL_OSCVAL_SHIFT; putreg32(regval, XMC4_SCU_OSCHPCTRL); /* Restart OSC Watchdog */ regval = getreg32(XMC4_SCU_PLLCON0); regval &= ~SCU_PLLCON0_OSCRES; - putreg(regval, XMC4_SCU_PLLCON0); + putreg32(regval, XMC4_SCU_PLLCON0); /* Wait till OSC_HP output frequency is usable */ @@ -527,7 +527,7 @@ void xmc4_clock_configure(void) /* Enable selected clocks */ - putreg32(CLKSET_VALUE, XMC4_SCU_CLKSET) + putreg32(CLKSET_VALUE, XMC4_SCU_CLKSET); } /**************************************************************************** @@ -605,7 +605,7 @@ uint32_t xmc4_get_coreclock(void) /* Check if the fSYS clock is divided by two to produce fCPU clock. */ - regval = getreg32(CPUCLKCR); + regval = getreg32(XMC4_SCU_CPUCLKCR); if ((regval & SCU_CPUCLKCR_CPUDIV) != 0) { temp = temp >> 1; diff --git a/arch/arm/src/xmc4/xmc4_irq.c b/arch/arm/src/xmc4/xmc4_irq.c index 17725b8c608..c31482b6385 100644 --- a/arch/arm/src/xmc4/xmc4_irq.c +++ b/arch/arm/src/xmc4/xmc4_irq.c @@ -45,6 +45,7 @@ #include #include #include +#include #include "nvic.h" #include "ram_vectors.h" diff --git a/configs/xmc4500-relax/include/board.h b/configs/xmc4500-relax/include/board.h index f3616a21e2c..dbc2440902d 100644 --- a/configs/xmc4500-relax/include/board.h +++ b/configs/xmc4500-relax/include/board.h @@ -130,6 +130,68 @@ #define BOARD_FLASH_WS 5 +/* LED definitions ******************************************************************/ +/* The XMC4500 Relax Lite v1 board has two LEDs: + * + * LED1 P1.1 High output illuminates + * LED2 P1.0 High output illuminates + * + * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in any + * way. The following definitions are used to access individual LEDs. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED0 0 +#define BOARD_LED1 1 +#define BOARD_NLEDS 2 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED0_BIT (1 << BOARD_LED0) +#define BOARD_LED1_BIT (1 << BOARD_LED1) + +/* These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is + * defined. In that case, the usage by the board port is defined in + * include/board.h and src/sam_autoleds.c. The LEDs are used to encode + * OS-related events as follows: + * + * SYMBOL Meaning LED state + * LED2 LED1 + * --------------------- -------------------------- ------ ------ */ + +#define LED_STARTED 0 /* NuttX has been started OFF OFF */ +#define LED_HEAPALLOCATE 0 /* Heap has been allocated OFF OFF */ +#define LED_IRQSENABLED 0 /* Interrupts enabled OFF OFF */ +#define LED_STACKCREATED 1 /* Idle stack created ON OFF */ +#define LED_INIRQ 2 /* In an interrupt No change */ +#define LED_SIGNAL 2 /* In a signal handler No change */ +#define LED_ASSERTION 2 /* An assertion failed No change */ +#define LED_PANIC 3 /* The system has crashed N/C Blinking */ +#undef LED_IDLE /* MCU is is sleep mode Not used */ + +/* Thus if LED0 is statically on, NuttX has successfully booted and is, + * apparently, running normally. If LED1 is flashing at approximately + * 2Hz, then a fatal error has been detected and the system has halted. + * + * NOTE: That LED0 is not used after completion of booting and may + * be used by other board-specific logic. + */ + +/* Button definitions ***************************************************************/ +/* The XMC4500 Relax Lite v1 board has two buttons: + * + * BUTTON1 P1.14 Low input sensed when button pressed + * BUTTON2 P1.15 Low input sensed when button pressed + */ + +#define BUTTON_0 0 +#define BUTTON_1 1 +#define NUM_BUTTONS 2 + +#define BUTTON_0_BIT (1 << BUTTON_0) +#define BUTTON_1_BIT (1 << BUTTON_1) + /************************************************************************************ * Public Data ************************************************************************************/ diff --git a/configs/xmc4500-relax/src/xmc4500-relax.h b/configs/xmc4500-relax/src/xmc4500-relax.h index 6a004c82448..7934462b70e 100644 --- a/configs/xmc4500-relax/src/xmc4500-relax.h +++ b/configs/xmc4500-relax/src/xmc4500-relax.h @@ -46,9 +46,21 @@ * Pre-processor Definitions ****************************************************************************/ -/* LEDs */ +/* LEDs + * + * The XMC4500 Relax Lite v1 board has two LEDs: + * + * LED1 P1.1 High output illuminates + * LED2 P1.0 High output illuminates + */ -/* BUTTONS */ +/* BUTTONS + * + * The XMC4500 Relax Lite v1 board has two buttons: + * + * BUTTON1 P1.14 Low input sensed when button pressed + * BUTTON2 P1.15 Low input sensed when button pressed + */ /**************************************************************************** * Public Types From e67baffc15109ec38969113524961417a772f830 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 16 Mar 2017 13:04:01 -0600 Subject: [PATCH 13/81] XMC4xxx: Add partial USIC header file. --- arch/arm/src/xmc4/chip/xmc4_memorymap.h | 9 +- arch/arm/src/xmc4/chip/xmc4_usic.h | 475 ++++++++++++++++++++++++ 2 files changed, 481 insertions(+), 3 deletions(-) create mode 100644 arch/arm/src/xmc4/chip/xmc4_usic.h diff --git a/arch/arm/src/xmc4/chip/xmc4_memorymap.h b/arch/arm/src/xmc4/chip/xmc4_memorymap.h index 19dd637ab59..c6d15f234f5 100644 --- a/arch/arm/src/xmc4/chip/xmc4_memorymap.h +++ b/arch/arm/src/xmc4/chip/xmc4_memorymap.h @@ -117,9 +117,10 @@ #define XMC4_CCU81_CC83_BASE 0x40024400 #define XMC4_POSIF0_BASE 0x40028000 #define XMC4_POSIF1_BASE 0x4002c000 -#define XMC4_USIC0_BASE 0x40030008 +#define XMC4_USIC0_BASE 0x40030000 #define XMC4_USIC0_CH0_BASE 0x40030000 #define XMC4_USIC0_CH1_BASE 0x40030200 +#define XMC4_USIC0_RAM_BASE 0x40030400 #define XMC4_ERU1_BASE 0x40044000 #define XMC4_PBA1_BASE 0x48000000 @@ -139,12 +140,14 @@ #define XMC4_CAN_MO_BASE 0x48015000 #define XMC4_DAC_BASE 0x48018000 #define XMC4_SDMMC_BASE 0x4801c000 +#define XMC4_USIC1_BASE 0x48020000 #define XMC4_USIC1_CH0_BASE 0x48020000 -#define XMC4_USIC1_BASE 0x48020008 #define XMC4_USIC1_CH1_BASE 0x48020200 +#define XMC4_USIC1_RAM_BASE 0x48020400 +#define XMC4_USIC2_BASE 0x48024000 #define XMC4_USIC2_CH0_BASE 0x48024000 -#define XMC4_USIC2_BASE 0x48024008 #define XMC4_USIC2_CH1_BASE 0x48024200 +#define XMC4_USIC2_CH1_BASE 0x48024400 #define XMC4_PORT0_BASE 0x48028000 #define XMC4_PORT1_BASE 0x48028100 #define XMC4_PORT2_BASE 0x48028200 diff --git a/arch/arm/src/xmc4/chip/xmc4_usic.h b/arch/arm/src/xmc4/chip/xmc4_usic.h new file mode 100644 index 00000000000..089a14811fc --- /dev/null +++ b/arch/arm/src/xmc4/chip/xmc4_usic.h @@ -0,0 +1,475 @@ +/************************************************************************************ + * arch/arm/src/xmc4/chip/xmc4_usic.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Reference: XMC4500 Reference Manual V1.5 2014-07 Microcontrollers. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * May include some logic from sample code provided by Infineon: + * + * Copyright (C) 2011-2015 Infineon Technologies AG. All rights reserved. + * + * Infineon Technologies AG (Infineon) is supplying this software for use with + * Infineon's microcontrollers. This file can be freely distributed within + * development tools that are supporting such microcontrollers. + * + * THIS SOFTWARE IS PROVIDED AS IS. NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, + * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_XMC4_CHIP_XMC4_USIC_H +#define __ARCH_ARM_SRC_XMC4_CHIP_XMC4_USIC_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register Offsets *****************************************************************/ + +/* PMU Registers -- See ID register */ +/* Prefetch Registers -- See PCON register */ + +/* Kernal Registers */ + +#define XMC4_USIC_ID_OFFSET 0x0008 /* Kernel State Configuration Register */ + +/* USIC Channel Registers */ + +#define XMC4_USIC_CCFG_OFFSET 0x0004 /* Channel Configuration Register */ +#define XMC4_USIC_KSCFG_OFFSET 0x000c /* Kernel State Configuration Register */ +#define XMC4_USIC_FDR_OFFSET 0x0010 /* Fractional Divider Register */ +#define XMC4_USIC_BRG_OFFSET 0x0014 /* Baud Rate Generator Register */ +#define XMC4_USIC_INPR_OFFSET 0x0018 /* Interrupt Node Pointer Register */ +#define XMC4_USIC_DX0CR_OFFSET 0x001c /* Input Control Register 0 */ +#define XMC4_USIC_DX1CR_OFFSET 0x0020 /* Input Control Register 1 */ +#define XMC4_USIC_DX2CR_OFFSET 0x0024 /* Input Control Register 2 */ +#define XMC4_USIC_DX3CR_OFFSET 0x0028 /* Input Control Register 3 */ +#define XMC4_USIC_DX4CR_OFFSET 0x002c /* Input Control Register 4 */ +#define XMC4_USIC_DX5CR_OFFSET 0x0030 /* Input Control Register 5 */ +#define XMC4_USIC_SCTR_OFFSET 0x0034 /* Shift Control Register */ +#define XMC4_USIC_TCSR_OFFSET 0x0038 /* Transmit Control/Status Register */ +#define XMC4_USIC_PCR_OFFSET 0x003c /* Protocol Control Register */ +#define XMC4_USIC_CCR_OFFSET 0x0040 /* Channel Control Register */ +#define XMC4_USIC_CMTR_OFFSET 0x0044 /* Capture Mode Timer Register */ +#define XMC4_USIC_PSR_OFFSET 0x0048 /* Protocol Status Register */ +#define XMC4_USIC_PSCR_OFFSET 0x004c /* Protocol Status Clear Register */ +#define XMC4_USIC_RBUFSR_OFFSET 0x0050 /* Receiver Buffer Status Register */ +#define XMC4_USIC_RBUF_OFFSET 0x0054 /* Receiver Buffer Register */ +#define XMC4_USIC_RBUFD_OFFSET 0x0058 /* Receiver Buffer Register for Debugger */ +#define XMC4_USIC_RBUF0_OFFSET 0x005c /* Receiver Buffer Register 0 */ +#define XMC4_USIC_RBUF1_OFFSET 0x0060 /* Receiver Buffer Register 1 */ +#define XMC4_USIC_RBUF01SR_OFFSET 0x0064 /* Receiver Buffer 01 Status Register */ +#define XMC4_USIC_FMR_OFFSET 0x0068 /* Flag Modification Register */ +#define XMC4_USIC_TBUF_OFFSET 0x0080 /* Transmit Buffer (32 x 4-bytes) */ + +/* USIC FIFO Registers */ + +#define XMC4_USIC_BYP_OFFSET 0x0100 /* Bypass Data Register */ +#define XMC4_USIC_BYPCR_OFFSET 0x0104 /* Bypass Control Register */ +#define XMC4_USIC_TBCTR_OFFSET 0x0108 /* Transmitter Buffer Control Register */ +#define XMC4_USIC_RBCTR_OFFSET 0x010c /* Receiver Buffer Control Register */ +#define XMC4_USIC_TRBPTR_OFFSET 0x0110 /* Transmit/Receive Buffer Pointer Register */ +#define XMC4_USIC_TRBSR_OFFSET 0x0114 /* Transmit/Receive Buffer Status Register */ +#define XMC4_USIC_TRBSCR_OFFSET 0x0118 /* Transmit/Receive Buffer Status Clear Register */ +#define XMC4_USIC_OUTR_OFFSET 0x011c /* Receiver Buffer Output Register */ +#define XMC4_USIC_OUTDR_OFFSET 0x0120 /* Receiver Buffer Output Register L for Debugger */ +#define XMC4_USIC_IN_OFFSET 0x0180 /* Transmit FIFO Buffer (32 x 4-bytes) */ + +/* Register Addresses ****************************************************************/ + +/* USIC0 Registers */ +/* Kernal Registers */ + +#define XMC4_USIC0_ID (XMC4_USIC0_BASE+XMC4_USIC_ID_OFFSET) + +/* USIC0 Channel 0 Registers */ + +#define XMC4_USIC00_CCFG (XMC4_USIC0_CH0_BASE+XMC4_USIC_CCFG_OFFSET) +#define XMC4_USIC00_KSCFG (XMC4_USIC0_CH0_BASE+XMC4_USIC_KSCFG_OFFSET) +#define XMC4_USIC00_FDR (XMC4_USIC0_CH0_BASE+XMC4_USIC_FDR_OFFSET) +#define XMC4_USIC00_BRG (XMC4_USIC0_CH0_BASE+XMC4_USIC_BRG_OFFSET) +#define XMC4_USIC00_INPR (XMC4_USIC0_CH0_BASE+XMC4_USIC_INPR_OFFSET) +#define XMC4_USIC00_DX0CR (XMC4_USIC0_CH0_BASE+XMC4_USIC_DX0CR_OFFSET) +#define XMC4_USIC00_DX1CR (XMC4_USIC0_CH0_BASE+XMC4_USIC_DX1CR_OFFSET) +#define XMC4_USIC00_DX2CR (XMC4_USIC0_CH0_BASE+XMC4_USIC_DX2CR_OFFSET) +#define XMC4_USIC00_DX3CR (XMC4_USIC0_CH0_BASE+XMC4_USIC_DX3CR_OFFSET) +#define XMC4_USIC00_DX4CR (XMC4_USIC0_CH0_BASE+XMC4_USIC_DX4CR_OFFSET) +#define XMC4_USIC00_DX5CR (XMC4_USIC0_CH0_BASE+XMC4_USIC_DX5CR_OFFSET) +#define XMC4_USIC00_SCTR (XMC4_USIC0_CH0_BASE+XMC4_USIC_SCTR_OFFSET) +#define XMC4_USIC00_TCSR (XMC4_USIC0_CH0_BASE+XMC4_USIC_TCSR_OFFSET) +#define XMC4_USIC00_PCR (XMC4_USIC0_CH0_BASE+XMC4_USIC_PCR_OFFSET) +#define XMC4_USIC00_CCR (XMC4_USIC0_CH0_BASE+XMC4_USIC_CCR_OFFSET) +#define XMC4_USIC00_CMTR (XMC4_USIC0_CH0_BASE+XMC4_USIC_CMTR_OFFSET) +#define XMC4_USIC00_PSR (XMC4_USIC0_CH0_BASE+XMC4_USIC_PSR_OFFSET) +#define XMC4_USIC00_PSCR (XMC4_USIC0_CH0_BASE+XMC4_USIC_PSCR_OFFSET) +#define XMC4_USIC00_RBUFSR (XMC4_USIC0_CH0_BASE+XMC4_USIC_RBUFSR_OFFSET) +#define XMC4_USIC00_RBUF (XMC4_USIC0_CH0_BASE+XMC4_USIC_RBUF_OFFSET) +#define XMC4_USIC00_RBUFD (XMC4_USIC0_CH0_BASE+XMC4_USIC_RBUFD_OFFSET) +#define XMC4_USIC00_RBUF0 (XMC4_USIC0_CH0_BASE+XMC4_USIC_RBUF0_OFFSET) +#define XMC4_USIC00_RBUF1 (XMC4_USIC0_CH0_BASE+XMC4_USIC_RBUF1_OFFSET) +#define XMC4_USIC00_RBUF01SR (XMC4_USIC0_CH0_BASE+XMC4_USIC_RBUF01SR_OFFSET) +#define XMC4_USIC00_FMR (XMC4_USIC0_CH0_BASE+XMC4_USIC_FMR_OFFSET) +#define XMC4_USIC00_TBUF (XMC4_USIC0_CH0_BASE+XMC4_USIC_TBUF_OFFSET) + +/* USIC0 Channel 0 FIFO Registers */ + +#define XMC4_USIC00_BYP (XMC4_USIC0_CH0_BASE+XMC4_USIC_BYP_OFFSET) +#define XMC4_USIC00_BYPCR (XMC4_USIC0_CH0_BASE+XMC4_USIC_BYPCR_OFFSET) +#define XMC4_USIC00_TBCTR (XMC4_USIC0_CH0_BASE+XMC4_USIC_TBCTR_OFFSET) +#define XMC4_USIC00_RBCTR (XMC4_USIC0_CH0_BASE+XMC4_USIC_RBCTR_OFFSET) +#define XMC4_USIC00_TRBPTR (XMC4_USIC0_CH0_BASE+XMC4_USIC_TRBPTR_OFFSET) +#define XMC4_USIC00_TRBSR (XMC4_USIC0_CH0_BASE+XMC4_USIC_TRBSR_OFFSET) +#define XMC4_USIC00_TRBSCR (XMC4_USIC0_CH0_BASE+XMC4_USIC_TRBSCR_OFFSET) +#define XMC4_USIC00_OUTR (XMC4_USIC0_CH0_BASE+XMC4_USIC_OUTR_OFFSET) +#define XMC4_USIC00_OUTDR (XMC4_USIC0_CH0_BASE+XMC4_USIC_OUTDR_OFFSET) +#define XMC4_USIC00_IN (XMC4_USIC0_CH0_BASE+XMC4_USIC_IN_OFFSET) + +/* USIC0 Channel 1 Registers */ + +#define XMC4_USIC01_CCFG (XMC4_USIC0_CH1_BASE+XMC4_USIC_CCFG_OFFSET) +#define XMC4_USIC01_KSCFG (XMC4_USIC0_CH1_BASE+XMC4_USIC_KSCFG_OFFSET) +#define XMC4_USIC01_FDR (XMC4_USIC0_CH1_BASE+XMC4_USIC_FDR_OFFSET) +#define XMC4_USIC01_BRG (XMC4_USIC0_CH1_BASE+XMC4_USIC_BRG_OFFSET) +#define XMC4_USIC01_INPR (XMC4_USIC0_CH1_BASE+XMC4_USIC_INPR_OFFSET) +#define XMC4_USIC01_DX0CR (XMC4_USIC0_CH1_BASE+XMC4_USIC_DX0CR_OFFSET) +#define XMC4_USIC01_DX1CR (XMC4_USIC0_CH1_BASE+XMC4_USIC_DX1CR_OFFSET) +#define XMC4_USIC01_DX2CR (XMC4_USIC0_CH1_BASE+XMC4_USIC_DX2CR_OFFSET) +#define XMC4_USIC01_DX3CR (XMC4_USIC0_CH1_BASE+XMC4_USIC_DX3CR_OFFSET) +#define XMC4_USIC01_DX4CR (XMC4_USIC0_CH1_BASE+XMC4_USIC_DX4CR_OFFSET) +#define XMC4_USIC01_DX5CR (XMC4_USIC0_CH1_BASE+XMC4_USIC_DX5CR_OFFSET) +#define XMC4_USIC01_SCTR (XMC4_USIC0_CH1_BASE+XMC4_USIC_SCTR_OFFSET) +#define XMC4_USIC01_TCSR (XMC4_USIC0_CH1_BASE+XMC4_USIC_TCSR_OFFSET) +#define XMC4_USIC01_PCR (XMC4_USIC0_CH1_BASE+XMC4_USIC_PCR_OFFSET) +#define XMC4_USIC01_CCR (XMC4_USIC0_CH1_BASE+XMC4_USIC_CCR_OFFSET) +#define XMC4_USIC01_CMTR (XMC4_USIC0_CH1_BASE+XMC4_USIC_CMTR_OFFSET) +#define XMC4_USIC01_PSR (XMC4_USIC0_CH1_BASE+XMC4_USIC_PSR_OFFSET) +#define XMC4_USIC01_PSCR (XMC4_USIC0_CH1_BASE+XMC4_USIC_PSCR_OFFSET) +#define XMC4_USIC01_RBUFSR (XMC4_USIC0_CH1_BASE+XMC4_USIC_RBUFSR_OFFSET) +#define XMC4_USIC01_RBUF (XMC4_USIC0_CH1_BASE+XMC4_USIC_RBUF_OFFSET) +#define XMC4_USIC01_RBUFD (XMC4_USIC0_CH1_BASE+XMC4_USIC_RBUFD_OFFSET) +#define XMC4_USIC01_RBUF0 (XMC4_USIC0_CH1_BASE+XMC4_USIC_RBUF0_OFFSET) +#define XMC4_USIC01_RBUF1 (XMC4_USIC0_CH1_BASE+XMC4_USIC_RBUF1_OFFSET) +#define XMC4_USIC01_RBUF01SR (XMC4_USIC0_CH1_BASE+XMC4_USIC_RBUF01SR_OFFSET) +#define XMC4_USIC01_FMR (XMC4_USIC0_CH1_BASE+XMC4_USIC_FMR_OFFSET) +#define XMC4_USIC01_TBUF (XMC4_USIC0_CH1_BASE+XMC4_USIC_TBUF_OFFSET) + +/* USIC0 Channel 1 FIFO Registers */ + +#define XMC4_USIC01_BYP (XMC4_USIC0_CH1_BASE+XMC4_USIC_BYP_OFFSET) +#define XMC4_USIC01_BYPCR (XMC4_USIC0_CH1_BASE+XMC4_USIC_BYPCR_OFFSET) +#define XMC4_USIC01_TBCTR (XMC4_USIC0_CH1_BASE+XMC4_USIC_TBCTR_OFFSET) +#define XMC4_USIC01_RBCTR (XMC4_USIC0_CH1_BASE+XMC4_USIC_RBCTR_OFFSET) +#define XMC4_USIC01_TRBPTR (XMC4_USIC0_CH1_BASE+XMC4_USIC_TRBPTR_OFFSET) +#define XMC4_USIC01_TRBSR (XMC4_USIC0_CH1_BASE+XMC4_USIC_TRBSR_OFFSET) +#define XMC4_USIC01_TRBSCR (XMC4_USIC0_CH1_BASE+XMC4_USIC_TRBSCR_OFFSET) +#define XMC4_USIC01_OUTR (XMC4_USIC0_CH1_BASE+XMC4_USIC_OUTR_OFFSET) +#define XMC4_USIC01_OUTDR (XMC4_USIC0_CH1_BASE+XMC4_USIC_OUTDR_OFFSET) +#define XMC4_USIC01_IN (XMC4_USIC0_CH1_BASE+XMC4_USIC_IN_OFFSET) + +/* USIC1 Registers */ +/* Kernal Registers */ + +#define XMC4_USIC1_ID (XMC4_USIC1_BASE+XMC4_USIC_ID_OFFSET) + +/* USIC1 Channel 0 Registers */ + +#define XMC4_USIC10_CCFG (XMC4_USIC1_CH0_BASE+XMC4_USIC_CCFG_OFFSET) +#define XMC4_USIC10_KSCFG (XMC4_USIC1_CH0_BASE+XMC4_USIC_KSCFG_OFFSET) +#define XMC4_USIC10_FDR (XMC4_USIC1_CH0_BASE+XMC4_USIC_FDR_OFFSET) +#define XMC4_USIC10_BRG (XMC4_USIC1_CH0_BASE+XMC4_USIC_BRG_OFFSET) +#define XMC4_USIC10_INPR (XMC4_USIC1_CH0_BASE+XMC4_USIC_INPR_OFFSET) +#define XMC4_USIC10_DX0CR (XMC4_USIC1_CH0_BASE+XMC4_USIC_DX0CR_OFFSET) +#define XMC4_USIC10_DX1CR (XMC4_USIC1_CH0_BASE+XMC4_USIC_DX1CR_OFFSET) +#define XMC4_USIC10_DX2CR (XMC4_USIC1_CH0_BASE+XMC4_USIC_DX2CR_OFFSET) +#define XMC4_USIC10_DX3CR (XMC4_USIC1_CH0_BASE+XMC4_USIC_DX3CR_OFFSET) +#define XMC4_USIC10_DX4CR (XMC4_USIC1_CH0_BASE+XMC4_USIC_DX4CR_OFFSET) +#define XMC4_USIC10_DX5CR (XMC4_USIC1_CH0_BASE+XMC4_USIC_DX5CR_OFFSET) +#define XMC4_USIC10_SCTR (XMC4_USIC1_CH0_BASE+XMC4_USIC_SCTR_OFFSET) +#define XMC4_USIC10_TCSR (XMC4_USIC1_CH0_BASE+XMC4_USIC_TCSR_OFFSET) +#define XMC4_USIC10_PCR (XMC4_USIC1_CH0_BASE+XMC4_USIC_PCR_OFFSET) +#define XMC4_USIC10_CCR (XMC4_USIC1_CH0_BASE+XMC4_USIC_CCR_OFFSET) +#define XMC4_USIC10_CMTR (XMC4_USIC1_CH0_BASE+XMC4_USIC_CMTR_OFFSET) +#define XMC4_USIC10_PSR (XMC4_USIC1_CH0_BASE+XMC4_USIC_PSR_OFFSET) +#define XMC4_USIC10_PSCR (XMC4_USIC1_CH0_BASE+XMC4_USIC_PSCR_OFFSET) +#define XMC4_USIC10_RBUFSR (XMC4_USIC1_CH0_BASE+XMC4_USIC_RBUFSR_OFFSET) +#define XMC4_USIC10_RBUF (XMC4_USIC1_CH0_BASE+XMC4_USIC_RBUF_OFFSET) +#define XMC4_USIC10_RBUFD (XMC4_USIC1_CH0_BASE+XMC4_USIC_RBUFD_OFFSET) +#define XMC4_USIC10_RBUF0 (XMC4_USIC1_CH0_BASE+XMC4_USIC_RBUF0_OFFSET) +#define XMC4_USIC10_RBUF1 (XMC4_USIC1_CH0_BASE+XMC4_USIC_RBUF1_OFFSET) +#define XMC4_USIC10_RBUF01SR (XMC4_USIC1_CH0_BASE+XMC4_USIC_RBUF01SR_OFFSET) +#define XMC4_USIC10_FMR (XMC4_USIC1_CH0_BASE+XMC4_USIC_FMR_OFFSET) +#define XMC4_USIC10_TBUF (XMC4_USIC1_CH0_BASE+XMC4_USIC_TBUF_OFFSET) + +/* USIC1 Channel 0 FIFO Registers */ + +#define XMC4_USIC10_BYP (XMC4_USIC1_CH0_BASE+XMC4_USIC_BYP_OFFSET) +#define XMC4_USIC10_BYPCR (XMC4_USIC1_CH0_BASE+XMC4_USIC_BYPCR_OFFSET) +#define XMC4_USIC10_TBCTR (XMC4_USIC1_CH0_BASE+XMC4_USIC_TBCTR_OFFSET) +#define XMC4_USIC10_RBCTR (XMC4_USIC1_CH0_BASE+XMC4_USIC_RBCTR_OFFSET) +#define XMC4_USIC10_TRBPTR (XMC4_USIC1_CH0_BASE+XMC4_USIC_TRBPTR_OFFSET) +#define XMC4_USIC10_TRBSR (XMC4_USIC1_CH0_BASE+XMC4_USIC_TRBSR_OFFSET) +#define XMC4_USIC10_TRBSCR (XMC4_USIC1_CH0_BASE+XMC4_USIC_TRBSCR_OFFSET) +#define XMC4_USIC10_OUTR (XMC4_USIC1_CH0_BASE+XMC4_USIC_OUTR_OFFSET) +#define XMC4_USIC10_OUTDR (XMC4_USIC1_CH0_BASE+XMC4_USIC_OUTDR_OFFSET) +#define XMC4_USIC10_IN (XMC4_USIC1_CH0_BASE+XMC4_USIC_IN_OFFSET) + +/* USIC1 Channel 1 Registers */ + +#define XMC4_USCI11_CCFG (XMC4_USIC1_CH1_BASE+XMC4_USIC_CCFG_OFFSET) +#define XMC4_USCI11_KSCFG (XMC4_USIC1_CH1_BASE+XMC4_USIC_KSCFG_OFFSET) +#define XMC4_USCI11_FDR (XMC4_USIC1_CH1_BASE+XMC4_USIC_FDR_OFFSET) +#define XMC4_USCI11_BRG (XMC4_USIC1_CH1_BASE+XMC4_USIC_BRG_OFFSET) +#define XMC4_USCI11_INPR (XMC4_USIC1_CH1_BASE+XMC4_USIC_INPR_OFFSET) +#define XMC4_USCI11_DX0CR (XMC4_USIC1_CH1_BASE+XMC4_USIC_DX0CR_OFFSET) +#define XMC4_USCI11_DX1CR (XMC4_USIC1_CH1_BASE+XMC4_USIC_DX1CR_OFFSET) +#define XMC4_USCI11_DX2CR (XMC4_USIC1_CH1_BASE+XMC4_USIC_DX2CR_OFFSET) +#define XMC4_USCI11_DX3CR (XMC4_USIC1_CH1_BASE+XMC4_USIC_DX3CR_OFFSET) +#define XMC4_USCI11_DX4CR (XMC4_USIC1_CH1_BASE+XMC4_USIC_DX4CR_OFFSET) +#define XMC4_USCI11_DX5CR (XMC4_USIC1_CH1_BASE+XMC4_USIC_DX5CR_OFFSET) +#define XMC4_USCI11_SCTR (XMC4_USIC1_CH1_BASE+XMC4_USIC_SCTR_OFFSET) +#define XMC4_USCI11_TCSR (XMC4_USIC1_CH1_BASE+XMC4_USIC_TCSR_OFFSET) +#define XMC4_USCI11_PCR (XMC4_USIC1_CH1_BASE+XMC4_USIC_PCR_OFFSET) +#define XMC4_USCI11_CCR (XMC4_USIC1_CH1_BASE+XMC4_USIC_CCR_OFFSET) +#define XMC4_USCI11_CMTR (XMC4_USIC1_CH1_BASE+XMC4_USIC_CMTR_OFFSET) +#define XMC4_USCI11_PSR (XMC4_USIC1_CH1_BASE+XMC4_USIC_PSR_OFFSET) +#define XMC4_USCI11_PSCR (XMC4_USIC1_CH1_BASE+XMC4_USIC_PSCR_OFFSET) +#define XMC4_USCI11_RBUFSR (XMC4_USIC1_CH1_BASE+XMC4_USIC_RBUFSR_OFFSET) +#define XMC4_USCI11_RBUF (XMC4_USIC1_CH1_BASE+XMC4_USIC_RBUF_OFFSET) +#define XMC4_USCI11_RBUFD (XMC4_USIC1_CH1_BASE+XMC4_USIC_RBUFD_OFFSET) +#define XMC4_USCI11_RBUF0 (XMC4_USIC1_CH1_BASE+XMC4_USIC_RBUF0_OFFSET) +#define XMC4_USCI11_RBUF1 (XMC4_USIC1_CH1_BASE+XMC4_USIC_RBUF1_OFFSET) +#define XMC4_USCI11_RBUF01SR (XMC4_USIC1_CH1_BASE+XMC4_USIC_RBUF01SR_OFFSET) +#define XMC4_USCI11_FMR (XMC4_USIC1_CH1_BASE+XMC4_USIC_FMR_OFFSET) +#define XMC4_USCI11_TBUF (XMC4_USIC1_CH1_BASE+XMC4_USIC_TBUF_OFFSET) + +/* USIC1 Channel 1 FIFO Registers */ + +#define XMC4_USCI11_BYP (XMC4_USIC1_CH1_BASE+XMC4_USIC_BYP_OFFSET) +#define XMC4_USCI11_BYPCR (XMC4_USIC1_CH1_BASE+XMC4_USIC_BYPCR_OFFSET) +#define XMC4_USCI11_TBCTR (XMC4_USIC1_CH1_BASE+XMC4_USIC_TBCTR_OFFSET) +#define XMC4_USCI11_RBCTR (XMC4_USIC1_CH1_BASE+XMC4_USIC_RBCTR_OFFSET) +#define XMC4_USCI11_TRBPTR (XMC4_USIC1_CH1_BASE+XMC4_USIC_TRBPTR_OFFSET) +#define XMC4_USCI11_TRBSR (XMC4_USIC1_CH1_BASE+XMC4_USIC_TRBSR_OFFSET) +#define XMC4_USCI11_TRBSCR (XMC4_USIC1_CH1_BASE+XMC4_USIC_TRBSCR_OFFSET) +#define XMC4_USCI11_OUTR (XMC4_USIC1_CH1_BASE+XMC4_USIC_OUTR_OFFSET) +#define XMC4_USCI11_OUTDR (XMC4_USIC1_CH1_BASE+XMC4_USIC_OUTDR_OFFSET) +#define XMC4_USCI11_IN (XMC4_USIC1_CH1_BASE+XMC4_USIC_IN_OFFSET) + +/* USCI2 Registers */ +/* Kernal Registers */ + +#define XMC4_USCI2_ID (XMC4_USCI2_BASE+XMC4_USIC_ID_OFFSET) + +/* USCI2 Channel 0 Registers */ + +#define XMC4_USCI20_CCFG (XMC4_USCI2_CH0_BASE+XMC4_USIC_CCFG_OFFSET) +#define XMC4_USCI20_KSCFG (XMC4_USCI2_CH0_BASE+XMC4_USIC_KSCFG_OFFSET) +#define XMC4_USCI20_FDR (XMC4_USCI2_CH0_BASE+XMC4_USIC_FDR_OFFSET) +#define XMC4_USCI20_BRG (XMC4_USCI2_CH0_BASE+XMC4_USIC_BRG_OFFSET) +#define XMC4_USCI20_INPR (XMC4_USCI2_CH0_BASE+XMC4_USIC_INPR_OFFSET) +#define XMC4_USCI20_DX0CR (XMC4_USCI2_CH0_BASE+XMC4_USIC_DX0CR_OFFSET) +#define XMC4_USCI20_DX1CR (XMC4_USCI2_CH0_BASE+XMC4_USIC_DX1CR_OFFSET) +#define XMC4_USCI20_DX2CR (XMC4_USCI2_CH0_BASE+XMC4_USIC_DX2CR_OFFSET) +#define XMC4_USCI20_DX3CR (XMC4_USCI2_CH0_BASE+XMC4_USIC_DX3CR_OFFSET) +#define XMC4_USCI20_DX4CR (XMC4_USCI2_CH0_BASE+XMC4_USIC_DX4CR_OFFSET) +#define XMC4_USCI20_DX5CR (XMC4_USCI2_CH0_BASE+XMC4_USIC_DX5CR_OFFSET) +#define XMC4_USCI20_SCTR (XMC4_USCI2_CH0_BASE+XMC4_USIC_SCTR_OFFSET) +#define XMC4_USCI20_TCSR (XMC4_USCI2_CH0_BASE+XMC4_USIC_TCSR_OFFSET) +#define XMC4_USCI20_PCR (XMC4_USCI2_CH0_BASE+XMC4_USIC_PCR_OFFSET) +#define XMC4_USCI20_CCR (XMC4_USCI2_CH0_BASE+XMC4_USIC_CCR_OFFSET) +#define XMC4_USCI20_CMTR (XMC4_USCI2_CH0_BASE+XMC4_USIC_CMTR_OFFSET) +#define XMC4_USCI20_PSR (XMC4_USCI2_CH0_BASE+XMC4_USIC_PSR_OFFSET) +#define XMC4_USCI20_PSCR (XMC4_USCI2_CH0_BASE+XMC4_USIC_PSCR_OFFSET) +#define XMC4_USCI20_RBUFSR (XMC4_USCI2_CH0_BASE+XMC4_USIC_RBUFSR_OFFSET) +#define XMC4_USCI20_RBUF (XMC4_USCI2_CH0_BASE+XMC4_USIC_RBUF_OFFSET) +#define XMC4_USCI20_RBUFD (XMC4_USCI2_CH0_BASE+XMC4_USIC_RBUFD_OFFSET) +#define XMC4_USCI20_RBUF0 (XMC4_USCI2_CH0_BASE+XMC4_USIC_RBUF0_OFFSET) +#define XMC4_USCI20_RBUF1 (XMC4_USCI2_CH0_BASE+XMC4_USIC_RBUF1_OFFSET) +#define XMC4_USCI20_RBUF01SR (XMC4_USCI2_CH0_BASE+XMC4_USIC_RBUF01SR_OFFSET) +#define XMC4_USCI20_FMR (XMC4_USCI2_CH0_BASE+XMC4_USIC_FMR_OFFSET) +#define XMC4_USCI20_TBUF (XMC4_USCI2_CH0_BASE+XMC4_USIC_TBUF_OFFSET) + +/* USCI2 Channel 0 FIFO Registers */ + +#define XMC4_USCI20_BYP (XMC4_USCI2_CH0_BASE+XMC4_USIC_BYP_OFFSET) +#define XMC4_USCI20_BYPCR (XMC4_USCI2_CH0_BASE+XMC4_USIC_BYPCR_OFFSET) +#define XMC4_USCI20_TBCTR (XMC4_USCI2_CH0_BASE+XMC4_USIC_TBCTR_OFFSET) +#define XMC4_USCI20_RBCTR (XMC4_USCI2_CH0_BASE+XMC4_USIC_RBCTR_OFFSET) +#define XMC4_USCI20_TRBPTR (XMC4_USCI2_CH0_BASE+XMC4_USIC_TRBPTR_OFFSET) +#define XMC4_USCI20_TRBSR (XMC4_USCI2_CH0_BASE+XMC4_USIC_TRBSR_OFFSET) +#define XMC4_USCI20_TRBSCR (XMC4_USCI2_CH0_BASE+XMC4_USIC_TRBSCR_OFFSET) +#define XMC4_USCI20_OUTR (XMC4_USCI2_CH0_BASE+XMC4_USIC_OUTR_OFFSET) +#define XMC4_USCI20_OUTDR (XMC4_USCI2_CH0_BASE+XMC4_USIC_OUTDR_OFFSET) +#define XMC4_USCI20_IN (XMC4_USCI2_CH0_BASE+XMC4_USIC_IN_OFFSET) + +/* USCI2 Channel 1 Registers */ + +#define XMC4_USCI21_CCFG (XMC4_USCI2_CH1_BASE+XMC4_USIC_CCFG_OFFSET) +#define XMC4_USCI21_KSCFG (XMC4_USCI2_CH1_BASE+XMC4_USIC_KSCFG_OFFSET) +#define XMC4_USCI21_FDR (XMC4_USCI2_CH1_BASE+XMC4_USIC_FDR_OFFSET) +#define XMC4_USCI21_BRG (XMC4_USCI2_CH1_BASE+XMC4_USIC_BRG_OFFSET) +#define XMC4_USCI21_INPR (XMC4_USCI2_CH1_BASE+XMC4_USIC_INPR_OFFSET) +#define XMC4_USCI21_DX0CR (XMC4_USCI2_CH1_BASE+XMC4_USIC_DX0CR_OFFSET) +#define XMC4_USCI21_DX1CR (XMC4_USCI2_CH1_BASE+XMC4_USIC_DX1CR_OFFSET) +#define XMC4_USCI21_DX2CR (XMC4_USCI2_CH1_BASE+XMC4_USIC_DX2CR_OFFSET) +#define XMC4_USCI21_DX3CR (XMC4_USCI2_CH1_BASE+XMC4_USIC_DX3CR_OFFSET) +#define XMC4_USCI21_DX4CR (XMC4_USCI2_CH1_BASE+XMC4_USIC_DX4CR_OFFSET) +#define XMC4_USCI21_DX5CR (XMC4_USCI2_CH1_BASE+XMC4_USIC_DX5CR_OFFSET) +#define XMC4_USCI21_SCTR (XMC4_USCI2_CH1_BASE+XMC4_USIC_SCTR_OFFSET) +#define XMC4_USCI21_TCSR (XMC4_USCI2_CH1_BASE+XMC4_USIC_TCSR_OFFSET) +#define XMC4_USCI21_PCR (XMC4_USCI2_CH1_BASE+XMC4_USIC_PCR_OFFSET) +#define XMC4_USCI21_CCR (XMC4_USCI2_CH1_BASE+XMC4_USIC_CCR_OFFSET) +#define XMC4_USCI21_CMTR (XMC4_USCI2_CH1_BASE+XMC4_USIC_CMTR_OFFSET) +#define XMC4_USCI21_PSR (XMC4_USCI2_CH1_BASE+XMC4_USIC_PSR_OFFSET) +#define XMC4_USCI21_PSCR (XMC4_USCI2_CH1_BASE+XMC4_USIC_PSCR_OFFSET) +#define XMC4_USCI21_RBUFSR (XMC4_USCI2_CH1_BASE+XMC4_USIC_RBUFSR_OFFSET) +#define XMC4_USCI21_RBUF (XMC4_USCI2_CH1_BASE+XMC4_USIC_RBUF_OFFSET) +#define XMC4_USCI21_RBUFD (XMC4_USCI2_CH1_BASE+XMC4_USIC_RBUFD_OFFSET) +#define XMC4_USCI21_RBUF0 (XMC4_USCI2_CH1_BASE+XMC4_USIC_RBUF0_OFFSET) +#define XMC4_USCI21_RBUF1 (XMC4_USCI2_CH1_BASE+XMC4_USIC_RBUF1_OFFSET) +#define XMC4_USCI21_RBUF01SR (XMC4_USCI2_CH1_BASE+XMC4_USIC_RBUF01SR_OFFSET) +#define XMC4_USCI21_FMR (XMC4_USCI2_CH1_BASE+XMC4_USIC_FMR_OFFSET) +#define XMC4_USCI21_TBUF (XMC4_USCI2_CH1_BASE+XMC4_USIC_TBUF_OFFSET) + +/* USCI2 Channel 1 FIFO Registers */ + +#define XMC4_USCI21_BYP (XMC4_USCI2_CH1_BASE+XMC4_USIC_BYP_OFFSET) +#define XMC4_USCI21_BYPCR (XMC4_USCI2_CH1_BASE+XMC4_USIC_BYPCR_OFFSET) +#define XMC4_USCI21_TBCTR (XMC4_USCI2_CH1_BASE+XMC4_USIC_TBCTR_OFFSET) +#define XMC4_USCI21_RBCTR (XMC4_USCI2_CH1_BASE+XMC4_USIC_RBCTR_OFFSET) +#define XMC4_USCI21_TRBPTR (XMC4_USCI2_CH1_BASE+XMC4_USIC_TRBPTR_OFFSET) +#define XMC4_USCI21_TRBSR (XMC4_USCI2_CH1_BASE+XMC4_USIC_TRBSR_OFFSET) +#define XMC4_USCI21_TRBSCR (XMC4_USCI2_CH1_BASE+XMC4_USIC_TRBSCR_OFFSET) +#define XMC4_USCI21_OUTR (XMC4_USCI2_CH1_BASE+XMC4_USIC_OUTR_OFFSET) +#define XMC4_USCI21_OUTDR (XMC4_USCI2_CH1_BASE+XMC4_USIC_OUTDR_OFFSET) +#define XMC4_USCI21_IN (XMC4_USCI2_CH1_BASE+XMC4_USIC_IN_OFFSET) + +/* Register Bit-Field Definitions **************************************************/ + +/* Kernal Registers */ +/* Kernel State Configuration Register */ + +#define USIC_ID_MOD_REV_SHIFT (0) /* Bits 0-7: Module Revision Number */ +#define USIC_ID_MOD_REV_MASK (0xff << USIC_ID_MOD_REV_SHIFT) +#define USIC_ID_MOD_TYPE_SHIFT (8) /* Bits 8-15: Module Type */ +#define USIC_ID_MOD_TYPE_MASK (0xff << USIC_ID_MOD_REV_SHIFT) +#define USIC_ID_MOD_NUMBER_SHIFT (16) /* Bits 16-31: Module Number Value */ +#define USIC_ID_MOD_NUMBER_MASK (0xffff << USIC_ID_MOD_NUMBER_SHIFT) + +/* USIC Channel Registers */ + +/* Channel Configuration Register */ +#define USIC_CCFG_ +/* Kernel State Configuration Register */ +#define USIC_KSCFG_ +/* Fractional Divider Register */ +#define USIC_FDR_ +/* Baud Rate Generator Register */ +#define USIC_BRG_ +/* Interrupt Node Pointer Register */ +#define USIC_INPR_ +/* Input Control Register 0 */ +#define USIC_DX0CR_ +/* Input Control Register 1 */ +#define USIC_DX1CR_ +/* Input Control Register 2 */ +#define USIC_DX2CR_ +/* Input Control Register 3 */ +#define USIC_DX3CR_ +/* Input Control Register 4 */ +#define USIC_DX4CR_ +/* Input Control Register 5 */ +#define USIC_DX5CR_ +/* Shift Control Register */ +#define USIC_SCTR_ +/* Transmit Control/Status Register */ +#define USIC_TCSR_ +/* Protocol Control Register */ +#define USIC_PCR_ +/* Channel Control Register */ +#define USIC_CCR_ +/* Capture Mode Timer Register */ +#define USIC_CMTR_ +/* Protocol Status Register */ +#define USIC_PSR_ +/* Protocol Status Clear Register */ +#define USIC_PSCR_ +/* Receiver Buffer Status Register */ +#define USIC_RBUFSR_ +/* Receiver Buffer Register */ +#define USIC_RBUF_ +/* Receiver Buffer Register for Debugger */ +#define USIC_RBUFD_ +/* Receiver Buffer Register 0 */ +#define USIC_RBUF0_ +/* Receiver Buffer Register 1 */ +#define USIC_RBUF1_ +/* Receiver Buffer 01 Status Register */ +#define USIC_RBUF01SR_ +/* Flag Modification Register */ +#define USIC_FMR_ +/* Transmit Buffer (32 x 4-bytes) */ +#define USIC_TBUF_ + +/* USIC FIFO Registers */ + +/* Bypass Data Register */ +#define USIC_BYP_ +/* Bypass Control Register */ +#define USIC_BYPCR_ +/* Transmitter Buffer Control Register */ +#define USIC_TBCTR_ +/* Receiver Buffer Control Register */ +#define USIC_RBCTR_ +/* Transmit/Receive Buffer Pointer Register */ +#define USIC_TRBPTR_ +/* Transmit/Receive Buffer Status Register */ +#define USIC_TRBSR_ +/* Transmit/Receive Buffer Status Clear Register */ +#define USIC_TRBSCR_ +/* Receiver Buffer Output Register */ +#define USIC_OUTR_ +/* Receiver Buffer Output Register L for Debugger */ +#define USIC_OUTDR_ +/* Transmit FIFO Buffer (32 x 4-bytes) */ +#define USIC_IN_ + +#endif /* __ARCH_ARM_SRC_XMC4_CHIP_XMC4_SCU_H */ From e30e47683bb23c45e0b029303bef28eabf895611 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 16 Mar 2017 13:24:32 -0600 Subject: [PATCH 14/81] XMC4xxx: Add partial PORTS header file. --- arch/arm/src/xmc4/chip/xmc4_ports.h | 279 ++++++++++++++++++++++++++++ 1 file changed, 279 insertions(+) create mode 100644 arch/arm/src/xmc4/chip/xmc4_ports.h diff --git a/arch/arm/src/xmc4/chip/xmc4_ports.h b/arch/arm/src/xmc4/chip/xmc4_ports.h new file mode 100644 index 00000000000..9bfa067eca2 --- /dev/null +++ b/arch/arm/src/xmc4/chip/xmc4_ports.h @@ -0,0 +1,279 @@ +/************************************************************************************ + * arch/arm/src/xmc4/chip/xmc4_ports.h + * + * Copyright (C /*2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Reference: XMC4500 Reference Manual V1.5 2014-07 Microcontrollers. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION /*HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE /*ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * May include some logic from sample code provided by Infineon: + * + * Copyright (C /*2011-2015 Infineon Technologies AG. All rights reserved. + * + * Infineon Technologies AG (Infineon /*is supplying this software for use with + * Infineon's microcontrollers. This file can be freely distributed within + * development tools that are supporting such microcontrollers. + * + * THIS SOFTWARE IS PROVIDED AS IS. NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, + * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_XMC4_CHIP_XMC4_PORTS_H +#define __ARCH_ARM_SRC_XMC4_CHIP_XMC4_PORTS_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register Offsets *****************************************************************/ + +/* PORTS Registers */ + +#define XMC4_PORTS_OUT_OFFSET 0x0000 /* Port Output Register */ +#define XMC4_PORTS_OMR_OFFSET 0x0004 /* Port Output Modification Register */ +#define XMC4_PORTS_IOCR0_OFFSET 0x0010 /* Port Input/Output Control Register 0 */ +#define XMC4_PORTS_IOCR4_OFFSET 0x0014 /* Port Input/Output Control Register 4 */ +#define XMC4_PORTS_IOCR8_OFFSET 0x0018 /* Port Input/Output Control Register 8 */ +#define XMC4_PORTS_IOCR12_OFFSET 0x001c /* Port Input/Output Control Register 12 */ +#define XMC4_PORTS_IN_OFFSET 0x0024 /* Port Input Register */ +#define XMC4_PORTS_PDR0_OFFSET 0x0040 /* Port Pad Driver Mode 0 Register */ +#define XMC4_PORTS_PDR1_OFFSET 0x0044 /* Port Pad Driver Mode 1 Register */ +#define XMC4_PORTS_PDISC_OFFSET 0x0060 /* Port Pin Function Decision Control Register */ +#define XMC4_PORTS_PPS_OFFSET 0x0070 /* Port Pin Power Save Register */ +#define XMC4_PORTS_HWSEL_OFFSET 0x0074 /* Port Pin Hardware Select Register */ + +/* Register Addresses ****************************************************************/ +#define 0x48028000 +#define XMC4_PORT1_BASE 0x48028100 +#define XMC4_PORT2_BASE 0x48028200 +#define XMC4_PORT3_BASE 0x48028300 +#define XMC4_PORT4_BASE 0x48028400 +#define XMC4_PORT5_BASE 0x48028500 +#define XMC4_PORT6_BASE 0x48028600 +#define XMC4_PORT7_BASE 0x48028700 +#define XMC4_PORT8_BASE 0x48028800 +#define XMC4_PORT9_BASE 0x48028900 +#define XMC4_PORT14_BASE 0x48028e00 +#define XMC4_PORT15_BASE 0x48028f00 + +#define XMC4_PORT0_OUT (XMC4_PORT0_BASE+XMC4_PORTS_OUT_OFFSET) +#define XMC4_PORT0_OMR (XMC4_PORT0_BASE+XMC4_PORTS_OMR_OFFSET) +#define XMC4_PORT0_IOCR0 (XMC4_PORT0_BASE+XMC4_PORTS_IOCR0_OFFSET) +#define XMC4_PORT0_IOCR4 (XMC4_PORT0_BASE+XMC4_PORTS_IOCR4_OFFSET) +#define XMC4_PORT0_IOCR8 (XMC4_PORT0_BASE+XMC4_PORTS_IOCR8_OFFSET) +#define XMC4_PORT0_IOCR12 (XMC4_PORT0_BASE+XMC4_PORTS_IOCR12_OFFSET) +#define XMC4_PORT0_IN (XMC4_PORT0_BASE+XMC4_PORTS_IN_OFFSET) +#define XMC4_PORT0_PDR0 (XMC4_PORT0_BASE+XMC4_PORTS_PDR0_OFFSET) +#define XMC4_PORT0_PDR1 (XMC4_PORT0_BASE+XMC4_PORTS_PDR1_OFFSET) +#define XMC4_PORT0_PDISC (XMC4_PORT0_BASE+XMC4_PORTS_PDISC_OFFSET) +#define XMC4_PORT0_PPS (XMC4_PORT0_BASE+XMC4_PORTS_PPS_OFFSET) +#define XMC4_PORT0_HWSEL (XMC4_PORT0_BASE+XMC4_PORTS_HWSEL_OFFSET) + +#define XMC4_PORT1_OUT (XMC4_PORT1_BASE+XMC4_PORTS_OUT_OFFSET) +#define XMC4_PORT1_OMR (XMC4_PORT1_BASE+XMC4_PORTS_OMR_OFFSET) +#define XMC4_PORT1_IOCR0 (XMC4_PORT1_BASE+XMC4_PORTS_IOCR0_OFFSET) +#define XMC4_PORT1_IOCR4 (XMC4_PORT1_BASE+XMC4_PORTS_IOCR4_OFFSET) +#define XMC4_PORT1_IOCR8 (XMC4_PORT1_BASE+XMC4_PORTS_IOCR8_OFFSET) +#define XMC4_PORT1_IOCR12 (XMC4_PORT1_BASE+XMC4_PORTS_IOCR12_OFFSET) +#define XMC4_PORT1_IN (XMC4_PORT1_BASE+XMC4_PORTS_IN_OFFSET) +#define XMC4_PORT1_PDR0 (XMC4_PORT1_BASE+XMC4_PORTS_PDR0_OFFSET) +#define XMC4_PORT1_PDR1 (XMC4_PORT1_BASE+XMC4_PORTS_PDR1_OFFSET) +#define XMC4_PORT1_PDISC (XMC4_PORT1_BASE+XMC4_PORTS_PDISC_OFFSET) +#define XMC4_PORT1_PPS (XMC4_PORT1_BASE+XMC4_PORTS_PPS_OFFSET) +#define XMC4_PORT1_HWSEL (XMC4_PORT1_BASE+XMC4_PORTS_HWSEL_OFFSET) + +#define XMC4_PORT2_OUT (XMC4_PORT2_BASE+XMC4_PORTS_OUT_OFFSET) +#define XMC4_PORT2_OMR (XMC4_PORT2_BASE+XMC4_PORTS_OMR_OFFSET) +#define XMC4_PORT2_IOCR0 (XMC4_PORT2_BASE+XMC4_PORTS_IOCR0_OFFSET) +#define XMC4_PORT2_IOCR4 (XMC4_PORT2_BASE+XMC4_PORTS_IOCR4_OFFSET) +#define XMC4_PORT2_IOCR8 (XMC4_PORT2_BASE+XMC4_PORTS_IOCR8_OFFSET) +#define XMC4_PORT2_IOCR12 (XMC4_PORT2_BASE+XMC4_PORTS_IOCR12_OFFSET) +#define XMC4_PORT2_IN (XMC4_PORT2_BASE+XMC4_PORTS_IN_OFFSET) +#define XMC4_PORT2_PDR0 (XMC4_PORT2_BASE+XMC4_PORTS_PDR0_OFFSET) +#define XMC4_PORT2_PDR1 (XMC4_PORT2_BASE+XMC4_PORTS_PDR1_OFFSET) +#define XMC4_PORT2_PDISC (XMC4_PORT2_BASE+XMC4_PORTS_PDISC_OFFSET) +#define XMC4_PORT2_PPS (XMC4_PORT2_BASE+XMC4_PORTS_PPS_OFFSET) +#define XMC4_PORT2_HWSEL (XMC4_PORT2_BASE+XMC4_PORTS_HWSEL_OFFSET) + +#define XMC4_PORT3_OUT (XMC4_PORT3_BASE+XMC4_PORTS_OUT_OFFSET) +#define XMC4_PORT3_OMR (XMC4_PORT3_BASE+XMC4_PORTS_OMR_OFFSET) +#define XMC4_PORT3_IOCR0 (XMC4_PORT3_BASE+XMC4_PORTS_IOCR0_OFFSET) +#define XMC4_PORT3_IOCR4 (XMC4_PORT3_BASE+XMC4_PORTS_IOCR4_OFFSET) +#define XMC4_PORT3_IOCR8 (XMC4_PORT3_BASE+XMC4_PORTS_IOCR8_OFFSET) +#define XMC4_PORT3_IOCR12 (XMC4_PORT3_BASE+XMC4_PORTS_IOCR12_OFFSET) +#define XMC4_PORT3_IN (XMC4_PORT3_BASE+XMC4_PORTS_IN_OFFSET) +#define XMC4_PORT3_PDR0 (XMC4_PORT3_BASE+XMC4_PORTS_PDR0_OFFSET) +#define XMC4_PORT3_PDR1 (XMC4_PORT3_BASE+XMC4_PORTS_PDR1_OFFSET) +#define XMC4_PORT3_PDISC (XMC4_PORT3_BASE+XMC4_PORTS_PDISC_OFFSET) +#define XMC4_PORT3_PPS (XMC4_PORT3_BASE+XMC4_PORTS_PPS_OFFSET) +#define XMC4_PORT3_HWSEL (XMC4_PORT3_BASE+XMC4_PORTS_HWSEL_OFFSET) + +#define XMC4_PORT4_OUT (XMC4_PORT4_BASE+XMC4_PORTS_OUT_OFFSET) +#define XMC4_PORT4_OMR (XMC4_PORT4_BASE+XMC4_PORTS_OMR_OFFSET) +#define XMC4_PORT4_IOCR0 (XMC4_PORT4_BASE+XMC4_PORTS_IOCR0_OFFSET) +#define XMC4_PORT4_IOCR4 (XMC4_PORT4_BASE+XMC4_PORTS_IOCR4_OFFSET) +#define XMC4_PORT4_IOCR8 (XMC4_PORT4_BASE+XMC4_PORTS_IOCR8_OFFSET) +#define XMC4_PORT4_IOCR12 (XMC4_PORT4_BASE+XMC4_PORTS_IOCR12_OFFSET) +#define XMC4_PORT4_IN (XMC4_PORT4_BASE+XMC4_PORTS_IN_OFFSET) +#define XMC4_PORT4_PDR0 (XMC4_PORT4_BASE+XMC4_PORTS_PDR0_OFFSET) +#define XMC4_PORT4_PDR1 (XMC4_PORT4_BASE+XMC4_PORTS_PDR1_OFFSET) +#define XMC4_PORT4_PDISC (XMC4_PORT4_BASE+XMC4_PORTS_PDISC_OFFSET) +#define XMC4_PORT4_PPS (XMC4_PORT4_BASE+XMC4_PORTS_PPS_OFFSET) +#define XMC4_PORT4_HWSEL (XMC4_PORT4_BASE+XMC4_PORTS_HWSEL_OFFSET) + +#define XMC4_PORT5_OUT (XMC4_PORT5_BASE+XMC4_PORTS_OUT_OFFSET) +#define XMC4_PORT5_OMR (XMC4_PORT5_BASE+XMC4_PORTS_OMR_OFFSET) +#define XMC4_PORT5_IOCR0 (XMC4_PORT5_BASE+XMC4_PORTS_IOCR0_OFFSET) +#define XMC4_PORT5_IOCR4 (XMC4_PORT5_BASE+XMC4_PORTS_IOCR4_OFFSET) +#define XMC4_PORT5_IOCR8 (XMC4_PORT5_BASE+XMC4_PORTS_IOCR8_OFFSET) +#define XMC4_PORT5_IOCR12 (XMC4_PORT5_BASE+XMC4_PORTS_IOCR12_OFFSET) +#define XMC4_PORT5_IN (XMC4_PORT5_BASE+XMC4_PORTS_IN_OFFSET) +#define XMC4_PORT5_PDR0 (XMC4_PORT5_BASE+XMC4_PORTS_PDR0_OFFSET) +#define XMC4_PORT5_PDR1 (XMC4_PORT5_BASE+XMC4_PORTS_PDR1_OFFSET) +#define XMC4_PORT5_PDISC (XMC4_PORT5_BASE+XMC4_PORTS_PDISC_OFFSET) +#define XMC4_PORT5_PPS (XMC4_PORT5_BASE+XMC4_PORTS_PPS_OFFSET) +#define XMC4_PORT5_HWSEL (XMC4_PORT5_BASE+XMC4_PORTS_HWSEL_OFFSET) + +#define XMC4_PORT6_OUT (XMC4_PORT6_BASE+XMC4_PORTS_OUT_OFFSET) +#define XMC4_PORT6_OMR (XMC4_PORT6_BASE+XMC4_PORTS_OMR_OFFSET) +#define XMC4_PORT6_IOCR0 (XMC4_PORT6_BASE+XMC4_PORTS_IOCR0_OFFSET) +#define XMC4_PORT6_IOCR4 (XMC4_PORT6_BASE+XMC4_PORTS_IOCR4_OFFSET) +#define XMC4_PORT6_IOCR8 (XMC4_PORT6_BASE+XMC4_PORTS_IOCR8_OFFSET) +#define XMC4_PORT6_IOCR12 (XMC4_PORT6_BASE+XMC4_PORTS_IOCR12_OFFSET) +#define XMC4_PORT6_IN (XMC4_PORT6_BASE+XMC4_PORTS_IN_OFFSET) +#define XMC4_PORT6_PDR0 (XMC4_PORT6_BASE+XMC4_PORTS_PDR0_OFFSET) +#define XMC4_PORT6_PDR1 (XMC4_PORT6_BASE+XMC4_PORTS_PDR1_OFFSET) +#define XMC4_PORT6_PDISC (XMC4_PORT6_BASE+XMC4_PORTS_PDISC_OFFSET) +#define XMC4_PORT6_PPS (XMC4_PORT6_BASE+XMC4_PORTS_PPS_OFFSET) +#define XMC4_PORT6_HWSEL (XMC4_PORT6_BASE+XMC4_PORTS_HWSEL_OFFSET) + +#define XMC4_PORT7_OUT (XMC4_PORT7_BASE+XMC4_PORTS_OUT_OFFSET) +#define XMC4_PORT7_OMR (XMC4_PORT7_BASE+XMC4_PORTS_OMR_OFFSET) +#define XMC4_PORT7_IOCR0 (XMC4_PORT7_BASE+XMC4_PORTS_IOCR0_OFFSET) +#define XMC4_PORT7_IOCR4 (XMC4_PORT7_BASE+XMC4_PORTS_IOCR4_OFFSET) +#define XMC4_PORT7_IOCR8 (XMC4_PORT7_BASE+XMC4_PORTS_IOCR8_OFFSET) +#define XMC4_PORT7_IOCR12 (XMC4_PORT7_BASE+XMC4_PORTS_IOCR12_OFFSET) +#define XMC4_PORT7_IN (XMC4_PORT7_BASE+XMC4_PORTS_IN_OFFSET) +#define XMC4_PORT7_PDR0 (XMC4_PORT7_BASE+XMC4_PORTS_PDR0_OFFSET) +#define XMC4_PORT7_PDR1 (XMC4_PORT7_BASE+XMC4_PORTS_PDR1_OFFSET) +#define XMC4_PORT7_PDISC (XMC4_PORT7_BASE+XMC4_PORTS_PDISC_OFFSET) +#define XMC4_PORT7_PPS (XMC4_PORT7_BASE+XMC4_PORTS_PPS_OFFSET) +#define XMC4_PORT7_HWSEL (XMC4_PORT7_BASE+XMC4_PORTS_HWSEL_OFFSET) + +#define XMC4_PORT8_OUT (XMC4_PORT8_BASE+XMC4_PORTS_OUT_OFFSET) +#define XMC4_PORT8_OMR (XMC4_PORT8_BASE+XMC4_PORTS_OMR_OFFSET) +#define XMC4_PORT8_IOCR0 (XMC4_PORT8_BASE+XMC4_PORTS_IOCR0_OFFSET) +#define XMC4_PORT8_IOCR4 (XMC4_PORT8_BASE+XMC4_PORTS_IOCR4_OFFSET) +#define XMC4_PORT8_IOCR8 (XMC4_PORT8_BASE+XMC4_PORTS_IOCR8_OFFSET) +#define XMC4_PORT8_IOCR12 (XMC4_PORT8_BASE+XMC4_PORTS_IOCR12_OFFSET) +#define XMC4_PORT8_IN (XMC4_PORT8_BASE+XMC4_PORTS_IN_OFFSET) +#define XMC4_PORT8_PDR0 (XMC4_PORT8_BASE+XMC4_PORTS_PDR0_OFFSET) +#define XMC4_PORT8_PDR1 (XMC4_PORT8_BASE+XMC4_PORTS_PDR1_OFFSET) +#define XMC4_PORT8_PDISC (XMC4_PORT8_BASE+XMC4_PORTS_PDISC_OFFSET) +#define XMC4_PORT8_PPS (XMC4_PORT8_BASE+XMC4_PORTS_PPS_OFFSET) +#define XMC4_PORT8_HWSEL (XMC4_PORT8_BASE+XMC4_PORTS_HWSEL_OFFSET) + +#define XMC4_PORT9_OUT (XMC4_PORT9_BASE+XMC4_PORTS_OUT_OFFSET) +#define XMC4_PORT9_OMR (XMC4_PORT9_BASE+XMC4_PORTS_OMR_OFFSET) +#define XMC4_PORT9_IOCR0 (XMC4_PORT9_BASE+XMC4_PORTS_IOCR0_OFFSET) +#define XMC4_PORT9_IOCR4 (XMC4_PORT9_BASE+XMC4_PORTS_IOCR4_OFFSET) +#define XMC4_PORT9_IOCR8 (XMC4_PORT9_BASE+XMC4_PORTS_IOCR8_OFFSET) +#define XMC4_PORT9_IOCR12 (XMC4_PORT9_BASE+XMC4_PORTS_IOCR12_OFFSET) +#define XMC4_PORT9_IN (XMC4_PORT9_BASE+XMC4_PORTS_IN_OFFSET) +#define XMC4_PORT9_PDR0 (XMC4_PORT9_BASE+XMC4_PORTS_PDR0_OFFSET) +#define XMC4_PORT9_PDR1 (XMC4_PORT9_BASE+XMC4_PORTS_PDR1_OFFSET) +#define XMC4_PORT9_PDISC (XMC4_PORT9_BASE+XMC4_PORTS_PDISC_OFFSET) +#define XMC4_PORT9_PPS (XMC4_PORT9_BASE+XMC4_PORTS_PPS_OFFSET) +#define XMC4_PORT9_HWSEL (XMC4_PORT9_BASE+XMC4_PORTS_HWSEL_OFFSET) + +#define XMC4_PORT14_OUT (XMC4_PORT14_BASE+XMC4_PORTS_OUT_OFFSET) +#define XMC4_PORT14_OMR (XMC4_PORT14_BASE+XMC4_PORTS_OMR_OFFSET) +#define XMC4_PORT14_IOCR0 (XMC4_PORT14_BASE+XMC4_PORTS_IOCR0_OFFSET) +#define XMC4_PORT14_IOCR4 (XMC4_PORT14_BASE+XMC4_PORTS_IOCR4_OFFSET) +#define XMC4_PORT14_IOCR8 (XMC4_PORT14_BASE+XMC4_PORTS_IOCR8_OFFSET) +#define XMC4_PORT14_IOCR12 (XMC4_PORT14_BASE+XMC4_PORTS_IOCR12_OFFSET) +#define XMC4_PORT14_IN (XMC4_PORT14_BASE+XMC4_PORTS_IN_OFFSET) +#define XMC4_PORT14_PDR0 (XMC4_PORT14_BASE+XMC4_PORTS_PDR0_OFFSET) +#define XMC4_PORT14_PDR1 (XMC4_PORT14_BASE+XMC4_PORTS_PDR1_OFFSET) +#define XMC4_PORT14_PDISC (XMC4_PORT14_BASE+XMC4_PORTS_PDISC_OFFSET) +#define XMC4_PORT14_PPS (XMC4_PORT14_BASE+XMC4_PORTS_PPS_OFFSET) +#define XMC4_PORT14_HWSEL (XMC4_PORT14_BASE+XMC4_PORTS_HWSEL_OFFSET) + +#define XMC4_PORT15_OUT (XMC4_PORT15_BASE+XMC4_PORTS_OUT_OFFSET) +#define XMC4_PORT15_OMR (XMC4_PORT15_BASE+XMC4_PORTS_OMR_OFFSET) +#define XMC4_PORT15_IOCR0 (XMC4_PORT15_BASE+XMC4_PORTS_IOCR0_OFFSET) +#define XMC4_PORT15_IOCR4 (XMC4_PORT15_BASE+XMC4_PORTS_IOCR4_OFFSET) +#define XMC4_PORT15_IOCR8 (XMC4_PORT15_BASE+XMC4_PORTS_IOCR8_OFFSET) +#define XMC4_PORT15_IOCR12 (XMC4_PORT15_BASE+XMC4_PORTS_IOCR12_OFFSET) +#define XMC4_PORT15_IN (XMC4_PORT15_BASE+XMC4_PORTS_IN_OFFSET) +#define XMC4_PORT15_PDR0 (XMC4_PORT15_BASE+XMC4_PORTS_PDR0_OFFSET) +#define XMC4_PORT15_PDR1 (XMC4_PORT15_BASE+XMC4_PORTS_PDR1_OFFSET) +#define XMC4_PORT15_PDISC (XMC4_PORT15_BASE+XMC4_PORTS_PDISC_OFFSET) +#define XMC4_PORT15_PPS (XMC4_PORT15_BASE+XMC4_PORTS_PPS_OFFSET) +#define XMC4_PORT15_HWSEL (XMC4_PORT15_BASE+XMC4_PORTS_HWSEL_OFFSET) + +/* Register Bit-Field Definitions **************************************************/ + +/* Port Output Register */ +#define PORTS_OUT_ +/* Port Output Modification Register */ +#define PORTS_OMR_ +/* Port Input/Output Control Register 0 */ +#define PORTS_IOCR0_ +/* Port Input/Output Control Register 4 */ +#define PORTS_IOCR4_ +/* Port Input/Output Control Register 8 */ +#define PORTS_IOCR8_ +/* Port Input/Output Control Register 12 */ +#define PORTS_IOCR12_ +/* Port Input Register */ +#define PORTS_IN_ +/* Port Pad Driver Mode 0 Register */ +#define PORTS_PDR0_ +/* Port Pad Driver Mode 1 Register */ +#define PORTS_PDR1_ +/* Port Pin Function Decision Control Register */ +#define PORTS_PDISC_ +/* Port Pin Power Save Register */ +#define PORTS_PPS_ +/* Port Pin Hardware Select Register */ +#define PORTS_HWSEL_ + +#endif /* __ARCH_ARM_SRC_XMC4_CHIP_XMC4_SCU_H */ From 6b167122c0e82f55f95b1037c1f63eb3fdc99c32 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 16 Mar 2017 14:26:22 -0600 Subject: [PATCH 15/81] XMC4xxx: Move clock utility functions from xmc4_clocconfig.c to new xmc4_clockutils.c --- arch/arm/src/xmc4/Make.defs | 6 +- arch/arm/src/xmc4/chip/xmc4_memorymap.h | 2 +- arch/arm/src/xmc4/xmc4_clockconfig.c | 84 ------------- arch/arm/src/xmc4/xmc4_clockutils.c | 150 ++++++++++++++++++++++++ 4 files changed, 154 insertions(+), 88 deletions(-) create mode 100644 arch/arm/src/xmc4/xmc4_clockutils.c diff --git a/arch/arm/src/xmc4/Make.defs b/arch/arm/src/xmc4/Make.defs index 79497388a49..63998a71336 100644 --- a/arch/arm/src/xmc4/Make.defs +++ b/arch/arm/src/xmc4/Make.defs @@ -110,9 +110,9 @@ endif CHIP_ASRCS = -CHIP_CSRCS = xmc4_allocateheap.c xmc4_clockconfig.c xmc4_clrpend.c -CHIP_CSRCS += xmc4_idle.c xmc4_irq.c xmc4_lowputc.c xmc4_gpio.c -CHIP_CSRCS += xmc4_serialinit.c xmc4_serial.c xmc4_start.c xmc4_uid.c +CHIP_CSRCS = xmc4_allocateheap.c xmc4_clockconfig.c xmc4_clockutils.c +CHIP_CSRCS += xmc4_clrpend.c xmc4_idle.c xmc4_irq.c xmc4_lowputc.c +CHIP_CSRCS += xmc4_gpio.c xmc4_serial.c xmc4_start.c # Configuration-dependent Kinetis files diff --git a/arch/arm/src/xmc4/chip/xmc4_memorymap.h b/arch/arm/src/xmc4/chip/xmc4_memorymap.h index c6d15f234f5..c2b847d4e07 100644 --- a/arch/arm/src/xmc4/chip/xmc4_memorymap.h +++ b/arch/arm/src/xmc4/chip/xmc4_memorymap.h @@ -147,7 +147,7 @@ #define XMC4_USIC2_BASE 0x48024000 #define XMC4_USIC2_CH0_BASE 0x48024000 #define XMC4_USIC2_CH1_BASE 0x48024200 -#define XMC4_USIC2_CH1_BASE 0x48024400 +#define XMC4_USIC2_RAM_BASE 0x48024400 #define XMC4_PORT0_BASE 0x48028000 #define XMC4_PORT1_BASE 0x48028100 #define XMC4_PORT2_BASE 0x48028200 diff --git a/arch/arm/src/xmc4/xmc4_clockconfig.c b/arch/arm/src/xmc4/xmc4_clockconfig.c index 26608a85b84..d663ea9f82d 100644 --- a/arch/arm/src/xmc4/xmc4_clockconfig.c +++ b/arch/arm/src/xmc4/xmc4_clockconfig.c @@ -529,87 +529,3 @@ void xmc4_clock_configure(void) putreg32(CLKSET_VALUE, XMC4_SCU_CLKSET); } - -/**************************************************************************** - * Name: xmc4_get_coreclock - * - * Description: - * Return the current core clock frequency (fCPU). - * - ****************************************************************************/ - -uint32_t xmc4_get_coreclock(void) -{ - uint32_t pdiv; - uint32_t ndiv; - uint32_t kdiv; - uint32_t sysdiv; - uint32_t regval; - uint32_t temp; - - if ((getreg32(XMC4_SCU_SYSCLKCR) & SCU_SYSCLKCR_SYSSEL) != 0) - { - /* fPLL is clock source for fSYS */ - - if ((getreg32(XMC4_SCU_PLLCON2) & SCU_PLLCON2_PINSEL) != 0) - { - /* PLL input clock is the backup clock (fOFI) */ - - temp = OFI_FREQUENCY; - } - else - { - /* PLL input clock is the high performance oscillator (fOSCHP); - * Only board specific logic knows this value. - */ - - temp = BOARD_XTAL_FREQUENCY; - } - - /* Check if PLL is locked */ - - regval = getreg32(XMC4_SCU_PLLSTAT); - if ((regval & SCU_PLLSTAT_VCOLOCK) != 0) - { - /* PLL normal mode */ - - regval = getreg32(XMC4_SCU_PLLCON1); - pdiv = ((regval & SCU_PLLCON1_PDIV_MASK) >> SCU_PLLCON1_PDIV_SHIFT) + 1; - ndiv = ((regval & SCU_PLLCON1_NDIV_MASK) >> SCU_PLLCON1_NDIV_SHIFT) + 1; - kdiv = ((regval & SCU_PLLCON1_K2DIV_MASK) >> SCU_PLLCON1_K2DIV_SHIFT) + 1; - - temp = (temp / (pdiv * kdiv)) * ndiv; - } - else - { - /* PLL prescalar mode */ - - regval = getreg32(XMC4_SCU_PLLCON1); - kdiv = ((regval & SCU_PLLCON1_K1DIV_MASK) >> SCU_PLLCON1_K1DIV_SHIFT) + 1; - - temp = (temp / kdiv); - } - } - else - { - /* fOFI is clock source for fSYS */ - - temp = OFI_FREQUENCY; - } - - /* Divide by SYSDIV to get fSYS */ - - regval = getreg32(XMC4_SCU_SYSCLKCR); - sysdiv = ((regval & SCU_SYSCLKCR_SYSDIV_MASK) >> SCU_SYSCLKCR_SYSDIV_SHIFT) + 1; - temp = temp / sysdiv; - - /* Check if the fSYS clock is divided by two to produce fCPU clock. */ - - regval = getreg32(XMC4_SCU_CPUCLKCR); - if ((regval & SCU_CPUCLKCR_CPUDIV) != 0) - { - temp = temp >> 1; - } - - return temp; -} diff --git a/arch/arm/src/xmc4/xmc4_clockutils.c b/arch/arm/src/xmc4/xmc4_clockutils.c new file mode 100644 index 00000000000..cf9649099ed --- /dev/null +++ b/arch/arm/src/xmc4/xmc4_clockutils.c @@ -0,0 +1,150 @@ +/**************************************************************************** + * arch/arm/src/xmc4/xmc4_clockutils.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * + * Reference: XMC4500 Reference Manual V1.5 2014-07 Microcontrollers. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * May include some logic from sample code provided by Infineon: + * + * Copyright (C) 2011-2015 Infineon Technologies AG. All rights reserved. + * + * Infineon Technologies AG (Infineon) is supplying this software for use with + * Infineon's microcontrollers. This file can be freely distributed within + * development tools that are supporting such microcontrollers. + * + * THIS SOFTWARE IS PROVIDED AS IS. NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, + * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "up_arch.h" +#include "chip/xmc4_scu.h" +#include "xmc4_clockconfig.h" + +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: xmc4_get_coreclock + * + * Description: + * Return the current core clock frequency (fCPU). + * + ****************************************************************************/ + +uint32_t xmc4_get_coreclock(void) +{ + uint32_t pdiv; + uint32_t ndiv; + uint32_t kdiv; + uint32_t sysdiv; + uint32_t regval; + uint32_t temp; + + if ((getreg32(XMC4_SCU_SYSCLKCR) & SCU_SYSCLKCR_SYSSEL) != 0) + { + /* fPLL is clock source for fSYS */ + + if ((getreg32(XMC4_SCU_PLLCON2) & SCU_PLLCON2_PINSEL) != 0) + { + /* PLL input clock is the backup clock (fOFI) */ + + temp = OFI_FREQUENCY; + } + else + { + /* PLL input clock is the high performance oscillator (fOSCHP); + * Only board specific logic knows this value. + */ + + temp = BOARD_XTAL_FREQUENCY; + } + + /* Check if PLL is locked */ + + regval = getreg32(XMC4_SCU_PLLSTAT); + if ((regval & SCU_PLLSTAT_VCOLOCK) != 0) + { + /* PLL normal mode */ + + regval = getreg32(XMC4_SCU_PLLCON1); + pdiv = ((regval & SCU_PLLCON1_PDIV_MASK) >> SCU_PLLCON1_PDIV_SHIFT) + 1; + ndiv = ((regval & SCU_PLLCON1_NDIV_MASK) >> SCU_PLLCON1_NDIV_SHIFT) + 1; + kdiv = ((regval & SCU_PLLCON1_K2DIV_MASK) >> SCU_PLLCON1_K2DIV_SHIFT) + 1; + + temp = (temp / (pdiv * kdiv)) * ndiv; + } + else + { + /* PLL prescalar mode */ + + regval = getreg32(XMC4_SCU_PLLCON1); + kdiv = ((regval & SCU_PLLCON1_K1DIV_MASK) >> SCU_PLLCON1_K1DIV_SHIFT) + 1; + + temp = (temp / kdiv); + } + } + else + { + /* fOFI is clock source for fSYS */ + + temp = OFI_FREQUENCY; + } + + /* Divide by SYSDIV to get fSYS */ + + regval = getreg32(XMC4_SCU_SYSCLKCR); + sysdiv = ((regval & SCU_SYSCLKCR_SYSDIV_MASK) >> SCU_SYSCLKCR_SYSDIV_SHIFT) + 1; + temp = temp / sysdiv; + + /* Check if the fSYS clock is divided by two to produce fCPU clock. */ + + regval = getreg32(XMC4_SCU_CPUCLKCR); + if ((regval & SCU_CPUCLKCR_CPUDIV) != 0) + { + temp = temp >> 1; + } + + return temp; +} From 7601a27cee348f70bebcac95e8e8372fe0651bbf Mon Sep 17 00:00:00 2001 From: David Sidrane Date: Thu, 16 Mar 2017 14:16:18 -1000 Subject: [PATCH 16/81] sem_holder:The logic for the list version is unchanged --- sched/semaphore/sem_holder.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/sched/semaphore/sem_holder.c b/sched/semaphore/sem_holder.c index bca4b4429bf..bc5c186e6bf 100644 --- a/sched/semaphore/sem_holder.c +++ b/sched/semaphore/sem_holder.c @@ -672,13 +672,17 @@ static int sem_restoreholderprioB(FAR struct semholder_s *pholder, if (pholder->htcb == rtcb) { - /* The running task has given up a count on the semaphore - * Release the holder if all counts have been given up. - * before reprioritizing causes a context switch. + /* The running task has given up a count on the semaphore */ + +#if CONFIG_SEM_PREALLOCHOLDERS == 0 + /* In the case where there are only 2 holders. This step + * is necessary to insure we have space. Release the holder + * if all counts have been given up. before reprioritizing + * causes a context switch. */ sem_findandfreeholder(sem, rtcb); - +#endif (void)sem_restoreholderprio(rtcb, sem, arg); return 1; } From f672478e7ea1a0248c1a1068d43eba486bed954a Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 17 Mar 2017 08:12:21 -0600 Subject: [PATCH 17/81] XMC4xxx: Completes the PORT register definition header file. --- arch/arm/src/xmc4/chip/xmc4_ports.h | 568 +++++++++++++++++++--------- 1 file changed, 383 insertions(+), 185 deletions(-) diff --git a/arch/arm/src/xmc4/chip/xmc4_ports.h b/arch/arm/src/xmc4/chip/xmc4_ports.h index 9bfa067eca2..1d6cfa6b428 100644 --- a/arch/arm/src/xmc4/chip/xmc4_ports.h +++ b/arch/arm/src/xmc4/chip/xmc4_ports.h @@ -66,214 +66,412 @@ /* PORTS Registers */ -#define XMC4_PORTS_OUT_OFFSET 0x0000 /* Port Output Register */ -#define XMC4_PORTS_OMR_OFFSET 0x0004 /* Port Output Modification Register */ -#define XMC4_PORTS_IOCR0_OFFSET 0x0010 /* Port Input/Output Control Register 0 */ -#define XMC4_PORTS_IOCR4_OFFSET 0x0014 /* Port Input/Output Control Register 4 */ -#define XMC4_PORTS_IOCR8_OFFSET 0x0018 /* Port Input/Output Control Register 8 */ -#define XMC4_PORTS_IOCR12_OFFSET 0x001c /* Port Input/Output Control Register 12 */ -#define XMC4_PORTS_IN_OFFSET 0x0024 /* Port Input Register */ -#define XMC4_PORTS_PDR0_OFFSET 0x0040 /* Port Pad Driver Mode 0 Register */ -#define XMC4_PORTS_PDR1_OFFSET 0x0044 /* Port Pad Driver Mode 1 Register */ -#define XMC4_PORTS_PDISC_OFFSET 0x0060 /* Port Pin Function Decision Control Register */ -#define XMC4_PORTS_PPS_OFFSET 0x0070 /* Port Pin Power Save Register */ -#define XMC4_PORTS_HWSEL_OFFSET 0x0074 /* Port Pin Hardware Select Register */ +#define XMC4_PORT_OUT_OFFSET 0x0000 /* Port Output Register */ +#define XMC4_PORT_OMR_OFFSET 0x0004 /* Port Output Modification Register */ +#define XMC4_PORT_IOCR0_OFFSET 0x0010 /* Port Input/Output Control Register 0 */ +#define XMC4_PORT_IOCR4_OFFSET 0x0014 /* Port Input/Output Control Register 4 */ +#define XMC4_PORT_IOCR8_OFFSET 0x0018 /* Port Input/Output Control Register 8 */ +#define XMC4_PORT_IOCR12_OFFSET 0x001c /* Port Input/Output Control Register 12 */ +#define XMC4_PORT_IN_OFFSET 0x0024 /* Port Input Register */ +#define XMC4_PORT_PDR0_OFFSET 0x0040 /* Port Pad Driver Mode 0 Register */ +#define XMC4_PORT_PDR1_OFFSET 0x0044 /* Port Pad Driver Mode 1 Register */ +#define XMC4_PORT_PDISC_OFFSET 0x0060 /* Port Pin Function Decision Control Register */ +#define XMC4_PORT_PPS_OFFSET 0x0070 /* Port Pin Power Save Register */ +#define XMC4_PORT_HWSEL_OFFSET 0x0074 /* Port Pin Hardware Select Register */ /* Register Addresses ****************************************************************/ -#define 0x48028000 -#define XMC4_PORT1_BASE 0x48028100 -#define XMC4_PORT2_BASE 0x48028200 -#define XMC4_PORT3_BASE 0x48028300 -#define XMC4_PORT4_BASE 0x48028400 -#define XMC4_PORT5_BASE 0x48028500 -#define XMC4_PORT6_BASE 0x48028600 -#define XMC4_PORT7_BASE 0x48028700 -#define XMC4_PORT8_BASE 0x48028800 -#define XMC4_PORT9_BASE 0x48028900 -#define XMC4_PORT14_BASE 0x48028e00 -#define XMC4_PORT15_BASE 0x48028f00 -#define XMC4_PORT0_OUT (XMC4_PORT0_BASE+XMC4_PORTS_OUT_OFFSET) -#define XMC4_PORT0_OMR (XMC4_PORT0_BASE+XMC4_PORTS_OMR_OFFSET) -#define XMC4_PORT0_IOCR0 (XMC4_PORT0_BASE+XMC4_PORTS_IOCR0_OFFSET) -#define XMC4_PORT0_IOCR4 (XMC4_PORT0_BASE+XMC4_PORTS_IOCR4_OFFSET) -#define XMC4_PORT0_IOCR8 (XMC4_PORT0_BASE+XMC4_PORTS_IOCR8_OFFSET) -#define XMC4_PORT0_IOCR12 (XMC4_PORT0_BASE+XMC4_PORTS_IOCR12_OFFSET) -#define XMC4_PORT0_IN (XMC4_PORT0_BASE+XMC4_PORTS_IN_OFFSET) -#define XMC4_PORT0_PDR0 (XMC4_PORT0_BASE+XMC4_PORTS_PDR0_OFFSET) -#define XMC4_PORT0_PDR1 (XMC4_PORT0_BASE+XMC4_PORTS_PDR1_OFFSET) -#define XMC4_PORT0_PDISC (XMC4_PORT0_BASE+XMC4_PORTS_PDISC_OFFSET) -#define XMC4_PORT0_PPS (XMC4_PORT0_BASE+XMC4_PORTS_PPS_OFFSET) -#define XMC4_PORT0_HWSEL (XMC4_PORT0_BASE+XMC4_PORTS_HWSEL_OFFSET) +#define XMC4_PORT0_OUT (XMC4_PORT0_BASE+XMC4_PORT_OUT_OFFSET) +#define XMC4_PORT0_OMR (XMC4_PORT0_BASE+XMC4_PORT_OMR_OFFSET) +#define XMC4_PORT0_IOCR0 (XMC4_PORT0_BASE+XMC4_PORT_IOCR0_OFFSET) +#define XMC4_PORT0_IOCR4 (XMC4_PORT0_BASE+XMC4_PORT_IOCR4_OFFSET) +#define XMC4_PORT0_IOCR8 (XMC4_PORT0_BASE+XMC4_PORT_IOCR8_OFFSET) +#define XMC4_PORT0_IOCR12 (XMC4_PORT0_BASE+XMC4_PORT_IOCR12_OFFSET) +#define XMC4_PORT0_IN (XMC4_PORT0_BASE+XMC4_PORT_IN_OFFSET) +#define XMC4_PORT0_PDR0 (XMC4_PORT0_BASE+XMC4_PORT_PDR0_OFFSET) +#define XMC4_PORT0_PDR1 (XMC4_PORT0_BASE+XMC4_PORT_PDR1_OFFSET) +#define XMC4_PORT0_PDISC (XMC4_PORT0_BASE+XMC4_PORT_PDISC_OFFSET) +#define XMC4_PORT0_PPS (XMC4_PORT0_BASE+XMC4_PORT_PPS_OFFSET) +#define XMC4_PORT0_HWSEL (XMC4_PORT0_BASE+XMC4_PORT_HWSEL_OFFSET) -#define XMC4_PORT1_OUT (XMC4_PORT1_BASE+XMC4_PORTS_OUT_OFFSET) -#define XMC4_PORT1_OMR (XMC4_PORT1_BASE+XMC4_PORTS_OMR_OFFSET) -#define XMC4_PORT1_IOCR0 (XMC4_PORT1_BASE+XMC4_PORTS_IOCR0_OFFSET) -#define XMC4_PORT1_IOCR4 (XMC4_PORT1_BASE+XMC4_PORTS_IOCR4_OFFSET) -#define XMC4_PORT1_IOCR8 (XMC4_PORT1_BASE+XMC4_PORTS_IOCR8_OFFSET) -#define XMC4_PORT1_IOCR12 (XMC4_PORT1_BASE+XMC4_PORTS_IOCR12_OFFSET) -#define XMC4_PORT1_IN (XMC4_PORT1_BASE+XMC4_PORTS_IN_OFFSET) -#define XMC4_PORT1_PDR0 (XMC4_PORT1_BASE+XMC4_PORTS_PDR0_OFFSET) -#define XMC4_PORT1_PDR1 (XMC4_PORT1_BASE+XMC4_PORTS_PDR1_OFFSET) -#define XMC4_PORT1_PDISC (XMC4_PORT1_BASE+XMC4_PORTS_PDISC_OFFSET) -#define XMC4_PORT1_PPS (XMC4_PORT1_BASE+XMC4_PORTS_PPS_OFFSET) -#define XMC4_PORT1_HWSEL (XMC4_PORT1_BASE+XMC4_PORTS_HWSEL_OFFSET) +#define XMC4_PORT1_OUT (XMC4_PORT1_BASE+XMC4_PORT_OUT_OFFSET) +#define XMC4_PORT1_OMR (XMC4_PORT1_BASE+XMC4_PORT_OMR_OFFSET) +#define XMC4_PORT1_IOCR0 (XMC4_PORT1_BASE+XMC4_PORT_IOCR0_OFFSET) +#define XMC4_PORT1_IOCR4 (XMC4_PORT1_BASE+XMC4_PORT_IOCR4_OFFSET) +#define XMC4_PORT1_IOCR8 (XMC4_PORT1_BASE+XMC4_PORT_IOCR8_OFFSET) +#define XMC4_PORT1_IOCR12 (XMC4_PORT1_BASE+XMC4_PORT_IOCR12_OFFSET) +#define XMC4_PORT1_IN (XMC4_PORT1_BASE+XMC4_PORT_IN_OFFSET) +#define XMC4_PORT1_PDR0 (XMC4_PORT1_BASE+XMC4_PORT_PDR0_OFFSET) +#define XMC4_PORT1_PDR1 (XMC4_PORT1_BASE+XMC4_PORT_PDR1_OFFSET) +#define XMC4_PORT1_PDISC (XMC4_PORT1_BASE+XMC4_PORT_PDISC_OFFSET) +#define XMC4_PORT1_PPS (XMC4_PORT1_BASE+XMC4_PORT_PPS_OFFSET) +#define XMC4_PORT1_HWSEL (XMC4_PORT1_BASE+XMC4_PORT_HWSEL_OFFSET) -#define XMC4_PORT2_OUT (XMC4_PORT2_BASE+XMC4_PORTS_OUT_OFFSET) -#define XMC4_PORT2_OMR (XMC4_PORT2_BASE+XMC4_PORTS_OMR_OFFSET) -#define XMC4_PORT2_IOCR0 (XMC4_PORT2_BASE+XMC4_PORTS_IOCR0_OFFSET) -#define XMC4_PORT2_IOCR4 (XMC4_PORT2_BASE+XMC4_PORTS_IOCR4_OFFSET) -#define XMC4_PORT2_IOCR8 (XMC4_PORT2_BASE+XMC4_PORTS_IOCR8_OFFSET) -#define XMC4_PORT2_IOCR12 (XMC4_PORT2_BASE+XMC4_PORTS_IOCR12_OFFSET) -#define XMC4_PORT2_IN (XMC4_PORT2_BASE+XMC4_PORTS_IN_OFFSET) -#define XMC4_PORT2_PDR0 (XMC4_PORT2_BASE+XMC4_PORTS_PDR0_OFFSET) -#define XMC4_PORT2_PDR1 (XMC4_PORT2_BASE+XMC4_PORTS_PDR1_OFFSET) -#define XMC4_PORT2_PDISC (XMC4_PORT2_BASE+XMC4_PORTS_PDISC_OFFSET) -#define XMC4_PORT2_PPS (XMC4_PORT2_BASE+XMC4_PORTS_PPS_OFFSET) -#define XMC4_PORT2_HWSEL (XMC4_PORT2_BASE+XMC4_PORTS_HWSEL_OFFSET) +#define XMC4_PORT2_OUT (XMC4_PORT2_BASE+XMC4_PORT_OUT_OFFSET) +#define XMC4_PORT2_OMR (XMC4_PORT2_BASE+XMC4_PORT_OMR_OFFSET) +#define XMC4_PORT2_IOCR0 (XMC4_PORT2_BASE+XMC4_PORT_IOCR0_OFFSET) +#define XMC4_PORT2_IOCR4 (XMC4_PORT2_BASE+XMC4_PORT_IOCR4_OFFSET) +#define XMC4_PORT2_IOCR8 (XMC4_PORT2_BASE+XMC4_PORT_IOCR8_OFFSET) +#define XMC4_PORT2_IOCR12 (XMC4_PORT2_BASE+XMC4_PORT_IOCR12_OFFSET) +#define XMC4_PORT2_IN (XMC4_PORT2_BASE+XMC4_PORT_IN_OFFSET) +#define XMC4_PORT2_PDR0 (XMC4_PORT2_BASE+XMC4_PORT_PDR0_OFFSET) +#define XMC4_PORT2_PDR1 (XMC4_PORT2_BASE+XMC4_PORT_PDR1_OFFSET) +#define XMC4_PORT2_PDISC (XMC4_PORT2_BASE+XMC4_PORT_PDISC_OFFSET) +#define XMC4_PORT2_PPS (XMC4_PORT2_BASE+XMC4_PORT_PPS_OFFSET) +#define XMC4_PORT2_HWSEL (XMC4_PORT2_BASE+XMC4_PORT_HWSEL_OFFSET) -#define XMC4_PORT3_OUT (XMC4_PORT3_BASE+XMC4_PORTS_OUT_OFFSET) -#define XMC4_PORT3_OMR (XMC4_PORT3_BASE+XMC4_PORTS_OMR_OFFSET) -#define XMC4_PORT3_IOCR0 (XMC4_PORT3_BASE+XMC4_PORTS_IOCR0_OFFSET) -#define XMC4_PORT3_IOCR4 (XMC4_PORT3_BASE+XMC4_PORTS_IOCR4_OFFSET) -#define XMC4_PORT3_IOCR8 (XMC4_PORT3_BASE+XMC4_PORTS_IOCR8_OFFSET) -#define XMC4_PORT3_IOCR12 (XMC4_PORT3_BASE+XMC4_PORTS_IOCR12_OFFSET) -#define XMC4_PORT3_IN (XMC4_PORT3_BASE+XMC4_PORTS_IN_OFFSET) -#define XMC4_PORT3_PDR0 (XMC4_PORT3_BASE+XMC4_PORTS_PDR0_OFFSET) -#define XMC4_PORT3_PDR1 (XMC4_PORT3_BASE+XMC4_PORTS_PDR1_OFFSET) -#define XMC4_PORT3_PDISC (XMC4_PORT3_BASE+XMC4_PORTS_PDISC_OFFSET) -#define XMC4_PORT3_PPS (XMC4_PORT3_BASE+XMC4_PORTS_PPS_OFFSET) -#define XMC4_PORT3_HWSEL (XMC4_PORT3_BASE+XMC4_PORTS_HWSEL_OFFSET) +#define XMC4_PORT3_OUT (XMC4_PORT3_BASE+XMC4_PORT_OUT_OFFSET) +#define XMC4_PORT3_OMR (XMC4_PORT3_BASE+XMC4_PORT_OMR_OFFSET) +#define XMC4_PORT3_IOCR0 (XMC4_PORT3_BASE+XMC4_PORT_IOCR0_OFFSET) +#define XMC4_PORT3_IOCR4 (XMC4_PORT3_BASE+XMC4_PORT_IOCR4_OFFSET) +#define XMC4_PORT3_IOCR8 (XMC4_PORT3_BASE+XMC4_PORT_IOCR8_OFFSET) +#define XMC4_PORT3_IOCR12 (XMC4_PORT3_BASE+XMC4_PORT_IOCR12_OFFSET) +#define XMC4_PORT3_IN (XMC4_PORT3_BASE+XMC4_PORT_IN_OFFSET) +#define XMC4_PORT3_PDR0 (XMC4_PORT3_BASE+XMC4_PORT_PDR0_OFFSET) +#define XMC4_PORT3_PDR1 (XMC4_PORT3_BASE+XMC4_PORT_PDR1_OFFSET) +#define XMC4_PORT3_PDISC (XMC4_PORT3_BASE+XMC4_PORT_PDISC_OFFSET) +#define XMC4_PORT3_PPS (XMC4_PORT3_BASE+XMC4_PORT_PPS_OFFSET) +#define XMC4_PORT3_HWSEL (XMC4_PORT3_BASE+XMC4_PORT_HWSEL_OFFSET) -#define XMC4_PORT4_OUT (XMC4_PORT4_BASE+XMC4_PORTS_OUT_OFFSET) -#define XMC4_PORT4_OMR (XMC4_PORT4_BASE+XMC4_PORTS_OMR_OFFSET) -#define XMC4_PORT4_IOCR0 (XMC4_PORT4_BASE+XMC4_PORTS_IOCR0_OFFSET) -#define XMC4_PORT4_IOCR4 (XMC4_PORT4_BASE+XMC4_PORTS_IOCR4_OFFSET) -#define XMC4_PORT4_IOCR8 (XMC4_PORT4_BASE+XMC4_PORTS_IOCR8_OFFSET) -#define XMC4_PORT4_IOCR12 (XMC4_PORT4_BASE+XMC4_PORTS_IOCR12_OFFSET) -#define XMC4_PORT4_IN (XMC4_PORT4_BASE+XMC4_PORTS_IN_OFFSET) -#define XMC4_PORT4_PDR0 (XMC4_PORT4_BASE+XMC4_PORTS_PDR0_OFFSET) -#define XMC4_PORT4_PDR1 (XMC4_PORT4_BASE+XMC4_PORTS_PDR1_OFFSET) -#define XMC4_PORT4_PDISC (XMC4_PORT4_BASE+XMC4_PORTS_PDISC_OFFSET) -#define XMC4_PORT4_PPS (XMC4_PORT4_BASE+XMC4_PORTS_PPS_OFFSET) -#define XMC4_PORT4_HWSEL (XMC4_PORT4_BASE+XMC4_PORTS_HWSEL_OFFSET) +#define XMC4_PORT4_OUT (XMC4_PORT4_BASE+XMC4_PORT_OUT_OFFSET) +#define XMC4_PORT4_OMR (XMC4_PORT4_BASE+XMC4_PORT_OMR_OFFSET) +#define XMC4_PORT4_IOCR0 (XMC4_PORT4_BASE+XMC4_PORT_IOCR0_OFFSET) +#define XMC4_PORT4_IOCR4 (XMC4_PORT4_BASE+XMC4_PORT_IOCR4_OFFSET) +#define XMC4_PORT4_IOCR8 (XMC4_PORT4_BASE+XMC4_PORT_IOCR8_OFFSET) +#define XMC4_PORT4_IOCR12 (XMC4_PORT4_BASE+XMC4_PORT_IOCR12_OFFSET) +#define XMC4_PORT4_IN (XMC4_PORT4_BASE+XMC4_PORT_IN_OFFSET) +#define XMC4_PORT4_PDR0 (XMC4_PORT4_BASE+XMC4_PORT_PDR0_OFFSET) +#define XMC4_PORT4_PDR1 (XMC4_PORT4_BASE+XMC4_PORT_PDR1_OFFSET) +#define XMC4_PORT4_PDISC (XMC4_PORT4_BASE+XMC4_PORT_PDISC_OFFSET) +#define XMC4_PORT4_PPS (XMC4_PORT4_BASE+XMC4_PORT_PPS_OFFSET) +#define XMC4_PORT4_HWSEL (XMC4_PORT4_BASE+XMC4_PORT_HWSEL_OFFSET) -#define XMC4_PORT5_OUT (XMC4_PORT5_BASE+XMC4_PORTS_OUT_OFFSET) -#define XMC4_PORT5_OMR (XMC4_PORT5_BASE+XMC4_PORTS_OMR_OFFSET) -#define XMC4_PORT5_IOCR0 (XMC4_PORT5_BASE+XMC4_PORTS_IOCR0_OFFSET) -#define XMC4_PORT5_IOCR4 (XMC4_PORT5_BASE+XMC4_PORTS_IOCR4_OFFSET) -#define XMC4_PORT5_IOCR8 (XMC4_PORT5_BASE+XMC4_PORTS_IOCR8_OFFSET) -#define XMC4_PORT5_IOCR12 (XMC4_PORT5_BASE+XMC4_PORTS_IOCR12_OFFSET) -#define XMC4_PORT5_IN (XMC4_PORT5_BASE+XMC4_PORTS_IN_OFFSET) -#define XMC4_PORT5_PDR0 (XMC4_PORT5_BASE+XMC4_PORTS_PDR0_OFFSET) -#define XMC4_PORT5_PDR1 (XMC4_PORT5_BASE+XMC4_PORTS_PDR1_OFFSET) -#define XMC4_PORT5_PDISC (XMC4_PORT5_BASE+XMC4_PORTS_PDISC_OFFSET) -#define XMC4_PORT5_PPS (XMC4_PORT5_BASE+XMC4_PORTS_PPS_OFFSET) -#define XMC4_PORT5_HWSEL (XMC4_PORT5_BASE+XMC4_PORTS_HWSEL_OFFSET) +#define XMC4_PORT5_OUT (XMC4_PORT5_BASE+XMC4_PORT_OUT_OFFSET) +#define XMC4_PORT5_OMR (XMC4_PORT5_BASE+XMC4_PORT_OMR_OFFSET) +#define XMC4_PORT5_IOCR0 (XMC4_PORT5_BASE+XMC4_PORT_IOCR0_OFFSET) +#define XMC4_PORT5_IOCR4 (XMC4_PORT5_BASE+XMC4_PORT_IOCR4_OFFSET) +#define XMC4_PORT5_IOCR8 (XMC4_PORT5_BASE+XMC4_PORT_IOCR8_OFFSET) +#define XMC4_PORT5_IOCR12 (XMC4_PORT5_BASE+XMC4_PORT_IOCR12_OFFSET) +#define XMC4_PORT5_IN (XMC4_PORT5_BASE+XMC4_PORT_IN_OFFSET) +#define XMC4_PORT5_PDR0 (XMC4_PORT5_BASE+XMC4_PORT_PDR0_OFFSET) +#define XMC4_PORT5_PDR1 (XMC4_PORT5_BASE+XMC4_PORT_PDR1_OFFSET) +#define XMC4_PORT5_PDISC (XMC4_PORT5_BASE+XMC4_PORT_PDISC_OFFSET) +#define XMC4_PORT5_PPS (XMC4_PORT5_BASE+XMC4_PORT_PPS_OFFSET) +#define XMC4_PORT5_HWSEL (XMC4_PORT5_BASE+XMC4_PORT_HWSEL_OFFSET) -#define XMC4_PORT6_OUT (XMC4_PORT6_BASE+XMC4_PORTS_OUT_OFFSET) -#define XMC4_PORT6_OMR (XMC4_PORT6_BASE+XMC4_PORTS_OMR_OFFSET) -#define XMC4_PORT6_IOCR0 (XMC4_PORT6_BASE+XMC4_PORTS_IOCR0_OFFSET) -#define XMC4_PORT6_IOCR4 (XMC4_PORT6_BASE+XMC4_PORTS_IOCR4_OFFSET) -#define XMC4_PORT6_IOCR8 (XMC4_PORT6_BASE+XMC4_PORTS_IOCR8_OFFSET) -#define XMC4_PORT6_IOCR12 (XMC4_PORT6_BASE+XMC4_PORTS_IOCR12_OFFSET) -#define XMC4_PORT6_IN (XMC4_PORT6_BASE+XMC4_PORTS_IN_OFFSET) -#define XMC4_PORT6_PDR0 (XMC4_PORT6_BASE+XMC4_PORTS_PDR0_OFFSET) -#define XMC4_PORT6_PDR1 (XMC4_PORT6_BASE+XMC4_PORTS_PDR1_OFFSET) -#define XMC4_PORT6_PDISC (XMC4_PORT6_BASE+XMC4_PORTS_PDISC_OFFSET) -#define XMC4_PORT6_PPS (XMC4_PORT6_BASE+XMC4_PORTS_PPS_OFFSET) -#define XMC4_PORT6_HWSEL (XMC4_PORT6_BASE+XMC4_PORTS_HWSEL_OFFSET) +#define XMC4_PORT6_OUT (XMC4_PORT6_BASE+XMC4_PORT_OUT_OFFSET) +#define XMC4_PORT6_OMR (XMC4_PORT6_BASE+XMC4_PORT_OMR_OFFSET) +#define XMC4_PORT6_IOCR0 (XMC4_PORT6_BASE+XMC4_PORT_IOCR0_OFFSET) +#define XMC4_PORT6_IOCR4 (XMC4_PORT6_BASE+XMC4_PORT_IOCR4_OFFSET) +#define XMC4_PORT6_IOCR8 (XMC4_PORT6_BASE+XMC4_PORT_IOCR8_OFFSET) +#define XMC4_PORT6_IOCR12 (XMC4_PORT6_BASE+XMC4_PORT_IOCR12_OFFSET) +#define XMC4_PORT6_IN (XMC4_PORT6_BASE+XMC4_PORT_IN_OFFSET) +#define XMC4_PORT6_PDR0 (XMC4_PORT6_BASE+XMC4_PORT_PDR0_OFFSET) +#define XMC4_PORT6_PDR1 (XMC4_PORT6_BASE+XMC4_PORT_PDR1_OFFSET) +#define XMC4_PORT6_PDISC (XMC4_PORT6_BASE+XMC4_PORT_PDISC_OFFSET) +#define XMC4_PORT6_PPS (XMC4_PORT6_BASE+XMC4_PORT_PPS_OFFSET) +#define XMC4_PORT6_HWSEL (XMC4_PORT6_BASE+XMC4_PORT_HWSEL_OFFSET) -#define XMC4_PORT7_OUT (XMC4_PORT7_BASE+XMC4_PORTS_OUT_OFFSET) -#define XMC4_PORT7_OMR (XMC4_PORT7_BASE+XMC4_PORTS_OMR_OFFSET) -#define XMC4_PORT7_IOCR0 (XMC4_PORT7_BASE+XMC4_PORTS_IOCR0_OFFSET) -#define XMC4_PORT7_IOCR4 (XMC4_PORT7_BASE+XMC4_PORTS_IOCR4_OFFSET) -#define XMC4_PORT7_IOCR8 (XMC4_PORT7_BASE+XMC4_PORTS_IOCR8_OFFSET) -#define XMC4_PORT7_IOCR12 (XMC4_PORT7_BASE+XMC4_PORTS_IOCR12_OFFSET) -#define XMC4_PORT7_IN (XMC4_PORT7_BASE+XMC4_PORTS_IN_OFFSET) -#define XMC4_PORT7_PDR0 (XMC4_PORT7_BASE+XMC4_PORTS_PDR0_OFFSET) -#define XMC4_PORT7_PDR1 (XMC4_PORT7_BASE+XMC4_PORTS_PDR1_OFFSET) -#define XMC4_PORT7_PDISC (XMC4_PORT7_BASE+XMC4_PORTS_PDISC_OFFSET) -#define XMC4_PORT7_PPS (XMC4_PORT7_BASE+XMC4_PORTS_PPS_OFFSET) -#define XMC4_PORT7_HWSEL (XMC4_PORT7_BASE+XMC4_PORTS_HWSEL_OFFSET) +#define XMC4_PORT7_OUT (XMC4_PORT7_BASE+XMC4_PORT_OUT_OFFSET) +#define XMC4_PORT7_OMR (XMC4_PORT7_BASE+XMC4_PORT_OMR_OFFSET) +#define XMC4_PORT7_IOCR0 (XMC4_PORT7_BASE+XMC4_PORT_IOCR0_OFFSET) +#define XMC4_PORT7_IOCR4 (XMC4_PORT7_BASE+XMC4_PORT_IOCR4_OFFSET) +#define XMC4_PORT7_IOCR8 (XMC4_PORT7_BASE+XMC4_PORT_IOCR8_OFFSET) +#define XMC4_PORT7_IOCR12 (XMC4_PORT7_BASE+XMC4_PORT_IOCR12_OFFSET) +#define XMC4_PORT7_IN (XMC4_PORT7_BASE+XMC4_PORT_IN_OFFSET) +#define XMC4_PORT7_PDR0 (XMC4_PORT7_BASE+XMC4_PORT_PDR0_OFFSET) +#define XMC4_PORT7_PDR1 (XMC4_PORT7_BASE+XMC4_PORT_PDR1_OFFSET) +#define XMC4_PORT7_PDISC (XMC4_PORT7_BASE+XMC4_PORT_PDISC_OFFSET) +#define XMC4_PORT7_PPS (XMC4_PORT7_BASE+XMC4_PORT_PPS_OFFSET) +#define XMC4_PORT7_HWSEL (XMC4_PORT7_BASE+XMC4_PORT_HWSEL_OFFSET) -#define XMC4_PORT8_OUT (XMC4_PORT8_BASE+XMC4_PORTS_OUT_OFFSET) -#define XMC4_PORT8_OMR (XMC4_PORT8_BASE+XMC4_PORTS_OMR_OFFSET) -#define XMC4_PORT8_IOCR0 (XMC4_PORT8_BASE+XMC4_PORTS_IOCR0_OFFSET) -#define XMC4_PORT8_IOCR4 (XMC4_PORT8_BASE+XMC4_PORTS_IOCR4_OFFSET) -#define XMC4_PORT8_IOCR8 (XMC4_PORT8_BASE+XMC4_PORTS_IOCR8_OFFSET) -#define XMC4_PORT8_IOCR12 (XMC4_PORT8_BASE+XMC4_PORTS_IOCR12_OFFSET) -#define XMC4_PORT8_IN (XMC4_PORT8_BASE+XMC4_PORTS_IN_OFFSET) -#define XMC4_PORT8_PDR0 (XMC4_PORT8_BASE+XMC4_PORTS_PDR0_OFFSET) -#define XMC4_PORT8_PDR1 (XMC4_PORT8_BASE+XMC4_PORTS_PDR1_OFFSET) -#define XMC4_PORT8_PDISC (XMC4_PORT8_BASE+XMC4_PORTS_PDISC_OFFSET) -#define XMC4_PORT8_PPS (XMC4_PORT8_BASE+XMC4_PORTS_PPS_OFFSET) -#define XMC4_PORT8_HWSEL (XMC4_PORT8_BASE+XMC4_PORTS_HWSEL_OFFSET) +#define XMC4_PORT8_OUT (XMC4_PORT8_BASE+XMC4_PORT_OUT_OFFSET) +#define XMC4_PORT8_OMR (XMC4_PORT8_BASE+XMC4_PORT_OMR_OFFSET) +#define XMC4_PORT8_IOCR0 (XMC4_PORT8_BASE+XMC4_PORT_IOCR0_OFFSET) +#define XMC4_PORT8_IOCR4 (XMC4_PORT8_BASE+XMC4_PORT_IOCR4_OFFSET) +#define XMC4_PORT8_IOCR8 (XMC4_PORT8_BASE+XMC4_PORT_IOCR8_OFFSET) +#define XMC4_PORT8_IOCR12 (XMC4_PORT8_BASE+XMC4_PORT_IOCR12_OFFSET) +#define XMC4_PORT8_IN (XMC4_PORT8_BASE+XMC4_PORT_IN_OFFSET) +#define XMC4_PORT8_PDR0 (XMC4_PORT8_BASE+XMC4_PORT_PDR0_OFFSET) +#define XMC4_PORT8_PDR1 (XMC4_PORT8_BASE+XMC4_PORT_PDR1_OFFSET) +#define XMC4_PORT8_PDISC (XMC4_PORT8_BASE+XMC4_PORT_PDISC_OFFSET) +#define XMC4_PORT8_PPS (XMC4_PORT8_BASE+XMC4_PORT_PPS_OFFSET) +#define XMC4_PORT8_HWSEL (XMC4_PORT8_BASE+XMC4_PORT_HWSEL_OFFSET) -#define XMC4_PORT9_OUT (XMC4_PORT9_BASE+XMC4_PORTS_OUT_OFFSET) -#define XMC4_PORT9_OMR (XMC4_PORT9_BASE+XMC4_PORTS_OMR_OFFSET) -#define XMC4_PORT9_IOCR0 (XMC4_PORT9_BASE+XMC4_PORTS_IOCR0_OFFSET) -#define XMC4_PORT9_IOCR4 (XMC4_PORT9_BASE+XMC4_PORTS_IOCR4_OFFSET) -#define XMC4_PORT9_IOCR8 (XMC4_PORT9_BASE+XMC4_PORTS_IOCR8_OFFSET) -#define XMC4_PORT9_IOCR12 (XMC4_PORT9_BASE+XMC4_PORTS_IOCR12_OFFSET) -#define XMC4_PORT9_IN (XMC4_PORT9_BASE+XMC4_PORTS_IN_OFFSET) -#define XMC4_PORT9_PDR0 (XMC4_PORT9_BASE+XMC4_PORTS_PDR0_OFFSET) -#define XMC4_PORT9_PDR1 (XMC4_PORT9_BASE+XMC4_PORTS_PDR1_OFFSET) -#define XMC4_PORT9_PDISC (XMC4_PORT9_BASE+XMC4_PORTS_PDISC_OFFSET) -#define XMC4_PORT9_PPS (XMC4_PORT9_BASE+XMC4_PORTS_PPS_OFFSET) -#define XMC4_PORT9_HWSEL (XMC4_PORT9_BASE+XMC4_PORTS_HWSEL_OFFSET) +#define XMC4_PORT9_OUT (XMC4_PORT9_BASE+XMC4_PORT_OUT_OFFSET) +#define XMC4_PORT9_OMR (XMC4_PORT9_BASE+XMC4_PORT_OMR_OFFSET) +#define XMC4_PORT9_IOCR0 (XMC4_PORT9_BASE+XMC4_PORT_IOCR0_OFFSET) +#define XMC4_PORT9_IOCR4 (XMC4_PORT9_BASE+XMC4_PORT_IOCR4_OFFSET) +#define XMC4_PORT9_IOCR8 (XMC4_PORT9_BASE+XMC4_PORT_IOCR8_OFFSET) +#define XMC4_PORT9_IOCR12 (XMC4_PORT9_BASE+XMC4_PORT_IOCR12_OFFSET) +#define XMC4_PORT9_IN (XMC4_PORT9_BASE+XMC4_PORT_IN_OFFSET) +#define XMC4_PORT9_PDR0 (XMC4_PORT9_BASE+XMC4_PORT_PDR0_OFFSET) +#define XMC4_PORT9_PDR1 (XMC4_PORT9_BASE+XMC4_PORT_PDR1_OFFSET) +#define XMC4_PORT9_PDISC (XMC4_PORT9_BASE+XMC4_PORT_PDISC_OFFSET) +#define XMC4_PORT9_PPS (XMC4_PORT9_BASE+XMC4_PORT_PPS_OFFSET) +#define XMC4_PORT9_HWSEL (XMC4_PORT9_BASE+XMC4_PORT_HWSEL_OFFSET) -#define XMC4_PORT14_OUT (XMC4_PORT14_BASE+XMC4_PORTS_OUT_OFFSET) -#define XMC4_PORT14_OMR (XMC4_PORT14_BASE+XMC4_PORTS_OMR_OFFSET) -#define XMC4_PORT14_IOCR0 (XMC4_PORT14_BASE+XMC4_PORTS_IOCR0_OFFSET) -#define XMC4_PORT14_IOCR4 (XMC4_PORT14_BASE+XMC4_PORTS_IOCR4_OFFSET) -#define XMC4_PORT14_IOCR8 (XMC4_PORT14_BASE+XMC4_PORTS_IOCR8_OFFSET) -#define XMC4_PORT14_IOCR12 (XMC4_PORT14_BASE+XMC4_PORTS_IOCR12_OFFSET) -#define XMC4_PORT14_IN (XMC4_PORT14_BASE+XMC4_PORTS_IN_OFFSET) -#define XMC4_PORT14_PDR0 (XMC4_PORT14_BASE+XMC4_PORTS_PDR0_OFFSET) -#define XMC4_PORT14_PDR1 (XMC4_PORT14_BASE+XMC4_PORTS_PDR1_OFFSET) -#define XMC4_PORT14_PDISC (XMC4_PORT14_BASE+XMC4_PORTS_PDISC_OFFSET) -#define XMC4_PORT14_PPS (XMC4_PORT14_BASE+XMC4_PORTS_PPS_OFFSET) -#define XMC4_PORT14_HWSEL (XMC4_PORT14_BASE+XMC4_PORTS_HWSEL_OFFSET) +#define XMC4_PORT14_OUT (XMC4_PORT14_BASE+XMC4_PORT_OUT_OFFSET) +#define XMC4_PORT14_OMR (XMC4_PORT14_BASE+XMC4_PORT_OMR_OFFSET) +#define XMC4_PORT14_IOCR0 (XMC4_PORT14_BASE+XMC4_PORT_IOCR0_OFFSET) +#define XMC4_PORT14_IOCR4 (XMC4_PORT14_BASE+XMC4_PORT_IOCR4_OFFSET) +#define XMC4_PORT14_IOCR8 (XMC4_PORT14_BASE+XMC4_PORT_IOCR8_OFFSET) +#define XMC4_PORT14_IOCR12 (XMC4_PORT14_BASE+XMC4_PORT_IOCR12_OFFSET) +#define XMC4_PORT14_IN (XMC4_PORT14_BASE+XMC4_PORT_IN_OFFSET) +#define XMC4_PORT14_PDR0 (XMC4_PORT14_BASE+XMC4_PORT_PDR0_OFFSET) +#define XMC4_PORT14_PDR1 (XMC4_PORT14_BASE+XMC4_PORT_PDR1_OFFSET) +#define XMC4_PORT14_PDISC (XMC4_PORT14_BASE+XMC4_PORT_PDISC_OFFSET) +#define XMC4_PORT14_PPS (XMC4_PORT14_BASE+XMC4_PORT_PPS_OFFSET) +#define XMC4_PORT14_HWSEL (XMC4_PORT14_BASE+XMC4_PORT_HWSEL_OFFSET) -#define XMC4_PORT15_OUT (XMC4_PORT15_BASE+XMC4_PORTS_OUT_OFFSET) -#define XMC4_PORT15_OMR (XMC4_PORT15_BASE+XMC4_PORTS_OMR_OFFSET) -#define XMC4_PORT15_IOCR0 (XMC4_PORT15_BASE+XMC4_PORTS_IOCR0_OFFSET) -#define XMC4_PORT15_IOCR4 (XMC4_PORT15_BASE+XMC4_PORTS_IOCR4_OFFSET) -#define XMC4_PORT15_IOCR8 (XMC4_PORT15_BASE+XMC4_PORTS_IOCR8_OFFSET) -#define XMC4_PORT15_IOCR12 (XMC4_PORT15_BASE+XMC4_PORTS_IOCR12_OFFSET) -#define XMC4_PORT15_IN (XMC4_PORT15_BASE+XMC4_PORTS_IN_OFFSET) -#define XMC4_PORT15_PDR0 (XMC4_PORT15_BASE+XMC4_PORTS_PDR0_OFFSET) -#define XMC4_PORT15_PDR1 (XMC4_PORT15_BASE+XMC4_PORTS_PDR1_OFFSET) -#define XMC4_PORT15_PDISC (XMC4_PORT15_BASE+XMC4_PORTS_PDISC_OFFSET) -#define XMC4_PORT15_PPS (XMC4_PORT15_BASE+XMC4_PORTS_PPS_OFFSET) -#define XMC4_PORT15_HWSEL (XMC4_PORT15_BASE+XMC4_PORTS_HWSEL_OFFSET) +#define XMC4_PORT15_OUT (XMC4_PORT15_BASE+XMC4_PORT_OUT_OFFSET) +#define XMC4_PORT15_OMR (XMC4_PORT15_BASE+XMC4_PORT_OMR_OFFSET) +#define XMC4_PORT15_IOCR0 (XMC4_PORT15_BASE+XMC4_PORT_IOCR0_OFFSET) +#define XMC4_PORT15_IOCR4 (XMC4_PORT15_BASE+XMC4_PORT_IOCR4_OFFSET) +#define XMC4_PORT15_IOCR8 (XMC4_PORT15_BASE+XMC4_PORT_IOCR8_OFFSET) +#define XMC4_PORT15_IOCR12 (XMC4_PORT15_BASE+XMC4_PORT_IOCR12_OFFSET) +#define XMC4_PORT15_IN (XMC4_PORT15_BASE+XMC4_PORT_IN_OFFSET) +#define XMC4_PORT15_PDR0 (XMC4_PORT15_BASE+XMC4_PORT_PDR0_OFFSET) +#define XMC4_PORT15_PDR1 (XMC4_PORT15_BASE+XMC4_PORT_PDR1_OFFSET) +#define XMC4_PORT15_PDISC (XMC4_PORT15_BASE+XMC4_PORT_PDISC_OFFSET) +#define XMC4_PORT15_PPS (XMC4_PORT15_BASE+XMC4_PORT_PPS_OFFSET) +#define XMC4_PORT15_HWSEL (XMC4_PORT15_BASE+XMC4_PORT_HWSEL_OFFSET) /* Register Bit-Field Definitions **************************************************/ -/* Port Output Register */ -#define PORTS_OUT_ -/* Port Output Modification Register */ -#define PORTS_OMR_ +/* Port Output Register, Port Output Modification Register, Port Input Register, + * Port Pin Function Decision Control Register, Port Pin Power Save Register. + */ + +#define PORT_PIN(n) (1 << (n)) + +/* Basic port input/output field values */ +/* Director Input */ + +#define IOCR_NOPULL 0 /* No internal pull device active */ +#define IOCR_PULLDOWN 1 /* Internal pull-down device active */ +#define IOCR_PULLUP 2 /* Internal pull-down device active */ +#define IOCR_CONT 3 /* No internal pull device active; Pn_OUTx continuously + * samples the input value */ + +/* Any of the above may be OR'ed with */ +/* Inverted Input */ + +#define IOCR_INVERT 4 /* Inverted input */ + /* Port Input/Output Control Register 0 */ -#define PORTS_IOCR0_ + +#define PORT_IOCR0_PC_SHIFT(p) (((p) << 3) + 3) +#define PORT_IOCR0_PC_MASK(p) (31 << PORT_IOCR0_PC_SHIFT(p)) +# define PORT_IOCR0_PC(p,n) ((uint32_t)(n) << PORT_IOCR0_PC_SHIFT(p)) +#define PORT_IOCR0_PC0_SHIFT (3) /* Bit 3-7: Port Control for Port n Pin 0 */ +#define PORT_IOCR0_PC0_MASK (31 << PORT_IOCR0_PC0_SHIFT) +# define PORT_IOCR0_PC0(n) ((uint32_t)(n) << PORT_IOCR0_PC0_SHIFT) +#define PORT_IOCR0_PC1_SHIFT (11) /* Bit 11-15: Port Control for Port n Pin 1 */ +#define PORT_IOCR0_PC1_MASK (31 << PORT_IOCR0_PC1_SHIFT) +# define PORT_IOCR0_PC1(n) ((uint32_t)(n) << PORT_IOCR0_PC1_SHIFT) +#define PORT_IOCR0_PC2_SHIFT (19) /* Bit 19-23: Port Control for Port n Pin 2 */ +#define PORT_IOCR0_PC2_MASK (31 << PORT_IOCR0_PC2_SHIFT) +# define PORT_IOCR0_PC2(n) ((uint32_t)(n) << PORT_IOCR0_PC2_SHIFT) +#define PORT_IOCR0_PC3_SHIFT (27) /* Bit 27-31: Port Control for Port 0 Pin 3 */ +#define PORT_IOCR0_PC3_MASK (31 << PORT_IOCR0_PC3_SHIFT) +# define PORT_IOCR0_PC3(n) ((uint32_t)(n) << PORT_IOCR0_PC3_SHIFT) + /* Port Input/Output Control Register 4 */ -#define PORTS_IOCR4_ + +#define PORT_IOCR4_PC_SHIFT(p) ((((p) - 4) << 3) + 3) +#define PORT_IOCR4_PC_MASK(p) (31 << PORT_IOCR4_PC_SHIFT(p)) +# define PORT_IOCR4_PC(p,n) ((uint32_t)(n) << PORT_IOCR4_PC_SHIFT(p)) +#define PORT_IOCR4_PC4_SHIFT (3) /* Bit 3-7: Port Control for Port n Pin 4 */ +#define PORT_IOCR4_PC4_MASK (31 << PORT_IOCR4_PC4_SHIFT) +# define PORT_IOCR4_PC4(n) ((uint32_t)(n) << PORT_IOCR4_PC4_SHIFT) +#define PORT_IOCR4_PC5_SHIFT (11) /* Bit 11-15: Port Control for Port n Pin 5 */ +#define PORT_IOCR4_PC5_MASK (31 << PORT_IOCR4_PC5_SHIFT) +# define PORT_IOCR4_PC5(n) ((uint32_t)(n) << PORT_IOCR4_PC5_SHIFT) +#define PORT_IOCR4_PC6_SHIFT (19) /* Bit 19-23: Port Control for Port n Pin 6 */ +#define PORT_IOCR4_PC6_MASK (31 << PORT_IOCR4_PC6_SHIFT) +# define PORT_IOCR4_PC6(n) ((uint32_t)(n) << PORT_IOCR4_PC6_SHIFT) +#define PORT_IOCR4_PC7_SHIFT (27) /* Bit 27-31: Port Control for Port 0 Pin 7 */ +#define PORT_IOCR4_PC7_MASK (31 << PORT_IOCR4_PC7_SHIFT) +# define PORT_IOCR4_PC7(n) ((uint32_t)(n) << PORT_IOCR4_PC7_SHIFT) + /* Port Input/Output Control Register 8 */ -#define PORTS_IOCR8_ + +#define PORT_IOCR8_PC_SHIFT(p) ((((p) - 8) << 3) + 3) +#define PORT_IOCR8_PC_MASK(p) (31 << PORT_IOCR8_PC_SHIFT(p)) +# define PORT_IOCR8_PC(p,n) ((uint32_t)(n) << PORT_IOCR8_PC_SHIFT(p)) +#define PORT_IOCR8_PC8_SHIFT (3) /* Bit 3-7: Port Control for Port n Pin 8 */ +#define PORT_IOCR8_PC8_MASK (31 << PORT_IOCR8_PC8_SHIFT) +# define PORT_IOCR8_PC8(n) ((uint32_t)(n) << PORT_IOCR8_PC8_SHIFT) +#define PORT_IOCR8_PC9_SHIFT (11) /* Bit 11-15: Port Control for Port n Pin 9 */ +#define PORT_IOCR8_PC9_MASK (31 << PORT_IOCR8_PC9_SHIFT) +# define PORT_IOCR8_PC9(n) ((uint32_t)(n) << PORT_IOCR8_PC9_SHIFT) +#define PORT_IOCR8_PC10_SHIFT (19) /* Bit 19-23: Port Control for Port n Pin 10 */ +#define PORT_IOCR8_PC10_MASK (31 << PORT_IOCR8_PC10_SHIFT) +# define PORT_IOCR8_PC10(n) ((uint32_t)(n) << PORT_IOCR8_PC10_SHIFT) +#define PORT_IOCR8_PC11_SHIFT (27) /* Bit 17-31: Port Control for Port 0 Pin 11 */ +#define PORT_IOCR8_PC11_MASK (31 << PORT_IOCR8_PC11_SHIFT) +# define PORT_IOCR8_PC11(n) ((uint32_t)(n) << PORT_IOCR8_PC11_SHIFT) + /* Port Input/Output Control Register 12 */ -#define PORTS_IOCR12_ -/* Port Input Register */ -#define PORTS_IN_ + +#define PORT_IOCR12_PC_SHIFT(p) ((((p) - 12) << 3) + 3) +#define PORT_IOCR12_PC_MASK(p) (31 << PORT_IOCR12_PC_SHIFT(p)) +# define PORT_IOCR12_PC(p,n) ((uint32_t)(n) << PORT_IOCR12_PC_SHIFT(p)) +#define PORT_IOCR12_PC12_SHIFT (3) /* Bit 3-7: Port Control for Port n Pin 12 */ +#define PORT_IOCR12_PC12_MASK (31 << PORT_IOCR12_PC12_SHIFT) +# define PORT_IOCR12_PC12(n) ((uint32_t)(n) << PORT_IOCR12_PC12_SHIFT) +#define PORT_IOCR12_PC13_SHIFT (11) /* Bit 3-7: Port Control for Port n Pin 13 */ +#define PORT_IOCR12_PC13_MASK (31 << PORT_IOCR12_PC13_SHIFT) +# define PORT_IOCR12_PC13(n) ((uint32_t)(n) << PORT_IOCR12_PC13_SHIFT) +#define PORT_IOCR12_PC14_SHIFT (19) /* Bit 3-7: Port Control for Port n Pin 14 */ +#define PORT_IOCR12_PC14_MASK (31 << PORT_IOCR12_PC14_SHIFT) +# define PORT_IOCR12_PC14(n) ((uint32_t)(n) << PORT_IOCR12_PC14_SHIFT) +#define PORT_IOCR12_PC15_SHIFT (27) /* Bit 3-7: Port Control for Port 0 Pin 15 */ +#define PORT_IOCR12_PC15_MASK (31 << PORT_IOCR12_PC15_SHIFT) +# define PORT_IOCR12_PC15(n) ((uint32_t)(n) << PORT_IOCR12_PC15_SHIFT) + +/* Pad driver field values */ +/* Pad class A1: */ + +#define PDR_PADA1_MEDIUM 0 /* Medium driver */ +#define PDR_PADA1_WEAK 1 /* Weak driver */ + +/* Pad class A1+: */ + +#define PDR_PADA1P_STRONGSOFT 0 /* Strong driver soft edge */ +#define PDR_PADA1P_STRONGSLOW 1 /* Strong driver slow edge */ +#define PDR_PADA1P_MEDIUM 4 /* Medium driver */ +#define PDR_PADA1P_WEAK 5 /* Weak driver */ + +/* Pad class A2: */ + +#define PDR_PADA2_STRONGSHARP 0 /* Strong driver sharp edge */ +#define PDR_PADA2_STRONGMEDIUM 1 /* Strong driver medium edge */ +#define PDR_PADA2_STRONGSOFT 2 /* Strong driver soft edge */ +#define PDR_PADA2_MEDIUM 4 /* Medium driver */ +#define PDR_PADA2_WEAK 7 /* Weak driver */ + /* Port Pad Driver Mode 0 Register */ -#define PORTS_PDR0_ + +#define PORT_PDR0_PD_SHIFT(p) ((p) << 2) +#define PORT_PDR0_PD_MASK(p) (7 << PORT_PDR0_PD_SHIFT(p)) +# define PORT_PDR0_PD(p,n) ((uint32_t)(n) << PORT_PDR0_PD_SHIFT(p)) +#define PORT_PDR0_PD0_SHIFT (0) /* Bit 0-2: Pad Driver Mode for Port n Pin 0 */ +#define PORT_PDR0_PD0_MASK (7 << PORT_PDR0_PD0_SHIFT) +# define PORT_PDR0_PD0(n) ((uint32_t)(n) << PORT_PDR0_PD0_SHIFT) +#define PORT_PDR0_PD1_SHIFT (4) /* Bit 4-6: Pad Driver Mode for Port n Pin 1 */ +#define PORT_PDR0_PD1_MASK (7 << PORT_PDR0_PD1_SHIFT) +# define PORT_PDR0_PD1(n) ((uint32_t)(n) << PORT_PDR0_PD1_SHIFT) +#define PORT_PDR0_PD2_SHIFT (8) /* Bit 8-10: Pad Driver Mode for Port n Pin 2 */ +#define PORT_PDR0_PD2_MASK (7 << PORT_PDR0_PD2_SHIFT) +# define PORT_PDR0_PD2(n) ((uint32_t)(n) << PORT_PDR0_PD2_SHIFT) +#define PORT_PDR0_PD3_SHIFT (12) /* Bit 12-14: Pad Driver Mode for Port 0 Pin 3 */ +#define PORT_PDR0_PD3_MASK (7 << PORT_PDR0_PD3_SHIFT) +# define PORT_PDR0_PD3(n) ((uint32_t)(n) << PORT_PDR0_PD3_SHIFT) +#define PORT_PDR0_PD4_SHIFT (16) /* Bit 16-18: Pad Driver Mode for Port 0 Pin 4 */ +#define PORT_PDR0_PD4_MASK (7 << PORT_PDR0_PD4_SHIFT) +# define PORT_PDR0_PD4(n) ((uint32_t)(n) << PORT_PDR0_PD4_SHIFT) +#define PORT_PDR0_PD5_SHIFT (20) /* Bit 20-22: Pad Driver Mode for Port 0 Pin 5 */ +#define PORT_PDR0_PD5_MASK (7 << PORT_PDR0_PD5_SHIFT) +# define PORT_PDR0_PD5(n) ((uint32_t)(n) << PORT_PDR0_PD5_SHIFT) +#define PORT_PDR0_PD6_SHIFT (24) /* Bit 24-26: Pad Driver Mode for Port 0 Pin 6 */ +#define PORT_PDR0_PD6_MASK (7 << PORT_PDR0_PD6_SHIFT) +# define PORT_PDR0_PD6(n) ((uint32_t)(n) << PORT_PDR0_PD6_SHIFT) +#define PORT_PDR0_PD7_SHIFT (28) /* Bit 28-30: Pad Driver Mode for Port 0 Pin 7 */ +#define PORT_PDR0_PD7_MASK (7 << PORT_PDR0_PD7_SHIFT) +# define PORT_PDR0_PD7(n) ((uint32_t)(n) << PORT_PDR0_PD7_SHIFT) + /* Port Pad Driver Mode 1 Register */ -#define PORTS_PDR1_ -/* Port Pin Function Decision Control Register */ -#define PORTS_PDISC_ -/* Port Pin Power Save Register */ -#define PORTS_PPS_ + +#define PORT_PDR1_PD_SHIFT(p) (((p) - 8) << 2) +#define PORT_PDR1_PD_MASK(p) (7 << PORT_PDR1_PD_SHIFT(p)) +# define PORT_PDR1_PD(p,n) ((uint32_t)(n) << PORT_PDR1_PD_SHIFT(p)) +#define PORT_PDR1_PD8_SHIFT (0) /* Bit 0-2: Pad Driver Mode for Port n Pin 8 */ +#define PORT_PDR1_PD8_MASK (7 << PORT_PDR1_PD8_SHIFT) +# define PORT_PDR1_PD8(n) ((uint32_t)(n) << PORT_PDR1_PD8_SHIFT) +#define PORT_PDR1_PD9_SHIFT (4) /* Bit 4-6: Pad Driver Mode for Port n Pin 9 */ +#define PORT_PDR1_PD9_MASK (7 << PORT_PDR1_PD9_SHIFT) +# define PORT_PDR1_PD9(n) ((uint32_t)(n) << PORT_PDR1_PD9_SHIFT) +#define PORT_PDR1_PD10_SHIFT (8) /* Bit 8-10: Pad Driver Mode for Port n Pin 10 */ +#define PORT_PDR1_PD10_MASK (7 << PORT_PDR1_PD10_SHIFT) +# define PORT_PDR1_PD10(n) ((uint32_t)(n) << PORT_PDR1_PD10_SHIFT) +#define PORT_PDR1_PD11_SHIFT (12) /* Bit 12-14: Pad Driver Mode for Port 0 Pin 11 */ +#define PORT_PDR1_PD11_MASK (7 << PORT_PDR1_PD11_SHIFT) +# define PORT_PDR1_PD11(n) ((uint32_t)(n) << PORT_PDR1_PD11_SHIFT) +#define PORT_PDR1_PD12_SHIFT (16) /* Bit 16-18: Pad Driver Mode for Port 0 Pin 12 */ +#define PORT_PDR1_PD12_MASK (7 << PORT_PDR1_PD12_SHIFT) +# define PORT_PDR1_PD12(n) ((uint32_t)(n) << PORT_PDR1_PD12_SHIFT) +#define PORT_PDR1_PD13_SHIFT (20) /* Bit 20-22: Pad Driver Mode for Port 0 Pin 13 */ +#define PORT_PDR1_PD13_MASK (7 << PORT_PDR1_PD13_SHIFT) +# define PORT_PDR1_PD13(n) ((uint32_t)(n) << PORT_PDR1_PD13_SHIFT) +#define PORT_PDR1_PD14_SHIFT (24) /* Bit 24-26: Pad Driver Mode for Port 0 Pin 14 */ +#define PORT_PDR1_PD14_MASK (7 << PORT_PDR1_PD14_SHIFT) +# define PORT_PDR1_PD14(n) ((uint32_t)(n) << PORT_PDR1_PD14_SHIFT) +#define PORT_PDR1_PD15_SHIFT (28) /* Bit 28-30: Pad Driver Mode for Port 0 Pin 15 */ +#define PORT_PDR1_PD15_MASK (7 << PORT_PDR1_PD15_SHIFT) +# define PORT_PDR1_PD15(n) ((uint32_t)(n) << PORT_PDR1_PD15_SHIFT) + +/* Hardware select field values */ + +#define HWSEL_SOFTWARE 0 /* Software control only */ +#define HWSEL_OVERRIDE0 1 /* HWI0/HWO0 control path can override the + * software configuration */ +#define HWSEL_OVERRIDE1 2 /* HWI1/HWO1 control path can override the + * software configuration */ + /* Port Pin Hardware Select Register */ -#define PORTS_HWSEL_ + +#define PORT_HWSEL_HW_SHIFT(p) ((p) << 1) +#define PORT_HWSEL_HW_MASK(p) (3 << PORT_HWSEL_HW_SHIFT(p)) +# define PORT_HWSEL_HW(p,n) ((uint32_t)(n) << PORT_HWSEL_HW_SHIFT(p)) +#define PORT_HWSEL_HW0_SHIFT (0) /* Bit 0-1: Port n Pin 0 Hardware Select */ +#define PORT_HWSEL_HW0_MASK (3 << PORT_HWSEL_HW0_SHIFT) +# define PORT_HWSEL_HW0(n) ((uint32_t)(n) << PORT_HWSEL_HW0_SHIFT) +#define PORT_HWSEL_HW1_SHIFT (2) /* Bit 2-3: Port n Pin 1 Hardware Select */ +#define PORT_HWSEL_HW1_MASK (3 << PORT_HWSEL_HW1_SHIFT) +# define PORT_HWSEL_HW1(n) ((uint32_t)(n) << PORT_HWSEL_HW1_SHIFT) +#define PORT_HWSEL_HW2_SHIFT (4) /* Bit 4-5: Port n Pin 2 Hardware Select */ +#define PORT_HWSEL_HW2_MASK (3 << PORT_HWSEL_HW2_SHIFT) +# define PORT_HWSEL_HW2(n) ((uint32_t)(n) << PORT_HWSEL_HW2_SHIFT) +#define PORT_HWSEL_HW3_SHIFT (6) /* Bit 6-7: Port 0 Pin 3 Hardware Select */ +#define PORT_HWSEL_HW3_MASK (3 << PORT_HWSEL_HW3_SHIFT) +# define PORT_HWSEL_HW3(n) ((uint32_t)(n) << PORT_HWSEL_HW3_SHIFT) +#define PORT_HWSEL_HW4_SHIFT (8) /* Bit 8-9: Port 0 Pin 4 Hardware Select */ +#define PORT_HWSEL_HW4_MASK (3 << PORT_HWSEL_HW4_SHIFT) +# define PORT_HWSEL_HW4(n) ((uint32_t)(n) << PORT_HWSEL_HW4_SHIFT) +#define PORT_HWSEL_HW5_SHIFT (10) /* Bit 10-11: Port 0 Pin 5 Hardware Select */ +#define PORT_HWSEL_HW5_MASK (3 << PORT_HWSEL_HW5_SHIFT) +# define PORT_HWSEL_HW5(n) ((uint32_t)(n) << PORT_HWSEL_HW5_SHIFT) +#define PORT_HWSEL_HW6_SHIFT (12) /* Bit 12-13: Port 0 Pin 6 Hardware Select */ +#define PORT_HWSEL_HW6_MASK (3 << PORT_HWSEL_HW6_SHIFT) +# define PORT_HWSEL_HW6(n) 14uint32_t)(n) << PORT_HWSEL_HW6_SHIFT) +#define PORT_HWSEL_HW7_SHIFT (14) /* Bit 14-15: Port 0 Pin 7 Hardware Select */ +#define PORT_HWSEL_HW7_MASK (3 << PORT_HWSEL_HW7_SHIFT) +# define PORT_HWSEL_HW7(n) ((uint32_t)(n) << PORT_HWSEL_HW7_SHIFT) +#define PORT_HWSEL_HW8_SHIFT (16) /* Bit 16-17: Port n Pin 8 Hardware Select */ +#define PORT_HWSEL_HW8_MASK (3 << PORT_HWSEL_HW8_SHIFT) +# define PORT_HWSEL_HW8(n) ((uint32_t)(n) << PORT_HWSEL_HW8_SHIFT) +#define PORT_HWSEL_HW9_SHIFT (18) /* Bit 18-19: Port n Pin 9 Hardware Select */ +#define PORT_HWSEL_HW9_MASK (3 << PORT_HWSEL_HW9_SHIFT) +# define PORT_HWSEL_HW9(n) ((uint32_t)(n) << PORT_HWSEL_HW9_SHIFT) +#define PORT_HWSEL_HW10_SHIFT (20) /* Bit 20-21: Port n Pin 10 Hardware Select */ +#define PORT_HWSEL_HW10_MASK (3 << PORT_HWSEL_HW10_SHIFT) +# define PORT_HWSEL_HW10(n) ((uint32_t)(n) << PORT_HWSEL_HW10_SHIFT) +#define PORT_HWSEL_HW11_SHIFT (22) /* Bit 22-23: Port 0 Pin 11 Hardware Select */ +#define PORT_HWSEL_HW11_MASK (3 << PORT_HWSEL_HW11_SHIFT) +# define PORT_HWSEL_HW11(n) ((uint32_t)(n) << PORT_HWSEL_HW11_SHIFT) +#define PORT_HWSEL_HW12_SHIFT (24) /* Bit 24-25: Port 0 Pin 12 Hardware Select */ +#define PORT_HWSEL_HW12_MASK (3 << PORT_HWSEL_HW12_SHIFT) +# define PORT_HWSEL_HW12(n) ((uint32_t)(n) << PORT_HWSEL_HW12_SHIFT) +#define PORT_HWSEL_HW13_SHIFT (26) /* Bit 26-27: Port 0 Pin 13 Hardware Select */ +#define PORT_HWSEL_HW13_MASK (3 << PORT_HWSEL_HW13_SHIFT) +# define PORT_HWSEL_HW13(n) ((uint32_t)(n) << PORT_HWSEL_HW13_SHIFT) +#define PORT_HWSEL_HW14_SHIFT (28) /* Bit 28-29: Port 0 Pin 14 Hardware Select */ +#define PORT_HWSEL_HW14_MASK (3 << PORT_HWSEL_HW14_SHIFT) +# define PORT_HWSEL_HW14(n) 14uint32_t)(n) << PORT_HWSEL_HW14_SHIFT) +#define PORT_HWSEL_HW15_SHIFT (30) /* Bit 30-31: Port 0 Pin 15 Hardware Select */ +#define PORT_HWSEL_HW15_MASK (3 << PORT_HWSEL_HW15_SHIFT) +# define PORT_HWSEL_HW15(n) ((uint32_t)(n) << PORT_HWSEL_HW15_SHIFT) #endif /* __ARCH_ARM_SRC_XMC4_CHIP_XMC4_SCU_H */ From 8f91c73304e5236a90f760373f23637aad378f8a Mon Sep 17 00:00:00 2001 From: Pascal Speck Date: Fri, 17 Mar 2017 15:13:03 +0100 Subject: [PATCH 18/81] - fixed wrong assert on udp dgram send --- net/udp/udp_psock_send.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/net/udp/udp_psock_send.c b/net/udp/udp_psock_send.c index e3e2eb0c881..c701fe064d7 100644 --- a/net/udp/udp_psock_send.c +++ b/net/udp/udp_psock_send.c @@ -78,7 +78,7 @@ ssize_t psock_udp_send(FAR struct socket *psock, FAR const void *buf, socklen_t tolen; DEBUGASSERT(psock != NULL && psock->s_crefs > 0); - DEBUGASSERT(psock->s_type != SOCK_DGRAM); + DEBUGASSERT(psock->s_type == SOCK_DGRAM); conn = (FAR struct udp_conn_s *)psock->s_conn; DEBUGASSERT(conn); From 042b33414abe8950d7dd7223490846681b46957c Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 17 Mar 2017 08:28:40 -0600 Subject: [PATCH 19/81] XMC4xxx: Missing OMR field in PORT register definition header file. --- arch/arm/src/xmc4/chip/xmc4_ports.h | 28 ++++++++++++++++++++-------- 1 file changed, 20 insertions(+), 8 deletions(-) diff --git a/arch/arm/src/xmc4/chip/xmc4_ports.h b/arch/arm/src/xmc4/chip/xmc4_ports.h index 1d6cfa6b428..1465c41a648 100644 --- a/arch/arm/src/xmc4/chip/xmc4_ports.h +++ b/arch/arm/src/xmc4/chip/xmc4_ports.h @@ -239,25 +239,37 @@ /* Register Bit-Field Definitions **************************************************/ -/* Port Output Register, Port Output Modification Register, Port Input Register, - * Port Pin Function Decision Control Register, Port Pin Power Save Register. +/* Port Output Register, , Port Input Register, Port Pin Function Decision Control + * Register, Port Pin Power Save Register. */ #define PORT_PIN(n) (1 << (n)) +/* Port Output Modification Register: + * + * PRx PSx Function + * 0 0 Bit Pn_OUT.Px is not changed. + * 0 1 Bit Pn_OUT.Px is set. + * 1 0 Bit Pn_OUT.Px is reset. + * 1 1 Bit Pn_OUT.Px is toggled. + */ + +#define OMR_PS(n) (1 << (n)) +#define OMR_PR(n) (1 << ((n) + 16)) + /* Basic port input/output field values */ /* Director Input */ -#define IOCR_NOPULL 0 /* No internal pull device active */ -#define IOCR_PULLDOWN 1 /* Internal pull-down device active */ -#define IOCR_PULLUP 2 /* Internal pull-down device active */ -#define IOCR_CONT 3 /* No internal pull device active; Pn_OUTx continuously - * samples the input value */ +#define IOCR_NOPULL 0 /* No internal pull device active */ +#define IOCR_PULLDOWN 1 /* Internal pull-down device active */ +#define IOCR_PULLUP 2 /* Internal pull-down device active */ +#define IOCR_CONT 3 /* No internal pull device active; Pn_OUTx + * continuously samples the input value */ /* Any of the above may be OR'ed with */ /* Inverted Input */ -#define IOCR_INVERT 4 /* Inverted input */ +#define IOCR_INVERT 4 /* Inverted input */ /* Port Input/Output Control Register 0 */ From d2d54b4ae70f0a85bdad8cb35dc521f524541564 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 17 Mar 2017 11:18:24 -0600 Subject: [PATCH 20/81] XMC4xxx: Add framework and definitions for GPIO support --- arch/arm/src/xmc4/chip/xmc4_ports.h | 37 +++-- arch/arm/src/xmc4/xmc4_gpio.c | 98 ++++++++++++ arch/arm/src/xmc4/xmc4_gpio.h | 222 ++++++++++++++++++++++++++++ arch/arm/src/xmc4/xmc4_lowputc.c | 2 +- arch/arm/src/xmc4/xmc4_serial.c | 2 +- arch/arm/src/xmc4/xmc4_start.c | 2 + 6 files changed, 349 insertions(+), 14 deletions(-) diff --git a/arch/arm/src/xmc4/chip/xmc4_ports.h b/arch/arm/src/xmc4/chip/xmc4_ports.h index 1465c41a648..3478d9dedb2 100644 --- a/arch/arm/src/xmc4/chip/xmc4_ports.h +++ b/arch/arm/src/xmc4/chip/xmc4_ports.h @@ -1,7 +1,7 @@ /************************************************************************************ * arch/arm/src/xmc4/chip/xmc4_ports.h * - * Copyright (C /*2017 Gregory Nutt. All rights reserved. + * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Reference: XMC4500 Reference Manual V1.5 2014-07 Microcontrollers. @@ -27,17 +27,17 @@ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION /*HOWEVER CAUSED + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE /*ARISING IN + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * * May include some logic from sample code provided by Infineon: * - * Copyright (C /*2011-2015 Infineon Technologies AG. All rights reserved. + * Copyright (C) 2011-2015 Infineon Technologies AG. All rights reserved. * - * Infineon Technologies AG (Infineon /*is supplying this software for use with + * Infineon Technologies AG (Infineon) is supplying this software for use with * Infineon's microcontrollers. This file can be freely distributed within * development tools that are supporting such microcontrollers. * @@ -258,18 +258,31 @@ #define OMR_PR(n) (1 << ((n) + 16)) /* Basic port input/output field values */ -/* Director Input */ +/* Direct Input */ -#define IOCR_NOPULL 0 /* No internal pull device active */ -#define IOCR_PULLDOWN 1 /* Internal pull-down device active */ -#define IOCR_PULLUP 2 /* Internal pull-down device active */ -#define IOCR_CONT 3 /* No internal pull device active; Pn_OUTx +#define IOCR_INPUT_NOPULL 0 /* No internal pull device active */ +#define IOCR_INPUT_PULLDOWN 1 /* Internal pull-down device active */ +#define IOCR_INPUT_PULLUP 2 /* Internal pull-down device active */ +#define IOCR_INPUT_CONT 3 /* No internal pull device active; Pn_OUTx * continuously samples the input value */ -/* Any of the above may be OR'ed with */ +/* Any of the above input configurations may be OR'ed with */ /* Inverted Input */ -#define IOCR_INVERT 4 /* Inverted input */ +#define IOCR_INPUT_INVERT 4 /* Inverted input modifier */ + +/* Push-pull Output (direct input) */ + +#define IOCR_OUTPUT 16 /* General-purpose output */ +#define IOCR_OUTPUT_ALT1 17 /* Alternate output function 1 */ +#define IOCR_OUTPUT_ALT2 18 /* Alternate output function 2 */ +#define IOCR_OUTPUT_ALT3 19 /* Alternate output function 3 */ +#define IOCR_OUTPUT_ALT4 20 /* Alternate output function 4 */ + +/* Any of the above may be OR'ed with */ +/* Open drain output */ + +#define IOCR_OUTPUT_OPENDRAIN 8 /* Output drain output modifier */ /* Port Input/Output Control Register 0 */ diff --git a/arch/arm/src/xmc4/xmc4_gpio.c b/arch/arm/src/xmc4/xmc4_gpio.c index e69de29bb2d..4080a0be992 100644 --- a/arch/arm/src/xmc4/xmc4_gpio.c +++ b/arch/arm/src/xmc4/xmc4_gpio.c @@ -0,0 +1,98 @@ +/**************************************************************************** + * arch/arm/src/xmc4/xmc4_gpio.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include +#include + +#include + +#include "up_arch.h" +#include "up_internal.h" + +#include "chip/xmc4_ports.h" +#include "xmc4_gpio.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: xmc4_gpio_config + * + * Description: + * Configure a PIN based on bit-encoded description of the pin, + * 'pincconfig'. + * + ****************************************************************************/ + +int xmc4_gpio_config(gpioconfig_t pinconfig) +{ +#warning Missing logic + return -EINVAL; +} + +/**************************************************************************** + * Name: xmc4_gpio_write + * + * Description: + * Write one or zero to the PORT pin selected by 'pinconfig' + * + ****************************************************************************/ + +void xmc4_gpio_write(gpioconfig_t pinconfig, bool value) +{ +#warning Missing logic +} + +/**************************************************************************** + * Name: xmc4_gpio_read + * + * Description: + * Read one or zero from the PORT pin selected by 'pinconfig' + * + ****************************************************************************/ + +bool xmc4_gpio_read(gpioconfig_t pinconfig) +{ +#warning Missing logic + return false; +} diff --git a/arch/arm/src/xmc4/xmc4_gpio.h b/arch/arm/src/xmc4/xmc4_gpio.h index e69de29bb2d..44ab0bde538 100644 --- a/arch/arm/src/xmc4/xmc4_gpio.h +++ b/arch/arm/src/xmc4/xmc4_gpio.h @@ -0,0 +1,222 @@ +/**************************************************************************** + * arch/arm/src/xmc4/xmc4_gpio.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "chip/xmc4_ports.h" + +/**************************************************************************** + * Preprocessor Definitions + ****************************************************************************/ + +/* 32-bit GIO encoding: + * + * .... TTTT TMDD DCC. .... .... PPPP BBBB + */ + + +/* This identifies the GPIO pint type: + * + * .... TTTT T... .... .... .... .... .... + */ + +#define GPIO_PINTYPE_SHIFT (23) /* Bits 23-27: Pin type */ +#define GPIO_PINTYPE_MASK (31 << GPIO_PINTYPE_SHIFT) + +/* See chip/xmc4_ports.h for the IOCR definitions */ +/* Direct input */ + +# define GPIO_INPUT_NOPULL (IOCR_INPUT_NOPULL << GPIO_PINTYPE_SHIFT) +# define GPIO_INPUT_PULLDOWN (IOCR_INPUT_PULLDOWN << GPIO_PINTYPE_SHIFT) +# define GPIO_INPUT_PULLUP (IOCR_INPUT_PULLUP << GPIO_PINTYPE_SHIFT) +# define GPIO_INPUT_CONT (IOCR_INPUT_CONT << GPIO_PINTYPE_SHIFT) + +/* Push-pull Output (direct input) */ + +# define GPIO_OUTPUT (IOCR_OUTPUT << GPIO_PINTYPE_SHIFT) +# define GPIO_OUTPUT_ALT1 (IOCR_OUTPUT_ALT1 << GPIO_PINTYPE_SHIFT) +# define GPIO_OUTPUT_ALT2 (IOCR_OUTPUT_ALT2 << GPIO_PINTYPE_SHIFT) +# define GPIO_OUTPUT_ALT3 (IOCR_OUTPUT_ALT3 << GPIO_PINTYPE_SHIFT) +# define GPIO_OUTPUT_ALT4 (IOCR_OUTPUT_ALT4 << GPIO_PINTYPE_SHIFT) + +# define _GPIO_OUTPUT_BIT (16 << GPIO_PINTYPE_SHIFT) +# define GPIO_ISINPUT(p) (((p) & _GPIO_OUTPUT_BIT) != 0) +# define GPIO_ISOUTPUT(p) (((p) & _GPIO_OUTPUT_BIT) == 0) + +/* Pin type modifier: + * + * .... .... .M.. .... .... .... .... .... + */ + +#define GPIO_INPUT_INVERT (1 << 22) /* Inverted input modifier */ +#define GPIOS_OUTPUT_OPENDRAIN (1 << 22) /* Output drain output modifier */ + +/* Pad driver strength: + * + * .... .... ..DD D... .... .... .... .... + */ + +#define GPIO_PADTYPE_SHIFT (19) /* Bits 19-21: Pad driver strength */ +#define GPIO_PADTYPE_MASK (7 << GPIO_PADTYPE_SHIFT) + +/* See chip/xmc4_ports.h for the PDR definitions */ +/* Pad class A1: */ + +# define GPIO_PADA1_MEDIUM (PDR_PADA1_MEDIUM << GPIO_PADTYPE_SHIFT) +# define GPIO_PADA1_WEAK (PDR_PADA1_WEAK << GPIO_PADTYPE_SHIFT) + +/* Pad class A1+: */ + +# define GPIO_PADA1P_STRONGSOFT (PDR_PADA1P_STRONGSOFT << GPIO_PADTYPE_SHIFT) +# define GPIO_PADA1P_STRONGSLOW (PDR_PADA1P_STRONGSLOW << GPIO_PADTYPE_SHIFT) +# define GPIO_PADA1P_MEDIUM (PDR_PADA1P_MEDIUM << GPIO_PADTYPE_SHIFT) +# define GPIO_PADA1P_WEAK (PDR_PADA1P_WEAK << GPIO_PADTYPE_SHIFT) + +/* Pad class A2: */ + +# define GPIO_PADA2_STRONGSHARP (PDR_PADA2_STRONGSHARP << GPIO_PADTYPE_SHIFT) +# define GPIO_PADA2_STRONGMEDIUM (PDR_PADA2_STRONGMEDIUM << GPIO_PADTYPE_SHIFT) +# define GPIO_PADA2_STRONGSOFT (PDR_PADA2_STRONGSOFT << GPIO_PADTYPE_SHIFT) +# define GPIO_PADA2_MEDIUM (PDR_PADA2_MEDIUM << GPIO_PADTYPE_SHIFT) +# define GPIO_PADA2_WEAK (PDR_PADA2_WEAK << GPIO_PADTYPE_SHIFT) + +/* Pin control: + * + * .... .... .... .CC. .... .... .... .... + */ + +#define GPIO_PINCTRL_SHIFT (17) /* Bits 17-18: Pad driver strength */ +#define GPIO_PINCTRL_MASK (3 << GPIO_PINCTRL_SHIFT) + +/* See chip/xmc4_ports.h for the PDR definitions */ + +# define GPIO_PINCTRL_SOFTWARE (HWSEL_SOFTWARE << GPIO_PINCTRL_SHIFT) +# define GPIO_PINCTRL_OVERRIDE0 (HWSEL_OVERRIDE0 << GPIO_PINCTRL_SHIFT) +# define GPIO_PINCTRL_OVERRIDE1 (HWSEL_OVERRIDE1 << GPIO_PINCTRL_SHIFT) + +/* This identifies the GPIO port: + * + * .... ... .... .... .... .... PPPP .... + */ + +#define GPIO_PORT_SHIFT (4) /* Bit 4-7: Port number */ +#define GPIO_PORT_MASK (7 << GPIO_PORT_SHIFT) +# define GPIO_PORT0 (0 << GPIO_PORT_SHIFT) +# define GPIO_PORT1 (1 << GPIO_PORT_SHIFT) +# define GPIO_PORT2 (2 << GPIO_PORT_SHIFT) +# define GPIO_PORT3 (3 << GPIO_PORT_SHIFT) +# define GPIO_PORT4 (4 << GPIO_PORT_SHIFT) +# define GPIO_PORT5 (5 << GPIO_PORT_SHIFT) +# define GPIO_PORT6 (6 << GPIO_PORT_SHIFT) +# define GPIO_PORT7 (7 << GPIO_PORT_SHIFT) +# define GPIO_PORT8 (8 << GPIO_PORT_SHIFT) +# define GPIO_PORT9 (9 << GPIO_PORT_SHIFT) +# define GPIO_PORT14 (14 << GPIO_PORT_SHIFT) +# define GPIO_PORT15 (15 << GPIO_PORT_SHIFT) + +/* This identifies the bit in the port: + * + * ... ..... .... .... .... .... .... BBBB + */ + +#define GPIO_PIN_SHIFT (0) /* Bits 0-3: GPIO pin: 0-15 */ +#define GPIO_PIN_MASK (31 << GPIO_PIN_SHIFT) +#define GPIO_PIN0 (0 << GPIO_PIN_SHIFT) +#define GPIO_PIN1 (1 << GPIO_PIN_SHIFT) +#define GPIO_PIN2 (2 << GPIO_PIN_SHIFT) +#define GPIO_PIN3 (3 << GPIO_PIN_SHIFT) +#define GPIO_PIN4 (4 << GPIO_PIN_SHIFT) +#define GPIO_PIN5 (5 << GPIO_PIN_SHIFT) +#define GPIO_PIN6 (6 << GPIO_PIN_SHIFT) +#define GPIO_PIN7 (7 << GPIO_PIN_SHIFT) +#define GPIO_PIN8 (8 << GPIO_PIN_SHIFT) +#define GPIO_PIN9 (9 << GPIO_PIN_SHIFT) +#define GPIO_PIN10 (10 << GPIO_PIN_SHIFT) +#define GPIO_PIN11 (11 << GPIO_PIN_SHIFT) +#define GPIO_PIN12 (12 << GPIO_PIN_SHIFT) +#define GPIO_PIN13 (13 << GPIO_PIN_SHIFT) +#define GPIO_PIN14 (14 << GPIO_PIN_SHIFT) +#define GPIO_PIN15 (15 << GPIO_PIN_SHIFT) + + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* This is a type large enought to hold all pin configuration bits. */ + +typedef uint32_t gpioconfig_t; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: xmc4_gpio_config + * + * Description: + * Configure a PIN based on bit-encoded description of the pin, + * 'pincconfig'. + * + ****************************************************************************/ + +int xmc4_gpio_config(gpioconfig_t pinconfig); + +/**************************************************************************** + * Name: xmc4_gpio_write + * + * Description: + * Write one or zero to the PORT pin selected by 'pinconfig' + * + ****************************************************************************/ + +void xmc4_gpio_write(gpioconfig_t pinconfig, bool value); + +/**************************************************************************** + * Name: xmc4_gpio_read + * + * Description: + * Read one or zero from the PORT pin selected by 'pinconfig' + * + ****************************************************************************/ + +bool xmc4_gpio_read(gpioconfig_t pinconfig); diff --git a/arch/arm/src/xmc4/xmc4_lowputc.c b/arch/arm/src/xmc4/xmc4_lowputc.c index 8fe2f4094b8..ec44caba54a 100644 --- a/arch/arm/src/xmc4/xmc4_lowputc.c +++ b/arch/arm/src/xmc4/xmc4_lowputc.c @@ -48,7 +48,7 @@ #include "up_arch.h" #include "xmc4_config.h" -#include "chip/xmc4_uart.h" +#include "chip/xmc4_usic.h" #include "chip/xmc4_pinmux.h" /**************************************************************************** diff --git a/arch/arm/src/xmc4/xmc4_serial.c b/arch/arm/src/xmc4/xmc4_serial.c index b90f1c19ff1..509cca56156 100644 --- a/arch/arm/src/xmc4/xmc4_serial.c +++ b/arch/arm/src/xmc4/xmc4_serial.c @@ -59,7 +59,7 @@ #include "xmc4_config.h" #include "chip.h" -#include "chip/xmc4_uart.h" +#include "chip/xmc4_usic.h" /**************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/xmc4/xmc4_start.c b/arch/arm/src/xmc4/xmc4_start.c index e712f97dd37..7bf76f1faef 100644 --- a/arch/arm/src/xmc4/xmc4_start.c +++ b/arch/arm/src/xmc4/xmc4_start.c @@ -46,11 +46,13 @@ #include #include +#include "nvic.h" #include "up_arch.h" #include "up_internal.h" #include "chip/xmc4_flash.h" #include "xmc4_userspace.h" +#include "xmc4_start.h" #ifdef CONFIG_ARCH_FPU # include "nvic.h" From 41758d8e4c274df26b4bc0373c322c6090899aa1 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 17 Mar 2017 11:22:42 -0600 Subject: [PATCH 21/81] XMC4xxx: minor update to GPIO definitions. --- arch/arm/src/xmc4/xmc4_gpio.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/src/xmc4/xmc4_gpio.h b/arch/arm/src/xmc4/xmc4_gpio.h index 44ab0bde538..716d821192e 100644 --- a/arch/arm/src/xmc4/xmc4_gpio.h +++ b/arch/arm/src/xmc4/xmc4_gpio.h @@ -87,8 +87,10 @@ * .... .... .M.. .... .... .... .... .... */ -#define GPIO_INPUT_INVERT (1 << 22) /* Inverted input modifier */ -#define GPIOS_OUTPUT_OPENDRAIN (1 << 22) /* Output drain output modifier */ +#define GPIO_INPUT_INVERT (1 << 22) /* Inverted direct input modifier */ + +#define GPIOS_OUTPUT_PUSHPULL (0) /* Push-ull output is the default */ +#define GPIOS_OUTPUT_OPENDRAIN (1 << 22) /* Output drain output modifier */ /* Pad driver strength: * From 8bfb735351850e374a435a5fb116e8fbe3b5fc37 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 17 Mar 2017 13:02:07 -0600 Subject: [PATCH 22/81] XMC4xxx: Finishes implementation of GPIO support. --- arch/arm/src/xmc4/chip/xmc4_memorymap.h | 1 + arch/arm/src/xmc4/chip/xmc4_ports.h | 8 + arch/arm/src/xmc4/xmc4_gpio.c | 399 +++++++++++++++++++++++- arch/arm/src/xmc4/xmc4_gpio.h | 75 +++-- 4 files changed, 450 insertions(+), 33 deletions(-) diff --git a/arch/arm/src/xmc4/chip/xmc4_memorymap.h b/arch/arm/src/xmc4/chip/xmc4_memorymap.h index c2b847d4e07..ea41ac30b1b 100644 --- a/arch/arm/src/xmc4/chip/xmc4_memorymap.h +++ b/arch/arm/src/xmc4/chip/xmc4_memorymap.h @@ -148,6 +148,7 @@ #define XMC4_USIC2_CH0_BASE 0x48024000 #define XMC4_USIC2_CH1_BASE 0x48024200 #define XMC4_USIC2_RAM_BASE 0x48024400 +#define XMC4_PORT_BASE(n) (0x48028000 + ((n) << 8)) #define XMC4_PORT0_BASE 0x48028000 #define XMC4_PORT1_BASE 0x48028100 #define XMC4_PORT2_BASE 0x48028200 diff --git a/arch/arm/src/xmc4/chip/xmc4_ports.h b/arch/arm/src/xmc4/chip/xmc4_ports.h index 3478d9dedb2..588965c9f0b 100644 --- a/arch/arm/src/xmc4/chip/xmc4_ports.h +++ b/arch/arm/src/xmc4/chip/xmc4_ports.h @@ -58,6 +58,8 @@ #include +#include "chip/xmc4_memorymap.h" + /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ @@ -68,13 +70,19 @@ #define XMC4_PORT_OUT_OFFSET 0x0000 /* Port Output Register */ #define XMC4_PORT_OMR_OFFSET 0x0004 /* Port Output Modification Register */ + +#define XMC4_PORT_IOCR_OFFSET(n) (0x0010 + ((n) & 3)) #define XMC4_PORT_IOCR0_OFFSET 0x0010 /* Port Input/Output Control Register 0 */ #define XMC4_PORT_IOCR4_OFFSET 0x0014 /* Port Input/Output Control Register 4 */ #define XMC4_PORT_IOCR8_OFFSET 0x0018 /* Port Input/Output Control Register 8 */ #define XMC4_PORT_IOCR12_OFFSET 0x001c /* Port Input/Output Control Register 12 */ + #define XMC4_PORT_IN_OFFSET 0x0024 /* Port Input Register */ + +#define XMC4_PORT_PDR_OFFSET(n) (0x0010 + (((n) >> 1) & 3)) #define XMC4_PORT_PDR0_OFFSET 0x0040 /* Port Pad Driver Mode 0 Register */ #define XMC4_PORT_PDR1_OFFSET 0x0044 /* Port Pad Driver Mode 1 Register */ + #define XMC4_PORT_PDISC_OFFSET 0x0060 /* Port Pin Function Decision Control Register */ #define XMC4_PORT_PPS_OFFSET 0x0070 /* Port Pin Power Save Register */ #define XMC4_PORT_HWSEL_OFFSET 0x0074 /* Port Pin Hardware Select Register */ diff --git a/arch/arm/src/xmc4/xmc4_gpio.c b/arch/arm/src/xmc4/xmc4_gpio.c index 4080a0be992..2bc8f108282 100644 --- a/arch/arm/src/xmc4/xmc4_gpio.c +++ b/arch/arm/src/xmc4/xmc4_gpio.c @@ -44,6 +44,7 @@ #include #include +#include #include "up_arch.h" #include "up_internal.h" @@ -51,6 +52,301 @@ #include "chip/xmc4_ports.h" #include "xmc4_gpio.h" +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: xmc4_gpio_getreg + * + * Description: + * Return the pin number for this pin configuration + * + ****************************************************************************/ + +static inline uint32_t xmc4_gpio_getreg(uintptr_t portbase, + unsigned int offset) +{ + return getreg32(portbase + offset); +} + +/**************************************************************************** + * Name: xmc4_gpio_putreg + * + * Description: + * Return the pin number for this pin configuration + * + ****************************************************************************/ + +static inline void xmc4_gpio_putreg(uintptr_t portbase, unsigned int offset, + uint32_t regval) +{ + putreg32(regval, portbase + offset); +} + +/**************************************************************************** + * Name: xmc4_gpio_port + * + * Description: + * Return the port number for this pin configuration + * + ****************************************************************************/ + +static inline int xmc4_gpio_port(gpioconfig_t pinconfig) +{ + return ((pinconfig & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT); +} + +/**************************************************************************** + * Name: xmc4_gpio_portbase + * + * Description: + * Return the base address of the port register for this pin configuration. + * + ****************************************************************************/ + +static uintptr_t xmc4_gpio_portbase(gpioconfig_t pinconfig) +{ + return XMC4_PORT_BASE(xmc4_gpio_port(pinconfig)); +} + +/**************************************************************************** + * Name: xmc4_gpio_pin + * + * Description: + * Return the pin number for this pin configuration + * + ****************************************************************************/ + +static unsigned int xmc4_gpio_pin(gpioconfig_t pinconfig) +{ + return ((pinconfig & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT); +} + +/**************************************************************************** + * Name: xmc4_gpio_pintype + * + * Description: + * Return the pintype for this pin configuration + * + ****************************************************************************/ + +static inline unsigned int xmc4_gpio_pintype(gpioconfig_t pinconfig) +{ + return ((pinconfig & GPIO_PINTYPE_MASK) >> GPIO_PINTYPE_SHIFT); +} + +/**************************************************************************** + * Name: xmc4_gpio_pinctrl + * + * Description: + * Return the pintype for this pin configuration + * + ****************************************************************************/ + +static inline unsigned int xmc4_gpio_pinctrl(gpioconfig_t pinconfig) +{ + return ((pinconfig & GPIO_PINCTRL_MASK) >> GPIO_PINCTRL_SHIFT); +} + +/**************************************************************************** + * Name: xmc4_gpio_padtype + * + * Description: + * Return the padtype for this pin configuration + * + ****************************************************************************/ + +static inline unsigned int xmc4_gpio_padtype(gpioconfig_t pinconfig) +{ + return ((pinconfig & GPIO_PADTYPE_MASK) >> GPIO_PADTYPE_SHIFT); +} + +/**************************************************************************** + * Name: xmc4_gpio_iocr + * + * Description: + * Update the IOCR register + * + ****************************************************************************/ + +static void xmc4_gpio_iocr(uintptr_t portbase, unsigned int pin, + unsigned int value) +{ + uint32_t regval; + uint32_t mask; + unsigned int offset; + unsigned int shift; + + /* Read the IOCR register */ + + offset = XMC4_PORT_IOCR_OFFSET(pin); + regval = xmc4_gpio_getreg(portbase, offset); + + /* Set the new value for this field */ + + pin &= 3; + shift = PORT_IOCR0_PC_SHIFT(pin); + mask = PORT_IOCR0_PC_MASK(pin); + + regval &= ~mask; + regval |= (uint32_t)value << shift; + + xmc4_gpio_putreg(portbase, offset, regval); +} + +/**************************************************************************** + * Name: xmc4_gpio_hwsel + * + * Description: + * Update the HWSEL register + * + ****************************************************************************/ + +static inline void xmc4_gpio_hwsel(uintptr_t portbase, unsigned int pin, + unsigned int value) +{ + uint32_t regval; + uint32_t mask; + unsigned int shift; + + /* Read the HWSEL register */ + + regval = xmc4_gpio_getreg(portbase, XMC4_PORT_HWSEL_OFFSET); + + /* Set the new value for this field */ + + shift = PORT_HWSEL_HW_SHIFT(pin); + mask = PORT_HWSEL_HW_MASK(pin); + + regval &= ~mask; + regval |= (uint32_t)value << shift; + + xmc4_gpio_putreg(portbase, XMC4_PORT_HWSEL_OFFSET, regval); +} + +/**************************************************************************** + * Name: xmc4_gpio_pdisc + * + * Description: + * Update the PDISC register + * + ****************************************************************************/ + +static inline void xmc4_gpio_pdisc(uintptr_t portbase, unsigned int pin, + bool value) +{ + uint32_t regval; + uint32_t mask; + + /* Read the PDISC register */ + + regval = xmc4_gpio_getreg(portbase, XMC4_PORT_PDISC_OFFSET); + + /* Set/clear the enable/disable (or analg) value for this field */ + + mask = PORT_PIN(pin); + if (value) + { + regval |= mask; + } + else + { + regval &= ~mask; + } + + xmc4_gpio_putreg(portbase, XMC4_PORT_PDISC_OFFSET, regval); +} + +/**************************************************************************** + * Name: xmc4_gpio_pps + * + * Description: + * Update the PPS register + * + ****************************************************************************/ + +static inline void xmc4_gpio_pps(uintptr_t portbase, unsigned int pin, + bool value) +{ + uint32_t regval; + uint32_t mask; + + /* Read the PPS register */ + + regval = xmc4_gpio_getreg(portbase, XMC4_PORT_PPS_OFFSET); + + /* Set/clear the enable/disable (or analg) value for this field */ + + mask = PORT_PIN(pin); + if (value) + { + regval |= mask; + } + else + { + regval &= ~mask; + } + + xmc4_gpio_putreg(portbase, XMC4_PORT_PPS_OFFSET, regval); +} + +/**************************************************************************** + * Name: xmc4_gpio_pdr + * + * Description: + * Update the IOCR register + * + ****************************************************************************/ + +static void xmc4_gpio_pdr(uintptr_t portbase, unsigned int pin, + unsigned int value) +{ + uint32_t regval; + uint32_t mask; + unsigned int offset; + unsigned int shift; + + /* Read the PDRregister */ + + offset = XMC4_PORT_PDR_OFFSET(pin); + regval = xmc4_gpio_getreg(portbase, offset); + + /* Set the new value for this field */ + + pin &= 7; + shift = PORT_PDR0_PD_SHIFT(pin); + mask = PORT_PDR0_PD_MASK(pin); + + regval &= ~mask; + regval |= (uint32_t)value << shift; + + xmc4_gpio_putreg(portbase, offset, regval); +} + +/**************************************************************************** + * Name: xmc4_gpio_inverted + * + * Description: + * Check if the input is inverted + * + ****************************************************************************/ + +static inline bool xmc4_gpio_inverted(gpioconfig_t pinconfig) +{ + return ((pinconfig & GPIO_INPUT_INVERT) != 0); +} + +/**************************************************************************** + * Name: xmc4_gpio_opendrain + * + * Description: + * Check if the output is opendram + * + ****************************************************************************/ + +#define xmc4_gpio_opendrain(p) xmc4_gpio_inverted(p) + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -66,8 +362,71 @@ int xmc4_gpio_config(gpioconfig_t pinconfig) { -#warning Missing logic - return -EINVAL; + uintptr_t portbase = xmc4_gpio_portbase(pinconfig); + unsigned int pin = xmc4_gpio_pin(pinconfig); + unsigned int value; + irqstate_t flags; + + flags = enter_critical_section(); + if (GPIO_ISINPUT(pinconfig)) + { + /* Get input pin type (IOCR) */ + + value = xmc4_gpio_pintype(pinconfig); + + /* Check if the input is inverted */ + + if (xmc4_gpio_inverted(pinconfig)) + { + value |= IOCR_INPUT_INVERT; + } + } + else + { + /* Force input while we configure */ + + xmc4_gpio_iocr(portbase, pin, IOCR_INPUT_NOPULL); + + /* Set output value before enabling output */ + + xmc4_gpio_write(pinconfig, ((pinconfig & GPIO_OUTPUT_SET) != 0)); + + /* Get output pin type (IOCR) */ + + value = xmc4_gpio_pintype(pinconfig); + + /* Get if the output is opendrain */ + + if (xmc4_gpio_opendrain(pinconfig)) + { + value |= IOCR_OUTPUT_OPENDRAIN; + } + } + + /* Update the IOCR register to instantiate the pin type */ + + xmc4_gpio_iocr(portbase, pin, value); + + /* Select pin control (HWSEL) */ + + value = xmc4_gpio_pinctrl(pinconfig); + xmc4_gpio_hwsel(portbase, pin, value); + + /* Select drive strength */ + + value = xmc4_gpio_padtype(pinconfig); + xmc4_gpio_pdr(portbase, pin, value); + + /* Enable/enable pad or Analog only (PDISC) */ + + xmc4_gpio_pdisc(portbase, pin, ((pinconfig & GPIO_PAD_DISABLE) != 0)); + + /* Make sure pin is not in power save mode (PDR) */ + + xmc4_gpio_pdisc(portbase, pin, false); + + leave_critical_section(flags); + return OK; } /**************************************************************************** @@ -80,7 +439,28 @@ int xmc4_gpio_config(gpioconfig_t pinconfig) void xmc4_gpio_write(gpioconfig_t pinconfig, bool value) { -#warning Missing logic + uintptr_t portbase = xmc4_gpio_portbase(pinconfig); + unsigned int pin = xmc4_gpio_pin(pinconfig); + uint32_t regval; + uint32_t mask; + + /* Read the OUT register */ + + regval = xmc4_gpio_getreg(portbase, XMC4_PORT_OUT_OFFSET); + + /* Set/clear output value for this pin */ + + mask = PORT_PIN(pin); + if (value) + { + regval |= mask; + } + else + { + regval &= ~mask; + } + + xmc4_gpio_putreg(portbase, XMC4_PORT_OUT_OFFSET, regval); } /**************************************************************************** @@ -93,6 +473,15 @@ void xmc4_gpio_write(gpioconfig_t pinconfig, bool value) bool xmc4_gpio_read(gpioconfig_t pinconfig) { -#warning Missing logic - return false; + uintptr_t portbase = xmc4_gpio_portbase(pinconfig); + unsigned int pin = xmc4_gpio_pin(pinconfig); + uint32_t regval; + + /* Read the OUT register */ + + regval = xmc4_gpio_getreg(portbase, XMC4_PORT_IN_OFFSET); + + /* Return in the input state for this pin */ + + return ((regval & PORT_PIN(pin)) != 0); } diff --git a/arch/arm/src/xmc4/xmc4_gpio.h b/arch/arm/src/xmc4/xmc4_gpio.h index 716d821192e..62b11bf048c 100644 --- a/arch/arm/src/xmc4/xmc4_gpio.h +++ b/arch/arm/src/xmc4/xmc4_gpio.h @@ -50,16 +50,16 @@ /* 32-bit GIO encoding: * - * .... TTTT TMDD DCC. .... .... PPPP BBBB + * TTTT TMPD DDCC V.... .... .... PPPP BBBB */ /* This identifies the GPIO pint type: * - * .... TTTT T... .... .... .... .... .... + * TTTT T... .... .... .... .... .... .... */ -#define GPIO_PINTYPE_SHIFT (23) /* Bits 23-27: Pin type */ +#define GPIO_PINTYPE_SHIFT (27) /* Bits 27-31: Pin type */ #define GPIO_PINTYPE_MASK (31 << GPIO_PINTYPE_SHIFT) /* See chip/xmc4_ports.h for the IOCR definitions */ @@ -84,60 +84,79 @@ /* Pin type modifier: * - * .... .... .M.. .... .... .... .... .... + * .... .M.. .... .... .... .... .... .... */ -#define GPIO_INPUT_INVERT (1 << 22) /* Inverted direct input modifier */ +#define GPIO_INPUT_INVERT (1 << 26) /* Bit 26: Inverted direct input modifier */ -#define GPIOS_OUTPUT_PUSHPULL (0) /* Push-ull output is the default */ -#define GPIOS_OUTPUT_OPENDRAIN (1 << 22) /* Output drain output modifier */ +#define GPIO_OUTPUT_OPENDRAIN (1 << 26) /* Bit 26: Output drain output modifier */ +#define GPIO_OUTPUT_PUSHPULL (0) /* Push-pull output is the default */ + +/* Disable PAD: + * + * .... ..P. .... ..... .... .... .... .... + * + * For P0-P6, the PDISC register is ready only. + * For P14-P15, the bit setting also selects Analog+Digital or Analog only + */ + +#define GPIO_PAD_DISABLE (1 << 25) /* Bit 25: Disable Pad (P7-P9) */ +#define GPIO_PAD_ANALOG (1 << 25) /* Bit 25: Analog only (P14-P15) */ /* Pad driver strength: * - * .... .... ..DD D... .... .... .... .... + * .... ...D DD.. ..... .... ......... .... */ -#define GPIO_PADTYPE_SHIFT (19) /* Bits 19-21: Pad driver strength */ -#define GPIO_PADTYPE_MASK (7 << GPIO_PADTYPE_SHIFT) +#define GPIO_PADTYPE_SHIFT (22) /* Bits 22-24: Pad driver strength */ +#define GPIO_PADTYPE_MASK (7 << GPIO_PADTYPE_SHIFT) /* See chip/xmc4_ports.h for the PDR definitions */ /* Pad class A1: */ -# define GPIO_PADA1_MEDIUM (PDR_PADA1_MEDIUM << GPIO_PADTYPE_SHIFT) -# define GPIO_PADA1_WEAK (PDR_PADA1_WEAK << GPIO_PADTYPE_SHIFT) +# define GPIO_PADA1_MEDIUM (PDR_PADA1_MEDIUM << GPIO_PADTYPE_SHIFT) +# define GPIO_PADA1_WEAK (PDR_PADA1_WEAK << GPIO_PADTYPE_SHIFT) /* Pad class A1+: */ -# define GPIO_PADA1P_STRONGSOFT (PDR_PADA1P_STRONGSOFT << GPIO_PADTYPE_SHIFT) -# define GPIO_PADA1P_STRONGSLOW (PDR_PADA1P_STRONGSLOW << GPIO_PADTYPE_SHIFT) -# define GPIO_PADA1P_MEDIUM (PDR_PADA1P_MEDIUM << GPIO_PADTYPE_SHIFT) -# define GPIO_PADA1P_WEAK (PDR_PADA1P_WEAK << GPIO_PADTYPE_SHIFT) +# define GPIO_PADA1P_STRONGSOFT (PDR_PADA1P_STRONGSOFT << GPIO_PADTYPE_SHIFT) +# define GPIO_PADA1P_STRONGSLOW (PDR_PADA1P_STRONGSLOW << GPIO_PADTYPE_SHIFT) +# define GPIO_PADA1P_MEDIUM (PDR_PADA1P_MEDIUM << GPIO_PADTYPE_SHIFT) +# define GPIO_PADA1P_WEAK (PDR_PADA1P_WEAK << GPIO_PADTYPE_SHIFT) /* Pad class A2: */ -# define GPIO_PADA2_STRONGSHARP (PDR_PADA2_STRONGSHARP << GPIO_PADTYPE_SHIFT) -# define GPIO_PADA2_STRONGMEDIUM (PDR_PADA2_STRONGMEDIUM << GPIO_PADTYPE_SHIFT) -# define GPIO_PADA2_STRONGSOFT (PDR_PADA2_STRONGSOFT << GPIO_PADTYPE_SHIFT) -# define GPIO_PADA2_MEDIUM (PDR_PADA2_MEDIUM << GPIO_PADTYPE_SHIFT) -# define GPIO_PADA2_WEAK (PDR_PADA2_WEAK << GPIO_PADTYPE_SHIFT) +# define GPIO_PADA2_STRONGSHARP (PDR_PADA2_STRONGSHARP << GPIO_PADTYPE_SHIFT) +# define GPIO_PADA2_STRONGMEDIUM (PDR_PADA2_STRONGMEDIUM << GPIO_PADTYPE_SHIFT) +# define GPIO_PADA2_STRONGSOFT (PDR_PADA2_STRONGSOFT << GPIO_PADTYPE_SHIFT) +# define GPIO_PADA2_MEDIUM (PDR_PADA2_MEDIUM << GPIO_PADTYPE_SHIFT) +# define GPIO_PADA2_WEAK (PDR_PADA2_WEAK << GPIO_PADTYPE_SHIFT) /* Pin control: * - * .... .... .... .CC. .... .... .... .... + * .... .... ..CC ..... .... .... .... .... */ -#define GPIO_PINCTRL_SHIFT (17) /* Bits 17-18: Pad driver strength */ -#define GPIO_PINCTRL_MASK (3 << GPIO_PINCTRL_SHIFT) +#define GPIO_PINCTRL_SHIFT (20) /* Bits 20-21: Pad driver strength */ +#define GPIO_PINCTRL_MASK (3 << GPIO_PINCTRL_SHIFT) /* See chip/xmc4_ports.h for the PDR definitions */ -# define GPIO_PINCTRL_SOFTWARE (HWSEL_SOFTWARE << GPIO_PINCTRL_SHIFT) -# define GPIO_PINCTRL_OVERRIDE0 (HWSEL_OVERRIDE0 << GPIO_PINCTRL_SHIFT) -# define GPIO_PINCTRL_OVERRIDE1 (HWSEL_OVERRIDE1 << GPIO_PINCTRL_SHIFT) +# define GPIO_PINCTRL_SOFTWARE (HWSEL_SOFTWARE << GPIO_PINCTRL_SHIFT) +# define GPIO_PINCTRL_OVERRIDE0 (HWSEL_OVERRIDE0 << GPIO_PINCTRL_SHIFT) +# define GPIO_PINCTRL_OVERRIDE1 (HWSEL_OVERRIDE1 << GPIO_PINCTRL_SHIFT) + +/* If the pin is an GPIO output, then this identifies the initial output value: + * + * .... .... .... V.... .... .... PPPP BBBB + */ + +#define GPIO_OUTPUT_SET (1 << 19) /* Bit 19: Initial value of output */ +#define GPIO_OUTPUT_CLEAR (0) /* This identifies the GPIO port: * - * .... ... .... .... .... .... PPPP .... + * .... .... .... .... .... .... PPPP .... */ #define GPIO_PORT_SHIFT (4) /* Bit 4-7: Port number */ From 5ae9564b7d2eab24ff753f7fdd0c5902180d137a Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 17 Mar 2017 16:26:11 -0600 Subject: [PATCH 23/81] XMC4xxx: GPIO write should use OMR, not OUTPUT register. --- arch/arm/src/xmc4/xmc4_gpio.c | 35 +++++++++++++++++++++++------------ 1 file changed, 23 insertions(+), 12 deletions(-) diff --git a/arch/arm/src/xmc4/xmc4_gpio.c b/arch/arm/src/xmc4/xmc4_gpio.c index 2bc8f108282..e26967f06f3 100644 --- a/arch/arm/src/xmc4/xmc4_gpio.c +++ b/arch/arm/src/xmc4/xmc4_gpio.c @@ -442,25 +442,34 @@ void xmc4_gpio_write(gpioconfig_t pinconfig, bool value) uintptr_t portbase = xmc4_gpio_portbase(pinconfig); unsigned int pin = xmc4_gpio_pin(pinconfig); uint32_t regval; - uint32_t mask; - /* Read the OUT register */ + /* Setup OMR value for this pin: + * + * PRx PSx Function + * 0 0 Bit Pn_OUT.Px is not changed. + * 0 1 Bit Pn_OUT.Px is set. + * 1 0 Bit Pn_OUT.Px is reset. + * 1 1 Bit Pn_OUT.Px is toggled. + */ - regval = xmc4_gpio_getreg(portbase, XMC4_PORT_OUT_OFFSET); - - /* Set/clear output value for this pin */ - - mask = PORT_PIN(pin); if (value) { - regval |= mask; + /* PRx==0; PSx==1 -> Set output */ + + regval = OMR_PS(pin); } else { - regval &= ~mask; + /* PRx==1; PSx==0 -> Reset output */ + + regval = OMR_PR(pin); } - xmc4_gpio_putreg(portbase, XMC4_PORT_OUT_OFFSET, regval); + /* Set/clear the OUTPUT. This is an atomoc operation so no critical + * section is needed. + */ + + xmc4_gpio_putreg(portbase, XMC4_PORT_OMR_OFFSET, regval); } /**************************************************************************** @@ -477,11 +486,13 @@ bool xmc4_gpio_read(gpioconfig_t pinconfig) unsigned int pin = xmc4_gpio_pin(pinconfig); uint32_t regval; - /* Read the OUT register */ + /* Read the OUT register. This is an atomoc operation so no critical + * section is needed. + */ regval = xmc4_gpio_getreg(portbase, XMC4_PORT_IN_OFFSET); - /* Return in the input state for this pin */ + /* Return in the input state for this pin at the time is was read */ return ((regval & PORT_PIN(pin)) != 0); } From 7bde01df98890f1b774c27f224a03ebd54995255 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 17 Mar 2017 16:40:29 -0600 Subject: [PATCH 24/81] XMC4C: Clean up some naming, fix some comments, add empty PINMUX header file. --- arch/arm/src/xmc4/chip/xmc4_flash.h | 2 +- arch/arm/src/xmc4/chip/xmc4_memorymap.h | 2 +- arch/arm/src/xmc4/chip/xmc4_pinmux.h | 52 +++++++++++++++++++++++++ arch/arm/src/xmc4/chip/xmc4_ports.h | 12 +++--- arch/arm/src/xmc4/chip/xmc4_usic.h | 2 +- arch/arm/src/xmc4/xmc4_gpio.h | 6 +-- 6 files changed, 64 insertions(+), 12 deletions(-) create mode 100644 arch/arm/src/xmc4/chip/xmc4_pinmux.h diff --git a/arch/arm/src/xmc4/chip/xmc4_flash.h b/arch/arm/src/xmc4/chip/xmc4_flash.h index e68e7078e9c..37afed16a2e 100644 --- a/arch/arm/src/xmc4/chip/xmc4_flash.h +++ b/arch/arm/src/xmc4/chip/xmc4_flash.h @@ -200,4 +200,4 @@ #define FLASH_PROCON2_S12_S13ROM (1 << 11) /* Bit 11: Sectors 12 and 13 Locked Forever by User 2 */ #define FLASH_PROCON2_S14_S15ROM (1 << 12) /* Bit 12: Sectors 14 and 15 Locked Forever by User 2 */ -#endif /* __ARCH_ARM_SRC_XMC4_CHIP_XMC4_SCU_H */ +#endif /* __ARCH_ARM_SRC_XMC4_CHIP_XMC4_FLASH_H */ diff --git a/arch/arm/src/xmc4/chip/xmc4_memorymap.h b/arch/arm/src/xmc4/chip/xmc4_memorymap.h index ea41ac30b1b..fb8dcbf183b 100644 --- a/arch/arm/src/xmc4/chip/xmc4_memorymap.h +++ b/arch/arm/src/xmc4/chip/xmc4_memorymap.h @@ -228,4 +228,4 @@ #define XMC4_PPB_BASE 0xe000e000 -#endif /* __ARCH_ARM_SRC_XMC4_CHIP_XMC4_SCU_H */ +#endif /* __ARCH_ARM_SRC_XMC4_CHIP_XMC4_MEMORYMAP_H */ diff --git a/arch/arm/src/xmc4/chip/xmc4_pinmux.h b/arch/arm/src/xmc4/chip/xmc4_pinmux.h new file mode 100644 index 00000000000..44d43074a83 --- /dev/null +++ b/arch/arm/src/xmc4/chip/xmc4_pinmux.h @@ -0,0 +1,52 @@ +/************************************************************************************ + * arch/arm/src/xmc4/chip/xmc4_pinmux.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Reference: XMC4500 Reference Manual V1.5 2014-07 Microcontrollers. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_XMC4_CHIP_XMC4_PINMUX_H +#define __ARCH_ARM_SRC_XMC4_CHIP_XMC4_PINMUX_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + + +#endif /* __ARCH_ARM_SRC_XMC4_CHIP_XMC4_PINMXU_H */ diff --git a/arch/arm/src/xmc4/chip/xmc4_ports.h b/arch/arm/src/xmc4/chip/xmc4_ports.h index 588965c9f0b..bdd90c2902b 100644 --- a/arch/arm/src/xmc4/chip/xmc4_ports.h +++ b/arch/arm/src/xmc4/chip/xmc4_ports.h @@ -447,11 +447,11 @@ /* Hardware select field values */ -#define HWSEL_SOFTWARE 0 /* Software control only */ -#define HWSEL_OVERRIDE0 1 /* HWI0/HWO0 control path can override the - * software configuration */ -#define HWSEL_OVERRIDE1 2 /* HWI1/HWO1 control path can override the - * software configuration */ +#define HWSEL_SW 0 /* Software control only */ +#define HWSEL_HW0 1 /* HWI0/HWO0 control path can override + * the software configuration */ +#define HWSEL_HW1 2 /* HWI1/HWO1 control path can override + * the software configuration */ /* Port Pin Hardware Select Register */ @@ -507,4 +507,4 @@ #define PORT_HWSEL_HW15_MASK (3 << PORT_HWSEL_HW15_SHIFT) # define PORT_HWSEL_HW15(n) ((uint32_t)(n) << PORT_HWSEL_HW15_SHIFT) -#endif /* __ARCH_ARM_SRC_XMC4_CHIP_XMC4_SCU_H */ +#endif /* __ARCH_ARM_SRC_XMC4_CHIP_XMC4_PORTS_H */ diff --git a/arch/arm/src/xmc4/chip/xmc4_usic.h b/arch/arm/src/xmc4/chip/xmc4_usic.h index 089a14811fc..1b3c4d2bdca 100644 --- a/arch/arm/src/xmc4/chip/xmc4_usic.h +++ b/arch/arm/src/xmc4/chip/xmc4_usic.h @@ -472,4 +472,4 @@ /* Transmit FIFO Buffer (32 x 4-bytes) */ #define USIC_IN_ -#endif /* __ARCH_ARM_SRC_XMC4_CHIP_XMC4_SCU_H */ +#endif /* __ARCH_ARM_SRC_XMC4_CHIP_XMC4_USIC_H */ diff --git a/arch/arm/src/xmc4/xmc4_gpio.h b/arch/arm/src/xmc4/xmc4_gpio.h index 62b11bf048c..c1bf09b87bd 100644 --- a/arch/arm/src/xmc4/xmc4_gpio.h +++ b/arch/arm/src/xmc4/xmc4_gpio.h @@ -142,9 +142,9 @@ /* See chip/xmc4_ports.h for the PDR definitions */ -# define GPIO_PINCTRL_SOFTWARE (HWSEL_SOFTWARE << GPIO_PINCTRL_SHIFT) -# define GPIO_PINCTRL_OVERRIDE0 (HWSEL_OVERRIDE0 << GPIO_PINCTRL_SHIFT) -# define GPIO_PINCTRL_OVERRIDE1 (HWSEL_OVERRIDE1 << GPIO_PINCTRL_SHIFT) +# define GPIO_PINCTRL_SOFTWARE (HWSEL_SW << GPIO_PINCTRL_SHIFT) +# define GPIO_PINCTRL_HW0 (HWSEL_HW0 << GPIO_PINCTRL_SHIFT) +# define GPIO_PINCTRL_HW1 (HWSEL_HW1 << GPIO_PINCTRL_SHIFT) /* If the pin is an GPIO output, then this identifies the initial output value: * From c6d5d3bdedd77e7430b58214fa871cb5e9c1b4e8 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 17 Mar 2017 16:44:26 -0600 Subject: [PATCH 25/81] XMC4xxx: All register definition files need to include memorymap.h --- arch/arm/src/xmc4/chip/xmc4_flash.h | 2 ++ arch/arm/src/xmc4/chip/xmc4_usic.h | 2 ++ arch/arm/src/xmc4/xmc4_gpio.h | 6 +++--- 3 files changed, 7 insertions(+), 3 deletions(-) diff --git a/arch/arm/src/xmc4/chip/xmc4_flash.h b/arch/arm/src/xmc4/chip/xmc4_flash.h index 37afed16a2e..0432e465b0a 100644 --- a/arch/arm/src/xmc4/chip/xmc4_flash.h +++ b/arch/arm/src/xmc4/chip/xmc4_flash.h @@ -58,6 +58,8 @@ #include +#include "chip/xmc4_memorymap.h" + /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ diff --git a/arch/arm/src/xmc4/chip/xmc4_usic.h b/arch/arm/src/xmc4/chip/xmc4_usic.h index 1b3c4d2bdca..8b91e88583a 100644 --- a/arch/arm/src/xmc4/chip/xmc4_usic.h +++ b/arch/arm/src/xmc4/chip/xmc4_usic.h @@ -58,6 +58,8 @@ #include +#include "chip/xmc4_memorymap.h" + /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ diff --git a/arch/arm/src/xmc4/xmc4_gpio.h b/arch/arm/src/xmc4/xmc4_gpio.h index c1bf09b87bd..49b80ba1968 100644 --- a/arch/arm/src/xmc4/xmc4_gpio.h +++ b/arch/arm/src/xmc4/xmc4_gpio.h @@ -142,9 +142,9 @@ /* See chip/xmc4_ports.h for the PDR definitions */ -# define GPIO_PINCTRL_SOFTWARE (HWSEL_SW << GPIO_PINCTRL_SHIFT) -# define GPIO_PINCTRL_HW0 (HWSEL_HW0 << GPIO_PINCTRL_SHIFT) -# define GPIO_PINCTRL_HW1 (HWSEL_HW1 << GPIO_PINCTRL_SHIFT) +# define GPIO_PINCTRL_SOFTWARE (HWSEL_SW << GPIO_PINCTRL_SHIFT) +# define GPIO_PINCTRL_HW0 (HWSEL_HW0 << GPIO_PINCTRL_SHIFT) +# define GPIO_PINCTRL_HW1 (HWSEL_HW1 << GPIO_PINCTRL_SHIFT) /* If the pin is an GPIO output, then this identifies the initial output value: * From ac0d957f26a8214835df6cfcd0bfcd89d6ce863e Mon Sep 17 00:00:00 2001 From: Jussi Kivilinna Date: Fri, 17 Mar 2017 17:32:44 -0600 Subject: [PATCH 26/81] libc: printf: fix precision for string formatting. Fixes use of format precision to truncate input string. --- libc/stdio/lib_libvsprintf.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/libc/stdio/lib_libvsprintf.c b/libc/stdio/lib_libvsprintf.c index 894f0404538..1a3501c704a 100644 --- a/libc/stdio/lib_libvsprintf.c +++ b/libc/stdio/lib_libvsprintf.c @@ -1171,9 +1171,7 @@ int lib_vsprintf(FAR struct lib_outstream_s *obj, FAR const IPTR char *src, FAR char *ptmp; #ifndef CONFIG_NOPRINTF_FIELDWIDTH int width; -#ifdef CONFIG_LIBC_FLOATINGPOINT int trunc; -#endif uint8_t fmt; #endif uint8_t flags; @@ -1215,9 +1213,7 @@ int lib_vsprintf(FAR struct lib_outstream_s *obj, FAR const IPTR char *src, #ifndef CONFIG_NOPRINTF_FIELDWIDTH fmt = FMT_RJUST; width = 0; -#ifdef CONFIG_LIBC_FLOATINGPOINT trunc = 0; -#endif #endif /* Process each format qualifier. */ @@ -1265,10 +1261,8 @@ int lib_vsprintf(FAR struct lib_outstream_s *obj, FAR const IPTR char *src, int value = va_arg(ap, int); if (IS_HASDOT(flags)) { -#ifdef CONFIG_LIBC_FLOATINGPOINT trunc = value; SET_HASASTERISKTRUNC(flags); -#endif } else { @@ -1307,9 +1301,7 @@ int lib_vsprintf(FAR struct lib_outstream_s *obj, FAR const IPTR char *src, if (IS_HASDOT(flags)) { -#ifdef CONFIG_LIBC_FLOATINGPOINT trunc = n; -#endif } else { @@ -1361,6 +1353,7 @@ int lib_vsprintf(FAR struct lib_outstream_s *obj, FAR const IPTR char *src, { #ifndef CONFIG_NOPRINTF_FIELDWIDTH int swidth; + int left; #endif /* Get the string to output */ @@ -1375,13 +1368,21 @@ int lib_vsprintf(FAR struct lib_outstream_s *obj, FAR const IPTR char *src, */ #ifndef CONFIG_NOPRINTF_FIELDWIDTH - swidth = strlen(ptmp); + swidth = (IS_HASDOT(flags) && trunc >= 0) + ? strnlen(ptmp, trunc) : strlen(ptmp); prejustify(obj, fmt, 0, width, swidth); + left = swidth; #endif /* Concatenate the string into the output */ while (*ptmp) { +#ifndef CONFIG_NOPRINTF_FIELDWIDTH + if (left-- <= 0) + { + break; + } +#endif obj->put(obj, *ptmp); ptmp++; } From acec5e3199e13e2d772e3340b2f73a0bf424c5d9 Mon Sep 17 00:00:00 2001 From: Jussi Kivilinna Date: Fri, 17 Mar 2017 17:34:56 -0600 Subject: [PATCH 27/81] vsnprintf(): If size is zero, then vsnprintf() should return the size of the required buffer without writing anything. This is same fix that was done for snprintf in 2014 by commit 59846a8fe928abb389e3776ebdbb52022da45be3. --- libc/stdio/lib_vsnprintf.c | 35 ++++++++++++++++++++++++++++------- 1 file changed, 28 insertions(+), 7 deletions(-) diff --git a/libc/stdio/lib_vsnprintf.c b/libc/stdio/lib_vsnprintf.c index d25fc0d2d53..40f7dffc502 100644 --- a/libc/stdio/lib_vsnprintf.c +++ b/libc/stdio/lib_vsnprintf.c @@ -55,17 +55,38 @@ int vsnprintf(FAR char *buf, size_t size, FAR const IPTR char *format, va_list ap) { - struct lib_memoutstream_s memoutstream; - int n; + union + { + struct lib_outstream_s nulloutstream; + struct lib_memoutstream_s memoutstream; + } u; - /* Initialize a memory stream to write to the buffer */ + FAR struct lib_outstream_s *stream; + int n; - lib_memoutstream((FAR struct lib_memoutstream_s *)&memoutstream, - buf, size); + /* "If the value of [size] is zero on a call to vsnprintf(), nothing shall + * be written, the number of bytes that would have been written had [size] + * been sufficiently large excluding the terminating null shall be returned, + * and [buf] may be a null pointer." -- opengroup.org + */ + + if (size > 0) + { + /* Initialize a memory stream to write to the buffer */ + + lib_memoutstream(&u.memoutstream, buf, size); + stream = &u.memoutstream.public; + } + else + { + /* Use a null stream to get the size of the buffer */ + + lib_nulloutstream(&u.nulloutstream); + stream = &u.nulloutstream; + } /* Then let lib_vsprintf do the real work */ - n = lib_vsprintf((FAR struct lib_outstream_s *)&memoutstream.public, - format, ap); + n = lib_vsprintf(stream, format, ap); return n; } From 0a95536b850ce4a8513989ab9c6b088e84a122a3 Mon Sep 17 00:00:00 2001 From: Brian Webb Date: Fri, 17 Mar 2017 20:35:49 -0700 Subject: [PATCH 28/81] Adds driver support for the XBox One controller. Currently only the latest version (XBox One X) controller works. The older XBox One controllers do not enumerate correctly. --- configs/stm32f4discovery/src/stm32_usb.c | 13 +- drivers/usbhost/Kconfig | 32 + drivers/usbhost/Make.defs | 4 + drivers/usbhost/usbhost_xboxcontroller.c | 2195 ++++++++++++++++++++++ include/nuttx/input/xbox-controller.h | 88 + include/nuttx/usb/usbhost.h | 21 + 6 files changed, 2352 insertions(+), 1 deletion(-) create mode 100644 drivers/usbhost/usbhost_xboxcontroller.c create mode 100644 include/nuttx/input/xbox-controller.h diff --git a/configs/stm32f4discovery/src/stm32_usb.c b/configs/stm32f4discovery/src/stm32_usb.c index c929c1bfe2c..f0d2e161705 100644 --- a/configs/stm32f4discovery/src/stm32_usb.c +++ b/configs/stm32f4discovery/src/stm32_usb.c @@ -167,7 +167,8 @@ int stm32_usbhost_initialize(void) { int pid; #if defined(CONFIG_USBHOST_HUB) || defined(CONFIG_USBHOST_MSC) || \ - defined(CONFIG_USBHOST_HIDKBD) || defined(CONFIG_USBHOST_HIDMOUSE) + defined(CONFIG_USBHOST_HIDKBD) || defined(CONFIG_USBHOST_HIDMOUSE) || \ + defined(CONFIG_USBHOST_XBOXCONTROLLER) int ret; #endif @@ -227,6 +228,16 @@ int stm32_usbhost_initialize(void) } #endif +#ifdef CONFIG_USBHOST_XBOXCONTROLLER + /* Initialize the HID mouse class */ + + ret = usbhost_xboxcontroller_init(); + if (ret != OK) + { + uerr("ERROR: Failed to register the XBox Controller class\n"); + } +#endif + /* Then get an instance of the USB host interface */ uinfo("Initialize USB host\n"); diff --git a/drivers/usbhost/Kconfig b/drivers/usbhost/Kconfig index 334e393f51c..5e49aa7b864 100644 --- a/drivers/usbhost/Kconfig +++ b/drivers/usbhost/Kconfig @@ -521,6 +521,38 @@ config RTL8187_PID endif # USBHOST_RTL8187 +config USBHOST_XBOXCONTROLLER + bool "Xbox Controller Support" + default n + depends on !INT_DISABLE + select INPUT + ---help--- + Enable support for the Xbox Controller driver. + +if USBHOST_XBOXCONTROLLER + +config XBOXCONTROLLER_DEFPRIO + int "Polling Thread Priority" + default 50 + ---help--- + Priority of the polling thread. Default: 50. + +config XBOXCONTROLLER_STACKSIZE + int "Polling thread stack size" + default 1024 + ---help--- + Stack size for polling thread. Default: 1024 + +config XBOXCONTROLLER_NPOLLWAITERS + int "Max Number of Waiters for Poll Event" + default 2 + depends on !DISABLE_POLL + ---help--- + If the poll() method is enabled, this defines the maximum number + of threads that can be waiting for mouse events. Default: 2. + +endif # USBHOST_XBOXCONTROLLER + config USBHOST_TRACE bool "Enable USB HCD tracing for debug" default n diff --git a/drivers/usbhost/Make.defs b/drivers/usbhost/Make.defs index fd28be8766f..105156aee36 100644 --- a/drivers/usbhost/Make.defs +++ b/drivers/usbhost/Make.defs @@ -66,6 +66,10 @@ ifeq ($(CONFIG_USBHOST_HIDMOUSE),y) CSRCS += usbhost_hidmouse.c endif +ifeq ($(CONFIG_USBHOST_XBOXCONTROLLER),y) +CSRCS += usbhost_xboxcontroller.c +endif + # HCD debug/trace logic ifeq ($(CONFIG_USBHOST_TRACE),y) diff --git a/drivers/usbhost/usbhost_xboxcontroller.c b/drivers/usbhost/usbhost_xboxcontroller.c new file mode 100644 index 00000000000..fd12efee975 --- /dev/null +++ b/drivers/usbhost/usbhost_xboxcontroller.c @@ -0,0 +1,2195 @@ +/**************************************************************************** + * drivers/usbhost/usbhost_xboxcontroller.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifndef CONFIG_SCHED_WORKQUEUE +# warning "Worker thread support is required (CONFIG_SCHED_WORKQUEUE)" +#endif + +#ifndef CONFIG_XBOXCONTROLLER_DEFPRIO +# define CONFIG_XBOXCONTROLLER_DEFPRIO 50 +#endif + +#ifndef CONFIG_XBOXCONTROLLER_STACKSIZE +# define CONFIG_XBOXCONTROLLER_STACKSIZE 1024 +#endif + +#ifndef CONFIG_XBOXCONTROLLER_NPOLLWAITERS +# define CONFIG_XBOXCONTROLLER_NPOLLWAITERS 2 +#endif + +/* Driver support ***********************************************************/ +/* This format is used to construct the /dev/xbox[n] device driver path. It + * defined here so that it will be used consistently in all places. + */ + +#define DEV_FORMAT "/dev/xbox%c" +#define DEV_NAMELEN 11 + +/* Used in usbhost_cfgdesc() */ + +#define USBHOST_IFFOUND 0x01 +#define USBHOST_EPINFOUND 0x02 /* Required interrupt IN EP descriptor found */ +#define USBHOST_EPOUTFOUND 0x04 /* Required interrupt OUT EP descriptor found */ +#define USBHOST_ALLFOUND 0x07 + +#define USBHOST_MAX_CREFS 0x7fff + +/* Received message types */ + +#define USBHOST_WAITING_CONNECTION 0x02 +#define USBHOST_GUIDE_BUTTON_STATUS 0x07 +#define USBHOST_BUTTON_DATA 0x20 + +/* Button definitions */ + +#define XBOX_BUTTON_GUIDE_INDEX 4 +#define XBOX_BUTTON_SYNC_INDEX 4 +#define XBOX_BUTTON_SYNC_MASK (1 << 0) +#define XBOX_BUTTON_START_INDEX 4 +#define XBOX_BUTTON_START_MASK (1 << 2) +#define XBOX_BUTTON_BACK_INDEX 4 +#define XBOX_BUTTON_BACK_MASK (1 << 3) +#define XBOX_BUTTON_A_INDEX 4 +#define XBOX_BUTTON_A_MASK (1 << 4) +#define XBOX_BUTTON_B_INDEX 4 +#define XBOX_BUTTON_B_MASK (1 << 5) +#define XBOX_BUTTON_X_INDEX 4 +#define XBOX_BUTTON_X_MASK (1 << 6) +#define XBOX_BUTTON_Y_INDEX 4 +#define XBOX_BUTTON_Y_MASK (1 << 7) +#define XBOX_BUTTON_DPAD_UP_INDEX 5 +#define XBOX_BUTTON_DPAD_UP_MASK (1 << 0) +#define XBOX_BUTTON_DPAD_DOWN_INDEX 5 +#define XBOX_BUTTON_DPAD_DOWN_MASK (1 << 1) +#define XBOX_BUTTON_DPAD_LEFT_INDEX 5 +#define XBOX_BUTTON_DPAD_LEFT_MASK (1 << 2) +#define XBOX_BUTTON_DPAD_RIGHT_INDEX 5 +#define XBOX_BUTTON_DPAD_RIGHT_MASK (1 << 3) +#define XBOX_BUTTON_BUMPER_LEFT_INDEX 5 +#define XBOX_BUTTON_BUMPER_LEFT_MASK (1 << 4) +#define XBOX_BUTTON_BUMPER_RIGHT_INDEX 5 +#define XBOX_BUTTON_BUMPER_RIGHT_MASK (1 << 5) +#define XBOX_BUTTON_STICK_LEFT_INDEX 5 +#define XBOX_BUTTON_STICK_LEFT_MASK (1 << 6) +#define XBOX_BUTTON_STICK_RIGHT_INDEX 5 +#define XBOX_BUTTON_STICK_RIGHT_MASK (1 << 7) +#define XBOX_BUTTON_TRIGGER_LEFT 3 +#define XBOX_BUTTON_TRIGGER_RIGHT 4 +#define XBOX_BUTTON_STICK_LEFT_X 5 +#define XBOX_BUTTON_STICK_LEFT_Y 6 +#define XBOX_BUTTON_STICK_RIGHT_X 7 +#define XBOX_BUTTON_STICK_RIGHT_Y 8 +#define XBOX_BUTTON_SET(buffer, index, mask) ((((buffer)[(index)] & (mask)) != 0) ? true : false); + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* This structure contains the internal, private state of the USB host class + * driver. + */ + +struct usbhost_state_s +{ + /* This is the externally visible portion of the state */ + + struct usbhost_class_s usbclass; + + /* The remainder of the fields are provide to the class driver */ + + char devchar; /* Character identifying the /dev/xbox[n] device */ + volatile bool disconnected; /* TRUE: Device has been disconnected */ + volatile bool polling; /* TRUE: Poll thread is running */ + volatile bool open; /* TRUE: The controller device is open */ + volatile bool valid; /* TRUE: New sample data is available */ + volatile bool initialized; /* TRUE: The initialization packet has been sent */ + uint8_t ifno; /* Interface number */ + uint8_t nwaiters; /* Number of threads waiting for controller data */ + sem_t waitsem; /* Used to wait for controller data */ + int16_t crefs; /* Reference count on the driver instance */ + sem_t exclsem; /* Used to maintain mutual exclusive access */ + struct work_s work; /* For interacting with the worker thread */ + FAR uint8_t *tbuffer; /* The allocated transfer buffer */ + FAR uint8_t obuffer[20]; /* The fixed output transfer buffer */ + size_t tbuflen; /* Size of the allocated transfer buffer */ + usbhost_ep_t epin; /* IN endpoint */ + usbhost_ep_t epout; /* OUT endpoint */ + pid_t pollpid; /* PID of the poll task */ + size_t out_seq_num; /* The sequence number for outgoing packets */ + struct xbox_controller_buttonstate_s rpt; /* The latest report out of the controller. */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Semaphores */ + +static void usbhost_takesem(sem_t *sem); +#define usbhost_givesem(s) sem_post(s); + +/* Memory allocation services */ + +static inline FAR struct usbhost_state_s *usbhost_allocclass(void); +static inline void usbhost_freeclass(FAR struct usbhost_state_s *usbclass); + +/* Device name management */ + +static int usbhost_allocdevno(FAR struct usbhost_state_s *priv); +static void usbhost_freedevno(FAR struct usbhost_state_s *priv); +static inline void usbhost_mkdevname(FAR struct usbhost_state_s *priv, + FAR char *devname); + +/* Worker thread actions */ + +static void usbhost_destroy(FAR void *arg); +static void usbhost_notify(FAR struct usbhost_state_s *priv); +static int usbhost_xboxcontroller_poll(int argc, char *argv[]); + +/* Helpers for usbhost_connect() */ + +static inline int usbhost_cfgdesc(FAR struct usbhost_state_s *priv, + FAR const uint8_t *configdesc, + int desclen); +static inline int usbhost_devinit(FAR struct usbhost_state_s *priv); + +/* (Little Endian) Data helpers */ + +static inline uint16_t usbhost_getle16(const uint8_t *val); +static inline void usbhost_putle16(uint8_t *dest, uint16_t val); +static inline uint32_t usbhost_getle32(const uint8_t *val); +#if 0 /* Not used */ +static void usbhost_putle32(uint8_t *dest, uint32_t val); +#endif + +/* Transfer descriptor memory management */ + +static inline int usbhost_talloc(FAR struct usbhost_state_s *priv); +static inline int usbhost_tfree(FAR struct usbhost_state_s *priv); + +/* struct usbhost_registry_s methods */ + +static struct usbhost_class_s *usbhost_create(FAR struct usbhost_hubport_s *hport, + FAR const struct usbhost_id_s *id); + +/* struct usbhost_class_s methods */ + +static int usbhost_connect(FAR struct usbhost_class_s *usbclass, + FAR const uint8_t *configdesc, int desclen); +static int usbhost_disconnected(FAR struct usbhost_class_s *usbclass); + +/* Driver methods. We export the controller as a standard character driver */ + +static int usbhost_open(FAR struct file *filep); +static int usbhost_close(FAR struct file *filep); +static ssize_t usbhost_read(FAR struct file *filep, + FAR char *buffer, size_t len); +static ssize_t usbhost_write(FAR struct file *filep, + FAR const char *buffer, size_t len); +static int usbhost_ioctl(FAR struct file* filep, int cmd, unsigned long arg); +#ifndef CONFIG_DISABLE_POLL +static int usbhost_poll(FAR struct file *filep, FAR struct pollfd *fds, + bool setup); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This structure provides the registry entry ID information that will be + * used to associate the USB class driver to a connected USB device. + */ + +static const const struct usbhost_id_s g_xboxcontroller_id[] = +{ + /* XBox One classic controller */ + { + USB_CLASS_VENDOR_SPEC, /* base -- Must be one of the USB_CLASS_* definitions in usb.h */ + 0x0047, /* subclass -- depends on the device */ + 0x00d0, /* proto -- depends on the device */ + 0x045E, /* vid */ + 0x02DD /* pid */ + }, + /* XBox One S controller */ + { + USB_CLASS_VENDOR_SPEC, /* base -- Must be one of the USB_CLASS_* definitions in usb.h */ + 0x0047, /* subclass -- depends on the device */ + 0x00d0, /* proto -- depends on the device */ + 0x045E, /* vid */ + 0x02EA /* pid */ + } +}; + +/* This is the USB host storage class's registry entry */ + +static struct usbhost_registry_s g_xboxcontroller = +{ + NULL, /* flink */ + usbhost_create, /* create */ + 2, /* nids */ + g_xboxcontroller_id /* id[] */ +}; + +/* The configuration information for the block file device. */ + +static const struct file_operations g_xboxcontroller_fops = +{ + usbhost_open, /* open */ + usbhost_close, /* close */ + usbhost_read, /* read */ + usbhost_write, /* write */ + 0, /* seek */ + usbhost_ioctl /* ioctl */ +#ifndef CONFIG_DISABLE_POLL + , usbhost_poll /* poll */ +#endif +}; + +/* This is a bitmap that is used to allocate device names /dev/xboxa-z. */ + +static uint32_t g_devinuse; + +/* The following are used to managed the class creation operation */ + +static sem_t g_exclsem; /* For mutually exclusive thread creation */ +static sem_t g_syncsem; /* Thread data passing interlock */ +static struct usbhost_state_s *g_priv; /* Data passed to thread */ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: usbhost_takesem + * + * Description: + * This is just a wrapper to handle the annoying behavior of semaphore + * waits that return due to the receipt of a signal. + * + ****************************************************************************/ + +static void usbhost_takesem(sem_t *sem) +{ + /* Take the semaphore (perhaps waiting) */ + + while (sem_wait(sem) != 0) + { + /* The only case that an error should occur here is if the wait was + * awakened by a signal. + */ + + ASSERT(errno == EINTR); + } +} + +/**************************************************************************** + * Name: usbhost_allocclass + * + * Description: + * This is really part of the logic that implements the create() method + * of struct usbhost_registry_s. This function allocates memory for one + * new class instance. + * + * Input Parameters: + * None + * + * Returned Values: + * On success, this function will return a non-NULL instance of struct + * usbhost_class_s. NULL is returned on failure; this function will + * will fail only if there are insufficient resources to create another + * USB host class instance. + * + ****************************************************************************/ + +static inline FAR struct usbhost_state_s *usbhost_allocclass(void) +{ + FAR struct usbhost_state_s *priv; + + DEBUGASSERT(!up_interrupt_context()); + priv = (FAR struct usbhost_state_s *)kmm_malloc(sizeof(struct usbhost_state_s)); + uinfo("Allocated: %p\n", priv); + return priv; +} + +/**************************************************************************** + * Name: usbhost_freeclass + * + * Description: + * Free a class instance previously allocated by usbhost_allocclass(). + * + * Input Parameters: + * usbclass - A reference to the class instance to be freed. + * + * Returned Values: + * None + * + ****************************************************************************/ + +static inline void usbhost_freeclass(FAR struct usbhost_state_s *usbclass) +{ + DEBUGASSERT(usbclass != NULL); + + /* Free the class instance (perhaps calling sched_kmm_free() in case we are + * executing from an interrupt handler. + */ + + uinfo("Freeing: %p\n", usbclass); + kmm_free(usbclass); +} + +/**************************************************************************** + * Name: Device name management + * + * Description: + * Some tiny functions to coordinate management of device names. + * + ****************************************************************************/ + +static int usbhost_allocdevno(FAR struct usbhost_state_s *priv) +{ + irqstate_t flags; + int devno; + + flags = enter_critical_section(); + for (devno = 0; devno < 26; devno++) + { + uint32_t bitno = 1 << devno; + if ((g_devinuse & bitno) == 0) + { + g_devinuse |= bitno; + priv->devchar = 'a' + devno; + leave_critical_section(flags); + return OK; + } + } + + leave_critical_section(flags); + return -EMFILE; +} + +static void usbhost_freedevno(FAR struct usbhost_state_s *priv) +{ + int devno = 'a' - priv->devchar; + + if (devno >= 0 && devno < 26) + { + irqstate_t flags = enter_critical_section(); + g_devinuse &= ~(1 << devno); + leave_critical_section(flags); + } +} + +static inline void usbhost_mkdevname(FAR struct usbhost_state_s *priv, + FAR char *devname) +{ + (void)snprintf(devname, DEV_NAMELEN, DEV_FORMAT, priv->devchar); +} + +/**************************************************************************** + * Name: usbhost_destroy + * + * Description: + * The USB device has been disconnected and the reference count on the USB + * host class instance has gone to 1.. Time to destroy the USB host class + * instance. + * + * Input Parameters: + * arg - A reference to the class instance to be destroyed. + * + * Returned Values: + * None + * + ****************************************************************************/ + +static void usbhost_destroy(FAR void *arg) +{ + FAR struct usbhost_state_s *priv = (FAR struct usbhost_state_s *)arg; + FAR struct usbhost_hubport_s *hport; + char devname[DEV_NAMELEN]; + + DEBUGASSERT(priv != NULL && priv->usbclass.hport != NULL); + uinfo("crefs: %d\n", priv->crefs); + + hport = priv->usbclass.hport; + + DEBUGASSERT(hport->drvr); + + uinfo("crefs: %d\n", priv->crefs); + + /* Unregister the driver */ + + uinfo("Unregister driver\n"); + usbhost_mkdevname(priv, devname); + (void)unregister_driver(devname); + + /* Release the device name used by this connection */ + + usbhost_freedevno(priv); + + /* Free the interrupt endpoints */ + + if (priv->epin) + { + DRVR_EPFREE(hport->drvr, priv->epin); + } + + /* Free any transfer buffers */ + + usbhost_tfree(priv); + + /* Destroy the semaphores */ + + sem_destroy(&priv->exclsem); + sem_destroy(&priv->waitsem); + + /* Disconnect the USB host device */ + + DRVR_DISCONNECT(hport->drvr, hport); + + /* Free the function address assigned to this device */ + + usbhost_devaddr_destroy(hport, hport->funcaddr); + hport->funcaddr = 0; + + /* And free the class instance. */ + + usbhost_freeclass(priv); +} + +/**************************************************************************** + * Name: usbhost_notify + * + * Description: + * Wake any threads waiting for controller data + * + * Input Paramters: + * priv - A reference to the controller state structure. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void usbhost_notify(FAR struct usbhost_state_s *priv) +{ +#ifndef CONFIG_DISABLE_POLL + int i; +#endif + + /* If there are threads waiting for read data, then signal one of them + * that the read data is available. + */ + + if (priv->nwaiters > 0) + { + sem_post(&priv->waitsem); + } + + /* If there are threads waiting on poll() for controller data to become available, + * then wake them up now. NOTE: we wake up all waiting threads because we + * do not know that they are going to do. If they all try to read the data, + * then some make end up blocking after all. + */ + +#ifndef CONFIG_DISABLE_POLL + for (i = 0; i < CONFIG_XBOXCONTROLLER_NPOLLWAITERS; i++) + { + struct pollfd *fds = priv->fds[i]; + if (fds) + { + fds->revents |= POLLIN; + iinfo("Report events: %02x\n", fds->revents); + sem_post(fds->sem); + } + } +#endif +} + +/**************************************************************************** + * Name: usbhost_xboxcontroller_poll + * + * Description: + * Periodically check for new controller data. + * + * Input Parameters: + * arg - A reference to the class instance to be destroyed. + * + * Returned Values: + * None + * + ****************************************************************************/ + +static int usbhost_xboxcontroller_poll(int argc, char *argv[]) +{ + FAR struct usbhost_state_s *priv; + FAR struct usbhost_hubport_s *hport; + irqstate_t flags; +#if defined(CONFIG_DEBUG_USB) && defined(CONFIG_DEBUG_INFO) + unsigned int npolls = 0; +#endif + unsigned int nerrors = 0; + ssize_t nbytes; + int ret = OK; + + /* Synchronize with the start-up logic. Get the private instance, re-start + * the start-up logic, and wait a bit to make sure that all of the class + * creation logic has a chance to run to completion. + * + * NOTE: that the reference count is *not* incremented here. When the driver + * structure was created, it was created with a reference count of one. This + * thread is responsible for that count. The count will be decrement when + * this thread exits. + */ + + priv = g_priv; + DEBUGASSERT(priv != NULL && priv->usbclass.hport != NULL); + hport = priv->usbclass.hport; + + priv->polling = true; + usbhost_givesem(&g_syncsem); + sleep(1); + + /* Loop here until the device is disconnected */ + + uinfo("Entering poll loop\n"); + + while (!priv->disconnected) + { + /* Read the next ccontroller report. We will stall here until the + * controller sends data. + */ + + nbytes = DRVR_TRANSFER(hport->drvr, priv->epin, + priv->tbuffer, priv->tbuflen); + + /* Check for errors -- Bail if an excessive number of consecutive + * errors are encountered. + */ + + if (nbytes < 0) + { + /* If DRVR_TRANSFER() returns EAGAIN, that simply means that + * the devices was not ready and has NAK'ed the transfer. That + * should not be treated as an error (unless it persists for a + * long time). + */ + + if (nbytes != -EAGAIN) + { + + uerr("ERROR: DRVR_TRANSFER returned: %d/%u\n", + (int)nbytes, nerrors); + + if (++nerrors > 200) + { + uerr(" Too many errors... aborting: %d\n", nerrors); + ret = (int)nbytes; + break; + } + } + } + + /* The report was received correctly. */ + + else + { + + /* Success, reset the error counter */ + + nerrors = 0; + + /* The type of message is in the first byte */ + switch (priv->tbuffer[0]) + { + + case USBHOST_WAITING_CONNECTION: + + /* Send the initialization message when we received the + * the first waiting connection message. + */ + + if (!priv->initialized) { + + /* Get exclusive access to the controller state data */ + + usbhost_takesem(&priv->exclsem); + + priv->tbuffer[0] = 0x05; + priv->tbuffer[1] = 0x20; + priv->tbuffer[2] = priv->out_seq_num++; + priv->tbuffer[3] = 0x01; + priv->tbuffer[4] = 0x00; + nbytes = DRVR_TRANSFER(hport->drvr, priv->epout, + priv->tbuffer, 5); + priv->initialized = true; + + /* Release our lock on the state structure */ + + usbhost_givesem(&priv->exclsem); + } + + break; + + case USBHOST_GUIDE_BUTTON_STATUS: + + /* Get exclusive access to the controller state data */ + + usbhost_takesem(&priv->exclsem); + + /* Read the data out of the controller report. */ + + priv->rpt.guide = (priv->tbuffer[XBOX_BUTTON_GUIDE_INDEX] != 0) ? true : false; + + priv->valid = true; + + /* The One X controller requires an ACK of the guide button status message. */ + + if (priv->tbuffer[1] == 0x30) + { + + static const uint8_t guide_button_report_ack[] = { + 0x01, 0x20, 0x00, 0x09, 0x00, 0x07, 0x20, 0x02, + 0x00, 0x00, 0x00, 0x00, 0x00 + }; + + /* Remember the input packet sequence number. */ + + uint8_t seq_num = priv->tbuffer[2]; + + /* Copy the ACK packet into the transfer buffer. */ + + memcpy(priv->tbuffer, guide_button_report_ack, sizeof(guide_button_report_ack)); + + /* Ensure the sequence number is the same as the input packet. */ + + priv->tbuffer[2] = seq_num; + + /* Perform the transfer. */ + + nbytes = DRVR_TRANSFER(hport->drvr, priv->epout, + priv->tbuffer, sizeof(guide_button_report_ack)); + } + + /* Notify any waiters that new controller data is available */ + + usbhost_notify(priv); + + /* Release our lock on the state structure */ + + usbhost_givesem(&priv->exclsem); + + break; + + case USBHOST_BUTTON_DATA: + + /* Ignore the controller data if no task has opened the driver. */ + + if (priv->open) + { + /* Get exclusive access to the controller state data */ + + usbhost_takesem(&priv->exclsem); + + /* Read the data out of the controller report. */ + + priv->rpt.sync = XBOX_BUTTON_SET(priv->tbuffer, XBOX_BUTTON_SYNC_INDEX, XBOX_BUTTON_SYNC_MASK); + priv->rpt.start = XBOX_BUTTON_SET(priv->tbuffer, XBOX_BUTTON_START_INDEX, XBOX_BUTTON_START_MASK); + priv->rpt.back = XBOX_BUTTON_SET(priv->tbuffer, XBOX_BUTTON_BACK_INDEX, XBOX_BUTTON_BACK_MASK); + priv->rpt.a = XBOX_BUTTON_SET(priv->tbuffer, XBOX_BUTTON_A_INDEX, XBOX_BUTTON_A_MASK); + priv->rpt.b = XBOX_BUTTON_SET(priv->tbuffer, XBOX_BUTTON_B_INDEX, XBOX_BUTTON_B_MASK); + priv->rpt.x = XBOX_BUTTON_SET(priv->tbuffer, XBOX_BUTTON_X_INDEX, XBOX_BUTTON_X_MASK); + priv->rpt.y = XBOX_BUTTON_SET(priv->tbuffer, XBOX_BUTTON_Y_INDEX, XBOX_BUTTON_Y_MASK); + priv->rpt.dpad_up = XBOX_BUTTON_SET(priv->tbuffer, XBOX_BUTTON_DPAD_UP_INDEX, XBOX_BUTTON_DPAD_UP_MASK); + priv->rpt.dpad_down = XBOX_BUTTON_SET(priv->tbuffer, XBOX_BUTTON_DPAD_DOWN_INDEX, XBOX_BUTTON_DPAD_DOWN_MASK); + priv->rpt.dpad_left = XBOX_BUTTON_SET(priv->tbuffer, XBOX_BUTTON_DPAD_LEFT_INDEX, XBOX_BUTTON_DPAD_LEFT_MASK); + priv->rpt.dpad_right = XBOX_BUTTON_SET(priv->tbuffer, XBOX_BUTTON_DPAD_RIGHT_INDEX, XBOX_BUTTON_DPAD_RIGHT_MASK); + priv->rpt.bumper_left = XBOX_BUTTON_SET(priv->tbuffer, XBOX_BUTTON_BUMPER_LEFT_INDEX, XBOX_BUTTON_BUMPER_LEFT_MASK); + priv->rpt.bumper_right = XBOX_BUTTON_SET(priv->tbuffer, XBOX_BUTTON_BUMPER_RIGHT_INDEX, XBOX_BUTTON_BUMPER_RIGHT_MASK); + priv->rpt.stick_click_left = XBOX_BUTTON_SET(priv->tbuffer, XBOX_BUTTON_STICK_LEFT_INDEX, XBOX_BUTTON_STICK_LEFT_MASK); + priv->rpt.stick_click_right = XBOX_BUTTON_SET(priv->tbuffer, XBOX_BUTTON_STICK_RIGHT_INDEX, XBOX_BUTTON_STICK_RIGHT_MASK); + priv->rpt.trigger_left = ((int16_t*)(priv->tbuffer))[XBOX_BUTTON_TRIGGER_LEFT]; + priv->rpt.trigger_right = ((int16_t*)(priv->tbuffer))[XBOX_BUTTON_TRIGGER_RIGHT]; + priv->rpt.stick_left_x = ((int16_t*)(priv->tbuffer))[XBOX_BUTTON_STICK_LEFT_X]; + priv->rpt.stick_left_y = ((int16_t*)(priv->tbuffer))[XBOX_BUTTON_STICK_LEFT_Y]; + priv->rpt.stick_right_x = ((int16_t*)(priv->tbuffer))[XBOX_BUTTON_STICK_RIGHT_X]; + priv->rpt.stick_right_y = ((int16_t*)(priv->tbuffer))[XBOX_BUTTON_STICK_RIGHT_Y]; + + priv->valid = true; + + /* Notify any waiters that new controller data is available */ + + usbhost_notify(priv); + + /* Release our lock on the state structure */ + + usbhost_givesem(&priv->exclsem); + } + + break; + + default: + + uinfo("Received messge type: %x\n", priv->tbuffer[0]); + + } + + } + + /* If USB debug is on, then provide some periodic indication that + * polling is still happening. + */ + +#if defined(CONFIG_DEBUG_USB) && defined(CONFIG_DEBUG_INFO) + npolls++; + if ((npolls & 31) == 0) + { + uinfo("Still polling: %d\n", npolls); + } +#endif + } + + /* We get here when the driver is removed.. or when too many errors have + * been encountered. + * + * Make sure that we have exclusive access to the private data structure. + * There may now be other tasks with the character driver open and actively + * trying to interact with the class driver. + */ + + usbhost_takesem(&priv->exclsem); + + /* Indicate that we are no longer running and decrement the reference + * count held by this thread. If there are no other users of the class, + * we can destroy it now. Otherwise, we have to wait until the all + * of the file descriptors are closed. + */ + + uinfo("Controller removed, polling halted\n"); + + flags = enter_critical_section(); + priv->polling = false; + + /* Decrement the reference count held by this thread. */ + + DEBUGASSERT(priv->crefs > 0); + priv->crefs--; + + /* There are two possibilities: + * 1) The reference count is greater than zero. This means that there + * are still open references to the controller driver. In this case + * we need to wait until usbhost_close() is called and all of the + * open driver references are decremented. Then usbhost_destroy() can + * be called from usbhost_close(). + * 2) The reference count is now zero. This means that there are no + * further open references and we can call usbhost_destroy() now. + */ + + if (priv->crefs < 1) + { + /* Unregister the driver and destroy the instance (while we hold + * the semaphore!) + */ + + usbhost_destroy(priv); + } + else + { + /* No, we will destroy the driver instance when it is final open + * reference is closed + */ + + usbhost_givesem(&priv->exclsem); + } + + leave_critical_section(flags); + return ret; +} + +/**************************************************************************** + * Name: usbhost_sample + * + * Description: + * Check if new controller data is available + * + * Input Parameters: + * priv - controller state instance + * sample - The location to return the sample data + * + ****************************************************************************/ + +static int usbhost_sample(FAR struct usbhost_state_s *priv, + FAR struct xbox_controller_buttonstate_s *sample) +{ + irqstate_t flags; + int ret = -EAGAIN; + + /* Interrupts me be disabled when this is called to (1) prevent posting + * of semaphores from interrupt handlers, and (2) to prevent sampled data + * from changing until it has been reported. + */ + + flags = enter_critical_section(); + + /* Is there new mouse data available? */ + + if (priv->valid) + { + /* Return a copy of the sampled data. */ + + memcpy(sample, &priv->rpt, sizeof(struct xbox_controller_buttonstate_s)); + + /* The sample has been reported and is no longer valid */ + + priv->valid = false; + ret = OK; + } + + leave_critical_section(flags); + return ret; +} + +/**************************************************************************** + * Name: usbhost_waitsample + * + * Description: + * Wait for the next valid controller sample + * + * Input Parameters: + * priv - controller state instance + * sample - The location to return the sample data + * + ****************************************************************************/ + +static int usbhost_waitsample(FAR struct usbhost_state_s *priv, + FAR struct xbox_controller_buttonstate_s *sample) +{ + irqstate_t flags; + int ret; + + /* Interrupts me be disabled when this is called to (1) prevent posting + * of semaphores from interrupt handlers, and (2) to prevent sampled data + * from changing until it has been reported. + * + * In addition, we will also disable pre-emption to prevent other threads + * from getting control while we muck with the semaphores. + */ + + sched_lock(); + flags = enter_critical_section(); + + /* Now release the semaphore that manages mutually exclusive access to + * the device structure. This may cause other tasks to become ready to + * run, but they cannot run yet because pre-emption is disabled. + */ + + sem_post(&priv->exclsem); + + /* Try to get the a sample... if we cannot, then wait on the semaphore + * that is posted when new sample data is available. + */ + + while (usbhost_sample(priv, sample) < 0) + { + /* Wait for a change in the HIDMOUSE state */ + + iinfo("Waiting..\n"); + priv->nwaiters++; + ret = sem_wait(&priv->waitsem); + priv->nwaiters--; + + if (ret < 0) + { + /* If we are awakened by a signal, then we need to return + * the failure now. + */ + + ierr("ERROR: sem_wait: %d\n", errno); + DEBUGASSERT(errno == EINTR); + ret = -EINTR; + goto errout; + } + + /* Did the controller become disconnected while we were waiting */ + + if (priv->disconnected) + { + ret = -ENODEV; + goto errout; + } + } + + iinfo("Sampled\n"); + + /* Re-acquire the semaphore that manages mutually exclusive access to + * the device structure. We may have to wait here. But we have our sample. + * Interrupts and pre-emption will be re-enabled while we wait. + */ + + ret = sem_wait(&priv->exclsem); + +errout: + /* Then re-enable interrupts. We might get interrupt here and there + * could be a new sample. But no new threads will run because we still + * have pre-emption disabled. + */ + + leave_critical_section(flags); + + /* Restore pre-emption. We might get suspended here but that is okay + * because we already have our sample. Note: this means that if there + * were two threads reading from the HIDMOUSE for some reason, the data + * might be read out of order. + */ + + sched_unlock(); + return ret; +} + +/**************************************************************************** + * Name: usbhost_cfgdesc + * + * Description: + * This function implements the connect() method of struct + * usbhost_class_s. This method is a callback into the class + * implementation. It is used to provide the device's configuration + * descriptor to the class so that the class may initialize properly + * + * Input Parameters: + * priv - The USB host class instance. + * configdesc - A pointer to a uint8_t buffer container the configuration + * descriptor. + * desclen - The length in bytes of the configuration descriptor. + * + * Returned Values: + * On success, zero (OK) is returned. On a failure, a negated errno value is + * returned indicating the nature of the failure + * + * Assumptions: + * This function will *not* be called from an interrupt handler. + * + ****************************************************************************/ + +static inline int usbhost_cfgdesc(FAR struct usbhost_state_s *priv, + FAR const uint8_t *configdesc, int desclen) +{ + FAR struct usbhost_hubport_s *hport; + FAR struct usb_cfgdesc_s *cfgdesc; + FAR struct usb_desc_s *desc; + FAR struct usbhost_epdesc_s epindesc; + FAR struct usbhost_epdesc_s epoutdesc; + int remaining; + uint8_t found = 0; + bool done = false; + int ret; + + DEBUGASSERT(priv != NULL && priv->usbclass.hport && + configdesc != NULL && desclen >= sizeof(struct usb_cfgdesc_s)); + hport = priv->usbclass.hport; + + /* Keep the compiler from complaining about uninitialized variables */ + + memset(&epindesc, 0, sizeof(struct usbhost_epdesc_s)); + memset(&epoutdesc, 0, sizeof(struct usbhost_epdesc_s)); + + /* Verify that we were passed a configuration descriptor */ + + cfgdesc = (FAR struct usb_cfgdesc_s *)configdesc; + if (cfgdesc->type != USB_DESC_TYPE_CONFIG) + { + return -EINVAL; + } + + /* Get the total length of the configuration descriptor (little endian). + * It might be a good check to get the number of interfaces here too. + */ + + remaining = (int)usbhost_getle16(cfgdesc->totallen); + + /* Skip to the next entry descriptor */ + + configdesc += cfgdesc->len; + remaining -= cfgdesc->len; + + /* Loop where there are more dscriptors to examine */ + + while (remaining >= sizeof(struct usb_desc_s) && !done) + { + /* What is the next descriptor? */ + + desc = (FAR struct usb_desc_s *)configdesc; + switch (desc->type) + { + /* Interface descriptor. We really should get the number of endpoints + * from this descriptor too. + */ + + case USB_DESC_TYPE_INTERFACE: + { + uinfo("Interface descriptor\n"); + DEBUGASSERT(remaining >= USB_SIZEOF_IFDESC); + + /* Did we already find what we needed from a preceding interface? */ + + if ((found & USBHOST_ALLFOUND) == USBHOST_ALLFOUND) + { + /* Yes.. then break out of the loop and use the preceding + * interface. + */ + + done = true; + } + else + { + /* Otherwise, discard any endpoints previously found */ + + found = USBHOST_IFFOUND; + } + } + break; + + /* Endpoint descriptor. Here, we expect two bulk endpoints, an IN + * and an OUT. + */ + + case USB_DESC_TYPE_ENDPOINT: + { + FAR struct usb_epdesc_s *epdesc = (FAR struct usb_epdesc_s *)configdesc; + + uinfo("Endpoint descriptor\n"); + DEBUGASSERT(remaining >= USB_SIZEOF_EPDESC); + + /* Check for a interrupt endpoint. */ + + if ((epdesc->attr & USB_EP_ATTR_XFERTYPE_MASK) == USB_EP_ATTR_XFER_INT) + { + /* Yes.. it is a interrupt endpoint. IN or OUT? */ + + if (USB_ISEPOUT(epdesc->addr)) + { + /* It is an OUT interrupt endpoint. There should be only one + * interrupt OUT endpoint. + */ + + if ((found & USBHOST_EPOUTFOUND) != 0) + { + /* Oops.. more than one endpoint. We don't know + * what to do with this. + */ + + return -EINVAL; + } + found |= USBHOST_EPOUTFOUND; + + /* Save the bulk OUT endpoint information */ + + epoutdesc.hport = hport; + epoutdesc.addr = epdesc->addr & USB_EP_ADDR_NUMBER_MASK; + epoutdesc.in = false; + epoutdesc.xfrtype = USB_EP_ATTR_XFER_INT; + epoutdesc.interval = epdesc->interval; + epoutdesc.mxpacketsize = usbhost_getle16(epdesc->mxpacketsize); + uerr("Interrupt OUT EP addr:%d mxpacketsize:%d\n", + epoutdesc.addr, epoutdesc.mxpacketsize); + } + else + { + /* It is an IN interrupt endpoint. There should be only one + * interrupt IN endpoint. + */ + + if ((found & USBHOST_EPINFOUND) != 0) + { + /* Oops.. more than one endpoint. We don't know + * what to do with this. + */ + + return -EINVAL; + } + + found |= USBHOST_EPINFOUND; + + /* Save the bulk IN endpoint information */ + + epindesc.hport = hport; + epindesc.addr = epdesc->addr & USB_EP_ADDR_NUMBER_MASK; + epindesc.in = true; + epindesc.xfrtype = USB_EP_ATTR_XFER_INT; + epindesc.interval = epdesc->interval; + epindesc.mxpacketsize = usbhost_getle16(epdesc->mxpacketsize); + uerr("Interrupt IN EP addr:%d mxpacketsize:%d\n", + epindesc.addr, epindesc.mxpacketsize); + } + } + } + break; + + /* Other descriptors are just ignored for now */ + + default: + break; + } + + /* If we found everything we need with this interface, then break out + * of the loop early. + */ + + if (found == USBHOST_ALLFOUND) + { + done=true; + } + + /* Increment the address of the next descriptor */ + + configdesc += desc->len; + remaining -= desc->len; + } + + /* Sanity checking... did we find all of things that we need? */ + + if (found != USBHOST_ALLFOUND) + { + uerr("ERROR: Found IF:%s BIN:%s EPOUT:%s\n", + (found & USBHOST_IFFOUND) != 0 ? "YES" : "NO", + (found & USBHOST_EPINFOUND) != 0 ? "YES" : "NO", + (found & USBHOST_EPOUTFOUND) != 0 ? "YES" : "NO"); + return -EINVAL; + } + + /* We are good... Allocate the endpoints */ + + ret = DRVR_EPALLOC(hport->drvr, &epoutdesc, &priv->epout); + if (ret < 0) + { + uerr("ERROR: Failed to allocate Interrupt OUT endpoint\n"); + return ret; + } + + ret = DRVR_EPALLOC(hport->drvr, &epindesc, &priv->epin); + if (ret < 0) + { + uerr("ERROR: Failed to allocate Interrupt IN endpoint\n"); + (void)DRVR_EPFREE(hport->drvr, priv->epout); + return ret; + } + + uinfo("Endpoints allocated\n"); + return OK; +} + +/**************************************************************************** + * Name: usbhost_devinit + * + * Description: + * The USB device has been successfully connected. This completes the + * initialization operations. It is first called after the + * configuration descriptor has been received. + * + * This function is called from the connect() method. This function always + * executes on the thread of the caller of connect(). + * + * Input Parameters: + * priv - A reference to the class instance. + * + * Returned Values: + * None + * + ****************************************************************************/ + +static inline int usbhost_devinit(FAR struct usbhost_state_s *priv) +{ + char devname[DEV_NAMELEN]; + int ret = OK; + + /* Set aside a transfer buffer for exclusive use by the class driver */ + + ret = usbhost_talloc(priv); + if (ret < 0) + { + uerr("ERROR: Failed to allocate transfer buffer\n"); + return ret; + } + + /* Increment the reference count. This will prevent usbhost_destroy() from + * being called asynchronously if the device is removed. + */ + + priv->crefs++; + DEBUGASSERT(priv->crefs == 2); + + /* Start a worker task to poll the USB device. It would be nice to used the + * the NuttX worker thread to do this, but this task needs to wait for events + * and activities on the worker thread should not involve significant waiting. + * Having a dedicated thread is more efficient in this sense, but requires more + * memory resources, primarily for the dedicated stack (CONFIG_XBOXCONTROLLER_STACKSIZE). + */ + + /* The inputs to a task started by kernel_thread() are very awkward for this + * purpose. They are really designed for command line tasks (argc/argv). So + * the following is kludge pass binary data when the controller poll task + * is started. + * + * First, make sure we have exclusive access to g_priv (what is the likelihood + * of this being used? About zero, but we protect it anyway). + */ + + usbhost_takesem(&g_exclsem); + g_priv = priv; + + uinfo("Starting thread\n"); + priv->pollpid = kernel_thread("xbox", CONFIG_XBOXCONTROLLER_DEFPRIO, + CONFIG_XBOXCONTROLLER_STACKSIZE, + (main_t)usbhost_xboxcontroller_poll, (FAR char * const *)NULL); + if (priv->pollpid == ERROR) + { + /* Failed to started the poll thread... probably due to memory resources */ + + usbhost_givesem(&g_exclsem); + ret = -ENOMEM; + goto errout; + } + + /* Now wait for the poll task to get properly initialized */ + + usbhost_takesem(&g_syncsem); + usbhost_givesem(&g_exclsem); + + /* Configure the device */ + + /* Register the driver */ + + uinfo("Register block driver\n"); + usbhost_mkdevname(priv, devname); + ret = register_driver(devname, &g_xboxcontroller_fops, 0666, priv); + + /* Check if we successfully initialized. We now have to be concerned + * about asynchronous modification of crefs because the block + * driver has been registerd. + */ + +errout: + usbhost_takesem(&priv->exclsem); + priv->crefs--; + usbhost_givesem(&priv->exclsem); + return ret; +} + +/**************************************************************************** + * Name: usbhost_getle16 + * + * Description: + * Get a (possibly unaligned) 16-bit little endian value. + * + * Input Parameters: + * val - A pointer to the first byte of the little endian value. + * + * Returned Values: + * A uint16_t representing the whole 16-bit integer value + * + ****************************************************************************/ + +static inline uint16_t usbhost_getle16(const uint8_t *val) +{ + return (uint16_t)val[1] << 8 | (uint16_t)val[0]; +} + +/**************************************************************************** + * Name: usbhost_putle16 + * + * Description: + * Put a (possibly unaligned) 16-bit little endian value. + * + * Input Parameters: + * dest - A pointer to the first byte to save the little endian value. + * val - The 16-bit value to be saved. + * + * Returned Values: + * None + * + ****************************************************************************/ + +static void usbhost_putle16(uint8_t *dest, uint16_t val) +{ + dest[0] = val & 0xff; /* Little endian means LS byte first in byte stream */ + dest[1] = val >> 8; +} + +/**************************************************************************** + * Name: usbhost_getle32 + * + * Description: + * Get a (possibly unaligned) 32-bit little endian value. + * + * Input Parameters: + * dest - A pointer to the first byte to save the big endian value. + * val - The 32-bit value to be saved. + * + * Returned Values: + * None + * + ****************************************************************************/ + +static inline uint32_t usbhost_getle32(const uint8_t *val) +{ + /* Little endian means LS halfword first in byte stream */ + + return (uint32_t)usbhost_getle16(&val[2]) << 16 | (uint32_t)usbhost_getle16(val); +} + +/**************************************************************************** + * Name: usbhost_putle32 + * + * Description: + * Put a (possibly unaligned) 32-bit little endian value. + * + * Input Parameters: + * dest - A pointer to the first byte to save the little endian value. + * val - The 32-bit value to be saved. + * + * Returned Values: + * None + * + ****************************************************************************/ + +#if 0 /* Not used */ +static void usbhost_putle32(uint8_t *dest, uint32_t val) +{ + /* Little endian means LS halfword first in byte stream */ + + usbhost_putle16(dest, (uint16_t)(val & 0xffff)); + usbhost_putle16(dest+2, (uint16_t)(val >> 16)); +} +#endif + +/**************************************************************************** + * Name: usbhost_talloc + * + * Description: + * Allocate transfer buffer memory. + * + * Input Parameters: + * priv - A reference to the class instance. + * + * Returned Values: + * On sucess, zero (OK) is returned. On failure, an negated errno value + * is returned to indicate the nature of the failure. + * + ****************************************************************************/ + +static inline int usbhost_talloc(FAR struct usbhost_state_s *priv) +{ + FAR struct usbhost_hubport_s *hport; + + DEBUGASSERT(priv != NULL && priv->usbclass.hport != NULL && + priv->tbuffer == NULL); + hport = priv->usbclass.hport; + + return DRVR_ALLOC(hport->drvr, &priv->tbuffer, &priv->tbuflen); +} + +/**************************************************************************** + * Name: usbhost_tfree + * + * Description: + * Free transfer buffer memory. + * + * Input Parameters: + * priv - A reference to the class instance. + * + * Returned Values: + * On sucess, zero (OK) is returned. On failure, an negated errno value + * is returned to indicate the nature of the failure. + * + ****************************************************************************/ + +static inline int usbhost_tfree(FAR struct usbhost_state_s *priv) +{ + FAR struct usbhost_hubport_s *hport; + int result = OK; + + DEBUGASSERT(priv != NULL && priv->usbclass.hport != NULL); + + if (priv->tbuffer) + { + hport = priv->usbclass.hport; + result = DRVR_FREE(hport->drvr, priv->tbuffer); + priv->tbuffer = NULL; + priv->tbuflen = 0; + } + + return result; +} + +/**************************************************************************** + * struct usbhost_registry_s methods + ****************************************************************************/ + +/**************************************************************************** + * Name: usbhost_create + * + * Description: + * This function implements the create() method of struct usbhost_registry_s. + * The create() method is a callback into the class implementation. It is + * used to (1) create a new instance of the USB host class state and to (2) + * bind a USB host driver "session" to the class instance. Use of this + * create() method will support environments where there may be multiple + * USB ports and multiple USB devices simultaneously connected. + * + * Input Parameters: + * hport - The hub hat manages the new class instance. + * id - In the case where the device supports multiple base classes, + * subclasses, or protocols, this specifies which to configure for. + * + * Returned Values: + * On success, this function will return a non-NULL instance of struct + * usbhost_class_s that can be used by the USB host driver to communicate + * with the USB host class. NULL is returned on failure; this function + * will fail only if the hport input parameter is NULL or if there are + * insufficient resources to create another USB host class instance. + * + ****************************************************************************/ + +static FAR struct usbhost_class_s *usbhost_create(FAR struct usbhost_hubport_s *hport, + FAR const struct usbhost_id_s *id) +{ + FAR struct usbhost_state_s *priv; + + /* Allocate a USB host class instance */ + + priv = usbhost_allocclass(); + if (priv) + { + /* Initialize the allocated storage class instance */ + + memset(priv, 0, sizeof(struct usbhost_state_s)); + + /* Assign a device number to this class instance */ + + if (usbhost_allocdevno(priv) == OK) + { + /* Initialize class method function pointers */ + + priv->usbclass.hport = hport; + priv->usbclass.connect = usbhost_connect; + priv->usbclass.disconnected = usbhost_disconnected; + + /* The initial reference count is 1... One reference is held by the driver */ + + priv->crefs = 1; + + /* Initialize semaphores (this works okay in the interrupt context) */ + + sem_init(&priv->exclsem, 0, 1); + sem_init(&priv->waitsem, 0, 0); + + /* The waitsem semaphore is used for signaling and, hence, should + * not have priority inheritance enabled. + */ + + sem_setprotocol(&priv->waitsem, SEM_PRIO_NONE); + + /* Return the instance of the USB class driver */ + + return &priv->usbclass; + } + } + + /* An error occurred. Free the allocation and return NULL on all failures */ + + if (priv) + { + usbhost_freeclass(priv); + } + return NULL; +} + +/**************************************************************************** + * struct usbhost_class_s methods + ****************************************************************************/ +/**************************************************************************** + * Name: usbhost_connect + * + * Description: + * This function implements the connect() method of struct + * usbhost_class_s. This method is a callback into the class + * implementation. It is used to provide the device's configuration + * descriptor to the class so that the class may initialize properly + * + * Input Parameters: + * usbclass - The USB host class entry previously obtained from a call to + * create(). + * configdesc - A pointer to a uint8_t buffer container the configuration + * descriptor. + * desclen - The length in bytes of the configuration descriptor. + * + * Returned Values: + * On success, zero (OK) is returned. On a failure, a negated errno value is + * returned indicating the nature of the failure + * + * NOTE that the class instance remains valid upon return with a failure. It is + * the responsibility of the higher level enumeration logic to call + * CLASS_DISCONNECTED to free up the class driver resources. + * + * Assumptions: + * - This function will *not* be called from an interrupt handler. + * - If this function returns an error, the USB host controller driver + * must call to DISCONNECTED method to recover from the error + * + ****************************************************************************/ + +static int usbhost_connect(FAR struct usbhost_class_s *usbclass, + FAR const uint8_t *configdesc, int desclen) +{ + FAR struct usbhost_state_s *priv = (FAR struct usbhost_state_s *)usbclass; + int ret; + + DEBUGASSERT(priv != NULL && + configdesc != NULL && + desclen >= sizeof(struct usb_cfgdesc_s)); + + /* Parse the configuration descriptor to get the endpoints */ + + ret = usbhost_cfgdesc(priv, configdesc, desclen); + if (ret < 0) + { + uerr("ERROR: usbhost_cfgdesc() failed: %d\n", ret); + } + else + { + /* Now configure the device and register the NuttX driver */ + + ret = usbhost_devinit(priv); + if (ret < 0) + { + uerr("ERROR: usbhost_devinit() failed: %d\n", ret); + } + } + + return ret; +} + +/**************************************************************************** + * Name: usbhost_disconnected + * + * Description: + * This function implements the disconnected() method of struct + * usbhost_class_s. This method is a callback into the class + * implementation. It is used to inform the class that the USB device has + * been disconnected. + * + * Input Parameters: + * usbclass - The USB host class entry previously obtained from a call to + * create(). + * + * Returned Values: + * On success, zero (OK) is returned. On a failure, a negated errno value + * is returned indicating the nature of the failure + * + * Assumptions: + * This function may be called from an interrupt handler. + * + ****************************************************************************/ + +static int usbhost_disconnected(struct usbhost_class_s *usbclass) +{ + FAR struct usbhost_state_s *priv = (FAR struct usbhost_state_s *)usbclass; + int i; + + DEBUGASSERT(priv != NULL); + + /* Set an indication to any users of the device that the device is no + * longer available. + */ + + priv->disconnected = true; + uinfo("Disconnected\n"); + + /* Are there a thread(s) waiting for controller data that will never come? */ + + for (i = 0; i < priv->nwaiters; i++) + { + /* Yes.. wake them up */ + + usbhost_givesem(&priv->waitsem); + } + + /* Possibilities: + * + * - Failure occurred before the controller poll task was started successfully. + * In this case, the disconnection will have to be handled on the worker + * task. + * - Failure occurred after the controller poll task was started successfully. In + * this case, the disconnection can be performed on the mouse poll thread. + */ + + if (priv->polling) + { + /* The polling task is still alive. Signal the mouse polling task. + * When that task wakes up, it will decrement the reference count and, + * perhaps, destroy the class instance. Then it will exit. + */ + + (void)kill(priv->pollpid, SIGALRM); + } + else + { + /* In the case where the failure occurs before the polling task was + * started. Now what? We are probably executing from an interrupt + * handler here. We will use the worker thread. This is kind of + * wasteful and begs for a re-design. + */ + + DEBUGASSERT(priv->work.worker == NULL); + (void)work_queue(HPWORK, &priv->work, usbhost_destroy, priv, 0); + } + + return OK; +} + +/**************************************************************************** + * Character driver methods + ****************************************************************************/ +/**************************************************************************** + * Name: usbhost_open + * + * Description: + * Standard character driver open method. + * + ****************************************************************************/ + +static int usbhost_open(FAR struct file *filep) +{ + FAR struct inode *inode; + FAR struct usbhost_state_s *priv; + irqstate_t flags; + int ret; + + uinfo("Entry\n"); + DEBUGASSERT(filep && filep->f_inode); + inode = filep->f_inode; + priv = inode->i_private; + + /* Make sure that we have exclusive access to the private data structure */ + + DEBUGASSERT(priv && priv->crefs > 0 && priv->crefs < USBHOST_MAX_CREFS); + usbhost_takesem(&priv->exclsem); + + /* Check if the controller device is still connected. We need to disable + * interrupts momentarily to assure that there are no asynchronous disconnect + * events. + */ + + flags = enter_critical_section(); + if (priv->disconnected) + { + /* No... the driver is no longer bound to the class. That means that + * the USB storage device is no longer connected. Refuse any further + * attempts to open the driver. + */ + + ret = -ENODEV; + } + else + { + /* Was the driver previously open? We need to perform special + * initialization on the first time that the driver is opened. + */ + + if (!priv->open) + { + /* Set the thresholding values so that the first button press + * will be reported. + */ + +#ifdef NEVER + priv->xlast = INVALID_POSITION_B16; + priv->ylast = INVALID_POSITION_B16; +#ifdef CONFIG_MOUSE_WHEEL + priv->wlast = INVALID_POSITION_B16; +#endif + /* Set the reported position to the center of the range */ + + priv->xaccum = (HIDMOUSE_XMAX_B16 >> 1); + priv->yaccum = (HIDMOUSE_YMAX_B16 >> 1); +#endif + } + + /* Otherwise, just increment the reference count on the driver */ + + priv->crefs++; + priv->open = true; + ret = OK; + } + + leave_critical_section(flags); + + usbhost_givesem(&priv->exclsem); + return ret; +} + +/**************************************************************************** + * Name: usbhost_close + * + * Description: + * Standard character driver close method. + * + ****************************************************************************/ + +static int usbhost_close(FAR struct file *filep) +{ + FAR struct inode *inode; + FAR struct usbhost_state_s *priv; + irqstate_t flags; + + uinfo("Entry\n"); + DEBUGASSERT(filep && filep->f_inode); + inode = filep->f_inode; + priv = inode->i_private; + + /* Decrement the reference count on the driver */ + + DEBUGASSERT(priv->crefs >= 1); + usbhost_takesem(&priv->exclsem); + + /* We need to disable interrupts momentarily to assure that there are no + * asynchronous poll or disconnect events. + */ + + flags = enter_critical_section(); + priv->crefs--; + + /* Check if the USB controller device is still connected. If the device is + * no longer connected, then unregister the driver and free the driver + * class instance. + */ + + if (priv->disconnected) + { + /* If the reference count is one or less then there are two + * possibilities: + * + * 1) It might be zero meaning that the polling thread has already + * exited and decremented its count. + * 2) If might be one meaning either that (a) the polling thread is still + * running and still holds a count, or (b) the polling thread has exited, + * but there is still an outstanding open reference. + */ + + if (priv->crefs == 0 || (priv->crefs == 1 && priv->polling)) + { + /* Yes.. In either case, then the driver is no longer open */ + + priv->open = false; + + /* Check if the USB keyboard device is still connected. */ + + if (priv->crefs == 0) + { + /* The polling thread is no longer running */ + + DEBUGASSERT(!priv->polling); + + /* If the device is no longer connected, unregister the driver + * and free the driver class instance. + */ + + usbhost_destroy(priv); + + /* Skip giving the semaphore... it is no longer valid */ + + leave_critical_section(flags); + return OK; + } + else /* if (priv->crefs == 1) */ + { + /* The polling thread is still running. Signal it so that it + * will wake up and call usbhost_destroy(). The particular + * signal that we use does not matter in this case. + */ + + (void)kill(priv->pollpid, SIGALRM); + } + } + } + + usbhost_givesem(&priv->exclsem); + leave_critical_section(flags); + return OK; +} + +/**************************************************************************** + * Name: usbhost_read + * + * Description: + * Standard character driver read method. + * + ****************************************************************************/ + +static ssize_t usbhost_read(FAR struct file *filep, FAR char *buffer, size_t len) +{ + FAR struct inode *inode; + FAR struct usbhost_state_s *priv; + FAR struct xbox_controller_buttonstate_s sample; + int ret; + + DEBUGASSERT(filep && filep->f_inode && buffer); + inode = filep->f_inode; + priv = inode->i_private; + + /* Make sure that we have exclusive access to the private data structure */ + + DEBUGASSERT(priv && priv->crefs > 0 && priv->crefs < USBHOST_MAX_CREFS); + usbhost_takesem(&priv->exclsem); + + /* Check if the controller is still connected. We need to disable interrupts + * momentarily to assure that there are no asynchronous disconnect events. + */ + + if (priv->disconnected) + { + /* No... the driver is no longer bound to the class. That means that + * the USB controller is no longer connected. Refuse any further attempts + * to access the driver. + */ + + ret = -ENODEV; + goto errout; + } + + /* Try to read sample data. */ + + ret = usbhost_sample(priv, &sample); + if (ret < 0) + { + /* Sample data is not available now. We would ave to wait to get + * receive sample data. If the user has specified the O_NONBLOCK + * option, then just return an error. + */ + + if (filep->f_oflags & O_NONBLOCK) + { + /* Yes.. then return a failure */ + + ret = -EAGAIN; + goto errout; + } + + /* Wait for sample data */ + + ret = usbhost_waitsample(priv, &sample); + ret = 0; + if (ret < 0) + { + /* We might have been awakened by a signal */ + + ierr("ERROR: usbhost_waitsample: %d\n", ret); + goto errout; + } + } + + /* We now have sampled controller data that we can report to the caller. */ + + memcpy(buffer, &sample, sizeof(struct xbox_controller_buttonstate_s)); + + ret = sizeof(struct xbox_controller_buttonstate_s); + +errout: + usbhost_givesem(&priv->exclsem); + iinfo("Returning: %d\n", ret); + return (ssize_t)ret; +} + +/**************************************************************************** + * Name: usbhost_write + * + * Description: + * Standard character driver write method. + * + ****************************************************************************/ + +static ssize_t usbhost_write(FAR struct file *filep, FAR const char *buffer, + size_t len) +{ + + /* Not implemented. */ + + return -ENOSYS; +} + +/**************************************************************************** + * Name: usbhost_ioctl + * + * Description: + * Standard character driver ioctl method. + * + ****************************************************************************/ + +static int usbhost_ioctl(FAR struct file* filep, int cmd, unsigned long arg) +{ + FAR struct inode *inode; + FAR struct usbhost_state_s *priv; + int ret = 0; + int nbytes; + FAR struct usbhost_hubport_s *hport; + static uint8_t rumble_cmd[] = { + 0x09, 0x00, 0x00, 0x09, 0x00, 0x0f, 0x00, + 0x00, 0x00, 0x00, 0xff, 0x00, 0xff + }; + + uinfo("Entered\n"); + DEBUGASSERT(filep && filep->f_inode && buffer); + inode = filep->f_inode; + priv = inode->i_private; + hport = priv->usbclass.hport; + + /* Check if the controller is still connected. We need to disable interrupts + * momentarily to assure that there are no asynchronous disconnect events. + */ + + if (priv->disconnected) + { + /* No... the driver is no longer bound to the class. That means that + * the USB controller is no longer connected. Refuse any further attempts + * to access the driver. + */ + + ret = -ENODEV; + goto errout; + } + + /* Determine which IOCTL command to execute. */ + switch (cmd) + { + + case XBOX_CONTROLLER_IOCTL_RUMBLE: + + /* The least significant byte is the weak actuator strength. + * The second byte is the strong actuator strength. + */ + + memcpy(priv->obuffer, rumble_cmd, sizeof(rumble_cmd)); + priv->obuffer[2] = priv->out_seq_num++; + priv->obuffer[8] = (arg >> 1) & 0xff; // Strong (left actuator) + priv->obuffer[9] = arg & 0xff; // Weak (right actuator) + + /* Perform the transfer. */ + + nbytes = DRVR_TRANSFER(hport->drvr, priv->epout, + priv->obuffer, sizeof(rumble_cmd)); + + /* Did we encounter an error? */ + + if (nbytes < 0) + { + ret = nbytes; + } + + break; + + default: + + ret = -EINVAL; + goto errout; + } + +errout: + iinfo("Returning: %d\n", ret); + return ret; +} + +/**************************************************************************** + * Name: usbhost_poll + * + * Description: + * Standard character driver poll method. + * + ****************************************************************************/ + +#ifndef CONFIG_DISABLE_POLL +static int usbhost_poll(FAR struct file *filep, FAR struct pollfd *fds, + bool setup) +{ + FAR struct inode *inode; + FAR struct usbhost_state_s *priv; + int ret = OK; + int i; + + DEBUGASSERT(filep && filep->f_inode && fds); + inode = filep->f_inode; + priv = inode->i_private; + + /* Make sure that we have exclusive access to the private data structure */ + + DEBUGASSERT(priv); + usbhost_takesem(&priv->exclsem); + + /* Check if the controller is still connected. We need to disable interrupts + * momentarily to assure that there are no asynchronous disconnect events. + */ + + if (priv->disconnected) + { + /* No... the driver is no longer bound to the class. That means that + * the USB controller is no longer connected. Refuse any further attempts + * to access the driver. + */ + + ret = -ENODEV; + } + else if (setup) + { + /* This is a request to set up the poll. Find an available slot for + * the poll structure reference + */ + + for (i = 0; i < CONFIG_XBOXCONTROLLER_NPOLLWAITERS; i++) + { + /* Find an available slot */ + + if (!priv->fds[i]) + { + /* Bind the poll structure and this slot */ + + priv->fds[i] = fds; + fds->priv = &priv->fds[i]; + break; + } + } + + if (i >= CONFIG_XBOXCONTROLLER_NPOLLWAITERS) + { + fds->priv = NULL; + ret = -EBUSY; + goto errout; + } + + /* Should we immediately notify on any of the requested events? Notify + * the POLLIN event if there is buffered controller data. + */ + + if (priv->valid) + { + usbhost_pollnotify(priv); + } + } + else + { + /* This is a request to tear down the poll. */ + + struct pollfd **slot = (struct pollfd **)fds->priv; + DEBUGASSERT(slot); + + /* Remove all memory of the poll setup */ + + *slot = NULL; + fds->priv = NULL; + } + +errout: + sem_post(&priv->exclsem); + return ret; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: usbhost_xboxcontroller_init + * + * Description: + * Initialize the USB class driver. This function should be called + * be platform-specific code in order to initialize and register support + * for the USB host class device. + * + * Input Parameters: + * None + * + * Returned Values: + * On success this function will return zero (OK); A negated errno value + * will be returned on failure. + * + ****************************************************************************/ + +int usbhost_xboxcontroller_init(void) +{ + + /* Perform any one-time initialization of the class implementation */ + + sem_init(&g_exclsem, 0, 1); + sem_init(&g_syncsem, 0, 0); + + /* The g_syncsem semaphore is used for signaling and, hence, should not + * have priority inheritance enabled. + */ + + sem_setprotocol(&g_syncsem, SEM_PRIO_NONE); + + /* Advertise our availability to support (certain) devices */ + + return usbhost_registerclass(&g_xboxcontroller); +} diff --git a/include/nuttx/input/xbox-controller.h b/include/nuttx/input/xbox-controller.h new file mode 100644 index 00000000000..b4e0262740e --- /dev/null +++ b/include/nuttx/input/xbox-controller.h @@ -0,0 +1,88 @@ +/************************************************************************************ + * include/nuttx/input/xbox-controller.h + * + * Copyright (C) 2016 Brian Webb. + * Author: Brian Webb + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __INCLUDE_NUTTX_INPUT_XBOX_CONTROLLER_H +#define __INCLUDE_NUTTX_INPUT_XBOX_CONTROLLER_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* This type defines the button data report from the controller. */ + +struct xbox_controller_buttonstate_s +{ + bool guide : 1; + bool sync : 1; + bool start : 1; + bool back : 1; + bool a : 1; + bool b : 1; + bool x : 1; + bool y : 1; + bool dpad_up : 1; + bool dpad_down : 1; + bool dpad_left : 1; + bool dpad_right : 1; + bool bumper_left : 1; + bool bumper_right : 1; + bool stick_click_left : 1; + bool stick_click_right : 1; + int16_t stick_left_x; + int16_t stick_left_y; + int16_t stick_right_x; + int16_t stick_right_y; + int16_t trigger_left; + int16_t trigger_right; +}; + +/* The supported IOCTL commands. */ + +enum +{ + XBOX_CONTROLLER_IOCTL_RUMBLE +} xbox_controller_iotcl_cmds; + +#ifdef __cplusplus +} +#endif + +#endif /* __INCLUDE_NUTTX_INPUT_XBOX_CONTROLLER_H */ + diff --git a/include/nuttx/usb/usbhost.h b/include/nuttx/usb/usbhost.h index 587917701cd..6b6b495954a 100644 --- a/include/nuttx/usb/usbhost.h +++ b/include/nuttx/usb/usbhost.h @@ -1084,6 +1084,27 @@ int usbhost_kbdinit(void); int usbhost_mouse_init(void); #endif +#ifdef CONFIG_USBHOST_XBOXCONTROLLER +/**************************************************************************** + * Name: usbhost_xboxcontroller_init + * + * Description: + * Initialize the USB XBox controller driver. This function + * should be called be platform-specific code in order to initialize and + * register support for the USB XBox controller. + * + * Input Parameters: + * None + * + * Returned Values: + * On success this function will return zero (OK); A negated errno value + * will be returned on failure. + * + ****************************************************************************/ + +int usbhost_xboxcontroller_init(void); +#endif + /**************************************************************************** * Name: usbhost_wlaninit * From 175f8960cfc20a00c8882be8bb04807d47adaee0 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 18 Mar 2017 06:47:34 -0600 Subject: [PATCH 29/81] Cosmetic changes from review of last PR --- drivers/usbhost/usbhost_xboxcontroller.c | 295 +++++++++++++---------- 1 file changed, 164 insertions(+), 131 deletions(-) diff --git a/drivers/usbhost/usbhost_xboxcontroller.c b/drivers/usbhost/usbhost_xboxcontroller.c index fd12efee975..6fcf49d6a88 100644 --- a/drivers/usbhost/usbhost_xboxcontroller.c +++ b/drivers/usbhost/usbhost_xboxcontroller.c @@ -2,7 +2,8 @@ * drivers/usbhost/usbhost_xboxcontroller.c * * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Authors: Gregory Nutt + * Brian Webb * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -143,7 +144,8 @@ #define XBOX_BUTTON_STICK_LEFT_Y 6 #define XBOX_BUTTON_STICK_RIGHT_X 7 #define XBOX_BUTTON_STICK_RIGHT_Y 8 -#define XBOX_BUTTON_SET(buffer, index, mask) ((((buffer)[(index)] & (mask)) != 0) ? true : false); +#define XBOX_BUTTON_SET(buffer, index, mask) \ + ((((buffer)[(index)] & (mask)) != 0) ? true : false); /**************************************************************************** * Private Types @@ -291,7 +293,7 @@ static struct usbhost_registry_s g_xboxcontroller = NULL, /* flink */ usbhost_create, /* create */ 2, /* nids */ - g_xboxcontroller_id /* id[] */ + g_xboxcontroller_id /* id[] */ }; /* The configuration information for the block file device. */ @@ -342,7 +344,7 @@ static void usbhost_takesem(sem_t *sem) * awakened by a signal. */ - ASSERT(errno == EINTR); + DEBUGASSERT(errno == EINTR); } } @@ -558,7 +560,7 @@ static void usbhost_notify(FAR struct usbhost_state_s *priv) #ifndef CONFIG_DISABLE_POLL for (i = 0; i < CONFIG_XBOXCONTROLLER_NPOLLWAITERS; i++) { - struct pollfd *fds = priv->fds[i]; + FAR struct pollfd *fds = priv->fds[i]; if (fds) { fds->revents |= POLLIN; @@ -640,16 +642,15 @@ static int usbhost_xboxcontroller_poll(int argc, char *argv[]) if (nbytes != -EAGAIN) { - - uerr("ERROR: DRVR_TRANSFER returned: %d/%u\n", - (int)nbytes, nerrors); - + uerr("ERROR: DRVR_TRANSFER returned: %d/%u\n", + (int)nbytes, nerrors); + if (++nerrors > 200) { uerr(" Too many errors... aborting: %d\n", nerrors); ret = (int)nbytes; break; - } + } } } @@ -657,146 +658,176 @@ static int usbhost_xboxcontroller_poll(int argc, char *argv[]) else { - /* Success, reset the error counter */ - nerrors = 0; - - /* The type of message is in the first byte */ - switch (priv->tbuffer[0]) - { + nerrors = 0; - case USBHOST_WAITING_CONNECTION: - - /* Send the initialization message when we received the - * the first waiting connection message. - */ - - if (!priv->initialized) { + /* The type of message is in the first byte */ - /* Get exclusive access to the controller state data */ + switch (priv->tbuffer[0]) + { + case USBHOST_WAITING_CONNECTION: + /* Send the initialization message when we received the + * the first waiting connection message. + */ - usbhost_takesem(&priv->exclsem); + if (!priv->initialized) + { + /* Get exclusive access to the controller state data */ - priv->tbuffer[0] = 0x05; - priv->tbuffer[1] = 0x20; - priv->tbuffer[2] = priv->out_seq_num++; - priv->tbuffer[3] = 0x01; - priv->tbuffer[4] = 0x00; - nbytes = DRVR_TRANSFER(hport->drvr, priv->epout, - priv->tbuffer, 5); - priv->initialized = true; - - /* Release our lock on the state structure */ + usbhost_takesem(&priv->exclsem); - usbhost_givesem(&priv->exclsem); - } + priv->tbuffer[0] = 0x05; + priv->tbuffer[1] = 0x20; + priv->tbuffer[2] = priv->out_seq_num++; + priv->tbuffer[3] = 0x01; + priv->tbuffer[4] = 0x00; + nbytes = DRVR_TRANSFER(hport->drvr, priv->epout, + priv->tbuffer, 5); + priv->initialized = true; - break; - - case USBHOST_GUIDE_BUTTON_STATUS: + /* Release our lock on the state structure */ - /* Get exclusive access to the controller state data */ + usbhost_givesem(&priv->exclsem); + } - usbhost_takesem(&priv->exclsem); + break; - /* Read the data out of the controller report. */ + case USBHOST_GUIDE_BUTTON_STATUS: + /* Get exclusive access to the controller state data */ - priv->rpt.guide = (priv->tbuffer[XBOX_BUTTON_GUIDE_INDEX] != 0) ? true : false; - - priv->valid = true; + usbhost_takesem(&priv->exclsem); - /* The One X controller requires an ACK of the guide button status message. */ + /* Read the data out of the controller report. */ - if (priv->tbuffer[1] == 0x30) - { - - static const uint8_t guide_button_report_ack[] = { - 0x01, 0x20, 0x00, 0x09, 0x00, 0x07, 0x20, 0x02, - 0x00, 0x00, 0x00, 0x00, 0x00 - }; + priv->rpt.guide = (priv->tbuffer[XBOX_BUTTON_GUIDE_INDEX] != 0) ? true : false; + priv->valid = true; - /* Remember the input packet sequence number. */ - - uint8_t seq_num = priv->tbuffer[2]; + /* The One X controller requires an ACK of the guide button status + * message. + */ - /* Copy the ACK packet into the transfer buffer. */ - - memcpy(priv->tbuffer, guide_button_report_ack, sizeof(guide_button_report_ack)); + if (priv->tbuffer[1] == 0x30) + { + static const uint8_t guide_button_report_ack[] = + { + 0x01, 0x20, 0x00, 0x09, 0x00, 0x07, 0x20, 0x02, + 0x00, 0x00, 0x00, 0x00, 0x00 + }; - /* Ensure the sequence number is the same as the input packet. */ - - priv->tbuffer[2] = seq_num; + /* Remember the input packet sequence number. */ - /* Perform the transfer. */ - - nbytes = DRVR_TRANSFER(hport->drvr, priv->epout, - priv->tbuffer, sizeof(guide_button_report_ack)); - } - - /* Notify any waiters that new controller data is available */ + uint8_t seq_num = priv->tbuffer[2]; - usbhost_notify(priv); + /* Copy the ACK packet into the transfer buffer. */ - /* Release our lock on the state structure */ + memcpy(priv->tbuffer, guide_button_report_ack, + sizeof(guide_button_report_ack)); - usbhost_givesem(&priv->exclsem); + /* Ensure the sequence number is the same as the input packet. */ - break; - - case USBHOST_BUTTON_DATA: + priv->tbuffer[2] = seq_num; - /* Ignore the controller data if no task has opened the driver. */ + /* Perform the transfer. */ - if (priv->open) - { - /* Get exclusive access to the controller state data */ + nbytes = DRVR_TRANSFER(hport->drvr, priv->epout, priv->tbuffer, + sizeof(guide_button_report_ack)); + } - usbhost_takesem(&priv->exclsem); + /* Notify any waiters that new controller data is available */ - /* Read the data out of the controller report. */ + usbhost_notify(priv); - priv->rpt.sync = XBOX_BUTTON_SET(priv->tbuffer, XBOX_BUTTON_SYNC_INDEX, XBOX_BUTTON_SYNC_MASK); - priv->rpt.start = XBOX_BUTTON_SET(priv->tbuffer, XBOX_BUTTON_START_INDEX, XBOX_BUTTON_START_MASK); - priv->rpt.back = XBOX_BUTTON_SET(priv->tbuffer, XBOX_BUTTON_BACK_INDEX, XBOX_BUTTON_BACK_MASK); - priv->rpt.a = XBOX_BUTTON_SET(priv->tbuffer, XBOX_BUTTON_A_INDEX, XBOX_BUTTON_A_MASK); - priv->rpt.b = XBOX_BUTTON_SET(priv->tbuffer, XBOX_BUTTON_B_INDEX, XBOX_BUTTON_B_MASK); - priv->rpt.x = XBOX_BUTTON_SET(priv->tbuffer, XBOX_BUTTON_X_INDEX, XBOX_BUTTON_X_MASK); - priv->rpt.y = XBOX_BUTTON_SET(priv->tbuffer, XBOX_BUTTON_Y_INDEX, XBOX_BUTTON_Y_MASK); - priv->rpt.dpad_up = XBOX_BUTTON_SET(priv->tbuffer, XBOX_BUTTON_DPAD_UP_INDEX, XBOX_BUTTON_DPAD_UP_MASK); - priv->rpt.dpad_down = XBOX_BUTTON_SET(priv->tbuffer, XBOX_BUTTON_DPAD_DOWN_INDEX, XBOX_BUTTON_DPAD_DOWN_MASK); - priv->rpt.dpad_left = XBOX_BUTTON_SET(priv->tbuffer, XBOX_BUTTON_DPAD_LEFT_INDEX, XBOX_BUTTON_DPAD_LEFT_MASK); - priv->rpt.dpad_right = XBOX_BUTTON_SET(priv->tbuffer, XBOX_BUTTON_DPAD_RIGHT_INDEX, XBOX_BUTTON_DPAD_RIGHT_MASK); - priv->rpt.bumper_left = XBOX_BUTTON_SET(priv->tbuffer, XBOX_BUTTON_BUMPER_LEFT_INDEX, XBOX_BUTTON_BUMPER_LEFT_MASK); - priv->rpt.bumper_right = XBOX_BUTTON_SET(priv->tbuffer, XBOX_BUTTON_BUMPER_RIGHT_INDEX, XBOX_BUTTON_BUMPER_RIGHT_MASK); - priv->rpt.stick_click_left = XBOX_BUTTON_SET(priv->tbuffer, XBOX_BUTTON_STICK_LEFT_INDEX, XBOX_BUTTON_STICK_LEFT_MASK); - priv->rpt.stick_click_right = XBOX_BUTTON_SET(priv->tbuffer, XBOX_BUTTON_STICK_RIGHT_INDEX, XBOX_BUTTON_STICK_RIGHT_MASK); - priv->rpt.trigger_left = ((int16_t*)(priv->tbuffer))[XBOX_BUTTON_TRIGGER_LEFT]; - priv->rpt.trigger_right = ((int16_t*)(priv->tbuffer))[XBOX_BUTTON_TRIGGER_RIGHT]; - priv->rpt.stick_left_x = ((int16_t*)(priv->tbuffer))[XBOX_BUTTON_STICK_LEFT_X]; - priv->rpt.stick_left_y = ((int16_t*)(priv->tbuffer))[XBOX_BUTTON_STICK_LEFT_Y]; - priv->rpt.stick_right_x = ((int16_t*)(priv->tbuffer))[XBOX_BUTTON_STICK_RIGHT_X]; - priv->rpt.stick_right_y = ((int16_t*)(priv->tbuffer))[XBOX_BUTTON_STICK_RIGHT_Y]; - - priv->valid = true; + /* Release our lock on the state structure */ - /* Notify any waiters that new controller data is available */ + usbhost_givesem(&priv->exclsem); - usbhost_notify(priv); + break; - /* Release our lock on the state structure */ + case USBHOST_BUTTON_DATA: + /* Ignore the controller data if no task has opened the driver. */ - usbhost_givesem(&priv->exclsem); - } + if (priv->open) + { + /* Get exclusive access to the controller state data */ - break; + usbhost_takesem(&priv->exclsem); - default: - - uinfo("Received messge type: %x\n", priv->tbuffer[0]); - - } - + /* Read the data out of the controller report. */ + + priv->rpt.sync = + XBOX_BUTTON_SET(priv->tbuffer, XBOX_BUTTON_SYNC_INDEX, + XBOX_BUTTON_SYNC_MASK); + priv->rpt.start = + XBOX_BUTTON_SET(priv->tbuffer, XBOX_BUTTON_START_INDEX, + XBOX_BUTTON_START_MASK); + priv->rpt.back = + XBOX_BUTTON_SET(priv->tbuffer, XBOX_BUTTON_BACK_INDEX, + XBOX_BUTTON_BACK_MASK); + priv->rpt.a = + XBOX_BUTTON_SET(priv->tbuffer, XBOX_BUTTON_A_INDEX, + XBOX_BUTTON_A_MASK); + priv->rpt.b = + XBOX_BUTTON_SET(priv->tbuffer, XBOX_BUTTON_B_INDEX, + XBOX_BUTTON_B_MASK); + priv->rpt.x = + XBOX_BUTTON_SET(priv->tbuffer, XBOX_BUTTON_X_INDEX, + XBOX_BUTTON_X_MASK); + priv->rpt.y = + XBOX_BUTTON_SET(priv->tbuffer, XBOX_BUTTON_Y_INDEX, + XBOX_BUTTON_Y_MASK); + priv->rpt.dpad_up = + XBOX_BUTTON_SET(priv->tbuffer, XBOX_BUTTON_DPAD_UP_INDEX, + XBOX_BUTTON_DPAD_UP_MASK); + priv->rpt.dpad_down = + XBOX_BUTTON_SET(priv->tbuffer, XBOX_BUTTON_DPAD_DOWN_INDEX, + XBOX_BUTTON_DPAD_DOWN_MASK); + priv->rpt.dpad_left = + XBOX_BUTTON_SET(priv->tbuffer, XBOX_BUTTON_DPAD_LEFT_INDEX, + XBOX_BUTTON_DPAD_LEFT_MASK); + priv->rpt.dpad_right = + XBOX_BUTTON_SET(priv->tbuffer, XBOX_BUTTON_DPAD_RIGHT_INDEX, + XBOX_BUTTON_DPAD_RIGHT_MASK); + priv->rpt.bumper_left = + XBOX_BUTTON_SET(priv->tbuffer, XBOX_BUTTON_BUMPER_LEFT_INDEX, + XBOX_BUTTON_BUMPER_LEFT_MASK); + priv->rpt.bumper_right = + XBOX_BUTTON_SET(priv->tbuffer, XBOX_BUTTON_BUMPER_RIGHT_INDEX, XBOX_BUTTON_BUMPER_RIGHT_MASK); + priv->rpt.stick_click_left = + XBOX_BUTTON_SET(priv->tbuffer, XBOX_BUTTON_STICK_LEFT_INDEX, + XBOX_BUTTON_STICK_LEFT_MASK); + priv->rpt.stick_click_right = + XBOX_BUTTON_SET(priv->tbuffer, XBOX_BUTTON_STICK_RIGHT_INDEX, + XBOX_BUTTON_STICK_RIGHT_MASK); + priv->rpt.trigger_left = + ((int16_t*)(priv->tbuffer))[XBOX_BUTTON_TRIGGER_LEFT]; + priv->rpt.trigger_right = + ((int16_t*)(priv->tbuffer))[XBOX_BUTTON_TRIGGER_RIGHT]; + priv->rpt.stick_left_x = + ((int16_t*)(priv->tbuffer))[XBOX_BUTTON_STICK_LEFT_X]; + priv->rpt.stick_left_y = + ((int16_t*)(priv->tbuffer))[XBOX_BUTTON_STICK_LEFT_Y]; + priv->rpt.stick_right_x = + ((int16_t*)(priv->tbuffer))[XBOX_BUTTON_STICK_RIGHT_X]; + priv->rpt.stick_right_y = + ((int16_t*)(priv->tbuffer))[XBOX_BUTTON_STICK_RIGHT_Y]; + + priv->valid = true; + + /* Notify any waiters that new controller data is available */ + + usbhost_notify(priv); + + /* Release our lock on the state structure */ + + usbhost_givesem(&priv->exclsem); + } + + break; + + default: + uinfo("Received messge type: %x\n", priv->tbuffer[0]); + } } /* If USB debug is on, then provide some periodic indication that @@ -925,7 +956,7 @@ static int usbhost_sample(FAR struct usbhost_state_s *priv, ****************************************************************************/ static int usbhost_waitsample(FAR struct usbhost_state_s *priv, - FAR struct xbox_controller_buttonstate_s *sample) + FAR struct xbox_controller_buttonstate_s *sample) { irqstate_t flags; int ret; @@ -1142,6 +1173,7 @@ static inline int usbhost_cfgdesc(FAR struct usbhost_state_s *priv, return -EINVAL; } + found |= USBHOST_EPOUTFOUND; /* Save the bulk OUT endpoint information */ @@ -1199,7 +1231,7 @@ static inline int usbhost_cfgdesc(FAR struct usbhost_state_s *priv, if (found == USBHOST_ALLFOUND) { - done=true; + done = true; } /* Increment the address of the next descriptor */ @@ -1563,6 +1595,7 @@ static FAR struct usbhost_class_s *usbhost_create(FAR struct usbhost_hubport_s * { usbhost_freeclass(priv); } + return NULL; } @@ -1785,7 +1818,6 @@ static int usbhost_open(FAR struct file *filep) } leave_critical_section(flags); - usbhost_givesem(&priv->exclsem); return ret; } @@ -1838,7 +1870,7 @@ static int usbhost_close(FAR struct file *filep) * but there is still an outstanding open reference. */ - if (priv->crefs == 0 || (priv->crefs == 1 && priv->polling)) + if (priv->crefs == 0 || (priv->crefs == 1 && priv->polling)) { /* Yes.. In either case, then the driver is no longer open */ @@ -1973,9 +2005,8 @@ errout: static ssize_t usbhost_write(FAR struct file *filep, FAR const char *buffer, size_t len) { - /* Not implemented. */ - + return -ENOSYS; } @@ -1994,7 +2025,8 @@ static int usbhost_ioctl(FAR struct file* filep, int cmd, unsigned long arg) int ret = 0; int nbytes; FAR struct usbhost_hubport_s *hport; - static uint8_t rumble_cmd[] = { + static uint8_t rumble_cmd[] = + { 0x09, 0x00, 0x00, 0x09, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0xff }; @@ -2021,6 +2053,7 @@ static int usbhost_ioctl(FAR struct file* filep, int cmd, unsigned long arg) } /* Determine which IOCTL command to execute. */ + switch (cmd) { @@ -2034,18 +2067,18 @@ static int usbhost_ioctl(FAR struct file* filep, int cmd, unsigned long arg) priv->obuffer[2] = priv->out_seq_num++; priv->obuffer[8] = (arg >> 1) & 0xff; // Strong (left actuator) priv->obuffer[9] = arg & 0xff; // Weak (right actuator) - + /* Perform the transfer. */ - + nbytes = DRVR_TRANSFER(hport->drvr, priv->epout, - priv->obuffer, sizeof(rumble_cmd)); + priv->obuffer, sizeof(rumble_cmd)); /* Did we encounter an error? */ if (nbytes < 0) - { - ret = nbytes; - } + { + ret = nbytes; + } break; @@ -2054,7 +2087,7 @@ static int usbhost_ioctl(FAR struct file* filep, int cmd, unsigned long arg) ret = -EINVAL; goto errout; } - + errout: iinfo("Returning: %d\n", ret); return ret; From 49e4e62aabad09c9d7a1a0b5398fcda993514b13 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Sat, 18 Mar 2017 16:31:06 +0100 Subject: [PATCH 30/81] STM32F33: Move DMA logic to a separate files --- arch/arm/src/stm32/chip/stm32f33xxx_dma.h | 366 ++++++++++++ arch/arm/src/stm32/stm32_dma.c | 5 +- arch/arm/src/stm32/stm32_dma.h | 5 +- arch/arm/src/stm32/stm32f10xxx_dma.c | 3 +- arch/arm/src/stm32/stm32f33xxx_dma.c | 696 ++++++++++++++++++++++ 5 files changed, 1070 insertions(+), 5 deletions(-) create mode 100644 arch/arm/src/stm32/chip/stm32f33xxx_dma.h create mode 100644 arch/arm/src/stm32/stm32f33xxx_dma.c diff --git a/arch/arm/src/stm32/chip/stm32f33xxx_dma.h b/arch/arm/src/stm32/chip/stm32f33xxx_dma.h new file mode 100644 index 00000000000..c30bcb0472c --- /dev/null +++ b/arch/arm/src/stm32/chip/stm32f33xxx_dma.h @@ -0,0 +1,366 @@ +/************************************************************************************ + * arch/arm/src/stm32/chip/stm32f33xxx_dma.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * Mateusz Szafoni + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F33XXX_DMA_H +#define __ARCH_ARM_SRC_STM32_CHIP_STM32F33XXX_DMA_H + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* 12 Channels Total: 7 DMA1 Channels(1-7) and 5 DMA2 channels (1-5) */ + +#define DMA1 0 +#define DMA2 1 +#define DMA3 2 +#define DMA4 3 +#define DMA5 4 +#define DMA6 5 +#define DMA7 6 + +/* Register Offsets *****************************************************************/ + +#define STM32_DMA_ISR_OFFSET 0x0000 /* DMA interrupt status register */ +#define STM32_DMA_IFCR_OFFSET 0x0004 /* DMA interrupt flag clear register */ + +#define STM32_DMACHAN_OFFSET(n) (0x0014*(n)) +#define STM32_DMACHAN1_OFFSET 0x0000 +#define STM32_DMACHAN2_OFFSET 0x0014 +#define STM32_DMACHAN3_OFFSET 0x0028 +#define STM32_DMACHAN4_OFFSET 0x003c +#define STM32_DMACHAN5_OFFSET 0x0050 +#define STM32_DMACHAN6_OFFSET 0x0064 +#define STM32_DMACHAN7_OFFSET 0x0078 + +#define STM32_DMACHAN_CCR_OFFSET 0x0008 /* DMA channel configuration register */ +#define STM32_DMACHAN_CNDTR_OFFSET 0x000c /* DMA channel number of data register */ +#define STM32_DMACHAN_CPAR_OFFSET 0x0010 /* DMA channel peripheral address register */ +#define STM32_DMACHAN_CMAR_OFFSET 0x0014 /* DMA channel 1 memory address register */ + +#define STM32_DMA_CCR_OFFSET(n) (STM32_DMACHAN_CCR_OFFSET+STM32_DMACHAN_OFFSET(n)) +#define STM32_DMA_CNDTR_OFFSET(n) (STM32_DMACHAN_CNDTR_OFFSET+STM32_DMACHAN_OFFSET(n)) +#define STM32_DMA_CPAR_OFFSET(n) (STM32_DMACHAN_CPAR_OFFSET+STM32_DMACHAN_OFFSET(n)) +#define STM32_DMA_CMAR_OFFSET(n) (STM32_DMACHAN_CMAR_OFFSET+STM32_DMACHAN_OFFSET(n)) + +#define STM32_DMA_CCR1_OFFSET 0x0008 /* DMA channel 1 configuration register */ +#define STM32_DMA_CCR2_OFFSET 0x001c /* DMA channel 2 configuration register */ +#define STM32_DMA_CCR3_OFFSET 0x0030 /* DMA channel 3 configuration register */ +#define STM32_DMA_CCR4_OFFSET 0x0044 /* DMA channel 4 configuration register */ +#define STM32_DMA_CCR5_OFFSET 0x0058 /* DMA channel 5 configuration register */ +#define STM32_DMA_CCR6_OFFSET 0x006c /* DMA channel 6 configuration register */ +#define STM32_DMA_CCR7_OFFSET 0x0080 /* DMA channel 7 configuration register */ + +#define STM32_DMA_CNDTR1_OFFSET 0x000c /* DMA channel 1 number of data register */ +#define STM32_DMA_CNDTR2_OFFSET 0x0020 /* DMA channel 2 number of data register */ +#define STM32_DMA_CNDTR3_OFFSET 0x0034 /* DMA channel 3 number of data register */ +#define STM32_DMA_CNDTR4_OFFSET 0x0048 /* DMA channel 4 number of data register */ +#define STM32_DMA_CNDTR5_OFFSET 0x005c /* DMA channel 5 number of data register */ +#define STM32_DMA_CNDTR6_OFFSET 0x0070 /* DMA channel 6 number of data register */ +#define STM32_DMA_CNDTR7_OFFSET 0x0084 /* DMA channel 7 number of data register */ + +#define STM32_DMA_CPAR1_OFFSET 0x0010 /* DMA channel 1 peripheral address register */ +#define STM32_DMA_CPAR2_OFFSET 0x0024 /* DMA channel 2 peripheral address register */ +#define STM32_DMA_CPAR3_OFFSET 0x0038 /* DMA channel 3 peripheral address register */ +#define STM32_DMA_CPAR4_OFFSET 0x004c /* DMA channel 4 peripheral address register */ +#define STM32_DMA_CPAR5_OFFSET 0x0060 /* DMA channel 5 peripheral address register */ +#define STM32_DMA_CPAR6_OFFSET 0x0074 /* DMA channel 6 peripheral address register */ +#define STM32_DMA_CPAR7_OFFSET 0x0088 /* DMA channel 7 peripheral address register */ + +#define STM32_DMA_CMAR1_OFFSET 0x0014 /* DMA channel 1 memory address register */ +#define STM32_DMA_CMAR2_OFFSET 0x0028 /* DMA channel 2 memory address register */ +#define STM32_DMA_CMAR3_OFFSET 0x003c /* DMA channel 3 memory address register */ +#define STM32_DMA_CMAR4_OFFSET 0x0050 /* DMA channel 4 memory address register */ +#define STM32_DMA_CMAR5_OFFSET 0x0064 /* DMA channel 5 memory address register */ +#define STM32_DMA_CMAR6_OFFSET 0x0078 /* DMA channel 6 memory address register */ +#define STM32_DMA_CMAR7_OFFSET 0x008c /* DMA channel 7 memory address register */ + +/* Register Addresses ***************************************************************/ + +#define STM32_DMA1_ISRC (STM32_DMA1_BASE+STM32_DMA_ISR_OFFSET) +#define STM32_DMA1_IFCR (STM32_DMA1_BASE+STM32_DMA_IFCR_OFFSET) + +#define STM32_DMA1_CCR(n) (STM32_DMA1_BASE+STM32_DMA_CCR_OFFSET(n)) +#define STM32_DMA1_CCR1 (STM32_DMA1_BASE+STM32_DMA_CCR1_OFFSET) +#define STM32_DMA1_CCR2 (STM32_DMA1_BASE+STM32_DMA_CCR2_OFFSET) +#define STM32_DMA1_CCR3 (STM32_DMA1_BASE+STM32_DMA_CCR3_OFFSET) +#define STM32_DMA1_CCR4 (STM32_DMA1_BASE+STM32_DMA_CCR4_OFFSET) +#define STM32_DMA1_CCR5 (STM32_DMA1_BASE+STM32_DMA_CCR5_OFFSET) +#define STM32_DMA1_CCR6 (STM32_DMA1_BASE+STM32_DMA_CCR6_OFFSET) +#define STM32_DMA1_CCR7 (STM32_DMA1_BASE+STM32_DMA_CCR7_OFFSET) + +#define STM32_DMA1_CNDTR(n) (STM32_DMA1_BASE+STM32_DMA_CNDTR_OFFSET(n)) +#define STM32_DMA1_CNDTR1 (STM32_DMA1_BASE+STM32_DMA_CNDTR1_OFFSET) +#define STM32_DMA1_CNDTR2 (STM32_DMA1_BASE+STM32_DMA_CNDTR2_OFFSET) +#define STM32_DMA1_CNDTR3 (STM32_DMA1_BASE+STM32_DMA_CNDTR3_OFFSET) +#define STM32_DMA1_CNDTR4 (STM32_DMA1_BASE+STM32_DMA_CNDTR4_OFFSET) +#define STM32_DMA1_CNDTR5 (STM32_DMA1_BASE+STM32_DMA_CNDTR5_OFFSET) +#define STM32_DMA1_CNDTR6 (STM32_DMA1_BASE+STM32_DMA_CNDTR6_OFFSET) +#define STM32_DMA1_CNDTR7 (STM32_DMA1_BASE+STM32_DMA_CNDTR7_OFFSET) + +#define STM32_DMA1_CPAR(n) (STM32_DMA1_BASE+STM32_DMA_CPAR_OFFSET(n)) +#define STM32_DMA1_CPAR1 (STM32_DMA1_BASE+STM32_DMA_CPAR1_OFFSET) +#define STM32_DMA1_CPAR2 (STM32_DMA1_BASE+STM32_DMA_CPAR2_OFFSET) +#define STM32_DMA1_CPAR3 (STM32_DMA1_BASE+STM32_DMA_CPAR3_OFFSET) +#define STM32_DMA1_CPAR4 (STM32_DMA1_BASE+STM32_DMA_CPAR4_OFFSET) +#define STM32_DMA1_CPAR5 (STM32_DMA1_BASE+STM32_DMA_CPAR5_OFFSET) +#define STM32_DMA1_CPAR6 (STM32_DMA1_BASE+STM32_DMA_CPAR6_OFFSET) +#define STM32_DMA1_CPAR7 (STM32_DMA1_BASE+STM32_DMA_CPAR7_OFFSET) + +#define STM32_DMA1_CMAR(n) (STM32_DMA1_BASE+STM32_DMA_CMAR_OFFSET(n)) +#define STM32_DMA1_CMAR1 (STM32_DMA1_BASE+STM32_DMA_CMAR1_OFFSET) +#define STM32_DMA1_CMAR2 (STM32_DMA1_BASE+STM32_DMA_CMAR2_OFFSET) +#define STM32_DMA1_CMAR3 (STM32_DMA1_BASE+STM32_DMA_CMAR3_OFFSET) +#define STM32_DMA1_CMAR4 (STM32_DMA1_BASE+STM32_DMA_CMAR4_OFFSET) +#define STM32_DMA1_CMAR5 (STM32_DMA1_BASE+STM32_DMA_CMAR5_OFFSET) +#define STM32_DMA1_CMAR6 (STM32_DMA1_BASE+STM32_DMA_CMAR6_OFFSET) +#define STM32_DMA1_CMAR7 (STM32_DMA1_BASE+STM32_DMA_CMAR7_OFFSET) + +#define STM32_DMA2_ISRC (STM32_DMA2_BASE+STM32_DMA_ISR_OFFSET) +#define STM32_DMA2_IFCR (STM32_DMA2_BASE+STM32_DMA_IFCR_OFFSET) + +#define STM32_DMA2_CCR(n) (STM32_DMA2_BASE+STM32_DMA_CCR_OFFSET(n)) +#define STM32_DMA2_CCR1 (STM32_DMA2_BASE+STM32_DMA_CCR1_OFFSET) +#define STM32_DMA2_CCR2 (STM32_DMA2_BASE+STM32_DMA_CCR2_OFFSET) +#define STM32_DMA2_CCR3 (STM32_DMA2_BASE+STM32_DMA_CCR3_OFFSET) +#define STM32_DMA2_CCR4 (STM32_DMA2_BASE+STM32_DMA_CCR4_OFFSET) +#define STM32_DMA2_CCR5 (STM32_DMA2_BASE+STM32_DMA_CCR5_OFFSET) + +#define STM32_DMA2_CNDTR(n) (STM32_DMA2_BASE+STM32_DMA_CNDTR_OFFSET(n)) +#define STM32_DMA2_CNDTR1 (STM32_DMA2_BASE+STM32_DMA_CNDTR1_OFFSET) +#define STM32_DMA2_CNDTR2 (STM32_DMA2_BASE+STM32_DMA_CNDTR2_OFFSET) +#define STM32_DMA2_CNDTR3 (STM32_DMA2_BASE+STM32_DMA_CNDTR3_OFFSET) +#define STM32_DMA2_CNDTR4 (STM32_DMA2_BASE+STM32_DMA_CNDTR4_OFFSET) +#define STM32_DMA2_CNDTR5 (STM32_DMA2_BASE+STM32_DMA_CNDTR5_OFFSET) + +#define STM32_DMA2_CPAR(n) (STM32_DMA2_BASE+STM32_DMA_CPAR_OFFSET(n)) +#define STM32_DMA2_CPAR1 (STM32_DMA2_BASE+STM32_DMA_CPAR1_OFFSET) +#define STM32_DMA2_CPAR2 (STM32_DMA2_BASE+STM32_DMA_CPAR2_OFFSET) +#define STM32_DMA2_CPAR3 (STM32_DMA2_BASE+STM32_DMA_CPAR3_OFFSET) +#define STM32_DMA2_CPAR4 (STM32_DMA2_BASE+STM32_DMA_CPAR4_OFFSET) +#define STM32_DMA2_CPAR5 (STM32_DMA2_BASE+STM32_DMA_CPAR5_OFFSET) + +#define STM32_DMA2_CMAR(n) (STM32_DMA2_BASE+STM32_DMA_CMAR_OFFSET(n)) +#define STM32_DMA2_CMAR1 (STM32_DMA2_BASE+STM32_DMA_CMAR1_OFFSET) +#define STM32_DMA2_CMAR2 (STM32_DMA2_BASE+STM32_DMA_CMAR2_OFFSET) +#define STM32_DMA2_CMAR3 (STM32_DMA2_BASE+STM32_DMA_CMAR3_OFFSET) +#define STM32_DMA2_CMAR4 (STM32_DMA2_BASE+STM32_DMA_CMAR4_OFFSET) +#define STM32_DMA2_CMAR5 (STM32_DMA2_BASE+STM32_DMA_CMAR5_OFFSET) + +/* Register Bitfield Definitions ****************************************************/ + +#define DMA_CHAN_SHIFT(n) ((n) << 2) +#define DMA_CHAN_MASK 0x0f +#define DMA_CHAN_GIF_BIT (1 << 0) /* Bit 0: Channel Global interrupt flag */ +#define DMA_CHAN_TCIF_BIT (1 << 1) /* Bit 1: Channel Transfer Complete flag */ +#define DMA_CHAN_HTIF_BIT (1 << 2) /* Bit 2: Channel Half Transfer flag */ +#define DMA_CHAN_TEIF_BIT (1 << 3) /* Bit 3: Channel Transfer Error flag */ + +/* DMA interrupt status register */ + +#define DMA_ISR_CHAN_SHIFT(n) DMA_CHAN_SHIFT(n) +#define DMA_ISR_CHAN_MASK(n) (DMA_CHAN_MASK << DMA_ISR_CHAN_SHIFT(n)) +#define DMA_ISR_CHAN1_SHIFT (0) /* Bits 3-0: DMA Channel 1 interrupt status */ +#define DMA_ISR_CHAN1_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN1_SHIFT) +#define DMA_ISR_CHAN2_SHIFT (4) /* Bits 7-4: DMA Channel 2 interrupt status */ +#define DMA_ISR_CHAN2_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN2_SHIFT) +#define DMA_ISR_CHAN3_SHIFT (8) /* Bits 11-8: DMA Channel 3 interrupt status */ +#define DMA_ISR_CHAN3_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN3_SHIFT) +#define DMA_ISR_CHAN4_SHIFT (12) /* Bits 15-12: DMA Channel 4 interrupt status */ +#define DMA_ISR_CHAN4_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN4_SHIFT) +#define DMA_ISR_CHAN5_SHIFT (16) /* Bits 19-16: DMA Channel 5 interrupt status */ +#define DMA_ISR_CHAN5_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN5_SHIFT) +#define DMA_ISR_CHAN6_SHIFT (20) /* Bits 23-20: DMA Channel 6 interrupt status */ +#define DMA_ISR_CHAN6_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN6_SHIFT) +#define DMA_ISR_CHAN7_SHIFT (24) /* Bits 27-24: DMA Channel 7 interrupt status */ +#define DMA_ISR_CHAN7_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN7_SHIFT) + +#define DMA_ISR_GIF(n) (DMA_CHAN_GIF_BIT << DMA_ISR_CHAN_SHIFT(n)) +#define DMA_ISR_TCIF(n) (DMA_CHAN_TCIF_BIT << DMA_ISR_CHAN_SHIFT(n)) +#define DMA_ISR_HTIF(n) (DMA_CHAN_HTIF_BIT << DMA_ISR_CHAN_SHIFT(n)) +#define DMA_ISR_TEIF(n) (DMA_CHAN_TEIF_BIT << DMA_ISR_CHAN_SHIFT(n)) + +/* DMA interrupt flag clear register */ + +#define DMA_IFCR_CHAN_SHIFT(n) DMA_CHAN_SHIFT(n) +#define DMA_IFCR_CHAN_MASK(n) (DMA_CHAN_MASK << DMA_IFCR_CHAN_SHIFT(n)) +#define DMA_IFCR_CHAN1_SHIFT (0) /* Bits 3-0: DMA Channel 1 interrupt flag clear */ +#define DMA_IFCR_CHAN1_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN1_SHIFT) +#define DMA_IFCR_CHAN2_SHIFT (4) /* Bits 7-4: DMA Channel 2 interrupt flag clear */ +#define DMA_IFCR_CHAN2_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN2_SHIFT) +#define DMA_IFCR_CHAN3_SHIFT (8) /* Bits 11-8: DMA Channel 3 interrupt flag clear */ +#define DMA_IFCR_CHAN3_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN3_SHIFT) +#define DMA_IFCR_CHAN4_SHIFT (12) /* Bits 15-12: DMA Channel 4 interrupt flag clear */ +#define DMA_IFCR_CHAN4_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN4_SHIFT) +#define DMA_IFCR_CHAN5_SHIFT (16) /* Bits 19-16: DMA Channel 5 interrupt flag clear */ +#define DMA_IFCR_CHAN5_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN5_SHIFT) +#define DMA_IFCR_CHAN6_SHIFT (20) /* Bits 23-20: DMA Channel 6 interrupt flag clear */ +#define DMA_IFCR_CHAN6_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN6_SHIFT) +#define DMA_IFCR_CHAN7_SHIFT (24) /* Bits 27-24: DMA Channel 7 interrupt flag clear */ +#define DMA_IFCR_CHAN7_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN7_SHIFT) +#define DMA_IFCR_ALLCHANNELS (0x0fffffff) + +#define DMA_IFCR_CGIF(n) (DMA_CHAN_GIF_BIT << DMA_IFCR_CHAN_SHIFT(n)) +#define DMA_IFCR_CTCIF(n) (DMA_CHAN_TCIF_BIT << DMA_IFCR_CHAN_SHIFT(n)) +#define DMA_IFCR_CHTIF(n) (DMA_CHAN_HTIF_BIT << DMA_IFCR_CHAN_SHIFT(n)) +#define DMA_IFCR_CTEIF(n) (DMA_CHAN_TEIF_BIT << DMA_IFCR_CHAN_SHIFT(n)) + +/* DMA channel configuration register */ + +#define DMA_CCR_EN (1 << 0) /* Bit 0: Channel enable */ +#define DMA_CCR_TCIE (1 << 1) /* Bit 1: Transfer complete interrupt enable */ +#define DMA_CCR_HTIE (1 << 2) /* Bit 2: Half Transfer interrupt enable */ +#define DMA_CCR_TEIE (1 << 3) /* Bit 3: Transfer error interrupt enable */ +#define DMA_CCR_DIR (1 << 4) /* Bit 4: Data transfer direction */ +#define DMA_CCR_CIRC (1 << 5) /* Bit 5: Circular mode */ +#define DMA_CCR_PINC (1 << 6) /* Bit 6: Peripheral increment mode */ +#define DMA_CCR_MINC (1 << 7) /* Bit 7: Memory increment mode */ +#define DMA_CCR_PSIZE_SHIFT (8) /* Bits 8-9: Peripheral size */ +#define DMA_CCR_PSIZE_MASK (3 << DMA_CCR_PSIZE_SHIFT) +# define DMA_CCR_PSIZE_8BITS (0 << DMA_CCR_PSIZE_SHIFT) /* 00: 8-bits */ +# define DMA_CCR_PSIZE_16BITS (1 << DMA_CCR_PSIZE_SHIFT) /* 01: 16-bits */ +# define DMA_CCR_PSIZE_32BITS (2 << DMA_CCR_PSIZE_SHIFT) /* 10: 32-bits */ +#define DMA_CCR_MSIZE_SHIFT (10) /* Bits 10-11: Memory size */ +#define DMA_CCR_MSIZE_MASK (3 << DMA_CCR_MSIZE_SHIFT) +# define DMA_CCR_MSIZE_8BITS (0 << DMA_CCR_MSIZE_SHIFT) /* 00: 8-bits */ +# define DMA_CCR_MSIZE_16BITS (1 << DMA_CCR_MSIZE_SHIFT) /* 01: 16-bits */ +# define DMA_CCR_MSIZE_32BITS (2 << DMA_CCR_MSIZE_SHIFT) /* 10: 32-bits */ +#define DMA_CCR_PL_SHIFT (12) /* Bits 12-13: Channel Priority level */ +#define DMA_CCR_PL_MASK (3 << DMA_CCR_PL_SHIFT) +# define DMA_CCR_PRILO (0 << DMA_CCR_PL_SHIFT) /* 00: Low */ +# define DMA_CCR_PRIMED (1 << DMA_CCR_PL_SHIFT) /* 01: Medium */ +# define DMA_CCR_PRIHI (2 << DMA_CCR_PL_SHIFT) /* 10: High */ +# define DMA_CCR_PRIVERYHI (3 << DMA_CCR_PL_SHIFT) /* 11: Very high */ +#define DMA_CCR_MEM2MEM (1 << 14) /* Bit 14: Memory to memory mode */ + +#define DMA_CCR_ALLINTS (DMA_CCR_TEIE|DMA_CCR_HTIE|DMA_CCR_TCIE) + +/* DMA channel number of data register */ + +#define DMA_CNDTR_NDT_SHIFT (0) /* Bits 15-0: Number of data to Transfer */ +#define DMA_CNDTR_NDT_MASK (0xffff << DMA_CNDTR_NDT_SHIFT) + +/* DMA Channel mapping. Each DMA channel has a mapping to several possible + * sources/sinks of data. The requests from peripherals assigned to a channel + * are simply OR'ed together before entering the DMA block. This means that only + * one request on a given channel can be enabled at once. + * + * Alternative DMA channel selections are provided with a numeric suffix like _1, + * _2, etc. Drivers, however, will use the pin selection without the numeric suffix. + * Additional definitions are required in the board.h file. + */ + +#define STM32_DMA1_CHAN1 (0) +#define STM32_DMA1_CHAN2 (1) +#define STM32_DMA1_CHAN3 (2) +#define STM32_DMA1_CHAN4 (3) +#define STM32_DMA1_CHAN5 (4) +#define STM32_DMA1_CHAN6 (5) +#define STM32_DMA1_CHAN7 (6) + +#define STM32_DMA2_CHAN1 (7) +#define STM32_DMA2_CHAN2 (8) +#define STM32_DMA2_CHAN3 (9) +#define STM32_DMA2_CHAN4 (10) +#define STM32_DMA2_CHAN5 (11) + +#define DMACHAN_ADC1 STM32_DMA1_CHAN1 +#define DMACHAN_TIM2_CH3 STM32_DMA1_CHAN1 +#define DMACHAN_TIM17_CH1_1 STM32_DMA1_CHAN1 +#define DMACHAN_TIM17_UP_1 STM32_DMA1_CHAN1 + +#define DMACHAN_ADC2_1 STM32_DMA1_CHAN2 +#define DMACHAN_SPI1_RX_1 STM32_DMA1_CHAN2 +#define DMACHAN_USART3_TX STM32_DMA1_CHAN2 +#define DMACHAN_I2C1_TX_3 STM32_DMA1_CHAN4 +#define DMACHAN_TIM1_CH1 STM32_DMA1_CHAN2 +#define DMACHAN_TIM2_UP STM32_DMA1_CHAN2 +#define DMACHAN_TIM3_CH3 STM32_DMA1_CHAN2 +#define DMACHAN_HRTIM1_M STM32_DMA1_CHAN2 + +#define DMACHAN_SPI1_TX_1 STM32_DMA1_CHAN3 +#define DMACHAN_USART3_RX STM32_DMA1_CHAN3 +#define DMACHAN_I2C1_RX_2 STM32_DMA1_CHAN3 +#define DMACHAN_TIM3_CH4 STM32_DMA1_CHAN3 +#define DMACHAN_TIM3_UP STM32_DMA1_CHAN3 +#define DMACHAN_TIM6_UP STM32_DMA1_CHAN3 +#define DMACHAN_DAC1_CH1 STM32_DMA1_CHAN3 +#define DMACHAN_DAC16_CH1_1 STM32_DMA1_CHAN3 +#define DMACHAN_DAC16_UP_1 STM32_DMA1_CHAN3 +#define DMACHAN_HRTIM1_A STM32_DMA1_CHAN3 + +#define DMACHAN_ADC2_2 STM32_DMA1_CHAN4 +#define DMACHAN_SPI1_RX_2 STM32_DMA1_CHAN4 +#define DMACHAN_USART1_TX STM32_DMA1_CHAN4 +#define DMACHAN_I2C1_TX_3 STM32_DMA1_CHAN4 +#define DMACHAN_TIM1_CH4 STM32_DMA1_CHAN4 +#define DMACHAN_TIM1_TRIG STM32_DMA1_CHAN4 +#define DMACHAN_TIM1_COM STM32_DMA1_CHAN4 +#define DMACHAN_TIM7_UP STM32_DMA1_CHAN4 +#define DMACHAN_DAC2_CH2 STM32_DMA1_CHAN4 +#define DMACHAN_HRTIM1_B STM32_DMA1_CHAN4 + +#define DMACHAN_SPI1_TX_2 STM32_DMA1_CHAN5 +#define DMACHAN_USART1_RX STM32_DMA1_CHAN5 +#define DMACHAN_I2C1_RX_3 STM32_DMA1_CHAN5 +#define DMACHAN_TIM1_UP STM32_DMA1_CHAN5 +#define DMACHAN_TIM2_CH1 STM32_DMA1_CHAN5 +#define DMACHAN_DAC2_CH1 STM32_DMA1_CHAN5 +#define DMACHAN_TIM15_CH1 STM32_DMA1_CHAN5 +#define DMACHAN_TIM15_UP STM32_DMA1_CHAN5 +#define DMACHAN_TIM15_TRIG STM32_DMA1_CHAN5 +#define DMACHAN_TIM15_COM STM32_DMA1_CHAN5 +#define DMACHAN_HRTIM1_C STM32_DMA1_CHAN5 + +#define DMACHAN_SPI1_RX_3 STM32_DMA1_CHAN6 +#define DMACHAN_USART2_RX STM32_DMA1_CHAN6 +#define DMACHAN_I2C1_TX_1 STM32_DMA1_CHAN6 +#define DMACHAN_TIM1_CH3 STM32_DMA1_CHAN6 +#define DMACHAN_TIM3_CH1 STM32_DMA1_CHAN6 +#define DMACHAN_TIM3_TRIG STM32_DMA1_CHAN6 +#define DMACHAN_TIM16_CH1_2 STM32_DMA1_CHAN6 +#define DMACHAN_TIM16_UP_2 STM32_DMA1_CHAN6 +#define DMACHAN_HRTIM1_D STM32_DMA1_CHAN6 + +#define DMACHAN_SPI1_TX_3 STM32_DMA1_CHAN7 +#define DMACHAN_USART2_TX STM32_DMA1_CHAN7 +#define DMACHAN_I2C1_RX_1 STM32_DMA1_CHAN7 +#define DMACHAN_TIM2_CH2 STM32_DMA1_CHAN7 +#define DMACHAN_TIM2_CH4 STM32_DMA1_CHAN7 +#define DMACHAN_TIM17_CH1_2 STM32_DMA1_CHAN7 +#define DMACHAN_TIM17_UP_2 STM32_DMA1_CHAN7 +#define DMACHAN_HRTIM1_E STM32_DMA1_CHAN7 + +#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F33XXX_DMA_H */ diff --git a/arch/arm/src/stm32/stm32_dma.c b/arch/arm/src/stm32/stm32_dma.c index 0de9cdcc3b8..9118c586d48 100644 --- a/arch/arm/src/stm32/stm32_dma.c +++ b/arch/arm/src/stm32/stm32_dma.c @@ -56,9 +56,10 @@ */ #if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || \ - defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ - defined(CONFIG_STM32_STM32F37XX) + defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) # include "stm32f10xxx_dma.c" +#elif defined(CONFIG_STM32_STM32F33XX) +# include "stm32f33xxx_dma.c" #elif defined(CONFIG_STM32_STM32F20XX) # include "stm32f20xxx_dma.c" #elif defined(CONFIG_STM32_STM32F40XX) diff --git a/arch/arm/src/stm32/stm32_dma.h b/arch/arm/src/stm32/stm32_dma.h index 36c21f3ca60..c29f7f0d8c2 100644 --- a/arch/arm/src/stm32/stm32_dma.h +++ b/arch/arm/src/stm32/stm32_dma.h @@ -48,9 +48,10 @@ /* Include the correct DMA register definitions for this STM32 family */ #if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || \ - defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ - defined(CONFIG_STM32_STM32F37XX) + defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) # include "chip/stm32f10xxx_dma.h" +#elif defined(CONFIG_STM32_STM32F33XX) +# include "chip/stm32f33xxx_dma.h" #elif defined(CONFIG_STM32_STM32F20XX) # include "chip/stm32f20xxx_dma.h" #elif defined(CONFIG_STM32_STM32F40XX) diff --git a/arch/arm/src/stm32/stm32f10xxx_dma.c b/arch/arm/src/stm32/stm32f10xxx_dma.c index 1e6751ee563..65136a450f6 100644 --- a/arch/arm/src/stm32/stm32f10xxx_dma.c +++ b/arch/arm/src/stm32/stm32f10xxx_dma.c @@ -57,7 +57,8 @@ #if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) || \ - defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32L15XX) + defined(CONFIG_STM32_STM32F33XX) || defined(CONFIG_STM32_STM32F37XX) || \ + defined(CONFIG_STM32_STM32L15XX) /**************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/stm32/stm32f33xxx_dma.c b/arch/arm/src/stm32/stm32f33xxx_dma.c new file mode 100644 index 00000000000..af8601a0fb6 --- /dev/null +++ b/arch/arm/src/stm32/stm32f33xxx_dma.c @@ -0,0 +1,696 @@ +/**************************************************************************** + * arch/arm/src/stm32/stm32f33xxx_dma.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * Mateusz Szafoni + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include + +#include "up_arch.h" +#include "up_internal.h" +#include "sched/sched.h" +#include "chip.h" +#include "stm32_dma.h" +#include "stm32.h" + +#if defined(CONFIG_STM32_DMA1) && defined(CONFIG_STM32_STM32F33XX) + +#ifndef CONFIG_ARCH_DMA +# warning "STM32 DMA enabled but CONFIG_ARCH_DMA disabled" +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define DMA1_NCHANNELS 7 +#define DMA_NCHANNELS DMA1_NCHANNELS + +#ifndef CONFIG_DMA_PRI +# define CONFIG_DMA_PRI NVIC_SYSH_PRIORITY_DEFAULT +#endif + +/* Convert the DMA channel base address to the DMA register block address */ + +#define DMA_BASE(ch) (ch & 0xfffffc00) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* This structure descibes one DMA channel */ + +struct stm32_dma_s +{ + uint8_t chan; /* DMA channel number (0-6) */ + uint8_t irq; /* DMA channel IRQ number */ + sem_t sem; /* Used to wait for DMA channel to become available */ + uint32_t base; /* DMA register channel base address */ + dma_callback_t callback; /* Callback invoked when the DMA completes */ + void *arg; /* Argument passed to callback function */ +}; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This array describes the state of each DMA */ + +static struct stm32_dma_s g_dma[DMA_NCHANNELS] = +{ + { + .chan = 0, + .irq = STM32_IRQ_DMA1CH1, + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(0), + }, + { + .chan = 1, + .irq = STM32_IRQ_DMA1CH2, + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(1), + }, + { + .chan = 2, + .irq = STM32_IRQ_DMA1CH3, + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(2), + }, + { + .chan = 3, + .irq = STM32_IRQ_DMA1CH4, + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(3), + }, + { + .chan = 4, + .irq = STM32_IRQ_DMA1CH5, + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(4), + }, + { + .chan = 5, + .irq = STM32_IRQ_DMA1CH6, + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(5), + }, + { + .chan = 6, + .irq = STM32_IRQ_DMA1CH7, + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(6), + }, +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * DMA register access functions + ****************************************************************************/ + +/* Get non-channel register from DMA1 or DMA2 */ + +static inline uint32_t dmabase_getreg(struct stm32_dma_s *dmach, uint32_t offset) +{ + return getreg32(DMA_BASE(dmach->base) + offset); +} + +/* Write to non-channel register in DMA1 or DMA2 */ + +static inline void dmabase_putreg(struct stm32_dma_s *dmach, uint32_t offset, uint32_t value) +{ + putreg32(value, DMA_BASE(dmach->base) + offset); +} + +/* Get channel register from DMA1 or DMA2 */ + +static inline uint32_t dmachan_getreg(struct stm32_dma_s *dmach, uint32_t offset) +{ + return getreg32(dmach->base + offset); +} + +/* Write to channel register in DMA1 or DMA2 */ + +static inline void dmachan_putreg(struct stm32_dma_s *dmach, uint32_t offset, uint32_t value) +{ + putreg32(value, dmach->base + offset); +} + +/************************************************************************************ + * Name: stm32_dmatake() and stm32_dmagive() + * + * Description: + * Used to get exclusive access to a DMA channel. + * + ************************************************************************************/ + +static void stm32_dmatake(FAR struct stm32_dma_s *dmach) +{ + /* Take the semaphore (perhaps waiting) */ + + while (sem_wait(&dmach->sem) != 0) + { + /* The only case that an error should occur here is if the wait was awakened + * by a signal. + */ + + ASSERT(errno == EINTR); + } +} + +static inline void stm32_dmagive(FAR struct stm32_dma_s *dmach) +{ + (void)sem_post(&dmach->sem); +} + +/************************************************************************************ + * Name: stm32_dmachandisable + * + * Description: + * Disable the DMA channel + * + ************************************************************************************/ + +static void stm32_dmachandisable(struct stm32_dma_s *dmach) +{ + uint32_t regval; + + /* Disable all interrupts at the DMA controller */ + + regval = dmachan_getreg(dmach, STM32_DMACHAN_CCR_OFFSET); + regval &= ~DMA_CCR_ALLINTS; + + /* Disable the DMA channel */ + + regval &= ~DMA_CCR_EN; + dmachan_putreg(dmach, STM32_DMACHAN_CCR_OFFSET, regval); + + /* Clear pending channel interrupts */ + + dmabase_putreg(dmach, STM32_DMA_IFCR_OFFSET, DMA_ISR_CHAN_MASK(dmach->chan)); +} + +/************************************************************************************ + * Name: stm32_dmainterrupt + * + * Description: + * DMA interrupt handler + * + ************************************************************************************/ + +static int stm32_dmainterrupt(int irq, void *context, FAR void *arg) +{ + struct stm32_dma_s *dmach; + uint32_t isr; + int chndx = 0; + + /* Get the channel structure from the interrupt number */ + + if (irq >= STM32_IRQ_DMA1CH1 && irq <= STM32_IRQ_DMA1CH7) + { + chndx = irq - STM32_IRQ_DMA1CH1; + } + else + { + PANIC(); + } + dmach = &g_dma[chndx]; + + /* Get the interrupt status (for this channel only) */ + + isr = dmabase_getreg(dmach, STM32_DMA_ISR_OFFSET) & DMA_ISR_CHAN_MASK(dmach->chan); + + /* Clear the interrupts we are handling */ + + dmabase_putreg(dmach, STM32_DMA_IFCR_OFFSET, isr); + + /* Invoke the callback */ + + if (dmach->callback) + { + dmach->callback(dmach, isr >> DMA_ISR_CHAN_SHIFT(dmach->chan), dmach->arg); + } + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_dmainitialize + * + * Description: + * Initialize the DMA subsystem + * + * Returned Value: + * None + * + ****************************************************************************/ + +void weak_function up_dmainitialize(void) +{ + struct stm32_dma_s *dmach; + int chndx; + + /* Initialize each DMA channel */ + + for (chndx = 0; chndx < DMA_NCHANNELS; chndx++) + { + dmach = &g_dma[chndx]; + sem_init(&dmach->sem, 0, 1); + + /* Attach DMA interrupt vectors */ + + (void)irq_attach(dmach->irq, stm32_dmainterrupt, NULL); + + /* Disable the DMA channel */ + + stm32_dmachandisable(dmach); + + /* Enable the IRQ at the NVIC (still disabled at the DMA controller) */ + + up_enable_irq(dmach->irq); + +#ifdef CONFIG_ARCH_IRQPRIO + /* Set the interrupt priority */ + + up_prioritize_irq(dmach->irq, CONFIG_DMA_PRI); +#endif + } +} + +/**************************************************************************** + * Name: stm32_dmachannel + * + * Description: + * Allocate a DMA channel. This function gives the caller mutually + * exclusive access to the DMA channel specified by the 'chndx' argument. + * DMA channels are shared on the STM32: Devices sharing the same DMA + * channel cannot do DMA concurrently! See the DMACHAN_* definitions in + * stm32_dma.h. + * + * If the DMA channel is not available, then stm32_dmachannel() will wait + * until the holder of the channel relinquishes the channel by calling + * stm32_dmafree(). WARNING: If you have two devices sharing a DMA + * channel and the code never releases the channel, the stm32_dmachannel + * call for the other will hang forever in this function! Don't let your + * design do that! + * + * Hmm.. I suppose this interface could be extended to make a non-blocking + * version. Feel free to do that if that is what you need. + * + * Input parameter: + * chndx - Identifies the stream/channel resource. For the STM32 F1, this + * is simply the channel number as provided by the DMACHAN_* definitions + * in chip/stm32f10xxx_dma.h. + * + * Returned Value: + * Provided that 'chndx' is valid, this function ALWAYS returns a non-NULL, + * void* DMA channel handle. (If 'chndx' is invalid, the function will + * assert if debug is enabled or do something ignorant otherwise). + * + * Assumptions: + * - The caller does not hold he DMA channel. + * - The caller can wait for the DMA channel to be freed if it is no + * available. + * + ****************************************************************************/ + +DMA_HANDLE stm32_dmachannel(unsigned int chndx) +{ + struct stm32_dma_s *dmach = &g_dma[chndx]; + + DEBUGASSERT(chndx < DMA_NCHANNELS); + + /* Get exclusive access to the DMA channel -- OR wait until the channel + * is available if it is currently being used by another driver + */ + + stm32_dmatake(dmach); + + /* The caller now has exclusive use of the DMA channel */ + + return (DMA_HANDLE)dmach; +} + +/**************************************************************************** + * Name: stm32_dmafree + * + * Description: + * Release a DMA channel. If another thread is waiting for this DMA channel + * in a call to stm32_dmachannel, then this function will re-assign the + * DMA channel to that thread and wake it up. NOTE: The 'handle' used + * in this argument must NEVER be used again until stm32_dmachannel() is + * called again to re-gain access to the channel. + * + * Returned Value: + * None + * + * Assumptions: + * - The caller holds the DMA channel. + * - There is no DMA in progress + * + ****************************************************************************/ + +void stm32_dmafree(DMA_HANDLE handle) +{ + struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle; + + DEBUGASSERT(handle != NULL); + + /* Release the channel */ + + stm32_dmagive(dmach); +} + +/**************************************************************************** + * Name: stm32_dmasetup + * + * Description: + * Configure DMA before using + * + ****************************************************************************/ + +void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, + size_t ntransfers, uint32_t ccr) +{ + struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle; + uint32_t regval; + + /* Then DMA_CNDTRx register can only be modified if the DMA channel is + * disabled. + */ + + regval = dmachan_getreg(dmach, STM32_DMACHAN_CCR_OFFSET); + regval &= ~(DMA_CCR_EN); + dmachan_putreg(dmach, STM32_DMACHAN_CCR_OFFSET, regval); + + /* Set the peripheral register address in the DMA_CPARx register. The data + * will be moved from/to this address to/from the memory after the + * peripheral event. + */ + + dmachan_putreg(dmach, STM32_DMACHAN_CPAR_OFFSET, paddr); + + /* Set the memory address in the DMA_CMARx register. The data will be + * written to or read from this memory after the peripheral event. + */ + + dmachan_putreg(dmach, STM32_DMACHAN_CMAR_OFFSET, maddr); + + /* Configure the total number of data to be transferred in the DMA_CNDTRx + * register. After each peripheral event, this value will be decremented. + */ + + dmachan_putreg(dmach, STM32_DMACHAN_CNDTR_OFFSET, ntransfers); + + /* Configure the channel priority using the PL[1:0] bits in the DMA_CCRx + * register. Configure data transfer direction, circular mode, peripheral & memory + * incremented mode, peripheral & memory data size, and interrupt after + * half and/or full transfer in the DMA_CCRx register. + */ + + regval = dmachan_getreg(dmach, STM32_DMACHAN_CCR_OFFSET); + regval &= ~(DMA_CCR_MEM2MEM | DMA_CCR_PL_MASK | DMA_CCR_MSIZE_MASK | + DMA_CCR_PSIZE_MASK | DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | + DMA_CCR_DIR); + ccr &= (DMA_CCR_MEM2MEM | DMA_CCR_PL_MASK | DMA_CCR_MSIZE_MASK | + DMA_CCR_PSIZE_MASK | DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | + DMA_CCR_DIR); + regval |= ccr; + dmachan_putreg(dmach, STM32_DMACHAN_CCR_OFFSET, regval); +} + +/**************************************************************************** + * Name: stm32_dmastart + * + * Description: + * Start the DMA transfer + * + * Assumptions: + * - DMA handle allocated by stm32_dmachannel() + * - No DMA in progress + * + ****************************************************************************/ + +void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, + void *arg, bool half) +{ + struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle; + uint32_t ccr; + + DEBUGASSERT(handle != NULL); + + /* Save the callback info. This will be invoked whent the DMA commpletes */ + + dmach->callback = callback; + dmach->arg = arg; + + /* Activate the channel by setting the ENABLE bit in the DMA_CCRx register. + * As soon as the channel is enabled, it can serve any DMA request from the + * peripheral connected on the channel. + */ + + ccr = dmachan_getreg(dmach, STM32_DMACHAN_CCR_OFFSET); + ccr |= DMA_CCR_EN; + + /* In normal mode, interrupt at either half or full completion. In circular mode, + * always interrupt on buffer wrap, and optionally interrupt at the halfway point. + */ + + if ((ccr & DMA_CCR_CIRC) == 0) + { + /* Once half of the bytes are transferred, the half-transfer flag (HTIF) is + * set and an interrupt is generated if the Half-Transfer Interrupt Enable + * bit (HTIE) is set. At the end of the transfer, the Transfer Complete Flag + * (TCIF) is set and an interrupt is generated if the Transfer Complete + * Interrupt Enable bit (TCIE) is set. + */ + + ccr |= (half ? (DMA_CCR_HTIE | DMA_CCR_TEIE) : (DMA_CCR_TCIE | DMA_CCR_TEIE)); + } + else + { + /* In nonstop mode, when the transfer completes it immediately resets + * and starts again. The transfer-complete interrupt is thus always + * enabled, and the half-complete interrupt can be used in circular + * mode to determine when the buffer is half-full, or in double-buffered + * mode to determine when one of the two buffers is full. + */ + + ccr |= (half ? DMA_CCR_HTIE : 0) | DMA_CCR_TCIE | DMA_CCR_TEIE; + } + + dmachan_putreg(dmach, STM32_DMACHAN_CCR_OFFSET, ccr); +} + +/**************************************************************************** + * Name: stm32_dmastop + * + * Description: + * Cancel the DMA. After stm32_dmastop() is called, the DMA channel is + * reset and stm32_dmasetup() must be called before stm32_dmastart() can be + * called again + * + * Assumptions: + * - DMA handle allocated by stm32_dmachannel() + * + ****************************************************************************/ + +void stm32_dmastop(DMA_HANDLE handle) +{ + struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle; + stm32_dmachandisable(dmach); +} + +/**************************************************************************** + * Name: stm32_dmaresidual + * + * Description: + * Returns the number of bytes remaining to be transferred + * + * Assumptions: + * - DMA handle allocated by stm32_dmachannel() + * + ****************************************************************************/ + +size_t stm32_dmaresidual(DMA_HANDLE handle) +{ + struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle; + + return dmachan_getreg(dmach, STM32_DMACHAN_CNDTR_OFFSET); +} + +/**************************************************************************** + * Name: stm32_dmacapable + * + * Description: + * Check if the DMA controller can transfer data to/from given memory + * address. This depends on the internal connections in the ARM bus matrix + * of the processor. Note that this only applies to memory addresses, it + * will return false for any peripheral address. + * + * Returned value: + * True, if transfer is possible. + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_DMACAPABLE +bool stm32_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr) +{ + uint32_t transfer_size; + uint32_t mend; + + /* Verify that the address conforms to the memory transfer size. + * Transfers to/from memory performed by the DMA controller are + * required to be aligned to their size. + * + * See ST RM0090 rev4, section 9.3.11 + * + * Compute mend inline to avoid a possible non-constant integer + * multiply. + */ + + switch (ccr & DMA_CCR_MSIZE_MASK) + { + case DMA_CCR_MSIZE_8BITS: + transfer_size = 1; + mend = maddr + count - 1; + break; + + case DMA_CCR_MSIZE_16BITS: + transfer_size = 2; + mend = maddr + (count << 1) - 1; + break; + + case DMA_CCR_MSIZE_32BITS: + transfer_size = 4; + mend = maddr + (count << 2) - 1; + break; + + default: + return false; + } + + if ((maddr & (transfer_size - 1)) != 0) + { + return false; + } + + /* Verify that the transfer is to a memory region that supports DMA. */ + + if ((maddr & STM32_REGION_MASK) != (mend & STM32_REGION_MASK)) + { + return false; + } + + switch (maddr & STM32_REGION_MASK) + { + case STM32_SRAM_BASE: + case STM32_CODE_BASE: + /* All RAM and flash is supported */ + + return true; + + default: + /* Everything else is unsupported by DMA */ + + return false; + } +} +#endif + +/**************************************************************************** + * Name: stm32_dmasample + * + * Description: + * Sample DMA register contents + * + * Assumptions: + * - DMA handle allocated by stm32_dmachannel() + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_DMA_INFO +void stm32_dmasample(DMA_HANDLE handle, struct stm32_dmaregs_s *regs) +{ + struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle; + irqstate_t flags; + + flags = enter_critical_section(); + regs->isr = dmabase_getreg(dmach, STM32_DMA_ISR_OFFSET); + regs->ccr = dmachan_getreg(dmach, STM32_DMACHAN_CCR_OFFSET); + regs->cndtr = dmachan_getreg(dmach, STM32_DMACHAN_CNDTR_OFFSET); + regs->cpar = dmachan_getreg(dmach, STM32_DMACHAN_CPAR_OFFSET); + regs->cmar = dmachan_getreg(dmach, STM32_DMACHAN_CMAR_OFFSET); + leave_critical_section(flags); +} +#endif + +/**************************************************************************** + * Name: stm32_dmadump + * + * Description: + * Dump previously sampled DMA register contents + * + * Assumptions: + * - DMA handle allocated by stm32_dmachannel() + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_DMA_INFO +void stm32_dmadump(DMA_HANDLE handle, const struct stm32_dmaregs_s *regs, + const char *msg) +{ + struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle; + uint32_t dmabase = DMA_BASE(dmach->base); + + dmainfo("DMA Registers: %s\n", msg); + dmainfo(" ISRC[%08x]: %08x\n", dmabase + STM32_DMA_ISR_OFFSET, regs->isr); + dmainfo(" CCR[%08x]: %08x\n", dmach->base + STM32_DMACHAN_CCR_OFFSET, regs->ccr); + dmainfo(" CNDTR[%08x]: %08x\n", dmach->base + STM32_DMACHAN_CNDTR_OFFSET, regs->cndtr); + dmainfo(" CPAR[%08x]: %08x\n", dmach->base + STM32_DMACHAN_CPAR_OFFSET, regs->cpar); + dmainfo(" CMAR[%08x]: %08x\n", dmach->base + STM32_DMACHAN_CMAR_OFFSET, regs->cmar); +} +#endif + +#endif /* CONFIG_STM32_DMA1 && CONFIG_STM32_STM32F33XX */ From fd42900dcc64ad2cf4d45fd4f4d7cfb98b6eccfb Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Sat, 18 Mar 2017 16:34:24 +0100 Subject: [PATCH 31/81] STM32F33: Add ADC support --- arch/arm/src/stm32/stm32_adc.c | 69 ++++++++++++++++++++++------------ 1 file changed, 44 insertions(+), 25 deletions(-) diff --git a/arch/arm/src/stm32/stm32_adc.c b/arch/arm/src/stm32/stm32_adc.c index ef91b77b40f..66ae2ce8b05 100644 --- a/arch/arm/src/stm32/stm32_adc.c +++ b/arch/arm/src/stm32/stm32_adc.c @@ -6,6 +6,7 @@ * Authors: Gregory Nutt * Diego Sanchez * Paul Alexander Patience + * Mateusz Szafoni * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -77,11 +78,12 @@ #if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || \ defined(CONFIG_STM32_ADC3) || defined(CONFIG_STM32_ADC4) -/* This implementation is for the STM32 F1, F2, F4 and STM32L15XX only */ +/* This implementation is for the STM32 F1, F2, F3, F4 and STM32L15XX only */ #if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F20XX) || \ - defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) || \ - defined(CONFIG_STM32_STM32F40XX) || defined(CONFIG_STM32_STM32L15XX) + defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ + defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F40XX) || \ + defined(CONFIG_STM32_STM32L15XX) /* At the moment there is no proper implementation for timers external * trigger in STM32L15XX May be added latter @@ -91,6 +93,14 @@ # warning "There is no proper implementation for TIMER TRIGGERS at the moment" #endif +/* At the moment there is no proper implementation for HRTIMER external + * trigger in STM32F33XX + */ + +#if defined(ADC_HAVE_HRTIMER) && defined(CONFIG_STM32_STM32F33XX) +# warning "There is no proper implementation for HRTIMER TRIGGERS at the moment" +#endif + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -108,6 +118,10 @@ # define RCC_RSTR_ADC2RST RCC_AHBRSTR_ADC12RST # define RCC_RSTR_ADC3RST RCC_AHBRSTR_ADC34RST # define RCC_RSTR_ADC4RST RCC_AHBRSTR_ADC34RST +#elif defined(CONFIG_STM32_STM32F33XX) +# define STM32_RCC_RSTR STM32_RCC_AHBRSTR +# define RCC_RSTR_ADC1RST RCC_AHBRSTR_ADC12RST +# define RCC_RSTR_ADC2RST RCC_AHBRSTR_ADC12RST #elif defined(CONFIG_STM32_STM32F37XX) # define STM32_RCC_RSTR STM32_RCC_APB2RSTR # define RCC_RSTR_ADC1RST RCC_APB2RSTR_ADCRST @@ -124,7 +138,7 @@ /* ADC interrupts ***********************************************************/ -#ifdef CONFIG_STM32_STM32F30XX +#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) # define STM32_ADC_DMAREG_OFFSET STM32_ADC_CFGR_OFFSET # define ADC_DMAREG_DMA ADC_CFGR_DMAEN # define STM32_ADC_EXTREG_OFFSET STM32_ADC_CFGR_OFFSET @@ -226,7 +240,7 @@ (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP7_SHIFT) | \ (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP8_SHIFT) | \ (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP9_SHIFT)) -#elif defined(CONFIG_STM32_STM32F30XX) +#elif defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) # if defined(ADC_HAVE_DMA) || (ADC_MAX_SAMPLES == 1) # define ADC_SMPR_DEFAULT ADC_SMPR_61p5 # else /* Slow down sampling frequency */ @@ -338,8 +352,8 @@ struct stm32_dev_s /* ADC Register access */ #if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \ - defined(CONFIG_STM32_STM32F37XX) ||defined(CONFIG_STM32_STM32F40XX) || \ - defined(CONFIG_STM32_STM32L15XX) + defined(CONFIG_STM32_STM32F33XX) || defined(CONFIG_STM32_STM32F37XX) || \ + defined(CONFIG_STM32_STM32F40XX) || defined(CONFIG_STM32_STM32L15XX) static void stm32_modifyreg32(unsigned int addr, uint32_t clrbits, uint32_t setbits); #endif @@ -606,8 +620,8 @@ static struct adc_dev_s g_adcdev4 = ****************************************************************************/ #if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \ - defined(CONFIG_STM32_STM32F37XX) ||defined(CONFIG_STM32_STM32F40XX) || \ - defined(CONFIG_STM32_STM32L15XX) + defined(CONFIG_STM32_STM32F33XX) || defined(CONFIG_STM32_STM32F37XX) || \ + defined(CONFIG_STM32_STM32F40XX) || defined(CONFIG_STM32_STM32L15XX) static void stm32_modifyreg32(unsigned int addr, uint32_t clrbits, uint32_t setbits) { @@ -1242,7 +1256,7 @@ static void adc_startconv(FAR struct stm32_dev_s *priv, bool enable) adc_enable(priv, true); } -#elif defined(CONFIG_STM32_STM32F30XX) +#elif defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) static void adc_startconv(FAR struct stm32_dev_s *priv, bool enable) { uint32_t regval; @@ -1520,7 +1534,7 @@ static void adc_select_ch_bank(FAR struct stm32_dev_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32_STM32F30XX +#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) static void adc_enable(FAR struct stm32_dev_s *priv, bool enable) { uint32_t regval; @@ -1699,8 +1713,8 @@ static void adc_dmaconvcallback(DMA_HANDLE handle, uint8_t isr, FAR void *arg) * Name: adc_bind * * Description: - * Bind the upper-half driver callbacks to the lower-half implementation. This - * must be called early in order to receive ADC event notifications. + * Bind the upper-half driver callbacks to the lower-half implementation. + * This must be called early in order to receive ADC event notifications. * ****************************************************************************/ @@ -1718,8 +1732,8 @@ static int adc_bind(FAR struct adc_dev_s *dev, * Name: adc_reset * * Description: - * Reset the ADC device. Called early to initialize the hardware. This - * is called, before adc_setup() and on error conditions. + * Reset the ADC device. Called early to initialize the hardware. + * This is called, before adc_setup() and on error conditions. * * Input Parameters: * @@ -1751,7 +1765,7 @@ static void adc_reset(FAR struct adc_dev_s *dev) #endif -#ifdef CONFIG_STM32_STM32F30XX +#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) /* Turn off the ADC so we can write the RCC bits */ @@ -1767,7 +1781,7 @@ static void adc_reset(FAR struct adc_dev_s *dev) adc_rccreset(priv, false); -#ifdef CONFIG_STM32_STM32F30XX +#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) /* Set voltage regular enable to intermediate state */ @@ -1822,7 +1836,7 @@ static void adc_reset(FAR struct adc_dev_s *dev) adc_putreg(priv, STM32_ADC_SMPR2_OFFSET, ADC_SMPR2_DEFAULT); #endif -#ifdef CONFIG_STM32_STM32F30XX +#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) /* Enable the analog watchdog */ @@ -1870,7 +1884,7 @@ static void adc_reset(FAR struct adc_dev_s *dev) adc_modifyreg(priv, STM32_ADC_IER_OFFSET, clrbits, setbits); -#else /* ifdef CONFIG_STM32_STM32F30XX */ +#else /* CONFIG_STM32_STM32F30XX || CONFIG_STM32_STM33XX */ /* Enable the analog watchdog */ @@ -1968,7 +1982,7 @@ static void adc_reset(FAR struct adc_dev_s *dev) /* ADC CCR configuration */ -#if defined(CONFIG_STM32_STM32F30XX) +#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) clrbits = ADC_CCR_DUAL_MASK | ADC_CCR_DELAY_MASK | ADC_CCR_DMACFG | ADC_CCR_MDMA_MASK | ADC_CCR_CKMODE_MASK | ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN; @@ -1979,10 +1993,12 @@ static void adc_reset(FAR struct adc_dev_s *dev) { stm32_modifyreg32(STM32_ADC12_CCR, clrbits, setbits); } +#ifndef CONFIG_STM32_STM32F33XX else { stm32_modifyreg32(STM32_ADC34_CCR, clrbits, setbits); } +#endif #elif defined(CONFIG_STM32_STM32F20XX) || \ defined(CONFIG_STM32_STM32F40XX) || \ defined(CONFIG_STM32_STM32L15XX) @@ -2050,7 +2066,7 @@ static void adc_reset(FAR struct adc_dev_s *dev) leave_critical_section(flags); -#ifdef CONFIG_STM32_STM32F30XX +#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) ainfo("ISR: 0x%08x CR: 0x%08x CFGR: 0x%08x\n", adc_getreg(priv, STM32_ADC_ISR_OFFSET), adc_getreg(priv, STM32_ADC_CR_OFFSET), @@ -2067,7 +2083,7 @@ static void adc_reset(FAR struct adc_dev_s *dev) adc_getreg(priv, STM32_ADC_SQR2_OFFSET), adc_getreg(priv, STM32_ADC_SQR3_OFFSET)); -#if defined(CONFIG_STM32_STM32F30XX) +#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) ainfo("SQR4: 0x%08x\n", adc_getreg(priv, STM32_ADC_SQR4_OFFSET)); #elif defined(CONFIG_STM32_STM32L15XX) ainfo("SQR4: 0x%08x SQR5: 0x%08x\n", @@ -2075,15 +2091,17 @@ static void adc_reset(FAR struct adc_dev_s *dev) adc_getreg(priv, STM32_ADC_SQR5_OFFSET)); #endif -#if defined(CONFIG_STM32_STM32F30XX) +#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) if (priv->base == STM32_ADC1_BASE || priv->base == STM32_ADC2_BASE) { ainfo("CCR: 0x%08x\n", getreg32(STM32_ADC12_CCR)); } +#ifndef CONFIG_STM32_STM32F33XX else { ainfo("CCR: 0x%08x\n", getreg32(STM32_ADC34_CCR)); } +#endif #elif defined(CONFIG_STM32_STM32F20XX) || \ defined(CONFIG_STM32_STM32F40XX) || \ defined(CONFIG_STM32_STM32L15XX) @@ -3085,8 +3103,9 @@ struct adc_dev_s *stm32_adcinitialize(int intf, FAR const uint8_t *chanlist, } #endif /* CONFIG_STM32_STM32F10XX || CONFIG_STM32_STM32F20XX || - * CONFIG_STM32_STM32F30XX || CONFIG_STM32_STM32F47XX || - * CONFIG_STM32_STM32F40XX || CONFIG_STM32_STM32L15XX + * CONFIG_STM32_STM32F30XX || CONFIG_STM32_STM32F33XX || + * CONFIG_STM32_STM32F47XX || CONFIG_STM32_STM32F40XX || + * CONFIG_STM32_STM32L15XX */ #endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || * CONFIG_STM32_ADC3 || CONFIG_STM32_ADC4 From 8491cd65bca944709fd3b6fc85e0927cb579c917 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Sat, 18 Mar 2017 16:39:40 +0100 Subject: [PATCH 32/81] configs/nucleo_f334r8: add ADC example --- configs/nucleo-f334r8/adc/Make.defs | 113 ++ configs/nucleo-f334r8/adc/defconfig | 1239 +++++++++++++++++++++ configs/nucleo-f334r8/adc/setenv.sh | 77 ++ configs/nucleo-f334r8/include/board.h | 4 +- configs/nucleo-f334r8/src/stm32_adc.c | 253 +++++ configs/nucleo-f334r8/src/stm32_appinit.c | 22 +- configs/nucleo-f334r8/src/stm32_boot.c | 3 +- 7 files changed, 1707 insertions(+), 4 deletions(-) create mode 100644 configs/nucleo-f334r8/adc/Make.defs create mode 100644 configs/nucleo-f334r8/adc/defconfig create mode 100644 configs/nucleo-f334r8/adc/setenv.sh diff --git a/configs/nucleo-f334r8/adc/Make.defs b/configs/nucleo-f334r8/adc/Make.defs new file mode 100644 index 00000000000..192071b180f --- /dev/null +++ b/configs/nucleo-f334r8/adc/Make.defs @@ -0,0 +1,113 @@ +############################################################################ +# configs/nucleo-f334r8/adc/Make.defs +# +# Copyright (C) 2017 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +include ${TOPDIR}/.config +include ${TOPDIR}/tools/Config.mk +include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = ld.script + +ifeq ($(WINTOOL),y) + # Windows-native toolchains + DIRLINK = $(TOPDIR)/tools/copydir.sh + DIRUNLINK = $(TOPDIR)/tools/unlink.sh + MKDEP = $(TOPDIR)/tools/mkwindeps.sh + ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" + ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" + ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}" +else + # Linux/Cygwin-native toolchain + MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT) + ARCHINCLUDES = -I. -isystem $(TOPDIR)/include + ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx + ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT) +endif + +CC = $(CROSSDEV)gcc +CXX = $(CROSSDEV)g++ +CPP = $(CROSSDEV)gcc -E +LD = $(CROSSDEV)ld +AR = $(ARCROSSDEV)ar rcs +NM = $(ARCROSSDEV)nm +OBJCOPY = $(CROSSDEV)objcopy +OBJDUMP = $(CROSSDEV)objdump + +ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'} +ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1} + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g +endif + +ifneq ($(CONFIG_DEBUG_NOOPT),y) + ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer +endif + +ARCHCFLAGS = -fno-builtin +ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -fno-rtti +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef +ARCHWARNINGSXX = -Wall -Wshadow -Wundef +ARCHDEFINES = +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) +AFLAGS = $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +ASMEXT = .S +OBJEXT = .o +LIBEXT = .a +EXEEXT = + +ifneq ($(CROSSDEV),arm-nuttx-elf-) + LDFLAGS += -nostartfiles -nodefaultlibs +endif +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + LDFLAGS += -g +endif + + +HOSTCC = gcc +HOSTINCLUDES = -I. +HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe +HOSTLDFLAGS = + diff --git a/configs/nucleo-f334r8/adc/defconfig b/configs/nucleo-f334r8/adc/defconfig new file mode 100644 index 00000000000..9a8481f5162 --- /dev/null +++ b/configs/nucleo-f334r8/adc/defconfig @@ -0,0 +1,1239 @@ +# +# Automatically generated file; DO NOT EDIT. +# Nuttx/ Configuration +# + +# +# Build Setup +# +# CONFIG_EXPERIMENTAL is not set +# CONFIG_DEFAULT_SMALL is not set +CONFIG_HOST_LINUX=y +# CONFIG_HOST_OSX is not set +# CONFIG_HOST_WINDOWS is not set +# CONFIG_HOST_OTHER is not set + +# +# Build Configuration +# +# CONFIG_APPS_DIR="../apps" +CONFIG_BUILD_FLAT=y +# CONFIG_BUILD_2PASS is not set + +# +# Binary Output Formats +# +# CONFIG_RRLOAD_BINARY is not set +CONFIG_INTELHEX_BINARY=y +# CONFIG_MOTOROLA_SREC is not set +CONFIG_RAW_BINARY=y +# CONFIG_UBOOT_UIMAGE is not set + +# +# Customize Header Files +# +# CONFIG_ARCH_STDINT_H is not set +# CONFIG_ARCH_STDBOOL_H is not set +# CONFIG_ARCH_MATH_H is not set +# CONFIG_ARCH_FLOAT_H is not set +# CONFIG_ARCH_STDARG_H is not set +# CONFIG_ARCH_DEBUG_H is not set + +# +# Debug Options +# +CONFIG_DEBUG_ALERT=y +CONFIG_DEBUG_FEATURES=y + +# +# Debug SYSLOG Output Controls +# +CONFIG_DEBUG_ERROR=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_ERROR=y +CONFIG_DEBUG_ASSERTIONS=y + +# +# Subsystem Debug Options +# +# CONFIG_DEBUG_BINFMT is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_DEBUG_GRAPHICS is not set +# CONFIG_DEBUG_LIB is not set +# CONFIG_DEBUG_MM is not set +# CONFIG_DEBUG_SCHED is not set + +# +# OS Function Debug Options +# +# CONFIG_DEBUG_IRQ is not set + +# +# Driver Debug Options +# +# CONFIG_DEBUG_LEDS is not set +# CONFIG_DEBUG_GPIO is not set +# CONFIG_DEBUG_TIMER is not set +CONFIG_ARCH_HAVE_STACKCHECK=y +# CONFIG_STACK_COLORATION is not set +CONFIG_ARCH_HAVE_HEAPCHECK=y +# CONFIG_HEAP_COLORATION is not set +CONFIG_DEBUG_SYMBOLS=y +CONFIG_ARCH_HAVE_CUSTOMOPT=y +# CONFIG_DEBUG_NOOPT is not set +# CONFIG_DEBUG_CUSTOMOPT is not set +CONFIG_DEBUG_FULLOPT=y + +# +# System Type +# +CONFIG_ARCH_ARM=y +# CONFIG_ARCH_AVR is not set +# CONFIG_ARCH_HC is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set +# CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set +# CONFIG_ARCH_SIM is not set +# CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set +# CONFIG_ARCH_Z16 is not set +# CONFIG_ARCH_Z80 is not set +CONFIG_ARCH="arm" + +# +# ARM Options +# +# CONFIG_ARCH_CHIP_A1X is not set +# CONFIG_ARCH_CHIP_C5471 is not set +# CONFIG_ARCH_CHIP_DM320 is not set +# CONFIG_ARCH_CHIP_EFM32 is not set +# CONFIG_ARCH_CHIP_IMX1 is not set +# CONFIG_ARCH_CHIP_IMX6 is not set +# CONFIG_ARCH_CHIP_KINETIS is not set +# CONFIG_ARCH_CHIP_KL is not set +# CONFIG_ARCH_CHIP_LM is not set +# CONFIG_ARCH_CHIP_TIVA is not set +# CONFIG_ARCH_CHIP_LPC11XX is not set +# CONFIG_ARCH_CHIP_LPC17XX is not set +# CONFIG_ARCH_CHIP_LPC214X is not set +# CONFIG_ARCH_CHIP_LPC2378 is not set +# CONFIG_ARCH_CHIP_LPC31XX is not set +# CONFIG_ARCH_CHIP_LPC43XX is not set +# CONFIG_ARCH_CHIP_NUC1XX is not set +# CONFIG_ARCH_CHIP_SAMA5 is not set +# CONFIG_ARCH_CHIP_SAMD is not set +# CONFIG_ARCH_CHIP_SAML is not set +# CONFIG_ARCH_CHIP_SAM34 is not set +# CONFIG_ARCH_CHIP_SAMV7 is not set +CONFIG_ARCH_CHIP_STM32=y +# CONFIG_ARCH_CHIP_STM32F7 is not set +# CONFIG_ARCH_CHIP_STM32L4 is not set +# CONFIG_ARCH_CHIP_STR71X is not set +# CONFIG_ARCH_CHIP_TMS570 is not set +# CONFIG_ARCH_CHIP_MOXART is not set +# CONFIG_ARCH_ARM7TDMI is not set +# CONFIG_ARCH_ARM926EJS is not set +# CONFIG_ARCH_ARM920T is not set +# CONFIG_ARCH_CORTEXM0 is not set +# CONFIG_ARCH_CORTEXM23 is not set +# CONFIG_ARCH_CORTEXM3 is not set +# CONFIG_ARCH_CORTEXM33 is not set +CONFIG_ARCH_CORTEXM4=y +# CONFIG_ARCH_CORTEXM7 is not set +# CONFIG_ARCH_CORTEXA5 is not set +# CONFIG_ARCH_CORTEXA8 is not set +# CONFIG_ARCH_CORTEXA9 is not set +# CONFIG_ARCH_CORTEXR4 is not set +# CONFIG_ARCH_CORTEXR4F is not set +# CONFIG_ARCH_CORTEXR5 is not set +# CONFIG_ARCH_CORTEX5F is not set +# CONFIG_ARCH_CORTEXR7 is not set +# CONFIG_ARCH_CORTEXR7F is not set +CONFIG_ARCH_FAMILY="armv7-m" +CONFIG_ARCH_CHIP="stm32" +# CONFIG_ARM_TOOLCHAIN_IAR is not set +CONFIG_ARM_TOOLCHAIN_GNU=y +# CONFIG_ARMV7M_USEBASEPRI is not set +CONFIG_ARCH_HAVE_CMNVECTOR=y +# CONFIG_ARMV7M_CMNVECTOR is not set +# CONFIG_ARMV7M_LAZYFPU is not set +CONFIG_ARCH_HAVE_FPU=y +# CONFIG_ARCH_HAVE_DPFPU is not set +# CONFIG_ARCH_FPU is not set +# CONFIG_ARCH_HAVE_TRUSTZONE is not set +CONFIG_ARM_HAVE_MPU_UNIFIED=y +# CONFIG_ARM_MPU is not set +# CONFIG_DEBUG_HARDFAULT is not set + +# +# ARMV7M Configuration Options +# +# CONFIG_ARMV7M_HAVE_ICACHE is not set +# CONFIG_ARMV7M_HAVE_DCACHE is not set +# CONFIG_ARMV7M_HAVE_ITCM is not set +# CONFIG_ARMV7M_HAVE_DTCM is not set +# CONFIG_ARMV7M_TOOLCHAIN_IARL is not set +CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y +# CONFIG_ARMV7M_TOOLCHAIN_CODEREDL is not set +# CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL is not set +# CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL is not set +# CONFIG_ARMV7M_OABI_TOOLCHAIN is not set +CONFIG_ARMV7M_HAVE_STACKCHECK=y +# CONFIG_ARMV7M_STACKCHECK is not set +# CONFIG_ARMV7M_ITMSYSLOG is not set +# CONFIG_SERIAL_TERMIOS is not set + +# +# STM32 Configuration Options +# +# CONFIG_ARCH_CHIP_STM32L151C6 is not set +# CONFIG_ARCH_CHIP_STM32L151C8 is not set +# CONFIG_ARCH_CHIP_STM32L151CB is not set +# CONFIG_ARCH_CHIP_STM32L151R6 is not set +# CONFIG_ARCH_CHIP_STM32L151R8 is not set +# CONFIG_ARCH_CHIP_STM32L151RB is not set +# CONFIG_ARCH_CHIP_STM32L151V6 is not set +# CONFIG_ARCH_CHIP_STM32L151V8 is not set +# CONFIG_ARCH_CHIP_STM32L151VB is not set +# CONFIG_ARCH_CHIP_STM32L152C6 is not set +# CONFIG_ARCH_CHIP_STM32L152C8 is not set +# CONFIG_ARCH_CHIP_STM32L152CB is not set +# CONFIG_ARCH_CHIP_STM32L152R6 is not set +# CONFIG_ARCH_CHIP_STM32L152R8 is not set +# CONFIG_ARCH_CHIP_STM32L152RB is not set +# CONFIG_ARCH_CHIP_STM32L152V6 is not set +# CONFIG_ARCH_CHIP_STM32L152V8 is not set +# CONFIG_ARCH_CHIP_STM32L152VB is not set +# CONFIG_ARCH_CHIP_STM32L162ZD is not set +# CONFIG_ARCH_CHIP_STM32L162VE is not set +# CONFIG_ARCH_CHIP_STM32F100C8 is not set +# CONFIG_ARCH_CHIP_STM32F100CB is not set +# CONFIG_ARCH_CHIP_STM32F100R8 is not set +# CONFIG_ARCH_CHIP_STM32F100RB is not set +# CONFIG_ARCH_CHIP_STM32F100RC is not set +# CONFIG_ARCH_CHIP_STM32F100RD is not set +# CONFIG_ARCH_CHIP_STM32F100RE is not set +# CONFIG_ARCH_CHIP_STM32F100V8 is not set +# CONFIG_ARCH_CHIP_STM32F100VB is not set +# CONFIG_ARCH_CHIP_STM32F100VC is not set +# CONFIG_ARCH_CHIP_STM32F100VD is not set +# CONFIG_ARCH_CHIP_STM32F100VE is not set +# CONFIG_ARCH_CHIP_STM32F102CB is not set +# CONFIG_ARCH_CHIP_STM32F103T8 is not set +# CONFIG_ARCH_CHIP_STM32F103TB is not set +# CONFIG_ARCH_CHIP_STM32F103C4 is not set +# CONFIG_ARCH_CHIP_STM32F103C8 is not set +# CONFIG_ARCH_CHIP_STM32F103CB is not set +# CONFIG_ARCH_CHIP_STM32F103R8 is not set +# CONFIG_ARCH_CHIP_STM32F103RB is not set +# CONFIG_ARCH_CHIP_STM32F103RC is not set +# CONFIG_ARCH_CHIP_STM32F103RD is not set +# CONFIG_ARCH_CHIP_STM32F103RE is not set +# CONFIG_ARCH_CHIP_STM32F103RG is not set +# CONFIG_ARCH_CHIP_STM32F103V8 is not set +# CONFIG_ARCH_CHIP_STM32F103VB is not set +# CONFIG_ARCH_CHIP_STM32F103VC is not set +# CONFIG_ARCH_CHIP_STM32F103VE is not set +# CONFIG_ARCH_CHIP_STM32F103ZE is not set +# CONFIG_ARCH_CHIP_STM32F105VB is not set +# CONFIG_ARCH_CHIP_STM32F105RB is not set +# CONFIG_ARCH_CHIP_STM32F107VC is not set +# CONFIG_ARCH_CHIP_STM32F205RG is not set +# CONFIG_ARCH_CHIP_STM32F207IG is not set +# CONFIG_ARCH_CHIP_STM32F207ZE is not set +# CONFIG_ARCH_CHIP_STM32F302K6 is not set +# CONFIG_ARCH_CHIP_STM32F302K8 is not set +# CONFIG_ARCH_CHIP_STM32F302CB is not set +# CONFIG_ARCH_CHIP_STM32F302CC is not set +# CONFIG_ARCH_CHIP_STM32F302RB is not set +# CONFIG_ARCH_CHIP_STM32F302RC is not set +# CONFIG_ARCH_CHIP_STM32F302VB is not set +# CONFIG_ARCH_CHIP_STM32F302VC is not set +# CONFIG_ARCH_CHIP_STM32F303K6 is not set +# CONFIG_ARCH_CHIP_STM32F303K8 is not set +# CONFIG_ARCH_CHIP_STM32F303C6 is not set +# CONFIG_ARCH_CHIP_STM32F303C8 is not set +# CONFIG_ARCH_CHIP_STM32F303CB is not set +# CONFIG_ARCH_CHIP_STM32F303CC is not set +# CONFIG_ARCH_CHIP_STM32F303RB is not set +# CONFIG_ARCH_CHIP_STM32F303RC is not set +# CONFIG_ARCH_CHIP_STM32F303RD is not set +# CONFIG_ARCH_CHIP_STM32F303RE is not set +# CONFIG_ARCH_CHIP_STM32F303VB is not set +# CONFIG_ARCH_CHIP_STM32F303VC is not set +# CONFIG_ARCH_CHIP_STM32F334K4 is not set +# CONFIG_ARCH_CHIP_STM32F334K6 is not set +# CONFIG_ARCH_CHIP_STM32F334K8 is not set +# CONFIG_ARCH_CHIP_STM32F334C4 is not set +# CONFIG_ARCH_CHIP_STM32F334C6 is not set +# CONFIG_ARCH_CHIP_STM32F334C8 is not set +# CONFIG_ARCH_CHIP_STM32F334R4 is not set +# CONFIG_ARCH_CHIP_STM32F334R6 is not set +CONFIG_ARCH_CHIP_STM32F334R8=y +# CONFIG_ARCH_CHIP_STM32F372C8 is not set +# CONFIG_ARCH_CHIP_STM32F372R8 is not set +# CONFIG_ARCH_CHIP_STM32F372V8 is not set +# CONFIG_ARCH_CHIP_STM32F372CB is not set +# CONFIG_ARCH_CHIP_STM32F372RB is not set +# CONFIG_ARCH_CHIP_STM32F372VB is not set +# CONFIG_ARCH_CHIP_STM32F372CC is not set +# CONFIG_ARCH_CHIP_STM32F372RC is not set +# CONFIG_ARCH_CHIP_STM32F372VC is not set +# CONFIG_ARCH_CHIP_STM32F373C8 is not set +# CONFIG_ARCH_CHIP_STM32F373R8 is not set +# CONFIG_ARCH_CHIP_STM32F373V8 is not set +# CONFIG_ARCH_CHIP_STM32F373CB is not set +# CONFIG_ARCH_CHIP_STM32F373RB is not set +# CONFIG_ARCH_CHIP_STM32F373VB is not set +# CONFIG_ARCH_CHIP_STM32F373CC is not set +# CONFIG_ARCH_CHIP_STM32F373RC is not set +# CONFIG_ARCH_CHIP_STM32F373VC is not set +# CONFIG_ARCH_CHIP_STM32F401RE is not set +# CONFIG_ARCH_CHIP_STM32F411RE is not set +# CONFIG_ARCH_CHIP_STM32F411VE is not set +# CONFIG_ARCH_CHIP_STM32F405RG is not set +# CONFIG_ARCH_CHIP_STM32F405VG is not set +# CONFIG_ARCH_CHIP_STM32F405ZG is not set +# CONFIG_ARCH_CHIP_STM32F407VE is not set +# CONFIG_ARCH_CHIP_STM32F407VG is not set +# CONFIG_ARCH_CHIP_STM32F407ZE is not set +# CONFIG_ARCH_CHIP_STM32F407ZG is not set +# CONFIG_ARCH_CHIP_STM32F407IE is not set +# CONFIG_ARCH_CHIP_STM32F407IG is not set +# CONFIG_ARCH_CHIP_STM32F427V is not set +# CONFIG_ARCH_CHIP_STM32F427Z is not set +# CONFIG_ARCH_CHIP_STM32F427I is not set +# CONFIG_ARCH_CHIP_STM32F429V is not set +# CONFIG_ARCH_CHIP_STM32F429Z is not set +# CONFIG_ARCH_CHIP_STM32F429I is not set +# CONFIG_ARCH_CHIP_STM32F429B is not set +# CONFIG_ARCH_CHIP_STM32F429N is not set +# CONFIG_ARCH_CHIP_STM32F446M is not set +# CONFIG_ARCH_CHIP_STM32F446R is not set +# CONFIG_ARCH_CHIP_STM32F446V is not set +# CONFIG_ARCH_CHIP_STM32F446Z is not set +# CONFIG_ARCH_CHIP_STM32F469A is not set +# CONFIG_ARCH_CHIP_STM32F469I is not set +# CONFIG_ARCH_CHIP_STM32F469B is not set +# CONFIG_ARCH_CHIP_STM32F469N is not set +CONFIG_STM32_FLASH_CONFIG_DEFAULT=y +# CONFIG_STM32_FLASH_CONFIG_4 is not set +# CONFIG_STM32_FLASH_CONFIG_6 is not set +# CONFIG_STM32_FLASH_CONFIG_8 is not set +# CONFIG_STM32_FLASH_CONFIG_B is not set +# CONFIG_STM32_FLASH_CONFIG_C is not set +# CONFIG_STM32_FLASH_CONFIG_D is not set +# CONFIG_STM32_FLASH_CONFIG_E is not set +# CONFIG_STM32_FLASH_CONFIG_F is not set +# CONFIG_STM32_FLASH_CONFIG_G is not set +# CONFIG_STM32_FLASH_CONFIG_I is not set +# CONFIG_STM32_STM32L15XX is not set +# CONFIG_STM32_ENERGYLITE is not set +# CONFIG_STM32_STM32F10XX is not set +# CONFIG_STM32_VALUELINE is not set +# CONFIG_STM32_CONNECTIVITYLINE is not set +# CONFIG_STM32_PERFORMANCELINE is not set +# CONFIG_STM32_USBACCESSLINE is not set +# CONFIG_STM32_HIGHDENSITY is not set +# CONFIG_STM32_MEDIUMDENSITY is not set +# CONFIG_STM32_LOWDENSITY is not set +# CONFIG_STM32_STM32F20XX is not set +# CONFIG_STM32_STM32F205 is not set +# CONFIG_STM32_STM32F207 is not set +# CONFIG_STM32_STM32F30XX is not set +# CONFIG_STM32_STM32F302 is not set +# CONFIG_STM32_STM32F303 is not set +CONFIG_STM32_STM32F33XX=y +# CONFIG_STM32_STM32F37XX is not set +# CONFIG_STM32_STM32F40XX is not set +# CONFIG_STM32_STM32F401 is not set +# CONFIG_STM32_STM32F411 is not set +# CONFIG_STM32_STM32F405 is not set +# CONFIG_STM32_STM32F407 is not set +# CONFIG_STM32_STM32F427 is not set +# CONFIG_STM32_STM32F429 is not set +# CONFIG_STM32_STM32F446 is not set +# CONFIG_STM32_STM32F469 is not set +# CONFIG_STM32_DFU is not set + +# +# STM32 Peripheral Support +# +CONFIG_STM32_HAVE_CCM=y +# CONFIG_STM32_HAVE_USBDEV is not set +# CONFIG_STM32_HAVE_OTGFS is not set +# CONFIG_STM32_HAVE_FSMC is not set +CONFIG_STM32_HAVE_HRTIM1=y +# CONFIG_STM32_HAVE_LTDC is not set +CONFIG_STM32_HAVE_USART3=y +# CONFIG_STM32_HAVE_UART4 is not set +# CONFIG_STM32_HAVE_UART5 is not set +# CONFIG_STM32_HAVE_USART6 is not set +# CONFIG_STM32_HAVE_UART7 is not set +# CONFIG_STM32_HAVE_UART8 is not set +CONFIG_STM32_HAVE_TIM1=y +# CONFIG_STM32_HAVE_TIM2 is not set +# CONFIG_STM32_HAVE_TIM3 is not set +# CONFIG_STM32_HAVE_TIM4 is not set +# CONFIG_STM32_HAVE_TIM5 is not set +# CONFIG_STM32_HAVE_TIM6 is not set +# CONFIG_STM32_HAVE_TIM7 is not set +# CONFIG_STM32_HAVE_TIM8 is not set +# CONFIG_STM32_HAVE_TIM9 is not set +# CONFIG_STM32_HAVE_TIM10 is not set +# CONFIG_STM32_HAVE_TIM11 is not set +# CONFIG_STM32_HAVE_TIM12 is not set +# CONFIG_STM32_HAVE_TIM13 is not set +# CONFIG_STM32_HAVE_TIM14 is not set +CONFIG_STM32_HAVE_TIM15=y +CONFIG_STM32_HAVE_TIM16=y +CONFIG_STM32_HAVE_TIM17=y +CONFIG_STM32_HAVE_ADC2=y +# CONFIG_STM32_HAVE_ADC3 is not set +# CONFIG_STM32_HAVE_ADC4 is not set +CONFIG_STM32_HAVE_ADC1_DMA=y +# CONFIG_STM32_HAVE_ADC2_DMA is not set +# CONFIG_STM32_HAVE_ADC3_DMA is not set +# CONFIG_STM32_HAVE_ADC4_DMA is not set +# CONFIG_STM32_HAVE_SDADC1 is not set +# CONFIG_STM32_HAVE_SDADC2 is not set +# CONFIG_STM32_HAVE_SDADC3 is not set +# CONFIG_STM32_HAVE_SDADC1_DMA is not set +# CONFIG_STM32_HAVE_SDADC2_DMA is not set +# CONFIG_STM32_HAVE_SDADC3_DMA is not set +CONFIG_STM32_HAVE_CAN1=y +# CONFIG_STM32_HAVE_CAN2 is not set +CONFIG_STM32_HAVE_COMP2=y +CONFIG_STM32_HAVE_COMP4=y +CONFIG_STM32_HAVE_COMP6=y +CONFIG_STM32_HAVE_DAC1=y +CONFIG_STM32_HAVE_DAC2=y +# CONFIG_STM32_HAVE_RNG is not set +# CONFIG_STM32_HAVE_ETHMAC is not set +# CONFIG_STM32_HAVE_I2C2 is not set +# CONFIG_STM32_HAVE_I2C3 is not set +# CONFIG_STM32_HAVE_SPI2 is not set +# CONFIG_STM32_HAVE_SPI3 is not set +# CONFIG_STM32_HAVE_SPI4 is not set +# CONFIG_STM32_HAVE_SPI5 is not set +# CONFIG_STM32_HAVE_SPI6 is not set +# CONFIG_STM32_HAVE_SAIPLL is not set +# CONFIG_STM32_HAVE_I2SPLL is not set +CONFIG_STM32_HAVE_OPAMP=y +CONFIG_STM32_ADC1=y +# CONFIG_STM32_ADC2 is not set +# CONFIG_STM32_COMP2 is not set +# CONFIG_STM32_COMP4 is not set +# CONFIG_STM32_COMP6 is not set +# CONFIG_STM32_CAN1 is not set +# CONFIG_STM32_CRC is not set +CONFIG_STM32_DMA1=y +# CONFIG_STM32_DMA2 is not set +# CONFIG_STM32_DAC1 is not set +# CONFIG_STM32_DAC2 is not set +# CONFIG_STM32_HRTIM1 is not set +# CONFIG_STM32_I2C1 is not set +# CONFIG_STM32_OPAMP is not set +CONFIG_STM32_PWR=y +# CONFIG_STM32_SDIO is not set +# CONFIG_STM32_SPI1 is not set +# CONFIG_STM32_TIM1 is not set +# CONFIG_STM32_TIM2 is not set +# CONFIG_STM32_TIM15 is not set +# CONFIG_STM32_TIM16 is not set +# CONFIG_STM32_TIM17 is not set +CONFIG_STM32_USART1=y +# CONFIG_STM32_USART2 is not set +# CONFIG_STM32_USART3 is not set +# CONFIG_STM32_IWDG is not set +# CONFIG_STM32_WWDG is not set +CONFIG_STM32_ADC=y +# CONFIG_STM32_NOEXT_VECTORS is not set + +# +# Alternate Pin Mapping +# +# CONFIG_STM32_JTAG_DISABLE is not set +# CONFIG_STM32_JTAG_FULL_ENABLE is not set +# CONFIG_STM32_JTAG_NOJNTRST_ENABLE is not set +CONFIG_STM32_JTAG_SW_ENABLE=y +# CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG is not set +# CONFIG_STM32_FORCEPOWER is not set +# CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is not set +CONFIG_STM32_CCMEXCLUDE=y + +# +# Timer Configuration +# +# CONFIG_STM32_ONESHOT is not set +# CONFIG_STM32_FREERUN is not set +# CONFIG_STM32_TIM1_CAP is not set +CONFIG_STM32_USART=y +CONFIG_STM32_SERIALDRIVER=y + +# +# ADC Configuration +# +CONFIG_STM32_ADC1_DMA=y +# CONFIG_STM32_HAVE_RTC_COUNTER is not set +# CONFIG_STM32_HAVE_RTC_SUBSECONDS is not set + +# +# U[S]ART Configuration +# + +# +# U[S]ART Device Configuration +# +CONFIG_STM32_USART1_SERIALDRIVER=y +# CONFIG_STM32_USART1_1WIREDRIVER is not set +# CONFIG_USART1_RS485 is not set + +# +# Serial Driver Configuration +# +# CONFIG_SERIAL_DISABLE_REORDERING is not set +# CONFIG_STM32_FLOWCONTROL_BROKEN is not set +# CONFIG_STM32_USART_BREAKS is not set +# CONFIG_STM32_USART_SINGLEWIRE is not set +# CONFIG_STM32_HAVE_RTC_COUNTER is not set +# CONFIG_STM32_HAVE_RTC_SUBSECONDS is not set + +# +# USB FS Host Configuration +# + +# +# USB HS Host Configuration +# + +# +# USB Host Debug Configuration +# + +# +# USB Device Configuration +# + +# +# Architecture Options +# +# CONFIG_ARCH_NOINTC is not set +# CONFIG_ARCH_VECNOTIRQ is not set +CONFIG_ARCH_DMA=y +CONFIG_ARCH_HAVE_IRQPRIO=y +# CONFIG_ARCH_L2CACHE is not set +# CONFIG_ARCH_HAVE_COHERENT_DCACHE is not set +# CONFIG_ARCH_HAVE_ADDRENV is not set +# CONFIG_ARCH_NEED_ADDRENV_MAPPING is not set +# CONFIG_ARCH_HAVE_MULTICPU is not set +CONFIG_ARCH_HAVE_VFORK=y +# CONFIG_ARCH_HAVE_MMU is not set +CONFIG_ARCH_HAVE_MPU=y +# CONFIG_ARCH_NAND_HWECC is not set +# CONFIG_ARCH_HAVE_EXTCLK is not set +# CONFIG_ARCH_HAVE_POWEROFF is not set +CONFIG_ARCH_HAVE_RESET=y +# CONFIG_ARCH_USE_MPU is not set +# CONFIG_ARCH_IRQPRIO is not set +CONFIG_ARCH_STACKDUMP=y +# CONFIG_ENDIAN_BIG is not set +# CONFIG_ARCH_IDLE_CUSTOM is not set +# CONFIG_ARCH_HAVE_RAMFUNCS is not set +CONFIG_ARCH_HAVE_RAMVECTORS=y +# CONFIG_ARCH_RAMVECTORS is not set +# CONFIG_ARCH_MINIMAL_VECTORTABLE is not set + +# +# Board Settings +# +CONFIG_BOARD_LOOPSPERMSEC=16717 +# CONFIG_ARCH_CALIBRATION is not set + +# +# Interrupt options +# +CONFIG_ARCH_HAVE_INTERRUPTSTACK=y +CONFIG_ARCH_INTERRUPTSTACK=0 +CONFIG_ARCH_HAVE_HIPRI_INTERRUPT=y +# CONFIG_ARCH_HIPRI_INTERRUPT is not set + +# +# Boot options +# +# CONFIG_BOOT_RUNFROMEXTSRAM is not set +CONFIG_BOOT_RUNFROMFLASH=y +# CONFIG_BOOT_RUNFROMISRAM is not set +# CONFIG_BOOT_RUNFROMSDRAM is not set +# CONFIG_BOOT_COPYTORAM is not set + +# +# Boot Memory Configuration +# +CONFIG_RAM_START=0x20000000 +CONFIG_RAM_SIZE=12288 +# CONFIG_ARCH_HAVE_SDRAM is not set + +# +# Board Selection +# +CONFIG_ARCH_BOARD_NUCLEO_F334R8=y +# CONFIG_ARCH_BOARD_CUSTOM is not set +CONFIG_ARCH_BOARD="nucleo-f334r8" + +# +# Common Board Options +# +CONFIG_ARCH_HAVE_LEDS=y +CONFIG_ARCH_LEDS=y +CONFIG_ARCH_HAVE_BUTTONS=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_HAVE_IRQBUTTONS=y +# CONFIG_ARCH_IRQBUTTONS is not set + +# +# Board-Specific Options +# +# CONFIG_BOARD_CRASHDUMP is not set +CONFIG_LIB_BOARDCTL=y +# CONFIG_BOARDCTL_RESET is not set +# CONFIG_BOARDCTL_UNIQUEID is not set +# CONFIG_BOARDCTL_TSCTEST is not set +# CONFIG_BOARDCTL_GRAPHICS is not set +# CONFIG_BOARDCTL_IOCTL is not set + +# +# RTOS Features +# +CONFIG_DISABLE_OS_API=y +CONFIG_DISABLE_POSIX_TIMERS=y +CONFIG_DISABLE_PTHREAD=y +CONFIG_DISABLE_SIGNALS=y +CONFIG_DISABLE_MQUEUE=y +CONFIG_DISABLE_ENVIRON=y + +# +# Clocks and Timers +# +CONFIG_ARCH_HAVE_TICKLESS=y +# CONFIG_SCHED_TICKLESS is not set +CONFIG_USEC_PER_TICK=10000 +# CONFIG_SYSTEM_TIME64 is not set +# CONFIG_CLOCK_MONOTONIC is not set +CONFIG_ARCH_HAVE_TIMEKEEPING=y +# CONFIG_JULIAN_TIME is not set +CONFIG_START_YEAR=2011 +CONFIG_START_MONTH=12 +CONFIG_START_DAY=6 +CONFIG_MAX_WDOGPARMS=1 +CONFIG_PREALLOC_WDOGS=1 +CONFIG_WDOG_INTRESERVE=0 +CONFIG_PREALLOC_TIMERS=2 + +# +# Tasks and Scheduling +# +# CONFIG_SPINLOCK is not set +# CONFIG_INIT_NONE is not set +CONFIG_INIT_ENTRYPOINT=y +# CONFIG_INIT_FILEPATH is not set +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_RR_INTERVAL=200 +# CONFIG_SCHED_SPORADIC is not set +CONFIG_TASK_NAME_SIZE=0 +CONFIG_MAX_TASKS=4 +# CONFIG_SCHED_HAVE_PARENT is not set +CONFIG_SCHED_WAITPID=y +# CONFIG_CANCELLATION_POINTS is not set + +# +# Performance Monitoring +# +# CONFIG_SCHED_CPULOAD is not set +# CONFIG_SCHED_INSTRUMENTATION is not set + +# +# Files and I/O +# +CONFIG_DEV_CONSOLE=y +# CONFIG_FDCLONE_DISABLE is not set +CONFIG_FDCLONE_STDIO=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NAME_MAX=16 +# CONFIG_PRIORITY_INHERITANCE is not set + +# +# RTOS hooks +# +# CONFIG_BOARD_INITIALIZE is not set +# CONFIG_SCHED_STARTHOOK is not set +# CONFIG_SCHED_ATEXIT is not set +# CONFIG_SCHED_ONEXIT is not set +# CONFIG_MODULE is not set + +# +# Work queue support +# + +# +# Stack and heap information +# +CONFIG_IDLETHREAD_STACKSIZE=1024 +CONFIG_USERMAIN_STACKSIZE=1024 +CONFIG_PTHREAD_STACK_MIN=1024 +CONFIG_PTHREAD_STACK_DEFAULT=1024 +# CONFIG_LIB_SYSCALL is not set + +# +# Device Drivers +# +CONFIG_DISABLE_POLL=y +# CONFIG_DEV_NULL is not set +# CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set +# CONFIG_DEV_LOOP is not set + +# +# Buffering +# +# CONFIG_DRVR_WRITEBUFFER is not set +# CONFIG_DRVR_READAHEAD is not set +# CONFIG_RAMDISK is not set +# CONFIG_CAN is not set +# CONFIG_ARCH_HAVE_PWM_PULSECOUNT is not set +# CONFIG_ARCH_HAVE_PWM_MULTICHAN is not set +# CONFIG_PWM is not set +CONFIG_ARCH_HAVE_I2CRESET=y +# CONFIG_I2C is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +CONFIG_ARCH_HAVE_SPI_BITORDER=y +# CONFIG_SPI is not set +# CONFIG_I2S is not set + +# +# Timer Driver Support +# +# CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set +# CONFIG_RTC is not set +# CONFIG_WATCHDOG is not set +CONFIG_ANALOG=y +CONFIG_ADC=y +CONFIG_ADC_FIFOSIZE=8 +# CONFIG_AUDIO_DEVICES is not set +# CONFIG_VIDEO_DEVICES is not set +# CONFIG_BCH is not set +# CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# +# CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set + +# +# LCD Driver Support +# +# CONFIG_LCD is not set +# CONFIG_SLCD is not set + +# +# LED Support +# +# CONFIG_USERLED is not set +# CONFIG_RGBLED is not set +# CONFIG_PCA9635PW is not set +# CONFIG_NCP5623C is not set +# CONFIG_MMCSD is not set +# CONFIG_MODEM is not set +# CONFIG_MTD is not set +# CONFIG_EEPROM is not set +# CONFIG_PIPES is not set +# CONFIG_PM is not set +# CONFIG_POWER is not set +# CONFIG_SENSORS is not set +CONFIG_SERIAL=y +# CONFIG_DEV_LOWCONSOLE is not set +# CONFIG_SERIAL_REMOVABLE is not set +CONFIG_SERIAL_CONSOLE=y +# CONFIG_16550_UART is not set +# CONFIG_UART_SERIALDRIVER is not set +# CONFIG_UART0_SERIALDRIVER is not set +# CONFIG_UART1_SERIALDRIVER is not set +# CONFIG_UART2_SERIALDRIVER is not set +# CONFIG_UART3_SERIALDRIVER is not set +# CONFIG_UART4_SERIALDRIVER is not set +# CONFIG_UART5_SERIALDRIVER is not set +# CONFIG_UART6_SERIALDRIVER is not set +# CONFIG_UART7_SERIALDRIVER is not set +# CONFIG_UART8_SERIALDRIVER is not set +# CONFIG_SCI0_SERIALDRIVER is not set +# CONFIG_SCI1_SERIALDRIVER is not set +# CONFIG_USART0_SERIALDRIVER is not set +CONFIG_USART1_SERIALDRIVER=y +# CONFIG_USART2_SERIALDRIVER is not set +# CONFIG_USART3_SERIALDRIVER is not set +# CONFIG_USART4_SERIALDRIVER is not set +# CONFIG_USART5_SERIALDRIVER is not set +# CONFIG_USART6_SERIALDRIVER is not set +# CONFIG_USART7_SERIALDRIVER is not set +# CONFIG_USART8_SERIALDRIVER is not set +# CONFIG_OTHER_UART_SERIALDRIVER is not set +CONFIG_MCU_SERIAL=y +CONFIG_STANDARD_SERIAL=y +# CONFIG_SERIAL_IFLOWCONTROL is not set +# CONFIG_SERIAL_OFLOWCONTROL is not set +# CONFIG_SERIAL_DMA is not set +# CONFIG_SERIAL_TIOCSERGSTRUCT is not set +CONFIG_ARCH_HAVE_SERIAL_TERMIOS=y +CONFIG_USART1_SERIAL_CONSOLE=y +# CONFIG_OTHER_SERIAL_CONSOLE is not set +# CONFIG_NO_SERIAL_CONSOLE is not set + +# +# USART1 Configuration +# +CONFIG_USART1_RXBUFSIZE=256 +CONFIG_USART1_TXBUFSIZE=256 +CONFIG_USART1_BAUD=115200 +CONFIG_USART1_BITS=8 +CONFIG_USART1_PARITY=0 +CONFIG_USART1_2STOP=0 +# CONFIG_USART1_IFLOWCONTROL is not set +# CONFIG_USART1_OFLOWCONTROL is not set +# CONFIG_USART1_DMA is not set +# CONFIG_PSEUDOTERM is not set +# CONFIG_USBDEV is not set +# CONFIG_USBHOST is not set +# CONFIG_HAVE_USBTRACE is not set +# CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set + +# +# System Logging +# +# CONFIG_ARCH_SYSLOG is not set +# CONFIG_RAMLOG is not set +# CONFIG_SYSLOG_INTBUFFER is not set +# CONFIG_SYSLOG_TIMESTAMP is not set +CONFIG_SYSLOG_SERIAL_CONSOLE=y +# CONFIG_SYSLOG_CHAR is not set +# CONFIG_SYSLOG_CONSOLE is not set +# CONFIG_SYSLOG_NONE is not set +# CONFIG_SYSLOG_FILE is not set +# CONFIG_CONSOLE_SYSLOG is not set +# CONFIG_SYSLOG_CHARDEV is not set + +# +# Networking Support +# +# CONFIG_ARCH_HAVE_NET is not set +# CONFIG_ARCH_HAVE_PHY is not set +# CONFIG_NET is not set + +# +# Crypto API +# +# CONFIG_CRYPTO is not set + +# +# File Systems +# + +# +# File system configuration +# +# CONFIG_DISABLE_MOUNTPOINT is not set +# CONFIG_FS_AUTOMOUNTER is not set +# CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set +# CONFIG_PSEUDOFS_SOFTLINKS is not set +# CONFIG_FS_READABLE is not set +# CONFIG_FS_WRITABLE is not set +# CONFIG_FS_NAMED_SEMAPHORES is not set +# CONFIG_FS_RAMMAP is not set +# CONFIG_FS_FAT is not set +# CONFIG_FS_NXFFS is not set +# CONFIG_FS_ROMFS is not set +# CONFIG_FS_TMPFS is not set +# CONFIG_FS_SMARTFS is not set +# CONFIG_FS_BINFS is not set +# CONFIG_FS_PROCFS is not set +# CONFIG_FS_UNIONFS is not set + +# +# Graphics Support +# +# CONFIG_NX is not set + +# +# Memory Management +# +# CONFIG_MM_SMALL is not set +CONFIG_MM_REGIONS=1 +# CONFIG_ARCH_HAVE_HEAP2 is not set +# CONFIG_GRAN is not set + +# +# Audio Support +# +# CONFIG_AUDIO is not set + +# +# Wireless Support +# + +# +# Binary Loader +# +# CONFIG_BINFMT_DISABLE is not set +# CONFIG_NXFLAT is not set +# CONFIG_ELF is not set +CONFIG_BUILTIN=y +# CONFIG_PIC is not set +# CONFIG_SYMTAB_ORDEREDBYNAME is not set + +# +# Library Routines +# + +# +# Standard C Library Options +# + +# +# Standard C I/O +# +# CONFIG_STDIO_DISABLE_BUFFERING is not set +CONFIG_STDIO_BUFFER_SIZE=64 +CONFIG_STDIO_LINEBUFFER=y +CONFIG_NUNGET_CHARS=2 +# CONFIG_NOPRINTF_FIELDWIDTH is not set +# CONFIG_LIBC_FLOATINGPOINT is not set +# CONFIG_LIBC_LONG_LONG is not set +# CONFIG_LIBC_SCANSET is not set +# CONFIG_EOL_IS_CR is not set +# CONFIG_EOL_IS_LF is not set +# CONFIG_EOL_IS_BOTH_CRLF is not set +CONFIG_EOL_IS_EITHER_CRLF=y +# CONFIG_MEMCPY_VIK is not set +# CONFIG_LIBM is not set + +# +# Architecture-Specific Support +# +CONFIG_ARCH_LOWPUTC=y +# CONFIG_ARCH_ROMGETC is not set +# CONFIG_LIBC_ARCH_MEMCPY is not set +# CONFIG_LIBC_ARCH_MEMCMP is not set +# CONFIG_LIBC_ARCH_MEMMOVE is not set +# CONFIG_LIBC_ARCH_MEMSET is not set +# CONFIG_LIBC_ARCH_STRCHR is not set +# CONFIG_LIBC_ARCH_STRCMP is not set +# CONFIG_LIBC_ARCH_STRCPY is not set +# CONFIG_LIBC_ARCH_STRNCPY is not set +# CONFIG_LIBC_ARCH_STRLEN is not set +# CONFIG_LIBC_ARCH_STRNLEN is not set +# CONFIG_LIBC_ARCH_ELF is not set +# CONFIG_ARMV7M_MEMCPY is not set + +# +# stdlib Options +# +CONFIG_LIB_RAND_ORDER=1 + +# +# Program Execution Options +# +# CONFIG_LIBC_EXECFUNCS is not set +CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=512 +CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=512 + +# +# errno Decode Support +# +# CONFIG_LIBC_STRERROR is not set +# CONFIG_LIBC_PERROR_STDOUT is not set + +# +# memcpy/memset Options +# +# CONFIG_MEMSET_OPTSPEED is not set +# CONFIG_LIBC_DLLFCN is not set +# CONFIG_LIBC_MODLIB is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set + +# +# Time/Time Zone Support +# +# CONFIG_TIME_EXTENDED is not set +CONFIG_ARCH_HAVE_TLS=y + +# +# Thread Local Storage (TLS) +# +# CONFIG_TLS is not set + +# +# Network-Related Options +# +# CONFIG_LIBC_IPv4_ADDRCONV is not set +# CONFIG_LIBC_IPv6_ADDRCONV is not set +# CONFIG_LIBC_NETDB is not set + +# +# NETDB Support +# +# CONFIG_LIBC_IOCTL_VARIADIC is not set +CONFIG_LIB_SENDFILE_BUFSIZE=512 + +# +# Non-standard Library Support +# +# CONFIG_LIB_CRC64_FAST is not set +# CONFIG_LIB_KBDCODEC is not set +# CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set + +# +# Basic CXX Support +# +# CONFIG_C99_BOOL8 is not set +# CONFIG_HAVE_CXX is not set + +# +# Application Configuration +# + +# +# Built-In Applications +# +CONFIG_BUILTIN_PROXY_STACKSIZE=512 + +# +# CAN Utilities +# + +# +# Examples +# +CONFIG_EXAMPLES_ADC=y +CONFIG_EXAMPLES_ADC_DEVPATH="/dev/adc0" +CONFIG_EXAMPLES_ADC_NSAMPLES=0 +CONFIG_EXAMPLES_ADC_GROUPSIZE=4 +CONFIG_EXAMPLES_ADC_SWTRIG=y +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set +# CONFIG_EXAMPLES_CHAT is not set +# CONFIG_EXAMPLES_CONFIGDATA is not set +# CONFIG_EXAMPLES_DHCPD is not set +# CONFIG_EXAMPLES_ELF is not set +# CONFIG_EXAMPLES_FTPC is not set +# CONFIG_EXAMPLES_FTPD is not set +# CONFIG_EXAMPLES_HELLO is not set +# CONFIG_EXAMPLES_HIDKBD is not set +# CONFIG_EXAMPLES_IGMP is not set +# CONFIG_EXAMPLES_JSON is not set +# CONFIG_EXAMPLES_KEYPADTEST is not set +# CONFIG_EXAMPLES_MEDIA is not set +# CONFIG_EXAMPLES_MM is not set +# CONFIG_EXAMPLES_MODBUS is not set +# CONFIG_EXAMPLES_MOUNT is not set +# CONFIG_EXAMPLES_NRF24L01TERM is not set +CONFIG_EXAMPLES_NSH=y +# CONFIG_EXAMPLES_NULL is not set +# CONFIG_EXAMPLES_NX is not set +# CONFIG_EXAMPLES_NXFFS is not set +# CONFIG_EXAMPLES_NXHELLO is not set +# CONFIG_EXAMPLES_NXIMAGE is not set +# CONFIG_EXAMPLES_NXLINES is not set +# CONFIG_EXAMPLES_NXTERM is not set +# CONFIG_EXAMPLES_NXTEXT is not set +# CONFIG_EXAMPLES_PCA9635 is not set +# CONFIG_EXAMPLES_POSIXSPAWN is not set +# CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set +# CONFIG_EXAMPLES_RGBLED is not set +# CONFIG_EXAMPLES_SENDMAIL is not set +# CONFIG_EXAMPLES_SERIALBLASTER is not set +# CONFIG_EXAMPLES_SERIALRX is not set +# CONFIG_EXAMPLES_SERLOOP is not set +# CONFIG_EXAMPLES_SLCD is not set +# CONFIG_EXAMPLES_SMART is not set +# CONFIG_EXAMPLES_SMART_TEST is not set +# CONFIG_EXAMPLES_SMP is not set +# CONFIG_EXAMPLES_STAT is not set +# CONFIG_EXAMPLES_TCPECHO is not set +# CONFIG_EXAMPLES_TELNETD is not set +# CONFIG_EXAMPLES_TIFF is not set +# CONFIG_EXAMPLES_TOUCHSCREEN is not set +# CONFIG_EXAMPLES_WATCHDOG is not set +# CONFIG_EXAMPLES_WEBSERVER is not set + +# +# File System Utilities +# +# CONFIG_FSUTILS_INIFILE is not set + +# +# GPS Utilities +# +# CONFIG_GPSUTILS_MINMEA_LIB is not set + +# +# Graphics Support +# +# CONFIG_TIFF is not set +# CONFIG_GRAPHICS_TRAVELER is not set + +# +# Interpreters +# +# CONFIG_INTERPRETERS_FICL is not set +# CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set +# CONFIG_INTERPRETERS_PCODE is not set + +# +# FreeModBus +# +# CONFIG_MODBUS is not set + +# +# Network Utilities +# +# CONFIG_NETUTILS_CODECS is not set +# CONFIG_NETUTILS_ESP8266 is not set +# CONFIG_NETUTILS_FTPC is not set +# CONFIG_NETUTILS_JSON is not set +# CONFIG_NETUTILS_SMTP is not set + +# +# NSH Library +# +CONFIG_NSH_LIBRARY=y +CONFIG_NSH_ARCHINIT=y + +# +# Command Line Configuration +# +CONFIG_NSH_READLINE=y +# CONFIG_NSH_CLE is not set +CONFIG_NSH_LINELEN=64 +# CONFIG_NSH_DISABLE_SEMICOLON is not set +CONFIG_NSH_CMDPARMS=y +CONFIG_NSH_MAXARGUMENTS=6 +CONFIG_NSH_ARGCAT=y +CONFIG_NSH_NESTDEPTH=3 +# CONFIG_NSH_DISABLEBG is not set +CONFIG_NSH_BUILTIN_APPS=y + +# +# Disable Individual commands +# +CONFIG_NSH_DISABLE_ADDROUTE=y +CONFIG_NSH_DISABLE_BASENAME=y +CONFIG_NSH_DISABLE_CAT=y +CONFIG_NSH_DISABLE_CD=y +CONFIG_NSH_DISABLE_CP=y +CONFIG_NSH_DISABLE_CMP=y +CONFIG_NSH_DISABLE_DATE=y +CONFIG_NSH_DISABLE_DD=y +CONFIG_NSH_DISABLE_DF=y +CONFIG_NSH_DISABLE_DELROUTE=y +CONFIG_NSH_DISABLE_DIRNAME=y +# CONFIG_NSH_DISABLE_ECHO is not set +CONFIG_NSH_DISABLE_EXEC=y +CONFIG_NSH_DISABLE_EXIT=y +# CONFIG_NSH_DISABLE_FREE is not set +CONFIG_NSH_DISABLE_GET=y +# CONFIG_NSH_DISABLE_HELP is not set +CONFIG_NSH_DISABLE_HEXDUMP=y +CONFIG_NSH_DISABLE_IFCONFIG=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +CONFIG_NSH_DISABLE_KILL=y +CONFIG_NSH_DISABLE_LOSETUP=y +CONFIG_NSH_DISABLE_LOSMART=y +CONFIG_NSH_DISABLE_LS=y +CONFIG_NSH_DISABLE_MB=y +CONFIG_NSH_DISABLE_MKDIR=y +CONFIG_NSH_DISABLE_MKRD=y +CONFIG_NSH_DISABLE_MH=y +CONFIG_NSH_DISABLE_MOUNT=y +CONFIG_NSH_DISABLE_MV=y +CONFIG_NSH_DISABLE_MW=y +# CONFIG_NSH_DISABLE_PRINTF is not set +CONFIG_NSH_DISABLE_PS=y +CONFIG_NSH_DISABLE_PUT=y +CONFIG_NSH_DISABLE_PWD=y +CONFIG_NSH_DISABLE_RM=y +CONFIG_NSH_DISABLE_RMDIR=y +CONFIG_NSH_DISABLE_SET=y +CONFIG_NSH_DISABLE_SH=y +CONFIG_NSH_DISABLE_SLEEP=y +CONFIG_NSH_DISABLE_TIME=y +CONFIG_NSH_DISABLE_TEST=y +CONFIG_NSH_DISABLE_UMOUNT=y +CONFIG_NSH_DISABLE_UNAME=y +CONFIG_NSH_DISABLE_UNSET=y +CONFIG_NSH_DISABLE_USLEEP=y +CONFIG_NSH_DISABLE_WGET=y +CONFIG_NSH_DISABLE_XD=y +CONFIG_NSH_MMCSDMINOR=0 + +# +# Configure Command Options +# +CONFIG_NSH_CODECS_BUFSIZE=128 +CONFIG_NSH_FILEIOSIZE=256 + +# +# Scripting Support +# +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_ITEF is not set +# CONFIG_NSH_DISABLE_LOOPS is not set + +# +# Console Configuration +# +CONFIG_NSH_CONSOLE=y +# CONFIG_NSH_ALTCONDEV is not set +# CONFIG_NSH_ARCHINIT is not set +# CONFIG_NSH_LOGIN is not set +# CONFIG_NSH_CONSOLE_LOGIN is not set + +# +# NxWidgets/NxWM +# + +# +# Platform-specific Support +# +# CONFIG_PLATFORM_CONFIGDATA is not set + +# +# System Libraries and NSH Add-Ons +# +# CONFIG_SYSTEM_CLE is not set +# CONFIG_SYSTEM_CUTERM is not set +# CONFIG_SYSTEM_FREE is not set +# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_SYSTEM_HEXED is not set +# CONFIG_SYSTEM_INSTALL is not set +# CONFIG_SYSTEM_RAMTEST is not set +CONFIG_READLINE_HAVE_EXTMATCH=y +CONFIG_SYSTEM_READLINE=y +CONFIG_READLINE_ECHO=y +# CONFIG_READLINE_TABCOMPLETION is not set +# CONFIG_READLINE_CMD_HISTORY is not set +# CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set +# CONFIG_SYSTEM_UBLOXMODEM is not set +# CONFIG_SYSTEM_VI is not set +# CONFIG_SYSTEM_ZMODEM is not set \ No newline at end of file diff --git a/configs/nucleo-f334r8/adc/setenv.sh b/configs/nucleo-f334r8/adc/setenv.sh new file mode 100644 index 00000000000..a9a8fc14a49 --- /dev/null +++ b/configs/nucleo-f334r8/adc/setenv.sh @@ -0,0 +1,77 @@ +#!/bin/bash +# configs/nucleo-f224r8/adc/setenv.sh +# +# Copyright (C) 2017 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +if [ "$_" = "$0" ] ; then + echo "You must source this script, not run it!" 1>&2 + exit 1 +fi + +WD=`pwd` +if [ ! -x "setenv.sh" ]; then + echo "This script must be executed from the top-level NuttX build directory" + exit 1 +fi + +if [ -z "${PATH_ORIG}" ]; then + export PATH_ORIG="${PATH}" +fi + +# This is the Cygwin path to the location where I installed the Atmel GCC +# toolchain under Windows. You will also have to edit this if you install +# this toolchain in any other location +#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/Atmel/Atmel Toolchain/ARM GCC/Native/4.7.3.99/arm-gnu-toolchain/bin" + +# This is the Cygwin path to the location where I installed the CodeSourcery +# toolchain under windows. You will also have to edit this if you install +# the CodeSourcery toolchain in any other location +#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin" +#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery_CodeBench_Lite_for_ARM_EABI/bin" +# export TOOLCHAIN_BIN="/cygdrive/c/Users/MyName/MentorGraphics/Sourcery_CodeBench_Lite_for_ARM_EABI/bin" + +# This is the location where I installed the ARM "GNU Tools for ARM Embedded Processors" +# You can this free toolchain here https://launchpad.net/gcc-arm-embedded +export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/GNU Tools ARM Embedded/4.9 2015q2/bin" + +# This is the path to the location where I installed the devkitARM toolchain +# You can get this free toolchain from http://devkitpro.org/ or http://sourceforge.net/projects/devkitpro/ +#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/devkitARM/bin" + +# This is the Cygwin path to the location where I build the buildroot +# toolchain. +# export TOOLCHAIN_BIN="${WD}/../buildroot/build_arm_nofpu/staging_dir/bin" + +# Add the path to the toolchain to the PATH varialble +export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}" + +echo "PATH : ${PATH}" diff --git a/configs/nucleo-f334r8/include/board.h b/configs/nucleo-f334r8/include/board.h index 0ebacd0b0c3..8d5ce807dcc 100644 --- a/configs/nucleo-f334r8/include/board.h +++ b/configs/nucleo-f334r8/include/board.h @@ -243,8 +243,8 @@ /* DMA channels *************************************************************/ /* ADC */ -#define ADC1_DMA_CHAN DMACHAN_ADC1 -#define ADC2_DMA_CHAN DMACHAN_ADC2_ +#define ADC1_DMA_CHAN DMACHAN_ADC1 /* DMA1_CH1 */ +#define ADC2_DMA_CHAN DMACHAN_ADC2_1 /* DMA1_CH2 */ /**************************************************************************** * Public Data diff --git a/configs/nucleo-f334r8/src/stm32_adc.c b/configs/nucleo-f334r8/src/stm32_adc.c index e69de29bb2d..f46970cef94 100644 --- a/configs/nucleo-f334r8/src/stm32_adc.c +++ b/configs/nucleo-f334r8/src/stm32_adc.c @@ -0,0 +1,253 @@ +/**************************************************************************** + * configs/nucleo-f334r8/src/stm32_adc.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Mateusz Szafoni + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" + +#if defined(CONFIG_ADC) && (defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2)) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* 1 or 2 ADC devices (DEV1, DEV2) */ + +#if defined(CONFIG_STM32_ADC1) +# define DEV1_PORT 1 +#endif + +#if defined(CONFIG_STM32_ADC2) +# if defined(DEV1_PORT) +# define DEV2_PORT 2 +# else +# define DEV1_PORT 2 +# endif +#endif + +/* The number of ADC channels in the conversion list */ +/* TODO DMA */ + +#define ADC1_NCHANNELS 3 +#define ADC2_NCHANNELS 3 + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* DEV 1 */ + +#if DEV1_PORT == 1 + +#define DEV1_NCHANNELS ADC1_NCHANNELS + +/* Identifying number of each ADC channel (even if NCHANNELS is less ) */ + +static const uint8_t g_chanlist1[3] = +{ + 1, + 2, + 11 +}; + +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist1[3] = +{ + GPIO_ADC1_IN1, /* PA0/A0 */ + GPIO_ADC1_IN2, /* PA1/A1 */ + GPIO_ADC1_IN11, /* PB0/A3 */ +}; + +#elif DEV1_PORT == 2 + +#define DEV1_NCHANNELS ADC2_NCHANNELS + +/* Identifying number of each ADC channel */ + +static const uint8_t g_chanlist1[3] = +{ + 1, + 6, + 7 +}; + +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist1[3] = +{ + GPIO_ADC2_IN1, /* PA4/A2 */ + GPIO_ADC2_IN7, /* PC1/A4 */ + GPIO_ADC2_IN6, /* PC0/A5 */ +}; + +#endif /* DEV1_PORT == 1 */ + +#ifdef DEV2_PORT + +/* DEV 2 */ + +#if DEV2_PORT == 2 + +#define DEV2_NCHANNELS ADC2_NCHANNELS + +/* Identifying number of each ADC channel */ + +static const uint8_t g_chanlist2[1] = +{ + 1, + 6, + 7 +}; + +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist2[3] = +{ + GPIO_ADC2_IN1, /* PA4/A2 */ + GPIO_ADC2_IN7, /* PC1/A4 */ + GPIO_ADC2_IN6, /* PC0/A5 */ +}; + +#endif /* DEV2_PORT == 2 */ +#endif /* DEV2_PORT */ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/************************************************************************************ + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ************************************************************************************/ + +int stm32_adc_setup(void) +{ + static bool initialized = false; + FAR struct adc_dev_s *adc; + int ret; + int i; + + /* Check if we have already initialized */ + + if (!initialized) + { + /* DEV1 */ + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < DEV1_NCHANNELS; i++) + { + stm32_configgpio(g_pinlist1[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(DEV1_PORT, g_chanlist1, DEV1_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface 1\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc0" */ + + ret = adc_register("/dev/adc0", adc); + if (ret < 0) + { + aerr("ERROR: adc_register /dev/adc0 failed: %d\n", ret); + return ret; + } + +#ifdef DEV2_PORT + + /* DEV2 */ + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < DEV2_NCHANNELS; i++) + { + stm32_configgpio(g_pinlist2[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(DEV2_PORT, g_chanlist2, DEV2_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface 2\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc1" */ + + ret = adc_register("/dev/adc1", adc); + if (ret < 0) + { + aerr("ERROR: adc_register /dev/adc1 failed: %d\n", ret); + return ret; + } +#endif + + initialized = true; + + } + + return OK; +} + +#endif /* CONFIG_ADC && (CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2) */ diff --git a/configs/nucleo-f334r8/src/stm32_appinit.c b/configs/nucleo-f334r8/src/stm32_appinit.c index 8e7e7535d4b..3579835c631 100644 --- a/configs/nucleo-f334r8/src/stm32_appinit.c +++ b/configs/nucleo-f334r8/src/stm32_appinit.c @@ -45,7 +45,7 @@ #include #include -#include "nucleo-f303re.h" +#include "nucleo-f334r8.h" /**************************************************************************** * Pre-processor Definitions @@ -107,6 +107,26 @@ int board_app_initialize(uintptr_t arg) } #endif +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = stm32_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_DAC + /* Initialize DAC and register the DAC driver. */ + + ret = stm32_dac_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_dac_setup failed: %d\n", ret); + } +#endif + UNUSED(ret); return OK; } diff --git a/configs/nucleo-f334r8/src/stm32_boot.c b/configs/nucleo-f334r8/src/stm32_boot.c index 370a1984102..278589e295e 100644 --- a/configs/nucleo-f334r8/src/stm32_boot.c +++ b/configs/nucleo-f334r8/src/stm32_boot.c @@ -78,9 +78,10 @@ void stm32_boardinitialize(void) { +#ifdef CONFIG_ARCH_LEDS /* Configure on-board LEDs if LED support has been selected. */ -#ifdef CONFIG_ARCH_LEDS board_autoled_initialize(); #endif + } From a10735b50d781f5006ed0dd9ac464bb8582dee73 Mon Sep 17 00:00:00 2001 From: Heesub Shin Date: Sat, 18 Mar 2017 22:27:06 +0900 Subject: [PATCH 33/81] mtd/progmem: fix incorrect target address calculation progmem_read/write() is incorrectly calculating the target address, expecting the offset argument is given in a block number. This is completely wrong and as a result invalid flash region is accessed. Byte-oriented read/write interfaces of mtd device accept the target address in a byte offset, not a block number. Signed-off-by: Heesub Shin --- drivers/mtd/mtd_progmem.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/mtd_progmem.c b/drivers/mtd/mtd_progmem.c index 3d76402fd86..9785a4c3607 100644 --- a/drivers/mtd/mtd_progmem.c +++ b/drivers/mtd/mtd_progmem.c @@ -245,14 +245,18 @@ static ssize_t progmem_bwrite(FAR struct mtd_dev_s *dev, off_t startblock, static ssize_t progmem_read(FAR struct mtd_dev_s *dev, off_t offset, size_t nbytes, FAR uint8_t *buffer) { + FAR struct progmem_dev_s *priv = (FAR struct progmem_dev_s *)dev; FAR const uint8_t *src; + off_t startblock; /* Read the specified bytes into the provided user buffer and return * status (The positive, number of bytes actually read or a negated * errno) */ - src = (FAR const uint8_t *)up_progmem_getaddress(offset); + startblock = offset >> priv->blkshift; + src = (FAR const uint8_t *)up_progmem_getaddress(startblock) + + (offset & ((1 << priv->blkshift) - 1)); memcpy(buffer, src, nbytes); return nbytes; } @@ -271,13 +275,16 @@ static ssize_t progmem_write(FAR struct mtd_dev_s *dev, off_t offset, size_t nbytes, FAR const uint8_t *buffer) { FAR struct progmem_dev_s *priv = (FAR struct progmem_dev_s *)dev; + off_t startblock; ssize_t result; /* Write the specified blocks from the provided user buffer and return status * (The positive, number of blocks actually written or a negated errno) */ - result = up_progmem_write(up_progmem_getaddress(offset), buffer, nbytes); + startblock = offset >> priv->blkshift; + result = up_progmem_write(up_progmem_getaddress(startblock) + + (offset & ((1 << priv->blkshift) - 1)), buffer, nbytes); return result < 0 ? result : nbytes; } #endif From 9769c67d4da19d1a52e910cc7fba21887442095c Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 18 Mar 2017 11:25:14 -0600 Subject: [PATCH 34/81] XMC4xxx: Add pin multiplexing header file. --- arch/arm/src/xmc4/chip/xmc4_pinmux.h | 752 +++++++++++++++++++++++++++ arch/arm/src/xmc4/xmc4_gpio.h | 2 +- 2 files changed, 753 insertions(+), 1 deletion(-) diff --git a/arch/arm/src/xmc4/chip/xmc4_pinmux.h b/arch/arm/src/xmc4/chip/xmc4_pinmux.h index 44d43074a83..b4ba4b0e24e 100644 --- a/arch/arm/src/xmc4/chip/xmc4_pinmux.h +++ b/arch/arm/src/xmc4/chip/xmc4_pinmux.h @@ -47,6 +47,758 @@ /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ +/* Alternate Pin Functions. All members of the XMC4xxx family share the same + * pin multiplexing (although they may differ in the pins physically available). + * + * Alternative pin selections are provided with a numeric suffix like _1, _2, etc. + * Drivers, however, will use the pin selection without the numeric suffix. + * Additional definitions are required in the board.h file. For example, if + * CAN_N2TXD connects vis P1.9 on some board, then the following definition should + * appear in the board.h header file for that board: + * + * #define GPIO_CAN_N2TXD GPIO_CAN_N2TXD_1 + * + * The driver will then automatically configre PA11 as the CAN1 RX pin. + */ +/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! + * Additional effort is required to select specific GPIO options such as frequency, + * open-drain/push-pull, and pull-up/down! Just the basics are defined for most + * pins in this file. + */ + +#define GPIO_CAN_N0RXDA (GPIO_INPUT | GPIO_PORT1 | GPIO_PIN5) +#define GPIO_CAN_N0RXDB (GPIO_INPUT | GPIO_PORT14 | GPIO_PIN3) +#define GPIO_CAN_N0RXDC (GPIO_INPUT | GPIO_PORT3 | GPIO_PIN12) +#define GPIO_CAN_N0TXD_1 (GPIO_OUTPUT_ALT2 | GPIO_PORT0 | GPIO_PIN0) +#define GPIO_CAN_N0TXD_2 (GPIO_OUTPUT_ALT2 | GPIO_PORT1 | GPIO_PIN4) +#define GPIO_CAN_N0TXD_3 (GPIO_OUTPUT_ALT2 | GPIO_PORT3 | GPIO_PIN10) +#define GPIO_CAN_N0TXD_4 (GPIO_OUTPUT_ALT2 | GPIO_PORT3 | GPIO_PIN2) +#define GPIO_CAN_N1RXDA (GPIO_INPUT | GPIO_PORT2 | GPIO_PIN6) +#define GPIO_CAN_N1RXDB (GPIO_INPUT | GPIO_PORT3 | GPIO_PIN11) +#define GPIO_CAN_N1RXDC (GPIO_INPUT | GPIO_PORT1 | GPIO_PIN13) +#define GPIO_CAN_N1RXDD (GPIO_INPUT | GPIO_PORT1 | GPIO_PIN4) +#define GPIO_CAN_N1TXD_1 (GPIO_OUTPUT_ALT1 | GPIO_PORT1 | GPIO_PIN5) +#define GPIO_CAN_N1TXD_2 (GPIO_OUTPUT_ALT2 | GPIO_PORT1 | GPIO_PIN12) +#define GPIO_CAN_N1TXD_3 (GPIO_OUTPUT_ALT2 | GPIO_PORT2 | GPIO_PIN7) +#define GPIO_CAN_N1TXD_4 (GPIO_OUTPUT_ALT2 | GPIO_PORT3 | GPIO_PIN9) +#define GPIO_CAN_N2RXDA (GPIO_INPUT | GPIO_PORT1 | GPIO_PIN8) +#define GPIO_CAN_N2RXDB (GPIO_INPUT | GPIO_PORT3 | GPIO_PIN8) +#define GPIO_CAN_N2RXDC (GPIO_INPUT | GPIO_PORT4 | GPIO_PIN6) +#define GPIO_CAN_N2TXD_1 (GPIO_OUTPUT_ALT2 | GPIO_PORT1 | GPIO_PIN9) +#define GPIO_CAN_N2TXD_2 (GPIO_OUTPUT_ALT2 | GPIO_PORT3 | GPIO_PIN7) +#define GPIO_CAN_N2TXD_3 (GPIO_OUTPUT_ALT2 | GPIO_PORT4 | GPIO_PIN7) + +#define GPIO_CCU40_IN0A (GPIO_INPUT | GPIO_PORT1 | GPIO_PIN3) +#define GPIO_CCU40_IN0B (GPIO_INPUT | GPIO_PORT2 | GPIO_PIN8) +#define GPIO_CCU40_IN0C (GPIO_INPUT | GPIO_PORT2 | GPIO_PIN1) +#define GPIO_CCU40_IN1A (GPIO_INPUT | GPIO_PORT1 | GPIO_PIN2) +#define GPIO_CCU40_IN1B (GPIO_INPUT | GPIO_PORT2 | GPIO_PIN8) +#define GPIO_CCU40_IN1C (GPIO_INPUT | GPIO_PORT2 | GPIO_PIN0) +#define GPIO_CCU40_IN2A (GPIO_INPUT | GPIO_PORT1 | GPIO_PIN1) +#define GPIO_CCU40_IN2B (GPIO_INPUT | GPIO_PORT2 | GPIO_PIN8) +#define GPIO_CCU40_IN2C (GPIO_INPUT | GPIO_PORT2 | GPIO_PIN7) +#define GPIO_CCU40_IN3A (GPIO_INPUT | GPIO_PORT1 | GPIO_PIN0) +#define GPIO_CCU40_IN3B (GPIO_INPUT | GPIO_PORT2 | GPIO_PIN8) +#define GPIO_CCU40_IN3C (GPIO_INPUT | GPIO_PORT2 | GPIO_PIN6) +#define GPIO_CCU40_OUT0_1 (GPIO_OUTPUT_ALT3 | GPIO_PORT0 | GPIO_PIN15) +#define GPIO_CCU40_OUT0_2 (GPIO_OUTPUT_ALT3 | GPIO_PORT1 | GPIO_PIN3) +#define GPIO_CCU40_OUT1_1 (GPIO_OUTPUT_ALT3 | GPIO_PORT0 | GPIO_PIN14) +#define GPIO_CCU40_OUT1_2 (GPIO_OUTPUT_ALT3 | GPIO_PORT1 | GPIO_PIN2) +#define GPIO_CCU40_OUT2_1 (GPIO_OUTPUT_ALT3 | GPIO_PORT0 | GPIO_PIN13) +#define GPIO_CCU40_OUT2_2 (GPIO_OUTPUT_ALT3 | GPIO_PORT1 | GPIO_PIN1) +#define GPIO_CCU40_OUT3_1 (GPIO_OUTPUT_ALT3 | GPIO_PORT0 | GPIO_PIN12) +#define GPIO_CCU40_OUT3_2 (GPIO_OUTPUT_ALT3 | GPIO_PORT1 | GPIO_PIN0) +#define GPIO_CCU41_IN0A (GPIO_INPUT | GPIO_PORT2 | GPIO_PIN5) +#define GPIO_CCU41_IN0B (GPIO_INPUT | GPIO_PORT2 | GPIO_PIN9) +#define GPIO_CCU41_IN0C (GPIO_INPUT | GPIO_PORT1 | GPIO_PIN4) +#define GPIO_CCU41_IN1A (GPIO_INPUT | GPIO_PORT2 | GPIO_PIN4) +#define GPIO_CCU41_IN1B (GPIO_INPUT | GPIO_PORT2 | GPIO_PIN9) +#define GPIO_CCU41_IN1C (GPIO_INPUT | GPIO_PORT1 | GPIO_PIN5) +#define GPIO_CCU41_IN2A (GPIO_INPUT | GPIO_PORT2 | GPIO_PIN3) +#define GPIO_CCU41_IN2B (GPIO_INPUT | GPIO_PORT2 | GPIO_PIN9) +#define GPIO_CCU41_IN2C (GPIO_INPUT | GPIO_PORT1 | GPIO_PIN10) +#define GPIO_CCU41_IN3A (GPIO_INPUT | GPIO_PORT2 | GPIO_PIN2) +#define GPIO_CCU41_IN3B (GPIO_INPUT | GPIO_PORT2 | GPIO_PIN9) +#define GPIO_CCU41_IN3C (GPIO_INPUT | GPIO_PORT1 | GPIO_PIN11) +#define GPIO_CCU41_OUT0_1 (GPIO_OUTPUT_ALT3 | GPIO_PORT2 | GPIO_PIN5) +#define GPIO_CCU41_OUT0_2 (GPIO_OUTPUT_ALT3 | GPIO_PORT3 | GPIO_PIN10) +#define GPIO_CCU41_OUT1_1 (GPIO_OUTPUT_ALT3 | GPIO_PORT2 | GPIO_PIN4) +#define GPIO_CCU41_OUT1_2 (GPIO_OUTPUT_ALT3 | GPIO_PORT3 | GPIO_PIN9) +#define GPIO_CCU41_OUT2_1 (GPIO_OUTPUT_ALT3 | GPIO_PORT2 | GPIO_PIN3) +#define GPIO_CCU41_OUT2_2 (GPIO_OUTPUT_ALT3 | GPIO_PORT3 | GPIO_PIN8) +#define GPIO_CCU41_OUT3_1 (GPIO_OUTPUT_ALT3 | GPIO_PORT2 | GPIO_PIN2) +#define GPIO_CCU41_OUT3_2 (GPIO_OUTPUT_ALT3 | GPIO_PORT3 | GPIO_PIN7) +#define GPIO_CCU42_IN0A (GPIO_INPUT | GPIO_PORT3 | GPIO_PIN6) +#define GPIO_CCU42_IN0B (GPIO_INPUT | GPIO_PORT2 | GPIO_PIN15) +#define GPIO_CCU42_IN0C (GPIO_INPUT | GPIO_PORT3 | GPIO_PIN15) +#define GPIO_CCU42_IN1A (GPIO_INPUT | GPIO_PORT3 | GPIO_PIN5) +#define GPIO_CCU42_IN1B (GPIO_INPUT | GPIO_PORT2 | GPIO_PIN15) +#define GPIO_CCU42_IN1C (GPIO_INPUT | GPIO_PORT3 | GPIO_PIN14) +#define GPIO_CCU42_IN2A (GPIO_INPUT | GPIO_PORT3 | GPIO_PIN4) +#define GPIO_CCU42_IN2B (GPIO_INPUT | GPIO_PORT2 | GPIO_PIN15) +#define GPIO_CCU42_IN2C (GPIO_INPUT | GPIO_PORT0 | GPIO_PIN15) +#define GPIO_CCU42_IN3A (GPIO_INPUT | GPIO_PORT3 | GPIO_PIN3) +#define GPIO_CCU42_IN3B (GPIO_INPUT | GPIO_PORT2 | GPIO_PIN15) +#define GPIO_CCU42_IN3C (GPIO_INPUT | GPIO_PORT0 | GPIO_PIN14) +#define GPIO_CCU42_OUT0_1 (GPIO_OUTPUT_ALT3 | GPIO_PORT3 | GPIO_PIN0) +#define GPIO_CCU42_OUT0_2 (GPIO_OUTPUT_ALT3 | GPIO_PORT3 | GPIO_PIN6) +#define GPIO_CCU42_OUT1_1 (GPIO_OUTPUT_ALT3 | GPIO_PORT3 | GPIO_PIN13) +#define GPIO_CCU42_OUT1_2 (GPIO_OUTPUT_ALT3 | GPIO_PORT3 | GPIO_PIN5) +#define GPIO_CCU42_OUT2_1 (GPIO_OUTPUT_ALT3 | GPIO_PORT3 | GPIO_PIN12) +#define GPIO_CCU42_OUT2_2 (GPIO_OUTPUT_ALT3 | GPIO_PORT3 | GPIO_PIN4) +#define GPIO_CCU42_OUT3_1 (GPIO_OUTPUT_ALT3 | GPIO_PORT3 | GPIO_PIN11) +#define GPIO_CCU42_OUT3_2 (GPIO_OUTPUT_ALT3 | GPIO_PORT3 | GPIO_PIN3) +#define GPIO_CCU43_IN0A (GPIO_INPUT | GPIO_PORT4 | GPIO_PIN6) +#define GPIO_CCU43_IN0B (GPIO_INPUT | GPIO_PORT2 | GPIO_PIN14) +#define GPIO_CCU43_IN0C (GPIO_INPUT | GPIO_PORT4 | GPIO_PIN7) +#define GPIO_CCU43_IN1A (GPIO_INPUT | GPIO_PORT4 | GPIO_PIN5) +#define GPIO_CCU43_IN1B (GPIO_INPUT | GPIO_PORT2 | GPIO_PIN14) +#define GPIO_CCU43_IN1C (GPIO_INPUT | GPIO_PORT4 | GPIO_PIN2) +#define GPIO_CCU43_IN2A (GPIO_INPUT | GPIO_PORT4 | GPIO_PIN4) +#define GPIO_CCU43_IN2B (GPIO_INPUT | GPIO_PORT2 | GPIO_PIN14) +#define GPIO_CCU43_IN2C (GPIO_INPUT | GPIO_PORT2 | GPIO_PIN13) +#define GPIO_CCU43_IN3A (GPIO_INPUT | GPIO_PORT4 | GPIO_PIN3) +#define GPIO_CCU43_IN3B (GPIO_INPUT | GPIO_PORT2 | GPIO_PIN14) +#define GPIO_CCU43_IN3C (GPIO_INPUT | GPIO_PORT2 | GPIO_PIN12) +#define GPIO_CCU43_OUT0_1 (GPIO_OUTPUT_ALT3 | GPIO_PORT4 | GPIO_PIN6) +#define GPIO_CCU43_OUT0_2 (GPIO_OUTPUT_ALT3 | GPIO_PORT6 | GPIO_PIN5) +#define GPIO_CCU43_OUT1_1 (GPIO_OUTPUT_ALT3 | GPIO_PORT4 | GPIO_PIN5) +#define GPIO_CCU43_OUT1_2 (GPIO_OUTPUT_ALT3 | GPIO_PORT6 | GPIO_PIN4) +#define GPIO_CCU43_OUT2_1 (GPIO_OUTPUT_ALT3 | GPIO_PORT4 | GPIO_PIN4) +#define GPIO_CCU43_OUT2_2 (GPIO_OUTPUT_ALT3 | GPIO_PORT6 | GPIO_PIN3) +#define GPIO_CCU43_OUT3_1 (GPIO_OUTPUT_ALT3 | GPIO_PORT4 | GPIO_PIN3) +#define GPIO_CCU43_OUT3_2 (GPIO_OUTPUT_ALT3 | GPIO_PORT6 | GPIO_PIN2) +#define GPIO_CCU80_IN0A (GPIO_INPUT | GPIO_PORT0 | GPIO_PIN7) +#define GPIO_CCU80_IN0B (GPIO_INPUT | GPIO_PORT3 | GPIO_PIN4) +#define GPIO_CCU80_IN0C (GPIO_INPUT | GPIO_PORT3 | GPIO_PIN2) +#define GPIO_CCU80_IN1A (GPIO_INPUT | GPIO_PORT0 | GPIO_PIN7) +#define GPIO_CCU80_IN1B (GPIO_INPUT | GPIO_PORT0 | GPIO_PIN8) +#define GPIO_CCU80_IN1C (GPIO_INPUT | GPIO_PORT3 | GPIO_PIN1) +#define GPIO_CCU80_IN2A (GPIO_INPUT | GPIO_PORT0 | GPIO_PIN7) +#define GPIO_CCU80_IN2B (GPIO_INPUT | GPIO_PORT0 | GPIO_PIN6) +#define GPIO_CCU80_IN2C (GPIO_INPUT | GPIO_PORT3 | GPIO_PIN0) +#define GPIO_CCU80_IN3A (GPIO_INPUT | GPIO_PORT0 | GPIO_PIN7) +#define GPIO_CCU80_IN3B (GPIO_INPUT | GPIO_PORT3 | GPIO_PIN3) +#define GPIO_CCU80_IN3C (GPIO_INPUT | GPIO_PORT3 | GPIO_PIN13) +#define GPIO_CCU80_OUT00_1 (GPIO_OUTPUT_ALT3 | GPIO_PORT0 | GPIO_PIN5) +#define GPIO_CCU80_OUT00_2 (GPIO_OUTPUT_ALT3 | GPIO_PORT5 | GPIO_PIN11) +#define GPIO_CCU80_OUT01_1 (GPIO_OUTPUT_ALT3 | GPIO_PORT0 | GPIO_PIN2) +#define GPIO_CCU80_OUT01_2 (GPIO_OUTPUT_ALT3 | GPIO_PORT5 | GPIO_PIN8) +#define GPIO_CCU80_OUT02 1 (GPIO_OUTPUT_ALT3 | GPIO_PORT0 | GPIO_PIN10) +#define GPIO_CCU80_OUT03 2 (GPIO_OUTPUT_ALT3 | GPIO_PORT2 | GPIO_PIN7) +#define GPIO_CCU80_OUT10_1 (GPIO_OUTPUT_ALT3 | GPIO_PORT0 | GPIO_PIN4) +#define GPIO_CCU80_OUT10_2 (GPIO_OUTPUT_ALT3 | GPIO_PORT5 | GPIO_PIN10) +#define GPIO_CCU80_OUT11_1 (GPIO_OUTPUT_ALT3 | GPIO_PORT0 | GPIO_PIN1) +#define GPIO_CCU80_OUT11_2 (GPIO_OUTPUT_ALT3 | GPIO_PORT2 | GPIO_PIN15) +#define GPIO_CCU80_OUT12 (GPIO_OUTPUT_ALT3 | GPIO_PORT0 | GPIO_PIN9) +#define GPIO_CCU80_OUT13 (GPIO_OUTPUT_ALT3 | GPIO_PORT2 | GPIO_PIN6) +#define GPIO_CCU80_OUT20_1 (GPIO_OUTPUT_ALT3 | GPIO_PORT0 | GPIO_PIN3) +#define GPIO_CCU80_OUT20_2 (GPIO_OUTPUT_ALT3 | GPIO_PORT5 | GPIO_PIN9) +#define GPIO_CCU80_OUT21_1 (GPIO_OUTPUT_ALT3 | GPIO_PORT0 | GPIO_PIN0) +#define GPIO_CCU80_OUT21_2 (GPIO_OUTPUT_ALT3 | GPIO_PORT2 | GPIO_PIN14) +#define GPIO_CCU80_OUT22_1 (GPIO_OUTPUT_ALT3 | GPIO_PORT2 | GPIO_PIN11) +#define GPIO_CCU80_OUT22_2 (GPIO_OUTPUT_ALT3 | GPIO_PORT2 | GPIO_PIN9) +#define GPIO_CCU80_OUT23 (GPIO_OUTPUT_ALT3 | GPIO_PORT1 | GPIO_PIN5) +#define GPIO_CCU80_OUT30 (GPIO_OUTPUT_ALT3 | GPIO_PORT0 | GPIO_PIN6) +#define GPIO_CCU80_OUT31 (GPIO_OUTPUT_ALT3 | GPIO_PORT0 | GPIO_PIN11) +#define GPIO_CCU80_OUT32 (GPIO_OUTPUT_ALT3 | GPIO_PORT2 | GPIO_PIN8) +#define GPIO_CCU80_OUT33 (GPIO_OUTPUT_ALT3 | GPIO_PORT1 | GPIO_PIN4) +#define GPIO_CCU81_IN0A (GPIO_INPUT | GPIO_PORT5 | GPIO_PIN0) +#define GPIO_CCU81_IN0B (GPIO_INPUT | GPIO_PORT5 | GPIO_PIN1) +#define GPIO_CCU81_IN0C (GPIO_INPUT | GPIO_PORT3 | GPIO_PIN0) +#define GPIO_CCU81_IN1A (GPIO_INPUT | GPIO_PORT5 | GPIO_PIN0) +#define GPIO_CCU81_IN1B (GPIO_INPUT | GPIO_PORT5 | GPIO_PIN2) +#define GPIO_CCU81_IN1C (GPIO_INPUT | GPIO_PORT3 | GPIO_PIN13) +#define GPIO_CCU81_IN2A (GPIO_INPUT | GPIO_PORT5 | GPIO_PIN0) +#define GPIO_CCU81_IN2B (GPIO_INPUT | GPIO_PORT5 | GPIO_PIN3) +#define GPIO_CCU81_IN2C (GPIO_INPUT | GPIO_PORT3 | GPIO_PIN12) +#define GPIO_CCU81_IN3A (GPIO_INPUT | GPIO_PORT5 | GPIO_PIN0) +#define GPIO_CCU81_IN3B (GPIO_INPUT | GPIO_PORT5 | GPIO_PIN4) +#define GPIO_CCU81_IN3C (GPIO_INPUT | GPIO_PORT3 | GPIO_PIN11) +#define GPIO_CCU81_OUT00 (GPIO_OUTPUT_ALT3 | GPIO_PORT1 | GPIO_PIN15) +#define GPIO_CCU81_OUT01_1 (GPIO_OUTPUT_ALT2 | GPIO_PORT2 | GPIO_PIN2) +#define GPIO_CCU81_OUT01_2 (GPIO_OUTPUT_ALT3 | GPIO_PORT1 | GPIO_PIN12) +#define GPIO_CCU81_OUT02 (GPIO_OUTPUT_ALT3 | GPIO_PORT5 | GPIO_PIN7) +#define GPIO_CCU81_OUT03 (GPIO_OUTPUT_ALT3 | GPIO_PORT5 | GPIO_PIN6) +#define GPIO_CCU81_OUT10_1 (GPIO_OUTPUT_ALT3 | GPIO_PORT1 | GPIO_PIN14) +#define GPIO_CCU81_OUT10_2 (GPIO_OUTPUT_ALT4 | GPIO_PORT1 | GPIO_PIN5) +#define GPIO_CCU81_OUT11_1 (GPIO_OUTPUT_ALT2 | GPIO_PORT2 | GPIO_PIN1) +#define GPIO_CCU81_OUT11_2 (GPIO_OUTPUT_ALT3 | GPIO_PORT1 | GPIO_PIN11) +#define GPIO_CCU81_OUT12 (GPIO_OUTPUT_ALT3 | GPIO_PORT5 | GPIO_PIN5) +#define GPIO_CCU81_OUT13 (GPIO_OUTPUT_ALT3 | GPIO_PORT5 | GPIO_PIN4) +#define GPIO_CCU81_OUT20_1 (GPIO_OUTPUT_ALT3 | GPIO_PORT1 | GPIO_PIN13) +#define GPIO_CCU81_OUT20_2 (GPIO_OUTPUT_ALT4 | GPIO_PORT1 | GPIO_PIN4) +#define GPIO_CCU81_OUT21_1 (GPIO_OUTPUT_ALT2 | GPIO_PORT2 | GPIO_PIN0) +#define GPIO_CCU81_OUT21_2 (GPIO_OUTPUT_ALT3 | GPIO_PORT1 | GPIO_PIN10) +#define GPIO_CCU81_OUT22 (GPIO_OUTPUT_ALT3 | GPIO_PORT5 | GPIO_PIN3) +#define GPIO_CCU81_OUT23 (GPIO_OUTPUT_ALT3 | GPIO_PORT5 | GPIO_PIN2) +#define GPIO_CCU81_OUT30 (GPIO_OUTPUT_ALT3 | GPIO_PORT6 | GPIO_PIN1) +#define GPIO_CCU81_OUT31 (GPIO_OUTPUT_ALT3 | GPIO_PORT6 | GPIO_PIN0) +#define GPIO_CCU81_OUT32 (GPIO_OUTPUT_ALT3 | GPIO_PORT5 | GPIO_PIN1) +#define GPIO_CCU81_OUT33_1 (GPIO_OUTPUT_ALT3 | GPIO_PORT2 | GPIO_PIN12) +#define GPIO_CCU81_OUT33_2 (GPIO_OUTPUT_ALT3 | GPIO_PORT5 | GPIO_PIN0) + +#define GPIO_DAC_OUT0 (GPIO_OUTPUT | GPIO_PINCTRL_HW0 | GPIO_PORT14 | GPIO_PIN8) +#define GPIO_DAC_OUT1 (GPIO_OUTPUT | GPIO_PINCTRL_HW0 | GPIO_PORT14 | GPIO_PIN9) + +#define GPIO_DAC_TRIGGER4 (GPIO_INPUT | GPIO_PORT2 | GPIO_PIN9) +#define GPIO_DAC_TRIGGER5 (GPIO_INPUT | GPIO_PORT2 | GPIO_PIN8) +#define GPIO_DB_ETMTRACECLK_1 (GPIO_OUTPUT | GPIO_PINCTRL_HW0 | GPIO_PORT2 | GPIO_PIN14) +#define GPIO_DB_ETMTRACECLK_2 (GPIO_OUTPUT | GPIO_PINCTRL_HW0 | GPIO_PORT6 | GPIO_PIN0) +#define GPIO_DB_ETMTRACEDATA0_1 (GPIO_OUTPUT | GPIO_PINCTRL_HW0 | GPIO_PORT2 | GPIO_PIN13) +#define GPIO_DB_ETMTRACEDATA0_2 (GPIO_OUTPUT | GPIO_PINCTRL_HW0 | GPIO_PORT6 | GPIO_PIN6) +#define GPIO_DB_ETMTRACEDATA1_1 (GPIO_OUTPUT | GPIO_PINCTRL_HW0 | GPIO_PORT2 | GPIO_PIN12) +#define GPIO_DB_ETMTRACEDATA1_2 (GPIO_OUTPUT | GPIO_PINCTRL_HW0 | GPIO_PORT6 | GPIO_PIN5) +#define GPIO_DB_ETMTRACEDATA2_1 (GPIO_OUTPUT | GPIO_PINCTRL_HW0 | GPIO_PORT2 | GPIO_PIN11) +#define GPIO_DB_ETMTRACEDATA2_2 (GPIO_OUTPUT | GPIO_PINCTRL_HW0 | GPIO_PORT6 | GPIO_PIN2) +#define GPIO_DB_ETMTRACEDATA3_1 (GPIO_OUTPUT | GPIO_PINCTRL_HW0 | GPIO_PORT2 | GPIO_PIN10) +#define GPIO_DB_ETMTRACEDATA3_2 (GPIO_OUTPUT | GPIO_PINCTRL_HW0 | GPIO_PORT6 | GPIO_PIN1) +#define GPIO_DB_TDI (GPIO_INPUT | GPIO_PINCTRL_HW0 | GPIO_PORT0 | GPIO_PIN7) +#define GPIO_DB_TDO (GPIO_OUTPUT | GPIO_PINCTRL_HW0 | GPIO_PORT2 | GPIO_PIN1) + +#define GPIO_DB_TRST (GPIO_INPUT | GPIO_PINCTRL_HW0 | GPIO_PORT0 | GPIO_PIN8) +#define GPIO_DSD_CGPWMN_1 (GPIO_OUTPUT_ALT1 | GPIO_PORT1 | GPIO_PIN0) +#define GPIO_DSD_CGPWMN_2 (GPIO_OUTPUT_ALT2 | GPIO_PORT5 | GPIO_PIN0) +#define GPIO_DSD_CGPWMN_3 (GPIO_OUTPUT_ALT3 | GPIO_PORT2 | GPIO_PIN0) +#define GPIO_DSD_CGPWMP_1 (GPIO_OUTPUT_ALT1 | GPIO_PORT1 | GPIO_PIN1) +#define GPIO_DSD_CGPWMP_2 (GPIO_OUTPUT_ALT2 | GPIO_PORT5 | GPIO_PIN1) +#define GPIO_DSD_CGPWMP_3 (GPIO_OUTPUT_ALT3 | GPIO_PORT2 | GPIO_PIN1) +#define GPIO_DSD_DIN0A (GPIO_INPUT | GPIO_PORT0 | GPIO_PIN8) +#define GPIO_DSD_DIN0B (GPIO_INPUT | GPIO_PORT2 | GPIO_PIN7) +#define GPIO_DSD_DIN1A (GPIO_INPUT | GPIO_PORT0 | GPIO_PIN7) +#define GPIO_DSD_DIN1B (GPIO_INPUT | GPIO_PORT2 | GPIO_PIN6) +#define GPIO_DSD_DIN2A (GPIO_INPUT | GPIO_PORT1 | GPIO_PIN6) +#define GPIO_DSD_DIN2B (GPIO_INPUT | GPIO_PORT1 | GPIO_PIN5) +#define GPIO_DSD_DIN3A (GPIO_INPUT | GPIO_PORT6 | GPIO_PIN5) +#define GPIO_DSD_DIN3B (GPIO_INPUT | GPIO_PORT3 | GPIO_PIN3) +#define GPIO_DSD_MCLK0 (GPIO_OUTPUT_ALT3 | GPIO_PORT4 | GPIO_PIN1) +#define GPIO_DSD_MCLK0A (GPIO_INPUT | GPIO_PORT1 | GPIO_PIN9) +#define GPIO_DSD_MCLK0B (GPIO_INPUT | GPIO_PORT4 | GPIO_PIN1) +#define GPIO_DSD_MCLK1_1 (GPIO_OUTPUT_ALT3 | GPIO_PORT1 | GPIO_PIN8) +#define GPIO_DSD_MCLK1_2 (GPIO_OUTPUT_ALT3 | GPIO_PORT4 | GPIO_PIN0) +#define GPIO_DSD_MCLK1A (GPIO_INPUT | GPIO_PORT1 | GPIO_PIN8) +#define GPIO_DSD_MCLK1B (GPIO_INPUT | GPIO_PORT4 | GPIO_PIN0) +#define GPIO_DSD_MCLK2_1 (GPIO_OUTPUT_ALT2 | GPIO_PORT1 | GPIO_PIN15) +#define GPIO_DSD_MCLK2_2 (GPIO_OUTPUT_ALT3 | GPIO_PORT1 | GPIO_PIN7) +#define GPIO_DSD_MCLK2A (GPIO_INPUT | GPIO_PORT1 | GPIO_PIN7) +#define GPIO_DSD_MCLK2B (GPIO_INPUT | GPIO_PORT1 | GPIO_PIN15) +#define GPIO_DSD_MCLK3_1 (GPIO_OUTPUT_ALT3 | GPIO_PORT6 | GPIO_PIN6) +#define GPIO_DSD_MCLK3_2 (GPIO_OUTPUT_ALT4 | GPIO_PORT3 | GPIO_PIN4) +#define GPIO_DSD_MCLK3A (GPIO_INPUT | GPIO_PORT6 | GPIO_PIN6) +#define GPIO_DSD_MCLK3B (GPIO_INPUT | GPIO_PORT3 | GPIO_PIN4) + +#define GPIO_EBU_A16 (GPIO_OUTPUT | GPIO_PINCTRL_HW1 | GPIO_PORT6 | GPIO_PIN0) +#define GPIO_EBU_A17 (GPIO_OUTPUT | GPIO_PINCTRL_HW1 | GPIO_PORT6 | GPIO_PIN1) +#define GPIO_EBU_A18 (GPIO_OUTPUT | GPIO_PINCTRL_HW1 | GPIO_PORT6 | GPIO_PIN2) +#define GPIO_EBU_A19 (GPIO_OUTPUT | GPIO_PINCTRL_HW1 | GPIO_PORT6 | GPIO_PIN4) +#define GPIO_EBU_A20 (GPIO_OUTPUT | GPIO_PINCTRL_HW1 | GPIO_PORT5 | GPIO_PIN3) +#define GPIO_EBU_A21 (GPIO_OUTPUT | GPIO_PINCTRL_HW1 | GPIO_PORT5 | GPIO_PIN4) +#define GPIO_EBU_A22 (GPIO_OUTPUT | GPIO_PINCTRL_HW1 | GPIO_PORT5 | GPIO_PIN5) +#define GPIO_EBU_A23 (GPIO_OUTPUT | GPIO_PINCTRL_HW1 | GPIO_PORT5 | GPIO_PIN6) +#define GPIO_EBU_AD0 (GPIO_OUTPUT | GPIO_PINCTRL_HW1 | GPIO_PORT0 | GPIO_PIN2) +#define GPIO_EBU_AD1 (GPIO_OUTPUT | GPIO_PINCTRL_HW1 | GPIO_PORT0 | GPIO_PIN3) +#define GPIO_EBU_AD2 (GPIO_OUTPUT | GPIO_PINCTRL_HW1 | GPIO_PORT0 | GPIO_PIN4) +#define GPIO_EBU_AD3 (GPIO_OUTPUT | GPIO_PINCTRL_HW1 | GPIO_PORT0 | GPIO_PIN5) +#define GPIO_EBU_AD4 (GPIO_OUTPUT | GPIO_PINCTRL_HW1 | GPIO_PORT3 | GPIO_PIN5) +#define GPIO_EBU_AD5 (GPIO_OUTPUT | GPIO_PINCTRL_HW1 | GPIO_PORT3 | GPIO_PIN6) +#define GPIO_EBU_AD6 (GPIO_OUTPUT | GPIO_PINCTRL_HW1 | GPIO_PORT0 | GPIO_PIN7) +#define GPIO_EBU_AD7 (GPIO_OUTPUT | GPIO_PINCTRL_HW1 | GPIO_PORT0 | GPIO_PIN8) +#define GPIO_EBU_AD8 (GPIO_OUTPUT | GPIO_PINCTRL_HW1 | GPIO_PORT4 | GPIO_PIN0) +#define GPIO_EBU_AD9 (GPIO_OUTPUT | GPIO_PINCTRL_HW1 | GPIO_PORT4 | GPIO_PIN1) +#define GPIO_EBU_AD10 (GPIO_OUTPUT | GPIO_PINCTRL_HW1 | GPIO_PORT1 | GPIO_PIN6) +#define GPIO_EBU_AD11 (GPIO_OUTPUT | GPIO_PINCTRL_HW1 | GPIO_PORT1 | GPIO_PIN7) +#define GPIO_EBU_AD12 (GPIO_OUTPUT | GPIO_PINCTRL_HW1 | GPIO_PORT1 | GPIO_PIN8) +#define GPIO_EBU_AD13 (GPIO_OUTPUT | GPIO_PINCTRL_HW1 | GPIO_PORT1 | GPIO_PIN9) +#define GPIO_EBU_AD14 (GPIO_OUTPUT | GPIO_PINCTRL_HW1 | GPIO_PORT1 | GPIO_PIN2) +#define GPIO_EBU_AD15 (GPIO_OUTPUT | GPIO_PINCTRL_HW1 | GPIO_PORT1 | GPIO_PIN3) +#define GPIO_EBU_AD16 (GPIO_OUTPUT | GPIO_PINCTRL_HW1 | GPIO_PORT1 | GPIO_PIN12) +#define GPIO_EBU_AD17 (GPIO_OUTPUT | GPIO_PINCTRL_HW1 | GPIO_PORT1 | GPIO_PIN13) +#define GPIO_EBU_AD18 (GPIO_OUTPUT | GPIO_PINCTRL_HW1 | GPIO_PORT1 | GPIO_PIN14) +#define GPIO_EBU_AD19 (GPIO_OUTPUT | GPIO_PINCTRL_HW1 | GPIO_PORT1 | GPIO_PIN15) +#define GPIO_EBU_AD20 (GPIO_OUTPUT | GPIO_PINCTRL_HW1 | GPIO_PORT2 | GPIO_PIN0) +#define GPIO_EBU_AD21 (GPIO_OUTPUT | GPIO_PINCTRL_HW1 | GPIO_PORT2 | GPIO_PIN1) +#define GPIO_EBU_AD22 (GPIO_OUTPUT | GPIO_PINCTRL_HW1 | GPIO_PORT2 | GPIO_PIN2) +#define GPIO_EBU_AD23 (GPIO_OUTPUT | GPIO_PINCTRL_HW1 | GPIO_PORT2 | GPIO_PIN3) +#define GPIO_EBU_AD24 (GPIO_OUTPUT | GPIO_PINCTRL_HW1 | GPIO_PORT2 | GPIO_PIN4) +#define GPIO_EBU_AD25 (GPIO_OUTPUT | GPIO_PINCTRL_HW1 | GPIO_PORT2 | GPIO_PIN5) +#define GPIO_EBU_AD26 (GPIO_OUTPUT | GPIO_PINCTRL_HW1 | GPIO_PORT2 | GPIO_PIN8) +#define GPIO_EBU_AD27 (GPIO_OUTPUT | GPIO_PINCTRL_HW1 | GPIO_PORT2 | GPIO_PIN9) +#define GPIO_EBU_AD28 (GPIO_OUTPUT | GPIO_PINCTRL_HW1 | GPIO_PORT2 | GPIO_PIN10) +#define GPIO_EBU_AD29 (GPIO_OUTPUT | GPIO_PINCTRL_HW1 | GPIO_PORT2 | GPIO_PIN11) +#define GPIO_EBU_AD30 (GPIO_OUTPUT | GPIO_PINCTRL_HW1 | GPIO_PORT2 | GPIO_PIN12) +#define GPIO_EBU_AD31 (GPIO_OUTPUT | GPIO_PINCTRL_HW1 | GPIO_PORT2 | GPIO_PIN13) +#define GPIO_EBU_ADV (GPIO_OUTPUT | GPIO_PINCTRL_HW1 | GPIO_PORT0 | GPIO_PIN6) +#define GPIO_EBU_BC0 (GPIO_OUTPUT | GPIO_PINCTRL_HW1 | GPIO_PORT2 | GPIO_PIN14) +#define GPIO_EBU_BC1 (GPIO_OUTPUT | GPIO_PINCTRL_HW1 | GPIO_PORT2 | GPIO_PIN15) +#define GPIO_EBU_BC2 (GPIO_OUTPUT | GPIO_PINCTRL_HW1 | GPIO_PORT6 | GPIO_PIN5) +#define GPIO_EBU_BC3 (GPIO_OUTPUT | GPIO_PINCTRL_HW1 | GPIO_PORT6 | GPIO_PIN6) +#define GPIO_EBU_BFCLKI (GPIO_INPUT | GPIO_PORT5 | GPIO_PIN6) +#define GPIO_EBU_BFCLKO_1 (GPIO_OUTPUT | GPIO_PINCTRL_HW0 | GPIO_PORT5 | GPIO_PIN6) +#define GPIO_EBU_BFCLKO_2 (GPIO_OUTPUT | GPIO_PINCTRL_HW0 | GPIO_PORT5 | GPIO_PIN9) +#define GPIO_EBU_BREQ (GPIO_OUTPUT | GPIO_PINCTRL_HW1 | GPIO_PORT0 | GPIO_PIN11) +#define GPIO_EBU_CAS (GPIO_OUTPUT | GPIO_PINCTRL_HW0 | GPIO_PORT5 | GPIO_PIN5) +#define GPIO_EBU_CKE (GPIO_OUTPUT | GPIO_PINCTRL_HW0 | GPIO_PORT5 | GPIO_PIN3) +#define GPIO_EBU_CS0 (GPIO_OUTPUT | GPIO_PINCTRL_HW1 | GPIO_PORT3 | GPIO_PIN2) +#define GPIO_EBU_CS1 (GPIO_OUTPUT | GPIO_PINCTRL_HW1 | GPIO_PORT0 | GPIO_PIN9) +#define GPIO_EBU_CS2 (GPIO_OUTPUT | GPIO_PINCTRL_HW1 | GPIO_PORT5 | GPIO_PIN8) +#define GPIO_EBU_CS3 (GPIO_OUTPUT | GPIO_PINCTRL_HW1 | GPIO_PORT5 | GPIO_PIN9) +#define GPIO_EBU_D0 (GPIO_INPUT | GPIO_PINCTRL_HW1 | GPIO_PORT0 | GPIO_PIN2) +#define GPIO_EBU_D1 (GPIO_INPUT | GPIO_PINCTRL_HW1 | GPIO_PORT0 | GPIO_PIN3) +#define GPIO_EBU_D2 (GPIO_INPUT | GPIO_PINCTRL_HW1 | GPIO_PORT0 | GPIO_PIN4) +#define GPIO_EBU_D3 (GPIO_INPUT | GPIO_PINCTRL_HW1 | GPIO_PORT0 | GPIO_PIN5) +#define GPIO_EBU_D4 (GPIO_INPUT | GPIO_PINCTRL_HW1 | GPIO_PORT3 | GPIO_PIN5) +#define GPIO_EBU_D5 (GPIO_INPUT | GPIO_PINCTRL_HW1 | GPIO_PORT3 | GPIO_PIN6) +#define GPIO_EBU_D6 (GPIO_INPUT | GPIO_PINCTRL_HW1 | GPIO_PORT0 | GPIO_PIN7) +#define GPIO_EBU_D7 (GPIO_INPUT | GPIO_PINCTRL_HW1 | GPIO_PORT0 | GPIO_PIN8) +#define GPIO_EBU_D8 (GPIO_INPUT | GPIO_PINCTRL_HW1 | GPIO_PORT4 | GPIO_PIN0) +#define GPIO_EBU_D9 (GPIO_INPUT | GPIO_PINCTRL_HW1 | GPIO_PORT4 | GPIO_PIN1) +#define GPIO_EBU_D10 (GPIO_INPUT | GPIO_PINCTRL_HW1 | GPIO_PORT1 | GPIO_PIN6) +#define GPIO_EBU_D11 (GPIO_INPUT | GPIO_PINCTRL_HW1 | GPIO_PORT1 | GPIO_PIN7) +#define GPIO_EBU_D12 (GPIO_INPUT | GPIO_PINCTRL_HW1 | GPIO_PORT1 | GPIO_PIN8) +#define GPIO_EBU_D13 (GPIO_INPUT | GPIO_PINCTRL_HW1 | GPIO_PORT1 | GPIO_PIN9) +#define GPIO_EBU_D14 (GPIO_INPUT | GPIO_PINCTRL_HW1 | GPIO_PORT1 | GPIO_PIN2) +#define GPIO_EBU_D15 (GPIO_INPUT | GPIO_PINCTRL_HW1 | GPIO_PORT1 | GPIO_PIN3) +#define GPIO_EBU_D16 (GPIO_INPUT | GPIO_PINCTRL_HW1 | GPIO_PORT1 | GPIO_PIN12) +#define GPIO_EBU_D17 (GPIO_INPUT | GPIO_PINCTRL_HW1 | GPIO_PORT1 | GPIO_PIN13) +#define GPIO_EBU_D18 (GPIO_INPUT | GPIO_PINCTRL_HW1 | GPIO_PORT1 | GPIO_PIN14) +#define GPIO_EBU_D19 (GPIO_INPUT | GPIO_PINCTRL_HW1 | GPIO_PORT1 | GPIO_PIN15) +#define GPIO_EBU_D20 (GPIO_INPUT | GPIO_PINCTRL_HW1 | GPIO_PORT2 | GPIO_PIN0) +#define GPIO_EBU_D21 (GPIO_INPUT | GPIO_PINCTRL_HW1 | GPIO_PORT2 | GPIO_PIN1) +#define GPIO_EBU_D22 (GPIO_INPUT | GPIO_PINCTRL_HW1 | GPIO_PORT2 | GPIO_PIN2) +#define GPIO_EBU_D23 (GPIO_INPUT | GPIO_PINCTRL_HW1 | GPIO_PORT2 | GPIO_PIN3) +#define GPIO_EBU_D24 (GPIO_INPUT | GPIO_PINCTRL_HW1 | GPIO_PORT2 | GPIO_PIN4) +#define GPIO_EBU_D25 (GPIO_INPUT | GPIO_PINCTRL_HW1 | GPIO_PORT2 | GPIO_PIN5) +#define GPIO_EBU_D26 (GPIO_INPUT | GPIO_PINCTRL_HW1 | GPIO_PORT2 | GPIO_PIN8) +#define GPIO_EBU_D27 (GPIO_INPUT | GPIO_PINCTRL_HW1 | GPIO_PORT2 | GPIO_PIN9) +#define GPIO_EBU_D28 (GPIO_INPUT | GPIO_PINCTRL_HW1 | GPIO_PORT2 | GPIO_PIN10) +#define GPIO_EBU_D29 (GPIO_INPUT | GPIO_PINCTRL_HW1 | GPIO_PORT2 | GPIO_PIN11) +#define GPIO_EBU_D30 (GPIO_INPUT | GPIO_PINCTRL_HW1 | GPIO_PORT2 | GPIO_PIN12) +#define GPIO_EBU_D31 (GPIO_INPUT | GPIO_PINCTRL_HW1 | GPIO_PORT2 | GPIO_PIN13) +#define GPIO_EBU_HLDA_1 (GPIO_INPUT | GPIO_PINCTRL_HW1 | GPIO_PORT0 | GPIO_PIN12) +#define GPIO_EBU_HLDA_2 (GPIO_OUTPUT | GPIO_PINCTRL_HW1 | GPIO_PORT0 | GPIO_PIN12) +#define GPIO_EBU_HOLD (GPIO_INPUT | GPIO_PINCTRL_HW1 | GPIO_PORT3 | GPIO_PIN4) +#define GPIO_EBU_RAS (GPIO_OUTPUT | GPIO_PINCTRL_HW0 | GPIO_PORT5 | GPIO_PIN4) +#define GPIO_EBU_RD (GPIO_OUTPUT | GPIO_PINCTRL_HW1 | GPIO_PORT3 | GPIO_PIN0) +#define GPIO_EBU_RDWR (GPIO_OUTPUT | GPIO_PINCTRL_HW1 | GPIO_PORT3 | GPIO_PIN1) +#define GPIO_EBU_SDCLKI (GPIO_INPUT | GPIO_PORT6 | GPIO_PIN4) +#define GPIO_EBU_SDCLKO_1 (GPIO_OUTPUT | GPIO_PINCTRL_HW0 | GPIO_PORT5 | GPIO_PIN8) +#define GPIO_EBU_SDCLKO_2 (GPIO_OUTPUT | GPIO_PINCTRL_HW0 | GPIO_PORT6 | GPIO_PIN4) +#define GPIO_EBU_WAIT (GPIO_INPUT | GPIO_PINCTRL_HW1 | GPIO_PORT3 | GPIO_PIN3) +#define GPIO_ERU0_0A0 (GPIO_INPUT | GPIO_PORT0 | GPIO_PIN1) +#define GPIO_ERU0_0A1 (GPIO_INPUT | GPIO_PORT3 | GPIO_PIN2) +#define GPIO_ERU0_0A2 (GPIO_INPUT | GPIO_PORT2 | GPIO_PIN5) +#define GPIO_ERU0_0B0 (GPIO_INPUT | GPIO_PORT0 | GPIO_PIN0) +#define GPIO_ERU0_0B1 (GPIO_INPUT | GPIO_PORT3 | GPIO_PIN1) +#define GPIO_ERU0_0B2 (GPIO_INPUT | GPIO_PORT2 | GPIO_PIN4) +#define GPIO_ERU0_0B3 (GPIO_INPUT | GPIO_PORT2 | GPIO_PIN0) +#define GPIO_ERU0_1A0 (GPIO_INPUT | GPIO_PORT0 | GPIO_PIN10) +#define GPIO_ERU0_1A2 (GPIO_INPUT | GPIO_PORT2 | GPIO_PIN3) +#define GPIO_ERU0_1B0 (GPIO_INPUT | GPIO_PORT0 | GPIO_PIN9) +#define GPIO_ERU0_1B2 (GPIO_INPUT | GPIO_PORT2 | GPIO_PIN2) +#define GPIO_ERU0_1B3 (GPIO_INPUT | GPIO_PORT2 | GPIO_PIN6) +#define GPIO_ERU0_2A0 (GPIO_INPUT | GPIO_PORT1 | GPIO_PIN5) +#define GPIO_ERU0_2A1 (GPIO_INPUT | GPIO_PORT0 | GPIO_PIN8) +#define GPIO_ERU0_2A2 (GPIO_INPUT | GPIO_PORT0 | GPIO_PIN13) +#define GPIO_ERU0_2B0 (GPIO_INPUT | GPIO_PORT1 | GPIO_PIN4) +#define GPIO_ERU0_2B1 (GPIO_INPUT | GPIO_PORT0 | GPIO_PIN7) +#define GPIO_ERU0_2B2 (GPIO_INPUT | GPIO_PORT0 | GPIO_PIN12) +#define GPIO_ERU0_2B3 (GPIO_INPUT | GPIO_PORT0 | GPIO_PIN4) +#define GPIO_ERU0_3A0 (GPIO_INPUT | GPIO_PORT1 | GPIO_PIN1) +#define GPIO_ERU0_3A1 (GPIO_INPUT | GPIO_PORT3 | GPIO_PIN6) +#define GPIO_ERU0_3A2 (GPIO_INPUT | GPIO_PORT0 | GPIO_PIN11) +#define GPIO_ERU0_3B0 (GPIO_INPUT | GPIO_PORT1 | GPIO_PIN0) +#define GPIO_ERU0_3B1 (GPIO_INPUT | GPIO_PORT3 | GPIO_PIN5) +#define GPIO_ERU0_3B2 (GPIO_INPUT | GPIO_PORT0 | GPIO_PIN6) +#define GPIO_ERU0_3B3 (GPIO_INPUT | GPIO_PORT0 | GPIO_PIN2) +#define GPIO_ERU1_0A0 (GPIO_INPUT | GPIO_PORT1 | GPIO_PIN5) +#define GPIO_ERU1_0B0 (GPIO_INPUT | GPIO_PORT2 | GPIO_PIN1) +#define GPIO_ERU1_1A0 (GPIO_INPUT | GPIO_PORT1 | GPIO_PIN15) +#define GPIO_ERU1_1B0 (GPIO_INPUT | GPIO_PORT2 | GPIO_PIN7) +#define GPIO_ERU1_2A0 (GPIO_INPUT | GPIO_PORT1 | GPIO_PIN3) +#define GPIO_ERU1_2B0 (GPIO_INPUT | GPIO_PORT1 | GPIO_PIN2) +#define GPIO_ERU1_3A0 (GPIO_INPUT | GPIO_PORT0 | GPIO_PIN5) +#define GPIO_ERU1_3B0 (GPIO_INPUT | GPIO_PORT0 | GPIO_PIN3) +#define GPIO_ERU1_PDOUT0 (GPIO_OUTPUT_ALT4 | GPIO_PORT1 | GPIO_PIN3) +#define GPIO_ERU1_PDOUT1 (GPIO_OUTPUT_ALT4 | GPIO_PORT1 | GPIO_PIN2) +#define GPIO_ERU1_PDOUT2 (GPIO_OUTPUT_ALT4 | GPIO_PORT1 | GPIO_PIN1) +#define GPIO_ERU1_PDOUT3 (GPIO_OUTPUT_ALT4 | GPIO_PORT1 | GPIO_PIN0) + +#define GPIO_ETH0_CLKRMIIA (GPIO_INPUT | GPIO_PORT2 | GPIO_PIN1) +#define GPIO_ETH0_CLKRMIIB (GPIO_INPUT | GPIO_PORT0 | GPIO_PIN0) +#define GPIO_ETH0_CLKRMIIC (GPIO_INPUT | GPIO_PORT15 | GPIO_PIN8) +#define GPIO_ETH0_CLKRMIID (GPIO_INPUT | GPIO_PORT6 | GPIO_PIN5) +#define GPIO_ETH0_CLKRXA (GPIO_INPUT | GPIO_PORT2 | GPIO_PIN1) +#define GPIO_ETH0_CLKRXB (GPIO_INPUT | GPIO_PORT0 | GPIO_PIN0) +#define GPIO_ETH0_CLKRXC (GPIO_INPUT | GPIO_PORT15 | GPIO_PIN8) +#define GPIO_ETH0_CLKRXD (GPIO_INPUT | GPIO_PORT6 | GPIO_PIN5) +#define GPIO_ETH0_CLKTXA (GPIO_INPUT | GPIO_PORT5 | GPIO_PIN10) +#define GPIO_ETH0_CLKTXB (GPIO_INPUT | GPIO_PORT6 | GPIO_PIN6) +#define GPIO_ETH0_COLA (GPIO_INPUT | GPIO_PORT2 | GPIO_PIN15) +#define GPIO_ETH0_COLD (GPIO_INPUT | GPIO_PORT5 | GPIO_PIN5) +#define GPIO_ETH0_CRSA (GPIO_INPUT | GPIO_PORT5 | GPIO_PIN11) +#define GPIO_ETH0_CRSD (GPIO_INPUT | GPIO_PORT5 | GPIO_PIN4) +#define GPIO_ETH0_CRSDVA_1 (GPIO_INPUT | GPIO_PORT2 | GPIO_PIN5) +#define GPIO_ETH0_CRSDVA_2 (GPIO_INPUT | GPIO_PORT2 | GPIO_PIN5) +#define GPIO_ETH0_CRSDVB (GPIO_INPUT | GPIO_PORT0 | GPIO_PIN1) +#define GPIO_ETH0_CRSDVC (GPIO_INPUT | GPIO_PORT15 | GPIO_PIN9) +#define GPIO_ETH0_CRSDVD (GPIO_INPUT | GPIO_PORT5 | GPIO_PIN2) +#define GPIO_ETH0_MDC_1 (GPIO_OUTPUT_ALT1 | GPIO_PORT0 | GPIO_PIN10) +#define GPIO_ETH0_MDC_2 (GPIO_OUTPUT_ALT1 | GPIO_PORT1 | GPIO_PIN10) +#define GPIO_ETH0_MDC_3 (GPIO_OUTPUT_ALT1 | GPIO_PORT2 | GPIO_PIN7) +#define GPIO_ETH0_MDIA (GPIO_INPUT | GPIO_PINCTRL_HW0 | GPIO_PORT0 | GPIO_PIN9) +#define GPIO_ETH0_MDIB (GPIO_INPUT | GPIO_PINCTRL_HW0 | GPIO_PORT2 | GPIO_PIN0) +#define GPIO_ETH0_MDIC (GPIO_INPUT | GPIO_PINCTRL_HW0 | GPIO_PORT1 | GPIO_PIN11) +#define GPIO_ETH0_MDO_1 (GPIO_OUTPUT | GPIO_PINCTRL_HW0 | GPIO_PORT0 | GPIO_PIN9) +#define GPIO_ETH0_MDO_2 (GPIO_OUTPUT | GPIO_PINCTRL_HW0 | GPIO_PORT1 | GPIO_PIN11) +#define GPIO_ETH0_MDO_3 (GPIO_OUTPUT | GPIO_PINCTRL_HW0 | GPIO_PORT2 | GPIO_PIN0) +#define GPIO_ETH0_RXD0A (GPIO_INPUT | GPIO_PORT2 | GPIO_PIN2) +#define GPIO_ETH0_RXD0B (GPIO_INPUT | GPIO_PORT0 | GPIO_PIN2) +#define GPIO_ETH0_RXD0C (GPIO_INPUT | GPIO_PORT14 | GPIO_PIN8) +#define GPIO_ETH0_RXD0D (GPIO_INPUT | GPIO_PORT5 | GPIO_PIN0) +#define GPIO_ETH0_RXD1A (GPIO_INPUT | GPIO_PORT2 | GPIO_PIN3) +#define GPIO_ETH0_RXD1B (GPIO_INPUT | GPIO_PORT0 | GPIO_PIN3) +#define GPIO_ETH0_RXD1C (GPIO_INPUT | GPIO_PORT14 | GPIO_PIN9) +#define GPIO_ETH0_RXD1D (GPIO_INPUT | GPIO_PORT5 | GPIO_PIN1) +#define GPIO_ETH0_RXD2A (GPIO_INPUT | GPIO_PORT5 | GPIO_PIN8) +#define GPIO_ETH0_RXD2B (GPIO_INPUT | GPIO_PORT6 | GPIO_PIN4) +#define GPIO_ETH0_RXD3A (GPIO_INPUT | GPIO_PORT5 | GPIO_PIN9) +#define GPIO_ETH0_RXD3B (GPIO_INPUT | GPIO_PORT6 | GPIO_PIN3) +#define GPIO_ETH0_RXDVB (GPIO_INPUT | GPIO_PORT0 | GPIO_PIN1) +#define GPIO_ETH0_RXDVC (GPIO_INPUT | GPIO_PORT15 | GPIO_PIN9) +#define GPIO_ETH0_RXDVD (GPIO_INPUT | GPIO_PORT5 | GPIO_PIN2) +#define GPIO_ETH0_RXERA (GPIO_INPUT | GPIO_PORT2 | GPIO_PIN4) +#define GPIO_ETH0_RXERB (GPIO_INPUT | GPIO_PORT0 | GPIO_PIN11) +#define GPIO_ETH0_RXERD (GPIO_INPUT | GPIO_PORT5 | GPIO_PIN3) +#define GPIO_ETH0_TXD0_1 (GPIO_OUTPUT_ALT1 | GPIO_PORT0 | GPIO_PIN5) +#define GPIO_ETH0_TXD0_2 (GPIO_OUTPUT_ALT1 | GPIO_PORT1 | GPIO_PIN13) +#define GPIO_ETH0_TXD0_3 (GPIO_OUTPUT_ALT1 | GPIO_PORT2 | GPIO_PIN8) +#define GPIO_ETH0_TXD0_4 (GPIO_OUTPUT_ALT4 | GPIO_PORT2 | GPIO_PIN12) +#define GPIO_ETH0_TXD1_1 (GPIO_OUTPUT_ALT1 | GPIO_PORT0 | GPIO_PIN6) +#define GPIO_ETH0_TXD1_2 (GPIO_OUTPUT_ALT1 | GPIO_PORT1 | GPIO_PIN14) +#define GPIO_ETH0_TXD1_3 (GPIO_OUTPUT_ALT1 | GPIO_PORT2 | GPIO_PIN9) +#define GPIO_ETH0_TXD1_4 (GPIO_OUTPUT_ALT4 | GPIO_PORT2 | GPIO_PIN13) +#define GPIO_ETH0_TXD2_1 (GPIO_OUTPUT_ALT1 | GPIO_PORT2 | GPIO_PIN12) +#define GPIO_ETH0_TXD2_2 (GPIO_OUTPUT_ALT1 | GPIO_PORT6 | GPIO_PIN0) +#define GPIO_ETH0_TXD3_1 (GPIO_OUTPUT_ALT1 | GPIO_PORT2 | GPIO_PIN13) +#define GPIO_ETH0_TXD3_2 (GPIO_OUTPUT_ALT1 | GPIO_PORT6 | GPIO_PIN1) +#define GPIO_ETH0_TXEN_1 (GPIO_OUTPUT_ALT1 | GPIO_PORT0 | GPIO_PIN4) +#define GPIO_ETH0_TXEN_2 (GPIO_OUTPUT_ALT1 | GPIO_PORT1 | GPIO_PIN12) +#define GPIO_ETH0_TXEN_3 (GPIO_OUTPUT_ALT1 | GPIO_PORT2 | GPIO_PIN5) +#define GPIO_ETH0_TXEN_4 (GPIO_OUTPUT_ALT4 | GPIO_PORT5 | GPIO_PIN9) +#define GPIO_ETH0_TXER_1 (GPIO_OUTPUT_ALT1 | GPIO_PORT2 | GPIO_PIN11) +#define GPIO_ETH0_TXER_2 (GPIO_OUTPUT_ALT1 | GPIO_PORT6 | GPIO_PIN2) + +#define GPIO_G0ORC6 (GPIO_INPUT | GPIO_PORT14 | GPIO_PIN6) +#define GPIO_G0ORC7 (GPIO_INPUT | GPIO_PORT14 | GPIO_PIN7) +#define GPIO_G1ORC6 (GPIO_INPUT | GPIO_PORT14 | GPIO_PIN14) +#define GPIO_G1ORC7 (GPIO_INPUT | GPIO_PORT14 | GPIO_PIN15) + +#define GPIO_LEDTS0_COL0_1 (GPIO_OUTPUT_ALT4 | GPIO_PORT0 | GPIO_PIN9) +#define GPIO_LEDTS0_COL0_2 (GPIO_OUTPUT_ALT4 | GPIO_PORT2 | GPIO_PIN1) +#define GPIO_LEDTS0_COL1_1 (GPIO_OUTPUT_ALT4 | GPIO_PORT0 | GPIO_PIN10) +#define GPIO_LEDTS0_COL1_2 (GPIO_OUTPUT_ALT4 | GPIO_PORT2 | GPIO_PIN0) +#define GPIO_LEDTS0_COL2_1 (GPIO_OUTPUT_ALT4 | GPIO_PORT0 | GPIO_PIN0) +#define GPIO_LEDTS0_COL2_2 (GPIO_OUTPUT_ALT4 | GPIO_PORT2 | GPIO_PIN7) +#define GPIO_LEDTS0_COL3_1 (GPIO_OUTPUT_ALT4 | GPIO_PORT0 | GPIO_PIN1) +#define GPIO_LEDTS0_COL3_2 (GPIO_OUTPUT_ALT4 | GPIO_PORT2 | GPIO_PIN6) +#define GPIO_LEDTS0_COLA_1 (GPIO_OUTPUT_ALT4 | GPIO_PORT3 | GPIO_PIN2) +#define GPIO_LEDTS0_COLA_2 (GPIO_OUTPUT_ALT4 | GPIO_PORT5 | GPIO_PIN7) +#define GPIO_LEDTS0_EXTENDED0 (GPIO_OUTPUT | GPIO_PINCTRL_HW0 | GPIO_PORT2 | GPIO_PIN2) +#define GPIO_LEDTS0_EXTENDED1 (GPIO_OUTPUT | GPIO_PINCTRL_HW0 | GPIO_PORT2 | GPIO_PIN3) +#define GPIO_LEDTS0_EXTENDED2 (GPIO_OUTPUT | GPIO_PINCTRL_HW0 | GPIO_PORT2 | GPIO_PIN4) +#define GPIO_LEDTS0_EXTENDED3 (GPIO_OUTPUT | GPIO_PINCTRL_HW0 | GPIO_PORT2 | GPIO_PIN5) +#define GPIO_LEDTS0_EXTENDED4 (GPIO_OUTPUT | GPIO_PINCTRL_HW0 | GPIO_PORT2 | GPIO_PIN8) +#define GPIO_LEDTS0_EXTENDED5 (GPIO_OUTPUT | GPIO_PINCTRL_HW0 | GPIO_PORT2 | GPIO_PIN9) +#define GPIO_LEDTS0_EXTENDED6 (GPIO_OUTPUT | GPIO_PINCTRL_HW0 | GPIO_PORT2 | GPIO_PIN15) +#define GPIO_LEDTS0_EXTENDED7 (GPIO_OUTPUT | GPIO_PINCTRL_HW0 | GPIO_PORT5 | GPIO_PIN10) +#define GPIO_LEDTS0_LINE0_1 (GPIO_OUTPUT_ALT4 | GPIO_PORT2 | GPIO_PIN2) +#define GPIO_LEDTS0_LINE0_2 (GPIO_OUTPUT_ALT4 | GPIO_PORT3 | GPIO_PIN7) +#define GPIO_LEDTS0_LINE1_1 (GPIO_OUTPUT_ALT4 | GPIO_PORT2 | GPIO_PIN3) +#define GPIO_LEDTS0_LINE1_2 (GPIO_OUTPUT_ALT4 | GPIO_PORT3 | GPIO_PIN8) +#define GPIO_LEDTS0_LINE2_1 (GPIO_OUTPUT_ALT4 | GPIO_PORT2 | GPIO_PIN4) +#define GPIO_LEDTS0_LINE2_2 (GPIO_OUTPUT_ALT4 | GPIO_PORT3 | GPIO_PIN9) +#define GPIO_LEDTS0_LINE3_1 (GPIO_OUTPUT_ALT4 | GPIO_PORT2 | GPIO_PIN5) +#define GPIO_LEDTS0_LINE3_2 (GPIO_OUTPUT_ALT4 | GPIO_PORT3 | GPIO_PIN10) +#define GPIO_LEDTS0_LINE4_1 (GPIO_OUTPUT_ALT4 | GPIO_PORT2 | GPIO_PIN8) +#define GPIO_LEDTS0_LINE4_2 (GPIO_OUTPUT_ALT4 | GPIO_PORT3 | GPIO_PIN11) +#define GPIO_LEDTS0_LINE5_1 (GPIO_OUTPUT_ALT4 | GPIO_PORT2 | GPIO_PIN9) +#define GPIO_LEDTS0_LINE5_2 (GPIO_OUTPUT_ALT4 | GPIO_PORT3 | GPIO_PIN12) +#define GPIO_LEDTS0_LINE6_1 (GPIO_OUTPUT_ALT4 | GPIO_PORT2 | GPIO_PIN15) +#define GPIO_LEDTS0_LINE6_2 (GPIO_OUTPUT_ALT4 | GPIO_PORT3 | GPIO_PIN13) +#define GPIO_LEDTS0_LINE7 (GPIO_OUTPUT_ALT4 | GPIO_PORT5 | GPIO_PIN10) +#define GPIO_LEDTS0_TSIN0A (GPIO_INPUT | GPIO_PINCTRL_HW0 | GPIO_PORT2 | GPIO_PIN2) +#define GPIO_LEDTS0_TSIN1A (GPIO_INPUT | GPIO_PINCTRL_HW0 | GPIO_PORT2 | GPIO_PIN3) +#define GPIO_LEDTS0_TSIN2A (GPIO_INPUT | GPIO_PINCTRL_HW0 | GPIO_PORT2 | GPIO_PIN4) +#define GPIO_LEDTS0_TSIN3A (GPIO_INPUT | GPIO_PINCTRL_HW0 | GPIO_PORT2 | GPIO_PIN5) +#define GPIO_LEDTS0_TSIN4A (GPIO_INPUT | GPIO_PINCTRL_HW0 | GPIO_PORT2 | GPIO_PIN8) +#define GPIO_LEDTS0_TSIN5A (GPIO_INPUT | GPIO_PINCTRL_HW0 | GPIO_PORT2 | GPIO_PIN9) +#define GPIO_LEDTS0_TSIN6A (GPIO_INPUT | GPIO_PINCTRL_HW0 | GPIO_PORT2 | GPIO_PIN15) +#define GPIO_LEDTS0_TSIN7A (GPIO_INPUT | GPIO_PINCTRL_HW0 | GPIO_PORT5 | GPIO_PIN10) + +#define GPIO_POSIF0_IN0A (GPIO_INPUT | GPIO_PORT1 | GPIO_PIN3) +#define GPIO_POSIF0_IN0B (GPIO_INPUT | GPIO_PORT14 | GPIO_PIN7) +#define GPIO_POSIF0_IN1A (GPIO_INPUT | GPIO_PORT1 | GPIO_PIN2) +#define GPIO_POSIF0_IN1B (GPIO_INPUT | GPIO_PORT14 | GPIO_PIN6) +#define GPIO_POSIF0_IN2A (GPIO_INPUT | GPIO_PORT1 | GPIO_PIN1) +#define GPIO_POSIF0_IN2B (GPIO_INPUT | GPIO_PORT14 | GPIO_PIN5) +#define GPIO_POSIF1_IN0A (GPIO_INPUT | GPIO_PORT2 | GPIO_PIN5) +#define GPIO_POSIF1_IN0B (GPIO_INPUT | GPIO_PORT3 | GPIO_PIN10) +#define GPIO_POSIF1_IN1A (GPIO_INPUT | GPIO_PORT2 | GPIO_PIN4) +#define GPIO_POSIF1_IN1B (GPIO_INPUT | GPIO_PORT3 | GPIO_PIN9) +#define GPIO_POSIF1_IN2A (GPIO_INPUT | GPIO_PORT2 | GPIO_PIN3) +#define GPIO_POSIF1_IN2B (GPIO_INPUT | GPIO_PORT3 | GPIO_PIN8) + +#define GPIO_SCU_EXTCLK_1 (GPIO_OUTPUT_ALT1 | GPIO_PORT0 | GPIO_PIN8) +#define GPIO_SCU_EXTCLK_2 (GPIO_OUTPUT_ALT1 | GPIO_PORT1 | GPIO_PIN15) + +#define GPIO_SDMMC_BUSPOWER (GPIO_OUTPUT | GPIO_PINCTRL_HW0 | GPIO_PORT3 | GPIO_PIN4) +#define GPIO_SDMMC_CLKIN (GPIO_INPUT | GPIO_PINCTRL_HW0 | GPIO_PORT3 | GPIO_PIN6) +#define GPIO_SDMMC_CLKOUT (GPIO_OUTPUT | GPIO_PINCTRL_HW0 | GPIO_PORT3 | GPIO_PIN6) +#define GPIO_SDMMC_CMDIN (GPIO_INPUT | GPIO_PINCTRL_HW0 | GPIO_PORT3 | GPIO_PIN5) +#define GPIO_SDMMC_CMDOUT (GPIO_OUTPUT | GPIO_PINCTRL_HW0 | GPIO_PORT3 | GPIO_PIN5) +#define GPIO_SDMMC_DATA0IN (GPIO_INPUT | GPIO_PINCTRL_HW0 | GPIO_PORT4 | GPIO_PIN0) +#define GPIO_SDMMC_DATA0OUT (GPIO_OUTPUT | GPIO_PINCTRL_HW0 | GPIO_PORT4 | GPIO_PIN0) +#define GPIO_SDMMC_DATA1IN (GPIO_INPUT | GPIO_PINCTRL_HW0 | GPIO_PORT1 | GPIO_PIN6) +#define GPIO_SDMMC_DATA1OUT (GPIO_OUTPUT | GPIO_PINCTRL_HW0 | GPIO_PORT1 | GPIO_PIN6) +#define GPIO_SDMMC_DATA2IN (GPIO_INPUT | GPIO_PINCTRL_HW0 | GPIO_PORT1 | GPIO_PIN7) +#define GPIO_SDMMC_DATA2OUT (GPIO_OUTPUT | GPIO_PINCTRL_HW0 | GPIO_PORT1 | GPIO_PIN7) +#define GPIO_SDMMC_DATA3IN (GPIO_INPUT | GPIO_PINCTRL_HW0 | GPIO_PORT4 | GPIO_PIN1) +#define GPIO_SDMMC_DATA3OUT (GPIO_OUTPUT | GPIO_PINCTRL_HW0 | GPIO_PORT4 | GPIO_PIN1) +#define GPIO_SDMMC_DATA4IN (GPIO_INPUT | GPIO_PINCTRL_HW0 | GPIO_PORT1 | GPIO_PIN8) +#define GPIO_SDMMC_DATA4OUT (GPIO_OUTPUT | GPIO_PINCTRL_HW0 | GPIO_PORT1 | GPIO_PIN8) +#define GPIO_SDMMC_DATA5IN (GPIO_INPUT | GPIO_PINCTRL_HW0 | GPIO_PORT1 | GPIO_PIN9) +#define GPIO_SDMMC_DATA5OUT (GPIO_OUTPUT | GPIO_PINCTRL_HW0 | GPIO_PORT1 | GPIO_PIN9) +#define GPIO_SDMMC_DATA6IN (GPIO_INPUT | GPIO_PINCTRL_HW0 | GPIO_PORT1 | GPIO_PIN12) +#define GPIO_SDMMC_DATA6OUT (GPIO_OUTPUT | GPIO_PINCTRL_HW0 | GPIO_PORT1 | GPIO_PIN12) +#define GPIO_SDMMC_DATA7IN (GPIO_INPUT | GPIO_PINCTRL_HW0 | GPIO_PORT1 | GPIO_PIN13) +#define GPIO_SDMMC_DATA7OUT (GPIO_OUTPUT | GPIO_PINCTRL_HW0 | GPIO_PORT1 | GPIO_PIN13) +#define GPIO_SDMMC_LED (GPIO_OUTPUT | GPIO_PINCTRL_HW0 | GPIO_PORT3 | GPIO_PIN3) +#define GPIO_SDMMC_RST (GPIO_OUTPUT | GPIO_PINCTRL_HW0 | GPIO_PORT0 | GPIO_PIN11) +#define GPIO_SDMMC_SDCD (GPIO_INPUT | GPIO_PINCTRL_HW0 | GPIO_PORT1 | GPIO_PIN10) +#define GPIO_SDMMC_SDWC (GPIO_INPUT | GPIO_PINCTRL_HW0 | GPIO_PORT1 | GPIO_PIN1) +#define GPIO_TRACESWO (GPIO_OUTPUT | GPIO_PINCTRL_HW0 | GPIO_PORT2 | GPIO_PIN1) + +#define GPIO_U0C0_DOUT0_1 (GPIO_OUTPUT | GPIO_PINCTRL_HW0 | GPIO_PORT1 | GPIO_PIN5) +#define GPIO_U0C0_DOUT0_2 (GPIO_OUTPUT_ALT1 | GPIO_PORT5 | GPIO_PIN1) +#define GPIO_U0C0_DOUT0_3 (GPIO_OUTPUT_ALT2 | GPIO_PORT1 | GPIO_PIN5) +#define GPIO_U0C0_DOUT0_4 (GPIO_OUTPUT_ALT2 | GPIO_PORT1 | GPIO_PIN7) +#define GPIO_U0C0_DOUT1_1 (GPIO_OUTPUT | GPIO_PINCTRL_HW0 | GPIO_PORT1 | GPIO_PIN4) +#define GPIO_U0C0_DOUT2_2 (GPIO_OUTPUT | GPIO_PINCTRL_HW0 | GPIO_PORT1 | GPIO_PIN3) +#define GPIO_U0C0_DOUT3_3 (GPIO_OUTPUT | GPIO_PINCTRL_HW0 | GPIO_PORT1 | GPIO_PIN2) +#define GPIO_U0C0_DX0A (GPIO_INPUT | GPIO_PORT1 | GPIO_PIN5) +#define GPIO_U0C0_DX0B (GPIO_INPUT | GPIO_PORT1 | GPIO_PIN4) +#define GPIO_U0C0_DX0C (GPIO_INPUT | GPIO_PORT4 | GPIO_PIN7) +#define GPIO_U0C0_DX0D (GPIO_INPUT | GPIO_PORT5 | GPIO_PIN0) +#define GPIO_U0C0_DX1A (GPIO_INPUT | GPIO_PORT1 | GPIO_PIN1) +#define GPIO_U0C0_DX1B (GPIO_INPUT | GPIO_PORT0 | GPIO_PIN8) +#define GPIO_U0C0_DX2A (GPIO_INPUT | GPIO_PORT1 | GPIO_PIN0) +#define GPIO_U0C0_DX2B (GPIO_INPUT | GPIO_PORT0 | GPIO_PIN7) +#define GPIO_U0C0_HWIN0 (GPIO_INPUT | GPIO_PINCTRL_HW0 | GPIO_PORT1 | GPIO_PIN5) +#define GPIO_U0C0_HWIN1 (GPIO_INPUT | GPIO_PINCTRL_HW0 | GPIO_PORT1 | GPIO_PIN4) +#define GPIO_U0C0_HWIN2 (GPIO_INPUT | GPIO_PINCTRL_HW0 | GPIO_PORT1 | GPIO_PIN3) +#define GPIO_U0C0_HWIN3 (GPIO_INPUT | GPIO_PINCTRL_HW0 | GPIO_PORT1 | GPIO_PIN2) +#define GPIO_U0C0_MCLKOUT (GPIO_OUTPUT_ALT2 | GPIO_PORT1 | GPIO_PIN3) +#define GPIO_U0C0_SCLKOUT_1 (GPIO_OUTPUT_ALT2 | GPIO_PORT0 | GPIO_PIN8) +#define GPIO_U0C0_SCLKOUT_2 (GPIO_OUTPUT_ALT2 | GPIO_PORT1 | GPIO_PIN1) +#define GPIO_U0C0_SCLKOUT_3 (GPIO_OUTPUT_ALT2 | GPIO_PORT1 | GPIO_PIN10) +#define GPIO_U0C0_SCLKOUT_4 (GPIO_OUTPUT_ALT2 | GPIO_PORT1 | GPIO_PIN6) +#define GPIO_U0C0_SELO0_1 (GPIO_OUTPUT_ALT2 | GPIO_PORT0 | GPIO_PIN7) +#define GPIO_U0C0_SELO0_2 (GPIO_OUTPUT_ALT2 | GPIO_PORT1 | GPIO_PIN0) +#define GPIO_U0C0_SELO0_3 (GPIO_OUTPUT_ALT2 | GPIO_PORT1 | GPIO_PIN11) +#define GPIO_U0C0_SELO1 (GPIO_OUTPUT_ALT2 | GPIO_PORT1 | GPIO_PIN8) +#define GPIO_U0C0_SELO2 (GPIO_OUTPUT_ALT2 | GPIO_PORT4 | GPIO_PIN6) +#define GPIO_U0C0_SELO3 (GPIO_OUTPUT_ALT2 | GPIO_PORT4 | GPIO_PIN5) +#define GPIO_U0C0_SELO4 (GPIO_OUTPUT_ALT2 | GPIO_PORT4 | GPIO_PIN4) +#define GPIO_U0C0_SELO5 (GPIO_OUTPUT_ALT2 | GPIO_PORT4 | GPIO_PIN3) +#define GPIO_U0C1_DOUT0_1 (GPIO_OUTPUT | GPIO_PINCTRL_HW0 | GPIO_PORT3 | GPIO_PIN13) +#define GPIO_U0C1_DOUT0_2 (GPIO_OUTPUT_ALT2 | GPIO_PORT2 | GPIO_PIN5) +#define GPIO_U0C1_DOUT0_3 (GPIO_OUTPUT_ALT2 | GPIO_PORT3 | GPIO_PIN13) +#define GPIO_U0C1_DOUT0_4 (GPIO_OUTPUT_ALT2 | GPIO_PORT6 | GPIO_PIN4) +#define GPIO_U0C1_DOUT0_5 (GPIO_OUTPUT_ALT4 | GPIO_PORT3 | GPIO_PIN5) +#define GPIO_U0C1_DOUT1 (GPIO_OUTPUT | GPIO_PINCTRL_HW0 | GPIO_PORT3 | GPIO_PIN12) +#define GPIO_U0C1_DOUT2 (GPIO_OUTPUT | GPIO_PINCTRL_HW0 | GPIO_PORT3 | GPIO_PIN11) +#define GPIO_U0C1_DOUT3 (GPIO_OUTPUT | GPIO_PINCTRL_HW0 | GPIO_PORT3 | GPIO_PIN10) +#define GPIO_U0C1_DX0A (GPIO_INPUT | GPIO_PORT2 | GPIO_PIN2) +#define GPIO_U0C1_DX0B (GPIO_INPUT | GPIO_PORT2 | GPIO_PIN5) +#define GPIO_U0C1_DX0C (GPIO_INPUT | GPIO_PORT6 | GPIO_PIN3) +#define GPIO_U0C1_DX0D (GPIO_INPUT | GPIO_PORT3 | GPIO_PIN13) +#define GPIO_U0C1_DX0E (GPIO_INPUT | GPIO_PORT4 | GPIO_PIN0) +#define GPIO_U0C1_DX1A (GPIO_INPUT | GPIO_PORT2 | GPIO_PIN4) +#define GPIO_U0C1_DX1B (GPIO_INPUT | GPIO_PORT3 | GPIO_PIN0) +#define GPIO_U0C1_DX1C (GPIO_INPUT | GPIO_PORT6 | GPIO_PIN2) +#define GPIO_U0C1_DX2A (GPIO_INPUT | GPIO_PORT2 | GPIO_PIN3) +#define GPIO_U0C1_DX2B (GPIO_INPUT | GPIO_PORT3 | GPIO_PIN1) +#define GPIO_U0C1_DX2C (GPIO_INPUT | GPIO_PORT6 | GPIO_PIN1) +#define GPIO_U0C1_HWIN0 (GPIO_INPUT | GPIO_PINCTRL_HW0 | GPIO_PORT3 | GPIO_PIN13) +#define GPIO_U0C1_HWIN1 (GPIO_INPUT | GPIO_PINCTRL_HW0 | GPIO_PORT3 | GPIO_PIN12) +#define GPIO_U0C1_HWIN2 (GPIO_INPUT | GPIO_PINCTRL_HW0 | GPIO_PORT3 | GPIO_PIN11) +#define GPIO_U0C1_HWIN3 (GPIO_INPUT | GPIO_PINCTRL_HW0 | GPIO_PORT3 | GPIO_PIN10) +#define GPIO_U0C1_MCLKOUT (GPIO_OUTPUT_ALT2 | GPIO_PORT6 | GPIO_PIN5) +#define GPIO_U0C1_SCLKOUT_1 (GPIO_OUTPUT_ALT2 | GPIO_PORT2 | GPIO_PIN4) +#define GPIO_U0C1_SCLKOUT_2 (GPIO_OUTPUT_ALT2 | GPIO_PORT3 | GPIO_PIN0) +#define GPIO_U0C1_SCLKOUT_3 (GPIO_OUTPUT_ALT2 | GPIO_PORT6 | GPIO_PIN2) +#define GPIO_U0C1_SCLKOUT_4 (GPIO_OUTPUT_ALT4 | GPIO_PORT3 | GPIO_PIN6) +#define GPIO_U0C1_SELO0_1 (GPIO_OUTPUT_ALT2 | GPIO_PORT2 | GPIO_PIN3) +#define GPIO_U0C1_SELO0_2 (GPIO_OUTPUT_ALT2 | GPIO_PORT3 | GPIO_PIN1) +#define GPIO_U0C1_SELO0_3 (GPIO_OUTPUT_ALT2 | GPIO_PORT6 | GPIO_PIN1) +#define GPIO_U0C1_SELO0_4 (GPIO_OUTPUT_ALT4 | GPIO_PORT4 | GPIO_PIN1) +#define GPIO_U0C1_SELO1_1 (GPIO_OUTPUT_ALT2 | GPIO_PORT3 | GPIO_PIN12) +#define GPIO_U0C1_SELO1_2 (GPIO_OUTPUT_ALT2 | GPIO_PORT6 | GPIO_PIN0) +#define GPIO_U0C1_SELO2_1 (GPIO_OUTPUT_ALT2 | GPIO_PORT1 | GPIO_PIN14) +#define GPIO_U0C1_SELO2_2 (GPIO_OUTPUT_ALT2 | GPIO_PORT3 | GPIO_PIN11) +#define GPIO_U0C1_SELO3_1 (GPIO_OUTPUT_ALT2 | GPIO_PORT1 | GPIO_PIN13) +#define GPIO_U0C1_SELO3_2 (GPIO_OUTPUT_ALT2 | GPIO_PORT3 | GPIO_PIN8) +#define GPIO_U1C0_DOUT0_1 (GPIO_OUTPUT | GPIO_PINCTRL_HW0 | GPIO_PORT0 | GPIO_PIN5) +#define GPIO_U1C0_DOUT0_2 (GPIO_OUTPUT_ALT2 | GPIO_PORT0 | GPIO_PIN5) +#define GPIO_U1C0_DOUT0_3 (GPIO_OUTPUT_ALT2 | GPIO_PORT2 | GPIO_PIN14) +#define GPIO_U1C0_DOUT1 (GPIO_OUTPUT | GPIO_PINCTRL_HW0 | GPIO_PORT0 | GPIO_PIN4) +#define GPIO_U1C0_DOUT2 (GPIO_OUTPUT | GPIO_PINCTRL_HW0 | GPIO_PORT0 | GPIO_PIN3) +#define GPIO_U1C0_DOUT3 (GPIO_OUTPUT | GPIO_PINCTRL_HW0 | GPIO_PORT0 | GPIO_PIN2) +#define GPIO_U1C0_DX0A (GPIO_INPUT | GPIO_PORT0 | GPIO_PIN4) +#define GPIO_U1C0_DX0B (GPIO_INPUT | GPIO_PORT0 | GPIO_PIN5) +#define GPIO_U1C0_DX0C (GPIO_INPUT | GPIO_PORT2 | GPIO_PIN15) +#define GPIO_U1C0_DX0D (GPIO_INPUT | GPIO_PORT2 | GPIO_PIN14) +#define GPIO_U1C0_DX1A (GPIO_INPUT | GPIO_PORT0 | GPIO_PIN11) +#define GPIO_U1C0_DX1B (GPIO_INPUT | GPIO_PORT5 | GPIO_PIN8) +#define GPIO_U1C0_DX2A (GPIO_INPUT | GPIO_PORT0 | GPIO_PIN6) +#define GPIO_U1C0_DX2B (GPIO_INPUT | GPIO_PORT5 | GPIO_PIN9) +#define GPIO_U1C0_HWIN0 (GPIO_INPUT | GPIO_PINCTRL_HW0 | GPIO_PORT0 | GPIO_PIN5) +#define GPIO_U1C0_HWIN1 (GPIO_INPUT | GPIO_PINCTRL_HW0 | GPIO_PORT0 | GPIO_PIN4) +#define GPIO_U1C0_HWIN2 (GPIO_INPUT | GPIO_PINCTRL_HW0 | GPIO_PORT0 | GPIO_PIN3) +#define GPIO_U1C0_HWIN3 (GPIO_INPUT | GPIO_PINCTRL_HW0 | GPIO_PORT0 | GPIO_PIN2) +#define GPIO_U1C0_MCLKOUT (GPIO_OUTPUT_ALT2 | GPIO_PORT5 | GPIO_PIN10) +#define GPIO_U1C0_SCLKOUT_1 (GPIO_OUTPUT_ALT2 | GPIO_PORT0 | GPIO_PIN11) +#define GPIO_U1C0_SCLKOUT_2 (GPIO_OUTPUT_ALT2 | GPIO_PORT5 | GPIO_PIN8) +#define GPIO_U1C0_SELO0_1 (GPIO_OUTPUT_ALT2 | GPIO_PORT0 | GPIO_PIN6) +#define GPIO_U1C0_SELO0_2 (GPIO_OUTPUT_ALT2 | GPIO_PORT5 | GPIO_PIN9) +#define GPIO_U1C0_SELO1_1 (GPIO_OUTPUT_ALT2 | GPIO_PORT0 | GPIO_PIN14) +#define GPIO_U1C0_SELO1_2 (GPIO_OUTPUT_ALT2 | GPIO_PORT5 | GPIO_PIN11) +#define GPIO_U1C0_SELO2 (GPIO_OUTPUT_ALT2 | GPIO_PORT0 | GPIO_PIN15) +#define GPIO_U1C0_SELO3 (GPIO_OUTPUT_ALT2 | GPIO_PORT3 | GPIO_PIN14) +#define GPIO_U1C1_DOUT0_1 (GPIO_OUTPUT | GPIO_PINCTRL_HW0 | GPIO_PORT3 | GPIO_PIN15) +#define GPIO_U1C1_DOUT0_2 (GPIO_OUTPUT_ALT2 | GPIO_PORT0 | GPIO_PIN1) +#define GPIO_U1C1_DOUT0_3 (GPIO_OUTPUT_ALT2 | GPIO_PORT3 | GPIO_PIN15) +#define GPIO_U1C1_DOUT0_4 (GPIO_OUTPUT_ALT2 | GPIO_PORT4 | GPIO_PIN2) +#define GPIO_U1C1_DOUT1 (GPIO_OUTPUT | GPIO_PINCTRL_HW0 | GPIO_PORT3 | GPIO_PIN14) +#define GPIO_U1C1_DOUT2 (GPIO_OUTPUT | GPIO_PINCTRL_HW0 | GPIO_PORT0 | GPIO_PIN15) +#define GPIO_U1C1_DOUT3 (GPIO_OUTPUT | GPIO_PINCTRL_HW0 | GPIO_PORT0 | GPIO_PIN14) +#define GPIO_U1C1_DX0A (GPIO_INPUT | GPIO_PORT3 | GPIO_PIN15) +#define GPIO_U1C1_DX0B (GPIO_INPUT | GPIO_PORT3 | GPIO_PIN14) +#define GPIO_U1C1_DX0C (GPIO_INPUT | GPIO_PORT4 | GPIO_PIN2) +#define GPIO_U1C1_DX0D (GPIO_INPUT | GPIO_PORT0 | GPIO_PIN0) +#define GPIO_U1C1_DX1A (GPIO_INPUT | GPIO_PORT0 | GPIO_PIN10) +#define GPIO_U1C1_DX1B (GPIO_INPUT | GPIO_PORT0 | GPIO_PIN13) +#define GPIO_U1C1_DX1C (GPIO_INPUT | GPIO_PORT4 | GPIO_PIN0) +#define GPIO_U1C1_DX2A (GPIO_INPUT | GPIO_PORT0 | GPIO_PIN9) +#define GPIO_U1C1_DX2B (GPIO_INPUT | GPIO_PORT0 | GPIO_PIN12) +#define GPIO_U1C1_HWIN0 (GPIO_INPUT | GPIO_PINCTRL_HW0 | GPIO_PORT3 | GPIO_PIN15) +#define GPIO_U1C1_HWIN1 (GPIO_INPUT | GPIO_PINCTRL_HW0 | GPIO_PORT3 | GPIO_PIN14) +#define GPIO_U1C1_HWIN2 (GPIO_INPUT | GPIO_PINCTRL_HW0 | GPIO_PORT0 | GPIO_PIN15) +#define GPIO_U1C1_HWIN3 (GPIO_INPUT | GPIO_PINCTRL_HW0 | GPIO_PORT0 | GPIO_PIN14) +#define GPIO_U1C1_SCLKOUT_1 (GPIO_OUTPUT_ALT2 | GPIO_PORT0 | GPIO_PIN10) +#define GPIO_U1C1_SCLKOUT_2 (GPIO_OUTPUT_ALT2 | GPIO_PORT0 | GPIO_PIN13) +#define GPIO_U1C1_SELO0_1 (GPIO_OUTPUT_ALT2 | GPIO_PORT0 | GPIO_PIN12) +#define GPIO_U1C1_SELO0_2 (GPIO_OUTPUT_ALT2 | GPIO_PORT0 | GPIO_PIN9) +#define GPIO_U1C1_SELO1_1 (GPIO_OUTPUT_ALT2 | GPIO_PORT0 | GPIO_PIN2) +#define GPIO_U1C1_SELO1_2 (GPIO_OUTPUT_ALT2 | GPIO_PORT3 | GPIO_PIN3) +#define GPIO_U1C1_SELO2 (GPIO_OUTPUT_ALT2 | GPIO_PORT3 | GPIO_PIN4) +#define GPIO_U1C1_SELO3 (GPIO_OUTPUT_ALT2 | GPIO_PORT3 | GPIO_PIN5) +#define GPIO_U1C1_SELO4 (GPIO_OUTPUT_ALT2 | GPIO_PORT3 | GPIO_PIN6) +#define GPIO_U2C0_DOUT0_1 (GPIO_OUTPUT | GPIO_PINCTRL_HW0 | GPIO_PORT5 | GPIO_PIN0) +#define GPIO_U2C0_DOUT0_2 (GPIO_OUTPUT_ALT1 | GPIO_PORT3 | GPIO_PIN8) +#define GPIO_U2C0_DOUT0_3 (GPIO_OUTPUT_ALT1 | GPIO_PORT5 | GPIO_PIN0) +#define GPIO_U2C0_DOUT1 (GPIO_OUTPUT | GPIO_PINCTRL_HW0 | GPIO_PORT5 | GPIO_PIN1) +#define GPIO_U2C0_DOUT2 (GPIO_OUTPUT | GPIO_PINCTRL_HW0 | GPIO_PORT5 | GPIO_PIN7) +#define GPIO_U2C0_DOUT3 (GPIO_OUTPUT | GPIO_PINCTRL_HW0 | GPIO_PORT2 | GPIO_PIN6) +#define GPIO_U2C0_DX0A (GPIO_INPUT | GPIO_PORT5 | GPIO_PIN1) +#define GPIO_U2C0_DX0B (GPIO_INPUT | GPIO_PORT5 | GPIO_PIN0) +#define GPIO_U2C0_DX0C (GPIO_INPUT | GPIO_PORT3 | GPIO_PIN7) +#define GPIO_U2C0_DX1A (GPIO_INPUT | GPIO_PORT5 | GPIO_PIN2) +#define GPIO_U2C0_DX2A (GPIO_INPUT | GPIO_PORT5 | GPIO_PIN3) +#define GPIO_U2C0_HWIN0 (GPIO_INPUT | GPIO_PINCTRL_HW0 | GPIO_PORT5 | GPIO_PIN0) +#define GPIO_U2C0_HWIN1 (GPIO_INPUT | GPIO_PINCTRL_HW0 | GPIO_PORT5 | GPIO_PIN1) +#define GPIO_U2C0_HWIN2 (GPIO_INPUT | GPIO_PINCTRL_HW0 | GPIO_PORT5 | GPIO_PIN7) +#define GPIO_U2C0_HWIN3 (GPIO_INPUT | GPIO_PINCTRL_HW0 | GPIO_PORT2 | GPIO_PIN6) +#define GPIO_U2C0_SCLKOUT_1 (GPIO_OUTPUT_ALT1 | GPIO_PORT3 | GPIO_PIN9) +#define GPIO_U2C0_SCLKOUT_2 (GPIO_OUTPUT_ALT1 | GPIO_PORT5 | GPIO_PIN2) +#define GPIO_U2C0_SELO0_1 (GPIO_OUTPUT_ALT1 | GPIO_PORT3 | GPIO_PIN10) +#define GPIO_U2C0_SELO0_2 (GPIO_OUTPUT_ALT1 | GPIO_PORT5 | GPIO_PIN3) +#define GPIO_U2C0_SELO1 (GPIO_OUTPUT_ALT1 | GPIO_PORT5 | GPIO_PIN4) +#define GPIO_U2C0_SELO2 (GPIO_OUTPUT_ALT1 | GPIO_PORT5 | GPIO_PIN5) +#define GPIO_U2C0_SELO3 (GPIO_OUTPUT_ALT1 | GPIO_PORT5 | GPIO_PIN6) +#define GPIO_U2C0_SELO4 (GPIO_OUTPUT_ALT1 | GPIO_PORT2 | GPIO_PIN6) +#define GPIO_U2C1_DOUT0_1 (GPIO_OUTPUT | GPIO_PINCTRL_HW0 | GPIO_PORT4 | GPIO_PIN7) +#define GPIO_U2C1_DOUT0_2 (GPIO_OUTPUT_ALT1 | GPIO_PORT3 | GPIO_PIN11) +#define GPIO_U2C1_DOUT0_3 (GPIO_OUTPUT_ALT1 | GPIO_PORT3 | GPIO_PIN5) +#define GPIO_U2C1_DOUT1 (GPIO_OUTPUT | GPIO_PINCTRL_HW0 | GPIO_PORT4 | GPIO_PIN6) +#define GPIO_U2C1_DOUT2 (GPIO_OUTPUT | GPIO_PINCTRL_HW0 | GPIO_PORT4 | GPIO_PIN5) +#define GPIO_U2C1_DOUT3 (GPIO_OUTPUT | GPIO_PINCTRL_HW0 | GPIO_PORT4 | GPIO_PIN4) +#define GPIO_U2C1_DX0A (GPIO_INPUT | GPIO_PORT3 | GPIO_PIN5) +#define GPIO_U2C1_DX0B (GPIO_INPUT | GPIO_PORT3 | GPIO_PIN4) +#define GPIO_U2C1_DX0C (GPIO_INPUT | GPIO_PORT4 | GPIO_PIN0) +#define GPIO_U2C1_DX0D (GPIO_INPUT | GPIO_PORT3 | GPIO_PIN12) +#define GPIO_U2C1_DX1A (GPIO_INPUT | GPIO_PORT4 | GPIO_PIN2) +#define GPIO_U2C1_DX1B (GPIO_INPUT | GPIO_PORT3 | GPIO_PIN6) +#define GPIO_U2C1_DX2A (GPIO_INPUT | GPIO_PORT4 | GPIO_PIN1) +#define GPIO_U2C1_DX2B (GPIO_INPUT | GPIO_PORT4 | GPIO_PIN1) +#define GPIO_U2C1_HWIN0 (GPIO_INPUT | GPIO_PINCTRL_HW0 | GPIO_PORT4 | GPIO_PIN7) +#define GPIO_U2C1_HWIN1 (GPIO_INPUT | GPIO_PINCTRL_HW0 | GPIO_PORT4 | GPIO_PIN6) +#define GPIO_U2C1_HWIN2 (GPIO_INPUT | GPIO_PINCTRL_HW0 | GPIO_PORT4 | GPIO_PIN5) +#define GPIO_U2C1_HWIN3 (GPIO_INPUT | GPIO_PINCTRL_HW0 | GPIO_PORT4 | GPIO_PIN4) +#define GPIO_U2C1_MCLKOUT (GPIO_OUTPUT_ALT1 | GPIO_PORT3 | GPIO_PIN4) +#define GPIO_U2C1_SCLKOUT_1 (GPIO_OUTPUT_ALT1 | GPIO_PORT3 | GPIO_PIN13) +#define GPIO_U2C1_SCLKOUT_1 (GPIO_OUTPUT_ALT1 | GPIO_PORT3 | GPIO_PIN6) +#define GPIO_U2C1_SCLKOUT_1 (GPIO_OUTPUT_ALT4 | GPIO_PORT4 | GPIO_PIN2) +#define GPIO_U2C1_SELO0_1 (GPIO_OUTPUT_ALT1 | GPIO_PORT3 | GPIO_PIN0) +#define GPIO_U2C1_SELO0_2 (GPIO_OUTPUT_ALT1 | GPIO_PORT4 | GPIO_PIN1) +#define GPIO_U2C1_SELO1 (GPIO_OUTPUT_ALT1 | GPIO_PORT4 | GPIO_PIN2) +#define GPIO_U2C1_SELO2 (GPIO_OUTPUT_ALT1 | GPIO_PORT4 | GPIO_PIN3) + +#define GPIO_USB_DRIVEVBUS_1 (GPIO_OUTPUT_ALT1 | GPIO_PORT0 | GPIO_PIN1) +#define GPIO_USB_DRIVEVBUS_2 (GPIO_OUTPUT_ALT1 | GPIO_PORT3 | GPIO_PIN2) +#define GPIO_USB_ID (GPIO_INPUT | GPIO_PORT0 | GPIO_PIN9) + +#define GPIO_VADC_EMUX00 (GPIO_OUTPUT_ALT1 | GPIO_PORT2 | GPIO_PIN2) +#define GPIO_VADC_EMUX01 (GPIO_OUTPUT_ALT1 | GPIO_PORT2 | GPIO_PIN3) +#define GPIO_VADC_EMUX02 (GPIO_OUTPUT_ALT1 | GPIO_PORT2 | GPIO_PIN4) +#define GPIO_VADC_EMUX10 (GPIO_OUTPUT_ALT1 | GPIO_PORT2 | GPIO_PIN10) +#define GPIO_VADC_EMUX11 (GPIO_OUTPUT_ALT1 | GPIO_PORT2 | GPIO_PIN14) +#define GPIO_VADC_EMUX12 (GPIO_OUTPUT_ALT1 | GPIO_PORT2 | GPIO_PIN15) +#define GPIO_VADC_G0CH0 (GPIO_INPUT | GPIO_PORT14 | GPIO_PIN0) +#define GPIO_VADC_G0CH1 (GPIO_INPUT | GPIO_PORT14 | GPIO_PIN1) +#define GPIO_VADC_G0CH2 (GPIO_INPUT | GPIO_PORT14 | GPIO_PIN2) +#define GPIO_VADC_G0CH3 (GPIO_INPUT | GPIO_PORT14 | GPIO_PIN3) +#define GPIO_VADC_G0CH4 (GPIO_INPUT | GPIO_PORT14 | GPIO_PIN4) +#define GPIO_VADC_G0CH5 (GPIO_INPUT | GPIO_PORT14 | GPIO_PIN5) +#define GPIO_VADC_G0CH6 (GPIO_INPUT | GPIO_PORT14 | GPIO_PIN6) +#define GPIO_VADC_G0CH7 (GPIO_INPUT | GPIO_PORT14 | GPIO_PIN7) +#define GPIO_VADC_G1CH0 (GPIO_INPUT | GPIO_PORT14 | GPIO_PIN8) +#define GPIO_VADC_G1CH1 (GPIO_INPUT | GPIO_PORT14 | GPIO_PIN9) +#define GPIO_VADC_G1CH2 (GPIO_INPUT | GPIO_PORT14 | GPIO_PIN2) +#define GPIO_VADC_G1CH3 (GPIO_INPUT | GPIO_PORT14 | GPIO_PIN3) +#define GPIO_VADC_G1CH4 (GPIO_INPUT | GPIO_PORT14 | GPIO_PIN12) +#define GPIO_VADC_G1CH5 (GPIO_INPUT | GPIO_PORT14 | GPIO_PIN13) +#define GPIO_VADC_G1CH6 (GPIO_INPUT | GPIO_PORT14 | GPIO_PIN14) +#define GPIO_VADC_G1CH7 (GPIO_INPUT | GPIO_PORT14 | GPIO_PIN15) +#define GPIO_VADC_G2CH0 (GPIO_INPUT | GPIO_PORT14 | GPIO_PIN4) +#define GPIO_VADC_G2CH1 (GPIO_INPUT | GPIO_PORT14 | GPIO_PIN5) +#define GPIO_VADC_G2CH2 (GPIO_INPUT | GPIO_PORT15 | GPIO_PIN2) +#define GPIO_VADC_G2CH3 (GPIO_INPUT | GPIO_PORT15 | GPIO_PIN3) +#define GPIO_VADC_G2CH4 (GPIO_INPUT | GPIO_PORT15 | GPIO_PIN4) +#define GPIO_VADC_G2CH5 (GPIO_INPUT | GPIO_PORT15 | GPIO_PIN5) +#define GPIO_VADC_G2CH6 (GPIO_INPUT | GPIO_PORT15 | GPIO_PIN6) +#define GPIO_VADC_G2CH7 (GPIO_INPUT | GPIO_PORT15 | GPIO_PIN7) +#define GPIO_VADC_G3CH0 (GPIO_INPUT | GPIO_PORT15 | GPIO_PIN8) +#define GPIO_VADC_G3CH1 (GPIO_INPUT | GPIO_PORT15 | GPIO_PIN9) +#define GPIO_VADC_G3CH2 (GPIO_INPUT | GPIO_PORT14 | GPIO_PIN8) +#define GPIO_VADC_G3CH3 (GPIO_INPUT | GPIO_PORT14 | GPIO_PIN9) +#define GPIO_VADC_G3CH4 (GPIO_INPUT | GPIO_PORT15 | GPIO_PIN12) +#define GPIO_VADC_G3CH5 (GPIO_INPUT | GPIO_PORT15 | GPIO_PIN13) +#define GPIO_VADC_G3CH6 (GPIO_INPUT | GPIO_PORT15 | GPIO_PIN14) +#define GPIO_VADC_G3CH7 (GPIO_INPUT | GPIO_PORT15 | GPIO_PIN15) + +#define GPIO_WWDT_SERVICEOUT_1 (GPIO_OUTPUT_ALT1 | GPIO_PORT0 | GPIO_PIN7) +#define GPIO_WWDT_SERVICEOUT_2 (GPIO_OUTPUT_ALT1 | GPIO_PORT1 | GPIO_PIN4) #endif /* __ARCH_ARM_SRC_XMC4_CHIP_XMC4_PINMXU_H */ diff --git a/arch/arm/src/xmc4/xmc4_gpio.h b/arch/arm/src/xmc4/xmc4_gpio.h index 49b80ba1968..4595fe6a795 100644 --- a/arch/arm/src/xmc4/xmc4_gpio.h +++ b/arch/arm/src/xmc4/xmc4_gpio.h @@ -65,7 +65,7 @@ /* See chip/xmc4_ports.h for the IOCR definitions */ /* Direct input */ -# define GPIO_INPUT_NOPULL (IOCR_INPUT_NOPULL << GPIO_PINTYPE_SHIFT) +# define GPIO_INPUT (IOCR_INPUT_NOPULL << GPIO_PINTYPE_SHIFT) # define GPIO_INPUT_PULLDOWN (IOCR_INPUT_PULLDOWN << GPIO_PINTYPE_SHIFT) # define GPIO_INPUT_PULLUP (IOCR_INPUT_PULLUP << GPIO_PINTYPE_SHIFT) # define GPIO_INPUT_CONT (IOCR_INPUT_CONT << GPIO_PINTYPE_SHIFT) From cfa75de85a92470926b40d73e9b3f0db3b2b0e0f Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 18 Mar 2017 13:07:59 -0600 Subject: [PATCH 35/81] XMC4xxx: A few more SCU register definitions. --- arch/arm/src/xmc4/chip/xmc4_scu.h | 167 ++++++++++++++++++++++++++---- 1 file changed, 148 insertions(+), 19 deletions(-) diff --git a/arch/arm/src/xmc4/chip/xmc4_scu.h b/arch/arm/src/xmc4/chip/xmc4_scu.h index 7e706f501bd..26862d8cbac 100644 --- a/arch/arm/src/xmc4/chip/xmc4_scu.h +++ b/arch/arm/src/xmc4/chip/xmc4_scu.h @@ -344,32 +344,161 @@ /* General SCU Registers */ -/* Module Identification Register */ -#define SCU_ID_ -/* Chip ID */ -#define SCU_IDCHIP_ +/* Module Identification Register (32-bit Chip ID) */ + +#define SCU_ID_MOD_REV_SHIFT (0) /* Bits 0-7: Module Revision Number */ +#define SCU_ID_MOD_REV_MASK (0xff << SCU_ID_MOD_REV_SHIFT) +#define SCU_ID_MOD_TYPE_SHIFT (8) /* Bits 8-15: Module Type */ +#define SCU_ID_MOD_TYPE_MASK (0xff << SCU_ID_MOD_REV_SHIFT) +#define SCU_ID_MOD_NUMBER_SHIFT (16) /* Bits 16-31: Module Number Value */ +#define SCU_ID_MOD_NUMBER_MASK (0xffff << SCU_ID_MOD_NUMBER_SHIFT) + +/* Chip ID (32-bit Chip ID) */ + /* Manufactory ID */ -#define SCU_IDMANUF_ + +#define SCU_IDMANUF_DEPT_SHIFT (0) /* Bits 0-4: Department Identification Number */ +#define SCU_IDMANUF_DEPT_MASK (31 << SCU_IDMANUF_MOD_DEPT_SHIFT) +#define SCU_IDMANUF_MANUF_SHIFT (5) /* Bits 5-15: Manufacturer Identification Number */ +#define SCU_IDMANUF_MANUF_MASK (0x7ff << SCU_IDMANUF_MOD_MANUF_SHIFT) + /* Start-up Control */ -#define SCU_STCON_ -/* General Purpose Register 0 */ -#define SCU_GPR0_ -/* General Purpose Register 1 */ -#define SCU_GPR1_ + +#define SCU_STCON_HWCON_SHIFT (0) /* Bits 0-1: HW Configuration */ +#define SCU_STCON_HWCON_MASK (3 << SCU_STCON_HWCON_SHIFT) +# define SCU_STCON_HWCON_JTAG (0 << SCU_STCON_HWCON_SHIFT) /* Normal mode, JTAG */ +# define SCU_STCON_HWCON_ACBSL (1 << SCU_STCON_HWCON_SHIFT) /* ASC BSL enabled */ +# define SCU_STCON_HWCON_BMI (2 << SCU_STCON_HWCON_SHIFT) /* BMI customized boot enabled */ +# define SCU_STCON_HWCON_CANBSL (3 << SCU_STCON_HWCON_SHIFT) /* CAN BSL enabled */ +#define SCU_STCON_SWCON_SHIFT (8) /* Bits 8-11: SW Configuration */ +#define SCU_STCON_SWCON_MASK (15 << SCU_STCON_SWCON_SHIFT) +# define SCU_STCON_SWCON_ ROM (0 << SCU_STCON_SWCON_SHIFT) /* Normal boot from Boot ROM */ +# define SCU_STCON_SWCON_ASCBSL (1 << SCU_STCON_SWCON_SHIFT) /* ASC BSL enabled */ +# define SCU_STCON_SWCON_BMI (2 << SCU_STCON_SWCON_SHIFT) /* BMI customized boot enabled */ +# define SCU_STCON_SWCON_CANBSL (3 << SCU_STCON_SWCON_SHIFT) /* CAN BSL enabled */ +# define SCU_STCON_SWCON_SRAM (4 << SCU_STCON_SWCON_SHIFT) /* Boot from Code SRAM */ +# define SCU_STCON_SWCON_FLASH0 (8 << SCU_STCON_SWCON_SHIFT) /* Boot from alternate Flash Address 0 */ +# define SCU_STCON_SWCON_FLASH1 (12 << SCU_STCON_SWCON_SHIFT) /* Boot from alternate Flash Address 1 */ +# define SCU_STCON_SWCON_ABM (15 << SCU_STCON_SWCON_SHIFT) /* Enable fallback Alternate Boot Mode (ABM) */ + +/* General Purpose Register 0 and General Purpose Register 1 (32-bit data) */ + /* Ethernet 0 Port Control */ -#define SCU_ETH0CON_ + +#define SCU_ETH0CON_RXD0_SHIFT (0) /* Bits 0-1: MAC Receive Input 0 */ +#define SCU_ETH0CON_RXD0_MASK (3 << SCU_ETH0CON_RXD0_SHIFT) +# define SCU_ETH0CON_RXD0A (0 << SCU_ETH0CON_RXD0_SHIFT) /* Data input RXD0A is selected */ +# define SCU_ETH0CON_RXD0B (1 << SCU_ETH0CON_RXD0_SHIFT) /* Data input RXD0B is selected */ +# define SCU_ETH0CON_RXD0C (2 << SCU_ETH0CON_RXD0_SHIFT) /* Data input RXD0C is selected */ +# define SCU_ETH0CON_RXD0D (3 << SCU_ETH0CON_RXD0_SHIFT) /* Data input RXD0D is selected */ +#define SCU_ETH0CON_RXD1_SHIFT (2) /* Bits 2-3: MAC Receive Input 1 */ +#define SCU_ETH0CON_RXD1_MASK (3 << SCU_ETH0CON_RXD1_SHIFT) +# define SCU_ETH0CON_RXD1A (0 << SCU_ETH0CON_RXD1_SHIFT) /* Data input RXD1A is selected */ +# define SCU_ETH0CON_RXD1B (1 << SCU_ETH0CON_RXD1_SHIFT) /* Data input RXD1B is selected */ +# define SCU_ETH0CON_RXD1C (2 << SCU_ETH0CON_RXD1_SHIFT) /* Data input RXD1C is selected */ +# define SCU_ETH0CON_RXD1D (3 << SCU_ETH0CON_RXD1_SHIFT) /* Data input RXD1D is selected */ +#define SCU_ETH0CON_RXD2_SHIFT (4) /* Bits 4-5: MAC Receive Input 2 */ +#define SCU_ETH0CON_RXD2_MASK (3 << SCU_ETH0CON_RXD2_SHIFT) +# define SCU_ETH0CON_RXD2A (0 << SCU_ETH0CON_RXD2_SHIFT) /* Data input RXD2A is selected */ +# define SCU_ETH0CON_RXD2B (1 << SCU_ETH0CON_RXD2_SHIFT) /* Data input RXD2B is selected */ +# define SCU_ETH0CON_RXD2C (2 << SCU_ETH0CON_RXD2_SHIFT) /* Data input RXD2C is selected */ +# define SCU_ETH0CON_RXD2D (3 << SCU_ETH0CON_RXD2_SHIFT) /* Data input RXD2D is selected */ +#define SCU_ETH0CON_RXD3_SHIFT (6) /* Bits 6-7: MAC Receive Input 3 */ +#define SCU_ETH0CON_RXD3_MASK (3 << SCU_ETH0CON_RXD3_SHIFT) +# define SCU_ETH0CON_RXD3A (0 << SCU_ETH0CON_RXD3_SHIFT) /* Data input RXD3A is selected */ +# define SCU_ETH0CON_RXD3B (1 << SCU_ETH0CON_RXD3_SHIFT) /* Data input RXD3B is selected */ +# define SCU_ETH0CON_RXD3C (2 << SCU_ETH0CON_RXD3_SHIFT) /* Data input RXD3C is selected */ +# define SCU_ETH0CON_RXD3D (3 << SCU_ETH0CON_RXD3_SHIFT) /* Data input RXD3D is selected */ +#define SCU_ETH0CON_CLKRMII_SHIFT (8) /* Bits 8-9: RMII clock input */ +#define SCU_ETH0CON_CLKRMII_MASK (3 << SCU_ETH0CON_CLKRMII_SHIFT) +# define SCU_ETH0CON_CLKRMIIA (0 << SCU_ETH0CON_CLKRMII_SHIFT) /* Data input RMIIA is selected */ +# define SCU_ETH0CON_CLKRMIIB (1 << SCU_ETH0CON_CLKRMII_SHIFT) /* Data input RMIIB is selected */ +# define SCU_ETH0CON_CLKRMIIC (2 << SCU_ETH0CON_CLKRMII_SHIFT) /* Data input RMIIC is selected */ +# define SCU_ETH0CON_CLKRMIID (3 << SCU_ETH0CON_CLKRMII_SHIFT) /* Data input RMIID is selected */ +#define SCU_ETH0CON_CRSDV_SHIFT (10) /* Bits 10-11: CRS_DV input */ +#define SCU_ETH0CON_CRSDV_MASK (3 << SCU_ETH0CON_CRSDV_SHIFT) +# define SCU_ETH0CON_CRSDVA (0 << SCU_ETH0CON_CRSDV_SHIFT) /* Data input CRS_DVA is selected */ +# define SCU_ETH0CON_CRSDVB (1 << SCU_ETH0CON_CRSDV_SHIFT) /* Data input CRS_DVB is selected */ +# define SCU_ETH0CON_CRSDVC (2 << SCU_ETH0CON_CRSDV_SHIFT) /* Data input CRS_DVC is selected */ +# define SCU_ETH0CON_CRSDVD (3 << SCU_ETH0CON_CRSDV_SHIFT) /* Data input CRS_DVD is selected */ +#define SCU_ETH0CON_CRS_SHIFT (12) /* Bits 12-13: CRS input */ +#define SCU_ETH0CON_CRS_MASK (3 << SCU_ETH0CON_CRS_SHIFT) +# define SCU_ETH0CON_CRSA (0 << SCU_ETH0CON_CRS_SHIFT) /* Data input CRSA is selected */ +# define SCU_ETH0CON_CRSB (1 << SCU_ETH0CON_CRS_SHIFT) /* Data input CRSB is selected */ +# define SCU_ETH0CON_CRSC (2 << SCU_ETH0CON_CRS_SHIFT) /* Data input CRSC is selected */ +# define SCU_ETH0CON_CRSD (3 << SCU_ETH0CON_CRS_SHIFT) /* Data input CRSD is selected */ +#define SCU_ETH0CON_RXER_SHIFT (14) /* Bits 14-15: RXER Input */ +#define SCU_ETH0CON_RXER_MASK (3 << SCU_ETH0CON_RXER_SHIFT) +# define SCU_ETH0CON_RXERA (0 << SCU_ETH0CON_RXER_SHIFT) /* Data input RXERA is selected */ +# define SCU_ETH0CON_RXERB (1 << SCU_ETH0CON_RXER_SHIFT) /* Data input RXERB is selected */ +# define SCU_ETH0CON_RXERC (2 << SCU_ETH0CON_RXER_SHIFT) /* Data input RXERC is selected */ +# define SCU_ETH0CON_RXERD (3 << SCU_ETH0CON_RXER_SHIFT) /* Data input RXERD is selected */ +#define SCU_ETH0CON_COL_SHIFT (16) /* Bits 16-17: COL input */ +#define SCU_ETH0CON_COL_MASK (3 << SCU_ETH0CON_COL_SHIFT) +# define SCU_ETH0CON_COLA (0 << SCU_ETH0CON_COL_SHIFT) /* Data input COLA is selected */ +# define SCU_ETH0CON_COLB (1 << SCU_ETH0CON_COL_SHIFT) /* Data input COLB is selected */ +# define SCU_ETH0CON_COLC (2 << SCU_ETH0CON_COL_SHIFT) /* Data input COLC is selected */ +# define SCU_ETH0CON_COLD (3 << SCU_ETH0CON_COL_SHIFT) /* Data input COLD is selected */ +#define SCU_ETH0CON_CLKTX_SHIFT (18) /* Bits 18-19: CLK_TX input */ +#define SCU_ETH0CON_CLKTX_MASK (3 << SCU_ETH0CON_CLKTX_SHIFT) +# define SCU_ETH0CON_CLKTXA (0 << SCU_ETH0CON_CLKTX_SHIFT) /* Data input CLK_TXA is selected */ +# define SCU_ETH0CON_CLKTXB (1 << SCU_ETH0CON_CLKTX_SHIFT) /* Data input CLK_TXB is selected */ +# define SCU_ETH0CON_CLKTXC (2 << SCU_ETH0CON_CLKTX_SHIFT) /* Data input CLK_TXC is selected */ +# define SCU_ETH0CON_CLKTXD (3 << SCU_ETH0CON_CLKTX_SHIFT) /* Data input CLK_TXD is selected */ +#define SCU_ETH0CON_MDIO_SHIFT (22) /* Bits 22-23: MDIO Input Select */ +#define SCU_ETH0CON_MDIO_MASK (3 << SCU_ETH0CON_MDIO_SHIFT) +# define SCU_ETH0CON_MDIOA (0 << SCU_ETH0CON_MDIO_SHIFT) /* Data input MDIOA is selected */ +# define SCU_ETH0CON_MDIOB (1 << SCU_ETH0CON_MDIO_SHIFT) /* Data input MDIOB is selected */ +# define SCU_ETH0CON_MDIOC (2 << SCU_ETH0CON_MDIO_SHIFT) /* Data input MDIOC is selected */ +# define SCU_ETH0CON_MDIOD (3 << SCU_ETH0CON_MDIO_SHIFT) /* Data input MDIOD is selected */ +#define SCU_ETH0CON_INFSEL (1 << 26) /* Bit 26: Ethernet MAC Interface Selection */ +# define SCU_ETH0CON_INFSEL_MII (0) /* 0=MII */ +# define SCU_ETH0CON_INFSEL_RMII (1 << 26) /* 1=RMII */ + /* CCUx Global Start Control Register */ -#define SCU_CCUCON_ + +#define SCU_CCUCON_GSC40 (1 << 0) /* Bit 0: Global Start Control CCU40 */ +#define SCU_CCUCON_GSC41 (1 << 1) /* Bit 1: Global Start Control CCU41 */ +#define SCU_CCUCON_GSC42 (1 << 2) /* Bit 2: Global Start Control CCU42 */ +#define SCU_CCUCON_GSC43 (1 << 3) /* Bit 3: Global Start Control CCU43 */ +#define SCU_CCUCON_GSC80 (1 << 8) /* Bit 8: Global Start Control CCU80 */ +#define SCU_CCUCON_GSC81 (1 << 9) /* Bit 9: Global Start Control CCU81 */ + /* DTS Control */ -#define SCU_DTSCON_ + +#define SCU_DTSCON_PWD (1 << 0) /* Bit 0: Sensor Power Down */ +#define SCU_DTSCON_START (1 << 1) /* Bit 1: Sensor Measurement Start */ +#define SCU_DTSCON_OFFSET_SHIFT (4) /* Bits 4-10: Offset Calibration Value */ +#define SCU_DTSCON_OFFSET_MASK (0x7f << SCU_DTSCON_OFFSET_SHIFT) +# define SCU_DTSCON_OFFSET(n) ((uint32_t)(n) << SCU_DTSCON_OFFSET_SHIFT) +#define SCU_DTSCON_GAIN_SHIFT (11) /* Bits 11-16: Gain Calibration Value */ +#define SCU_DTSCON_GAIN_MASK (0x3f << SCU_DTSCON_GAIN_SHIFT) +# define SCU_DTSCON_GAIN(n) ((uint32_t)(n) << SCU_DTSCON_GAIN_SHIFT) +#define SCU_DTSCON_REFTRIM_SHIFT (17) /* Bits 17-19: Reference Trim Calibration Value */ +#define SCU_DTSCON_REFTRIM_MASK (7 << SCU_DTSCON_REFTRIM_SHIFT) +# define SCU_DTSCON_REFTRIM(n) ((uint32_t)(n) << SCU_DTSCON_REFTRIM_SHIFT) +#define SCU_DTSCON_BGTRIM_SHIFT (20) /* Bits 20-23: Bandgap Trim Calibration Value */ +#define SCU_DTSCON_BGTRIM_MASK (15 << SCU_DTSCON_BGTRIM_SHIFT) +# define SCU_DTSCON_BGTRIM(n) ((uint32_t)(n) << SCU_DTSCON_BGTRIM_SHIFT) + /* DTS Status */ -#define SCU_DTSSTAT_ + +#define SCU_DTSSTAT_RESULT_SHIFT (0) /* Bits 0-9: Result of the DTS Measurement */ +#define SCU_DTSSTAT_RESULT_MASK (0x3ff << SCU_DTSSTAT_RESULT_SHIFT) +#define SCU_DTSSTAT_RDY (1 << 14) /* Bit 14: Sensor Ready Status */ +#define SCU_DTSSTAT_BUSY (1 << 15) /* Bit 15: Sensor Busy Status */ + /* SD-MMC Delay Control Register */ -#define SCU_SDMMCDEL_ -/* Out-Of-Range Comparator Enable Register 0 */ -#define SCU_G0ORCEN_ -/* Out-Of-Range Comparator Enable Register 1 */ -#define SCU_G1ORCEN_ + +#define SCU_SDMMCDEL_TAPEN (1 << 0) /* Bit 0: Enable delay on the CMD/DAT out lines */ +#define SCU_SDMMCDEL_TAPDEL_SHIFT (4) /* Bitx 4-7: Number of Delay Elements Select */ +#define SCU_SDMMCDEL_TAPDEL_MASK (15 << SCU_SDMMCDEL_TAPDEL_SHIFT) +# define SCU_SDMMCDEL_TAPDEL(n) ((uint32_t)((n)-1) << SCU_SDMMCDEL_TAPDEL_SHIFT) + +/* Out-Of-Range Comparator Enable Register 0 and Out-Of-Range Comparator Enable Register 1 */ + +#define SCU_GORCEN_ENORC6 (1 << 6) /* Bit 6: Enable Out of Range Comparator, Channel 6 */ +#define SCU_GORCEN_ENORC7 (1 << 7) /* Bit 7: Enable Out of Range Comparator, Channel 7 */ /* Mirror Update Status Register */ From 7706810fc021b91678af2326a63872a06b29ae60 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 18 Mar 2017 14:08:35 -0600 Subject: [PATCH 36/81] XMC4xxx: A few more SCU register definitions. --- arch/arm/src/xmc4/chip/xmc4_scu.h | 133 +++++++++++++++++++++--------- 1 file changed, 94 insertions(+), 39 deletions(-) diff --git a/arch/arm/src/xmc4/chip/xmc4_scu.h b/arch/arm/src/xmc4/chip/xmc4_scu.h index 26862d8cbac..7e8b10bc7be 100644 --- a/arch/arm/src/xmc4/chip/xmc4_scu.h +++ b/arch/arm/src/xmc4/chip/xmc4_scu.h @@ -537,10 +537,13 @@ /* Enable Promoting Events to NMI Request */ #define SCU_NMIREQEN_ /* Retention Memory Access Control Register */ -#define SCU_RMACR_ -/* Retention Memory Access Data Register */ -#define SCU_RMADATA_ -/* Parity Error Enable Register */ + +#define SCU_RMACR_RDWR (1 << 0) /* Bit 0: Hibernate Retention Memory Register Update Control */ +#define SCU_RMACR_ADDR_SHIFT (16) /* Bits 16-19: Hibernate Retention Memory Register Address Select */ +#define SCU_RMACR_ADDR_MASK (15 << SCU_RMACR_ADDR_SHIFT) +# define SCU_RMACR_ADDR(n) ((uint32_t)(n) << SCU_RMACR_ADDR_SHIFT) + +/* Retention Memory Access Data Register (32-bit data) */ /* SDMMC Control SCU Registers */ @@ -715,39 +718,62 @@ #define SCU_RSTCLR_HIBRS (1 << 9) /* Bit 9: Clear Hibernate Reset */ #define SCU_RSTCLR_LCKEN (1 << 10) /* Bit 10: Clear Hibernate Reset */ -/* Peripheral Reset Status Register 0 */ -#define SCU_PRSTAT0_ -/* Peripheral Reset Set Register 0 */ -#define SCU_PRSET0_ -/* Peripheral Reset Clear Register 0 */ -#define SCU_PRCLR0_ -/* Peripheral Reset Status Register 1 */ -#define SCU_PRSTAT1_ -/* Peripheral Reset Set Register 1 */ -#define SCU_PRSET1_ -/* Peripheral Reset Clear Register 1 */ -#define SCU_PRCLR1_ -/* Peripheral Reset Status Register 2 */ -#define SCU_PRSTAT2_ -/* Peripheral Reset Set Register 2 */ -#define SCU_PRSET2_ -/* Peripheral Reset Clear Register 2 */ -#define SCU_PRCLR2_ -/* Peripheral Reset Status Register 3 */ -#define SCU_PRSTAT3_ -/* Peripheral Reset Set Register 3 */ -#define SCU_PRSET3_ -/* Peripheral Reset Clear Register 3 */ -#define SCU_PRCLR3_ +/* Peripheral Reset Status Register 0, Peripheral Reset Set Register 0, Peripheral + * Reset Clear Register 0 + */ + +#define SCU_PR0_VADCRS (1 << 0) /* Bit 0: VADC Reset */ +#define SCU_PR0_DSDRS (1 << 1) /* Bit 1: DSD Reset */ +#define SCU_PR0_CCU40RS (1 << 2) /* Bit 2: CCU40 Reset */ +#define SCU_PR0_CCU41RS (1 << 3) /* Bit 3: CCU41 Reset */ +#define SCU_PR0_CCU42RS (1 << 4) /* Bit 4: CCU42 Reset */ +#define SCU_PR0_CCU80RS (1 << 7) /* Bit 7: CCU80 Reset */ +#define SCU_PR0_CCU81RS (1 << 8) /* Bit 8: CCU81 Reset */ +#define SCU_PR0_POSIF0RS (1 << 9) /* Bit 9: POSIF0 Reset */ +#define SCU_PR0_POSIF1RS (1 << 10) /* Bit 10: POSIF1 Reset */ +#define SCU_PR0_USIC0RS (1 << 11) /* Bit 11: USIC0 Reset */ +#define SCU_PR0_ERU1RS (1 << 16) /* Bit 16: ERU1 Reset */ + +/* Peripheral Reset Status Register 1, Peripheral Reset Set Register 1, Peripheral + * Reset Clear Register 1 + */ + +#define SCU_PR1_CCU43RS (1 << 0) /* Bit 0: CCU43 Reset */ +#define SCU_PR1_LEDTSCU0RS (1 << 3) /* Bit 3: LEDTS Reset */ +#define SCU_PR1_MCAN0RS (1 << 4) /* Bit 4: MultiCAN Reset */ +#define SCU_PR1_DACRS (1 << 5) /* Bit 5: DAC Reset */ +#define SCU_PR1_MMCIRS (1 << 6) /* Bit 6: MMC Interface Reset */ +#define SCU_PR1_USIC1RS (1 << 7) /* Bit 7: USIC1 Reset */ +#define SCU_PR1_USIC2RS (1 << 8) /* Bit 8: USIC2 Reset */ +#define SCU_PR1_PPORTSRS (1 << 9) /* Bit 9: PORTS Reset */ + +/* Peripheral Reset Status Register 1, Peripheral Reset Set Register 1, Peripheral + * Reset Clear Register 1 + */ + +#define SCU_PR2_WDTRS (1 << 1) /* Bit 1: WDT Reset */ +#define SCU_PR2_ETH0RS (1 << 2) /* Bit 2: ETH0 Reset */ +#define SCU_PR2_DMA0RS (1 << 4) /* Bit 4: DMA0 Reset */ +#define SCU_PR2_DMA1RS (1 << 5) /* Bit 5: DMA1 Reset */ +#define SCU_PR2_FCERS (1 << 6) /* Bit 6: FCE Reset */ +#define SCU_PR2_USBRS (1 << 7) /* Bit 7: USB Reset */ + +/* Peripheral Reset Status Register 3, Peripheral Reset Set Register 3, Peripheral + * Reset Clear Register 3 + */ + +#define SCU_PR3_EBURS (1 << 2) /* Bit 2: EBU Reset */ /* Clock Control SCU Registers */ -/* Clock Status Register */ -#define SCU_CLKSTAT_ -/* Clock Set Control Register */ -#define SCU_CLKSET_ -/* Clock clear Control Register */ -#define SCU_CLKCLR_ +/* Clock Status Register, Clock Set Control Register, Clock clear Control Register */ + +#define SCU_CLK_USBC (1 << 0) /* Bit 0: USB Clock */ +#define SCU_CLK_MMCC (1 << 1) /* Bit 1: MMC Clock */ +#define SCU_CLK_ETH0C (1 << 2) /* Bit 2: Ethernet Clock */ +#define SCU_CLK_EBUC (1 << 3) /* Bit 3: EBU Clock */ +#define SCU_CLK_CCUC (1 << 4) /* Bit 4: CCU Clock */ +#define SCU_CLK_WDTC (1 << 5) /* Bit 5: WDT Clock */ /* System Clock Control */ @@ -764,7 +790,10 @@ #define SCU_CPUCLKCR_CPUDIV (1 << 0) /* Bit 0: CPU Clock Divider Enable */ /* Peripheral Bus Clock Control */ -#define SCU_PBCLKCR_ + +#define SCU_PBCLKCR_PBDIV_Pos (1 << 0) /* Bit 0: PB Clock Divider Enable */ +# define SCU_PBCLKCR_PBDIV_FCPU (0) /* 0=fCPU */ +# define SCU_PBCLKCR_PBDIV_DIV2 ((1 << 0) /* 1=fCPU/2 */ /* USB Clock Control */ @@ -776,13 +805,39 @@ # define SCU_USBCLKCR_USBSEL_PLL (1 << 16) /* 1= PLL Clock */ /* EBU Clock Control */ -#define SCU_EBUCLKCR_ + +#define SCU_EBUCLKCR_EBUDIV_SHIFT (0) /* Bitx 0-5: EBU Clock Divider Value */ +#define SCU_EBUCLKCR_EBUDIV_MASK (0x3f << SCU_EBUCLKCR_EBUDIV_SHIFT) +# define SCU_EBUCLKCR_EBUDIV(n) ((uint32_t)((n)-1) << SCU_EBUCLKCR_EBUDIV_SHIFT) + /* CCU Clock Control */ -#define SCU_CCUCLKCR_ + +#define SCU_CCUCLKCR_CCUDIV_Pos (1 << 0) /* Bit 0: CCU Clock Divider Enable */ +# define SCU_CCUCLKCR_CCUDIV_FSYS (0) /* 0= SYS */ +# define SCU_CCUCLKCR_CCUDIV_DIV2 (1 << 0) /* 1=fSYS/2 */ + /* WDT Clock Control */ -#define SCU_WDTCLKCR_ + +#define SCU_WDTCLKCR_WDTDIV_SHIFT (0) /* Bits 0-7: WDT Clock Divider Value */ +#define SCU_WDTCLKCR_WDTDIV_MASK (0xff << SCU_WDTCLKCR_WDTDIV_SHIFT) +# define SCU_WDTCLKCR_WDTDIV(n) ((uint32_t)((n)-1) << SCU_WDTCLKCR_WDTDIV_SHIFT) +#define SCU_WDTCLKCR_WDTSEL_SHIFT (16) /* Bits 16-17: WDT Clock Selection Value */ +#define SCU_WDTCLKCR_WDTSEL_MASK (3 << SCU_WDTCLKCR_WDTSEL_SHIFT) +# define SCU_WDTCLKCR_WDTSEL_FOFI (0 << SCU_WDTCLKCR_WDTSEL_SHIFT) /* fOFI clock */ +# define SCU_WDTCLKCR_WDTSEL_FSTDY (1 << SCU_WDTCLKCR_WDTSEL_SHIFT) /* fSTDBY clock */ +# define SCU_WDTCLKCR_WDTSEL_FPLL (2 << SCU_WDTCLKCR_WDTSEL_SHIFT) /* fPLL clock */ + /* External clock Control Register */ -#define SCU_EXTCLKCR_ + +#define SCU_EXTCLKCR_ECKSEL_SHIFT (0) /* Bits 0-1: External Clock Selection Value */ +#define SCU_EXTCLKCR_ECKSEL_MASK (3 << SCU_EXTCLKCR_ECKSEL_SHIFT) +# define SCU_EXTCLKCR_ECKSEL_FSYS (0 << SCU_EXTCLKCR_ECKSEL_SHIFT) /* fSYS clock */ +# define SCU_EXTCLKCR_ECKSEL_FUSB (2 << SCU_EXTCLKCR_ECKSEL_SHIFT) /* fUSB clock divided by ECKDIV */ +# define SCU_EXTCLKCR_ECKSEL_FPLL (3 << SCU_EXTCLKCR_ECKSEL_SHIFT) /* fPLL clock divided by ECKDIV */ +#define SCU_EXTCLKCR_ECKDIV_SHIFT (16) /* Bits 16-24: External Clock Divider Value */ +#define SCU_EXTCLKCR_ECKDIV_MASK (0x1ff << SCU_EXTCLKCR_ECKDIV_SHIFT) +# define SCU_EXTCLKCR_ECKDIV(n) ((uint32_t)((n)-1) << SCU_EXTCLKCR_ECKDIV_SHIFT) + /* Sleep Control Register */ #define SCU_SLEEPCR_ /* Deep Sleep Control Register */ From 301e70b0731175caa03d2f22dda3fa1b6619de5e Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 18 Mar 2017 15:19:02 -0600 Subject: [PATCH 37/81] XMC4xxx: A few more SCU register definitions. --- arch/arm/src/xmc4/chip/xmc4_scu.h | 237 ++++++++++++++++++++++-------- 1 file changed, 178 insertions(+), 59 deletions(-) diff --git a/arch/arm/src/xmc4/chip/xmc4_scu.h b/arch/arm/src/xmc4/chip/xmc4_scu.h index 7e8b10bc7be..b48eebd824e 100644 --- a/arch/arm/src/xmc4/chip/xmc4_scu.h +++ b/arch/arm/src/xmc4/chip/xmc4_scu.h @@ -538,10 +538,10 @@ #define SCU_NMIREQEN_ /* Retention Memory Access Control Register */ -#define SCU_RMACR_RDWR (1 << 0) /* Bit 0: Hibernate Retention Memory Register Update Control */ -#define SCU_RMACR_ADDR_SHIFT (16) /* Bits 16-19: Hibernate Retention Memory Register Address Select */ -#define SCU_RMACR_ADDR_MASK (15 << SCU_RMACR_ADDR_SHIFT) -# define SCU_RMACR_ADDR(n) ((uint32_t)(n) << SCU_RMACR_ADDR_SHIFT) +#define SCU_RMACR_RDWR (1 << 0) /* Bit 0: Hibernate Retention Memory Register Update Control */ +#define SCU_RMACR_ADDR_SHIFT (16) /* Bits 16-19: Hibernate Retention Memory Register Address Select */ +#define SCU_RMACR_ADDR_MASK (15 << SCU_RMACR_ADDR_SHIFT) +# define SCU_RMACR_ADDR(n) ((uint32_t)(n) << SCU_RMACR_ADDR_SHIFT) /* Retention Memory Access Data Register (32-bit data) */ @@ -552,19 +552,98 @@ /* Parity Control Registers */ -#define SCU_PEEN_ +/* Parity Error Enable Register */ + +#define SCU_PEEN_PEENPS (1 << 0) /* Bit 0: Parity Error Enable for PSRAM */ +#define SCU_PEEN_PEENDS1 (1 << 1) /* Bit 1: Parity Error Enable for DSRAM1 */ +#define SCU_PEEN_PEENDS2 (1 << 2) /* Bit 2: Parity Error Enable for DSRAM2 */ +#define SCU_PEEN_PEENU0 (1 << 8) /* Bit 8: Parity Error Enable for USIC0 Memory */ +#define SCU_PEEN_PEENU1 (1 << 9) /* Bit 9: Parity Error Enable for USIC1 Memory */ +#define SCU_PEEN_PEENU2 (1 << 10) /* Bit 10: Parity Error Enable for USIC2 Memory */ +#define SCU_PEEN_PEENMC (1 << 12) /* Bit 12: Parity Error Enable for MultiCAN Memory */ +#define SCU_PEEN_PEENPPRF (1 << 13) /* Bit 13: Parity Error Enable for PMU Prefetch Memory */ +#define SCU_PEEN_PEENUSB (1 << 16) /* Bit 16: Parity Error Enable for USB Memory */ +#define SCU_PEEN_PEENETH0TX (1 << 17) /* Bit 17: Parity Error Enable for ETH TX Memory */ +#define SCU_PEEN_PEENETH0RX (1 << 18) /* Bit 18: Parity Error Enable for ETH RX Memory */ +#define SCU_PEEN_PEENSD0 (1 << 19) /* Bit 19: Parity Error Enable for SDMMC Memory 0 */ +#define SCU_PEEN_PEENSD1 (1 << 20) /* Bit 20: Parity Error Enable for SDMMC Memory 1 */ + /* Memory Checking Control Register */ -#define SCU_MCHKCON_ + +#define SCU_MCHKCON_SELPS (1 << 0) /* Bit 0: Select Memory Check for PSRAM */ +#define SCU_MCHKCON_SELDS1 (1 << 1) /* Bit 1: Select Memory Check for DSRAM1 */ +#define SCU_MCHKCON_SELDS2 (1 << 2) /* Bit 2: Select Memory Check for DSRAM2 */ +#define SCU_MCHKCON_USIC0DRA (1 << 8) /* Bit 8: Select Memory Check for USIC0 */ +#define SCU_MCHKCON_USIC1DRA (1 << 9) /* Bit 9: Select Memory Check for USIC1 */ +#define SCU_MCHKCON_USIC2DRA (1 << 10) /* Bit 10: Select Memory Check for USIC2 */ +#define SCU_MCHKCON_MCANDRA (1 << 12) /* Bit 12: Select Memory Check for MultiCAN */ +#define SCU_MCHKCON_PPRFDRA (1 << 13) /* Bit 13: Select Memory Check for PMU */ +#define SCU_MCHKCON_SELUSB (1 << 16) /* Bit 16: Select Memory Check for USB SRAM */ +#define SCU_MCHKCON_SELETH0TX (1 << 17) /* Bit 17: Select Memory Check for ETH0 TX SRAM */ +#define SCU_MCHKCON_SELETH0RX (1 << 18) /* Bit 18: Select Memory Check for ETH0 RX SRAM */ +#define SCU_MCHKCON_SELSD0 (1 << 19) /* Bit 19: Select Memory Check for SDMMC SRAM 0 */ +#define SCU_MCHKCON_SELSD1 (1 << 20) /* Bit 20: Select Memory Check for SDMMC SRAM 1 */ + /* Parity Error Trap Enable Register */ -#define SCU_PETE_ + +#define SCU_PETE_PETEPS (1 << 0) /* Bit 0: Parity Error Trap Enable for PSRAM */ +#define SCU_PETE_PETEDS1 (1 << 1) /* Bit 1: Parity Error Trap Enable for DSRAM1 */ +#define SCU_PETE_PETEDS2 (1 << 2) /* Bit 2: Parity Error Trap Enable for DSRAM2 */ +#define SCU_PETE_PETEU0 (1 << 8) /* Bit 8: Parity Error Trap Enable for USIC0 Memory */ +#define SCU_PETE_PETEU1 (1 << 9) /* Bit 9: Parity Error Trap Enable for USIC1 Memory */ +#define SCU_PETE_PETEU2 (1 << 10) /* Bit 10: Parity Error Trap Enable for USIC2 Memory */ +#define SCU_PETE_PETEMC (1 << 12) /* Bit 12: Parity Error Trap Enable for MultiCAN Memory */ +#define SCU_PETE_PETEPPRF (1 << 13) /* Bit 13: Parity Error Trap Enable for PMU Prefetch Memory */ +#define SCU_PETE_PETEUSB (1 << 16) /* Bit 16: Parity Error Trap Enable for USB Memory */ +#define SCU_PETE_PETEETH0TX (1 << 17) /* Bit 17: Parity Error Trap Enable for ETH0 TX Memory */ +#define SCU_PETE_PETEETH0RX (1 << 18) /* Bit 18: Parity Error Trap Enable for ETH0 RX Memory */ +#define SCU_PETE_PETESD0 (1 << 19) /* Bit 19: Parity Error Trap Enable for SDMMC SRAM 0 Memory */ +#define SCU_PETE_PETESD1 (1 << 20) /* Bit 20: Parity Error Trap Enable for SDMMC SRAM 1 Memory */ + /* Reset upon Parity Error Enable Register */ -#define SCU_PERSTEN_ + +#define SCU_PERSTEN_RSEN (1 << 0) /* Bit 0: System Reset Enable upon Parity Error Trap */ + /* Parity Error Control Register */ -#define SCU_PEFLAG_ + +#define SCU_PEFLAG_PEFPS (1 << 0) /* Bit 0: Parity Error Flag for PSRAM */ +#define SCU_PEFLAG_PEFDS1 (1 << 1) /* Bit 1: Parity Error Flag for DSRAM1 */ +#define SCU_PEFLAG_PEFDS2 (1 << 2) /* Bit 2: Parity Error Flag for DSRAM2 */ +#define SCU_PEFLAG_PEFU0 (1 << 8) /* Bit 8: Parity Error Flag for USIC0 Memory */ +#define SCU_PEFLAG_PEFU1 (1 << 9) /* Bit 9: Parity Error Flag for USIC1 Memory */ +#define SCU_PEFLAG_PEFU2 (1 << 10) /* Bit 10: Parity Error Flag for USIC2 Memory */ +#define SCU_PEFLAG_PEFMC (1 << 12) /* Bit 12: Parity Error Flag for MultiCAN Memory */ +#define SCU_PEFLAG_PEFPPRF (1 << 13) /* Bit 13: Parity Error Flag for PMU Prefetch Memory */ +#define SCU_PEFLAG_PEUSB (1 << 16) /* Bit 16: Parity Error Flag for USB Memory */ +#define SCU_PEFLAG_PEETH0TX (1 << 17) /* Bit 17: Parity Error Flag for ETH TX Memory */ +#define SCU_PEFLAG_PEETH0RX (1 << 18) /* Bit 18: Parity Error Flag for ETH RX Memory */ +#define SCU_PEFLAG_PESD0 (1 << 19) /* Bit 19: Parity Error Flag for SDMMC Memory 0 */ +#define SCU_PEFLAG_PESD1 (1 << 20) /* Bit 20: Parity Error Flag for SDMMC Memory 1 */ + /* Parity Memory Test Pattern Register */ -#define SCU_PMTPR_ + +#define SCU_PMTPR_PWR_SHIFT (0) /* Bits 0-7: Parity Read Values for Memory Test */ +#define SCU_PMTPR_PWR_MASK (0xff << SCU_PMTPR_PWR_SHIFT) +# define SCU_PMTPR_PWR(n) ((uint32_t)(n) << SCU_PMTPR_PWR_SHIFT) +#define SCU_PMTPR_PRD_SHIFT (8) /* Bits 8-15: Parity Write Values for Memory Test */ +#define SCU_PMTPR_PRD_MASK (0xff << SCU_PMTPR_PRD_SHIFT) +# define SCU_PMTPR_PRD(n) ((uint32_t)(n) << SCU_PMTPR_PRD_SHIFT) + /* Parity Memory Test Select Register */ -#define SCU_PMTSR_ + +#define SCU_PMTSR_MTENPS (1 << 0) /* Bit 0: Test Enable Control for PSRAM */ +#define SCU_PMTSR_MTENDS1 (1 << 1) /* Bit 1: Test Enable Control for DSRAM1 */ +#define SCU_PMTSR_MTENDS2 (1 << 2) /* Bit 2: Test Enable Control for DSRAM2 */ +#define SCU_PMTSR_MTEU0 (1 << 8) /* Bit 8: Test Enable Control for USIC0 Memory */ +#define SCU_PMTSR_MTEU1 (1 << 9) /* Bit 9: Test Enable Control for USIC1 Memory */ +#define SCU_PMTSR_MTEU2 (1 << 10) /* Bit 10: Test Enable Control for USIC2 Memory */ +#define SCU_PMTSR_MTEMC (1 << 12) /* Bit 12: Test Enable Control for MultiCAN Memory */ +#define SCU_PMTSR_MTEPPRF (1 << 13) /* Bit 13: Test Enable Control for PMU Prefetch Memory */ +#define SCU_PMTSR_MTUSB (1 << 16) /* Bit 16: Test Enable Control for USB Memory */ +#define SCU_PMTSR_MTETH0TX (1 << 17) /* Bit 17: Test Enable Control for ETH TX Memory */ +#define SCU_PMTSR_MTETH0RX (1 << 18) /* Bit 18: Test Enable Control for ETH RX Memory */ +#define SCU_PMTSR_MTSD0 (1 << 19) /* Bit 19: Test Enable Control for SDMMC Memory 0 */ +#define SCU_PMTSR_MTSD1 (1 << 20) /* Bit 20: Test Enable Control for SDMMC Memory 1 */ /* Trap Control Registers */ @@ -791,7 +870,7 @@ /* Peripheral Bus Clock Control */ -#define SCU_PBCLKCR_PBDIV_Pos (1 << 0) /* Bit 0: PB Clock Divider Enable */ +#define SCU_PBCLKCR_PBDIV (1 << 0) /* Bit 0: PB Clock Divider Enable */ # define SCU_PBCLKCR_PBDIV_FCPU (0) /* 0=fCPU */ # define SCU_PBCLKCR_PBDIV_DIV2 ((1 << 0) /* 1=fCPU/2 */ @@ -812,65 +891,102 @@ /* CCU Clock Control */ -#define SCU_CCUCLKCR_CCUDIV_Pos (1 << 0) /* Bit 0: CCU Clock Divider Enable */ -# define SCU_CCUCLKCR_CCUDIV_FSYS (0) /* 0= SYS */ -# define SCU_CCUCLKCR_CCUDIV_DIV2 (1 << 0) /* 1=fSYS/2 */ +#define SCU_CCUCLKCR_CCUDIV (1 << 0) /* Bit 0: CCU Clock Divider Enable */ +# define SCU_CCUCLKCR_CCUDIV_FSYS (0) /* 0= SYS */ +# define SCU_CCUCLKCR_CCUDIV_DIV2 (1 << 0) /* 1=fSYS/2 */ /* WDT Clock Control */ -#define SCU_WDTCLKCR_WDTDIV_SHIFT (0) /* Bits 0-7: WDT Clock Divider Value */ -#define SCU_WDTCLKCR_WDTDIV_MASK (0xff << SCU_WDTCLKCR_WDTDIV_SHIFT) -# define SCU_WDTCLKCR_WDTDIV(n) ((uint32_t)((n)-1) << SCU_WDTCLKCR_WDTDIV_SHIFT) -#define SCU_WDTCLKCR_WDTSEL_SHIFT (16) /* Bits 16-17: WDT Clock Selection Value */ -#define SCU_WDTCLKCR_WDTSEL_MASK (3 << SCU_WDTCLKCR_WDTSEL_SHIFT) -# define SCU_WDTCLKCR_WDTSEL_FOFI (0 << SCU_WDTCLKCR_WDTSEL_SHIFT) /* fOFI clock */ -# define SCU_WDTCLKCR_WDTSEL_FSTDY (1 << SCU_WDTCLKCR_WDTSEL_SHIFT) /* fSTDBY clock */ -# define SCU_WDTCLKCR_WDTSEL_FPLL (2 << SCU_WDTCLKCR_WDTSEL_SHIFT) /* fPLL clock */ +#define SCU_WDTCLKCR_WDTDIV_SHIFT (0) /* Bits 0-7: WDT Clock Divider Value */ +#define SCU_WDTCLKCR_WDTDIV_MASK (0xff << SCU_WDTCLKCR_WDTDIV_SHIFT) +# define SCU_WDTCLKCR_WDTDIV(n) ((uint32_t)((n)-1) << SCU_WDTCLKCR_WDTDIV_SHIFT) +#define SCU_WDTCLKCR_WDTSEL_SHIFT (16) /* Bits 16-17: WDT Clock Selection Value */ +#define SCU_WDTCLKCR_WDTSEL_MASK (3 << SCU_WDTCLKCR_WDTSEL_SHIFT) +# define SCU_WDTCLKCR_WDTSEL_FOFI (0 << SCU_WDTCLKCR_WDTSEL_SHIFT) /* fOFI clock */ +# define SCU_WDTCLKCR_WDTSEL_FSTDY (1 << SCU_WDTCLKCR_WDTSEL_SHIFT) /* fSTDBY clock */ +# define SCU_WDTCLKCR_WDTSEL_FPLL (2 << SCU_WDTCLKCR_WDTSEL_SHIFT) /* fPLL clock */ /* External clock Control Register */ -#define SCU_EXTCLKCR_ECKSEL_SHIFT (0) /* Bits 0-1: External Clock Selection Value */ -#define SCU_EXTCLKCR_ECKSEL_MASK (3 << SCU_EXTCLKCR_ECKSEL_SHIFT) -# define SCU_EXTCLKCR_ECKSEL_FSYS (0 << SCU_EXTCLKCR_ECKSEL_SHIFT) /* fSYS clock */ -# define SCU_EXTCLKCR_ECKSEL_FUSB (2 << SCU_EXTCLKCR_ECKSEL_SHIFT) /* fUSB clock divided by ECKDIV */ -# define SCU_EXTCLKCR_ECKSEL_FPLL (3 << SCU_EXTCLKCR_ECKSEL_SHIFT) /* fPLL clock divided by ECKDIV */ -#define SCU_EXTCLKCR_ECKDIV_SHIFT (16) /* Bits 16-24: External Clock Divider Value */ -#define SCU_EXTCLKCR_ECKDIV_MASK (0x1ff << SCU_EXTCLKCR_ECKDIV_SHIFT) -# define SCU_EXTCLKCR_ECKDIV(n) ((uint32_t)((n)-1) << SCU_EXTCLKCR_ECKDIV_SHIFT) +#define SCU_EXTCLKCR_ECKSEL_SHIFT (0) /* Bits 0-1: External Clock Selection Value */ +#define SCU_EXTCLKCR_ECKSEL_MASK (3 << SCU_EXTCLKCR_ECKSEL_SHIFT) +# define SCU_EXTCLKCR_ECKSEL_FSYS (0 << SCU_EXTCLKCR_ECKSEL_SHIFT) /* fSYS clock */ +# define SCU_EXTCLKCR_ECKSEL_FUSB (2 << SCU_EXTCLKCR_ECKSEL_SHIFT) /* fUSB clock divided by ECKDIV */ +# define SCU_EXTCLKCR_ECKSEL_FPLL (3 << SCU_EXTCLKCR_ECKSEL_SHIFT) /* fPLL clock divided by ECKDIV */ +#define SCU_EXTCLKCR_ECKDIV_SHIFT (16) /* Bits 16-24: External Clock Divider Value */ +#define SCU_EXTCLKCR_ECKDIV_MASK (0x1ff << SCU_EXTCLKCR_ECKDIV_SHIFT) +# define SCU_EXTCLKCR_ECKDIV(n) ((uint32_t)((n)-1) << SCU_EXTCLKCR_ECKDIV_SHIFT) /* Sleep Control Register */ -#define SCU_SLEEPCR_ + +#define SCU_SLEEPCR_SYSSEL (1 << 0) /* Bit 0: System Clock Selection Value */ +# define SCU_SLEEPCR_SYSSEL_OFI (0) /* 0=fOFI */ +# define SCU_SLEEPCR_SYSSEL_ PLL (1 << 0) /* 1=fPLL */ +#define SCU_SLEEPCR_USBCR (1 << 16) /* Bit 6: USB Clock Control in Sleep Mode */ +#define SCU_SLEEPCR_MMCCR (1 << 17) /* Bit 17: MMC Clock Control in Sleep Mode */ +#define SCU_SLEEPCR_ETH0CR (1 << 18) /* Bit 18: Ethernet Clock Control in Sleep Mode */ +#define SCU_SLEEPCR_EBUCR (1 << 19) /* Bit 19: EBU Clock Control in Sleep Mode */ +#define SCU_SLEEPCR_CCUCR (1 << 20) /* Bit 20: CCU Clock Control in Sleep Mode */ +#define SCU_SLEEPCR_WDTCR (1 << 21) /* Bit 21: WDT Clock Control in Sleep Mode */ + /* Deep Sleep Control Register */ -#define SCU_DSLEEPCR_ -/* Peripheral 0 Clock Gating Status */ -#define SCU_CGATSTAT0_ -/* Peripheral 0 Clock Gating Set */ -#define SCU_CGATSET0_ -/* Peripheral 0 Clock Gating Clear */ -#define SCU_CGATCLR0_ -/* Peripheral 1 Clock Gating Status */ -#define SCU_CGATSTAT1_ -/* Peripheral 1 Clock Gating Set */ -#define SCU_CGATSET1_ -/* Peripheral 1 Clock Gating Clear */ -#define SCU_CGATCLR1_ -/* Peripheral 2 Clock Gating Status */ -#define SCU_CGATSTAT2_ -/* Peripheral 2 Clock Gating Set */ -#define SCU_CGATSET2_ -/* Peripheral 2 Clock Gating Clear */ -#define SCU_CGATCLR2_ -/* Peripheral 3 Clock Gating Status */ -#define SCU_CGATSTAT3_ -/* Peripheral 3 Clock Gating Set */ -#define SCU_CGATSET3_ -/* Peripheral 3 Clock Gating Clear */ -#define SCU_CGATCLR3_ + +#define SCU_DSLEEPCR_SYSSEL (1 << 0) /* Bit 0: System Clock Selection Value */ +# define SCU_DSLEEPCR_SYSSEL_FOFI (0) /* 0=fOFI */ +# define SCU_DSLEEPCR_SYSSEL_FPLL (1 << 0) /* 1=fPLL */ +#define SCU_DSLEEPCR_FPDN (1 << 11) /* Bit 11: Flash Power Down */ +#define SCU_DSLEEPCR_PLLPDN (1 << 12) /* Bit 12: PLL Power Down */ +#define SCU_DSLEEPCR_VCOPDN (1 << 13) /* Bit 13: PLL Power Down */ +#define SCU_DSLEEPCR_USBCR (1 << 16) /* Bit 16: USB Clock Control in Deep Sleep Mode */ +#define SCU_DSLEEPCR_MMCCR (1 << 17) /* Bit 17: MMC Clock Control in Deep Sleep Mode */ +#define SCU_DSLEEPCR_ETH0CR (1 << 18) /* Bit 18: Ethernet Clock Control in Deep Sleep Mode */ +#define SCU_DSLEEPCR_EBUCR (1 << 19) /* Bit 19: EBU Clock Control in Deep Sleep Mode */ +#define SCU_DSLEEPCR_CCUCR (1 << 20) /* Bit 20: CCU Clock Control in Deep Sleep Mod */ +#define SCU_DSLEEPCR_WDTCR (1 << 21) /* Bit 21: WDT Clock Control in Deep Sleep Mode */ + +/* Peripheral 0 Clock Gating Status, Peripheral 0 Clock Gating Set, Peripheral 0 Clock Gating Clear */ + +#define SCU_CGAT0_VADC (1 << 0) /* Bit 0: */ +#define SCU_CGAT0_DSD (1 << 1) /* Bit 1: */ +#define SCU_CGAT0_CCU40 (1 << 2) /* Bit 2: */ +#define SCU_CGAT0_CCU41 (1 << 3) /* Bit 3: */ +#define SCU_CGAT0_CCU42 (1 << 4) /* Bit 4: */ +#define SCU_CGAT0_CCU80 (1 << 7) /* Bit 7: */ +#define SCU_CGAT0_CCU81 (1 << 8) /* Bit 8: */ +#define SCU_CGAT0_POSIF0 (1 << 9) /* Bit 9: */ +#define SCU_CGAT0_POSIF1 (1 << 10) /* Bit 10: */ +#define SCU_CGAT0_USIC0 (1 << 11) /* Bit 11: */ +#define SCU_CGAT0_ERU1_ (1 << 16) /* Bit 16: */ + +/* Peripheral 1 Clock Gating Status, Peripheral 1 Clock Gating Set, Peripheral 1 Clock Gating Clear */ + +#define SCU_CGATSTAT1_CCU43 (1 << 0) /* Bit 0: */ +#define SCU_CGATSTAT1_LEDTSCU0 (1 << 3) /* Bit 3: */ +#define SCU_CGATSTAT1_MCAN0 (1 << 4) /* Bit 4: */ +#define SCU_CGATSTAT1_DAC (1 << 5) /* Bit 5: */ +#define SCU_CGATSTAT1_MMCI (1 << 6) /* Bit 6: */ +#define SCU_CGATSTAT1_USIC1 (1 << 7) /* Bit 7: */ +#define SCU_CGATSTAT1_USIC2 (1 << 8) /* Bit 8: */ +#define SCU_CGATSTAT1_PPORTS (1 << 9) /* Bit 9: */ + +/* Peripheral 2 Clock Gating Status, Peripheral 2 Clock Gating Set, Peripheral 2 Clock Gating Clear */ + +#define SCU_CGATSTAT2_WDT (1 << 1) /* Bit 1: */ +#define SCU_CGATSTAT2_ETH0 (1 << 2) /* Bit 2: */ +#define SCU_CGATSTAT2_DMA0 (1 << 4) /* Bit 4: */ +#define SCU_CGATSTAT2_DMA1 (1 << 5) /* Bit 5: */ +#define SCU_CGATSTAT2_FCE (1 << 6) /* Bit 6: */ +#define SCU_CGATSTAT2_USB (1 << 7) /* Bit 7: */ + +/* Peripheral 3 Clock Gating Status, Peripheral 3 Clock Gating Set, Peripheral 3 Clock Gating Clear */ + +#define SCU_CGATSTAT3_EBU (1 << 2) /* Bit 2: */ /* Oscillator Control SCU Registers */ /* OSC_HP Status Register */ -#define SCU_OSCHPSTAT_ + +#define SCU_OSCHPSTAT_X1D (1 << 0) /* Bit 0: XTAL1 Data Value */ /* OSC_HP Control Register */ @@ -890,7 +1006,10 @@ # define SCU_OSCHPCTRL_OSCVAL(n) ((uint32_t)((n)-1) << SCU_OSCHPCTRL_OSCVAL_SHIFT) /* Clock Calibration Constant Register */ -#define SCU_CLKCALCONST_ + +#define SCU_CLKCALCONST_CALIBCONST_SHIFT (0) /* Bits 0-3: Clock Calibration Constant Value */ +#define SCU_CLKCALCONST_CALIBCONST_MASK (15 << SCU_CLKCALCONST_CALIBCONST_SHIFT) +# define SCU_CLKCALCONST_CALIBCONST(n) ((uint32_t)(n) << SCU_CLKCALCONST_CALIBCONST_SHIFT) /* PLL Control SCU Registers */ From e82a3b3ca7f84b159c7daeb72d46e25e186aedbe Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 18 Mar 2017 16:13:59 -0600 Subject: [PATCH 38/81] XMC4xxx: Completes most SCU register definitions. --- arch/arm/src/xmc4/chip/xmc4_scu.h | 75 ++++++++++++++++++++++--------- 1 file changed, 55 insertions(+), 20 deletions(-) diff --git a/arch/arm/src/xmc4/chip/xmc4_scu.h b/arch/arm/src/xmc4/chip/xmc4_scu.h index b48eebd824e..fee8e55b8f4 100644 --- a/arch/arm/src/xmc4/chip/xmc4_scu.h +++ b/arch/arm/src/xmc4/chip/xmc4_scu.h @@ -318,11 +318,11 @@ #define XMC4_SCU_CGATSET1 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATSET1_OFFSET) #define XMC4_SCU_CGATCLR1 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATCLR1_OFFSET) #define XMC4_SCU_CGATSTAT2 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATSTAT2_OFFSET) -#define XMC4_SCU_CGATSET2 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATSET2_OFFSET -#define XMC4_SCU_CGATCLR2 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATCLR2_OFFSET -#define XMC4_SCU_CGATSTAT3 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATSTAT3_OFFSET -#define XMC4_SCU_CGATSET3 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATSET3_OFFSET -#define XMC4_SCU_CGATCLR3 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATCLR3_OFFSET_ +#define XMC4_SCU_CGATSET2 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATSET2_OFFSET) +#define XMC4_SCU_CGATCLR2 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATCLR2_OFFSET) +#define XMC4_SCU_CGATSTAT3 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATSTAT3_OFFSET) +#define XMC4_SCU_CGATSET3 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATSET3_OFFSET) +#define XMC4_SCU_CGATCLR3 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATCLR3_OFFSET) /* Oscillator Control SCU Registers */ @@ -524,18 +524,38 @@ /* Interrupt Control SCU Registers */ -/* Service Request Status */ -#define SCU_SRSTAT_ -/* RAW Service Request Status */ -#define SCU_SRRAW_ -/* Service Request Mask */ -#define SCU_SRMSK_ -/* Service Request Clear */ -#define SCU_SRCLR_ -/* Service Request Set */ -#define SCU_SRSET_ +/* Service Request Status, RAW Service Request Status, Service Request Mask, Service + * Request Clear, Service Request Set + */ + +#define SCU_INT_PRWARN (1 << 0) /* Bit 0: WDT pre-warning Interrupt */ +#define SCU_INT_PI (1 << 1) /* Bit 1: RTC Periodic Interrupt */ +#define SCU_INT_AI (1 << 2) /* Bit 2: Alarm Interrupt */ +#define SCU_INT_DLROVR (1 << 3) /* Bit 3: DLR Request Overrun Interrupt */ +#define SCU_INT_HDSTAT (1 << 16) /* Bit 16: HDSTAT Mirror Register Update */ +#define SCU_INT_HDCLR (1 << 17) /* Bit 17: HDCLR Mirror Register Update */ +#define SCU_INT_HDSET (1 << 18) /* Bit 18: HDSET Mirror Register Update */ +#define SCU_INT_HDCR (1 << 19) /* Bit 19: HDCR Mirror Register Update */ +#define SCU_INT_OSCSICTRL (1 << 21) /* Bit 21: OSCSICTRL Mirror Register Update */ +#define SCU_INT_OSCULSTAT (1 << 22) /* Bit 22: OSCULTAT Mirror Register Update */ +#define SCU_INT_OSCULCTRL (1 << 23) /* Bit 23: OSCULCTRL Mirror Register Update */ +#define SCU_INT_RTC_CTR (1 << 24) /* Bit 24: RTC CTR Mirror Register Update */ +#define SCU_INT_RTC_ATIM0 (1 << 25) /* Bit 25: RTC ATIM0 Mirror Register Update */ +#define SCU_INT_RTC_ATIM1 (1 << 26) /* Bit 26: RTC ATIM1 Mirror Register Update */ +#define SCU_INT_RTC_TIM0 (1 << 27) /* Bit 27: RTC TIM0 Mirror Register Update */ +#define SCU_INT_RTC_TIM1 (1 << 28) /* Bit 28: RTC TIM1 Mirror Register Update */ +#define SCU_INTT_RMX (1 << 29) /* Bit 29: Retention Memory Mirror Register */ + /* Enable Promoting Events to NMI Request */ -#define SCU_NMIREQEN_ + +#define SCU_NMIREQEN_PRWARN (1 << 0) /* Bit 0: Promote Pre-Warning Interrupt Request to NMI Request */ +#define SCU_NMIREQEN_PI (1 << 1) /* Bit 1: Promote RTC Periodic Interrupt request to NMI Request */ +#define SCU_NMIREQEN_AI (1 << 2) /* Bit 2: Promote RTC Alarm Interrupt Request to NMIRequest */ +#define SCU_NMIREQEN_ERU00 (1 << 16) /* Bit 16: Promote Channel 0 Interrupt of ERU0 Request to NMI Request */ +#define SCU_NMIREQEN_ERU01 (1 << 17) /* Bit 17: Promote Channel 1 Interrupt of ERU0 Request to NMI Request */ +#define SCU_NMIREQEN_ERU02 (1 << 18) /* Bit 18: Promote Channel 2 Interrupt of ERU0 Request to NMI Request */ +#define SCU_NMIREQEN_ERU03 (1 << 19) /* Bit 19: Promote Channel 3 Interrupt of ERU0 Request to NMI Request */ + /* Retention Memory Access Control Register */ #define SCU_RMACR_RDWR (1 << 0) /* Bit 0: Hibernate Retention Memory Register Update Control */ @@ -672,11 +692,25 @@ #define SCU_PWR_USBPUWQ (1 << 18) /* Bit 18: USB Weak Pull-Up at PADN State */ /* EVR Status Register */ -#define SCU_EVRSTAT_ + +#define SCU_EVRSTAT_OV13 (1 << 1) /* Bit 1: Regulator Overvoltage for 1.3 V */ + /* EVR VADC Status Register */ -#define SCU_EVRVADCSTAT_ + +#define SCU_EVRVADCSTAT_VADC13V_SHIFT (0) /* Bits 0-7: VADC 1.3 V Conversion Result */ +#define SCU_EVRVADCSTAT_VADC13V_MASK (0xff << SCU_EVRVADCSTAT_VADC13V_SHIFT) +#define SCU_EVRVADCSTAT_VADC33V_SHIFT (8) /* Bits 8-15: VADC 3.3 V Conversion Result */ +#define SCU_EVRVADCSTAT_VADC33V_MASK (0xff << SCU_EVRVADCSTAT_VADC33V_SHIFT) + /* Power Monitor Value */ -#define SCU_PWRMON_ + +#define SCU_PWRMON_THRS_SHIFT (0) /* Bits 0-7: Threshold */ +#define SCU_PWRMON_THRS_MASK (0xff << SCU_POWER_PWRMON_THRS_SHIFT) +# define SCU_PWRMON_THRS(n) ((uint32_t)(n) << SCU_POWER_PWRMON_THRS_SHIFT) +#define SCU_PWRMON_INTV_SHIFT (8) /* Bits 8-15: Interval */ +#define SCU_PWRMON_INTV_MASK (0xff << SCU_POWER_PWRMON_INTV_SHIFT) +# define SCU_PWRMON_INTV(n) ((uint32_t)(n) << SCU_POWER_PWRMON_INTV_SHIFT) +#define SCU_PWRMON_ENB (1 << 16) /* Bit 16: Enable */ /* Hibernation SCU Registers */ /* Hibernate Domain Status Register */ @@ -750,7 +784,8 @@ # define SCU_HDCR_HIBIO1SEL_ODGPIO (14 << SCU_HDCR_HIBIO1SEL_SHIFT) /* Open-drain GPIO output */ /* Internal 32.768 kHz Clock Source Control Register */ -#define SCU_OSCSICTRL_ + +#define SCU_OSCSICTRL_PWD (1 << 0) /* Bit 0: Turn OFF the fOSI Clock Source */ /* OSC_ULP Status Register */ From 47cd105e322040d20aafc1fd53b0803cf09141c5 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 18 Mar 2017 16:41:33 -0600 Subject: [PATCH 39/81] XMC4xxxx: Final clean-up of SCU heder file --- arch/arm/src/xmc4/chip/xmc4_scu.h | 401 ++++++++++++++---------------- 1 file changed, 190 insertions(+), 211 deletions(-) diff --git a/arch/arm/src/xmc4/chip/xmc4_scu.h b/arch/arm/src/xmc4/chip/xmc4_scu.h index fee8e55b8f4..0618e7e02b0 100644 --- a/arch/arm/src/xmc4/chip/xmc4_scu.h +++ b/arch/arm/src/xmc4/chip/xmc4_scu.h @@ -79,14 +79,11 @@ #define XMC4_SCU_SDMMCDEL_OFFSET 0x009c /* SD-MMC Delay Control Register */ #define XMC4_SCU_G0ORCEN_OFFSET 0x00a0 /* Out-Of-Range Comparator Enable Register 0 */ #define XMC4_SCU_G1ORCEN_OFFSET 0x00a4 /* Out-Of-Range Comparator Enable Register 1 */ +#define XMC4_SCU_SDMMCCON_OFFSET 0x00b4 /* SDMMC Configuration */ #define XMC4_SCU_MIRRSTS_OFFSET 0x00c4 /* Mirror Update Status Register */ #define XMC4_SCU_RMACR_OFFSET 0x00c8 /* Retention Memory Access Control Register */ #define XMC4_SCU_RMADATA_OFFSET 0x00cc /* Retention Memory Access Data Register */ -/* Ethernet Control SCU Resters */ - -#define XMC4_SCU_ETHCON_OFFSET 0x0000 /* Ethernet 0 Port Control Register */ - /* Interrupt Control SCU Registers */ #define XMC4_SCU_SRSTAT_OFFSET 0x0000 /* Service Request Status */ @@ -96,10 +93,6 @@ #define XMC4_SCU_SRSET_OFFSET 0x0010 /* Service Request Set */ #define XMC4_SCU_NMIREQEN_OFFSET 0x0014 /* Enable Promoting Events to NMI Request */ -/* SDMMC Control SCU Registers */ - -#define XMC4_SCU_SDMMCCON_OFFSET 0x0000 /* SDMMC Configuration */ - /* Parity Control Registers */ #define XMC4_SCU_PEEN_OFFSET 0x0000 /* Parity Error Enable Register */ @@ -215,14 +208,11 @@ #define XMC4_SCU_SDMMCDEL (XMC4_SCU_GENERAL_BASE+XMC4_SCU_SDMMCDEL_OFFSET) #define XMC4_SCU_G0ORCEN (XMC4_SCU_GENERAL_BASE+XMC4_SCU_G0ORCEN_OFFSET) #define XMC4_SCU_G1ORCEN (XMC4_SCU_GENERAL_BASE+XMC4_SCU_G1ORCEN_OFFSET) +#define XMC4_SCU_SDMMCCON (XMC4_SDMMC_CON_BASE+XMC4_SCU_SDMMCCON_OFFSET) #define XMC4_SCU_MIRRSTS (XMC4_SCU_GENERAL_BASE+XMC4_SCU_MIRRSTS_OFFSET) #define XMC4_SCU_RMACR (XMC4_SCU_GENERAL_BASE+XMC4_SCU_RMACR_OFFSET) #define XMC4_SCU_RMADATA (XMC4_SCU_GENERAL_BASE+XMC4_SCU_RMADATA_OFFSET) -/* Ethernet Control SCU Registers */ - -#define XMC4_SCU_ETHCON (XMC4_ETH0_CON_BASE+XMC4_SCU_ETHCON_OFFSET) - /* Parity Control Registers */ #define XMC4_SCU_PEEN (XMC4_SCU_PARITY_BASE+XMC4_SCU_PEEN_OFFSET) @@ -241,11 +231,6 @@ #define XMC4_SCU_TRAPCLR (XMC4_SCU_TRAP_BASE+XMC4_SCU_TRAPCLR_OFFSET) #define XMC4_SCU_TRAPSET (XMC4_SCU_TRAP_BASE+XMC4_SCU_TRAPSET_OFFSET) -/* Ethernet Control SCU Resters */ - -#define XMC4_SCU_ETHCON_OFFSET 0x0000 /* Ethernet 0 Port Control Register */ -#define XMC4_SCU_ETHCON_OFFSET 0x0000 /* Ethernet 0 Port Control Register */ - /* Interrupt Control SCU Registers */ #define XMC4_SCU_SRSTAT (XMC4_SCU_INTERRUPT_BASE+XMC4_SCU_SRSTAT_OFFSET) @@ -255,10 +240,6 @@ #define XMC4_SCU_SRSET (XMC4_SCU_INTERRUPT_BASE+XMC4_SCU_SRSET_OFFSET) #define XMC4_SCU_NMIREQEN (XMC4_SCU_INTERRUPT_BASE+XMC4_SCU_NMIREQEN_OFFSET) -/* SDMMC Control SCU Registers */ - -#define XMC4_SCU_SDMMCCON (XMC4_SDMMC_CON_BASE+XMC4_SCU_SDMMCCON_OFFSET) - /* Power control SCU Registers */ #define XMC4_SCU_PWRSTAT (XMC4_SCU_POWER_BASE+XMC4_SCU_PWRSTAT_OFFSET) @@ -346,159 +327,166 @@ /* Module Identification Register (32-bit Chip ID) */ -#define SCU_ID_MOD_REV_SHIFT (0) /* Bits 0-7: Module Revision Number */ -#define SCU_ID_MOD_REV_MASK (0xff << SCU_ID_MOD_REV_SHIFT) -#define SCU_ID_MOD_TYPE_SHIFT (8) /* Bits 8-15: Module Type */ -#define SCU_ID_MOD_TYPE_MASK (0xff << SCU_ID_MOD_REV_SHIFT) -#define SCU_ID_MOD_NUMBER_SHIFT (16) /* Bits 16-31: Module Number Value */ -#define SCU_ID_MOD_NUMBER_MASK (0xffff << SCU_ID_MOD_NUMBER_SHIFT) +#define SCU_ID_MOD_REV_SHIFT (0) /* Bits 0-7: Module Revision Number */ +#define SCU_ID_MOD_REV_MASK (0xff << SCU_ID_MOD_REV_SHIFT) +#define SCU_ID_MOD_TYPE_SHIFT (8) /* Bits 8-15: Module Type */ +#define SCU_ID_MOD_TYPE_MASK (0xff << SCU_ID_MOD_REV_SHIFT) +#define SCU_ID_MOD_NUMBER_SHIFT (16) /* Bits 16-31: Module Number Value */ +#define SCU_ID_MOD_NUMBER_MASK (0xffff << SCU_ID_MOD_NUMBER_SHIFT) /* Chip ID (32-bit Chip ID) */ /* Manufactory ID */ -#define SCU_IDMANUF_DEPT_SHIFT (0) /* Bits 0-4: Department Identification Number */ -#define SCU_IDMANUF_DEPT_MASK (31 << SCU_IDMANUF_MOD_DEPT_SHIFT) -#define SCU_IDMANUF_MANUF_SHIFT (5) /* Bits 5-15: Manufacturer Identification Number */ -#define SCU_IDMANUF_MANUF_MASK (0x7ff << SCU_IDMANUF_MOD_MANUF_SHIFT) +#define SCU_IDMANUF_DEPT_SHIFT (0) /* Bits 0-4: Department Identification Number */ +#define SCU_IDMANUF_DEPT_MASK (31 << SCU_IDMANUF_MOD_DEPT_SHIFT) +#define SCU_IDMANUF_MANUF_SHIFT (5) /* Bits 5-15: Manufacturer Identification Number */ +#define SCU_IDMANUF_MANUF_MASK (0x7ff << SCU_IDMANUF_MOD_MANUF_SHIFT) /* Start-up Control */ -#define SCU_STCON_HWCON_SHIFT (0) /* Bits 0-1: HW Configuration */ -#define SCU_STCON_HWCON_MASK (3 << SCU_STCON_HWCON_SHIFT) -# define SCU_STCON_HWCON_JTAG (0 << SCU_STCON_HWCON_SHIFT) /* Normal mode, JTAG */ -# define SCU_STCON_HWCON_ACBSL (1 << SCU_STCON_HWCON_SHIFT) /* ASC BSL enabled */ -# define SCU_STCON_HWCON_BMI (2 << SCU_STCON_HWCON_SHIFT) /* BMI customized boot enabled */ -# define SCU_STCON_HWCON_CANBSL (3 << SCU_STCON_HWCON_SHIFT) /* CAN BSL enabled */ -#define SCU_STCON_SWCON_SHIFT (8) /* Bits 8-11: SW Configuration */ -#define SCU_STCON_SWCON_MASK (15 << SCU_STCON_SWCON_SHIFT) -# define SCU_STCON_SWCON_ ROM (0 << SCU_STCON_SWCON_SHIFT) /* Normal boot from Boot ROM */ -# define SCU_STCON_SWCON_ASCBSL (1 << SCU_STCON_SWCON_SHIFT) /* ASC BSL enabled */ -# define SCU_STCON_SWCON_BMI (2 << SCU_STCON_SWCON_SHIFT) /* BMI customized boot enabled */ -# define SCU_STCON_SWCON_CANBSL (3 << SCU_STCON_SWCON_SHIFT) /* CAN BSL enabled */ -# define SCU_STCON_SWCON_SRAM (4 << SCU_STCON_SWCON_SHIFT) /* Boot from Code SRAM */ -# define SCU_STCON_SWCON_FLASH0 (8 << SCU_STCON_SWCON_SHIFT) /* Boot from alternate Flash Address 0 */ -# define SCU_STCON_SWCON_FLASH1 (12 << SCU_STCON_SWCON_SHIFT) /* Boot from alternate Flash Address 1 */ -# define SCU_STCON_SWCON_ABM (15 << SCU_STCON_SWCON_SHIFT) /* Enable fallback Alternate Boot Mode (ABM) */ +#define SCU_STCON_HWCON_SHIFT (0) /* Bits 0-1: HW Configuration */ +#define SCU_STCON_HWCON_MASK (3 << SCU_STCON_HWCON_SHIFT) +# define SCU_STCON_HWCON_JTAG (0 << SCU_STCON_HWCON_SHIFT) /* Normal mode, JTAG */ +# define SCU_STCON_HWCON_ACBSL (1 << SCU_STCON_HWCON_SHIFT) /* ASC BSL enabled */ +# define SCU_STCON_HWCON_BMI (2 << SCU_STCON_HWCON_SHIFT) /* BMI customized boot enabled */ +# define SCU_STCON_HWCON_CANBSL (3 << SCU_STCON_HWCON_SHIFT) /* CAN BSL enabled */ +#define SCU_STCON_SWCON_SHIFT (8) /* Bits 8-11: SW Configuration */ +#define SCU_STCON_SWCON_MASK (15 << SCU_STCON_SWCON_SHIFT) +# define SCU_STCON_SWCON_ ROM (0 << SCU_STCON_SWCON_SHIFT) /* Normal boot from Boot ROM */ +# define SCU_STCON_SWCON_ASCBSL (1 << SCU_STCON_SWCON_SHIFT) /* ASC BSL enabled */ +# define SCU_STCON_SWCON_BMI (2 << SCU_STCON_SWCON_SHIFT) /* BMI customized boot enabled */ +# define SCU_STCON_SWCON_CANBSL (3 << SCU_STCON_SWCON_SHIFT) /* CAN BSL enabled */ +# define SCU_STCON_SWCON_SRAM (4 << SCU_STCON_SWCON_SHIFT) /* Boot from Code SRAM */ +# define SCU_STCON_SWCON_FLASH0 (8 << SCU_STCON_SWCON_SHIFT) /* Boot from alternate Flash Address 0 */ +# define SCU_STCON_SWCON_FLASH1 (12 << SCU_STCON_SWCON_SHIFT) /* Boot from alternate Flash Address 1 */ +# define SCU_STCON_SWCON_ABM (15 << SCU_STCON_SWCON_SHIFT) /* Enable fallback Alternate Boot Mode (ABM) */ /* General Purpose Register 0 and General Purpose Register 1 (32-bit data) */ /* Ethernet 0 Port Control */ -#define SCU_ETH0CON_RXD0_SHIFT (0) /* Bits 0-1: MAC Receive Input 0 */ -#define SCU_ETH0CON_RXD0_MASK (3 << SCU_ETH0CON_RXD0_SHIFT) -# define SCU_ETH0CON_RXD0A (0 << SCU_ETH0CON_RXD0_SHIFT) /* Data input RXD0A is selected */ -# define SCU_ETH0CON_RXD0B (1 << SCU_ETH0CON_RXD0_SHIFT) /* Data input RXD0B is selected */ -# define SCU_ETH0CON_RXD0C (2 << SCU_ETH0CON_RXD0_SHIFT) /* Data input RXD0C is selected */ -# define SCU_ETH0CON_RXD0D (3 << SCU_ETH0CON_RXD0_SHIFT) /* Data input RXD0D is selected */ -#define SCU_ETH0CON_RXD1_SHIFT (2) /* Bits 2-3: MAC Receive Input 1 */ -#define SCU_ETH0CON_RXD1_MASK (3 << SCU_ETH0CON_RXD1_SHIFT) -# define SCU_ETH0CON_RXD1A (0 << SCU_ETH0CON_RXD1_SHIFT) /* Data input RXD1A is selected */ -# define SCU_ETH0CON_RXD1B (1 << SCU_ETH0CON_RXD1_SHIFT) /* Data input RXD1B is selected */ -# define SCU_ETH0CON_RXD1C (2 << SCU_ETH0CON_RXD1_SHIFT) /* Data input RXD1C is selected */ -# define SCU_ETH0CON_RXD1D (3 << SCU_ETH0CON_RXD1_SHIFT) /* Data input RXD1D is selected */ -#define SCU_ETH0CON_RXD2_SHIFT (4) /* Bits 4-5: MAC Receive Input 2 */ -#define SCU_ETH0CON_RXD2_MASK (3 << SCU_ETH0CON_RXD2_SHIFT) -# define SCU_ETH0CON_RXD2A (0 << SCU_ETH0CON_RXD2_SHIFT) /* Data input RXD2A is selected */ -# define SCU_ETH0CON_RXD2B (1 << SCU_ETH0CON_RXD2_SHIFT) /* Data input RXD2B is selected */ -# define SCU_ETH0CON_RXD2C (2 << SCU_ETH0CON_RXD2_SHIFT) /* Data input RXD2C is selected */ -# define SCU_ETH0CON_RXD2D (3 << SCU_ETH0CON_RXD2_SHIFT) /* Data input RXD2D is selected */ -#define SCU_ETH0CON_RXD3_SHIFT (6) /* Bits 6-7: MAC Receive Input 3 */ -#define SCU_ETH0CON_RXD3_MASK (3 << SCU_ETH0CON_RXD3_SHIFT) -# define SCU_ETH0CON_RXD3A (0 << SCU_ETH0CON_RXD3_SHIFT) /* Data input RXD3A is selected */ -# define SCU_ETH0CON_RXD3B (1 << SCU_ETH0CON_RXD3_SHIFT) /* Data input RXD3B is selected */ -# define SCU_ETH0CON_RXD3C (2 << SCU_ETH0CON_RXD3_SHIFT) /* Data input RXD3C is selected */ -# define SCU_ETH0CON_RXD3D (3 << SCU_ETH0CON_RXD3_SHIFT) /* Data input RXD3D is selected */ -#define SCU_ETH0CON_CLKRMII_SHIFT (8) /* Bits 8-9: RMII clock input */ -#define SCU_ETH0CON_CLKRMII_MASK (3 << SCU_ETH0CON_CLKRMII_SHIFT) -# define SCU_ETH0CON_CLKRMIIA (0 << SCU_ETH0CON_CLKRMII_SHIFT) /* Data input RMIIA is selected */ -# define SCU_ETH0CON_CLKRMIIB (1 << SCU_ETH0CON_CLKRMII_SHIFT) /* Data input RMIIB is selected */ -# define SCU_ETH0CON_CLKRMIIC (2 << SCU_ETH0CON_CLKRMII_SHIFT) /* Data input RMIIC is selected */ -# define SCU_ETH0CON_CLKRMIID (3 << SCU_ETH0CON_CLKRMII_SHIFT) /* Data input RMIID is selected */ -#define SCU_ETH0CON_CRSDV_SHIFT (10) /* Bits 10-11: CRS_DV input */ -#define SCU_ETH0CON_CRSDV_MASK (3 << SCU_ETH0CON_CRSDV_SHIFT) -# define SCU_ETH0CON_CRSDVA (0 << SCU_ETH0CON_CRSDV_SHIFT) /* Data input CRS_DVA is selected */ -# define SCU_ETH0CON_CRSDVB (1 << SCU_ETH0CON_CRSDV_SHIFT) /* Data input CRS_DVB is selected */ -# define SCU_ETH0CON_CRSDVC (2 << SCU_ETH0CON_CRSDV_SHIFT) /* Data input CRS_DVC is selected */ -# define SCU_ETH0CON_CRSDVD (3 << SCU_ETH0CON_CRSDV_SHIFT) /* Data input CRS_DVD is selected */ -#define SCU_ETH0CON_CRS_SHIFT (12) /* Bits 12-13: CRS input */ -#define SCU_ETH0CON_CRS_MASK (3 << SCU_ETH0CON_CRS_SHIFT) -# define SCU_ETH0CON_CRSA (0 << SCU_ETH0CON_CRS_SHIFT) /* Data input CRSA is selected */ -# define SCU_ETH0CON_CRSB (1 << SCU_ETH0CON_CRS_SHIFT) /* Data input CRSB is selected */ -# define SCU_ETH0CON_CRSC (2 << SCU_ETH0CON_CRS_SHIFT) /* Data input CRSC is selected */ -# define SCU_ETH0CON_CRSD (3 << SCU_ETH0CON_CRS_SHIFT) /* Data input CRSD is selected */ -#define SCU_ETH0CON_RXER_SHIFT (14) /* Bits 14-15: RXER Input */ -#define SCU_ETH0CON_RXER_MASK (3 << SCU_ETH0CON_RXER_SHIFT) -# define SCU_ETH0CON_RXERA (0 << SCU_ETH0CON_RXER_SHIFT) /* Data input RXERA is selected */ -# define SCU_ETH0CON_RXERB (1 << SCU_ETH0CON_RXER_SHIFT) /* Data input RXERB is selected */ -# define SCU_ETH0CON_RXERC (2 << SCU_ETH0CON_RXER_SHIFT) /* Data input RXERC is selected */ -# define SCU_ETH0CON_RXERD (3 << SCU_ETH0CON_RXER_SHIFT) /* Data input RXERD is selected */ -#define SCU_ETH0CON_COL_SHIFT (16) /* Bits 16-17: COL input */ -#define SCU_ETH0CON_COL_MASK (3 << SCU_ETH0CON_COL_SHIFT) -# define SCU_ETH0CON_COLA (0 << SCU_ETH0CON_COL_SHIFT) /* Data input COLA is selected */ -# define SCU_ETH0CON_COLB (1 << SCU_ETH0CON_COL_SHIFT) /* Data input COLB is selected */ -# define SCU_ETH0CON_COLC (2 << SCU_ETH0CON_COL_SHIFT) /* Data input COLC is selected */ -# define SCU_ETH0CON_COLD (3 << SCU_ETH0CON_COL_SHIFT) /* Data input COLD is selected */ -#define SCU_ETH0CON_CLKTX_SHIFT (18) /* Bits 18-19: CLK_TX input */ -#define SCU_ETH0CON_CLKTX_MASK (3 << SCU_ETH0CON_CLKTX_SHIFT) -# define SCU_ETH0CON_CLKTXA (0 << SCU_ETH0CON_CLKTX_SHIFT) /* Data input CLK_TXA is selected */ -# define SCU_ETH0CON_CLKTXB (1 << SCU_ETH0CON_CLKTX_SHIFT) /* Data input CLK_TXB is selected */ -# define SCU_ETH0CON_CLKTXC (2 << SCU_ETH0CON_CLKTX_SHIFT) /* Data input CLK_TXC is selected */ -# define SCU_ETH0CON_CLKTXD (3 << SCU_ETH0CON_CLKTX_SHIFT) /* Data input CLK_TXD is selected */ -#define SCU_ETH0CON_MDIO_SHIFT (22) /* Bits 22-23: MDIO Input Select */ -#define SCU_ETH0CON_MDIO_MASK (3 << SCU_ETH0CON_MDIO_SHIFT) -# define SCU_ETH0CON_MDIOA (0 << SCU_ETH0CON_MDIO_SHIFT) /* Data input MDIOA is selected */ -# define SCU_ETH0CON_MDIOB (1 << SCU_ETH0CON_MDIO_SHIFT) /* Data input MDIOB is selected */ -# define SCU_ETH0CON_MDIOC (2 << SCU_ETH0CON_MDIO_SHIFT) /* Data input MDIOC is selected */ -# define SCU_ETH0CON_MDIOD (3 << SCU_ETH0CON_MDIO_SHIFT) /* Data input MDIOD is selected */ -#define SCU_ETH0CON_INFSEL (1 << 26) /* Bit 26: Ethernet MAC Interface Selection */ -# define SCU_ETH0CON_INFSEL_MII (0) /* 0=MII */ -# define SCU_ETH0CON_INFSEL_RMII (1 << 26) /* 1=RMII */ +#define SCU_ETH0CON_RXD0_SHIFT (0) /* Bits 0-1: MAC Receive Input 0 */ +#define SCU_ETH0CON_RXD0_MASK (3 << SCU_ETH0CON_RXD0_SHIFT) +# define SCU_ETH0CON_RXD0A (0 << SCU_ETH0CON_RXD0_SHIFT) /* Data input RXD0A is selected */ +# define SCU_ETH0CON_RXD0B (1 << SCU_ETH0CON_RXD0_SHIFT) /* Data input RXD0B is selected */ +# define SCU_ETH0CON_RXD0C (2 << SCU_ETH0CON_RXD0_SHIFT) /* Data input RXD0C is selected */ +# define SCU_ETH0CON_RXD0D (3 << SCU_ETH0CON_RXD0_SHIFT) /* Data input RXD0D is selected */ +#define SCU_ETH0CON_RXD1_SHIFT (2) /* Bits 2-3: MAC Receive Input 1 */ +#define SCU_ETH0CON_RXD1_MASK (3 << SCU_ETH0CON_RXD1_SHIFT) +# define SCU_ETH0CON_RXD1A (0 << SCU_ETH0CON_RXD1_SHIFT) /* Data input RXD1A is selected */ +# define SCU_ETH0CON_RXD1B (1 << SCU_ETH0CON_RXD1_SHIFT) /* Data input RXD1B is selected */ +# define SCU_ETH0CON_RXD1C (2 << SCU_ETH0CON_RXD1_SHIFT) /* Data input RXD1C is selected */ +# define SCU_ETH0CON_RXD1D (3 << SCU_ETH0CON_RXD1_SHIFT) /* Data input RXD1D is selected */ +#define SCU_ETH0CON_RXD2_SHIFT (4) /* Bits 4-5: MAC Receive Input 2 */ +#define SCU_ETH0CON_RXD2_MASK (3 << SCU_ETH0CON_RXD2_SHIFT) +# define SCU_ETH0CON_RXD2A (0 << SCU_ETH0CON_RXD2_SHIFT) /* Data input RXD2A is selected */ +# define SCU_ETH0CON_RXD2B (1 << SCU_ETH0CON_RXD2_SHIFT) /* Data input RXD2B is selected */ +# define SCU_ETH0CON_RXD2C (2 << SCU_ETH0CON_RXD2_SHIFT) /* Data input RXD2C is selected */ +# define SCU_ETH0CON_RXD2D (3 << SCU_ETH0CON_RXD2_SHIFT) /* Data input RXD2D is selected */ +#define SCU_ETH0CON_RXD3_SHIFT (6) /* Bits 6-7: MAC Receive Input 3 */ +#define SCU_ETH0CON_RXD3_MASK (3 << SCU_ETH0CON_RXD3_SHIFT) +# define SCU_ETH0CON_RXD3A (0 << SCU_ETH0CON_RXD3_SHIFT) /* Data input RXD3A is selected */ +# define SCU_ETH0CON_RXD3B (1 << SCU_ETH0CON_RXD3_SHIFT) /* Data input RXD3B is selected */ +# define SCU_ETH0CON_RXD3C (2 << SCU_ETH0CON_RXD3_SHIFT) /* Data input RXD3C is selected */ +# define SCU_ETH0CON_RXD3D (3 << SCU_ETH0CON_RXD3_SHIFT) /* Data input RXD3D is selected */ +#define SCU_ETH0CON_CLKRMII_SHIFT (8) /* Bits 8-9: RMII clock input */ +#define SCU_ETH0CON_CLKRMII_MASK (3 << SCU_ETH0CON_CLKRMII_SHIFT) +# define SCU_ETH0CON_CLKRMIIA (0 << SCU_ETH0CON_CLKRMII_SHIFT) /* Data input RMIIA is selected */ +# define SCU_ETH0CON_CLKRMIIB (1 << SCU_ETH0CON_CLKRMII_SHIFT) /* Data input RMIIB is selected */ +# define SCU_ETH0CON_CLKRMIIC (2 << SCU_ETH0CON_CLKRMII_SHIFT) /* Data input RMIIC is selected */ +# define SCU_ETH0CON_CLKRMIID (3 << SCU_ETH0CON_CLKRMII_SHIFT) /* Data input RMIID is selected */ +#define SCU_ETH0CON_CRSDV_SHIFT (10) /* Bits 10-11: CRS_DV input */ +#define SCU_ETH0CON_CRSDV_MASK (3 << SCU_ETH0CON_CRSDV_SHIFT) +# define SCU_ETH0CON_CRSDVA (0 << SCU_ETH0CON_CRSDV_SHIFT) /* Data input CRS_DVA is selected */ +# define SCU_ETH0CON_CRSDVB (1 << SCU_ETH0CON_CRSDV_SHIFT) /* Data input CRS_DVB is selected */ +# define SCU_ETH0CON_CRSDVC (2 << SCU_ETH0CON_CRSDV_SHIFT) /* Data input CRS_DVC is selected */ +# define SCU_ETH0CON_CRSDVD (3 << SCU_ETH0CON_CRSDV_SHIFT) /* Data input CRS_DVD is selected */ +#define SCU_ETH0CON_CRS_SHIFT (12) /* Bits 12-13: CRS input */ +#define SCU_ETH0CON_CRS_MASK (3 << SCU_ETH0CON_CRS_SHIFT) +# define SCU_ETH0CON_CRSA (0 << SCU_ETH0CON_CRS_SHIFT) /* Data input CRSA is selected */ +# define SCU_ETH0CON_CRSB (1 << SCU_ETH0CON_CRS_SHIFT) /* Data input CRSB is selected */ +# define SCU_ETH0CON_CRSC (2 << SCU_ETH0CON_CRS_SHIFT) /* Data input CRSC is selected */ +# define SCU_ETH0CON_CRSD (3 << SCU_ETH0CON_CRS_SHIFT) /* Data input CRSD is selected */ +#define SCU_ETH0CON_RXER_SHIFT (14) /* Bits 14-15: RXER Input */ +#define SCU_ETH0CON_RXER_MASK (3 << SCU_ETH0CON_RXER_SHIFT) +# define SCU_ETH0CON_RXERA (0 << SCU_ETH0CON_RXER_SHIFT) /* Data input RXERA is selected */ +# define SCU_ETH0CON_RXERB (1 << SCU_ETH0CON_RXER_SHIFT) /* Data input RXERB is selected */ +# define SCU_ETH0CON_RXERC (2 << SCU_ETH0CON_RXER_SHIFT) /* Data input RXERC is selected */ +# define SCU_ETH0CON_RXERD (3 << SCU_ETH0CON_RXER_SHIFT) /* Data input RXERD is selected */ +#define SCU_ETH0CON_COL_SHIFT (16) /* Bits 16-17: COL input */ +#define SCU_ETH0CON_COL_MASK (3 << SCU_ETH0CON_COL_SHIFT) +# define SCU_ETH0CON_COLA (0 << SCU_ETH0CON_COL_SHIFT) /* Data input COLA is selected */ +# define SCU_ETH0CON_COLB (1 << SCU_ETH0CON_COL_SHIFT) /* Data input COLB is selected */ +# define SCU_ETH0CON_COLC (2 << SCU_ETH0CON_COL_SHIFT) /* Data input COLC is selected */ +# define SCU_ETH0CON_COLD (3 << SCU_ETH0CON_COL_SHIFT) /* Data input COLD is selected */ +#define SCU_ETH0CON_CLKTX_SHIFT (18) /* Bits 18-19: CLK_TX input */ +#define SCU_ETH0CON_CLKTX_MASK (3 << SCU_ETH0CON_CLKTX_SHIFT) +# define SCU_ETH0CON_CLKTXA (0 << SCU_ETH0CON_CLKTX_SHIFT) /* Data input CLK_TXA is selected */ +# define SCU_ETH0CON_CLKTXB (1 << SCU_ETH0CON_CLKTX_SHIFT) /* Data input CLK_TXB is selected */ +# define SCU_ETH0CON_CLKTXC (2 << SCU_ETH0CON_CLKTX_SHIFT) /* Data input CLK_TXC is selected */ +# define SCU_ETH0CON_CLKTXD (3 << SCU_ETH0CON_CLKTX_SHIFT) /* Data input CLK_TXD is selected */ +#define SCU_ETH0CON_MDIO_SHIFT (22) /* Bits 22-23: MDIO Input Select */ +#define SCU_ETH0CON_MDIO_MASK (3 << SCU_ETH0CON_MDIO_SHIFT) +# define SCU_ETH0CON_MDIOA (0 << SCU_ETH0CON_MDIO_SHIFT) /* Data input MDIOA is selected */ +# define SCU_ETH0CON_MDIOB (1 << SCU_ETH0CON_MDIO_SHIFT) /* Data input MDIOB is selected */ +# define SCU_ETH0CON_MDIOC (2 << SCU_ETH0CON_MDIO_SHIFT) /* Data input MDIOC is selected */ +# define SCU_ETH0CON_MDIOD (3 << SCU_ETH0CON_MDIO_SHIFT) /* Data input MDIOD is selected */ +#define SCU_ETH0CON_INFSEL (1 << 26) /* Bit 26: Ethernet MAC Interface Selection */ +# define SCU_ETH0CON_INFSEL_MII (0) /* 0=MII */ +# define SCU_ETH0CON_INFSEL_RMII (1 << 26) /* 1=RMII */ /* CCUx Global Start Control Register */ -#define SCU_CCUCON_GSC40 (1 << 0) /* Bit 0: Global Start Control CCU40 */ -#define SCU_CCUCON_GSC41 (1 << 1) /* Bit 1: Global Start Control CCU41 */ -#define SCU_CCUCON_GSC42 (1 << 2) /* Bit 2: Global Start Control CCU42 */ -#define SCU_CCUCON_GSC43 (1 << 3) /* Bit 3: Global Start Control CCU43 */ -#define SCU_CCUCON_GSC80 (1 << 8) /* Bit 8: Global Start Control CCU80 */ -#define SCU_CCUCON_GSC81 (1 << 9) /* Bit 9: Global Start Control CCU81 */ +#define SCU_CCUCON_GSC40 (1 << 0) /* Bit 0: Global Start Control CCU40 */ +#define SCU_CCUCON_GSC41 (1 << 1) /* Bit 1: Global Start Control CCU41 */ +#define SCU_CCUCON_GSC42 (1 << 2) /* Bit 2: Global Start Control CCU42 */ +#define SCU_CCUCON_GSC43 (1 << 3) /* Bit 3: Global Start Control CCU43 */ +#define SCU_CCUCON_GSC80 (1 << 8) /* Bit 8: Global Start Control CCU80 */ +#define SCU_CCUCON_GSC81 (1 << 9) /* Bit 9: Global Start Control CCU81 */ /* DTS Control */ -#define SCU_DTSCON_PWD (1 << 0) /* Bit 0: Sensor Power Down */ -#define SCU_DTSCON_START (1 << 1) /* Bit 1: Sensor Measurement Start */ -#define SCU_DTSCON_OFFSET_SHIFT (4) /* Bits 4-10: Offset Calibration Value */ -#define SCU_DTSCON_OFFSET_MASK (0x7f << SCU_DTSCON_OFFSET_SHIFT) -# define SCU_DTSCON_OFFSET(n) ((uint32_t)(n) << SCU_DTSCON_OFFSET_SHIFT) -#define SCU_DTSCON_GAIN_SHIFT (11) /* Bits 11-16: Gain Calibration Value */ -#define SCU_DTSCON_GAIN_MASK (0x3f << SCU_DTSCON_GAIN_SHIFT) -# define SCU_DTSCON_GAIN(n) ((uint32_t)(n) << SCU_DTSCON_GAIN_SHIFT) -#define SCU_DTSCON_REFTRIM_SHIFT (17) /* Bits 17-19: Reference Trim Calibration Value */ -#define SCU_DTSCON_REFTRIM_MASK (7 << SCU_DTSCON_REFTRIM_SHIFT) -# define SCU_DTSCON_REFTRIM(n) ((uint32_t)(n) << SCU_DTSCON_REFTRIM_SHIFT) -#define SCU_DTSCON_BGTRIM_SHIFT (20) /* Bits 20-23: Bandgap Trim Calibration Value */ -#define SCU_DTSCON_BGTRIM_MASK (15 << SCU_DTSCON_BGTRIM_SHIFT) -# define SCU_DTSCON_BGTRIM(n) ((uint32_t)(n) << SCU_DTSCON_BGTRIM_SHIFT) +#define SCU_DTSCON_PWD (1 << 0) /* Bit 0: Sensor Power Down */ +#define SCU_DTSCON_START (1 << 1) /* Bit 1: Sensor Measurement Start */ +#define SCU_DTSCON_OFFSET_SHIFT (4) /* Bits 4-10: Offset Calibration Value */ +#define SCU_DTSCON_OFFSET_MASK (0x7f << SCU_DTSCON_OFFSET_SHIFT) +# define SCU_DTSCON_OFFSET(n) ((uint32_t)(n) << SCU_DTSCON_OFFSET_SHIFT) +#define SCU_DTSCON_GAIN_SHIFT (11) /* Bits 11-16: Gain Calibration Value */ +#define SCU_DTSCON_GAIN_MASK (0x3f << SCU_DTSCON_GAIN_SHIFT) +# define SCU_DTSCON_GAIN(n) ((uint32_t)(n) << SCU_DTSCON_GAIN_SHIFT) +#define SCU_DTSCON_REFTRIM_SHIFT (17) /* Bits 17-19: Reference Trim Calibration Value */ +#define SCU_DTSCON_REFTRIM_MASK (7 << SCU_DTSCON_REFTRIM_SHIFT) +# define SCU_DTSCON_REFTRIM(n) ((uint32_t)(n) << SCU_DTSCON_REFTRIM_SHIFT) +#define SCU_DTSCON_BGTRIM_SHIFT (20) /* Bits 20-23: Bandgap Trim Calibration Value */ +#define SCU_DTSCON_BGTRIM_MASK (15 << SCU_DTSCON_BGTRIM_SHIFT) +# define SCU_DTSCON_BGTRIM(n) ((uint32_t)(n) << SCU_DTSCON_BGTRIM_SHIFT) /* DTS Status */ -#define SCU_DTSSTAT_RESULT_SHIFT (0) /* Bits 0-9: Result of the DTS Measurement */ -#define SCU_DTSSTAT_RESULT_MASK (0x3ff << SCU_DTSSTAT_RESULT_SHIFT) -#define SCU_DTSSTAT_RDY (1 << 14) /* Bit 14: Sensor Ready Status */ -#define SCU_DTSSTAT_BUSY (1 << 15) /* Bit 15: Sensor Busy Status */ +#define SCU_DTSSTAT_RESULT_SHIFT (0) /* Bits 0-9: Result of the DTS Measurement */ +#define SCU_DTSSTAT_RESULT_MASK (0x3ff << SCU_DTSSTAT_RESULT_SHIFT) +#define SCU_DTSSTAT_RDY (1 << 14) /* Bit 14: Sensor Ready Status */ +#define SCU_DTSSTAT_BUSY (1 << 15) /* Bit 15: Sensor Busy Status */ /* SD-MMC Delay Control Register */ -#define SCU_SDMMCDEL_TAPEN (1 << 0) /* Bit 0: Enable delay on the CMD/DAT out lines */ -#define SCU_SDMMCDEL_TAPDEL_SHIFT (4) /* Bitx 4-7: Number of Delay Elements Select */ -#define SCU_SDMMCDEL_TAPDEL_MASK (15 << SCU_SDMMCDEL_TAPDEL_SHIFT) -# define SCU_SDMMCDEL_TAPDEL(n) ((uint32_t)((n)-1) << SCU_SDMMCDEL_TAPDEL_SHIFT) +#define SCU_SDMMCDEL_TAPEN (1 << 0) /* Bit 0: Enable delay on the CMD/DAT out lines */ +#define SCU_SDMMCDEL_TAPDEL_SHIFT (4) /* Bitx 4-7: Number of Delay Elements Select */ +#define SCU_SDMMCDEL_TAPDEL_MASK (15 << SCU_SDMMCDEL_TAPDEL_SHIFT) +# define SCU_SDMMCDEL_TAPDEL(n) ((uint32_t)((n)-1) << SCU_SDMMCDEL_TAPDEL_SHIFT) /* Out-Of-Range Comparator Enable Register 0 and Out-Of-Range Comparator Enable Register 1 */ -#define SCU_GORCEN_ENORC6 (1 << 6) /* Bit 6: Enable Out of Range Comparator, Channel 6 */ -#define SCU_GORCEN_ENORC7 (1 << 7) /* Bit 7: Enable Out of Range Comparator, Channel 7 */ +#define SCU_GORCEN_ENORC6 (1 << 6) /* Bit 6: Enable Out of Range Comparator, Channel 6 */ +#define SCU_GORCEN_ENORC7 (1 << 7) /* Bit 7: Enable Out of Range Comparator, Channel 7 */ + +/* SDMMC Configuration */ + +#define SCU_SDMMCCON_WPSEL (1 << 0) /* Bit 0: SDMMC Write Protection Input Multiplexer Control */ +#define SCU_SDMMCCON_WPSVAL (1 << 4) /* Bit 4: SDMMC Write Protect Software Control */ +#define SCU_SDMMCCON_CDSEL (1 << 16) /* Bit 16: SDMMC Card Detection Control */ +#define SCU_SDMMCCON_CDSVAL (1 << 20) /* Bit 20: SDMMC Write Protect Software Control */ /* Mirror Update Status Register */ @@ -517,44 +505,39 @@ #define SCU_MIRRSTS_RTC_MSKSR (1 << 14) /* Bit 14: RTC MSKSSR Mirror Register Write Status */ #define SCU_MIRRSTS_RTC_CLRSR (1 << 15) /* Bit 15: RTC CLRSR Mirror Register Write Status */ -/* Ethernet Control SCU Resters */ - -/* Ethernet 0 Port Control Register */ -#define SCU_ETHCON_ - /* Interrupt Control SCU Registers */ /* Service Request Status, RAW Service Request Status, Service Request Mask, Service * Request Clear, Service Request Set */ -#define SCU_INT_PRWARN (1 << 0) /* Bit 0: WDT pre-warning Interrupt */ -#define SCU_INT_PI (1 << 1) /* Bit 1: RTC Periodic Interrupt */ -#define SCU_INT_AI (1 << 2) /* Bit 2: Alarm Interrupt */ -#define SCU_INT_DLROVR (1 << 3) /* Bit 3: DLR Request Overrun Interrupt */ -#define SCU_INT_HDSTAT (1 << 16) /* Bit 16: HDSTAT Mirror Register Update */ -#define SCU_INT_HDCLR (1 << 17) /* Bit 17: HDCLR Mirror Register Update */ -#define SCU_INT_HDSET (1 << 18) /* Bit 18: HDSET Mirror Register Update */ -#define SCU_INT_HDCR (1 << 19) /* Bit 19: HDCR Mirror Register Update */ -#define SCU_INT_OSCSICTRL (1 << 21) /* Bit 21: OSCSICTRL Mirror Register Update */ -#define SCU_INT_OSCULSTAT (1 << 22) /* Bit 22: OSCULTAT Mirror Register Update */ -#define SCU_INT_OSCULCTRL (1 << 23) /* Bit 23: OSCULCTRL Mirror Register Update */ -#define SCU_INT_RTC_CTR (1 << 24) /* Bit 24: RTC CTR Mirror Register Update */ -#define SCU_INT_RTC_ATIM0 (1 << 25) /* Bit 25: RTC ATIM0 Mirror Register Update */ -#define SCU_INT_RTC_ATIM1 (1 << 26) /* Bit 26: RTC ATIM1 Mirror Register Update */ -#define SCU_INT_RTC_TIM0 (1 << 27) /* Bit 27: RTC TIM0 Mirror Register Update */ -#define SCU_INT_RTC_TIM1 (1 << 28) /* Bit 28: RTC TIM1 Mirror Register Update */ -#define SCU_INTT_RMX (1 << 29) /* Bit 29: Retention Memory Mirror Register */ +#define SCU_INT_PRWARN (1 << 0) /* Bit 0: WDT pre-warning Interrupt */ +#define SCU_INT_PI (1 << 1) /* Bit 1: RTC Periodic Interrupt */ +#define SCU_INT_AI (1 << 2) /* Bit 2: Alarm Interrupt */ +#define SCU_INT_DLROVR (1 << 3) /* Bit 3: DLR Request Overrun Interrupt */ +#define SCU_INT_HDSTAT (1 << 16) /* Bit 16: HDSTAT Mirror Register Update */ +#define SCU_INT_HDCLR (1 << 17) /* Bit 17: HDCLR Mirror Register Update */ +#define SCU_INT_HDSET (1 << 18) /* Bit 18: HDSET Mirror Register Update */ +#define SCU_INT_HDCR (1 << 19) /* Bit 19: HDCR Mirror Register Update */ +#define SCU_INT_OSCSICTRL (1 << 21) /* Bit 21: OSCSICTRL Mirror Register Update */ +#define SCU_INT_OSCULSTAT (1 << 22) /* Bit 22: OSCULTAT Mirror Register Update */ +#define SCU_INT_OSCULCTRL (1 << 23) /* Bit 23: OSCULCTRL Mirror Register Update */ +#define SCU_INT_RTC_CTR (1 << 24) /* Bit 24: RTC CTR Mirror Register Update */ +#define SCU_INT_RTC_ATIM0 (1 << 25) /* Bit 25: RTC ATIM0 Mirror Register Update */ +#define SCU_INT_RTC_ATIM1 (1 << 26) /* Bit 26: RTC ATIM1 Mirror Register Update */ +#define SCU_INT_RTC_TIM0 (1 << 27) /* Bit 27: RTC TIM0 Mirror Register Update */ +#define SCU_INT_RTC_TIM1 (1 << 28) /* Bit 28: RTC TIM1 Mirror Register Update */ +#define SCU_INTT_RMX (1 << 29) /* Bit 29: Retention Memory Mirror Register */ /* Enable Promoting Events to NMI Request */ -#define SCU_NMIREQEN_PRWARN (1 << 0) /* Bit 0: Promote Pre-Warning Interrupt Request to NMI Request */ -#define SCU_NMIREQEN_PI (1 << 1) /* Bit 1: Promote RTC Periodic Interrupt request to NMI Request */ -#define SCU_NMIREQEN_AI (1 << 2) /* Bit 2: Promote RTC Alarm Interrupt Request to NMIRequest */ -#define SCU_NMIREQEN_ERU00 (1 << 16) /* Bit 16: Promote Channel 0 Interrupt of ERU0 Request to NMI Request */ -#define SCU_NMIREQEN_ERU01 (1 << 17) /* Bit 17: Promote Channel 1 Interrupt of ERU0 Request to NMI Request */ -#define SCU_NMIREQEN_ERU02 (1 << 18) /* Bit 18: Promote Channel 2 Interrupt of ERU0 Request to NMI Request */ -#define SCU_NMIREQEN_ERU03 (1 << 19) /* Bit 19: Promote Channel 3 Interrupt of ERU0 Request to NMI Request */ +#define SCU_NMIREQEN_PRWARN (1 << 0) /* Bit 0: Promote Pre-Warning Interrupt Request to NMI Request */ +#define SCU_NMIREQEN_PI (1 << 1) /* Bit 1: Promote RTC Periodic Interrupt request to NMI Request */ +#define SCU_NMIREQEN_AI (1 << 2) /* Bit 2: Promote RTC Alarm Interrupt Request to NMIRequest */ +#define SCU_NMIREQEN_ERU00 (1 << 16) /* Bit 16: Promote Channel 0 Interrupt of ERU0 Request to NMI Request */ +#define SCU_NMIREQEN_ERU01 (1 << 17) /* Bit 17: Promote Channel 1 Interrupt of ERU0 Request to NMI Request */ +#define SCU_NMIREQEN_ERU02 (1 << 18) /* Bit 18: Promote Channel 2 Interrupt of ERU0 Request to NMI Request */ +#define SCU_NMIREQEN_ERU03 (1 << 19) /* Bit 19: Promote Channel 3 Interrupt of ERU0 Request to NMI Request */ /* Retention Memory Access Control Register */ @@ -565,11 +548,6 @@ /* Retention Memory Access Data Register (32-bit data) */ -/* SDMMC Control SCU Registers */ - -/* SDMMC Configuration */ -#define SCU_SDMMCCON_ - /* Parity Control Registers */ /* Parity Error Enable Register */ @@ -715,11 +693,11 @@ /* Hibernation SCU Registers */ /* Hibernate Domain Status Register */ -#define SCU_HDSTAT_EPEV (1 << 0) /* Bit 0: Wake-up Pin Event Positive Edge Status */ -#define SCU_HDSTAT_ENEV (1 << 1) /* Bit 1: Wake-up Pin Event Negative Edge Status */ -#define SCU_HDSTAT_RTCEV (1 << 2) /* Bit 2: RTC Event Status */ -#define SCU_HDSTAT_ULPWDG (1 << 3) /* Bit 3: ULP WDG Alarm Status */ -#define SCU_HDSTAT_HIBNOUT (1 << 4) /* Bit 3: Hibernate Control Status */ +#define SCU_HDSTAT_EPEV (1 << 0) /* Bit 0: Wake-up Pin Event Positive Edge Status */ +#define SCU_HDSTAT_ENEV (1 << 1) /* Bit 1: Wake-up Pin Event Negative Edge Status */ +#define SCU_HDSTAT_RTCEV (1 << 2) /* Bit 2: RTC Event Status */ +#define SCU_HDSTAT_ULPWDG (1 << 3) /* Bit 3: ULP WDG Alarm Status */ +#define SCU_HDSTAT_HIBNOUT (1 << 4) /* Bit 3: Hibernate Control Status */ /* Hibernate Domain Status Clear Register */ @@ -981,41 +959,42 @@ /* Peripheral 0 Clock Gating Status, Peripheral 0 Clock Gating Set, Peripheral 0 Clock Gating Clear */ -#define SCU_CGAT0_VADC (1 << 0) /* Bit 0: */ -#define SCU_CGAT0_DSD (1 << 1) /* Bit 1: */ -#define SCU_CGAT0_CCU40 (1 << 2) /* Bit 2: */ -#define SCU_CGAT0_CCU41 (1 << 3) /* Bit 3: */ -#define SCU_CGAT0_CCU42 (1 << 4) /* Bit 4: */ -#define SCU_CGAT0_CCU80 (1 << 7) /* Bit 7: */ -#define SCU_CGAT0_CCU81 (1 << 8) /* Bit 8: */ -#define SCU_CGAT0_POSIF0 (1 << 9) /* Bit 9: */ -#define SCU_CGAT0_POSIF1 (1 << 10) /* Bit 10: */ -#define SCU_CGAT0_USIC0 (1 << 11) /* Bit 11: */ -#define SCU_CGAT0_ERU1_ (1 << 16) /* Bit 16: */ +#define SCU_CGAT0_VADC (1 << 0) /* Bit 0: VADC Gating Status */ +#define SCU_CGAT0_DSD (1 << 1) /* Bit 1: DSD Gating Status */ +#define SCU_CGAT0_CCU40 (1 << 2) /* Bit 2: CCU40 Gating Status */ +#define SCU_CGAT0_CCU41 (1 << 3) /* Bit 3: CCU41 Gating Status */ +#define SCU_CGAT0_CCU42 (1 << 4) /* Bit 4: CCU42 Gating Status */ +#define SCU_CGAT0_CCU80 (1 << 7) /* Bit 7: CCU80 Gating Status */ +#define SCU_CGAT0_CCU81 (1 << 8) /* Bit 8: CCU81 Gating Status */ +#define SCU_CGAT0_POSIF0 (1 << 9) /* Bit 9: POSIF0 Gating Status */ +#define SCU_CGAT0_POSIF1 (1 << 10) /* Bit 10: POSIF1 Gating Status */ +#define SCU_CGAT0_USIC0 (1 << 11) /* Bit 11: USIC0 Gating Status */ +#define SCU_CGAT0_ERU1_ (1 << 16) /* Bit 16: ERU1 Gating Status */ /* Peripheral 1 Clock Gating Status, Peripheral 1 Clock Gating Set, Peripheral 1 Clock Gating Clear */ -#define SCU_CGATSTAT1_CCU43 (1 << 0) /* Bit 0: */ -#define SCU_CGATSTAT1_LEDTSCU0 (1 << 3) /* Bit 3: */ -#define SCU_CGATSTAT1_MCAN0 (1 << 4) /* Bit 4: */ -#define SCU_CGATSTAT1_DAC (1 << 5) /* Bit 5: */ -#define SCU_CGATSTAT1_MMCI (1 << 6) /* Bit 6: */ -#define SCU_CGATSTAT1_USIC1 (1 << 7) /* Bit 7: */ -#define SCU_CGATSTAT1_USIC2 (1 << 8) /* Bit 8: */ -#define SCU_CGATSTAT1_PPORTS (1 << 9) /* Bit 9: */ +#define SCU_CGATSTAT1_CCU43 (1 << 0) /* Bit 0: CCU43 Gating Status */ +#define SCU_CGATSTAT1_LEDTSCU0 (1 << 3) /* Bit 3: LEDTS Gating Status */ +#define SCU_CGATSTAT1_MCAN0 (1 << 4) /* Bit 4: MultiCAN Gating Status */ +#define SCU_CGATSTAT1_DAC (1 << 5) /* Bit 5: DAC Gating Status */ +#define SCU_CGATSTAT1_MMCI (1 << 6) /* Bit 6: MMC Interface Gating Status */ +#define SCU_CGATSTAT1_USIC1 (1 << 7) /* Bit 7: USIC1 Gating Status */ +#define SCU_CGATSTAT1_USIC2 (1 << 8) /* Bit 8: USIC1 Gating Status */ +#define SCU_CGATSTAT1_PPORTS (1 << 9) /* Bit 9: PORTS Gating Status */ /* Peripheral 2 Clock Gating Status, Peripheral 2 Clock Gating Set, Peripheral 2 Clock Gating Clear */ -#define SCU_CGATSTAT2_WDT (1 << 1) /* Bit 1: */ -#define SCU_CGATSTAT2_ETH0 (1 << 2) /* Bit 2: */ -#define SCU_CGATSTAT2_DMA0 (1 << 4) /* Bit 4: */ -#define SCU_CGATSTAT2_DMA1 (1 << 5) /* Bit 5: */ -#define SCU_CGATSTAT2_FCE (1 << 6) /* Bit 6: */ -#define SCU_CGATSTAT2_USB (1 << 7) /* Bit 7: */ +#define SCU_CGATSTAT2_WDT (1 << 1) /* Bit 1: WDT Gating Status */ +#define SCU_CGATSTAT2_ETH0 (1 << 2) /* Bit 2: ETH0 Gating Status */ +#define SCU_CGATSTAT2_DMA0 (1 << 4) /* Bit 4: DMA0 Gating Status */ +#define SCU_CGATSTAT2_DMA1 (1 << 5) /* Bit 5: DMA1 Gating Status */ +#define SCU_CGATSTAT2_FCE (1 << 6) /* Bit 6: FCE Gating Status */ +#define SCU_CGATSTAT2_USB (1 << 7) /* Bit 7: USB Gating Status */ +#define SCU_CGATSTAT2_USB (1 << 10) /* Bit 10: ECAT Gating Status */ /* Peripheral 3 Clock Gating Status, Peripheral 3 Clock Gating Set, Peripheral 3 Clock Gating Clear */ -#define SCU_CGATSTAT3_EBU (1 << 2) /* Bit 2: */ +#define SCU_CGATSTAT3_EBU (1 << 2) /* Bit 2: EBU Gating Status */ /* Oscillator Control SCU Registers */ From 6b5dc4957374b7fa9404b668f4172d23ae5f6974 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 18 Mar 2017 19:16:29 -0600 Subject: [PATCH 40/81] XMC4xxx: Flesh out USIC header file. Still needs a little work. --- arch/arm/src/xmc4/chip/xmc4_usic.h | 535 ++++++++++++++++++++++++++--- 1 file changed, 492 insertions(+), 43 deletions(-) diff --git a/arch/arm/src/xmc4/chip/xmc4_usic.h b/arch/arm/src/xmc4/chip/xmc4_usic.h index 8b91e88583a..8d204fcf8c8 100644 --- a/arch/arm/src/xmc4/chip/xmc4_usic.h +++ b/arch/arm/src/xmc4/chip/xmc4_usic.h @@ -69,7 +69,7 @@ /* PMU Registers -- See ID register */ /* Prefetch Registers -- See PCON register */ -/* Kernal Registers */ +/* Kernel Registers */ #define XMC4_USIC_ID_OFFSET 0x0008 /* Kernel State Configuration Register */ @@ -399,79 +399,528 @@ /* USIC Channel Registers */ /* Channel Configuration Register */ -#define USIC_CCFG_ + +#define USIC_CCFG_SSC (1 << 0) /* Bit 0: */ +#define USIC_CCFG_ASC (1 << 1) /* Bit 1: */ +#define USIC_CCFG_IIC (1 << 2) /* Bit 2: */ +#define USIC_CCFG_IIS (1 << 3) /* Bit 3: */ +#define USIC_CCFG_RB (1 << 6) /* Bit 6: */ +#define USIC_CCFG_TB (1 << 7) /* Bit 7: */ + /* Kernel State Configuration Register */ -#define USIC_KSCFG_ + +#define USIC_KSCFG_MODEN (1 << 0) /* Bit 0: */ +#define USIC_KSCFG_BPMODEN (1 << 1) /* Bit 1: */ +#define USIC_KSCFG_NOMCFG_SHIFT (4) /* Bits 4-5: */ +#define USIC_KSCFG_NOMCFG_MASK (3 << USIC_KSCFG_NOMCFG_SHIFT) +#define USIC_KSCFG_BPNOM (1 << 7) /* Bit 7: */ +#define USIC_KSCFG_SUMCFG_SHIFT (8) /* Bits 8-9: */ +#define USIC_KSCFG_SUMCFG_MASK (3 << USIC_KSCFG_SUMCFG_SHIFT) +#define USIC_KSCFG_BPSUM (1 << 11) /* Bit 11: */ + /* Fractional Divider Register */ -#define USIC_FDR_ + +#define USIC_FDR_STEP_SHIFT (0) /* Bits 0-9: */ +#define USIC_FDR_STEP_MASK (0x3ff << USIC_FDR_STEP_SHIFT) +#define USIC_FDR_DM_SHIFT (14) /* Bits 14-15: */ +#define USIC_FDR_DM_MASK (3 << USIC_FDR_DM_SHIFT) +#define USIC_FDR_RESULT_SHIFT (16) /* Bits 16-25: */ +#define USIC_FDR_RESULT_MASK (0x3ff << USIC_FDR_RESULT_SHIFT) + /* Baud Rate Generator Register */ -#define USIC_BRG_ + +#define USIC_BRG_CLKSEL_SHIFT (0) /* Bits 0-1: */ +#define USIC_BRG_CLKSEL_MASK (3 << USIC_BRG_CLKSEL_SHIFT) +#define USIC_BRG_TMEN (1 << 3) /* Bit 3: */ +#define USIC_BRG_PPPEN (1 << 4) /* Bit 4: */ +#define USIC_BRG_CTQSEL_SHIFT (6) /* Bits 6-7: */ +#define USIC_BRG_CTQSEL_MASK (3 << USIC_BRG_CTQSEL_SHIFT) +#define USIC_BRG_PCTQ_SHIFT (8) /* Bits 8-9: */ +#define USIC_BRG_PCTQ_MASK (3 << USIC_BRG_PCTQ_SHIFT) +#define USIC_BRG_DCTQ_SHIFT (10) /* Bits 10-15: */ +#define USIC_BRG_DCTQ_MASK (0x3f << USIC_BRG_DCTQ_SHIFT) +#define USIC_BRG_PDIV_SHIFT (16) /* Bits 16-25: */ +#define USIC_BRG_PDIV_MASK (0x3ff << USIC_BRG_PDIV_SHIFT) +#define USIC_BRG_SCLKOSEL (1 << 28) /* Bit 28: */ +#define USIC_BRG_MCLKCFG (1 << 29) /* Bit 29: */ +#define USIC_BRG_SCLKCFG (1 << 30) /* Bit 30: */ + /* Interrupt Node Pointer Register */ -#define USIC_INPR_ -/* Input Control Register 0 */ -#define USIC_DX0CR_ -/* Input Control Register 1 */ -#define USIC_DX1CR_ -/* Input Control Register 2 */ -#define USIC_DX2CR_ -/* Input Control Register 3 */ -#define USIC_DX3CR_ -/* Input Control Register 4 */ -#define USIC_DX4CR_ -/* Input Control Register 5 */ -#define USIC_DX5CR_ + +#define USIC_INPR_TSINP_SHIFT (0) /* Bits 0-2: */ +#define USIC_INPR_TSINP_MASK (7 << USIC_INPR_TSINP_SHIFT) +#define USIC_INPR_TBINP_SHIFT (4) /* Bits 4-6: */ +#define USIC_INPR_TBINP_MASK (7 << USIC_INPR_TBINP_SHIFT) +#define USIC_INPR_RINP_SHIFT (8) /* Bits 8-10: */ +#define USIC_INPR_RINP_MASK (7 << USIC_INPR_RINP_SHIFT) +#define USIC_INPR_AINP_SHIFT (12) /* Bits 12-14: */ +#define USIC_INPR_AINP_MASK (7 << USIC_INPR_AINP_SHIFT) +#define USIC_INPR_PINP_SHIFT (16) /* Bits 16-18: */ +#define USIC_INPR_PINP_MASK (7 << USIC_INPR_PINP_SHIFT) + +/* Input Control Register 0, Input Control Register 1, Input Control Register 2, + * Input Control Register 3, Input Control Register 4, Input Control Register 5 + */ + +#define USIC_DXCR_DSEL_SHIFT (0) /* Bits 0-2: */ +#define USIC_DXCR_DSEL_MASK (7 << USIC_DX0CR_DSEL_SHIFT) +#define USIC_DX1CR_DCEN (1 << 3) /* Bit 3: (DX1CR only) */ +#define USIC_DXCR_INSW (1 << 4) /* Bit 4: */ +#define USIC_DXCR_DFEN (1 << 5) /* Bit 5: */ +#define USIC_DXCR_DSEN (1 << 6) /* Bit 6: */ +#define USIC_DXCR_DPOL (1 << 8) /* Bit 8: */ +#define USIC_DXCR_SFSEL (1 << 9) /* Bit 9: */ +#define USIC_DXCR_CM_SHIFT (10) /* Bits 10-12: */ +#define USIC_DXCR_CM_MASK (3 << USIC_DX0CR_CM_SHIFT) +#define USIC_DXCR_DXS (1 << 15) /* Bit 15: */ + /* Shift Control Register */ -#define USIC_SCTR_ + +#define USIC_SCTR_SDIR (1 << 0) /* Bit 0: */ +#define USIC_SCTR_PDL (1 << 1) /* Bit `: */ +#define USIC_SCTR_DSM_SHIFT (2) /* Bits 2-3: */ +#define USIC_SCTR_DSM_MASK (3 << USIC_SCTR_DSM_SHIFT) +#define USIC_SCTR_HPCDIR (1 << 4) /* Bit 4: */ +#define USIC_SCTR_DOCFG_SHIFT (6) /* Bits 6-7: */ +#define USIC_SCTR_DOCFG_MASK (3 << USIC_SCTR_DOCFG_SHIFT) +#define USIC_SCTR_TRM_SHIFT (8) /* Bits 8-9: */ +#define USIC_SCTR_TRM_MASK (3 << USIC_SCTR_TRM_SHIFT) +#define USIC_SCTR_FLE_SHIFT (16) /* Bits 16-21: */ +#define USIC_SCTR_FLE_MASK (0x3f << USIC_SCTR_FLE_SHIFT) +#define USIC_SCTR_WLE_SHIFT (24) /* Bits 24-27: */ +#define USIC_SCTR_WLE_MASK (15 << USIC_SCTR_WLE_SHIFT) + /* Transmit Control/Status Register */ -#define USIC_TCSR_ + +#define USIC_TCSR_WLEMD (1 << 0) /* Bit 0: */ +#define USIC_TCSR_SELMD (1 << 1) /* Bit 1: */ +#define USIC_TCSR_FLEMD (1 << 2) /* Bit 2: */ +#define USIC_TCSR_WAMD (1 << 3) /* Bit 3: */ +#define USIC_TCSR_HPCMD (1 << 4) /* Bit 4: */ +#define USIC_TCSR_SOF (1 << 5) /* Bit 5: */ +#define USIC_TCSR_EOF (1 << 6) /* Bit 6: */ +#define USIC_TCSR_TDV (1 << 7) /* Bit 7: */ +#define USIC_TCSR_TDSSM (1 << 8) /* Bit 8: */ +#define USIC_TCSR_TDEN_SHIFT (10) /* Bits 10-11: */ +#define USIC_TCSR_TDEN_MASK (3 << USIC_TCSR_TDEN_SHIFT) +#define USIC_TCSR_TDVTR (1 << 12) /* Bit 12: */ +#define USIC_TCSR_WA (1 << 13) /* Bit 13: */ +#define USIC_TCSR_TSOF (1 << 24) /* Bit 24: */ +#define USIC_TCSR_TV (1 << 26) /* Bit 26: */ +#define USIC_TCSR_TVC (1 << 27) /* Bit 27: */ +#define USIC_TCSR_TE (1 << 28) /* Bit 28: */ + /* Protocol Control Register */ -#define USIC_PCR_ + +#define USIC_PCR_CTR0 (1 << 0) /* Bit 0: */ +#define USIC_PCR_CTR1 (1 << 1) /* Bit 1: */ +#define USIC_PCR_CTR2 (1 << 2) /* Bit 2: */ +#define USIC_PCR_CTR3 (1 << 3) /* Bit 3: */ +#define USIC_PCR_CTR4 (1 << 4) /* Bit 4: */ +#define USIC_PCR_CTR5 (1 << 5) /* Bit 5: */ +#define USIC_PCR_CTR6 (1 << 6) /* Bit 6: */ +#define USIC_PCR_CTR7 (1 << 7) /* Bit 7: */ +#define USIC_PCR_CTR8 (1 << 8) /* Bit 8: */ +#define USIC_PCR_CTR9 (1 << 9) /* Bit 9: */ +#define USIC_PCR_CTR10 (1 << 10) /* Bit 10: */ +#define USIC_PCR_CTR11 (1 << 11) /* Bit 11: */ +#define USIC_PCR_CTR12 (1 << 12) /* Bit 12: */ +#define USIC_PCR_CTR13 (1 << 13) /* Bit 13: */ +#define USIC_PCR_CTR14 (1 << 14) /* Bit 14: */ +#define USIC_PCR_CTR15 (1 << 15) /* Bit 15: */ +#define USIC_PCR_CTR16 (1 << 16) /* Bit 16: */ +#define USIC_PCR_CTR17 (1 << 17) /* Bit 17: */ +#define USIC_PCR_CTR18 (1 << 18) /* Bit 18: */ +#define USIC_PCR_CTR19 (1 << 19) /* Bit 19: */ +#define USIC_PCR_CTR20 (1 << 20) /* Bit 20: */ +#define USIC_PCR_CTR21 (1 << 21) /* Bit 21: */ +#define USIC_PCR_CTR22 (1 << 22) /* Bit 22: */ +#define USIC_PCR_CTR23 (1 << 23) /* Bit 23: */ +#define USIC_PCR_CTR24 (1 << 24) /* Bit 24: */ +#define USIC_PCR_CTR25 (1 << 25) /* Bit 25: */ +#define USIC_PCR_CTR26 (1 << 26) /* Bit 26: */ +#define USIC_PCR_CTR27 (1 << 27) /* Bit 27: */ +#define USIC_PCR_CTR28 (1 << 28) /* Bit 28: */ +#define USIC_PCR_CTR29 (1 << 29) /* Bit 29: */ +#define USIC_PCR_CTR30 (1 << 30) /* Bit 30: */ +#define USIC_PCR_CTR31 (1 << 31) /* Bit 31: */ + +#define USIC_PCR_ASCMODE_SMD (1 << 0) /* Bit 0: */ +#define USIC_PCR_ASCMODE_STPB (1 << 1) /* Bit 1: */ +#define USIC_PCR_ASCMODE_IDM (1 << 2) /* Bit 2: */ +#define USIC_PCR_ASCMODE_SBIEN (1 << 3) /* Bit 3: */ +#define USIC_PCR_ASCMODE_CDEN (1 << 4) /* Bit 4: */ +#define USIC_PCR_ASCMODE_RNIEN (1 << 5) /* Bit 5: */ +#define USIC_PCR_ASCMODE_FEIEN (1 << 6) /* Bit 6: */ +#define USIC_PCR_ASCMODE_FFIEN (1 << 7) /* Bit 7: */ +#define USIC_PCR_ASCMODE_SP_SHIFT (8) /* Bits 8-12: */ +#define USIC_PCR_ASCMODE_SP_MASK (31 << USIC_PCR_ASCMODE_SP_SHIFT) +#define USIC_PCR_ASCMODE_PL_SHIFT (13) /* Bits 13-15: */ +#define USIC_PCR_ASCMODE_PL_MASK (7 << USIC_PCR_ASCMODE_PL_SHIFT) +#define USIC_PCR_ASCMODE_RSTEN (1 << 16) /* Bit 16: */ +#define USIC_PCR_ASCMODE_TSTEN (1 << 17) /* Bit 16: */ +#define USIC_PCR_ASCMODE_MCLK (1 << 31) /* Bit 31: */ + +#define USIC_PCR_SSCMODE_MSLSEN (1 << 0) /* Bit 0: */ +#define USIC_PCR_SSCMODE_SELCTR (1 << 1) /* Bit 1: */ +#define USIC_PCR_SSCMODE_SELINV (1 << 2) /* Bit 2: */ +#define USIC_PCR_SSCMODE_FEM (1 << 3) /* Bit 3: */ +#define USIC_PCR_SSCMODE_CTQSEL1_SHIFT (4) /* Bits 4-5: */ +#define USIC_PCR_SSCMODE_CTQSEL1_MASK (3 << USIC_PCR_SSCMODE_CTQSEL1_SHIFT) +#define USIC_PCR_SSCMODE_PCTQ1_SHIFT (6) /* Bits 6-7: */ +#define USIC_PCR_SSCMODE_PCTQ1_MASK (3 << USIC_PCR_SSCMODE_PCTQ1_SHIFT) +#define USIC_PCR_SSCMODE_DCTQ1_SHIFT (8) /* Bits 8-12: */ +#define USIC_PCR_SSCMODE_DCTQ1_MASK (0x1f << USIC_PCR_SSCMODE_DCTQ1_SHIFT) +#define USIC_PCR_SSCMODE_PARIEN (1 << 13) /* Bit 13: */ +#define USIC_PCR_SSCMODE_MSLSIEN (1 << 14) /* Bit 14: */ +#define USIC_PCR_SSCMODE_DX2TIEN (1 << 15) /* Bit 15: */ +#define USIC_PCR_SSCMODE_SELO_SHIFT (16) /* Bits 16-23: */ +#define USIC_PCR_SSCMODE_SELO_MASK (0xff << USIC_PCR_SSCMODE_SELO_SHIFT) +#define USIC_PCR_SSCMODE_TIWEN (1 << 24) /* Bit 24: */ +#define USIC_PCR_SSCMODE_SLPHSEL (1 << 25) /* Bit 25: */ +#define USIC_PCR_SSCMODE_MCLK (1 << 31) /* Bit 31: */ + +#define USIC_PCR_IICMODE_SLAD_SHIFT (0) /* Bits 0-15: */ +#define USIC_PCR_IICMODE_SLAD_MASK (0xffff << USIC_PCR_IICMODE_SLAD_SHIFT) +#define USIC_PCR_IICMODE_ACK00 (1 << 16) /* Bit 16: */ +#define USIC_PCR_IICMODE_STIM (1 << 17) /* Bit 17: */ +#define USIC_PCR_IICMODE_SCRIEN (1 << 18) /* Bit 18: */ +#define USIC_PCR_IICMODE_RSCRIEN (1 << 19) /* Bit 19: */ +#define USIC_PCR_IICMODE_PCRIEN (1 << 20) /* Bit 20: */ +#define USIC_PCR_IICMODE_NACKIEN (1 << 21) /* Bit 21: */ +#define USIC_PCR_IICMODE_ARLIEN (1 << 22) /* Bit 22: */ +#define USIC_PCR_IICMODE_SRRIEN (1 << 23) /* Bit 23: */ +#define USIC_PCR_IICMODE_ERRIEN (1 << 24) /* Bit 24: */ +#define USIC_PCR_IICMODE_SACKDIS (1 << 25) /* Bit 25: */ +#define USIC_PCR_IICMODE_HDEL_SHIFT (26) /* Bits 26-29: */ +#define USIC_PCR_IICMODE_HDEL_MASK (15 << USIC_PCR_IICMODE_HDEL_SHIFT) +#define USIC_PCR_IICMODE_ACKIEN (1 << 30) /* Bit 30: */ +#define USIC_PCR_IICMODE_MCLK (1 << 31) /* Bit 31: */ + +#define USIC_PCR_IISMODE_WAGEN (1 << 0) /* Bit 0: */ +#define USIC_PCR_IISMODE_DTEN (1 << 1) /* Bit 1: */ +#define USIC_PCR_IISMODE_SELINV (1 << 2) /* Bit 2: */ +#define USIC_PCR_IISMODE_WAFEIEN (1 << 4) /* Bit 4: */ +#define USIC_PCR_IISMODE_WAREIEN (1 << 5) /* Bit 5: */ +#define USIC_PCR_IISMODE_ENDIEN (1 << 6) /* Bit 6: */ +#define USIC_PCR_IISMODE_TDEL_SHIFT (16) /* Bits 15-21: */ +#define USIC_PCR_IISMODE_TDEL_MASK (0x3f << USIC_PCR_IISMODE_TDEL_SHIFT) +#define USIC_PCR_IISMODE_MCLK (1 << 31) /* Bit 31: */ + /* Channel Control Register */ -#define USIC_CCR_ + +#define USIC_CCR_MODE_SHIFT (0) /* Bits 0-3: */ +#define USIC_CCR_MODE_MASK (15 << USIC_CCR_MODE_SHIFT) +#define USIC_CCR_HPCEN_SHIFT (6) /* Bits 6-7: */ +#define USIC_CCR_HPCEN_MASK (3 << USIC_CCR_HPCEN_SHIFT) +#define USIC_CCR_PM_SHIFT (8) /* Bits 8-9: */ +#define USIC_CCR_PM_MASK (3 << USIC_CCR_PM_SHIFT) +#define USIC_CCR_RSIEN (1 << 10) /* Bit 10: */ +#define USIC_CCR_DLIEN (1 << 11) /* Bit 11: */ +#define USIC_CCR_TSIEN (1 << 12) /* Bit 12: */ +#define USIC_CCR_TBIEN (1 << 13) /* Bit 13: */ +#define USIC_CCR_RIEN (1 << 14) /* Bit 14: */ +#define USIC_CCR_AIEN (1 << 15) /* Bit 15: */ +#define USIC_CCR_BRGIEN (1 << 16) /* Bit 16: */ + /* Capture Mode Timer Register */ -#define USIC_CMTR_ + +#define USIC_CMTR_CTV_SHIFT (0) /* Bits 0-9: */ +#define USIC_CMTR_CTV_MASK (0x3ff << USIC_CMTR_CTV_SHIFT) + /* Protocol Status Register */ -#define USIC_PSR_ + +#define USIC_PSR_ST0 (1 << 0) /* Bit 0: */ +#define USIC_PSR_ST1 (1 << 1) /* Bit 1: */ +#define USIC_PSR_ST2 (1 << 2) /* Bit 2: */ +#define USIC_PSR_ST3 (1 << 3) /* Bit 3: */ +#define USIC_PSR_ST4 (1 << 4) /* Bit 4: */ +#define USIC_PSR_ST5 (1 << 5) /* Bit 5: */ +#define USIC_PSR_ST6 (1 << 6) /* Bit 6: */ +#define USIC_PSR_ST7 (1 << 7) /* Bit 7: */ +#define USIC_PSR_ST8 (1 << 8) /* Bit 8: */ +#define USIC_PSR_ST9 (1 << 9) /* Bit 9: */ +#define USIC_PSR_RSIF (1 << 10) /* Bit 10: */ +#define USIC_PSR_DLIF (1 << 11) /* Bit 11: */ +#define USIC_PSR_TSIF (1 << 12) /* Bit 12: */ +#define USIC_PSR_TBIF (1 << 13) /* Bit 13: */ +#define USIC_PSR_RIF (1 << 14) /* Bit 14: */ +#define USIC_PSR_AIF (1 << 15) /* Bit 15: */ +#define USIC_PSR_BRGIF (1 << 16) /* Bit 16: */ + +#define USIC_PSR_ASCMODE_TXIDLE (1 << 0) /* Bit 0: */ +#define USIC_PSR_ASCMODE_RXIDLE (1 << 1) /* Bit 1: */ +#define USIC_PSR_ASCMODE_SBD (1 << 2) /* Bit 2: */ +#define USIC_PSR_ASCMODE_COL (1 << 3) /* Bit 3: */ +#define USIC_PSR_ASCMODE_RNS (1 << 4) /* Bit 4: */ +#define USIC_PSR_ASCMODE_FER0 (1 << 5) /* Bit 5: */ +#define USIC_PSR_ASCMODE_FER1 (1 << 6) /* Bit 6: */ +#define USIC_PSR_ASCMODE_RFF (1 << 7) /* Bit 7: */ +#define USIC_PSR_ASCMODE_TFF (1 << 8) /* Bit 8: */ +#define USIC_PSR_ASCMODE_BUSY (1 << 9) /* Bit 9: */ +#define USIC_PSR_ASCMODE_RSIF (1 << 10) /* Bit 10: */ +#define USIC_PSR_ASCMODE_DLIF (1 << 11) /* Bit 11: */ +#define USIC_PSR_ASCMODE_TSIF (1 << 12) /* Bit 12: */ +#define USIC_PSR_ASCMODE_TBIF (1 << 13) /* Bit 13: */ +#define USIC_PSR_ASCMODE_RIF (1 << 14) /* Bit 14: */ +#define USIC_PSR_ASCMODE_AIF (1 << 15) /* Bit 15: */ +#define USIC_PSR_ASCMODE_BRGIF (1 << 16) /* Bit 16: */ + +#define USIC_PSR_SSCMODE_MSLS (1 << 0) /* Bit 0: */ +#define USIC_PSR_SSCMODE_DX2S (1 << 1) /* Bit 1: */ +#define USIC_PSR_SSCMODE_MSLSEV (1 << 2) /* Bit 2: */ +#define USIC_PSR_SSCMODE_DX2TEV (1 << 3) /* Bit 3: */ +#define USIC_PSR_SSCMODE_PARERR (1 << 4) /* Bit 4: */ +#define USIC_PSR_SSCMODE_RSIF (1 << 10) /* Bit 10: */ +#define USIC_PSR_SSCMODE_DLIF (1 << 11) /* Bit 11: */ +#define USIC_PSR_SSCMODE_TSIF (1 << 12) /* Bit 12: */ +#define USIC_PSR_SSCMODE_TBIF (1 << 13) /* Bit 13: */ +#define USIC_PSR_SSCMODE_RIF (1 << 14) /* Bit 14: */ +#define USIC_PSR_SSCMODE_AIF (1 << 15) /* Bit 15: */ +#define USIC_PSR_SSCMODE_BRGIF (1 << 16) /* Bit 16: */ + +#define USIC_PSR_IICMODE_SLSEL (1 << 0) /* Bit 0: */ +#define USIC_PSR_IICMODE_WTDF (1 << 1) /* Bit 1: */ +#define USIC_PSR_IICMODE_SCR (1 << 2) /* Bit 2: */ +#define USIC_PSR_IICMODE_RSCR (1 << 3) /* Bit 3: */ +#define USIC_PSR_IICMODE_PCR (1 << 4) /* Bit 4: */ +#define USIC_PSR_IICMODE_NACK (1 << 5) /* Bit 5: */ +#define USIC_PSR_IICMODE_ARL (1 << 6) /* Bit 6: */ +#define USIC_PSR_IICMODE_SRR (1 << 7) /* Bit 7: */ +#define USIC_PSR_IICMODE_ERR (1 << 8) /* Bit 8: */ +#define USIC_PSR_IICMODE_ACK (1 << 9) /* Bit 9: */ +#define USIC_PSR_IICMODE_RSIF (1 << 10) /* Bit 10: */ +#define USIC_PSR_IICMODE_DLIF (1 << 11) /* Bit 11: */ +#define USIC_PSR_IICMODE_TSIF (1 << 12) /* Bit 12: */ +#define USIC_PSR_IICMODE_TBIF (1 << 13) /* Bit 13: */ +#define USIC_PSR_IICMODE_RIF (1 << 14) /* Bit 14: */ +#define USIC_PSR_IICMODE_AIF (1 << 15) /* Bit 15: */ +#define USIC_PSR_IICMODE_BRGIF (1 << 16) /* Bit 16: */ + +#define USIC_PSR_IISMODE_WA (1 << 0) /* Bit 0: */ +#define USIC_PSR_IISMODE_DX2S (1 << 1) /* Bit 1: */ +#define USIC_PSR_IISMODE_DX2TEV (1 << 3) /* Bit 3: */ +#define USIC_PSR_IISMODE_WAFE (1 << 4) /* Bit 4: */ +#define USIC_PSR_IISMODE_WARE (1 << 5) /* Bit 5: */ +#define USIC_PSR_IISMODE_END (1 << 6) /* Bit 6: */ +#define USIC_PSR_IISMODE_RSIF (1 << 10) /* Bit 10: */ +#define USIC_PSR_IISMODE_DLIF (1 << 11) /* Bit 11: */ +#define USIC_PSR_IISMODE_TSIF (1 << 12) /* Bit 12: */ +#define USIC_PSR_IISMODE_TBIF (1 << 13) /* Bit 13: */ +#define USIC_PSR_IISMODE_RIF (1 << 14) /* Bit 14: */ +#define USIC_PSR_IISMODE_AIF (1 << 15) /* Bit 15: */ +#define USIC_PSR_IISMODE_BRGIF (1 << 16) /* Bit 16: */ + /* Protocol Status Clear Register */ -#define USIC_PSCR_ + +#define USIC_PSCR_CST0 (1 << 0) /* Bit 0: */ +#define USIC_PSCR_CST1 (1 << 1) /* Bit 1: */ +#define USIC_PSCR_CST2 (1 << 2) /* Bit 2: */ +#define USIC_PSCR_CST3 (1 << 3) /* Bit 3: */ +#define USIC_PSCR_CST4 (1 << 4) /* Bit 4: */ +#define USIC_PSCR_CST5 (1 << 5) /* Bit 5: */ +#define USIC_PSCR_CST6 (1 << 6) /* Bit 6: */ +#define USIC_PSCR_CST7 (1 << 7) /* Bit 7: */ +#define USIC_PSCR_CST8 (1 << 8) /* Bit 8: */ +#define USIC_PSCR_CST9 (1 << 9) /* Bit 9: */ +#define USIC_PSCR_CRSIF (1 << 10) /* Bit 10: */ +#define USIC_PSCR_CDLIF (1 << 11) /* Bit 11: */ +#define USIC_PSCR_CTSIF (1 << 12) /* Bit 12: */ +#define USIC_PSCR_CTBIF (1 << 13) /* Bit 13: */ +#define USIC_PSCR_CRIF (1 << 14) /* Bit 14: */ +#define USIC_PSCR_CAIF (1 << 15) /* Bit 15: */ +#define USIC_PSCR_CBRGIF (1 << 16) /* Bit 16: */ + /* Receiver Buffer Status Register */ -#define USIC_RBUFSR_ + +#define USIC_RBUFSR_WLEN_SHIFT (0) /* Bits 0-3: */ +#define USIC_RBUFSR_WLEN_MASK (15 << USIC_RBUFSR_WLEN_SHIFT) +#define USIC_RBUFSR_SOF (1 << 6) /* Bit 6: */ +#define USIC_RBUFSR_PAR (1 << 8) /* Bit 8: */ +#define USIC_RBUFSR_PERR (1 << 9) /* Bit 9: */ +#define USIC_RBUFSR_RDV0 (1 << 13) /* Bit 13: */ +#define USIC_RBUFSR_RDV1 (1 << 14) /* Bit 14: */ +#define USIC_RBUFSR_DS (1 << 15) /* Bit 15: */ + /* Receiver Buffer Register */ -#define USIC_RBUF_ + +#define USIC_RBUF_DSR_SHIFT (0) /* Bits 0-15: */ +#define USIC_RBUF_DSR_MASK (0xffff << USIC_RBUF_DSR_SHIFT) + /* Receiver Buffer Register for Debugger */ -#define USIC_RBUFD_ + +#define USIC_RBUFD_DSR_SHIFT (0) /* Bits 0-15: */ +#define USIC_RBUFD_DSR_MASK (0xffff << USIC_RBUFD_DSR_SHIFT) + /* Receiver Buffer Register 0 */ -#define USIC_RBUF0_ + +#define USIC_RBUF0_DSR0_SHIFT (0) /* Bits 0-15: */ +#define USIC_RBUF0_DSR0_MASK (0xffff << USIC_RBUF0_DSR0_SHIFT) + /* Receiver Buffer Register 1 */ -#define USIC_RBUF1_ + +#define USIC_RBUF1_DSR1_SHIFT (0) /* Bits 0-15: */ +#define USIC_RBUF1_DSR1_MASK (0xffff << USIC_RBUF1_DSR1_SHIFT) + /* Receiver Buffer 01 Status Register */ -#define USIC_RBUF01SR_ + +#define USIC_RBUF01SR_WLEN0_SHIFT (0) /* Bits 0-3: */ +#define USIC_RBUF01SR_WLEN0_MASK (15 << USIC_RBUF01SR_WLEN0_SHIFT) +#define USIC_RBUF01SR_SOF0 (1 << 6) /* Bit 6: */ +#define USIC_RBUF01SR_PAR0 (1 << 8) /* Bit 8: */ +#define USIC_RBUF01SR_PERR0 (1 << 9) /* Bit 9: */ +#define USIC_RBUF01SR_RDV00 (1 << 13) /* Bit 13: */ +#define USIC_RBUF01SR_RDV01 (1 << 14) /* Bit 14: */ +#define USIC_RBUF01SR_DS0 (1 << 15) /* Bit 15: */ +#define USIC_RBUF01SR_WLEN1_SHIFT (16) /* Bits 16-19: */ +#define USIC_RBUF01SR_WLEN1_MASK (15 << USIC_RBUF01SR_WLEN1_SHIFT) +#define USIC_RBUF01SR_SOF1 (1 << 22) /* Bit 22: */ +#define USIC_RBUF01SR_PAR1 (1 << 24) /* Bit 24: */ +#define USIC_RBUF01SR_PERR1 (1 << 25) /* Bit 25: */ +#define USIC_RBUF01SR_RDV10 (1 << 29) /* Bit 29: */ +#define USIC_RBUF01SR_RDV11 (1 << 30) /* Bit 30: */ +#define USIC_RBUF01SR_DS1 (1 << 31) /* Bit 31: */ + /* Flag Modification Register */ -#define USIC_FMR_ + +#define USIC_FMR_MTDV_SHIFT (0) /* Bits 0-1: */ +#define USIC_FMR_MTDV_MASK (3 << USIC_FMR_MTDV_SHIFT) +#define USIC_FMR_ATVC (1 << 4) /* Bit 4: */ +#define USIC_FMR_CRDV0 (1 << 14) /* Bit 14: */ +#define USIC_FMR_CRDV1 (1 << 15) /* Bit 15: */ +#define USIC_FMR_SIO0 (1 << 16) /* Bit 16: */ +#define USIC_FMR_SIO1 (1 << 17) /* Bit 17: */ +#define USIC_FMR_SIO2 (1 << 18) /* Bit 18: */ +#define USIC_FMR_SIO3 (1 << 19) /* Bit 19: */ +#define USIC_FMR_SIO4 (1 << 20) /* Bit 20: */ +#define USIC_FMR_SIO5 (1 << 21) /* Bit 21: */ + /* Transmit Buffer (32 x 4-bytes) */ -#define USIC_TBUF_ + +#define USIC_TBUF_TDATA_SHIFT (0) /* Bits 0-15: */ +#define USIC_TBUF_TDATA_MASK (0xffff << USIC_TBUF_TDATA_SHIFT) /* USIC FIFO Registers */ /* Bypass Data Register */ -#define USIC_BYP_ + +#define USIC_BYP_BDATA_SHIFT (0) /* Bits 0-15: */ +#define USIC_BYP_BDATA_MASK (0xffff << USIC_BYP_BDATA_SHIFT) + /* Bypass Control Register */ -#define USIC_BYPCR_ + +#define USIC_BYPCR_BWLE_SHIFT (0) /* Bits 0-3: */ +#define USIC_BYPCR_BWLE_MASK (15 << USIC_BYPCR_BWLE_SHIFT) +#define USIC_BYPCR_BDSSM (1 << 8) /* Bit 8: */ +#define USIC_BYPCR_BDEN_SHIFT (10) /* Bits 10-11: */ +#define USIC_BYPCR_BDEN_MASK (3 << USIC_BYPCR_BDEN_SHIFT) +#define USIC_BYPCR_BDVTR (1 << 12) /* Bit 12: */ +#define USIC_BYPCR_BPRIO (1 << 13) /* Bit 13: */ +#define USIC_BYPCR_BDV (1 << 15) /* Bit 15: */ +#define USIC_BYPCR_BSELO_SHIFT (16) /* Bits 16-20: */ +#define USIC_BYPCR_BSELO_MASK (31 << USIC_BYPCR_BSELO_SHIFT) +#define USIC_BYPCR_BHPC_SHIFT (21) /* Bits 21-23: */ +#define USIC_BYPCR_BHPC_MASK (7 << USIC_BYPCR_BHPC_SHIFT) + /* Transmitter Buffer Control Register */ -#define USIC_TBCTR_ + +#define USIC_TBCTR_DPTR_SHIFT (0) /* Bits 0-1: */ +#define USIC_TBCTR_DPTR_MASK (3 << USIC_TBCTR_DPTR_SHIFT) +#define USIC_TBCTR_LIMIT_SHIFT (8) /* Bits 8-13: */ +#define USIC_TBCTR_LIMIT_MASK (0x3f << USIC_TBCTR_LIMIT_SHIFT) +#define USIC_TBCTR_STBTM (1 << 14) /* Bit 14: */ +#define USIC_TBCTR_STBTEN (1 << 15) /* Bit 15: */ +#define USIC_TBCTR_STBINP_SHIFT (16) /* Bits 16-18: */ +#define USIC_TBCTR_STBINP_MASK (7 << USIC_TBCTR_STBINP_SHIFT) +#define USIC_TBCTR_ATBINP_SHIFT (19) /* Bits 19-21: */ +#define USIC_TBCTR_ATBINP_MASK (7 << USIC_TBCTR_ATBINP_SHIFT) +#define USIC_TBCTR_SIZE_SHIFT (24) /* Bits 24-26: */ +#define USIC_TBCTR_SIZE_MASK (7 << USIC_TBCTR_SIZE_SHIFT) +#define USIC_TBCTR_LOF (1 << 28) /* Bit 28: */ +#define USIC_TBCTR_STBIEN (1 << 30) /* Bit 30: */ +#define USIC_TBCTR_TBERIEN (1 << 31) /* Bit 31: */ + /* Receiver Buffer Control Register */ -#define USIC_RBCTR_ + +#define USIC_RBCTR_DPTR_SHIFT (0) /* Bits 0-5: */ +#define USIC_RBCTR_DPTR_MASK (0x3f << USIC_RBCTR_DPTR_SHIFT) +#define USIC_RBCTR_LIMIT_SHIFT (8) /* Bits 8-13: */ +#define USIC_RBCTR_LIMIT_MASK (0x3f << USIC_RBCTR_LIMIT_SHIFT) +#define USIC_RBCTR_SRBTM (1 << 14) /* Bit 14: */ +#define USIC_RBCTR_SRBTEN (1 << 15) /* Bit 15: */ +#define USIC_RBCTR_SRBINP_SHIFT (16) /* Bits 16-18: */ +#define USIC_RBCTR_SRBINP_MASK (7 << USIC_RBCTR_SRBINP_SHIFT) +#define USIC_RBCTR_ARBINP_SHIFT (19) /* Bits 19-21: */ +#define USIC_RBCTR_ARBINP_MASK (7 << USIC_RBCTR_ARBINP_SHIFT) +#define USIC_RBCTR_RCIM_SHIFT (22) /* Bits 22-23: */ +#define USIC_RBCTR_RCIM_MASK (3 << USIC_RBCTR_RCIM_SHIFT) +#define USIC_RBCTR_SIZE_SHIFT (24) /* Bits 24-26: */ +#define USIC_RBCTR_SIZE_MASK (7 << USIC_RBCTR_SIZE_SHIFT) +#define USIC_RBCTR_RNM (1 << 27) /* Bit 27: */ +#define USIC_RBCTR_LOF (1 << 28) /* Bit 28: */ +#define USIC_RBCTR_ARBIEN (1 << 29) /* Bit 29: */ +#define USIC_RBCTR_SRBIEN (1 << 30) /* Bit 30: */ +#define USIC_RBCTR_RBERIEN (1 << 31) /* Bit 31: */ + /* Transmit/Receive Buffer Pointer Register */ -#define USIC_TRBPTR_ + +#define USIC_TRBPTR_TDIPTR_SHIFT (0) /* Bits 0-5: */ +#define USIC_TRBPTR_TDIPTR_MASK (0x3f << USIC_TRBPTR_TDIPTR_SHIFT) +#define USIC_TRBPTR_TDOPTR_SHIFT (8) /* Bits 813xx: */ +#define USIC_TRBPTR_TDOPTR_MASK (0x3f << USIC_TRBPTR_TDOPTR_SHIFT) +#define USIC_TRBPTR_RDIPTR_SHIFT (16) /* Bits 16-21: */ +#define USIC_TRBPTR_RDIPTR_MASK (0x3f << USIC_TRBPTR_RDIPTR_SHIFT) +#define USIC_TRBPTR_RDOPTR_SHIFT (24) /* Bits 24-29: */ +#define USIC_TRBPTR_RDOPTR_MASK (0x3f << USIC_TRBPTR_RDOPTR_SHIFT) + /* Transmit/Receive Buffer Status Register */ -#define USIC_TRBSR_ + +#define USIC_TRBSR_SRBI (1 << 0) /* Bit 0: */ +#define USIC_TRBSR_RBERI (1 << 1) /* Bit 1: */ +#define USIC_TRBSR_ARBI (1 << 2) /* Bit 2: */ +#define USIC_TRBSR_REMPTY (1 << 3) /* Bit 3: */ +#define USIC_TRBSR_RFULL (1 << 4) /* Bit 4: */ +#define USIC_TRBSR_RBUS (1 << 5) /* Bit 5: */ +#define USIC_TRBSR_SRBT (1 << 6) /* Bit 6: */ +#define USIC_TRBSR_STBI (1 << 8) /* Bit 8: */ +#define USIC_TRBSR_TBERI (1 << 9) /* Bit 9: */ +#define USIC_TRBSR_TEMPTY (1 << 11) /* Bit 11: */ +#define USIC_TRBSR_TFULL (1 << 12) /* Bit 12: */ +#define USIC_TRBSR_TBUS (1 << 13) /* Bit 13: */ +#define USIC_TRBSR_STBT (1 << 14) /* Bit 14: */ +#define USIC_TRBSR_RBFLVL_SHIFT (16) /* Bits 16-22: */ +#define USIC_TRBSR_RBFLVL_MASK (0x7f << USIC_TRBSR_RBFLVL_SHIFT) +#define USIC_TRBSR_TBFLVL_SHIFT (24) /* Bits 22-28: */ +#define USIC_TRBSR_TBFLVL_MASK (0x7f << USIC_TRBSR_TBFLVL_SHIFT) + /* Transmit/Receive Buffer Status Clear Register */ -#define USIC_TRBSCR_ + +#define USIC_TRBSCR_CSRBI (1 << 0) /* Bit 0: */ +#define USIC_TRBSCR_CRBERI (1 << 1) /* Bit 1: */ +#define USIC_TRBSCR_CARBI (1 << 2) /* Bit 2: */ +#define USIC_TRBSCR_CSTBI (1 << 8) /* Bit 8: */ +#define USIC_TRBSCR_CTBERI (1 << 9) /* Bit 9: */ +#define USIC_TRBSCR_CBDV (1 << 10) /* Bit 10: */ +#define USIC_TRBSCR_FLUSHRB (1 << 14) /* Bit 14: */ +#define USIC_TRBSCR_FLUSHTB (1 << 15) /* Bit 15: */ + /* Receiver Buffer Output Register */ -#define USIC_OUTR_ + +#define USIC_OUTR_DSR_SHIFT (0) /* Bits 0-15: */ +#define USIC_OUTR_DSR_MASK (0xffff << USIC_OUTR_DSR_SHIFT) +#define USIC_OUTR_RCI_SHIFT (16) /* Bits 16-20: */ +#define USIC_OUTR_RCI_MASK (31 << USIC_OUTR_RCI_SHIFT) + /* Receiver Buffer Output Register L for Debugger */ -#define USIC_OUTDR_ + +#define USIC_OUTDR_DSR_SHIFT (0) /* Bits 0-15: */ +#define USIC_OUTDR_DSR_MASK (0xffff << USIC_OUTDR_DSR_SHIFT) +#define USIC_OUTDR_RCI_SHIFT (16) /* Bits 16-30: */ +#define USIC_OUTDR_RCI_MASK (31 << USIC_OUTDR_RCI_SHIFT) + /* Transmit FIFO Buffer (32 x 4-bytes) */ -#define USIC_IN_ + +#define USIC_IN_TDATA_SHIFT (0) /* Bits 0-15: */ +#define USIC_IN_TDATA_MASK (0xffff << USIC_IN_TDATA_SHIFT) #endif /* __ARCH_ARM_SRC_XMC4_CHIP_XMC4_USIC_H */ From 9110b7d45c799ec4acb191eafc03dc8f6da9f722 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 19 Mar 2017 08:44:28 -0600 Subject: [PATCH 41/81] XMC4xxxx: Add more definitions to USIC register definition header. --- arch/arm/src/xmc4/chip/xmc4_usic.h | 521 +++++++++++++++++------------ 1 file changed, 314 insertions(+), 207 deletions(-) diff --git a/arch/arm/src/xmc4/chip/xmc4_usic.h b/arch/arm/src/xmc4/chip/xmc4_usic.h index 8d204fcf8c8..d6d5299cbd3 100644 --- a/arch/arm/src/xmc4/chip/xmc4_usic.h +++ b/arch/arm/src/xmc4/chip/xmc4_usic.h @@ -400,150 +400,231 @@ /* Channel Configuration Register */ -#define USIC_CCFG_SSC (1 << 0) /* Bit 0: */ -#define USIC_CCFG_ASC (1 << 1) /* Bit 1: */ -#define USIC_CCFG_IIC (1 << 2) /* Bit 2: */ -#define USIC_CCFG_IIS (1 << 3) /* Bit 3: */ -#define USIC_CCFG_RB (1 << 6) /* Bit 6: */ -#define USIC_CCFG_TB (1 << 7) /* Bit 7: */ +#define USIC_CCFG_SSC (1 << 0) /* Bit 0: SSC Protocol Available */ +#define USIC_CCFG_ASC (1 << 1) /* Bit 1: ASC Protocol Available */ +#define USIC_CCFG_I2C (1 << 2) /* Bit 2: IIC Protocol Available */ +#define USIC_CCFG_I2S (1 << 3) /* Bit 3: IIS Protocol Available */ +#define USIC_CCFG_RB (1 << 6) /* Bit 6: Receive FIFO Buffer Available */ +#define USIC_CCFG_TB (1 << 7) /* Bit 7: Transmit FIFO Buffer Available */ /* Kernel State Configuration Register */ -#define USIC_KSCFG_MODEN (1 << 0) /* Bit 0: */ -#define USIC_KSCFG_BPMODEN (1 << 1) /* Bit 1: */ -#define USIC_KSCFG_NOMCFG_SHIFT (4) /* Bits 4-5: */ +#define USIC_KSCFG_MODEN (1 << 0) /* Bit 0: Module Enable */ +#define USIC_KSCFG_BPMODEN (1 << 1) /* Bit 1: Bit Protection for MODEN */ +#define USIC_KSCFG_NOMCFG_SHIFT (4) /* Bits 4-5: Normal Operation Mode Configuration */ #define USIC_KSCFG_NOMCFG_MASK (3 << USIC_KSCFG_NOMCFG_SHIFT) -#define USIC_KSCFG_BPNOM (1 << 7) /* Bit 7: */ -#define USIC_KSCFG_SUMCFG_SHIFT (8) /* Bits 8-9: */ +# define USIC_KSCFG_NOMCFG_RUN0 (0 << USIC_KSCFG_NOMCFG_SHIFT) /* Run mode 0 selected */ +# define USIC_KSCFG_NOMCFG_RUN1 (1 << USIC_KSCFG_NOMCFG_SHIFT) /* Run mode 1 selected */ +# define USIC_KSCFG_NOMCFG_STOP0 (2 << USIC_KSCFG_NOMCFG_SHIFT) /* Stop mode 0 selected */ +# define USIC_KSCFG_NOMCFG_STOP1 (3 << USIC_KSCFG_NOMCFG_SHIFT) /* Stop mode 1 selected */ +#define USIC_KSCFG_BPNOM (1 << 7) /* Bit 7: Bit Protection for NOMCFG */ +#define USIC_KSCFG_SUMCFG_SHIFT (8) /* Bits 8-9: Suspend Mode Configuration */ #define USIC_KSCFG_SUMCFG_MASK (3 << USIC_KSCFG_SUMCFG_SHIFT) -#define USIC_KSCFG_BPSUM (1 << 11) /* Bit 11: */ +# define USIC_KSCFG_SUMCFG_RUN0 (0 << USIC_KSCFG_SUMCFG_SHIFT) /* Run mode 0 selected */ +# define USIC_KSCFG_SUMCFG_RUN1 (1 << USIC_KSCFG_SUMCFG_SHIFT) /* Run mode 1 selected */ +# define USIC_KSCFG_SUMCFG_STOP0 (2 << USIC_KSCFG_SUMCFG_SHIFT) /* Stop mode 0 selected */ +# define USIC_KSCFG_SUMCFG_STOP1 (3 << USIC_KSCFG_SUMCFG_SHIFT) /* Stop mode 1 selected */ +#define USIC_KSCFG_BPSUM (1 << 11) /* Bit 11: Bit Protection for SUMCFG */ /* Fractional Divider Register */ -#define USIC_FDR_STEP_SHIFT (0) /* Bits 0-9: */ +#define USIC_FDR_STEP_SHIFT (0) /* Bits 0-9: Step Value */ #define USIC_FDR_STEP_MASK (0x3ff << USIC_FDR_STEP_SHIFT) -#define USIC_FDR_DM_SHIFT (14) /* Bits 14-15: */ +# define USIC_FDR_STEP(n) ((uint32_t)(n) << USIC_FDR_STEP_SHIFT) +#define USIC_FDR_DM_SHIFT (14) /* Bits 14-15: Divider Mode */ #define USIC_FDR_DM_MASK (3 << USIC_FDR_DM_SHIFT) -#define USIC_FDR_RESULT_SHIFT (16) /* Bits 16-25: */ +# define USIC_FDR_DM_ OFF (0 << USIC_FDR_DM_SHIFT) /* Divider switched off */ +# define USIC_FDR_DM_ NORMAL (1 << USIC_FDR_DM_SHIFT) /* Normal divider mode selected */ +# define USIC_FDR_DM_ FRACTIONAL (2 << USIC_FDR_DM_SHIFT) /* Fractional divider mode selected */ +#define USIC_FDR_RESULT_SHIFT (16) /* Bits 16-25: Result Value */ #define USIC_FDR_RESULT_MASK (0x3ff << USIC_FDR_RESULT_SHIFT) /* Baud Rate Generator Register */ -#define USIC_BRG_CLKSEL_SHIFT (0) /* Bits 0-1: */ +#define USIC_BRG_CLKSEL_SHIFT (0) /* Bits 0-1: Clock Selection */ #define USIC_BRG_CLKSEL_MASK (3 << USIC_BRG_CLKSEL_SHIFT) -#define USIC_BRG_TMEN (1 << 3) /* Bit 3: */ -#define USIC_BRG_PPPEN (1 << 4) /* Bit 4: */ -#define USIC_BRG_CTQSEL_SHIFT (6) /* Bits 6-7: */ +# define USIC_BRG_CLKSEL_FRAC (0 << USIC_BRG_CLKSEL_SHIFT) /* Fractional divider frequency fFD */ +# define USIC_BRG_CLKSEL_DX1T (2 << USIC_BRG_CLKSEL_SHIFT) /* Trigger signal DX1T defines fPIN */ +# define USIC_BRG_CLKSEL_DX1S (3 << USIC_BRG_CLKSEL_SHIFT) /* Frequency fPIN is derived from DX1S */ +#define USIC_BRG_TMEN (1 << 3) /* Bit 3: Timing Measurement Enable */ +#define USIC_BRG_PPPEN (1 << 4) /* Bit 4: Enable 2:1 Divider for fPPP */ +#define USIC_BRG_CTQSEL_SHIFT (6) /* Bits 6-7: Input Selection for CTQ */ #define USIC_BRG_CTQSEL_MASK (3 << USIC_BRG_CTQSEL_SHIFT) -#define USIC_BRG_PCTQ_SHIFT (8) /* Bits 8-9: */ +# define USIC_BRG_CTQSEL_FPDIV (0 << USIC_BRG_CTQSEL_SHIFT) /* fCTQIN = fPDIV */ +# define USIC_BRG_CTQSEL_FPPP (1 << USIC_BRG_CTQSEL_SHIFT) /* fCTQIN = fPPP */ +# define USIC_BRG_CTQSEL_FSCLK (2 << USIC_BRG_CTQSEL_SHIFT) /* fCTQIN = fSCLK */ +# define USIC_BRG_CTQSEL_FMCLK (3 << USIC_BRG_CTQSEL_SHIFT) /* fCTQIN = fMCLK */ +#define USIC_BRG_PCTQ_SHIFT (8) /* Bits 8-9: Pre-Divider for Time Quanta Counter */ #define USIC_BRG_PCTQ_MASK (3 << USIC_BRG_PCTQ_SHIFT) -#define USIC_BRG_DCTQ_SHIFT (10) /* Bits 10-15: */ +# define USIC_BRG_PCTQ(n) ((uint32_t)((n)-1) << USIC_BRG_PCTQ_SHIFT) +#define USIC_BRG_DCTQ_SHIFT (10) /* Bits 10-15: Denominator for Time Quanta Counter */ #define USIC_BRG_DCTQ_MASK (0x3f << USIC_BRG_DCTQ_SHIFT) -#define USIC_BRG_PDIV_SHIFT (16) /* Bits 16-25: */ +# define USIC_BRG_DCTQ(n) ((uint32_t)(n) << USIC_BRG_DCTQ_SHIFT) +#define USIC_BRG_PDIV_SHIFT (16) /* Bits 16-25: Divider Mode: Divider Factor to Generate fPDIV */ #define USIC_BRG_PDIV_MASK (0x3ff << USIC_BRG_PDIV_SHIFT) -#define USIC_BRG_SCLKOSEL (1 << 28) /* Bit 28: */ -#define USIC_BRG_MCLKCFG (1 << 29) /* Bit 29: */ -#define USIC_BRG_SCLKCFG (1 << 30) /* Bit 30: */ +# define USIC_BRG_PDIV(n) ((uint32_t)(n) << USIC_BRG_PDIV_SHIFT) +#define USIC_BRG_SCLKOSEL (1 << 28) /* Bit 28: Shift Clock Output Select */ +#define USIC_BRG_MCLKCFG (1 << 29) /* Bit 29: Master Clock Configuration */ +#define USIC_BRG_SCLKCFG (1 << 30) /* Bit 30: Shift Clock Output Configuration */ /* Interrupt Node Pointer Register */ -#define USIC_INPR_TSINP_SHIFT (0) /* Bits 0-2: */ +#define USIC_INPR_TSINP_SHIFT (0) /* Bits 0-2: Transmit Shift Interrupt Node Pointer */ #define USIC_INPR_TSINP_MASK (7 << USIC_INPR_TSINP_SHIFT) -#define USIC_INPR_TBINP_SHIFT (4) /* Bits 4-6: */ +# define USIC_INPR_TSINP_SR0 (0 << USIC_INPR_TSINP_SHIFT) /* Output SR0 activated */ +# define USIC_INPR_TSINP_SR1 (1 << USIC_INPR_TSINP_SHIFT) /* Output SR1 activated */ +# define USIC_INPR_TSINP_SR2 (2 << USIC_INPR_TSINP_SHIFT) /* Output SR2 activated */ +# define USIC_INPR_TSINP_SR3 (3 << USIC_INPR_TSINP_SHIFT) /* Output SR3 activated */ +# define USIC_INPR_TSINP_SR4 (4 << USIC_INPR_TSINP_SHIFT) /* Output SR4 activated */ +# define USIC_INPR_TSINP_SR5 (5 << USIC_INPR_TSINP_SHIFT) /* Output SR5 activated */ +#define USIC_INPR_TBINP_SHIFT (4) /* Bits 4-6: Transmit Buffer Interrupt Node Poi */ #define USIC_INPR_TBINP_MASK (7 << USIC_INPR_TBINP_SHIFT) -#define USIC_INPR_RINP_SHIFT (8) /* Bits 8-10: */ +# define USIC_INPR_TBINP_SR0 (0 << USIC_INPR_TBINP_SHIFT) /* Output SR0 activated */ +# define USIC_INPR_TBINP_SR1 (1 << USIC_INPR_TBINP_SHIFT) /* Output SR1 activated */ +# define USIC_INPR_TBINP_SR2 (2 << USIC_INPR_TBINP_SHIFT) /* Output SR2 activated */ +# define USIC_INPR_TBINP_SR3 (3 << USIC_INPR_TBINP_SHIFT) /* Output SR3 activated */ +# define USIC_INPR_TBINP_SR4 (4 << USIC_INPR_TBINP_SHIFT) /* Output SR4 activated */ +# define USIC_INPR_TBINP_SR5 (5 << USIC_INPR_TBINP_SHIFT) /* Output SR5 activated */ +#define USIC_INPR_RINP_SHIFT (8) /* Bits 8-10: Receive Interrupt Node Pointer */ #define USIC_INPR_RINP_MASK (7 << USIC_INPR_RINP_SHIFT) -#define USIC_INPR_AINP_SHIFT (12) /* Bits 12-14: */ +# define USIC_INPR_RINP_SR0 (0 << USIC_INPR_RINP_SHIFT) /* Output SR0 activated */ +# define USIC_INPR_RINP_SR1 (1 << USIC_INPR_RINP_SHIFT) /* Output SR1 activated */ +# define USIC_INPR_RINP_SR2 (2 << USIC_INPR_RINP_SHIFT) /* Output SR2 activated */ +# define USIC_INPR_RINP_SR3 (3 << USIC_INPR_RINP_SHIFT) /* Output SR3 activated */ +# define USIC_INPR_RINP_SR4 (4 << USIC_INPR_RINP_SHIFT) /* Output SR4 activated */ +# define USIC_INPR_RINP_SR5 (5 << USIC_INPR_RINP_SHIFT) /* Output SR5 activated */ +#define USIC_INPR_AINP_SHIFT (12) /* Bits 12-14: Alternative Receive Interrupt Node Pointer */ #define USIC_INPR_AINP_MASK (7 << USIC_INPR_AINP_SHIFT) -#define USIC_INPR_PINP_SHIFT (16) /* Bits 16-18: */ +# define USIC_INPR_AINP_SR0 (0 << USIC_INPR_AINP_SHIFT) /* Output SR0 activated */ +# define USIC_INPR_AINP_SR1 (1 << USIC_INPR_AINP_SHIFT) /* Output SR1 activated */ +# define USIC_INPR_AINP_SR2 (2 << USIC_INPR_AINP_SHIFT) /* Output SR2 activated */ +# define USIC_INPR_AINP_SR3 (3 << USIC_INPR_AINP_SHIFT) /* Output SR3 activated */ +# define USIC_INPR_AINP_SR4 (4 << USIC_INPR_AINP_SHIFT) /* Output SR4 activated */ +# define USIC_INPR_AINP_SR5 (5 << USIC_INPR_AINP_SHIFT) /* Output SR5 activated */ +#define USIC_INPR_PINP_SHIFT (16) /* Bits 16-18: Protocol Interrupt Node Pointer */ #define USIC_INPR_PINP_MASK (7 << USIC_INPR_PINP_SHIFT) +# define USIC_INPR_PINP_SR0 (0 << USIC_INPR_PINP_SHIFT) /* Output SR0 activated */ +# define USIC_INPR_PINP_SR1 (1 << USIC_INPR_PINP_SHIFT) /* Output SR1 activated */ +# define USIC_INPR_PINP_SR2 (2 << USIC_INPR_PINP_SHIFT) /* Output SR2 activated */ +# define USIC_INPR_PINP_SR3 (3 << USIC_INPR_PINP_SHIFT) /* Output SR3 activated */ +# define USIC_INPR_PINP_SR4 (4 << USIC_INPR_PINP_SHIFT) /* Output SR4 activated */ +# define USIC_INPR_PINP_SR5 (5 << USIC_INPR_PINP_SHIFT) /* Output SR5 activated */ /* Input Control Register 0, Input Control Register 1, Input Control Register 2, * Input Control Register 3, Input Control Register 4, Input Control Register 5 */ -#define USIC_DXCR_DSEL_SHIFT (0) /* Bits 0-2: */ +#define USIC_DXCR_DSEL_SHIFT (0) /* Bits 0-2: Data Selection for Input Signal */ #define USIC_DXCR_DSEL_MASK (7 << USIC_DX0CR_DSEL_SHIFT) -#define USIC_DX1CR_DCEN (1 << 3) /* Bit 3: (DX1CR only) */ -#define USIC_DXCR_INSW (1 << 4) /* Bit 4: */ -#define USIC_DXCR_DFEN (1 << 5) /* Bit 5: */ -#define USIC_DXCR_DSEN (1 << 6) /* Bit 6: */ -#define USIC_DXCR_DPOL (1 << 8) /* Bit 8: */ -#define USIC_DXCR_SFSEL (1 << 9) /* Bit 9: */ -#define USIC_DXCR_CM_SHIFT (10) /* Bits 10-12: */ +# define USIC_DXCR_DSEL_DXA (0 << USIC_DX0CR_DSEL_SHIFT) /* Data input DXnA selected */ +# define USIC_DXCR_DSEL_DXB (1 << USIC_DX0CR_DSEL_SHIFT) /* Data input DXnB selected */ +# define USIC_DXCR_DSEL_DXC (2 << USIC_DX0CR_DSEL_SHIFT) /* Data input DXnC selected */ +# define USIC_DXCR_DSEL_DXD (3 << USIC_DX0CR_DSEL_SHIFT) /* Data input DXnD selected */ +# define USIC_DXCR_DSEL_DXE (4 << USIC_DX0CR_DSEL_SHIFT) /* Data input DXnE selected */ +# define USIC_DXCR_DSEL_DXF (5 << USIC_DX0CR_DSEL_SHIFT) /* Data input DXnF selected */ +# define USIC_DXCR_DSEL_DXG (6 << USIC_DX0CR_DSEL_SHIFT) /* Data input DXnG selected */ +# define USIC_DXCR_DSEL_ONE (7 << USIC_DX0CR_DSEL_SHIFT) /* Data input is always 1 */ +#define USIC_DX1CR_DCEN (1 << 3) /* Bit 3: Delay Compensation Enable (DX1CR only) */ +#define USIC_DXCR_INSW (1 << 4) /* Bit 4: Input Switch */ +#define USIC_DXCR_DFEN (1 << 5) /* Bit 5: Digital Filter Enable */ +#define USIC_DXCR_DSEN (1 << 6) /* Bit 6: Data Synchronization Enable */ +#define USIC_DXCR_DPOL (1 << 8) /* Bit 8: Data Polarity for DXn */ +#define USIC_DXCR_SFSEL (1 << 9) /* Bit 9: Sampling Frequency Selection */ +#define USIC_DXCR_CM_SHIFT (10) /* Bits 10-11: Combination Mode */ #define USIC_DXCR_CM_MASK (3 << USIC_DX0CR_CM_SHIFT) +# define USIC_DXCR_CM_DISABLE (0 << USIC_DX0CR_CM_SHIFT) /* Trigger activation disabled */ +# define USIC_DXCR_CM_RISING (1 << USIC_DX0CR_CM_SHIFT) /* Rising edge activates DXnT */ +# define USIC_DXCR_CM_FALLING (2 << USIC_DX0CR_CM_SHIFT) /* Falling edge activates DXnT */ +# define USIC_DXCR_CM_BOTH (3 << USIC_DX0CR_CM_SHIFT) /* Both edges activate DXnT */ + #define USIC_DXCR_DXS (1 << 15) /* Bit 15: */ /* Shift Control Register */ -#define USIC_SCTR_SDIR (1 << 0) /* Bit 0: */ -#define USIC_SCTR_PDL (1 << 1) /* Bit `: */ -#define USIC_SCTR_DSM_SHIFT (2) /* Bits 2-3: */ +#define USIC_SCTR_SDIR (1 << 0) /* Bit 0: Shift Direction */ +#define USIC_SCTR_PDL (1 << 1) /* Bit 1: Passive Data Level */ +#define USIC_SCTR_DSM_SHIFT (2) /* Bits 2-3: Data Shift Mode */ #define USIC_SCTR_DSM_MASK (3 << USIC_SCTR_DSM_SHIFT) -#define USIC_SCTR_HPCDIR (1 << 4) /* Bit 4: */ -#define USIC_SCTR_DOCFG_SHIFT (6) /* Bits 6-7: */ +# define USIC_SCTR_DSM_1BIT (0 << USIC_SCTR_DSM_SHIFT) /* Data is shifted one bit at a time */ +# define USIC_SCTR_DSM_2BITS (2 << USIC_SCTR_DSM_SHIFT) /* Data is shifted two bits at a time */ +# define USIC_SCTR_DSM_4BITS (3 << USIC_SCTR_DSM_SHIFT) /* Data is shifted four bits at a time */ +#define USIC_SCTR_HPCDIR (1 << 4) /* Bit 4: Port Control Direction */ +#define USIC_SCTR_DOCFG_SHIFT (6) /* Bits 6-7: Data Output Configuration */ #define USIC_SCTR_DOCFG_MASK (3 << USIC_SCTR_DOCFG_SHIFT) -#define USIC_SCTR_TRM_SHIFT (8) /* Bits 8-9: */ + #define USIC_SCTR_DOCFG_SHIFT (0 << USIC_SCTR_DOCFG_SHIFT) /* DOUTx = shift data value */ + #define USIC_SCTR_DOCFG_INVERT (1 << USIC_SCTR_DOCFG_SHIFT) /* DOUTx = inverted shift data value */ +#define USIC_SCTR_TRM_SHIFT (8) /* Bits 8-9: Transmission Mode */ #define USIC_SCTR_TRM_MASK (3 << USIC_SCTR_TRM_SHIFT) -#define USIC_SCTR_FLE_SHIFT (16) /* Bits 16-21: */ +# define USIC_SCTR_TRM_INACTIVE (0 << USIC_SCTR_TRM_SHIFT) /* Inactive */ +# define USIC_SCTR_TRM_0LEVEL (1 << USIC_SCTR_TRM_SHIFT) /* Active at 1-level */ +# define USIC_SCTR_TRM_1LEVEL (2 << USIC_SCTR_TRM_SHIFT) /* Active if it is at 0-level */ +# define USIC_SCTR_TRM_ACTIVE (3 << USIC_SCTR_TRM_SHIFT) /* Active without regard to signal level */ +#define USIC_SCTR_FLE_SHIFT (16) /* Bits 16-21: Frame Length */ #define USIC_SCTR_FLE_MASK (0x3f << USIC_SCTR_FLE_SHIFT) -#define USIC_SCTR_WLE_SHIFT (24) /* Bits 24-27: */ +# define USIC_SCTR_FLE(n) ((uint32_t)(n) << USIC_SCTR_FLE_SHIFT) +#define USIC_SCTR_WLE_SHIFT (24) /* Bits 24-27: Word Length */ #define USIC_SCTR_WLE_MASK (15 << USIC_SCTR_WLE_SHIFT) +# define USIC_SCTR_WLE(n) ((uint32_t)((n)-1) << USIC_SCTR_WLE_SHIFT) /* Transmit Control/Status Register */ -#define USIC_TCSR_WLEMD (1 << 0) /* Bit 0: */ -#define USIC_TCSR_SELMD (1 << 1) /* Bit 1: */ -#define USIC_TCSR_FLEMD (1 << 2) /* Bit 2: */ -#define USIC_TCSR_WAMD (1 << 3) /* Bit 3: */ -#define USIC_TCSR_HPCMD (1 << 4) /* Bit 4: */ -#define USIC_TCSR_SOF (1 << 5) /* Bit 5: */ -#define USIC_TCSR_EOF (1 << 6) /* Bit 6: */ -#define USIC_TCSR_TDV (1 << 7) /* Bit 7: */ -#define USIC_TCSR_TDSSM (1 << 8) /* Bit 8: */ -#define USIC_TCSR_TDEN_SHIFT (10) /* Bits 10-11: */ +#define USIC_TCSR_WLEMD (1 << 0) /* Bit 0: WLE Mode */ +#define USIC_TCSR_SELMD (1 << 1) /* Bit 1: Select Mode */ +#define USIC_TCSR_FLEMD (1 << 2) /* Bit 2: FLE Mode */ +#define USIC_TCSR_WAMD (1 << 3) /* Bit 3: WA Mode */ +#define USIC_TCSR_HPCMD (1 << 4) /* Bit 4: Hardware Port Control Mode */ +#define USIC_TCSR_SOF (1 << 5) /* Bit 5: Start Of Frame */ +#define USIC_TCSR_EOF (1 << 6) /* Bit 6: End Of Frame */ +#define USIC_TCSR_TDV (1 << 7) /* Bit 7: Transmit Data Valid */ +#define USIC_TCSR_TDSSM (1 << 8) /* Bit 8: TBUF Data Single Shot Mode */ +#define USIC_TCSR_TDEN_SHIFT (10) /* Bits 10-11: TBUF Data Enable */ #define USIC_TCSR_TDEN_MASK (3 << USIC_TCSR_TDEN_SHIFT) -#define USIC_TCSR_TDVTR (1 << 12) /* Bit 12: */ -#define USIC_TCSR_WA (1 << 13) /* Bit 13: */ -#define USIC_TCSR_TSOF (1 << 24) /* Bit 24: */ -#define USIC_TCSR_TV (1 << 26) /* Bit 26: */ -#define USIC_TCSR_TVC (1 << 27) /* Bit 27: */ -#define USIC_TCSR_TE (1 << 28) /* Bit 28: */ +# define USIC_TCSR_TDEN_DISABLE (0 << USIC_TCSR_TDEN_SHIFT) /* Transmission of data word disabled */ +# define USIC_TCSR_TDEN_TDIV (1 << USIC_TCSR_TDEN_SHIFT) /* Transmission of data word if TDV = 1 */ +# define USIC_TCSR_TDEN_TDIVDX2S0 (2 << USIC_TCSR_TDEN_SHIFT) /* Transmission of data word if TDV = 1 while DX2S = 0 */ +# define USIC_TCSR_TDEN_TDIVDX2S1 (3 << USIC_TCSR_TDEN_SHIFT) /* Transmission of data word if TDV = 1 while DX2S = 1 */ +#define USIC_TCSR_TDVTR (1 << 12) /* Bit 12: TBUF Data Valid Trigger */ +#define USIC_TCSR_WA (1 << 13) /* Bit 13: Word Addre */ +#define USIC_TCSR_TSOF (1 << 24) /* Bit 24: Transmitted Start Of Frame */ +#define USIC_TCSR_TV (1 << 26) /* Bit 26: Transmission Valid */ +#define USIC_TCSR_TVC (1 << 27) /* Bit 27: Transmission Valid Cumulated */ +#define USIC_TCSR_TE (1 << 28) /* Bit 28: Trigger Event */ /* Protocol Control Register */ -#define USIC_PCR_CTR0 (1 << 0) /* Bit 0: */ -#define USIC_PCR_CTR1 (1 << 1) /* Bit 1: */ -#define USIC_PCR_CTR2 (1 << 2) /* Bit 2: */ -#define USIC_PCR_CTR3 (1 << 3) /* Bit 3: */ -#define USIC_PCR_CTR4 (1 << 4) /* Bit 4: */ -#define USIC_PCR_CTR5 (1 << 5) /* Bit 5: */ -#define USIC_PCR_CTR6 (1 << 6) /* Bit 6: */ -#define USIC_PCR_CTR7 (1 << 7) /* Bit 7: */ -#define USIC_PCR_CTR8 (1 << 8) /* Bit 8: */ -#define USIC_PCR_CTR9 (1 << 9) /* Bit 9: */ -#define USIC_PCR_CTR10 (1 << 10) /* Bit 10: */ -#define USIC_PCR_CTR11 (1 << 11) /* Bit 11: */ -#define USIC_PCR_CTR12 (1 << 12) /* Bit 12: */ -#define USIC_PCR_CTR13 (1 << 13) /* Bit 13: */ -#define USIC_PCR_CTR14 (1 << 14) /* Bit 14: */ -#define USIC_PCR_CTR15 (1 << 15) /* Bit 15: */ -#define USIC_PCR_CTR16 (1 << 16) /* Bit 16: */ -#define USIC_PCR_CTR17 (1 << 17) /* Bit 17: */ -#define USIC_PCR_CTR18 (1 << 18) /* Bit 18: */ -#define USIC_PCR_CTR19 (1 << 19) /* Bit 19: */ -#define USIC_PCR_CTR20 (1 << 20) /* Bit 20: */ -#define USIC_PCR_CTR21 (1 << 21) /* Bit 21: */ -#define USIC_PCR_CTR22 (1 << 22) /* Bit 22: */ -#define USIC_PCR_CTR23 (1 << 23) /* Bit 23: */ -#define USIC_PCR_CTR24 (1 << 24) /* Bit 24: */ -#define USIC_PCR_CTR25 (1 << 25) /* Bit 25: */ -#define USIC_PCR_CTR26 (1 << 26) /* Bit 26: */ -#define USIC_PCR_CTR27 (1 << 27) /* Bit 27: */ -#define USIC_PCR_CTR28 (1 << 28) /* Bit 28: */ -#define USIC_PCR_CTR29 (1 << 29) /* Bit 29: */ -#define USIC_PCR_CTR30 (1 << 30) /* Bit 30: */ -#define USIC_PCR_CTR31 (1 << 31) /* Bit 31: */ +#define USIC_PCR_CTR(n) (1 << (n))/* Bit n: Protocol Control Bit n */ +#define USIC_PCR_CTR0 (1 << 0) /* Bit 0: Protocol Control Bit 0 */ +#define USIC_PCR_CTR1 (1 << 1) /* Bit 1: Protocol Control Bit 1 */ +#define USIC_PCR_CTR2 (1 << 2) /* Bit 2: Protocol Control Bit 2 */ +#define USIC_PCR_CTR3 (1 << 3) /* Bit 3: Protocol Control Bit 3 */ +#define USIC_PCR_CTR4 (1 << 4) /* Bit 4: Protocol Control Bit 4 */ +#define USIC_PCR_CTR5 (1 << 5) /* Bit 5: Protocol Control Bit 5 */ +#define USIC_PCR_CTR6 (1 << 6) /* Bit 6: Protocol Control Bit 6 */ +#define USIC_PCR_CTR7 (1 << 7) /* Bit 7: Protocol Control Bit 7 */ +#define USIC_PCR_CTR8 (1 << 8) /* Bit 8: Protocol Control Bit 8 */ +#define USIC_PCR_CTR9 (1 << 9) /* Bit 9: Protocol Control Bit 9 */ +#define USIC_PCR_CTR10 (1 << 10) /* Bit 10: Protocol Control Bit 10 */ +#define USIC_PCR_CTR11 (1 << 11) /* Bit 11: Protocol Control Bit 11 */ +#define USIC_PCR_CTR12 (1 << 12) /* Bit 12: Protocol Control Bit 12 */ +#define USIC_PCR_CTR13 (1 << 13) /* Bit 13: Protocol Control Bit 13 */ +#define USIC_PCR_CTR14 (1 << 14) /* Bit 14: Protocol Control Bit 14 */ +#define USIC_PCR_CTR15 (1 << 15) /* Bit 15: Protocol Control Bit 15 */ +#define USIC_PCR_CTR16 (1 << 16) /* Bit 16: Protocol Control Bit 16 */ +#define USIC_PCR_CTR17 (1 << 17) /* Bit 17: Protocol Control Bit 17 */ +#define USIC_PCR_CTR18 (1 << 18) /* Bit 18: Protocol Control Bit 18 */ +#define USIC_PCR_CTR19 (1 << 19) /* Bit 19: Protocol Control Bit 19 */ +#define USIC_PCR_CTR20 (1 << 20) /* Bit 20: Protocol Control Bit 20 */ +#define USIC_PCR_CTR21 (1 << 21) /* Bit 21: Protocol Control Bit 21 */ +#define USIC_PCR_CTR22 (1 << 22) /* Bit 22: Protocol Control Bit 22 */ +#define USIC_PCR_CTR23 (1 << 23) /* Bit 23: Protocol Control Bit 23 */ +#define USIC_PCR_CTR24 (1 << 24) /* Bit 24: Protocol Control Bit 24 */ +#define USIC_PCR_CTR25 (1 << 25) /* Bit 25: Protocol Control Bit 25 */ +#define USIC_PCR_CTR26 (1 << 26) /* Bit 26: Protocol Control Bit 26 */ +#define USIC_PCR_CTR27 (1 << 27) /* Bit 27: Protocol Control Bit 27 */ +#define USIC_PCR_CTR28 (1 << 28) /* Bit 28: Protocol Control Bit 28 */ +#define USIC_PCR_CTR29 (1 << 29) /* Bit 29: Protocol Control Bit 29 */ +#define USIC_PCR_CTR30 (1 << 30) /* Bit 30: Protocol Control Bit 30 */ +#define USIC_PCR_CTR31 (1 << 31) /* Bit 31: Protocol Control Bit 31 */ #define USIC_PCR_ASCMODE_SMD (1 << 0) /* Bit 0: */ #define USIC_PCR_ASCMODE_STPB (1 << 1) /* Bit 1: */ @@ -609,44 +690,57 @@ /* Channel Control Register */ -#define USIC_CCR_MODE_SHIFT (0) /* Bits 0-3: */ +#define USIC_CCR_MODE_SHIFT (0) /* Bits 0-3: Operating Mode */ #define USIC_CCR_MODE_MASK (15 << USIC_CCR_MODE_SHIFT) -#define USIC_CCR_HPCEN_SHIFT (6) /* Bits 6-7: */ +# define USIC_CCR_MODE_DISABLE (0 << USIC_CCR_MODE_SHIFT) /* USIC channel is disabled */ +# define USIC_CCR_MODE_SPI (1 << USIC_CCR_MODE_SHIFT) /* SSC (SPI) protocol is selected */ +# define USIC_CCR_MODE_ASC (2 << USIC_CCR_MODE_SHIFT) /* ASC (SCI, UART) protocol is selected */ +# define USIC_CCR_MODE_I2S (3 << USIC_CCR_MODE_SHIFT) /* IIS protocol is selected */ +# define USIC_CCR_MODE_I2C (4 << USIC_CCR_MODE_SHIFT) /* IIC protocol is selected */ +#define USIC_CCR_HPCEN_SHIFT (6) /* Bits 6-7: Hardware Port Control Enable */ #define USIC_CCR_HPCEN_MASK (3 << USIC_CCR_HPCEN_SHIFT) -#define USIC_CCR_PM_SHIFT (8) /* Bits 8-9: */ +# define USIC_CCR_HPCEN_DISABLE (0 << USIC_CCR_HPCEN_SHIFT) /* Port control disabled */ +# define USIC_CCR_HPCEN_DX0_1 (1 << USIC_CCR_HPCEN_SHIFT) /* Port control enabled for DX0 and DOUT0 */ +# define USIC_CCR_HPCEN_DX3 (2 << USIC_CCR_HPCEN_SHIFT) /* Port control enabled for DX3, DX0 and DOUT[1:0] */ +# define USIC_CCR_HPCEN_DX0_2 (3 << USIC_CCR_HPCEN_SHIFT) /* Port control enabled for DX0, DX[5:3] and DOUT[3:0] */ +#define USIC_CCR_PM_SHIFT (8) /* Bits 8-9: Parity Mode */ #define USIC_CCR_PM_MASK (3 << USIC_CCR_PM_SHIFT) -#define USIC_CCR_RSIEN (1 << 10) /* Bit 10: */ -#define USIC_CCR_DLIEN (1 << 11) /* Bit 11: */ -#define USIC_CCR_TSIEN (1 << 12) /* Bit 12: */ -#define USIC_CCR_TBIEN (1 << 13) /* Bit 13: */ -#define USIC_CCR_RIEN (1 << 14) /* Bit 14: */ -#define USIC_CCR_AIEN (1 << 15) /* Bit 15: */ -#define USIC_CCR_BRGIEN (1 << 16) /* Bit 16: */ +# define USIC_CCR_PM_ DISABLE (0 << USIC_CCR_PM_SHIFT) /* Parity generation is disabled */ +# define USIC_CCR_PM_ EVEN (2 << USIC_CCR_PM_SHIFT) /* Even parity is selected */ +# define USIC_CCR_PM_ ODD (3 << USIC_CCR_PM_SHIFT) /* Odd parity is selected */ +#define USIC_CCR_RSIEN (1 << 10) /* Bit 10: Receiver Start Interrupt Enable */ +#define USIC_CCR_DLIEN (1 << 11) /* Bit 11: Data Lost Interrupt Enable */ +#define USIC_CCR_TSIEN (1 << 12) /* Bit 12: Transmit Shift Interrupt Enable */ +#define USIC_CCR_TBIEN (1 << 13) /* Bit 13: Transmit Buffer Interrupt Enable */ +#define USIC_CCR_RIEN (1 << 14) /* Bit 14: Receive Interrupt Enable */ +#define USIC_CCR_AIEN (1 << 15) /* Bit 15: Alternative Receive Interrupt Enable */ +#define USIC_CCR_BRGIEN (1 << 16) /* Bit 16: Baud Rate Generator Interrupt Enable */ /* Capture Mode Timer Register */ -#define USIC_CMTR_CTV_SHIFT (0) /* Bits 0-9: */ +#define USIC_CMTR_CTV_SHIFT (0) /* Bits 0-9: Captured Timer Value */ #define USIC_CMTR_CTV_MASK (0x3ff << USIC_CMTR_CTV_SHIFT) /* Protocol Status Register */ -#define USIC_PSR_ST0 (1 << 0) /* Bit 0: */ -#define USIC_PSR_ST1 (1 << 1) /* Bit 1: */ -#define USIC_PSR_ST2 (1 << 2) /* Bit 2: */ -#define USIC_PSR_ST3 (1 << 3) /* Bit 3: */ -#define USIC_PSR_ST4 (1 << 4) /* Bit 4: */ -#define USIC_PSR_ST5 (1 << 5) /* Bit 5: */ -#define USIC_PSR_ST6 (1 << 6) /* Bit 6: */ -#define USIC_PSR_ST7 (1 << 7) /* Bit 7: */ -#define USIC_PSR_ST8 (1 << 8) /* Bit 8: */ -#define USIC_PSR_ST9 (1 << 9) /* Bit 9: */ -#define USIC_PSR_RSIF (1 << 10) /* Bit 10: */ -#define USIC_PSR_DLIF (1 << 11) /* Bit 11: */ -#define USIC_PSR_TSIF (1 << 12) /* Bit 12: */ -#define USIC_PSR_TBIF (1 << 13) /* Bit 13: */ -#define USIC_PSR_RIF (1 << 14) /* Bit 14: */ -#define USIC_PSR_AIF (1 << 15) /* Bit 15: */ -#define USIC_PSR_BRGIF (1 << 16) /* Bit 16: */ +#define USIC_PSR_ST(n) (1 << (n))/* Bit n: Protocol Status Flag n */ +#define USIC_PSR_ST0 (1 << 0) /* Bit 0: Protocol Status Flag 0 */ +#define USIC_PSR_ST1 (1 << 1) /* Bit 1: Protocol Status Flag 1 */ +#define USIC_PSR_ST2 (1 << 2) /* Bit 2: Protocol Status Flag 2 */ +#define USIC_PSR_ST3 (1 << 3) /* Bit 3: Protocol Status Flag 3 */ +#define USIC_PSR_ST4 (1 << 4) /* Bit 4: Protocol Status Flag 4 */ +#define USIC_PSR_ST5 (1 << 5) /* Bit 5: Protocol Status Flag 5 */ +#define USIC_PSR_ST6 (1 << 6) /* Bit 6: Protocol Status Flag 6 */ +#define USIC_PSR_ST7 (1 << 7) /* Bit 7: Protocol Status Flag 7 */ +#define USIC_PSR_ST8 (1 << 8) /* Bit 8: Protocol Status Flag 8 */ +#define USIC_PSR_ST9 (1 << 9) /* Bit 9: Protocol Status Flag 9 */ +#define USIC_PSR_RSIF (1 << 10) /* Bit 10: Receiver Start Indication Flag */ +#define USIC_PSR_DLIF (1 << 11) /* Bit 11: Data Lost Indication Flag */ +#define USIC_PSR_TSIF (1 << 12) /* Bit 12: Transmit Shift Indication Flag */ +#define USIC_PSR_TBIF (1 << 13) /* Bit 13: Transmit Buffer Indication Flag */ +#define USIC_PSR_RIF (1 << 14) /* Bit 14: Receive Indication Fla */ +#define USIC_PSR_AIF (1 << 15) /* Bit 15: Alternative Receive Indication Flag */ +#define USIC_PSR_BRGIF (1 << 16) /* Bit 16: Baud Rate Generator Indication Fl */ #define USIC_PSR_ASCMODE_TXIDLE (1 << 0) /* Bit 0: */ #define USIC_PSR_ASCMODE_RXIDLE (1 << 1) /* Bit 1: */ @@ -713,114 +807,125 @@ /* Protocol Status Clear Register */ -#define USIC_PSCR_CST0 (1 << 0) /* Bit 0: */ -#define USIC_PSCR_CST1 (1 << 1) /* Bit 1: */ -#define USIC_PSCR_CST2 (1 << 2) /* Bit 2: */ -#define USIC_PSCR_CST3 (1 << 3) /* Bit 3: */ -#define USIC_PSCR_CST4 (1 << 4) /* Bit 4: */ -#define USIC_PSCR_CST5 (1 << 5) /* Bit 5: */ -#define USIC_PSCR_CST6 (1 << 6) /* Bit 6: */ -#define USIC_PSCR_CST7 (1 << 7) /* Bit 7: */ -#define USIC_PSCR_CST8 (1 << 8) /* Bit 8: */ -#define USIC_PSCR_CST9 (1 << 9) /* Bit 9: */ -#define USIC_PSCR_CRSIF (1 << 10) /* Bit 10: */ -#define USIC_PSCR_CDLIF (1 << 11) /* Bit 11: */ -#define USIC_PSCR_CTSIF (1 << 12) /* Bit 12: */ -#define USIC_PSCR_CTBIF (1 << 13) /* Bit 13: */ -#define USIC_PSCR_CRIF (1 << 14) /* Bit 14: */ -#define USIC_PSCR_CAIF (1 << 15) /* Bit 15: */ -#define USIC_PSCR_CBRGIF (1 << 16) /* Bit 16: */ +#define USIC_PSCR_CST(n) (1 << (n))/* Bit n: Clear Status Flag n in PSR */ +#define USIC_PSCR_CST0 (1 << 0) /* Bit 0: Clear Status Flag 0 in PSR */ +#define USIC_PSCR_CST1 (1 << 1) /* Bit 1: Clear Status Flag 1 in PSR */ +#define USIC_PSCR_CST2 (1 << 2) /* Bit 2: Clear Status Flag 2 in PSR */ +#define USIC_PSCR_CST3 (1 << 3) /* Bit 3: Clear Status Flag 3 in PSR */ +#define USIC_PSCR_CST4 (1 << 4) /* Bit 4: Clear Status Flag 4 in PSR */ +#define USIC_PSCR_CST5 (1 << 5) /* Bit 5: Clear Status Flag 5 in PSR */ +#define USIC_PSCR_CST6 (1 << 6) /* Bit 6: Clear Status Flag 6 in PSR */ +#define USIC_PSCR_CST7 (1 << 7) /* Bit 7: Clear Status Flag 7 in PSR */ +#define USIC_PSCR_CST8 (1 << 8) /* Bit 8: Clear Status Flag 8 in PSR */ +#define USIC_PSCR_CST9 (1 << 9) /* Bit 9: Clear Status Flag 9 in PSR */ +#define USIC_PSCR_CRSIF (1 << 10) /* Bit 10: Clear Receiver Start Indication Flag */ +#define USIC_PSCR_CDLIF (1 << 11) /* Bit 11: Clear Data Lost Indication Flag */ +#define USIC_PSCR_CTSIF (1 << 12) /* Bit 12: Clear Transmit Shift Indication Flag */ +#define USIC_PSCR_CTBIF (1 << 13) /* Bit 13: Clear Transmit Buffer Indication Flag */ +#define USIC_PSCR_CRIF (1 << 14) /* Bit 14: Clear Receive Indication Flag */ +#define USIC_PSCR_CAIF (1 << 15) /* Bit 15: Clear Alternative Receive Indication Flag */ +#define USIC_PSCR_CBRGIF (1 << 16) /* Bit 16: Clear Baud Rate Generator Indication Flag */ /* Receiver Buffer Status Register */ -#define USIC_RBUFSR_WLEN_SHIFT (0) /* Bits 0-3: */ +#define USIC_RBUFSR_WLEN_SHIFT (0) /* Bits 0-3: Received Data Word Length in RBUF or RBUFD */ #define USIC_RBUFSR_WLEN_MASK (15 << USIC_RBUFSR_WLEN_SHIFT) -#define USIC_RBUFSR_SOF (1 << 6) /* Bit 6: */ -#define USIC_RBUFSR_PAR (1 << 8) /* Bit 8: */ -#define USIC_RBUFSR_PERR (1 << 9) /* Bit 9: */ -#define USIC_RBUFSR_RDV0 (1 << 13) /* Bit 13: */ -#define USIC_RBUFSR_RDV1 (1 << 14) /* Bit 14: */ -#define USIC_RBUFSR_DS (1 << 15) /* Bit 15: */ +#define USIC_RBUFSR_SOF (1 << 6) /* Bit 6: Start of Frame in RBUF or RBUFD */ +#define USIC_RBUFSR_PAR (1 << 8) /* Bit 8: Protocol-Related Argument in RBUF or RBUFD */ +#define USIC_RBUFSR_PERR (1 << 9) /* Bit 9: Protocol-related Error in RBUF or RBUFD */ +#define USIC_RBUFSR_RDV0 (1 << 13) /* Bit 13: Receive Data Valid in RBUF or RBUFD */ +#define USIC_RBUFSR_RDV1 (1 << 14) /* Bit 14: Receive Data Valid in RBUF or RBUFD */ +#define USIC_RBUFSR_DS (1 << 15) /* Bit 15: Data Source of RBUF or RBUFD */ /* Receiver Buffer Register */ -#define USIC_RBUF_DSR_SHIFT (0) /* Bits 0-15: */ +#define USIC_RBUF_DSR_SHIFT (0) /* Bits 0-15: Received Data */ #define USIC_RBUF_DSR_MASK (0xffff << USIC_RBUF_DSR_SHIFT) /* Receiver Buffer Register for Debugger */ -#define USIC_RBUFD_DSR_SHIFT (0) /* Bits 0-15: */ +#define USIC_RBUFD_DSR_SHIFT (0) /* Bits 0-15: Data from Shift Register */ #define USIC_RBUFD_DSR_MASK (0xffff << USIC_RBUFD_DSR_SHIFT) /* Receiver Buffer Register 0 */ -#define USIC_RBUF0_DSR0_SHIFT (0) /* Bits 0-15: */ +#define USIC_RBUF0_DSR0_SHIFT (0) /* Bits 0-15: Data of Shift Registers 0[3:0] */ #define USIC_RBUF0_DSR0_MASK (0xffff << USIC_RBUF0_DSR0_SHIFT) /* Receiver Buffer Register 1 */ -#define USIC_RBUF1_DSR1_SHIFT (0) /* Bits 0-15: */ +#define USIC_RBUF1_DSR1_SHIFT (0) /* Bits 0-15: Data of Shift Registers 1[3:0] */ #define USIC_RBUF1_DSR1_MASK (0xffff << USIC_RBUF1_DSR1_SHIFT) /* Receiver Buffer 01 Status Register */ -#define USIC_RBUF01SR_WLEN0_SHIFT (0) /* Bits 0-3: */ +#define USIC_RBUF01SR_WLEN0_SHIFT (0) /* Bits 0-3: Received Data Word Length in RBUF0 */ #define USIC_RBUF01SR_WLEN0_MASK (15 << USIC_RBUF01SR_WLEN0_SHIFT) -#define USIC_RBUF01SR_SOF0 (1 << 6) /* Bit 6: */ -#define USIC_RBUF01SR_PAR0 (1 << 8) /* Bit 8: */ -#define USIC_RBUF01SR_PERR0 (1 << 9) /* Bit 9: */ -#define USIC_RBUF01SR_RDV00 (1 << 13) /* Bit 13: */ -#define USIC_RBUF01SR_RDV01 (1 << 14) /* Bit 14: */ -#define USIC_RBUF01SR_DS0 (1 << 15) /* Bit 15: */ -#define USIC_RBUF01SR_WLEN1_SHIFT (16) /* Bits 16-19: */ +#define USIC_RBUF01SR_SOF0 (1 << 6) /* Bit 6: Start of Frame in RBUF0 */ +#define USIC_RBUF01SR_PAR0 (1 << 8) /* Bit 8: Protocol-Related Argument in RBUF0 */ +#define USIC_RBUF01SR_PERR0 (1 << 9) /* Bit 9: Protocol-related Error in RBUF0 */ +#define USIC_RBUF01SR_RDV00 (1 << 13) /* Bit 13: Receive Data Valid in RBUF0 */ +#define USIC_RBUF01SR_RDV01 (1 << 14) /* Bit 14: Receive Data Valid in RBUF1 */ +#define USIC_RBUF01SR_DS0 (1 << 15) /* Bit 15: Data Source */ +#define USIC_RBUF01SR_WLEN1_SHIFT (16) /* Bits 16-19: Received Data Word Length in RBUF1 */ #define USIC_RBUF01SR_WLEN1_MASK (15 << USIC_RBUF01SR_WLEN1_SHIFT) -#define USIC_RBUF01SR_SOF1 (1 << 22) /* Bit 22: */ -#define USIC_RBUF01SR_PAR1 (1 << 24) /* Bit 24: */ -#define USIC_RBUF01SR_PERR1 (1 << 25) /* Bit 25: */ -#define USIC_RBUF01SR_RDV10 (1 << 29) /* Bit 29: */ -#define USIC_RBUF01SR_RDV11 (1 << 30) /* Bit 30: */ -#define USIC_RBUF01SR_DS1 (1 << 31) /* Bit 31: */ +#define USIC_RBUF01SR_SOF1 (1 << 22) /* Bit 22: Start of Frame in RBUF1 */ +#define USIC_RBUF01SR_PAR1 (1 << 24) /* Bit 24: Protocol-Related Argument in RBUF1 */ +#define USIC_RBUF01SR_PERR1 (1 << 25) /* Bit 25: Protocol-related Error in RBU */ +#define USIC_RBUF01SR_RDV10 (1 << 29) /* Bit 29: Receive Data Valid in RBUF0 */ +#define USIC_RBUF01SR_RDV11 (1 << 30) /* Bit 30: Receive Data Valid in RBUF1 */ +#define USIC_RBUF01SR_DS1 (1 << 31) /* Bit 31: Data Source */ /* Flag Modification Register */ -#define USIC_FMR_MTDV_SHIFT (0) /* Bits 0-1: */ +#define USIC_FMR_MTDV_SHIFT (0) /* Bits 0-1: Modify Transmit Data Valid */ #define USIC_FMR_MTDV_MASK (3 << USIC_FMR_MTDV_SHIFT) -#define USIC_FMR_ATVC (1 << 4) /* Bit 4: */ -#define USIC_FMR_CRDV0 (1 << 14) /* Bit 14: */ -#define USIC_FMR_CRDV1 (1 << 15) /* Bit 15: */ -#define USIC_FMR_SIO0 (1 << 16) /* Bit 16: */ -#define USIC_FMR_SIO1 (1 << 17) /* Bit 17: */ -#define USIC_FMR_SIO2 (1 << 18) /* Bit 18: */ -#define USIC_FMR_SIO3 (1 << 19) /* Bit 19: */ -#define USIC_FMR_SIO4 (1 << 20) /* Bit 20: */ -#define USIC_FMR_SIO5 (1 << 21) /* Bit 21: */ +# define USIC_FMR_MTDV_NOACTION (0 << USIC_FMR_MTDV_SHIFT) /* No action */ +# define USIC_FMR_MTDV_TDV (1 << USIC_FMR_MTDV_SHIFT) /* Bit TDV is set, TE is unchanged */ +# define USIC_FMR_MTDV_TDVTE (2 << USIC_FMR_MTDV_SHIFT) /* Bits TDV and TE are cleared */ +#define USIC_FMR_ATVC (1 << 4) /* Bit 4: Activate Bit TVC */ +#define USIC_FMR_CRDV0 (1 << 14) /* Bit 14: Clear Bits RDV for RBUF0 */ +#define USIC_FMR_CRDV1 (1 << 15) /* Bit 15: Clear Bit RDV for RBUF1 */ +#define USIC_FMR_SIO0 (1 << 16) /* Bit 16: Set Interrupt Output SR0 */ +#define USIC_FMR_SIO1 (1 << 17) /* Bit 17: Set Interrupt Output SR1 */ +#define USIC_FMR_SIO2 (1 << 18) /* Bit 18: Set Interrupt Output SR2 */ +#define USIC_FMR_SIO3 (1 << 19) /* Bit 19: Set Interrupt Output SR3 */ +#define USIC_FMR_SIO4 (1 << 20) /* Bit 20: Set Interrupt Output SR4 */ +#define USIC_FMR_SIO5 (1 << 21) /* Bit 21: Set Interrupt Output SR5 */ /* Transmit Buffer (32 x 4-bytes) */ -#define USIC_TBUF_TDATA_SHIFT (0) /* Bits 0-15: */ +#define USIC_TBUF_TDATA_SHIFT (0) /* Bits 0-15: Transmit Data */ #define USIC_TBUF_TDATA_MASK (0xffff << USIC_TBUF_TDATA_SHIFT) /* USIC FIFO Registers */ /* Bypass Data Register */ -#define USIC_BYP_BDATA_SHIFT (0) /* Bits 0-15: */ +#define USIC_BYP_BDATA_SHIFT (0) /* Bits 0-15: Bypass Data */ #define USIC_BYP_BDATA_MASK (0xffff << USIC_BYP_BDATA_SHIFT) /* Bypass Control Register */ -#define USIC_BYPCR_BWLE_SHIFT (0) /* Bits 0-3: */ +#define USIC_BYPCR_BWLE_SHIFT (0) /* Bits 0-3: Bypass Word Length */ #define USIC_BYPCR_BWLE_MASK (15 << USIC_BYPCR_BWLE_SHIFT) -#define USIC_BYPCR_BDSSM (1 << 8) /* Bit 8: */ -#define USIC_BYPCR_BDEN_SHIFT (10) /* Bits 10-11: */ + #define USIC_BYPCR_BWLE(n) ((uint32_t)((n)-1) << USIC_BYPCR_BWLE_SHIFT) +#define USIC_BYPCR_BDSSM (1 << 8) /* Bit 8: Bypass Data Single Shot Mode */ +#define USIC_BYPCR_BDEN_SHIFT (10) /* Bits 10-11: Bypass Data Enable */ #define USIC_BYPCR_BDEN_MASK (3 << USIC_BYPCR_BDEN_SHIFT) -#define USIC_BYPCR_BDVTR (1 << 12) /* Bit 12: */ -#define USIC_BYPCR_BPRIO (1 << 13) /* Bit 13: */ -#define USIC_BYPCR_BDV (1 << 15) /* Bit 15: */ -#define USIC_BYPCR_BSELO_SHIFT (16) /* Bits 16-20: */ +# define USIC_BYPCR_BDEN_DISABLE (0 << USIC_BYPCR_BDEN_SHIFT) /* Transfer of bypass data is disabled */ +# define USIC_BYPCR_BDEN_ENABLED (1 << USIC_BYPCR_BDEN_SHIFT) /* Transfer of bypass data to TBUF if BDV = 1 */ +# define USIC_BYPCR_BDEN_GATED0 (2 << USIC_BYPCR_BDEN_SHIFT) /* Bypass data transferred if BDV = 1 and DX2S = 0 */ +# define USIC_BYPCR_BDEN_GATED1 (3 << USIC_BYPCR_BDEN_SHIFT) /* Bypass data transferred if BDV = 1 and DX2S = 1 */ +#define USIC_BYPCR_BDVTR (1 << 12) /* Bit 12: Bypass Data Valid Trigger */ +#define USIC_BYPCR_BPRIO (1 << 13) /* Bit 13: Bypass Priority */ +#define USIC_BYPCR_BDV (1 << 15) /* Bit 15: Bypass Data Valid */ +#define USIC_BYPCR_BSELO_SHIFT (16) /* Bits 16-20: Bypass Select Outputs */ #define USIC_BYPCR_BSELO_MASK (31 << USIC_BYPCR_BSELO_SHIFT) -#define USIC_BYPCR_BHPC_SHIFT (21) /* Bits 21-23: */ +# define USIC_BYPCR_BSELO(n) ((uint32_t)(n) << USIC_BYPCR_BSELO_SHIFT) +#define USIC_BYPCR_BHPC_SHIFT (21) /* Bits 21-23: Bypass Hardware Port Control */ #define USIC_BYPCR_BHPC_MASK (7 << USIC_BYPCR_BHPC_SHIFT) +# define USIC_BYPCR_BHPC(n) ((uint32_t)(n) << USIC_BYPCR_BHPC_SHIFT) /* Transmitter Buffer Control Register */ @@ -875,34 +980,36 @@ /* Transmit/Receive Buffer Status Register */ -#define USIC_TRBSR_SRBI (1 << 0) /* Bit 0: */ -#define USIC_TRBSR_RBERI (1 << 1) /* Bit 1: */ -#define USIC_TRBSR_ARBI (1 << 2) /* Bit 2: */ -#define USIC_TRBSR_REMPTY (1 << 3) /* Bit 3: */ -#define USIC_TRBSR_RFULL (1 << 4) /* Bit 4: */ -#define USIC_TRBSR_RBUS (1 << 5) /* Bit 5: */ -#define USIC_TRBSR_SRBT (1 << 6) /* Bit 6: */ -#define USIC_TRBSR_STBI (1 << 8) /* Bit 8: */ -#define USIC_TRBSR_TBERI (1 << 9) /* Bit 9: */ -#define USIC_TRBSR_TEMPTY (1 << 11) /* Bit 11: */ -#define USIC_TRBSR_TFULL (1 << 12) /* Bit 12: */ -#define USIC_TRBSR_TBUS (1 << 13) /* Bit 13: */ -#define USIC_TRBSR_STBT (1 << 14) /* Bit 14: */ -#define USIC_TRBSR_RBFLVL_SHIFT (16) /* Bits 16-22: */ +#define USIC_TRBSR_SRBI (1 << 0) /* Bit 0: Standard Receive Buffer Event */ +#define USIC_TRBSR_RBERI (1 << 1) /* Bit 1: Receive Buffer Error Event */ +#define USIC_TRBSR_ARBI (1 << 2) /* Bit 2: Alternative Receive Buffer Event */ +#define USIC_TRBSR_REMPTY (1 << 3) /* Bit 3: Receive Buffer Empty */ +#define USIC_TRBSR_RFULL (1 << 4) /* Bit 4: Receive Buffer Full */ +#define USIC_TRBSR_RBUS (1 << 5) /* Bit 5: Receive Buffer Busy */ +#define USIC_TRBSR_SRBT (1 << 6) /* Bit 6: Standard Receive Buffer Event Trigger */ +#define USIC_TRBSR_STBI (1 << 8) /* Bit 8: Standard Transmit Buffer Event */ +#define USIC_TRBSR_TBERI (1 << 9) /* Bit 9: Transmit Buffer Error Event */ +#define USIC_TRBSR_TEMPTY (1 << 11) /* Bit 11: Transmit Buffer Empty */ +#define USIC_TRBSR_TFULL (1 << 12) /* Bit 12: Transmit Buffer Full */ +#define USIC_TRBSR_TBUS (1 << 13) /* Bit 13: Transmit Buffer Busy */ +#define USIC_TRBSR_STBT (1 << 14) /* Bit 14: Standard Transmit Buffer Event Trigger */ +#define USIC_TRBSR_RBFLVL_SHIFT (16) /* Bits 16-22: Receive Buffer Filling Level */ #define USIC_TRBSR_RBFLVL_MASK (0x7f << USIC_TRBSR_RBFLVL_SHIFT) -#define USIC_TRBSR_TBFLVL_SHIFT (24) /* Bits 22-28: */ +# define USIC_TRBSR_RBFLVL(n) ((uint32_t)(n) << USIC_TRBSR_RBFLVL_SHIFT) +#define USIC_TRBSR_TBFLVL_SHIFT (24) /* Bits 22-28: Transmit Buffer Filling Level */ #define USIC_TRBSR_TBFLVL_MASK (0x7f << USIC_TRBSR_TBFLVL_SHIFT) +# define USIC_TRBSR_TBFLVL(n) ((uint32_t)(n) << USIC_TRBSR_TBFLVL_SHIFT) /* Transmit/Receive Buffer Status Clear Register */ -#define USIC_TRBSCR_CSRBI (1 << 0) /* Bit 0: */ -#define USIC_TRBSCR_CRBERI (1 << 1) /* Bit 1: */ -#define USIC_TRBSCR_CARBI (1 << 2) /* Bit 2: */ -#define USIC_TRBSCR_CSTBI (1 << 8) /* Bit 8: */ -#define USIC_TRBSCR_CTBERI (1 << 9) /* Bit 9: */ -#define USIC_TRBSCR_CBDV (1 << 10) /* Bit 10: */ -#define USIC_TRBSCR_FLUSHRB (1 << 14) /* Bit 14: */ -#define USIC_TRBSCR_FLUSHTB (1 << 15) /* Bit 15: */ +#define USIC_TRBSCR_CSRBI (1 << 0) /* Bit 0: Clear Standard Receive Buffer Event */ +#define USIC_TRBSCR_CRBERI (1 << 1) /* Bit 1: Clear Receive Buffer Error Event */ +#define USIC_TRBSCR_CARBI (1 << 2) /* Bit 2: Clear Alternative Receive Buffer Event */ +#define USIC_TRBSCR_CSTBI (1 << 8) /* Bit 8: Clear Standard Transmit Buffer Event */ +#define USIC_TRBSCR_CTBERI (1 << 9) /* Bit 9: Clear Transmit Buffer Error Event */ +#define USIC_TRBSCR_CBDV (1 << 10) /* Bit 10: Clear Bypass Data Valid */ +#define USIC_TRBSCR_FLUSHRB (1 << 14) /* Bit 14: Flush Receive Buffer */ +#define USIC_TRBSCR_FLUSHTB (1 << 15) /* Bit 15: Flush Transmit Buffer */ /* Receiver Buffer Output Register */ From 064ae17af5f6bd5ba21b83e0bf4afea48309d5ac Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 19 Mar 2017 09:46:57 -0600 Subject: [PATCH 42/81] XMC4xxx: Finishes UIC register definition header file. --- arch/arm/src/xmc4/chip/xmc4_usic.h | 347 +++++++++++++++++------------ 1 file changed, 203 insertions(+), 144 deletions(-) diff --git a/arch/arm/src/xmc4/chip/xmc4_usic.h b/arch/arm/src/xmc4/chip/xmc4_usic.h index d6d5299cbd3..0b49ebfff42 100644 --- a/arch/arm/src/xmc4/chip/xmc4_usic.h +++ b/arch/arm/src/xmc4/chip/xmc4_usic.h @@ -536,8 +536,7 @@ # define USIC_DXCR_CM_RISING (1 << USIC_DX0CR_CM_SHIFT) /* Rising edge activates DXnT */ # define USIC_DXCR_CM_FALLING (2 << USIC_DX0CR_CM_SHIFT) /* Falling edge activates DXnT */ # define USIC_DXCR_CM_BOTH (3 << USIC_DX0CR_CM_SHIFT) /* Both edges activate DXnT */ - -#define USIC_DXCR_DXS (1 << 15) /* Bit 15: */ +#define USIC_DXCR_DXS (1 << 15) /* Bit 15: Synchronized Data Value */ /* Shift Control Register */ @@ -626,67 +625,80 @@ #define USIC_PCR_CTR30 (1 << 30) /* Bit 30: Protocol Control Bit 30 */ #define USIC_PCR_CTR31 (1 << 31) /* Bit 31: Protocol Control Bit 31 */ -#define USIC_PCR_ASCMODE_SMD (1 << 0) /* Bit 0: */ -#define USIC_PCR_ASCMODE_STPB (1 << 1) /* Bit 1: */ -#define USIC_PCR_ASCMODE_IDM (1 << 2) /* Bit 2: */ -#define USIC_PCR_ASCMODE_SBIEN (1 << 3) /* Bit 3: */ -#define USIC_PCR_ASCMODE_CDEN (1 << 4) /* Bit 4: */ -#define USIC_PCR_ASCMODE_RNIEN (1 << 5) /* Bit 5: */ -#define USIC_PCR_ASCMODE_FEIEN (1 << 6) /* Bit 6: */ -#define USIC_PCR_ASCMODE_FFIEN (1 << 7) /* Bit 7: */ -#define USIC_PCR_ASCMODE_SP_SHIFT (8) /* Bits 8-12: */ +#define USIC_PCR_ASCMODE_SMD (1 << 0) /* Bit 0: Sample Mode */ +#define USIC_PCR_ASCMODE_STPB (1 << 1) /* Bit 1: Stop Bits */ +#define USIC_PCR_ASCMODE_IDM (1 << 2) /* Bit 2: Idle Detection Mode */ +#define USIC_PCR_ASCMODE_SBIEN (1 << 3) /* Bit 3: Synchronization Break Interrupt Enable */ +#define USIC_PCR_ASCMODE_CDEN (1 << 4) /* Bit 4: Collision Detection Enable */ +#define USIC_PCR_ASCMODE_RNIEN (1 << 5) /* Bit 5: Receiver Noise Detection Interrupt Enable */ +#define USIC_PCR_ASCMODE_FEIEN (1 << 6) /* Bit 6: Format Error Interrupt Enable */ +#define USIC_PCR_ASCMODE_FFIEN (1 << 7) /* Bit 7: Frame Finished Interrupt Enable */ +#define USIC_PCR_ASCMODE_SP_SHIFT (8) /* Bits 8-12: Sample Point */ #define USIC_PCR_ASCMODE_SP_MASK (31 << USIC_PCR_ASCMODE_SP_SHIFT) -#define USIC_PCR_ASCMODE_PL_SHIFT (13) /* Bits 13-15: */ +# define USIC_PCR_ASCMODE_SP(n) ((uint32_t)(n) << USIC_PCR_ASCMODE_SP_SHIFT) +#define USIC_PCR_ASCMODE_PL_SHIFT (13) /* Bits 13-15: Pulse Length */ #define USIC_PCR_ASCMODE_PL_MASK (7 << USIC_PCR_ASCMODE_PL_SHIFT) -#define USIC_PCR_ASCMODE_RSTEN (1 << 16) /* Bit 16: */ -#define USIC_PCR_ASCMODE_TSTEN (1 << 17) /* Bit 16: */ -#define USIC_PCR_ASCMODE_MCLK (1 << 31) /* Bit 31: */ + #define USIC_PCR_ASCMODE_PL(n) ((uint32_t)((n)-1) << USIC_PCR_ASCMODE_PL_SHIFT) +#define USIC_PCR_ASCMODE_RSTEN (1 << 16) /* Bit 16: Receiver Status Enable */ +#define USIC_PCR_ASCMODE_TSTEN (1 << 17) /* Bit 17: Transmitter Status Enable */ +#define USIC_PCR_ASCMODE_MCLK (1 << 31) /* Bit 31: Master Clock Enable */ -#define USIC_PCR_SSCMODE_MSLSEN (1 << 0) /* Bit 0: */ -#define USIC_PCR_SSCMODE_SELCTR (1 << 1) /* Bit 1: */ -#define USIC_PCR_SSCMODE_SELINV (1 << 2) /* Bit 2: */ -#define USIC_PCR_SSCMODE_FEM (1 << 3) /* Bit 3: */ -#define USIC_PCR_SSCMODE_CTQSEL1_SHIFT (4) /* Bits 4-5: */ -#define USIC_PCR_SSCMODE_CTQSEL1_MASK (3 << USIC_PCR_SSCMODE_CTQSEL1_SHIFT) -#define USIC_PCR_SSCMODE_PCTQ1_SHIFT (6) /* Bits 6-7: */ +#define USIC_PCR_SSCMODE_MSLSEN (1 << 0) /* Bit 0: MSLS Enable */ +#define USIC_PCR_SSCMODE_SELCTR (1 << 1) /* Bit 1: Select Control */ +#define USIC_PCR_SSCMODE_SELINV (1 << 2) /* Bit 2: Select Inversion */ +#define USIC_PCR_SSCMODE_FEM (1 << 3) /* Bit 3: Frame End Mode */ +#define USIC_PCR_SSCMODE_CTQSEL1_SHIFT (4) /* Bits 4-5: Input Frequency Selection */ +#define USIC_PCR_SSCMODE_CTQSEL1_MASK (3 << USIC_PCR_SSCMODE_CTQSEL1_SHIFT) +# define USIC_PCR_SSCMODE_CTQSEL1_FPDIV (0 << USIC_PCR_SSCMODE_CTQSEL1_SHIFT) /* fCTQIN = fPDIV */ +# define USIC_PCR_SSCMODE_CTQSEL1_FPPP (1 << USIC_PCR_SSCMODE_CTQSEL1_SHIFT) /* fCTQIN = fPPP */ +# define USIC_PCR_SSCMODE_CTQSEL1_FSCLK (2 << USIC_PCR_SSCMODE_CTQSEL1_SHIFT) /* fCTQIN = fSCLK */ +# define USIC_PCR_SSCMODE_CTQSEL1_FMCLK (3 << USIC_PCR_SSCMODE_CTQSEL1_SHIFT) /* fCTQIN = fMCLK */ +#define USIC_PCR_SSCMODE_PCTQ1_SHIFT (6) /* Bits 6-7: Divider Factor PCTQ1 for Tiw and Tnf */ #define USIC_PCR_SSCMODE_PCTQ1_MASK (3 << USIC_PCR_SSCMODE_PCTQ1_SHIFT) -#define USIC_PCR_SSCMODE_DCTQ1_SHIFT (8) /* Bits 8-12: */ -#define USIC_PCR_SSCMODE_DCTQ1_MASK (0x1f << USIC_PCR_SSCMODE_DCTQ1_SHIFT) -#define USIC_PCR_SSCMODE_PARIEN (1 << 13) /* Bit 13: */ -#define USIC_PCR_SSCMODE_MSLSIEN (1 << 14) /* Bit 14: */ -#define USIC_PCR_SSCMODE_DX2TIEN (1 << 15) /* Bit 15: */ -#define USIC_PCR_SSCMODE_SELO_SHIFT (16) /* Bits 16-23: */ +# define USIC_PCR_SSCMODE_PCTQ1(n) ((uint32_t)((n)-1) << USIC_PCR_SSCMODE_PCTQ1_SHIFT) +#define USIC_PCR_SSCMODE_DCTQ1_SHIFT (8) /* Bits 8-12: Divider Factor DCTQ1 for Tiw and Tnf */ +# define USIC_PCR_SSCMODE_DCTQ1(n) (0x1f << USIC_PCR_SSCMODE_DCTQ1_SHIFT) +#define USIC_PCR_SSCMODE_DCTQ1_MASK ((uint32_t)((n)-1) << USIC_PCR_SSCMODE_DCTQ1_SHIFT) +#define USIC_PCR_SSCMODE_PARIEN (1 << 13) /* Bit 13: Parity Error Interrupt Enable */ +#define USIC_PCR_SSCMODE_MSLSIEN (1 << 14) /* Bit 14: MSLS Interrupt Enable */ +#define USIC_PCR_SSCMODE_DX2TIEN (1 << 15) /* Bit 15: DX2T Interrupt Enable */ +#define USIC_PCR_SSCMODE_SELO_SHIFT (16) /* Bits 16-23: Select Output */ #define USIC_PCR_SSCMODE_SELO_MASK (0xff << USIC_PCR_SSCMODE_SELO_SHIFT) -#define USIC_PCR_SSCMODE_TIWEN (1 << 24) /* Bit 24: */ -#define USIC_PCR_SSCMODE_SLPHSEL (1 << 25) /* Bit 25: */ -#define USIC_PCR_SSCMODE_MCLK (1 << 31) /* Bit 31: */ +# define USIC_PCR_SSCMODE_SELO(n) (1 << ((n) + USIC_PCR_SSCMODE_SELO_SHIFT)) +#define USIC_PCR_SSCMODE_TIWEN (1 << 24) /* Bit 24: Enable Inter-Word Delay Tiw */ +#define USIC_PCR_SSCMODE_SLPHSEL (1 << 25) /* Bit 25: Slave Mode Clock Phase Select */ +#define USIC_PCR_SSCMODE_MCLK (1 << 31) /* Bit 31: Master Clock Enable */ -#define USIC_PCR_IICMODE_SLAD_SHIFT (0) /* Bits 0-15: */ +#define USIC_PCR_IICMODE_SLAD_SHIFT (0) /* Bits 0-15: Slave Address */ #define USIC_PCR_IICMODE_SLAD_MASK (0xffff << USIC_PCR_IICMODE_SLAD_SHIFT) -#define USIC_PCR_IICMODE_ACK00 (1 << 16) /* Bit 16: */ -#define USIC_PCR_IICMODE_STIM (1 << 17) /* Bit 17: */ -#define USIC_PCR_IICMODE_SCRIEN (1 << 18) /* Bit 18: */ -#define USIC_PCR_IICMODE_RSCRIEN (1 << 19) /* Bit 19: */ -#define USIC_PCR_IICMODE_PCRIEN (1 << 20) /* Bit 20: */ -#define USIC_PCR_IICMODE_NACKIEN (1 << 21) /* Bit 21: */ -#define USIC_PCR_IICMODE_ARLIEN (1 << 22) /* Bit 22: */ -#define USIC_PCR_IICMODE_SRRIEN (1 << 23) /* Bit 23: */ -#define USIC_PCR_IICMODE_ERRIEN (1 << 24) /* Bit 24: */ -#define USIC_PCR_IICMODE_SACKDIS (1 << 25) /* Bit 25: */ -#define USIC_PCR_IICMODE_HDEL_SHIFT (26) /* Bits 26-29: */ +# define USIC_PCR_IICMODE_SLAD(n) ((uint32_t)(n) << USIC_PCR_IICMODE_SLAD_SHIFT) +#define USIC_PCR_IICMODE_ACK00 (1 << 16) /* Bit 16: Acknowledge 00H */ +#define USIC_PCR_IICMODE_STIM (1 << 17) /* Bit 17: Symbol Timing */ +#define USIC_PCR_IICMODE_SCRIEN (1 << 18) /* Bit 18: Start Condition Received Interrupt Enable */ +#define USIC_PCR_IICMODE_RSCRIEN (1 << 19) /* Bit 19: Repeated Start Condition Received Interrupt */ +#define USIC_PCR_IICMODE_PCRIEN (1 << 20) /* Bit 20: Stop Condition Received Interrupt Enable */ +#define USIC_PCR_IICMODE_NACKIEN (1 << 21) /* Bit 21: Non-Acknowledge Interrupt Enable */ +#define USIC_PCR_IICMODE_ARLIEN (1 << 22) /* Bit 22: Arbitration Lost Interrupt Enable */ +#define USIC_PCR_IICMODE_SRRIEN (1 << 23) /* Bit 23: Slave Read Request Interrupt Enable */ +#define USIC_PCR_IICMODE_ERRIEN (1 << 24) /* Bit 24: Error Interrupt Enable */ +#define USIC_PCR_IICMODE_SACKDIS (1 << 25) /* Bit 25: Slave Acknowledge Disable */ +#define USIC_PCR_IICMODE_HDEL_SHIFT (26) /* Bits 26-29: Hardware Delay */ #define USIC_PCR_IICMODE_HDEL_MASK (15 << USIC_PCR_IICMODE_HDEL_SHIFT) -#define USIC_PCR_IICMODE_ACKIEN (1 << 30) /* Bit 30: */ -#define USIC_PCR_IICMODE_MCLK (1 << 31) /* Bit 31: */ +# define USIC_PCR_IICMODE_HDEL(n) ((uint32_t)(n) << USIC_PCR_IICMODE_HDEL_SHIFT) +#define USIC_PCR_IICMODE_ACKIEN (1 << 30) /* Bit 30: Acknowledge Interrupt Enable */ +#define USIC_PCR_IICMODE_MCLK (1 << 31) /* Bit 31: Master Clock Enable */ -#define USIC_PCR_IISMODE_WAGEN (1 << 0) /* Bit 0: */ -#define USIC_PCR_IISMODE_DTEN (1 << 1) /* Bit 1: */ -#define USIC_PCR_IISMODE_SELINV (1 << 2) /* Bit 2: */ -#define USIC_PCR_IISMODE_WAFEIEN (1 << 4) /* Bit 4: */ -#define USIC_PCR_IISMODE_WAREIEN (1 << 5) /* Bit 5: */ -#define USIC_PCR_IISMODE_ENDIEN (1 << 6) /* Bit 6: */ -#define USIC_PCR_IISMODE_TDEL_SHIFT (16) /* Bits 15-21: */ +#define USIC_PCR_IISMODE_WAGEN (1 << 0) /* Bit 0: WA Generation Enable */ +#define USIC_PCR_IISMODE_DTEN (1 << 1) /* Bit 1: Data Transfers Enable */ +#define USIC_PCR_IISMODE_SELINV (1 << 2) /* Bit 2: Select Inversion */ +#define USIC_PCR_IISMODE_WAFEIEN (1 << 4) /* Bit 4: WA Falling Edge Interrupt Enable */ +#define USIC_PCR_IISMODE_WAREIEN (1 << 5) /* Bit 5: WA Rising Edge Interrupt Enable */ +#define USIC_PCR_IISMODE_ENDIEN (1 << 6) /* Bit 6: END Interrupt Enable */ +#define USIC_PCR_IISMODE_DX2TIEN (1 << 15) /* Bit 15: DX2T Interrupt Enable */ +#define USIC_PCR_IISMODE_TDEL_SHIFT (16) /* Bits 16-21: Transfer Delay */ #define USIC_PCR_IISMODE_TDEL_MASK (0x3f << USIC_PCR_IISMODE_TDEL_SHIFT) -#define USIC_PCR_IISMODE_MCLK (1 << 31) /* Bit 31: */ +# define USIC_PCR_IISMODE_TDEL(n) ((uint32_t)(n) << USIC_PCR_IISMODE_TDEL_SHIFT) +#define USIC_PCR_IISMODE_MCLK (1 << 31) /* Bit 31: Master Clock Enable */ /* Channel Control Register */ @@ -742,68 +754,68 @@ #define USIC_PSR_AIF (1 << 15) /* Bit 15: Alternative Receive Indication Flag */ #define USIC_PSR_BRGIF (1 << 16) /* Bit 16: Baud Rate Generator Indication Fl */ -#define USIC_PSR_ASCMODE_TXIDLE (1 << 0) /* Bit 0: */ -#define USIC_PSR_ASCMODE_RXIDLE (1 << 1) /* Bit 1: */ -#define USIC_PSR_ASCMODE_SBD (1 << 2) /* Bit 2: */ -#define USIC_PSR_ASCMODE_COL (1 << 3) /* Bit 3: */ -#define USIC_PSR_ASCMODE_RNS (1 << 4) /* Bit 4: */ -#define USIC_PSR_ASCMODE_FER0 (1 << 5) /* Bit 5: */ -#define USIC_PSR_ASCMODE_FER1 (1 << 6) /* Bit 6: */ -#define USIC_PSR_ASCMODE_RFF (1 << 7) /* Bit 7: */ -#define USIC_PSR_ASCMODE_TFF (1 << 8) /* Bit 8: */ -#define USIC_PSR_ASCMODE_BUSY (1 << 9) /* Bit 9: */ -#define USIC_PSR_ASCMODE_RSIF (1 << 10) /* Bit 10: */ -#define USIC_PSR_ASCMODE_DLIF (1 << 11) /* Bit 11: */ -#define USIC_PSR_ASCMODE_TSIF (1 << 12) /* Bit 12: */ -#define USIC_PSR_ASCMODE_TBIF (1 << 13) /* Bit 13: */ -#define USIC_PSR_ASCMODE_RIF (1 << 14) /* Bit 14: */ -#define USIC_PSR_ASCMODE_AIF (1 << 15) /* Bit 15: */ -#define USIC_PSR_ASCMODE_BRGIF (1 << 16) /* Bit 16: */ +#define USIC_PSR_ASCMODE_TXIDLE (1 << 0) /* Bit 0: Transmission Idle */ +#define USIC_PSR_ASCMODE_RXIDLE (1 << 1) /* Bit 1: Reception Idle */ +#define USIC_PSR_ASCMODE_SBD (1 << 2) /* Bit 2: Synchronization Break Detected */ +#define USIC_PSR_ASCMODE_COL (1 << 3) /* Bit 3: Collision Detected */ +#define USIC_PSR_ASCMODE_RNS (1 << 4) /* Bit 4: Receiver Noise Detected */ +#define USIC_PSR_ASCMODE_FER0 (1 << 5) /* Bit 5: Format Error in Stop Bit 0 */ +#define USIC_PSR_ASCMODE_FER1 (1 << 6) /* Bit 6: Format Error in Stop Bit 1 */ +#define USIC_PSR_ASCMODE_RFF (1 << 7) /* Bit 7: Receive Frame Finished */ +#define USIC_PSR_ASCMODE_TFF (1 << 8) /* Bit 8: Transmitter Frame Finished */ +#define USIC_PSR_ASCMODE_BUSY (1 << 9) /* Bit 9: Transfer Status BUSY */ +#define USIC_PSR_ASCMODE_RSIF (1 << 10) /* Bit 10: Receiver Start Indication Flag */ +#define USIC_PSR_ASCMODE_DLIF (1 << 11) /* Bit 11: Data Lost Indication Flag */ +#define USIC_PSR_ASCMODE_TSIF (1 << 12) /* Bit 12: Transmit Shift Indication Flag */ +#define USIC_PSR_ASCMODE_TBIF (1 << 13) /* Bit 13: Transmit Buffer Indication Flag */ +#define USIC_PSR_ASCMODE_RIF (1 << 14) /* Bit 14: Receive Indication Flag */ +#define USIC_PSR_ASCMODE_AIF (1 << 15) /* Bit 15: Alternative Receive Indication Flag */ +#define USIC_PSR_ASCMODE_BRGIF (1 << 16) /* Bit 16: Baud Rate Generator Indication Flag */ -#define USIC_PSR_SSCMODE_MSLS (1 << 0) /* Bit 0: */ -#define USIC_PSR_SSCMODE_DX2S (1 << 1) /* Bit 1: */ -#define USIC_PSR_SSCMODE_MSLSEV (1 << 2) /* Bit 2: */ -#define USIC_PSR_SSCMODE_DX2TEV (1 << 3) /* Bit 3: */ -#define USIC_PSR_SSCMODE_PARERR (1 << 4) /* Bit 4: */ -#define USIC_PSR_SSCMODE_RSIF (1 << 10) /* Bit 10: */ -#define USIC_PSR_SSCMODE_DLIF (1 << 11) /* Bit 11: */ -#define USIC_PSR_SSCMODE_TSIF (1 << 12) /* Bit 12: */ -#define USIC_PSR_SSCMODE_TBIF (1 << 13) /* Bit 13: */ -#define USIC_PSR_SSCMODE_RIF (1 << 14) /* Bit 14: */ -#define USIC_PSR_SSCMODE_AIF (1 << 15) /* Bit 15: */ -#define USIC_PSR_SSCMODE_BRGIF (1 << 16) /* Bit 16: */ +#define USIC_PSR_SSCMODE_MSLS (1 << 0) /* Bit 0: MSLS Status */ +#define USIC_PSR_SSCMODE_DX2S (1 << 1) /* Bit 1: DX2S Status */ +#define USIC_PSR_SSCMODE_MSLSEV (1 << 2) /* Bit 2: MSLS Event Detected */ +#define USIC_PSR_SSCMODE_DX2TEV (1 << 3) /* Bit 3: DX2T Event Detected */ +#define USIC_PSR_SSCMODE_PARERR (1 << 4) /* Bit 4: Parity Error Event Detected */ +#define USIC_PSR_SSCMODE_RSIF (1 << 10) /* Bit 10: Receiver Start Indication Flag */ +#define USIC_PSR_SSCMODE_DLIF (1 << 11) /* Bit 11: Data Lost Indication Flag */ +#define USIC_PSR_SSCMODE_TSIF (1 << 12) /* Bit 12: Transmit Shift Indication Flag */ +#define USIC_PSR_SSCMODE_TBIF (1 << 13) /* Bit 13: Transmit Buffer Indication Flag */ +#define USIC_PSR_SSCMODE_RIF (1 << 14) /* Bit 14: Receive Indication Flag */ +#define USIC_PSR_SSCMODE_AIF (1 << 15) /* Bit 15: Alternative Receive Indication Flag */ +#define USIC_PSR_SSCMODE_BRGIF (1 << 16) /* Bit 16: Baud Rate Generator Indication Flag */ -#define USIC_PSR_IICMODE_SLSEL (1 << 0) /* Bit 0: */ -#define USIC_PSR_IICMODE_WTDF (1 << 1) /* Bit 1: */ -#define USIC_PSR_IICMODE_SCR (1 << 2) /* Bit 2: */ -#define USIC_PSR_IICMODE_RSCR (1 << 3) /* Bit 3: */ -#define USIC_PSR_IICMODE_PCR (1 << 4) /* Bit 4: */ -#define USIC_PSR_IICMODE_NACK (1 << 5) /* Bit 5: */ -#define USIC_PSR_IICMODE_ARL (1 << 6) /* Bit 6: */ -#define USIC_PSR_IICMODE_SRR (1 << 7) /* Bit 7: */ -#define USIC_PSR_IICMODE_ERR (1 << 8) /* Bit 8: */ -#define USIC_PSR_IICMODE_ACK (1 << 9) /* Bit 9: */ -#define USIC_PSR_IICMODE_RSIF (1 << 10) /* Bit 10: */ -#define USIC_PSR_IICMODE_DLIF (1 << 11) /* Bit 11: */ -#define USIC_PSR_IICMODE_TSIF (1 << 12) /* Bit 12: */ -#define USIC_PSR_IICMODE_TBIF (1 << 13) /* Bit 13: */ -#define USIC_PSR_IICMODE_RIF (1 << 14) /* Bit 14: */ -#define USIC_PSR_IICMODE_AIF (1 << 15) /* Bit 15: */ -#define USIC_PSR_IICMODE_BRGIF (1 << 16) /* Bit 16: */ +#define USIC_PSR_IICMODE_SLSEL (1 << 0) /* Bit 0: Slave Select */ +#define USIC_PSR_IICMODE_WTDF (1 << 1) /* Bit 1: Wrong TDF Code Found */ +#define USIC_PSR_IICMODE_SCR (1 << 2) /* Bit 2: Start Condition Received */ +#define USIC_PSR_IICMODE_RSCR (1 << 3) /* Bit 3: Repeated Start Condition Received */ +#define USIC_PSR_IICMODE_PCR (1 << 4) /* Bit 4: Stop Condition Received */ +#define USIC_PSR_IICMODE_NACK (1 << 5) /* Bit 5: Non-Acknowledge Received */ +#define USIC_PSR_IICMODE_ARL (1 << 6) /* Bit 6: Arbitration Lost */ +#define USIC_PSR_IICMODE_SRR (1 << 7) /* Bit 7: Slave Read Request */ +#define USIC_PSR_IICMODE_ERR (1 << 8) /* Bit 8: Error */ +#define USIC_PSR_IICMODE_ACK (1 << 9) /* Bit 9: Acknowledge Received */ +#define USIC_PSR_IICMODE_RSIF (1 << 10) /* Bit 10: Receiver Start Indication Flag */ +#define USIC_PSR_IICMODE_DLIF (1 << 11) /* Bit 11: Data Lost Indication Flag */ +#define USIC_PSR_IICMODE_TSIF (1 << 12) /* Bit 12: Transmit Shift Indication Flag */ +#define USIC_PSR_IICMODE_TBIF (1 << 13) /* Bit 13: Transmit Buffer Indication Flag */ +#define USIC_PSR_IICMODE_RIF (1 << 14) /* Bit 14: Receive Indication Flag */ +#define USIC_PSR_IICMODE_AIF (1 << 15) /* Bit 15: Alternative Receive Indication Flag */ +#define USIC_PSR_IICMODE_BRGIF (1 << 16) /* Bit 16: Baud Rate Generator Indication Flag */ -#define USIC_PSR_IISMODE_WA (1 << 0) /* Bit 0: */ -#define USIC_PSR_IISMODE_DX2S (1 << 1) /* Bit 1: */ -#define USIC_PSR_IISMODE_DX2TEV (1 << 3) /* Bit 3: */ -#define USIC_PSR_IISMODE_WAFE (1 << 4) /* Bit 4: */ -#define USIC_PSR_IISMODE_WARE (1 << 5) /* Bit 5: */ -#define USIC_PSR_IISMODE_END (1 << 6) /* Bit 6: */ -#define USIC_PSR_IISMODE_RSIF (1 << 10) /* Bit 10: */ -#define USIC_PSR_IISMODE_DLIF (1 << 11) /* Bit 11: */ -#define USIC_PSR_IISMODE_TSIF (1 << 12) /* Bit 12: */ -#define USIC_PSR_IISMODE_TBIF (1 << 13) /* Bit 13: */ -#define USIC_PSR_IISMODE_RIF (1 << 14) /* Bit 14: */ -#define USIC_PSR_IISMODE_AIF (1 << 15) /* Bit 15: */ -#define USIC_PSR_IISMODE_BRGIF (1 << 16) /* Bit 16: */ +#define USIC_PSR_IISMODE_WA (1 << 0) /* Bit 0: Word Address */ +#define USIC_PSR_IISMODE_DX2S (1 << 1) /* Bit 1: DX2S Sta */ +#define USIC_PSR_IISMODE_DX2TEV (1 << 3) /* Bit 3: DX2T Event Detected */ +#define USIC_PSR_IISMODE_WAFE (1 << 4) /* Bit 4: WA Falling Edge Event */ +#define USIC_PSR_IISMODE_WARE (1 << 5) /* Bit 5: WA Rising Edge Event */ +#define USIC_PSR_IISMODE_END (1 << 6) /* Bit 6: WA Generation End */ +#define USIC_PSR_IISMODE_RSIF (1 << 10) /* Bit 10: Receiver Start Indication Flag */ +#define USIC_PSR_IISMODE_DLIF (1 << 11) /* Bit 11: Data Lost Indication Flag */ +#define USIC_PSR_IISMODE_TSIF (1 << 12) /* Bit 12: Transmit Shift Indication Flag */ +#define USIC_PSR_IISMODE_TBIF (1 << 13) /* Bit 13: Transmit Buffer Indication Flag */ +#define USIC_PSR_IISMODE_RIF (1 << 14) /* Bit 14: Receive Indication Flag */ +#define USIC_PSR_IISMODE_AIF (1 << 15) /* Bit 15: Alternative Receive Indication Flag */ +#define USIC_PSR_IISMODE_BRGIF (1 << 16) /* Bit 16: Baud Rate Generator Indication Flag */ /* Protocol Status Clear Register */ @@ -929,53 +941,100 @@ /* Transmitter Buffer Control Register */ -#define USIC_TBCTR_DPTR_SHIFT (0) /* Bits 0-1: */ +#define USIC_TBCTR_DPTR_SHIFT (0) /* Bits 0-1: Data Pointer */ #define USIC_TBCTR_DPTR_MASK (3 << USIC_TBCTR_DPTR_SHIFT) -#define USIC_TBCTR_LIMIT_SHIFT (8) /* Bits 8-13: */ +# define USIC_TBCTR_DPTR(n) ((uint32_t)(n) << USIC_TBCTR_DPTR_SHIFT) +#define USIC_TBCTR_LIMIT_SHIFT (8) /* Bits 8-13: Limit For Interrupt Generation */ #define USIC_TBCTR_LIMIT_MASK (0x3f << USIC_TBCTR_LIMIT_SHIFT) -#define USIC_TBCTR_STBTM (1 << 14) /* Bit 14: */ -#define USIC_TBCTR_STBTEN (1 << 15) /* Bit 15: */ -#define USIC_TBCTR_STBINP_SHIFT (16) /* Bits 16-18: */ +# define USIC_TBCTR_LIMIT(n) ((uint32_t)(n) << USIC_TBCTR_LIMIT_SHIFT) +#define USIC_TBCTR_STBTM (1 << 14) /* Bit 14: Standard Transmit Buffer Trigger Mode */ +#define USIC_TBCTR_STBTEN (1 << 15) /* Bit 15: Standard Transmit Buffer Trigger Enable */ +#define USIC_TBCTR_STBINP_SHIFT (16) /* Bits 16-18: Standard Transmit Buffer Interrupt Node Pointer */ #define USIC_TBCTR_STBINP_MASK (7 << USIC_TBCTR_STBINP_SHIFT) -#define USIC_TBCTR_ATBINP_SHIFT (19) /* Bits 19-21: */ +# define USIC_TBCTR_STBINP_SR0 (0 << USIC_TBCTR_STBINP_SHIFT) /* Output SR0 becomes activated */ +# define USIC_TBCTR_STBINP_SR1 (1 << USIC_TBCTR_STBINP_SHIFT) /* Output SR1 becomes activated */ +# define USIC_TBCTR_STBINP_SR2 (2 << USIC_TBCTR_STBINP_SHIFT) /* Output SR2 becomes activated */ +# define USIC_TBCTR_STBINP_SR3 (3 << USIC_TBCTR_STBINP_SHIFT) /* Output SR3 becomes activated */ +# define USIC_TBCTR_STBINP_SR4 (4 << USIC_TBCTR_STBINP_SHIFT) /* Output SR4 becomes activated */ +# define USIC_TBCTR_STBINP_SR5 (5 << USIC_TBCTR_STBINP_SHIFT) /* Output SR5 becomes activated */ +#define USIC_TBCTR_ATBINP_SHIFT (19) /* Bits 19-21: Alternative Transmit Buffer Interrupt Node Pointer */ #define USIC_TBCTR_ATBINP_MASK (7 << USIC_TBCTR_ATBINP_SHIFT) -#define USIC_TBCTR_SIZE_SHIFT (24) /* Bits 24-26: */ +# define USIC_TBCTR_ATBINP_SR0 (0 << USIC_TBCTR_ATBINP_SHIFT) /* Output SR0 becomes activated */ +# define USIC_TBCTR_ATBINP_SR1 (1 << USIC_TBCTR_ATBINP_SHIFT) /* Output SR1 becomes activated */ +# define USIC_TBCTR_ATBINP_SR2 (2 << USIC_TBCTR_ATBINP_SHIFT) /* Output SR2 becomes activated */ +# define USIC_TBCTR_ATBINP_SR3 (3 << USIC_TBCTR_ATBINP_SHIFT) /* Output SR3 becomes activated */ +# define USIC_TBCTR_ATBINP_SR4 (4 << USIC_TBCTR_ATBINP_SHIFT) /* Output SR4 becomes activated */ +# define USIC_TBCTR_ATBINP_SR5 (5 << USIC_TBCTR_ATBINP_SHIFT) /* Output SR5 becomes activated */ +#define USIC_TBCTR_SIZE_SHIFT (24) /* Bits 24-26: Buffer Size */ #define USIC_TBCTR_SIZE_MASK (7 << USIC_TBCTR_SIZE_SHIFT) -#define USIC_TBCTR_LOF (1 << 28) /* Bit 28: */ -#define USIC_TBCTR_STBIEN (1 << 30) /* Bit 30: */ -#define USIC_TBCTR_TBERIEN (1 << 31) /* Bit 31: */ +# define USIC_TBCTR_SIZE_DISABLE (0 << USIC_TBCTR_SIZE_SHIFT) /* FIFO mechanism is disabled */ +# define USIC_TBCTR_SIZE_2 (1 << USIC_TBCTR_SIZE_SHIFT) /* FIFO buffer contains 2 entries */ +# define USIC_TBCTR_SIZE_4 (2 << USIC_TBCTR_SIZE_SHIFT) /* FIFO buffer contains 4 entries */ +# define USIC_TBCTR_SIZE_8 (3 << USIC_TBCTR_SIZE_SHIFT) /* FIFO buffer contains 8 entries */ +# define USIC_TBCTR_SIZE_16 (4 << USIC_TBCTR_SIZE_SHIFT) /* FIFO buffer contains 16 entries */ +# define USIC_TBCTR_SIZE_32 (5 << USIC_TBCTR_SIZE_SHIFT) /* FIFO buffer contains 32 entries */ +# define USIC_TBCTR_SIZE_64 (6 << USIC_TBCTR_SIZE_SHIFT) /* FIFO buffer contains 64 entries */ +#define USIC_TBCTR_LOF (1 << 28) /* Bit 28: Buffer Event on Limit Overflow */ +#define USIC_TBCTR_STBIEN (1 << 30) /* Bit 30: Standard Transmit Buffer Interrupt Enable */ +#define USIC_TBCTR_TBERIEN (1 << 31) /* Bit 31: Transmit Buffer Error Interrupt Enable */ /* Receiver Buffer Control Register */ -#define USIC_RBCTR_DPTR_SHIFT (0) /* Bits 0-5: */ +#define USIC_RBCTR_DPTR_SHIFT (0) /* Bits 0-5: Data Pointer */ #define USIC_RBCTR_DPTR_MASK (0x3f << USIC_RBCTR_DPTR_SHIFT) -#define USIC_RBCTR_LIMIT_SHIFT (8) /* Bits 8-13: */ +# define USIC_RBCTR_DPTR(n) ((uint32_t)(n) << USIC_RBCTR_DPTR_SHIFT) +#define USIC_RBCTR_LIMIT_SHIFT (8) /* Bits 8-13: Limit For Interrupt Generation */ #define USIC_RBCTR_LIMIT_MASK (0x3f << USIC_RBCTR_LIMIT_SHIFT) -#define USIC_RBCTR_SRBTM (1 << 14) /* Bit 14: */ -#define USIC_RBCTR_SRBTEN (1 << 15) /* Bit 15: */ -#define USIC_RBCTR_SRBINP_SHIFT (16) /* Bits 16-18: */ +# define USIC_RBCTR_LIMIT(n) ((uint32_t)(n) << USIC_RBCTR_LIMIT_SHIFT) +#define USIC_RBCTR_SRBTM (1 << 14) /* Bit 14: Standard Receive Buffer Trigger Mode */ +#define USIC_RBCTR_SRBTEN (1 << 15) /* Bit 15: Standard Receive Buffer Trigger Enable */ +#define USIC_RBCTR_SRBINP_SHIFT (16) /* Bits 16-18: Standard Receive Buffer Interrupt Node Pointer */ #define USIC_RBCTR_SRBINP_MASK (7 << USIC_RBCTR_SRBINP_SHIFT) -#define USIC_RBCTR_ARBINP_SHIFT (19) /* Bits 19-21: */ +# define USIC_RBCTR_SRBINP_SR0 (0 << USIC_RBCTR_SRBINP_SHIFT) /* Output SR0 becomes activated */ +# define USIC_RBCTR_SRBINP_SR1 (1 << USIC_RBCTR_SRBINP_SHIFT) /* Output SR1 becomes activated */ +# define USIC_RBCTR_SRBINP_SR2 (2 << USIC_RBCTR_SRBINP_SHIFT) /* Output SR2 becomes activated */ +# define USIC_RBCTR_SRBINP_SR3 (3 << USIC_RBCTR_SRBINP_SHIFT) /* Output SR3 becomes activated */ +# define USIC_RBCTR_SRBINP_SR4 (4 << USIC_RBCTR_SRBINP_SHIFT) /* Output SR4 becomes activated */ +# define USIC_RBCTR_SRBINP_SR5 (5 << USIC_RBCTR_SRBINP_SHIFT) /* Output SR5 becomes activated */ +#define USIC_RBCTR_ARBINP_SHIFT (19) /* Bits 19-21: Alternative Receive Buffer Interrupt Node Pointer */ #define USIC_RBCTR_ARBINP_MASK (7 << USIC_RBCTR_ARBINP_SHIFT) -#define USIC_RBCTR_RCIM_SHIFT (22) /* Bits 22-23: */ +# define USIC_RBCTR_ARBINP_SR0 (0 << USIC_RBCTR_ARBINP_SHIFT) /* Output SR0 becomes activated */ +# define USIC_RBCTR_ARBINP_SR1 (1 << USIC_RBCTR_ARBINP_SHIFT) /* Output SR1 becomes activated */ +# define USIC_RBCTR_ARBINP_SR2 (2 << USIC_RBCTR_ARBINP_SHIFT) /* Output SR2 becomes activated */ +# define USIC_RBCTR_ARBINP_SR3 (3 << USIC_RBCTR_ARBINP_SHIFT) /* Output SR3 becomes activated */ +# define USIC_RBCTR_ARBINP_SR4 (4 << USIC_RBCTR_ARBINP_SHIFT) /* Output SR4 becomes activated */ +# define USIC_RBCTR_ARBINP_SR5 (5 << USIC_RBCTR_ARBINP_SHIFT) /* Output SR5 becomes activated */ +#define USIC_RBCTR_RCIM_SHIFT (22) /* Bits 22-23: Receiver Control Information Mode */ #define USIC_RBCTR_RCIM_MASK (3 << USIC_RBCTR_RCIM_SHIFT) -#define USIC_RBCTR_SIZE_SHIFT (24) /* Bits 24-26: */ +# define USIC_RBCTR_RCIM_MODE0 (0 << USIC_RBCTR_RCIM_SHIFT) /* RCI[4] = PERR, RCI[3:0] = WLEN */ +# define USIC_RBCTR_RCIM_MODE1 (1 << USIC_RBCTR_RCIM_SHIFT) /* RCI[4] = SOF, RCI[3:0] = WLEN */ +# define USIC_RBCTR_RCIM_MODE2 (2 << USIC_RBCTR_RCIM_SHIFT) /* RCI[4] = 0, RCI[3:0] = WLEN */ +# define USIC_RBCTR_RCIM_MODE3 (3 << USIC_RBCTR_RCIM_SHIFT) /* RCI[4] = PERR, RCI[3] = PAR, + * RCI[2:1] = 0, RCI[0] = SOF */ +#define USIC_RBCTR_SIZE_SHIFT (24) /* Bits 24-26: Buffer Size */ #define USIC_RBCTR_SIZE_MASK (7 << USIC_RBCTR_SIZE_SHIFT) -#define USIC_RBCTR_RNM (1 << 27) /* Bit 27: */ -#define USIC_RBCTR_LOF (1 << 28) /* Bit 28: */ -#define USIC_RBCTR_ARBIEN (1 << 29) /* Bit 29: */ -#define USIC_RBCTR_SRBIEN (1 << 30) /* Bit 30: */ -#define USIC_RBCTR_RBERIEN (1 << 31) /* Bit 31: */ +# define USIC_RBCTR_SIZE_DISABLE (0 << USIC_RBCTR_SIZE_SHIFT) /* FIFO mechanism is disabled */ +# define USIC_RBCTR_SIZE_2 (1 << USIC_RBCTR_SIZE_SHIFT) /* FIFO buffer contains 2 entries */ +# define USIC_RBCTR_SIZE_4 (2 << USIC_RBCTR_SIZE_SHIFT) /* FIFO buffer contains 4 entries */ +# define USIC_RBCTR_SIZE_8 (3 << USIC_RBCTR_SIZE_SHIFT) /* FIFO buffer contains 8 entries */ +# define USIC_RBCTR_SIZE_16 (4 << USIC_RBCTR_SIZE_SHIFT) /* FIFO buffer contains 16 entries */ +# define USIC_RBCTR_SIZE_32 (5 << USIC_RBCTR_SIZE_SHIFT) /* FIFO buffer contains 32 entries */ +# define USIC_RBCTR_SIZE_64 (6 << USIC_RBCTR_SIZE_SHIFT) /* FIFO buffer contains 64 entries */ +#define USIC_RBCTR_RNM (1 << 27) /* Bit 27: Receiver Notification Mode */ +#define USIC_RBCTR_LOF (1 << 28) /* Bit 28: Buffer Event on Limit Overflow */ +#define USIC_RBCTR_ARBIEN (1 << 29) /* Bit 29: Alternative Receive Buffer Interrupt Enable */ +#define USIC_RBCTR_SRBIEN (1 << 30) /* Bit 30: Standard Receive Buffer Interrupt Enable */ +#define USIC_RBCTR_RBERIEN (1 << 31) /* Bit 31: Receive Buffer Error Interrupt Enable */ /* Transmit/Receive Buffer Pointer Register */ -#define USIC_TRBPTR_TDIPTR_SHIFT (0) /* Bits 0-5: */ +#define USIC_TRBPTR_TDIPTR_SHIFT (0) /* Bits 0-5: Transmitter Data Input Pointer */ #define USIC_TRBPTR_TDIPTR_MASK (0x3f << USIC_TRBPTR_TDIPTR_SHIFT) -#define USIC_TRBPTR_TDOPTR_SHIFT (8) /* Bits 813xx: */ +#define USIC_TRBPTR_TDOPTR_SHIFT (8) /* Bits 8-13: Transmitter Data Output Pointer */ #define USIC_TRBPTR_TDOPTR_MASK (0x3f << USIC_TRBPTR_TDOPTR_SHIFT) -#define USIC_TRBPTR_RDIPTR_SHIFT (16) /* Bits 16-21: */ +#define USIC_TRBPTR_RDIPTR_SHIFT (16) /* Bits 16-21: Receiver Data Input Pointer */ #define USIC_TRBPTR_RDIPTR_MASK (0x3f << USIC_TRBPTR_RDIPTR_SHIFT) -#define USIC_TRBPTR_RDOPTR_SHIFT (24) /* Bits 24-29: */ +#define USIC_TRBPTR_RDOPTR_SHIFT (24) /* Bits 24-29: Receiver Data Output Pointer */ #define USIC_TRBPTR_RDOPTR_MASK (0x3f << USIC_TRBPTR_RDOPTR_SHIFT) /* Transmit/Receive Buffer Status Register */ @@ -1013,21 +1072,21 @@ /* Receiver Buffer Output Register */ -#define USIC_OUTR_DSR_SHIFT (0) /* Bits 0-15: */ +#define USIC_OUTR_DSR_SHIFT (0) /* Bits 0-15: Received Data */ #define USIC_OUTR_DSR_MASK (0xffff << USIC_OUTR_DSR_SHIFT) -#define USIC_OUTR_RCI_SHIFT (16) /* Bits 16-20: */ +#define USIC_OUTR_RCI_SHIFT (16) /* Bits 16-20: Receiver Control Information */ #define USIC_OUTR_RCI_MASK (31 << USIC_OUTR_RCI_SHIFT) /* Receiver Buffer Output Register L for Debugger */ -#define USIC_OUTDR_DSR_SHIFT (0) /* Bits 0-15: */ +#define USIC_OUTDR_DSR_SHIFT (0) /* Bits 0-15: Data from Shift Register */ #define USIC_OUTDR_DSR_MASK (0xffff << USIC_OUTDR_DSR_SHIFT) -#define USIC_OUTDR_RCI_SHIFT (16) /* Bits 16-30: */ +#define USIC_OUTDR_RCI_SHIFT (16) /* Bits 16-30: Receive Control Information from Shift Register */ #define USIC_OUTDR_RCI_MASK (31 << USIC_OUTDR_RCI_SHIFT) /* Transmit FIFO Buffer (32 x 4-bytes) */ -#define USIC_IN_TDATA_SHIFT (0) /* Bits 0-15: */ +#define USIC_IN_TDATA_SHIFT (0) /* Bits 0-15: Transmit Data */ #define USIC_IN_TDATA_MASK (0xffff << USIC_IN_TDATA_SHIFT) #endif /* __ARCH_ARM_SRC_XMC4_CHIP_XMC4_USIC_H */ From a9aa11f968d86db50ebd9f9ec6e37777f32f28ac Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 19 Mar 2017 10:03:31 -0600 Subject: [PATCH 43/81] XMC4xxx: A few compilation issues; still a long way to go. --- arch/arm/src/xmc4/chip/xmc4_pinmux.h | 4 ++-- arch/arm/src/xmc4/chip/xmc4_scu.h | 2 +- arch/arm/src/xmc4/chip/xmc4_usic.h | 14 +++++++------- arch/arm/src/xmc4/xmc4_lowputc.c | 2 +- arch/arm/src/xmc4/xmc4_serial.c | 3 ++- arch/arm/src/xmc4/xmc4_start.c | 1 + 6 files changed, 14 insertions(+), 12 deletions(-) diff --git a/arch/arm/src/xmc4/chip/xmc4_pinmux.h b/arch/arm/src/xmc4/chip/xmc4_pinmux.h index b4ba4b0e24e..daece1f509b 100644 --- a/arch/arm/src/xmc4/chip/xmc4_pinmux.h +++ b/arch/arm/src/xmc4/chip/xmc4_pinmux.h @@ -748,8 +748,8 @@ #define GPIO_U2C1_HWIN3 (GPIO_INPUT | GPIO_PINCTRL_HW0 | GPIO_PORT4 | GPIO_PIN4) #define GPIO_U2C1_MCLKOUT (GPIO_OUTPUT_ALT1 | GPIO_PORT3 | GPIO_PIN4) #define GPIO_U2C1_SCLKOUT_1 (GPIO_OUTPUT_ALT1 | GPIO_PORT3 | GPIO_PIN13) -#define GPIO_U2C1_SCLKOUT_1 (GPIO_OUTPUT_ALT1 | GPIO_PORT3 | GPIO_PIN6) -#define GPIO_U2C1_SCLKOUT_1 (GPIO_OUTPUT_ALT4 | GPIO_PORT4 | GPIO_PIN2) +#define GPIO_U2C1_SCLKOUT_2 (GPIO_OUTPUT_ALT1 | GPIO_PORT3 | GPIO_PIN6) +#define GPIO_U2C1_SCLKOUT_3 (GPIO_OUTPUT_ALT4 | GPIO_PORT4 | GPIO_PIN2) #define GPIO_U2C1_SELO0_1 (GPIO_OUTPUT_ALT1 | GPIO_PORT3 | GPIO_PIN0) #define GPIO_U2C1_SELO0_2 (GPIO_OUTPUT_ALT1 | GPIO_PORT4 | GPIO_PIN1) #define GPIO_U2C1_SELO1 (GPIO_OUTPUT_ALT1 | GPIO_PORT4 | GPIO_PIN2) diff --git a/arch/arm/src/xmc4/chip/xmc4_scu.h b/arch/arm/src/xmc4/chip/xmc4_scu.h index 0618e7e02b0..49b74a3e487 100644 --- a/arch/arm/src/xmc4/chip/xmc4_scu.h +++ b/arch/arm/src/xmc4/chip/xmc4_scu.h @@ -990,7 +990,7 @@ #define SCU_CGATSTAT2_DMA1 (1 << 5) /* Bit 5: DMA1 Gating Status */ #define SCU_CGATSTAT2_FCE (1 << 6) /* Bit 6: FCE Gating Status */ #define SCU_CGATSTAT2_USB (1 << 7) /* Bit 7: USB Gating Status */ -#define SCU_CGATSTAT2_USB (1 << 10) /* Bit 10: ECAT Gating Status */ +#define SCU_CGATSTAT2_ECAT (1 << 10) /* Bit 10: ECAT Gating Status */ /* Peripheral 3 Clock Gating Status, Peripheral 3 Clock Gating Set, Peripheral 3 Clock Gating Clear */ diff --git a/arch/arm/src/xmc4/chip/xmc4_usic.h b/arch/arm/src/xmc4/chip/xmc4_usic.h index 0b49ebfff42..12d4bda2bcf 100644 --- a/arch/arm/src/xmc4/chip/xmc4_usic.h +++ b/arch/arm/src/xmc4/chip/xmc4_usic.h @@ -433,9 +433,9 @@ # define USIC_FDR_STEP(n) ((uint32_t)(n) << USIC_FDR_STEP_SHIFT) #define USIC_FDR_DM_SHIFT (14) /* Bits 14-15: Divider Mode */ #define USIC_FDR_DM_MASK (3 << USIC_FDR_DM_SHIFT) -# define USIC_FDR_DM_ OFF (0 << USIC_FDR_DM_SHIFT) /* Divider switched off */ -# define USIC_FDR_DM_ NORMAL (1 << USIC_FDR_DM_SHIFT) /* Normal divider mode selected */ -# define USIC_FDR_DM_ FRACTIONAL (2 << USIC_FDR_DM_SHIFT) /* Fractional divider mode selected */ +# define USIC_FDR_DM_OFF (0 << USIC_FDR_DM_SHIFT) /* Divider switched off */ +# define USIC_FDR_DM_NORMAL (1 << USIC_FDR_DM_SHIFT) /* Normal divider mode selected */ +# define USIC_FDR_DM_FRACTIONAL (2 << USIC_FDR_DM_SHIFT) /* Fractional divider mode selected */ #define USIC_FDR_RESULT_SHIFT (16) /* Bits 16-25: Result Value */ #define USIC_FDR_RESULT_MASK (0x3ff << USIC_FDR_RESULT_SHIFT) @@ -550,7 +550,7 @@ #define USIC_SCTR_HPCDIR (1 << 4) /* Bit 4: Port Control Direction */ #define USIC_SCTR_DOCFG_SHIFT (6) /* Bits 6-7: Data Output Configuration */ #define USIC_SCTR_DOCFG_MASK (3 << USIC_SCTR_DOCFG_SHIFT) - #define USIC_SCTR_DOCFG_SHIFT (0 << USIC_SCTR_DOCFG_SHIFT) /* DOUTx = shift data value */ + #define USIC_SCTR_DOCFG_NORMAL (0 << USIC_SCTR_DOCFG_SHIFT) /* DOUTx = shift data value */ #define USIC_SCTR_DOCFG_INVERT (1 << USIC_SCTR_DOCFG_SHIFT) /* DOUTx = inverted shift data value */ #define USIC_SCTR_TRM_SHIFT (8) /* Bits 8-9: Transmission Mode */ #define USIC_SCTR_TRM_MASK (3 << USIC_SCTR_TRM_SHIFT) @@ -717,9 +717,9 @@ # define USIC_CCR_HPCEN_DX0_2 (3 << USIC_CCR_HPCEN_SHIFT) /* Port control enabled for DX0, DX[5:3] and DOUT[3:0] */ #define USIC_CCR_PM_SHIFT (8) /* Bits 8-9: Parity Mode */ #define USIC_CCR_PM_MASK (3 << USIC_CCR_PM_SHIFT) -# define USIC_CCR_PM_ DISABLE (0 << USIC_CCR_PM_SHIFT) /* Parity generation is disabled */ -# define USIC_CCR_PM_ EVEN (2 << USIC_CCR_PM_SHIFT) /* Even parity is selected */ -# define USIC_CCR_PM_ ODD (3 << USIC_CCR_PM_SHIFT) /* Odd parity is selected */ +# define USIC_CCR_PM_DISABLE (0 << USIC_CCR_PM_SHIFT) /* Parity generation is disabled */ +# define USIC_CCR_PM_EVEN (2 << USIC_CCR_PM_SHIFT) /* Even parity is selected */ +# define USIC_CCR_PM_ODD (3 << USIC_CCR_PM_SHIFT) /* Odd parity is selected */ #define USIC_CCR_RSIEN (1 << 10) /* Bit 10: Receiver Start Interrupt Enable */ #define USIC_CCR_DLIEN (1 << 11) /* Bit 11: Data Lost Interrupt Enable */ #define USIC_CCR_TSIEN (1 << 12) /* Bit 12: Transmit Shift Interrupt Enable */ diff --git a/arch/arm/src/xmc4/xmc4_lowputc.c b/arch/arm/src/xmc4/xmc4_lowputc.c index ec44caba54a..28ae38195bb 100644 --- a/arch/arm/src/xmc4/xmc4_lowputc.c +++ b/arch/arm/src/xmc4/xmc4_lowputc.c @@ -50,6 +50,7 @@ #include "xmc4_config.h" #include "chip/xmc4_usic.h" #include "chip/xmc4_pinmux.h" +#include "xmc4_lowputc.h" /**************************************************************************** * Pre-processor Definitions @@ -232,4 +233,3 @@ void xmc4_uart_configure(uintptr_t uart_base, uint32_t baud, #warning Missing logic } #endif - diff --git a/arch/arm/src/xmc4/xmc4_serial.c b/arch/arm/src/xmc4/xmc4_serial.c index 509cca56156..4992ddaeb8e 100644 --- a/arch/arm/src/xmc4/xmc4_serial.c +++ b/arch/arm/src/xmc4/xmc4_serial.c @@ -57,9 +57,10 @@ #include "up_arch.h" #include "up_internal.h" -#include "xmc4_config.h" #include "chip.h" +#include "xmc4_config.h" #include "chip/xmc4_usic.h" +#include "xmc4_lowputc.h" /**************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/xmc4/xmc4_start.c b/arch/arm/src/xmc4/xmc4_start.c index 7bf76f1faef..aade30978f1 100644 --- a/arch/arm/src/xmc4/xmc4_start.c +++ b/arch/arm/src/xmc4/xmc4_start.c @@ -52,6 +52,7 @@ #include "chip/xmc4_flash.h" #include "xmc4_userspace.h" +#include "xmc4_lowputc.h" #include "xmc4_start.h" #ifdef CONFIG_ARCH_FPU From 59b9ef8fdcc94e5f376cd8544512eb226baca0bc Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 19 Mar 2017 11:10:31 -0600 Subject: [PATCH 44/81] XMC4xxx: Revise configuration for USICs. Three USICs but 4 UARTs possible with each channel of USIC. --- arch/arm/src/xmc4/Kconfig | 233 +++++++++++++++------------- arch/arm/src/xmc4/xmc4_config.h | 57 ++++--- arch/arm/src/xmc4/xmc4_lowputc.c | 14 +- arch/arm/src/xmc4/xmc4_lowputc.h | 90 +++++++++++ arch/arm/src/xmc4/xmc4_serial.c | 76 ++++----- arch/arm/src/xmc4/xmc4_usic.h | 109 +++++++++++++ configs/xmc4500-relax/nsh/defconfig | 21 ++- 7 files changed, 417 insertions(+), 183 deletions(-) create mode 100644 arch/arm/src/xmc4/xmc4_lowputc.h create mode 100644 arch/arm/src/xmc4/xmc4_usic.h diff --git a/arch/arm/src/xmc4/Kconfig b/arch/arm/src/xmc4/Kconfig index 096a65fb858..c73e281fb50 100644 --- a/arch/arm/src/xmc4/Kconfig +++ b/arch/arm/src/xmc4/Kconfig @@ -66,263 +66,272 @@ config XMC4_USIC1 Support USIC1 config XMC4_USIC2 - bool "USIC3" + bool "USIC2" default n select XMC4_USIC ---help--- Support USIC2 -config XMC4_USIC3 - bool "USIC3" - default n - select XMC4_USIC - ---help--- - Support USIC3 - -config XMC4_USIC4 - bool "USIC4" - default n - select XMC4_USIC - ---help--- - Support USIC4 - -config XMC4_USIC5 - bool "USIC5" - default n - select XMC4_USIC - ---help--- - Support USIC5 - endmenu menu "XMC4xxx USIC Configuration" depends on XMC4_USIC choice - prompt "USIC0 Configuration" - default XMC4_USIC0_ISUART + prompt "USIC0 Channel 0 Configuration" + default XMC4_USIC0_CHAN0_ISUART depends on XMC4_USIC0 -config XMC4_USIC0_ISUART - bool "UART" +config XMC4_USIC0_CHAN0_NONE + bool "Not used" + ---help--- + USIC0 Channel 0 will not be enabled + +config XMC4_USIC0_CHAN0_ISUART + bool "UART0" select UART0_SERIALDRIVER select XMC4_USCI_UART ---help--- - Configure USIC0 as a UART + Configure USIC0 Channel 0 as a UART -config XMC4_USIC0_ISLIN +config XMC4_USIC0_CHAN0_ISLIN bool "LIN" select XMC4_USCI_LIN ---help--- - Configure USIC0 as a LIN UART + Configure USIC0 Channel 0 as a LIN UART -config XMC4_USIC0_ISSPI +config XMC4_USIC0_CHAN0_ISSPI bool "SPI" select XMC4_USCI_SPI ---help--- - Configure USIC0 For SPI communications + Configure USIC0 Channel 0 for SPI communications -config XMC4_USIC0_ISI2C +config XMC4_USIC0_CHAN0_ISI2C bool "I2C" select XMC4_USCI_I2C ---help--- - Configure USIC0 For I2C communications + Configure USIC0 Channel 0 for I2C communications -config XMC4_USIC0_ISI2S +config XMC4_USIC0_CHAN0_ISI2S bool "I2S" select XMC4_USCI_I2S ---help--- - Configure USIC0 For I2S audio + Configure USIC0 Channel 0 for I2S audio -endchoice # USIC0 Configuration +endchoice # USIC0 Channel 0 Configuration choice - prompt "USIC1 Configuration" - default XMC4_USIC1_ISUART - depends on XMC4_USIC1 + prompt "USIC0 Channel 1 Configuration" + default XMC4_USIC0_CHAN1_ISUART + depends on XMC4_USIC0 -config XMC4_USIC1_ISUART - bool "UART" +config XMC4_USIC0_CHAN1_NONE + bool "Not used" + ---help--- + USIC0 Channel 1 will not be enabled + +config XMC4_USIC0_CHAN1_ISUART + bool "UART1" select UART1_SERIALDRIVER select XMC4_USCI_UART ---help--- - Configure USIC1 as a UART + Configure USIC0 Channel 1 as a UART -config XMC4_USIC1_ISLIN +config XMC4_USIC0_CHAN1_ISLIN bool "LIN" select XMC4_USCI_LIN ---help--- - Configure USIC1 as a LIN UART + Configure USIC0 Channel 1 as a LIN UART -config XMC4_USIC1_ISSPI +config XMC4_USIC0_CHAN1_ISSPI bool "SPI" select XMC4_USCI_SPI ---help--- - Configure USIC1 For SPI communications + Configure USIC0 Channel 1 for SPI communications -config XMC4_USIC1_ISI2C +config XMC4_USIC0_CHAN1_ISI2C bool "I2C" select XMC4_USCI_I2C ---help--- - Configure USIC1 For I2C communications + Configure USIC0 Channel 1 for I2C communications -config XMC4_USIC1_ISI2S +config XMC4_USIC0_CHAN1_ISI2S bool "I2S" select XMC4_USCI_I2S ---help--- - Configure USIC1 For I2S audio + Configure USIC0 Channel 1 for I2S audio -endchoice # USIC1 Configuration +endchoice # USIC0 Channel 1 Configuration choice - prompt "USIC2 Configuration" - default XMC4_USIC2_ISUART - depends on XMC4_USIC2 + prompt "USIC1 Channel 0 Configuration" + default XMC4_USIC1_CHAN0_ISUART + depends on XMC4_USIC1 -config XMC4_USIC2_ISUART - bool "UART" +config XMC4_USIC1_CHAN0_NONE + bool "Not used" + ---help--- + USIC0 Channel 0 will not be enabled + +config XMC4_USIC1_CHAN0_ISUART + bool "UART2" select UART2_SERIALDRIVER select XMC4_USCI_UART ---help--- - Configure USIC2 as a UART + Configure USIC1 Channel 0 as a UART -config XMC4_USIC2_ISLIN +config XMC4_USIC1_CHAN0_ISLIN bool "LIN" select XMC4_USCI_LIN ---help--- - Configure USIC2 as a LIN UART + Configure USIC1 Channel 0 as a LIN UART -config XMC4_USIC2_ISSPI +config XMC4_USIC1_CHAN0_ISSPI bool "SPI" select XMC4_USCI_SPI ---help--- - Configure USIC2 For SPI communications + Configure USIC1 Channel 0 for SPI communications -config XMC4_USIC2_ISI2C +config XMC4_USIC1_CHAN0_ISI2C bool "I2C" select XMC4_USCI_I2C ---help--- - Configure USIC2 For I2C communications + Configure USIC1 Channel 0 for I2C communications -config XMC4_USIC2_ISI2S +config XMC4_USIC1_CHAN0_ISI2S bool "I2S" select XMC4_USCI_I2S ---help--- - Configure USIC2 For I2S audio + Configure USIC1 Channel 0 for I2S audio -endchoice # USIC2 Configuration +endchoice # USIC1 Channel 0 Configuration choice - prompt "USIC3 Configuration" - default XMC4_USIC3_ISUART - depends on XMC4_USIC3 + prompt "USIC1 Channel 1 Configuration" + default XMC4_USIC1_CHAN1_ISUART + depends on XMC4_USIC1 -config XMC4_USIC3_ISUART - bool "UART" +config XMC4_USIC1_CHAN1_NONE + bool "Not used" + ---help--- + USIC0 Channel 1 will not be enabled + +config XMC4_USIC1_CHAN1_ISUART + bool "UART3" select UART3_SERIALDRIVER select XMC4_USCI_UART ---help--- - Configure USIC3 as a UART + Configure USIC1 Channel 1 as a UART -config XMC4_USIC3_ISLIN +config XMC4_USIC1_CHAN1_ISLIN bool "LIN" select XMC4_USCI_LIN ---help--- - Configure USIC3 as a LIN UART + Configure USIC1 Channel 1 as a LIN UART -config XMC4_USIC3_ISSPI +config XMC4_USIC1_CHAN1_ISSPI bool "SPI" select XMC4_USCI_SPI ---help--- - Configure USIC3 For SPI communications + Configure USIC1 Channel 1 for SPI communications -config XMC4_USIC3_ISI2C +config XMC4_USIC1_CHAN1_ISI2C bool "I2C" select XMC4_USCI_I2C ---help--- - Configure USIC3 For I2C communications + Configure USIC1 Channel 1 for I2C communications -config XMC4_USIC3_ISI2S +config XMC4_USIC1_CHAN1_ISI2S bool "I2S" select XMC4_USCI_I2S ---help--- - Configure USIC3 For I2S audio + Configure USIC1 Channel 1 for I2S audio -endchoice # USIC3 Configuration +endchoice # USIC1 Channel 1 Configuration choice - prompt "USIC4 Configuration" - default XMC4_USIC4_ISUART - depends on XMC4_USIC4 + prompt "USIC2 Channel 0 Configuration" + default XMC4_USIC2_CHAN0_ISUART + depends on XMC4_USIC2 -config XMC4_USIC4_ISUART - bool "UART" +config XMC4_USIC2_CHAN0_NONE + bool "Not used" + ---help--- + USIC0 Channel 0 will not be enabled + +config XMC4_USIC2_CHAN0_ISUART + bool "UART4" select UART4_SERIALDRIVER select XMC4_USCI_UART ---help--- - Configure USIC4 as a UART + Configure USIC2 Channel 0 as a UART -config XMC4_USIC4_ISLIN +config XMC4_USIC2_CHAN0_ISLIN bool "LIN" select XMC4_USCI_LIN ---help--- - Configure USIC4 as a LIN UART + Configure USIC2 Channel 0 as a LIN UART -config XMC4_USIC4_ISSPI +config XMC4_USIC2_CHAN0_ISSPI bool "SPI" select XMC4_USCI_SPI ---help--- - Configure USIC4 For SPI communications + Configure USIC2 Channel 0 for SPI communications -config XMC4_USIC4_ISI2C +config XMC4_USIC2_CHAN0_ISI2C bool "I2C" select XMC4_USCI_I2C ---help--- - Configure USIC4 For I2C communications + Configure USIC2 Channel 0 for I2C communications -config XMC4_USIC4_ISI2S +config XMC4_USIC2_CHAN0_ISI2S bool "I2S" select XMC4_USCI_I2S ---help--- - Configure USIC4 For I2S audio + Configure USIC2 Channel 0 for I2S audio -endchoice # USIC4 Configuration +endchoice # USIC2 Channel 0 Configuration choice - prompt "USIC5 Configuration" - default XMC4_USIC5_ISUART - depends on XMC4_USIC5 + prompt "USIC2 Channel 1 Configuration" + default XMC4_USIC2_CHAN1_ISUART + depends on XMC4_USIC2 -config XMC4_USIC5_ISUART - bool "UART" - select UART0_SERIALDRIVER +config XMC4_USIC2_CHAN1_NONE + bool "Not used" + ---help--- + USIC0 Channel 1 will not be enabled + +config XMC4_USIC2_CHAN1_ISUART + bool "UART5" + select UART5_SERIALDRIVER select XMC4_USCI_UART ---help--- - Configure USIC5 as a UART + Configure USIC2 Channel 1 as a UART -config XMC4_USIC5_ISLIN +config XMC4_USIC2_CHAN1_ISLIN bool "LIN" select XMC4_USCI_LIN ---help--- - Configure USIC5 as a LIN UART + Configure USIC2 Channel 1 as a LIN UART -config XMC4_USIC5_ISSPI +config XMC4_USIC2_CHAN1_ISSPI bool "SPI" select XMC4_USCI_SPI ---help--- - Configure USIC5 For SPI communications + Configure USIC2 Channel 1 for SPI communications -config XMC4_USIC5_ISI2C +config XMC4_USIC2_CHAN1_ISI2C bool "I2C" select XMC4_USCI_I2C ---help--- - Configure USIC5 For I2C communications + Configure USIC2 Channel 1 for I2C communications -config XMC4_USIC5_ISI2S +config XMC4_USIC2_CHAN1_ISI2S bool "I2S" select XMC4_USCI_I2S ---help--- - Configure USIC5 For I2S audio + Configure USIC2 Channel 1 for I2S audio -endchoice # USIC5 Configuration +endchoice # USIC2 Channel 1 Configuration endmenu # XMC4xxx USIC Configuration diff --git a/arch/arm/src/xmc4/xmc4_config.h b/arch/arm/src/xmc4/xmc4_config.h index e81932569ec..0a9c204268d 100644 --- a/arch/arm/src/xmc4/xmc4_config.h +++ b/arch/arm/src/xmc4/xmc4_config.h @@ -53,30 +53,51 @@ /* Make sure that no unsupported UARTs are enabled */ #ifndef CONFIG_XMC4_USIC0 -# undef CONFIG_XMC4_USIC0_ISUART +# undef CONFIG_XMC4_USIC0_CHAN0_ISUART +# undef CONFIG_XMC4_USIC0_CHAN1_ISUART #endif #ifndef CONFIG_XMC4_USIC1 -# undef CONFIG_XMC4_USIC1_ISUART +# undef CONFIG_XMC4_USIC1_CHAN0_ISUART +# undef CONFIG_XMC4_USIC1_CHAN1_ISUART #endif #ifndef CONFIG_XMC4_USIC2 -# undef CONFIG_XMC4_USIC2_ISUART +# undef CONFIG_XMC4_USIC2_CHAN0_ISUART +# undef CONFIG_XMC4_USIC2_CHAN1_ISUART #endif -#ifndef CONFIG_XMC4_USIC3 -# undef CONFIG_XMC4_USIC3_ISUART + +/* Map logical UART names (Just for simplicity of naming) */ + +#undef HAVE_UART0 +#undef HAVE_UART1 +#undef HAVE_UART2 +#undef HAVE_UART3 +#undef HAVE_UART4 +#undef HAVE_UART5 + +#ifdef CONFIG_XMC4_USIC0_CHAN0_ISUART +# define HAVE_UART0 #endif -#ifndef CONFIG_XMC4_USIC4 -# undef CONFIG_XMC4_USIC4_ISUART +#ifdef CONFIG_XMC4_USIC0_CHAN1_ISUART +# define HAVE_UART1 #endif -#ifndef CONFIG_XMC4_USIC5 -# undef CONFIG_XMC4_USIC5_ISUART +#ifdef CONFIG_XMC4_USIC1_CHAN0_ISUART +# define HAVE_UART2 +#endif +#ifdef CONFIG_XMC4_USIC1_CHAN1_ISUART +# define HAVE_UART3 +#endif +#ifdef CONFIG_XMC4_USIC2_CHAN0_ISUART +# define HAVE_UART4 +#endif +#ifdef CONFIG_XMC4_USIC2_CHAN1_ISUART +# define HAVE_UART5 #endif /* Are any UARTs enabled? */ #undef HAVE_UART_DEVICE -#if defined(CONFIG_XMC4_USIC0_ISUART) || defined(CONFIG_XMC4_USIC1_ISUART) || \ - defined(CONFIG_XMC4_USIC2_ISUART) || defined(CONFIG_XMC4_USIC3_ISUART) || \ - defined(CONFIG_XMC4_USIC3_ISUART) || defined(CONFIG_XMC4_USIC4_ISUART) +#if defined(HAVE_UART0) || defined(HAVE_UART1) || defined(HAVE_UART2) || \ + defined(HAVE_UART3) || defined(HAVE_UART4) || defined(HAVE_UART5) # define HAVE_UART_DEVICE 1 #endif @@ -94,42 +115,42 @@ # undef CONFIG_UART4_SERIAL_CONSOLE # undef CONFIG_UART5_SERIAL_CONSOLE #else -# if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_XMC4_USIC0_ISUART) +# if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(HAVE_UART0) # undef CONFIG_UART1_SERIAL_CONSOLE # undef CONFIG_UART2_SERIAL_CONSOLE # undef CONFIG_UART3_SERIAL_CONSOLE # undef CONFIG_UART4_SERIAL_CONSOLE # undef CONFIG_UART5_SERIAL_CONSOLE # define HAVE_UART_CONSOLE 1 -# elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_XMC4_USIC1_ISUART) +# elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(HAVE_UART1) # undef CONFIG_UART0_SERIAL_CONSOLE # undef CONFIG_UART2_SERIAL_CONSOLE # undef CONFIG_UART3_SERIAL_CONSOLE # undef CONFIG_UART4_SERIAL_CONSOLE # undef CONFIG_UART5_SERIAL_CONSOLE # define HAVE_UART_CONSOLE 1 -# elif defined(CONFIG_UART2_SERIAL_CONSOLE) && defined(CONFIG_XMC4_USIC2_ISUART) +# elif defined(CONFIG_UART2_SERIAL_CONSOLE) && defined(HAVE_UART2) # undef CONFIG_UART0_SERIAL_CONSOLE # undef CONFIG_UART1_SERIAL_CONSOLE # undef CONFIG_UART3_SERIAL_CONSOLE # undef CONFIG_UART4_SERIAL_CONSOLE # undef CONFIG_UART5_SERIAL_CONSOLE # define HAVE_UART_CONSOLE 1 -# elif defined(CONFIG_UART3_SERIAL_CONSOLE) && defined(CONFIG_XMC4_USIC3_ISUART) +# elif defined(CONFIG_UART3_SERIAL_CONSOLE) && defined(HAVE_UART3) # undef CONFIG_UART0_SERIAL_CONSOLE # undef CONFIG_UART1_SERIAL_CONSOLE # undef CONFIG_UART2_SERIAL_CONSOLE # undef CONFIG_UART4_SERIAL_CONSOLE # undef CONFIG_UART5_SERIAL_CONSOLE # define HAVE_UART_CONSOLE 1 -# elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_XMC4_USIC4_ISUART) +# elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(HAVE_UART4) # undef CONFIG_UART0_SERIAL_CONSOLE # undef CONFIG_UART1_SERIAL_CONSOLE # undef CONFIG_UART2_SERIAL_CONSOLE # undef CONFIG_UART3_SERIAL_CONSOLE # undef CONFIG_UART5_SERIAL_CONSOLE # define HAVE_UART_CONSOLE 1 -# elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_XMC4_USIC5_ISUART) +# elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(HAVE_UART5) # undef CONFIG_UART0_SERIAL_CONSOLE # undef CONFIG_UART1_SERIAL_CONSOLE # undef CONFIG_UART2_SERIAL_CONSOLE diff --git a/arch/arm/src/xmc4/xmc4_lowputc.c b/arch/arm/src/xmc4/xmc4_lowputc.c index 28ae38195bb..6df364565ca 100644 --- a/arch/arm/src/xmc4/xmc4_lowputc.c +++ b/arch/arm/src/xmc4/xmc4_lowputc.c @@ -60,42 +60,42 @@ #if defined(HAVE_UART_CONSOLE) # if defined(CONFIG_UART0_SERIAL_CONSOLE) -# define CONSOLE_BASE XMC4_UART0_BASE +# define CONSOLE_BASE XMC4_USIC0_CH0_BASE # define CONSOLE_FREQ BOARD_CORECLK_FREQ # define CONSOLE_BAUD CONFIG_UART0_BAUD # define CONSOLE_BITS CONFIG_UART0_BITS # define CONSOLE_2STOP CONFIG_UART0_2STOP # define CONSOLE_PARITY CONFIG_UART0_PARITY # elif defined(CONFIG_UART1_SERIAL_CONSOLE) -# define CONSOLE_BASE XMC4_UART1_BASE +# define CONSOLE_BASE XMC4_USIC0_CH1_BASE # define CONSOLE_FREQ BOARD_CORECLK_FREQ # define CONSOLE_BAUD CONFIG_UART1_BAUD # define CONSOLE_BITS CONFIG_UART1_BITS # define CONSOLE_2STOP CONFIG_UART1_2STOP # define CONSOLE_PARITY CONFIG_UART1_PARITY # elif defined(CONFIG_UART2_SERIAL_CONSOLE) -# define CONSOLE_BASE XMC4_UART2_BASE +# define CONSOLE_BASE XMC4_USIC1_CH0_BASE # define CONSOLE_FREQ BOARD_BUS_FREQ # define CONSOLE_BAUD CONFIG_UART2_BAUD # define CONSOLE_BITS CONFIG_UART2_BITS # define CONSOLE_2STOP CONFIG_UART2_2STOP # define CONSOLE_PARITY CONFIG_UART2_PARITY # elif defined(CONFIG_UART3_SERIAL_CONSOLE) -# define CONSOLE_BASE XMC4_UART3_BASE +# define CONSOLE_BASE XMC4_USIC1_CH1_BASE # define CONSOLE_FREQ BOARD_BUS_FREQ # define CONSOLE_BAUD CONFIG_UART3_BAUD # define CONSOLE_BITS CONFIG_UART3_BITS # define CONSOLE_2STOP CONFIG_UART3_2STOP # define CONSOLE_PARITY CONFIG_UART3_PARITY # elif defined(CONFIG_UART4_SERIAL_CONSOLE) -# define CONSOLE_BASE XMC4_UART4_BASE +# define CONSOLE_BASE XMC4_USIC2_CH0_BASE # define CONSOLE_FREQ BOARD_BUS_FREQ # define CONSOLE_BAUD CONFIG_UART4_BAUD # define CONSOLE_BITS CONFIG_UART4_BITS # define CONSOLE_2STOP CONFIG_UART4_2STOP # define CONSOLE_PARITY CONFIG_UART4_PARITY # elif defined(CONFIG_UART5_SERIAL_CONSOLE) -# define CONSOLE_BASE XMC4_UART5_BASE +# define CONSOLE_BASE XMC4_USIC2_CH1_BASE # define CONSOLE_FREQ BOARD_BUS_FREQ # define CONSOLE_BAUD CONFIG_UART5_BAUD # define CONSOLE_BITS CONFIG_UART5_BITS @@ -161,7 +161,7 @@ void xmc4_lowsetup(void) uint32_t regval; /* Enable peripheral clocking for all enabled UARTs. */ -#wanring Missing logic +#warning Missing logic /* Configure UART pins for the all enabled UARTs */ diff --git a/arch/arm/src/xmc4/xmc4_lowputc.h b/arch/arm/src/xmc4/xmc4_lowputc.h new file mode 100644 index 00000000000..7287855a7be --- /dev/null +++ b/arch/arm/src/xmc4/xmc4_lowputc.h @@ -0,0 +1,90 @@ +/**************************************************************************** + * arch/arm/src/xmc4/xmc4_lowputc.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_XMC4_XMC4_LOWPUTC_H +#define __ARCH_ARM_SRC_XMC4_XMC4_LOWPUTC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include "xmc4_config.h" + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: xmc4_lowsetup + * + * Description: + * This performs basic initialization of the UART used for the serial + * console. Its purpose is to get the console output available as soon + * as possible. + * + ****************************************************************************/ + +void xmc4_lowsetup(void); + +/**************************************************************************** + * Name: xmc4_uart_reset + * + * Description: + * Reset a UART. + * + ****************************************************************************/ + +#ifdef HAVE_UART_DEVICE +void xmc4_uart_reset(uintptr_t uart_base); +#endif + +/**************************************************************************** + * Name: xmc4_uart_configure + * + * Description: + * Configure a UART as a RS-232 UART. + * + ****************************************************************************/ + +#ifdef HAVE_UART_DEVICE +void xmc4_uart_configure(uintptr_t uart_base, uint32_t baud, + uint32_t clock, unsigned int parity, + unsigned int nbits, unsigned int stop2); +#endif + + +#endif /* __ARCH_ARM_SRC_XMC4_XMC4_LOWPUTC_H */ diff --git a/arch/arm/src/xmc4/xmc4_serial.c b/arch/arm/src/xmc4/xmc4_serial.c index 4992ddaeb8e..e09a23ef55f 100644 --- a/arch/arm/src/xmc4/xmc4_serial.c +++ b/arch/arm/src/xmc4/xmc4_serial.c @@ -110,22 +110,22 @@ # define UART5_ASSIGNED 1 #else # undef CONSOLE_DEV /* No console */ -# if defined(CONFIG_XMC4_USIC0_ISUART) +# if defined(HAVE_UART0) # define TTYS0_DEV g_uart0port /* UART0 is ttyS0 */ # define UART0_ASSIGNED 1 -# elif defined(CONFIG_XMC4_USIC1_ISUART) +# elif defined(HAVE_UART1) # define TTYS0_DEV g_uart1port /* UART1 is ttyS0 */ # define UART1_ASSIGNED 1 -# elif defined(CONFIG_XMC4_USIC2_ISUART) +# elif defined(HAVE_UART2) # define TTYS0_DEV g_uart2port /* UART2 is ttyS0 */ # define UART2_ASSIGNED 1 -# elif defined(CONFIG_XMC4_USIC3_ISUART) +# elif defined(HAVE_UART3) # define TTYS0_DEV g_uart3port /* UART3 is ttyS0 */ # define UART3_ASSIGNED 1 -# elif defined(CONFIG_XMC4_USIC4_ISUART) +# elif defined(HAVE_UART4) # define TTYS0_DEV g_uart4port /* UART4 is ttyS0 */ # define UART4_ASSIGNED 1 -# elif defined(CONFIG_XMC4_USIC5_ISUART) +# elif defined(HAVE_UART5) # define TTYS0_DEV g_uart5port /* UART5 is ttyS0 */ # define UART5_ASSIGNED 1 # endif @@ -133,22 +133,22 @@ /* Pick ttys1. This could be any of UART0-5 excluding the console UART. */ -#if defined(CONFIG_XMC4_USIC0_ISUART) && !defined(UART0_ASSIGNED) +#if defined(HAVE_UART0) && !defined(UART0_ASSIGNED) # define TTYS1_DEV g_uart0port /* UART0 is ttyS1 */ # define UART0_ASSIGNED 1 -#elif defined(CONFIG_XMC4_USIC1_ISUART) && !defined(UART1_ASSIGNED) +#elif defined(HAVE_UART1) && !defined(UART1_ASSIGNED) # define TTYS1_DEV g_uart1port /* UART1 is ttyS1 */ # define UART1_ASSIGNED 1 -#elif defined(CONFIG_XMC4_USIC2_ISUART) && !defined(UART2_ASSIGNED) +#elif defined(HAVE_UART2) && !defined(UART2_ASSIGNED) # define TTYS1_DEV g_uart2port /* UART2 is ttyS1 */ # define UART2_ASSIGNED 1 -#elif defined(CONFIG_XMC4_USIC3_ISUART) && !defined(UART3_ASSIGNED) +#elif defined(HAVE_UART3) && !defined(UART3_ASSIGNED) # define TTYS1_DEV g_uart3port /* UART3 is ttyS1 */ # define UART3_ASSIGNED 1 -#elif defined(CONFIG_XMC4_USIC4_ISUART) && !defined(UART4_ASSIGNED) +#elif defined(HAVE_UART4) && !defined(UART4_ASSIGNED) # define TTYS1_DEV g_uart4port /* UART4 is ttyS1 */ # define UART4_ASSIGNED 1 -#elif defined(CONFIG_XMC4_USIC5_ISUART) && !defined(UART5_ASSIGNED) +#elif defined(HAVE_UART5) && !defined(UART5_ASSIGNED) # define TTYS1_DEV g_uart5port /* UART5 is ttyS1 */ # define UART5_ASSIGNED 1 #endif @@ -158,19 +158,19 @@ * console. */ -#if defined(CONFIG_XMC4_USIC1_ISUART) && !defined(UART1_ASSIGNED) +#if defined(HAVE_UART1) && !defined(UART1_ASSIGNED) # define TTYS2_DEV g_uart1port /* UART1 is ttyS2 */ # define UART1_ASSIGNED 1 -#elif defined(CONFIG_XMC4_USIC2_ISUART) && !defined(UART2_ASSIGNED) +#elif defined(HAVE_UART2) && !defined(UART2_ASSIGNED) # define TTYS2_DEV g_uart2port /* UART2 is ttyS2 */ # define UART2_ASSIGNED 1 -#elif defined(CONFIG_XMC4_USIC3_ISUART) && !defined(UART3_ASSIGNED) +#elif defined(HAVE_UART3) && !defined(UART3_ASSIGNED) # define TTYS2_DEV g_uart3port /* UART3 is ttyS2 */ # define UART3_ASSIGNED 1 -#elif defined(CONFIG_XMC4_USIC4_ISUART) && !defined(UART4_ASSIGNED) +#elif defined(HAVE_UART4) && !defined(UART4_ASSIGNED) # define TTYS2_DEV g_uart4port /* UART4 is ttyS2 */ # define UART4_ASSIGNED 1 -#elif defined(CONFIG_XMC4_USIC5_ISUART) && !defined(UART5_ASSIGNED) +#elif defined(HAVE_UART5) && !defined(UART5_ASSIGNED) # define TTYS2_DEV g_uart5port /* UART5 is ttyS2 */ # define UART5_ASSIGNED 1 #endif @@ -180,16 +180,16 @@ * UART 2-5 could also be the console. */ -#if defined(CONFIG_XMC4_USIC2_ISUART) && !defined(UART2_ASSIGNED) +#if defined(HAVE_UART2) && !defined(UART2_ASSIGNED) # define TTYS3_DEV g_uart2port /* UART2 is ttyS3 */ # define UART2_ASSIGNED 1 -#elif defined(CONFIG_XMC4_USIC3_ISUART) && !defined(UART3_ASSIGNED) +#elif defined(HAVE_UART3) && !defined(UART3_ASSIGNED) # define TTYS3_DEV g_uart3port /* UART3 is ttyS3 */ # define UART3_ASSIGNED 1 -#elif defined(CONFIG_XMC4_USIC4_ISUART) && !defined(UART4_ASSIGNED) +#elif defined(HAVE_UART4) && !defined(UART4_ASSIGNED) # define TTYS3_DEV g_uart4port /* UART4 is ttyS3 */ # define UART4_ASSIGNED 1 -#elif defined(CONFIG_XMC4_USIC5_ISUART) && !defined(UART5_ASSIGNED) +#elif defined(HAVE_UART5) && !defined(UART5_ASSIGNED) # define TTYS3_DEV g_uart5port /* UART5 is ttyS3 */ # define UART5_ASSIGNED 1 #endif @@ -199,13 +199,13 @@ * UART 3-5 could also be the console. */ -#if defined(CONFIG_XMC4_USIC3_ISUART) && !defined(UART3_ASSIGNED) +#if defined(HAVE_UART3) && !defined(UART3_ASSIGNED) # define TTYS4_DEV g_uart3port /* UART3 is ttyS4 */ # define UART3_ASSIGNED 1 -#elif defined(CONFIG_XMC4_USIC4_ISUART) && !defined(UART4_ASSIGNED) +#elif defined(HAVE_UART4) && !defined(UART4_ASSIGNED) # define TTYS4_DEV g_uart4port /* UART4 is ttyS4 */ # define UART4_ASSIGNED 1 -#elif defined(CONFIG_XMC4_USIC5_ISUART) && !defined(UART5_ASSIGNED) +#elif defined(HAVE_UART5) && !defined(UART5_ASSIGNED) # define TTYS4_DEV g_uart5port /* UART5 is ttyS4 */ # define UART5_ASSIGNED 1 #endif @@ -215,10 +215,10 @@ * UART 4-5 could also be the console. */ -#if defined(CONFIG_XMC4_USIC4_ISUART) && !defined(UART4_ASSIGNED) +#if defined(HAVE_UART4) && !defined(UART4_ASSIGNED) # define TTYS5_DEV g_uart4port /* UART4 is ttyS5 */ # define UART4_ASSIGNED 1 -#elif defined(CONFIG_XMC4_USIC5_ISUART) && !defined(UART5_ASSIGNED) +#elif defined(HAVE_UART5) && !defined(UART5_ASSIGNED) # define TTYS5_DEV g_uart5port /* UART5 is ttyS5 */ # define UART5_ASSIGNED 1 #endif @@ -282,34 +282,34 @@ static const struct uart_ops_s g_uart_ops = /* I/O buffers */ -#ifdef CONFIG_XMC4_USIC0_ISUART +#ifdef HAVE_UART0 static char g_uart0rxbuffer[CONFIG_UART0_RXBUFSIZE]; static char g_uart0txbuffer[CONFIG_UART0_TXBUFSIZE]; #endif -#ifdef CONFIG_XMC4_USIC1_ISUART +#ifdef HAVE_UART1 static char g_uart1rxbuffer[CONFIG_UART1_RXBUFSIZE]; static char g_uart1txbuffer[CONFIG_UART1_TXBUFSIZE]; #endif -#ifdef CONFIG_XMC4_USIC2_ISUART +#ifdef HAVE_UART2 static char g_uart2rxbuffer[CONFIG_UART2_RXBUFSIZE]; static char g_uart2txbuffer[CONFIG_UART2_TXBUFSIZE]; #endif -#ifdef CONFIG_XMC4_USIC3_ISUART +#ifdef HAVE_UART3 static char g_uart3rxbuffer[CONFIG_UART3_RXBUFSIZE]; static char g_uart3txbuffer[CONFIG_UART3_TXBUFSIZE]; #endif -#ifdef CONFIG_XMC4_USIC4_ISUART +#ifdef HAVE_UART4 static char g_uart4rxbuffer[CONFIG_UART4_RXBUFSIZE]; static char g_uart4txbuffer[CONFIG_UART4_TXBUFSIZE]; #endif -#ifdef CONFIG_XMC4_USIC5_ISUART +#ifdef HAVE_UART5 static char g_uart5rxbuffer[CONFIG_UART5_RXBUFSIZE]; static char g_uart5txbuffer[CONFIG_UART5_TXBUFSIZE]; #endif /* This describes the state of the Kinetis UART0 port. */ -#ifdef CONFIG_XMC4_USIC0_ISUART +#ifdef HAVE_UART0 static struct xmc4_dev_s g_uart0priv = { .uartbase = XMC4_UART0_BASE, @@ -340,7 +340,7 @@ static uart_dev_t g_uart0port = /* This describes the state of the Kinetis UART1 port. */ -#ifdef CONFIG_XMC4_USIC1_ISUART +#ifdef HAVE_UART1 static struct xmc4_dev_s g_uart1priv = { .uartbase = XMC4_UART1_BASE, @@ -371,7 +371,7 @@ static uart_dev_t g_uart1port = /* This describes the state of the Kinetis UART2 port. */ -#ifdef CONFIG_XMC4_USIC2_ISUART +#ifdef HAVE_UART2 static struct xmc4_dev_s g_uart2priv = { .uartbase = XMC4_UART2_BASE, @@ -402,7 +402,7 @@ static uart_dev_t g_uart2port = /* This describes the state of the Kinetis UART3 port. */ -#ifdef CONFIG_XMC4_USIC3_ISUART +#ifdef HAVE_UART3 static struct xmc4_dev_s g_uart3priv = { .uartbase = XMC4_UART3_BASE, @@ -433,7 +433,7 @@ static uart_dev_t g_uart3port = /* This describes the state of the Kinetis UART4 port. */ -#ifdef CONFIG_XMC4_USIC4_ISUART +#ifdef HAVE_UART4 static struct xmc4_dev_s g_uart4priv = { .uartbase = XMC4_UART4_BASE, @@ -464,7 +464,7 @@ static uart_dev_t g_uart4port = /* This describes the state of the Kinetis UART5 port. */ -#ifdef CONFIG_XMC4_USIC5_ISUART +#ifdef HAVE_UART5 static struct xmc4_dev_s g_uart5priv = { .uartbase = XMC4_UART5_BASE, diff --git a/arch/arm/src/xmc4/xmc4_usic.h b/arch/arm/src/xmc4/xmc4_usic.h new file mode 100644 index 00000000000..d589459037b --- /dev/null +++ b/arch/arm/src/xmc4/xmc4_usic.h @@ -0,0 +1,109 @@ +/**************************************************************************** + * arch/arm/src/xmc4/xmc4_usic.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_XMC4_XMC4_USIC_H +#define __ARCH_ARM_SRC_XMC4_XMC4_USIC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include "xmc4_config.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* This enumeration identifies the USIC */ + +enum usic_e +{ + USIC0 = 0, /* USIC0 */ + USIC1 = 1, /* USIC1 */ + USIC2 = 2 /* USIC2 */ +}; + +/* This enumeration identifies USIC channels */ + +enum usic_channel_e +{ + USIC0_CHAN0 = 0, /* USIC0, Channel 0 */ + USIC0_CHAN1 = 1, /* USIC0, Channel 1 */ + USIC1_CHAN0 = 0, /* USIC1, Channel 0 */ + USIC1_CHAN1 = 1, /* USIC1, Channel 1 */ + USIC2_CHAN0 = 0, /* USIC2, Channel 0 */ + USIC2_CHAN1 = 1 /* USIC2, Channel 1 */ +}; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: xmc4_enable_usic + * + * Description: + * Enable the USIC module indicated by the 'usic' enumeration value + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned to + * indicate the nature of any failure. + * + ****************************************************************************/ + +int xmc4_enable_usic(enum usic_e usic); + +/**************************************************************************** + * Name: xmc4_enable_usic_channel + * + * Description: + * Enable the USIC channel indicated by 'channel'. Also enable and reset + * the USIC module if it is not already enabled. + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned to + * indicate the nature of any failure. + * + ****************************************************************************/ + +int xmc4_enable_usic_channel(enum usic_channel_e channel); + +#endif /* __ARCH_ARM_SRC_XMC4_XMC4_USIC_H */ diff --git a/configs/xmc4500-relax/nsh/defconfig b/configs/xmc4500-relax/nsh/defconfig index 54bd16a3928..f938e18bc4f 100644 --- a/configs/xmc4500-relax/nsh/defconfig +++ b/configs/xmc4500-relax/nsh/defconfig @@ -177,18 +177,22 @@ CONFIG_XMC4_USCI_UART=y CONFIG_XMC4_USIC0=y # CONFIG_XMC4_USIC1 is not set # CONFIG_XMC4_USIC2 is not set -# CONFIG_XMC4_USIC3 is not set -# CONFIG_XMC4_USIC4 is not set -# CONFIG_XMC4_USIC5 is not set # # XMC4xxx USIC Configuration # -CONFIG_XMC4_USIC0_ISUART=y -# CONFIG_XMC4_USIC0_ISLIN is not set -# CONFIG_XMC4_USIC0_ISSPI is not set -# CONFIG_XMC4_USIC0_ISI2C is not set -# CONFIG_XMC4_USIC0_ISI2S is not set +# CONFIG_XMC4_USIC0_CHAN0_NONE is not set +CONFIG_XMC4_USIC0_CHAN0_ISUART=y +# CONFIG_XMC4_USIC0_CHAN0_ISLIN is not set +# CONFIG_XMC4_USIC0_CHAN0_ISSPI is not set +# CONFIG_XMC4_USIC0_CHAN0_ISI2C is not set +# CONFIG_XMC4_USIC0_CHAN0_ISI2S is not set +CONFIG_XMC4_USIC0_CHAN1_NONE=y +# CONFIG_XMC4_USIC0_CHAN1_ISUART is not set +# CONFIG_XMC4_USIC0_CHAN1_ISLIN is not set +# CONFIG_XMC4_USIC0_CHAN1_ISSPI is not set +# CONFIG_XMC4_USIC0_CHAN1_ISI2C is not set +# CONFIG_XMC4_USIC0_CHAN1_ISI2S is not set # # Architecture Options @@ -554,6 +558,7 @@ CONFIG_STANDARD_SERIAL=y # CONFIG_SERIAL_DMA is not set # CONFIG_ARCH_HAVE_SERIAL_TERMIOS is not set CONFIG_UART0_SERIAL_CONSOLE=y +# CONFIG_UART1_SERIAL_CONSOLE is not set # CONFIG_OTHER_SERIAL_CONSOLE is not set # CONFIG_NO_SERIAL_CONSOLE is not set From c760d00158044e1b9fbfbb8000e17362e8232407 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Sun, 19 Mar 2017 18:27:31 +0100 Subject: [PATCH 45/81] stm32f33xx_comp.h: fix typos --- arch/arm/src/stm32/chip/stm32f33xxx_comp.h | 33 +++++++++++----------- 1 file changed, 17 insertions(+), 16 deletions(-) diff --git a/arch/arm/src/stm32/chip/stm32f33xxx_comp.h b/arch/arm/src/stm32/chip/stm32f33xxx_comp.h index a0803ea04bf..0e83a1c965c 100644 --- a/arch/arm/src/stm32/chip/stm32f33xxx_comp.h +++ b/arch/arm/src/stm32/chip/stm32f33xxx_comp.h @@ -72,7 +72,8 @@ # define COMP_CSR_INMSEL_1P2VREF (1 << COMP_CSR_INMSEL_SHIFT) /* 0001: 1/2 of Vrefint */ # define COMP_CSR_INMSEL_3P4VREF (2 << COMP_CSR_INMSEL_SHIFT) /* 0010: 3/4 of Vrefint */ # define COMP_CSR_INMSEL_VREF (3 << COMP_CSR_INMSEL_SHIFT) /* 0011: Vrefint */ -# define COMP_CSR_INMSEL_PA4 (4 << COMP_CSR_INMSEL_SHIFT) /* 0100: PA4 or DAC1_CH output if enabled */ +# define COMP_CSR_INMSEL_PA4 (4 << COMP_CSR_INMSEL_SHIFT) /* 0100: PA4 or */ +# define COMP_CSR_INMSEL_DAC1CH1 (4 << COMP_CSR_INMSEL_SHIFT) /* 0100: DAC1_CH1 output if enabled */ # define COMP_CSR_INMSEL_DAC1CH2 (5 << COMP_CSR_INMSEL_SHIFT) /* 0101: DAC1_CH2 output */ # define COMP_CSR_INMSEL_PA2 (6 << COMP_CSR_INMSEL_SHIFT) /* 0110: PA2 (COMP2 only) */ # define COMP_CSR_INMSEL_PB2 (7 << COMP4_CSR_INMSEL_SHIFT) /* 0111: PB2 (COMP4 only) */ @@ -87,32 +88,32 @@ /* 0011: Reserved */ /* 0100: Reserved */ # define COMP_CSR_OUTSEL_BRK2_ (5 << COMP_CSR_INMSEL_SHIFT) /* 0101: Timer 1 break input2 */ -# define COMP_CSR_OUTSEL_T1OCCC (6 << COMP_CSR_INMSEL_SHIFT) /* 0110: Timer 1 OCREF_CLR input (COMP2 only) */ +# define COMP_CSR_OUTSEL_T1OCC (6 << COMP_CSR_INMSEL_SHIFT) /* 0110: Timer 1 OCREF_CLR input (COMP2 only) */ # define COMP_CSR_OUTSEL_T3CAP3 (6 << COMP_CSR_INMSEL_SHIFT) /* 0110: Timer 3 input apture 3 (COMP4 only) */ # define COMP_CSR_OUTSEL_T2CAP2 (6 << COMP_CSR_INMSEL_SHIFT) /* 0110: Timer 2 input apture 2 (COMP6 only) */ # define COMP_CSR_OUTSEL_T1CAP1 (7 << COMP_CSR_INMSEL_SHIFT) /* 0111: Timer 1 input capture 1 (COMP2 only) */ # define COMP_CSR_OUTSEL_T2CAP4 (8 << COMP_CSR_INMSEL_SHIFT) /* 1000: Timer 2 input capture 4 (COMP2 only) */ # define COMP_CSR_OUTSEL_T15CAP2 (8 << COMP_CSR_INMSEL_SHIFT) /* 1000: Timer 15 input capture 2 (COMP4 only) */ -# define COMP_CSR_OUTSEL_T2OCC (8 << COMP_CSR_INMSEL_SHIFT) /* 1000: Timer 2 OCREF CLR input (COMP6 only) */ -# define COMP_CSR_OUTSEL_T2OCC (9 << COMP_CSR_INMSEL_SHIFT) /* 1001: Timer 2 OCREF_CLR input (COMP2 only) */ +# define COMP6_CSR_OUTSEL_T2OCC (8 << COMP_CSR_INMSEL_SHIFT) /* 1000: Timer 2 OCREF CLR input (COMP6 only) */ +# define COMP2_CSR_OUTSEL_T2OCC (9 << COMP_CSR_INMSEL_SHIFT) /* 1001: Timer 2 OCREF_CLR input (COMP2 only) */ # define COMP_CSR_OUTSEL_T16OCC (9 << COMP_CSR_INMSEL_SHIFT) /* 1001: Timer 16 OCREF_CLR input (COMP6 only) */ # define COMP_CSR_OUTSEL_T3CAP1 (10 << COMP_CSR_INMSEL_SHIFT) /* 1010: Timer 3 input capture 1 (COMP2 only) */ -# define COMP_CSR_OUTSEL_T3CAP1 (10 << COMP_CSR_INMSEL_SHIFT) /* 1010: Timer 15 OCREF_CLR input (COMP4 only) */ -# define COMP_CSR_OUTSEL_T3CAP1 (10 << COMP_CSR_INMSEL_SHIFT) /* 1010: Timer 16 input capture 1 (COMP6 only) */ +# define COMP_CSR_OUTSEL_T15OCC (10 << COMP_CSR_INMSEL_SHIFT) /* 1010: Timer 15 OCREF_CLR input (COMP4 only) */ +# define COMP_CSR_OUTSEL_T16CAP1 (10 << COMP_CSR_INMSEL_SHIFT) /* 1010: Timer 16 input capture 1 (COMP6 only) */ # define COMP_CSR_OUTSEL_T3OCC (11 << COMP_CSR_INMSEL_SHIFT) /* 1011: Timer 3 OCREF_CLR input (COMP2,COMP4 only) */ /* Bit 14: Reserved */ #define COMP_CSR_POL (1 << 15) /* Bit 15: comparator output polarity */ /* Bits 16-17: Reserved */ -#define COMP_CSR_BLANCKING_SHIFT (18) /* Bit 18-20: comparator output blanking source */ -#define COMP_CSR_BLANCKING_MASK (7 << COMP_CSR_BLANCKING_SHIFT) -# define COMP_CSR_BLANCKING_DIS (0 << COMP_CSR_BLANCKING_SHIFT) /* 000: No blanking */ -# define COMP_CSR_BLANCKING_T1OC5 (1 << COMP_CSR_BLANCKING_SHIFT) /* 001: TIM1 OC5 as blanking source (COMP2 only) */ -# define COMP_CSR_BLANCKING_T3OC4 (1 << COMP_CSR_BLANCKING_SHIFT) /* 001: TIM3 OC4 as blanking source (COMP4 only) */ -# define COMP_CSR_BLANCKING_T2OC3 (2 << COMP_CSR_BLANCKING_SHIFT) /* 010: TIM2 OC3 as blanking source (COMP2 only) */ -# define COMP_CSR_BLANCKING_T3OC3 (3 << COMP_CSR_BLANCKING_SHIFT) /* 011: TIM3 OC3 as blanking source (COMP2 only) */ -# define COMP_CSR_BLANCKING_T15OC1 (3 << COMP_CSR_BLANCKING_SHIFT) /* 011: TIM15 OC1 as blanking source (COMP4 only) */ -# define COMP_CSR_BLANCKING_T2OC4 (3 << COMP_CSR_BLANCKING_SHIFT) /* 011: TIM2 OC4 as blanking source (COMP6 only) */ -# define COMP_CSR_BLANCKING_T15OC2 (4 << COMP_CSR_BLANCKING_SHIFT) /* 011: TIM15 OC2 as blanking source (COMP6 only) */ +#define COMP_CSR_BLANKING_SHIFT (18) /* Bit 18-20: comparator output blanking source */ +#define COMP_CSR_BLANKING_MASK (7 << COMP_CSR_BLANKING_SHIFT) +# define COMP_CSR_BLANKING_DIS (0 << COMP_CSR_BLANKING_SHIFT) /* 000: No blanking */ +# define COMP_CSR_BLANKING_T1OC5 (1 << COMP_CSR_BLANKING_SHIFT) /* 001: TIM1 OC5 as blanking source (COMP2 only) */ +# define COMP_CSR_BLANKING_T3OC4 (1 << COMP_CSR_BLANKING_SHIFT) /* 001: TIM3 OC4 as blanking source (COMP4 only) */ +# define COMP_CSR_BLANKING_T2OC3 (2 << COMP_CSR_BLANKING_SHIFT) /* 010: TIM2 OC3 as blanking source (COMP2 only) */ +# define COMP_CSR_BLANKING_T3OC3 (3 << COMP_CSR_BLANKING_SHIFT) /* 011: TIM3 OC3 as blanking source (COMP2 only) */ +# define COMP_CSR_BLANKING_T15OC1 (3 << COMP_CSR_BLANKING_SHIFT) /* 011: TIM15 OC1 as blanking source (COMP4 only) */ +# define COMP_CSR_BLANKING_T2OC4 (3 << COMP_CSR_BLANKING_SHIFT) /* 011: TIM2 OC4 as blanking source (COMP6 only) */ +# define COMP_CSR_BLANKING_T15OC2 (4 << COMP_CSR_BLANKING_SHIFT) /* 011: TIM15 OC2 as blanking source (COMP6 only) */ /* Bit 21: Reserved */ #define COMP_CSR_INMSEL_DAC2CH1 (1 << 22) /* Bit 22: used with bits 4-6, DAC2_CH1 output */ /* Bits 23-29: Reserved */ From 651b8360c6d25039d76104c3a40a5d66916896e5 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Sun, 19 Mar 2017 18:36:44 +0100 Subject: [PATCH 46/81] STM32F33: Add COMP support --- arch/arm/src/stm32/Make.defs | 4 + arch/arm/src/stm32/stm32.h | 1 + arch/arm/src/stm32/stm32_comp.c | 838 ++++++++++++++++++++++++++++++++ arch/arm/src/stm32/stm32_comp.h | 281 +++++++++++ 4 files changed, 1124 insertions(+) create mode 100644 arch/arm/src/stm32/stm32_comp.c create mode 100644 arch/arm/src/stm32/stm32_comp.h diff --git a/arch/arm/src/stm32/Make.defs b/arch/arm/src/stm32/Make.defs index 1558c8417d5..970ce3ba0c0 100644 --- a/arch/arm/src/stm32/Make.defs +++ b/arch/arm/src/stm32/Make.defs @@ -217,6 +217,10 @@ ifeq ($(CONFIG_DAC),y) CHIP_CSRCS += stm32_dac.c endif +ifeq ($(CONFIG_COMP),y) +CHIP_CSRCS += stm32_comp.c +endif + ifeq ($(CONFIG_STM32_1WIREDRIVER),y) CHIP_CSRCS += stm32_1wire.c endif diff --git a/arch/arm/src/stm32/stm32.h b/arch/arm/src/stm32/stm32.h index 6680e81293f..534d30246c0 100644 --- a/arch/arm/src/stm32/stm32.h +++ b/arch/arm/src/stm32/stm32.h @@ -59,6 +59,7 @@ #include "stm32_adc.h" //#include "stm32_bkp.h" #include "stm32_can.h" +#include "stm32_comp.h" #include "stm32_dbgmcu.h" #include "stm32_dma.h" #include "stm32_dac.h" diff --git a/arch/arm/src/stm32/stm32_comp.c b/arch/arm/src/stm32/stm32_comp.c new file mode 100644 index 00000000000..59a3abacbc1 --- /dev/null +++ b/arch/arm/src/stm32/stm32_comp.c @@ -0,0 +1,838 @@ +/**************************************************************************** + * arch/arm/src/stm32/stm32_comp.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Mateusz Szafoni + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#include "chip.h" +#include "stm32_gpio.h" +#include "stm32_comp.h" + +#ifdef CONFIG_STM32_COMP + +/* Some COMP peripheral must be enabled */ +/* Up to 7 comparators in STM32F2 Series */ + +#if defined(CONFIG_STM32_COMP1) || defined(CONFIG_STM32_COMP2) || \ + defined(CONFIG_STM32_COMP3) || defined(CONFIG_STM32_COMP4) || \ + defined(CONFIG_STM32_COMP5) || defined(CONFIG_STM32_COMP6) || \ + defined(CONFIG_STM32_COMP7) + +/* @TODO: support for STM32F30XX and STM32F37XX comparators */ + +#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ + defined(CONFIG_STM32_STM32F37XX) + +/* Currently only STM32F33XX supported */ + +#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) +# error "Not supported yet" +#endif + +#if defined(CONFIG_STM32_STM32F33XX) +# if defined(CONFIG_STM32_COMP1) || defined(CONFIG_STM32_COMP3) || \ + defined(CONFIG_STM32_COMP5) || defined(CONFIG_STM32_COMP7) +# error "STM32F33 supports only COMP2, COMP4 and COMP6" +# endif +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +/* COMP2 default configuration **********************************************/ + +#ifdef CONFIG_STM32_COMP2 +# ifndef COMP2_BLANLKING +# define COMP2_BLANKING COMP_BLANKING_DEFAULT +# endif +# ifndef COMP2_POL +# define COMP2_POL COMP_BLANKING_DEFAULT +# endif +# ifndef COMP2_INM +# define COMP2_INM COMP_INM_DEFAULT +# endif +# ifndef COMP2_OUTSEL +# define COMP2_OUTSEL COMP_OUTSEL_DEFAULT +# endif +# ifndef COMP2_LOCK +# define COMP2_LOCK COMP_LOCK_DEFAULT +# endif +#endif + +/* COMP4 default configuration **********************************************/ + +#ifdef CONFIG_STM32_COMP4 +# ifndef COMP4_BLANLKING +# define COMP4_BLANKING COMP_BLANKING_DEFAULT +# endif +# ifndef COMP4_POL +# define COMP4_POL COMP_BLANKING_DEFAULT +# endif +# ifndef COMP4_INM +# define COMP4_INM COMP_INM_DEFAULT +# endif +# ifndef COMP4_OUTSEL +# define COMP4_OUTSEL COMP_OUTSEL_DEFAULT +# endif +# ifndef COMP4_LOCK +# define COMP4_LOCK COMP_LOCK_DEFAULT +# endif +#endif + +/* COMP6 default configuration **********************************************/ + +#ifdef CONFIG_STM32_COMP6 +# ifndef COMP6_BLANLKING +# define COMP6_BLANKING COMP_BLANKING_DEFAULT +# endif +# ifndef COMP6_POL +# define COMP6_POL COMP_BLANKING_DEFAULT +# endif +# ifndef COMP6_INM +# define COMP6_INM COMP_INM_DEFAULT +# endif +# ifndef COMP6_OUTSEL +# define COMP6_OUTSEL COMP_OUTSEL_DEFAULT +# endif +# ifndef COMP6_LOCK +# define COMP6_LOCK COMP_LOCK_DEFAULT +# endif +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +#ifdef CONFIG_STM32_COMP1 +static struct stm32_comp_s g_comp1priv = + { + .blanking = COMP1_BLANKING, + .pol = COMP1_POL, + .inm = COMP1_INM, + .out = COMP1_OUTSEL, + .lock = COMP1_LOCK, + .csr = STM32_COMP1_CSR, +#ifndef CONFIG_STM32_STM32F33XX + .mode = COMP1_MODE, + .hyst = COMP1_HYST, +#endif + }; +#endif + +#ifdef CONFIG_STM32_COMP2 +static struct stm32_comp_s g_comp2priv = + { + .blanking = COMP2_BLANKING, + .pol = COMP2_POL, + .inm = COMP2_INM, + .out = COMP2_OUTSEL, + .lock = COMP2_LOCK, + .csr = STM32_COMP2_CSR, +#ifndef CONFIG_STM32_STM32F33XX + .mode = COMP2_MODE, + .hyst = COMP2_HYST, +#endif + }; +#endif + +#ifdef CONFIG_STM32_COMP3 + static struct stm32_comp_s g_comp3priv = + { + .blanking = COMP3_BLANKING, + .pol = COMP3_POL, + .inm = COMP3_INM, + .out = COMP3_OUTSEL, + .lock = COMP3_LOCK, + .csr = STM32_COMP3_CSR, +#ifndef CONFIG_STM32_STM32F33XX + .mode = COMP3_MODE, + .hyst = COMP3_HYST, +#endif + }; +#endif + +#ifdef CONFIG_STM32_COMP4 + static struct stm32_comp_s g_comp4priv = + { + .blanking = COMP4_BLANKING, + .pol = COMP4_POL, + .inm = COMP4_INM, + .out = COMP4_OUTSEL, + .lock = COMP4_LOCK, + .csr = STM32_COMP4_CSR, +#ifndef CONFIG_STM32_STM32F33XX + .mode = COMP4_MODE, + .hyst = COMP4_HYST, +#endif + }; +#endif + +#ifdef CONFIG_STM32_COMP5 + static struct stm32_comp_s g_comp5priv = + { + .blanking = COMP5_BLANKING, + .pol = COMP5_POL, + .inm = COMP5_INM, + .out = COMP5_OUTSEL, + .lock = COMP5_LOCK, + .csr = STM32_COMP5_CSR, +#ifndef CONFIG_STM32_STM32F33XX + .mode = COMP5_MODE, + .hyst = COMP5_HYST, +#endif + }; +#endif + +#ifdef CONFIG_STM32_COMP6 + static struct stm32_comp_s g_comp6priv = + { + .blanking = COMP6_BLANKING, + .pol = COMP6_POL, + .inm = COMP6_INM, + .out = COMP6_OUTSEL, + .lock = COMP6_LOCK, + .csr = STM32_COMP6_CSR, +#ifndef CONFIG_STM32_STM32F33XX + .mode = COMP6_MODE, + .hyst = COMP6_HYST, +#endif + }; +#endif + +#ifdef CONFIG_STM32_COMP7 + static struct stm32_comp_s g_comp7priv = + { + .blanking = COMP7_BLANKING, + .pol = COMP7_POL, + .inm = COMP7_INM, + .out = COMP7_OUTSEL, + .lock = COMP7_LOCK, + .csr = STM32_COMP7_CSR, +#ifndef CONFIG_STM32_STM32F33XX + .mode = COMP7_MODE, + .hyst = COMP7_HYST, +#endif + }; +#endif + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static inline void comp_modify_csr(FAR struct stm32_comp_s *priv, + uint32_t clearbits, uint32_t setbits); +static inline uint32_t comp_getreg_csr(FAR struct stm32_comp_s *priv); +static inline void comp_putreg_csr(FAR struct stm32_comp_s *priv, + uint32_t value); +static bool stm32_complock_get(FAR struct stm32_comp_s *priv); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: comp_modify_csr + * + * Description: + * Modify the value of a 32-bit COMP CSR register (not atomic). + * + * Input Parameters: + * priv - A reference to the COMP structure + * clrbits - The bits to clear + * setbits - The bits to set + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void comp_modify_csr(FAR struct stm32_comp_s *priv, + uint32_t clearbits, uint32_t setbits) +{ + uint32_t csr = priv->csr; + + modifyreg32(csr, clearbits, setbits); +} + +/**************************************************************************** + * Name: comp_getreg_csr + * + * Description: + * Read the value of an COMP CSR register + * + * Input Parameters: + * priv - A reference to the COMP structure + * + * Returned Value: + * The current contents of the COMP CSR register + * + ****************************************************************************/ + +static inline uint32_t comp_getreg_csr(FAR struct stm32_comp_s *priv) +{ + uint32_t csr = priv->csr; + + return getreg32(csr); +} + +/**************************************************************************** + * Name: comp_putreg_csr + * + * Description: + * Write a value to an COMP register. + * + * Input Parameters: + * priv - A reference to the COMP structure + * value - The value to write to the COMP CSR register + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void comp_putreg_csr(FAR struct stm32_comp_s *priv, + uint32_t value) +{ + uint32_t csr = priv->csr; + + putreg32(value, csr); +} + +/**************************************************************************** + * Name: stm32_comp_complock_get + * + * Description: + * Get COMP lock bit state + * + * Input Parameters: + * priv - A reference to the COMP structure + * + * Returned Value: + * True if COMP locked, false if not locked + * + ****************************************************************************/ + +static bool stm32_complock_get(FAR struct stm32_comp_s *priv) +{ + uint32_t regval; + + regval = comp_getreg_csr(priv); + + return ((regval & COMP_CSR_LOCK == 0) ? false : true); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_compconfig + * + * Description: + * Configure comparator and used I/Os + * + * Input Parameters: + * priv - A reference to the COMP structure + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + * REVISIT: Where to config comparator output pin ? + * + ****************************************************************************/ + +int stm32_compconfig(FAR struct stm32_comp_s *priv) +{ + uint32_t regval; + int index; + + /* Get comparator index */ + + switch (priv->csr) + { +#ifdef CONFIG_STM32_COMP1 + case STM32_COMP1_CSR: + index = 1; + break; +#endif + case STM32_COMP2_CSR: + index = 2; + break; +#ifdef CONFIG_STM32_COMP3 + case STM32_COMP3_CSR: + index = 3; + break; +#endif + case STM32_COMP4_CSR: + index = 4; + break; +#ifdef CONFIG_STM32_COMP5 + case STM32_COMP5_CSR: + index = 5; + break; +#endif + case STM32_COMP6_CSR: + index = 6; + break; +#ifdef CONFIG_STM32_COMP7 + case STM32_COMP7_CSR: + index = 7; + break; +#endif + default: + return -EINVAL; + } + + /* Configure non inverting input */ + + switch (index) + { +#ifdef CONFIG_STM32_COMP2 + case 2: + stm32_configgpio(GPIO_COMP2_INP); + break; +#endif +#ifdef CONFIG_STM32_COMP4 + case 4: + stm32_configgpio(GPIO_COMP4_INP); + break; +#endif +#ifdef CONFIG_STM32_COMP6 + case 6: + stm32_configgpio(GPIO_COMP6_INP); + break; +#endif + default: + return -EINVAL; + } + + /* Set Comparator inverting input */ + + switch (priv->inm) + { + case COMP_INMSEL_1P4VREF: + regval |= COMP_CSR_INMSEL_1P4VREF; + break; + + case COMP_INMSEL_1P2VREF: + regval |= COMP_CSR_INMSEL_1P2VREF; + break; + + case COMP_INMSEL_3P4VREF: + regval |= COMP_CSR_INMSEL_3P4VREF; + break; + + case COMP_INMSEL_VREF: + regval |= COMP_CSR_INMSEL_VREF; + break; + + case COMP_INMSEL_DAC1CH1: + regval |= COMP_CSR_INMSEL_DAC1CH1; + break; + + case COMP_INMSEL_DAC1CH2: + regval |= COMP_CSR_INMSEL_DAC1CH2; + break; + + case COMP_INMSEL_PIN: + { + /* INMSEL PIN configuration dependent on COMP index */ + + switch (index) + { +#ifdef CONFIG_STM32_COMP2 + case 2: + { + stm32_configgpio(GPIO_COMP2_INM); + regval |= COMP_CSR_INMSEL_PA2; + break; + } +#endif +#ifdef CONFIG_STM32_COMP4 + case 4: + { + /* COMP4_INM can be PB2 or PA4 */ + + stm32_configgpio(GPIO_COMP4_INM); + regval |= (GPIO_COMP4_INM == GPIO_COMP4_INM_1 ? COMP_CSR_INMSEL_PB2 : COMP_CSR_INMSEL_PA4); + break; + } +#endif +#ifdef CONFIG_STM32_COMP6 + case 6: + { + /* COMP6_INM can be PB15 or PA4 */ + + stm32_configgpio(GPIO_COMP6_INM); + regval |= (GPIO_COMP6_INM == GPIO_COMP6_INM_1 ? COMP_CSR_INMSEL_PB15 : COMP_CSR_INMSEL_PA4); + break; + } +#endif + default : + return -EINVAL; + } + + break; + } + + default: + return -EINVAL; + } + + /* Set Comparator output selection */ + + switch (priv->out) + { + case COMP_OUTSEL_NOSEL: + regval |= COMP_CSR_OUTSEL_NOSEL; + break; + + case COMP_OUTSEL_BRKACTH: + regval |= COMP_CSR_OUTSEL_BRKACTH; + break; + + case COMP_OUTSEL_BRK2: + regval |= COMP_CSR_OUTSEL_BRK2; + break; + + case COMP_OUTSEL_T1OCC: + regval |= COMP_CSR_OUTSEL_T1OCC; + break; + + case COMP_OUTSEL_T3CAP3: + regval |= COMP_CSR_OUTSEL_T3CAP3; + break; + + case COMP_OUTSEL_T2CAP2: + regval |= COMP_CSR_OUTSEL_T2CAP2; + break; + + case COMP_OUTSEL_T1CAP1: + regval |= COMP_CSR_OUTSEL_T1CAP1; + break; + + case COMP_OUTSEL_T2CAP4: + regval |= COMP_CSR_OUTSEL_T2CAP4; + break; + + case COMP_OUTSEL_T15CAP2: + regval |= COMP_CSR_OUTSEL_T15CAP2; + break; + + case COMP_OUTSEL_T2OCC: + if (index == 2) + regval |= COMP2_CSR_OUTSEL_T2OCC; + else if (index == 6) + regval |= COMP6_CSR_OUTSEL_T2OCC; + break; + + case COMP_OUTSEL_T16OCC: + regval |= COMP_CSR_OUTSEL_T16OCC; + break; + + case COMP_OUTSEL_T3CAP1: + regval |= COMP_CSR_OUTSEL_T3CAP1; + break; + + case COMP_OUTSEL_T15OCC: + regval |= COMP_CSR_OUTSEL_T15OCC; + break; + + case COMP_OUTSEL_T16CAP1: + regval |= COMP_CSR_OUTSEL_T16CAP1; + break; + + case COMP_OUTSEL_T3OCC: + regval |= COMP_CSR_OUTSEL_T3OCC; + break; + + default: + return -EINVAL; + + } + + /* Set Comparator output polarity */ + + regval |= (priv->pol == COMP_POL_INVERTED ? COMP_CSR_POL : 0); + + /* Set Comparator output blanking source */ + + switch (priv->blanking) + { + case COMP_BLANKING_DIS: + regval |= COMP_CSR_BLANKING_DIS; + break; + + case COMP_BLANKING_T1OC5: + regval |= COMP_CSR_BLANKING_T1OC5; + break; + + case COMP_BLANKING_T3OC4: + regval |= COMP_CSR_BLANKING_T3OC4; + break; + + case COMP_BLANKING_T2OC3: + regval |= COMP_CSR_BLANKING_T2OC3; + break; + + case COMP_BLANKING_T15OC1: + regval |= COMP_CSR_BLANKING_T15OC1; + break; + + case COMP_BLANKING_T2OC4: + regval |= COMP_CSR_BLANKING_T2OC4; + break; + + case COMP_BLANKING_T15OC2: + regval |= COMP_CSR_BLANKING_T15OC1; + break; + + default: + return -EINVAL; + } + + /* Save CSR register */ + + comp_putreg_csr(priv, regval); + + /* Enable Comparator */ + + stm32_compenable(priv, true); + + /* Lock Comparator if needed */ + + if (priv->lock == COMP_LOCK_RO) + stm32_complock(priv, true); + + return OK; +} + +/**************************************************************************** + * Name: stm32_compinitialize + * + * Description: + * Initialize the COMP. + * + * Input Parameters: + * intf - The COMP interface number. + * + * Returned Value: + * Valid COMP device structure reference on succcess; a NULL on failure. + * + * Assumptions: + * 1. Clock to the COMP block has enabled, + * 2. Board-specific logic has already configured + * + ****************************************************************************/ + +FAR struct stm32_comp_s* stm32_compinitialize(int intf) +{ + FAR struct stm32_comp_s *priv; + int ret; + + switch (intf) + { +#ifdef CONFIG_STM32_COMP1 + case 1: + ainfo("COMP1 selected\n"); + priv = &g_comp1priv; + break; +#endif +#ifdef CONFIG_STM32_COMP2 + case 2: + ainfo("COMP2 selected\n"); + priv = &g_comp2priv; + break; +#endif +#ifdef CONFIG_STM32_COMP3 + case 3: + ainfo("COMP3 selected\n"); + priv = &g_comp3priv; + break; +#endif +#ifdef CONFIG_STM32_COMP4 + case 4: + ainfo("COMP4 selected\n"); + priv = &g_comp4priv; + break; +#endif +#ifdef CONFIG_STM32_COMP5 + case 5: + ainfo("COMP5 selected\n"); + priv = &g_comp5priv; + break; +#endif +#ifdef CONFIG_STM32_COMP6 + case 6: + ainfo("COMP6 selected\n"); + priv = &g_comp6priv; + break; +#endif +#ifdef CONFIG_STM32_COMP7 + case 7: + ainfo("COMP7 selected\n"); + priv = &g_comp7priv; + break; +#endif + default: + aerr("ERROR: No COMP interface defined\n"); + return NULL; + } + + /* Configure selected comparator */ + + ret = stm32_compconfig(priv); + if (ret < 0) + { + aerr("ERROR: Failed to initialize COMP%d: %d\n", intf, ret); + errno = -ret; + return NULL; + } + + return priv; +} + +/**************************************************************************** + * Name: stm32_compenable + * + * Description: + * Enable/disable comparator + * + * Input Parameters: + * priv - A reference to the COMP structure + * enable - enable/disable flag + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +int stm32_compenable(FAR struct stm32_comp_s *priv, bool enable) +{ + bool lock; + + ainfo("enable: %d\n", enable ? 1 : 0); + + lock = stm32_complock_get(priv); + + if (lock) + { + aerr("ERROR: Comparator locked!\n"); + + return -EPERM; + } + else + { + if (enable) + { + /* Enable the COMP */ + + comp_modify_csr(priv, COMP_CSR_COMPEN, 0); + } + else + { + /* Disable the COMP */ + + comp_modify_csr(priv, 0, COMP_CSR_COMPEN); + } + } + + return OK; +} + +/**************************************************************************** + * Name: stm32_complock + * + * Description: + * Lock comparator CSR register + * + * Input Parameters: + * priv - A reference to the COMP structure + * enable - lock flag + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +int stm32_complock(FAR struct stm32_comp_s *priv, bool lock) +{ + bool current; + + current = stm32_complock_get(priv); + + if (current) + { + if (lock == false) + { + aerr("ERROR: COMP LOCK can be cleared only by a system reset\n"); + + return -EPERM; + } + } + else + { + if (lock == true) + { + comp_modify_csr(priv, COMP_CSR_LOCK, 0); + + priv->lock = COMP_LOCK_RO; + } + } + + return OK; +} + +#endif /* CONFIG_STM32_STM32F30XX || CONFIG_STM32_STM32F33XX || + * CONFIG_STM32_STM32F37XX*/ + +#endif /* CONFIG_STM32_COMP2 || CONFIG_STM32_COMP4 || + * CONFIG_STM32_COMP6 */ + +#endif /* CONFIG_STM32_COMP */ diff --git a/arch/arm/src/stm32/stm32_comp.h b/arch/arm/src/stm32/stm32_comp.h new file mode 100644 index 00000000000..3b858dbcc3d --- /dev/null +++ b/arch/arm/src/stm32/stm32_comp.h @@ -0,0 +1,281 @@ +/************************************************************************************ + * arch/arm/src/stm32/stm32_comp.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Mateusz Szafoni + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32_STM32_COMP_H +#define __ARCH_ARM_SRC_STM32_STM32_COMP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" + +#if defined(CONFIG_STM32_STM32F30XX) +# error "COMP support for STM32F30XX not implemented yet" +#elif defined(CONFIG_STM32_STM32F33XX) +# include "chip/stm32f33xxx_comp.h" +#elif defined(CONFIG_STM32_STM32F37XX) +# error "COMP support for STM32F37XX ot implemented yet" +#endif + +/************************************************************************************ + * Pre-processor definitions + ************************************************************************************/ + +#define COMP_BLANKING_DEFAULT COMP_BLANKING_DIS /* No blanking */ +#define COMP_POL_DEFAULT COMP_POL_NONINVERT /* Output is not inverted */ +#define COMP_INM_DEFAULT COMP_INMSEL_1P4VREF /* 1/4 of Vrefint as INM */ +#define COMP_OUTSEL_DEFAULT COMP_OUTSEL_NOSEL /* Output not selected */ +#define COMP_LOCK_DEFAULT COMP_LOCK_RO /* Do not lock CSR register */ + +#ifndef CONFIG_STM32_STM32F33XX +#define COMP_MODE_DEFAULT +#define COMP_HYST_DEFAULT +#define COMP_WINMODE_DEFAULT +#endif + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/* Blanking source */ + +enum stm32_comp_blanking_e + { + COMP_BLANKING_DIS, +#if defined(CONFIG_STM32_STM32F33XX) + COMP_BLANKING_T1OC5, + COMP_BLANKING_T3OC4, + COMP_BLANKING_T2OC3, + COMP_BLANKING_T3OC3, + COMP_BLANKING_T15OC1, + COMP_BLANKING_T2OC4, + COMP_BLANKING_T15OC2, +#endif + }; + +/* Output polarisation */ + +enum stm32_comp_pol_e + { + COMP_POL_NONINVERT, + COMP_POL_INVERTED + }; + +/* Inverting input */ + +enum stm32_comp_inm_e + { + COMP_INMSEL_1P4VREF, + COMP_INMSEL_1P2VREF, + COMP_INMSEL_3P4VREF, + COMP_INMSEL_VREF, + COMP_INMSEL_DAC1CH1, + COMP_INMSEL_DAC1CH2, + COMP_INMSEL_PIN + }; + +/* Output selection */ + +enum stm32_comp_outsel_e + { + COMP_OUTSEL_NOSEL, +#if defined(CONFIG_STM32_STM32F33XX) + COMP_OUTSEL_BRKACTH, + COMP_OUTSEL_BRK2, + COMP_OUTSEL_T1OCC, /* COMP2 only */ + COMP_OUTSEL_T3CAP3, /* COMP4 only */ + COMP_OUTSEL_T2CAP2, /* COMP6 only */ + COMP_OUTSEL_T1CAP1, /* COMP2 only */ + COMP_OUTSEL_T2CAP4, /* COMP2 only */ + COMP_OUTSEL_T15CAP2, /* COMP4 only */ + COMP_OUTSEL_T2OCC, /* COMP6 only */ + COMP_OUTSEL_T16OCC, /* COMP2 only */ + COMP_OUTSEL_T3CAP1, /* COMP2 only */ + COMP_OUTSEL_T15OCC, /* COMP4 only */ + COMP_OUTSEL_T16CAP1, /* COMP6 only */ + COMP_OUTSEL_T3OCC, /* COMP2 and COMP4 only */ +#endif + }; + +/* CSR register lock state */ + +enum stm32_comp_lock_e + { + COMP_LOCK_RW, + COMP_LOCK_RO + }; + +#ifndef CONFIG_STM32_STM32F33XX + +/* Hysteresis */ + +enum stm32_comp_hyst_e + { + COMP_HYST_DIS, + COMP_HYST_LOW, + COMP_HYST_MEDIUM, + COMP_HYST_HIGH + }, + +/* Power/Speed Modes */ + +enum stm32_comp_mode_e + { + COMP_MODE_HIGHSPEED, + COMP_MODE_MEDIUMSPEED, + COMP_MODE_LOWPOWER, + COMP_MODE_ULTRALOWPOWER + }; + +/* Window mode */ + +enum stm32_comp_winmode_e + { + COMP_WINMODE_DIS, + COMP_WINMODE_EN + }; + +#endif + +/* Comparator configuration ***********************************************************/ + +struct stm32_comp_s +{ + uint8_t blanking; /* Blanking source */ + uint8_t pol; /* Output polarity */ + uint8_t inm; /* Inverting input selection */ + uint8_t out; /* Comparator output */ + uint8_t lock; /* Comparator Lock */ + uint32_t csr; /* Control and status register */ +#ifndef CONFIG_STM32_STM32F33XX + uint8_t mode; /* Comparator mode */ + uint8_t hyst; /* Comparator hysteresis */ + /* @TODO: Window mode + INP selection */ +#endif +}; + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** +* Name: stm32_compconfig +* +* Description: +* Configure comparator and used I/Os +* +* Input Parameters: +* priv - A reference to the COMP structure +* +* Returned Value: +* 0 on success, a negated errno value on failure +* +****************************************************************************/ + +int stm32_compconfig(FAR struct stm32_comp_s *priv); + +/**************************************************************************** +* Name: stm32_compinitialize +* +* Description: +* Initialize the COMP. +* +* Input Parameters: +* intf - The COMP interface number. +* +* Returned Value: +* Valid COMP device structure reference on succcess; a NULL on failure. +* +* Assumptions: +* 1. Clock to the COMP block has enabled, +* 2. Board-specific logic has already configured +* +****************************************************************************/ + +FAR struct stm32_comp_s* stm32_compinitialize(int intf); + +/**************************************************************************** +* Name: stm32_compenable +* +* Description: +* Enable/disable comparator +* +* Input Parameters: +* priv - A reference to the COMP structure +* enable - enable/disable flag +* +* Returned Value: +* 0 on success, a negated errno value on failure +* +****************************************************************************/ + +int stm32_compenable(FAR struct stm32_comp_s *priv, bool enable); + +/**************************************************************************** +* Name: stm32_complock +* +* Description: +* Lock comparator CSR register +* +* Input Parameters: +* priv - A reference to the COMP structure +* enable - lock flag +* +* Returned Value: +* 0 on success, a negated errno value on failure +* +****************************************************************************/ + +int stm32_complock(FAR struct stm32_comp_s *priv, bool lock); + +#undef EXTERN +#ifdef __cplusplus +} +#endif +#endif /* __ASSEMBLY__ */ + +#endif /* __ARCH_ARM_SRC_STM32_STM32_COMP_H */ From 726fd224db92602ed93a48f83779f01c8d9679fe Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Sun, 19 Mar 2017 18:39:41 +0100 Subject: [PATCH 47/81] nucleo-f334r8: Add COMP support --- configs/nucleo-f334r8/src/nucleo-f334r8.h | 12 ++ configs/nucleo-f334r8/src/stm32_appinit.c | 10 ++ configs/nucleo-f334r8/src/stm32_comp.c | 140 ++++++++++++++++++++++ 3 files changed, 162 insertions(+) diff --git a/configs/nucleo-f334r8/src/nucleo-f334r8.h b/configs/nucleo-f334r8/src/nucleo-f334r8.h index d9cd2e1cf7c..20b2dbbd5b4 100644 --- a/configs/nucleo-f334r8/src/nucleo-f334r8.h +++ b/configs/nucleo-f334r8/src/nucleo-f334r8.h @@ -190,4 +190,16 @@ int stm32_adc_setup(void); int stm32_can_setup(void); #endif +/**************************************************************************** + * Name: stm32_comp_setup + * + * Description: + * Initialize COMP peripheral for the board. + * + ****************************************************************************/ + +#ifdef CONFIG_COMP +int stm32_comp_setup(void); +#endif + #endif /* __CONFIGS_NUCLEO_F334R8_SRC_NUCLEO_F334R8_H */ diff --git a/configs/nucleo-f334r8/src/stm32_appinit.c b/configs/nucleo-f334r8/src/stm32_appinit.c index 3579835c631..2eb43b85b08 100644 --- a/configs/nucleo-f334r8/src/stm32_appinit.c +++ b/configs/nucleo-f334r8/src/stm32_appinit.c @@ -127,6 +127,16 @@ int board_app_initialize(uintptr_t arg) } #endif +#ifdef CONFIG_COMP + /* Initialize COMP and register the COMP driver. */ + + ret = stm32_comp_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_comp_setup failed: %d\n", ret); + } +#endif + UNUSED(ret); return OK; } diff --git a/configs/nucleo-f334r8/src/stm32_comp.c b/configs/nucleo-f334r8/src/stm32_comp.c index e69de29bb2d..392dd92d7a0 100644 --- a/configs/nucleo-f334r8/src/stm32_comp.c +++ b/configs/nucleo-f334r8/src/stm32_comp.c @@ -0,0 +1,140 @@ +/**************************************************************************** + * configs/nucleo-f334r8/src/stm32_comp.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Mateusz Szafoni + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +/* #include */ + +#include "stm32.h" + +#if defined(CONFIG_COMP) && (defined(CONFIG_STM32_COMP2) || \ + defined(CONFIG_STM32_COMP4) || \ + defined(CONFIG_STM32_COMP6)) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_comp_setup + * + * Description: + * Initialize COMP + * + ****************************************************************************/ + +int stm32_comp_setup(void) +{ + static bool initialized = false; + struct stm32_comp_s* comp = NULL; + int ret; + UNUSED(ret); + + if (!initialized) + { +#ifdef CONFIG_STM32_COMP2 + comp = stm32_compinitialize(2); + if (comp == NULL) + { + aerr("ERROR: Failed to get COMP%d interface\n", 2); + return -ENODEV; + } +#endif + +#ifdef CONFIG_STM32_COMP4 + comp = stm32_compinitialize(4); + if (comp == NULL) + { + aerr("ERROR: Failed to get COMP%d interface\n", 4); + return -ENODEV; + } +#endif + +#ifdef CONFIG_STM32_COMP6 + comp = stm32_compinitialize(6); + if (comp == NULL) + { + aerr("ERROR: Failed to get COMP%d interface\n", 6); + return -ENODEV; + } +#endif + + +#if 0 + /* COMP driver not implemented yet */ + + ret = comp_register("/dev/comp0", comp); + if (ret < 0) + { + aerr("ERROR: comp_register failed: %d\n", ret); + return ret; + } +#endif + + initialized = true; + } + + return OK; +} + + +#endif /* CONFIG_COMP && (CONFIG_STM32_COMP1 || + * CONFIG_STM32_COMP2 + * CONFIG_STM32_COMP6) */ From 5c0be816a5742fb3158c1a6f18eefdf84b7f445d Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 19 Mar 2017 12:48:37 -0600 Subject: [PATCH 48/81] XMC4xxx: Add commin USIC support logic for use in all USIC configurations. --- arch/arm/include/xmc4/chip.h | 8 +- arch/arm/src/xmc4/Make.defs | 2 +- arch/arm/src/xmc4/chip/xmc4_scu.h | 34 +-- arch/arm/src/xmc4/xmc4_clrpend.c | 16 -- arch/arm/src/xmc4/xmc4_serial.c | 19 +- arch/arm/src/xmc4/xmc4_usic.c | 397 ++++++++++++++++++++++++++++++ arch/arm/src/xmc4/xmc4_usic.h | 37 ++- 7 files changed, 465 insertions(+), 48 deletions(-) create mode 100644 arch/arm/src/xmc4/xmc4_usic.c diff --git a/arch/arm/include/xmc4/chip.h b/arch/arm/include/xmc4/chip.h index 019c1078230..76cd0c4cd6f 100644 --- a/arch/arm/include/xmc4/chip.h +++ b/arch/arm/include/xmc4/chip.h @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_INCLUDE_XM4_CHIP_H -#define __ARCH_ARM_INCLUDE_XM4_CHIP_H +#ifndef __ARCH_ARM_INCLUDE_XMC4_CHIP_H +#define __ARCH_ARM_INCLUDE_XMC4_CHIP_H /************************************************************************************ * Included Files @@ -49,7 +49,7 @@ /* Get customizations for each supported chip */ #if defined(CONFIG_ARCH_CHIP_XMC4500) -# define XM4_NUSIC 3 /* Three USIC modules: USCI0-2 */ +# define XMC4_NUSIC 3 /* Three USIC modules: USCI0-2 */ #else # error "Unsupported XMC4xxx chip" @@ -127,4 +127,4 @@ * Public Functions ************************************************************************************/ -#endif /* __ARCH_ARM_INCLUDE_XM4_CHIP_H */ +#endif /* __ARCH_ARM_INCLUDE_XMC4_CHIP_H */ diff --git a/arch/arm/src/xmc4/Make.defs b/arch/arm/src/xmc4/Make.defs index 63998a71336..76ddb95391e 100644 --- a/arch/arm/src/xmc4/Make.defs +++ b/arch/arm/src/xmc4/Make.defs @@ -112,7 +112,7 @@ CHIP_ASRCS = CHIP_CSRCS = xmc4_allocateheap.c xmc4_clockconfig.c xmc4_clockutils.c CHIP_CSRCS += xmc4_clrpend.c xmc4_idle.c xmc4_irq.c xmc4_lowputc.c -CHIP_CSRCS += xmc4_gpio.c xmc4_serial.c xmc4_start.c +CHIP_CSRCS += xmc4_gpio.c xmc4_serial.c xmc4_start.c xmc4_usic.c # Configuration-dependent Kinetis files diff --git a/arch/arm/src/xmc4/chip/xmc4_scu.h b/arch/arm/src/xmc4/chip/xmc4_scu.h index 49b74a3e487..d916b8330c5 100644 --- a/arch/arm/src/xmc4/chip/xmc4_scu.h +++ b/arch/arm/src/xmc4/chip/xmc4_scu.h @@ -969,32 +969,32 @@ #define SCU_CGAT0_POSIF0 (1 << 9) /* Bit 9: POSIF0 Gating Status */ #define SCU_CGAT0_POSIF1 (1 << 10) /* Bit 10: POSIF1 Gating Status */ #define SCU_CGAT0_USIC0 (1 << 11) /* Bit 11: USIC0 Gating Status */ -#define SCU_CGAT0_ERU1_ (1 << 16) /* Bit 16: ERU1 Gating Status */ +#define SCU_CGAT0_ERU1 (1 << 16) /* Bit 16: ERU1 Gating Status */ /* Peripheral 1 Clock Gating Status, Peripheral 1 Clock Gating Set, Peripheral 1 Clock Gating Clear */ -#define SCU_CGATSTAT1_CCU43 (1 << 0) /* Bit 0: CCU43 Gating Status */ -#define SCU_CGATSTAT1_LEDTSCU0 (1 << 3) /* Bit 3: LEDTS Gating Status */ -#define SCU_CGATSTAT1_MCAN0 (1 << 4) /* Bit 4: MultiCAN Gating Status */ -#define SCU_CGATSTAT1_DAC (1 << 5) /* Bit 5: DAC Gating Status */ -#define SCU_CGATSTAT1_MMCI (1 << 6) /* Bit 6: MMC Interface Gating Status */ -#define SCU_CGATSTAT1_USIC1 (1 << 7) /* Bit 7: USIC1 Gating Status */ -#define SCU_CGATSTAT1_USIC2 (1 << 8) /* Bit 8: USIC1 Gating Status */ -#define SCU_CGATSTAT1_PPORTS (1 << 9) /* Bit 9: PORTS Gating Status */ +#define SCU_CGAT1_CCU43 (1 << 0) /* Bit 0: CCU43 Gating Status */ +#define SCU_CGAT1_LEDTSCU0 (1 << 3) /* Bit 3: LEDTS Gating Status */ +#define SCU_CGAT1_MCAN0 (1 << 4) /* Bit 4: MultiCAN Gating Status */ +#define SCU_CGAT1_DAC (1 << 5) /* Bit 5: DAC Gating Status */ +#define SCU_CGAT1_MMCI (1 << 6) /* Bit 6: MMC Interface Gating Status */ +#define SCU_CGAT1_USIC1 (1 << 7) /* Bit 7: USIC1 Gating Status */ +#define SCU_CGAT1_USIC2 (1 << 8) /* Bit 8: USIC1 Gating Status */ +#define SCU_CGAT1_PPORTS (1 << 9) /* Bit 9: PORTS Gating Status */ /* Peripheral 2 Clock Gating Status, Peripheral 2 Clock Gating Set, Peripheral 2 Clock Gating Clear */ -#define SCU_CGATSTAT2_WDT (1 << 1) /* Bit 1: WDT Gating Status */ -#define SCU_CGATSTAT2_ETH0 (1 << 2) /* Bit 2: ETH0 Gating Status */ -#define SCU_CGATSTAT2_DMA0 (1 << 4) /* Bit 4: DMA0 Gating Status */ -#define SCU_CGATSTAT2_DMA1 (1 << 5) /* Bit 5: DMA1 Gating Status */ -#define SCU_CGATSTAT2_FCE (1 << 6) /* Bit 6: FCE Gating Status */ -#define SCU_CGATSTAT2_USB (1 << 7) /* Bit 7: USB Gating Status */ -#define SCU_CGATSTAT2_ECAT (1 << 10) /* Bit 10: ECAT Gating Status */ +#define SCU_CGAT2_WDT (1 << 1) /* Bit 1: WDT Gating Status */ +#define SCU_CGAT2_ETH0 (1 << 2) /* Bit 2: ETH0 Gating Status */ +#define SCU_CGAT2_DMA0 (1 << 4) /* Bit 4: DMA0 Gating Status */ +#define SCU_CGAT2_DMA1 (1 << 5) /* Bit 5: DMA1 Gating Status */ +#define SCU_CGAT2_FCE (1 << 6) /* Bit 6: FCE Gating Status */ +#define SCU_CGAT2_USB (1 << 7) /* Bit 7: USB Gating Status */ +#define SCU_CGAT2_ECAT (1 << 10) /* Bit 10: ECAT Gating Status */ /* Peripheral 3 Clock Gating Status, Peripheral 3 Clock Gating Set, Peripheral 3 Clock Gating Clear */ -#define SCU_CGATSTAT3_EBU (1 << 2) /* Bit 2: EBU Gating Status */ +#define SCU_CGAT3_EBU (1 << 2) /* Bit 2: EBU Gating Status */ /* Oscillator Control SCU Registers */ diff --git a/arch/arm/src/xmc4/xmc4_clrpend.c b/arch/arm/src/xmc4/xmc4_clrpend.c index 2eab7d6ffa2..33422ea5e2e 100644 --- a/arch/arm/src/xmc4/xmc4_clrpend.c +++ b/arch/arm/src/xmc4/xmc4_clrpend.c @@ -44,22 +44,6 @@ #include "nvic.h" #include "up_arch.h" -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - /**************************************************************************** * Public Functions ****************************************************************************/ diff --git a/arch/arm/src/xmc4/xmc4_serial.c b/arch/arm/src/xmc4/xmc4_serial.c index e09a23ef55f..78db3fd792d 100644 --- a/arch/arm/src/xmc4/xmc4_serial.c +++ b/arch/arm/src/xmc4/xmc4_serial.c @@ -232,6 +232,7 @@ struct xmc4_dev_s uintptr_t uartbase; /* Base address of UART registers */ uint32_t baud; /* Configured baud */ uint32_t clock; /* Clocking frequency of the UART module */ + uint8_t channel; /* USIC channel identification */ uint8_t irqs; /* Status IRQ associated with this UART (for enable) */ uint8_t ie; /* Interrupts enabled */ uint8_t parity; /* 0=none, 1=odd, 2=even */ @@ -312,8 +313,9 @@ static char g_uart5txbuffer[CONFIG_UART5_TXBUFSIZE]; #ifdef HAVE_UART0 static struct xmc4_dev_s g_uart0priv = { - .uartbase = XMC4_UART0_BASE, + .uartbase = XMC4_USIC0_CH0_BASE, .clock = BOARD_CORECLK_FREQ, + .channel = (uint8_t)USIC0_CHAN0, .baud = CONFIG_UART0_BAUD, .irqs = XMC4_IRQ_USIC0, .parity = CONFIG_UART0_PARITY, @@ -343,8 +345,9 @@ static uart_dev_t g_uart0port = #ifdef HAVE_UART1 static struct xmc4_dev_s g_uart1priv = { - .uartbase = XMC4_UART1_BASE, + .uartbase = XMC4_USIC0_CH1_BASE, .clock = BOARD_CORECLK_FREQ, + .channel = (uint8_t)USIC0_CHAN1, .baud = CONFIG_UART1_BAUD, .irqs = XMC4_IRQ_USIC1, .parity = CONFIG_UART1_PARITY, @@ -374,8 +377,9 @@ static uart_dev_t g_uart1port = #ifdef HAVE_UART2 static struct xmc4_dev_s g_uart2priv = { - .uartbase = XMC4_UART2_BASE, + .uartbase = XMC4_USIC1_CH0_BASE, .clock = BOARD_BUS_FREQ, + .channel = (uint8_t)USIC1_CHAN0, .baud = CONFIG_UART2_BAUD, .irqs = XMC4_IRQ_USIC2, .parity = CONFIG_UART2_PARITY, @@ -405,8 +409,9 @@ static uart_dev_t g_uart2port = #ifdef HAVE_UART3 static struct xmc4_dev_s g_uart3priv = { - .uartbase = XMC4_UART3_BASE, + .uartbase = XMC4_USIC1_CH1_BASE, .clock = BOARD_BUS_FREQ, + .channel = (uint8_t)USIC1_CHAN1, .baud = CONFIG_UART3_BAUD, .irqs = XMC4_IRQ_USIC3, .parity = CONFIG_UART3_PARITY, @@ -436,8 +441,9 @@ static uart_dev_t g_uart3port = #ifdef HAVE_UART4 static struct xmc4_dev_s g_uart4priv = { - .uartbase = XMC4_UART4_BASE, + .uartbase = XMC4_USIC2_CH0_BASE, .clock = BOARD_BUS_FREQ, + .channel = (uint8_t)USIC2_CHAN0, .baud = CONFIG_UART4_BAUD, .irqs = XMC4_IRQ_USIC4, .parity = CONFIG_UART4_PARITY, @@ -467,8 +473,9 @@ static uart_dev_t g_uart4port = #ifdef HAVE_UART5 static struct xmc4_dev_s g_uart5priv = { - .uartbase = XMC4_UART5_BASE, + .uartbase = XMC4_USIC2_CH1_BASE, .clock = BOARD_BUS_FREQ, + .channel = (uint8_t)USIC2_CHAN1, .baud = CONFIG_UART5_BAUD, .irqs = XMC4_IRQ_USIC5, .parity = CONFIG_UART5_PARITY, diff --git a/arch/arm/src/xmc4/xmc4_usic.c b/arch/arm/src/xmc4/xmc4_usic.c new file mode 100644 index 00000000000..f252bb1a499 --- /dev/null +++ b/arch/arm/src/xmc4/xmc4_usic.c @@ -0,0 +1,397 @@ +/**************************************************************************** + * arch/arm/src/xmc4/xmc4_usic.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "up_arch.h" +#include "chip/xmc4_usic.h" +#include "chip/xmc4_scu.h" +#include "xmc4_usic.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: xmc4_enable_usic + * + * Description: + * Enable the USIC module indicated by the 'usic' enumeration value + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned to + * indicate the nature of any failure. + * + ****************************************************************************/ + +int xmc4_enable_usic(enum usic_e usic) +{ + switch (usic) + { + case USIC0: + /* Check if USIC0 is already ungated */ + + if ((getreg32(XMC4_SCU_CGATSTAT0) & SCU_CGAT0_USIC0) == 0) + { + /* Ungate USIC0 clocking */ + + putreg32(SCU_CGAT0_USIC0, XMC4_SCU_CGATCLR0); + + /* De-assert peripheral reset USIC0 */ + + putreg32(SCU_PR0_USIC0RS, XMC4_SCU_PRCLR0); + } + + break; + +#if XMC4_NUSIC > 1 + case USIC1: + /* Check if USIC1 is already ungated */ + + if ((getreg32(XMC4_SCU_CGATSTAT1) & SCU_CGAT1_USIC1) == 0) + { + /* Ungate USIC1 clocking */ + + putreg32(SCU_CGAT1_USIC1, XMC4_SCU_CGATCLR1); + + /* De-assert peripheral reset USIC1 */ + + putreg32(SCU_PR1_USIC1RS, XMC4_SCU_PRCLR1); + } + + break; + +#if XMC4_NUSIC > 2 + case USIC2: + /* Check if USIC2 is already ungated */ + + if ((getreg32(XMC4_SCU_CGATSTAT1) & SCU_CGAT1_USIC2) == 0) + { + /* Ungate USIC2 clocking */ + + putreg32(SCU_CGAT1_USIC2, XMC4_SCU_CGATCLR1); + + /* De-assert peripheral reset USIC2 */ + + putreg32(SCU_PR1_USIC2RS, XMC4_SCU_PRCLR1); + } + + break; +#endif +#endif + + default: + return -EINVAL; + } + + return OK; +} + +/**************************************************************************** + * Name: xmc4_disable_usic + * + * Description: + * Disable the USIC module indicated by the 'usic' enumeration value + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned to + * indicate the nature of any failure. + * + ****************************************************************************/ + +int xmc4_disable_usic(enum usic_e usic) +{ + switch (usic) + { + case USIC0: + /* Assert peripheral reset USIC0 */ + + putreg32(SCU_PR0_USIC0RS, XMC4_SCU_PRSET0); + + /* Gate USIC0 clocking */ + + putreg32(SCU_CGAT0_USIC0, XMC4_SCU_CGATSET0); + break; + +#if XMC4_NUSIC > 1 + case USIC1: + /* Assert peripheral reset USIC0 */ + + putreg32(SCU_PR1_USIC1RS, XMC4_SCU_PRSET1); + + /* Gate USIC0 clocking */ + + putreg32(SCU_CGAT1_USIC1, XMC4_SCU_CGATSET1); + break; + +#if XMC4_NUSIC > 2 + case USIC2: + /* Assert peripheral reset USIC0 */ + + putreg32(SCU_PR1_USIC2RS, XMC4_SCU_PRSET1); + + /* Gate USIC0 clocking */ + + putreg32(SCU_CGAT1_USIC2, XMC4_SCU_CGATSET1); + break; +#endif +#endif + + default: + return -EINVAL; + } + + return OK; +} + +/**************************************************************************** + * Name: xmc4_enable_usic_channel + * + * Description: + * Enable the USIC channel indicated by 'channel'. Also enable and reset + * the USIC module if it is not already enabled. + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned to + * indicate the nature of any failure. + * + ****************************************************************************/ + +int xmc4_enable_usic_channel(enum usic_channel_e channel) +{ + uintptr_t base; + uintptr_t regaddr; + uint32_t regval; + + switch (channel) + { + case USIC0_CHAN0: + /* USIC0 Channel 0 base address */ + + base = XMC4_USIC0_CH0_BASE; + + /* Enable USIC0 */ + + xmc4_enable_usic(USIC0); + break; + + case USIC0_CHAN1: + /* USIC0 Channel 1 base address */ + + base = XMC4_USIC0_CH1_BASE; + + /* Enable USIC0 */ + + xmc4_enable_usic(USIC0); + break; + +#if XMC4_NUSIC > 1 + case USIC1_CHAN0: + /* USIC1 Channel 0 base address */ + + base = XMC4_USIC1_CH0_BASE; + + /* Enable USIC1 */ + + xmc4_enable_usic(USIC1); + break; + + case USIC1_CHAN1: + /* USIC1 Channel 1 base address */ + + base = XMC4_USIC1_CH1_BASE; + + /* Enable USIC1 */ + + xmc4_enable_usic(USIC1); + break; + +#if XMC4_NUSIC > 2 + case USIC2_CHAN0: + /* USIC2 Channel 0 base address */ + + base = XMC4_USIC2_CH0_BASE; + + /* Enable USIC2 */ + + xmc4_enable_usic(USIC2); + break; + + case USIC2_CHAN1: + /* USIC2 Channel 1 base address */ + + base = XMC4_USIC2_CH1_BASE; + + /* Enable USIC2 */ + + xmc4_enable_usic(USIC2); + break; +#endif +#endif + + default: + return -EINVAL; + } + + /* Enable USIC channel */ + + regaddr = base + XMC4_USIC_KSCFG_OFFSET; + putreg32(USIC_KSCFG_MODEN | USIC_KSCFG_BPMODEN, regaddr); + + /* Wait for the channel to become fully enabled */ + + while ((getreg32(regaddr) & USIC_KSCFG_MODEN) == 0) + { + } + + /* Set USIC channel in IDLE mode */ + + regaddr = base + XMC4_USIC_CCR_OFFSET; + regval = getreg32(regaddr); + regval &= ~USIC_CCR_MODE_MASK; + putreg32(regval, regaddr); + + return OK; +} + +/**************************************************************************** + * Name: xmc4_disable_usic_channel + * + * Description: + * Disable the USIC channel indicated by 'channel'. Also disable and reset + * the USIC module if both channels have been disabled. + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned to + * indicate the nature of any failure. + * + ****************************************************************************/ + +int xmc4_disable_usic_channel(enum usic_channel_e channel) +{ + uintptr_t base; + uintptr_t other; + uintptr_t regaddr; + uint32_t regval; + enum usic_e usic; + + switch (channel) + { + case USIC0_CHAN0: + /* Enable USIC0 Channel 0 base address */ + + base = XMC4_USIC0_CH0_BASE; + other = XMC4_USIC0_CH1_BASE; + usic = USIC0; + break; + + case USIC0_CHAN1: + /* Enable USIC0 Channel 1 base address */ + + base = XMC4_USIC0_CH1_BASE; + other = XMC4_USIC0_CH0_BASE; + usic = USIC0; + break; + +#if XMC4_NUSIC > 1 + case USIC1_CHAN0: + /* Enable USIC1 Channel 0 base address */ + + base = XMC4_USIC1_CH0_BASE; + other = XMC4_USIC1_CH1_BASE; + usic = USIC1; + break; + + case USIC1_CHAN1: + /* Enable USIC1 Channel 1 base address */ + + base = XMC4_USIC1_CH1_BASE; + other = XMC4_USIC1_CH0_BASE; + usic = USIC1; + break; + +#if XMC4_NUSIC > 2 + case USIC2_CHAN0: + /* Enable USIC2 Channel 0 base address */ + + base = XMC4_USIC2_CH0_BASE; + other = XMC4_USIC2_CH1_BASE; + usic = USIC2; + break; + + case USIC2_CHAN1: + /* Enable USIC2 Channel 1 base address */ + + base = XMC4_USIC2_CH1_BASE; + other = XMC4_USIC2_CH0_BASE; + usic = USIC2; + break; +#endif +#endif + + default: + return -EINVAL; + } + + /* Disable this channel */ + + regaddr = base + XMC4_USIC_KSCFG_OFFSET; + regval = getreg32(regaddr); + regval &= ~USIC_KSCFG_MODEN; + regval |= USIC_KSCFG_BPMODEN; + putreg32(regval, regaddr); + + /* Check if the other channel has also been disabled */ + + regaddr = other + XMC4_USIC_KSCFG_OFFSET; + if ((getreg32(regaddr) & USIC_KSCFG_MODEN) == 0) + { + /* Yes... Disable the USIC module */ + + xmc4_disable_usic(usic); + } + + return OK; +} \ No newline at end of file diff --git a/arch/arm/src/xmc4/xmc4_usic.h b/arch/arm/src/xmc4/xmc4_usic.h index d589459037b..e1bf78dc07f 100644 --- a/arch/arm/src/xmc4/xmc4_usic.h +++ b/arch/arm/src/xmc4/xmc4_usic.h @@ -67,10 +67,10 @@ enum usic_channel_e { USIC0_CHAN0 = 0, /* USIC0, Channel 0 */ USIC0_CHAN1 = 1, /* USIC0, Channel 1 */ - USIC1_CHAN0 = 0, /* USIC1, Channel 0 */ - USIC1_CHAN1 = 1, /* USIC1, Channel 1 */ - USIC2_CHAN0 = 0, /* USIC2, Channel 0 */ - USIC2_CHAN1 = 1 /* USIC2, Channel 1 */ + USIC1_CHAN0 = 2, /* USIC1, Channel 0 */ + USIC1_CHAN1 = 3, /* USIC1, Channel 1 */ + USIC2_CHAN0 = 4, /* USIC2, Channel 0 */ + USIC2_CHAN1 = 5 /* USIC2, Channel 1 */ }; /**************************************************************************** @@ -91,6 +91,20 @@ enum usic_channel_e int xmc4_enable_usic(enum usic_e usic); +/**************************************************************************** + * Name: xmc4_disable_usic + * + * Description: + * Disable the USIC module indicated by the 'usic' enumeration value + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned to + * indicate the nature of any failure. + * + ****************************************************************************/ + +int xmc4_disable_usic(enum usic_e usic); + /**************************************************************************** * Name: xmc4_enable_usic_channel * @@ -106,4 +120,19 @@ int xmc4_enable_usic(enum usic_e usic); int xmc4_enable_usic_channel(enum usic_channel_e channel); +/**************************************************************************** + * Name: xmc4_disable_usic_channel + * + * Description: + * Disable the USIC channel indicated by 'channel'. Also disable and reset + * the USIC module if both channels have been disabled. + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned to + * indicate the nature of any failure. + * + ****************************************************************************/ + +int xmc4_disable_usic_channel(enum usic_channel_e channel); + #endif /* __ARCH_ARM_SRC_XMC4_XMC4_USIC_H */ From e8a30890f2229a9849ed59fc856b82d01f066f80 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 19 Mar 2017 13:05:31 -0600 Subject: [PATCH 49/81] Cosmetic changes from review of last PR. --- arch/arm/src/stm32/stm32_comp.c | 187 ++++++++++++++----------- arch/arm/src/stm32/stm32_comp.h | 120 ++++++++-------- configs/nucleo-f334r8/src/stm32_comp.c | 18 --- 3 files changed, 163 insertions(+), 162 deletions(-) diff --git a/arch/arm/src/stm32/stm32_comp.c b/arch/arm/src/stm32/stm32_comp.c index 59a3abacbc1..548baa9b110 100644 --- a/arch/arm/src/stm32/stm32_comp.c +++ b/arch/arm/src/stm32/stm32_comp.c @@ -147,114 +147,114 @@ #ifdef CONFIG_STM32_COMP1 static struct stm32_comp_s g_comp1priv = - { - .blanking = COMP1_BLANKING, - .pol = COMP1_POL, - .inm = COMP1_INM, - .out = COMP1_OUTSEL, - .lock = COMP1_LOCK, - .csr = STM32_COMP1_CSR, +{ + .blanking = COMP1_BLANKING, + .pol = COMP1_POL, + .inm = COMP1_INM, + .out = COMP1_OUTSEL, + .lock = COMP1_LOCK, + .csr = STM32_COMP1_CSR, #ifndef CONFIG_STM32_STM32F33XX - .mode = COMP1_MODE, - .hyst = COMP1_HYST, + .mode = COMP1_MODE, + .hyst = COMP1_HYST, #endif - }; +}; #endif #ifdef CONFIG_STM32_COMP2 static struct stm32_comp_s g_comp2priv = - { - .blanking = COMP2_BLANKING, - .pol = COMP2_POL, - .inm = COMP2_INM, - .out = COMP2_OUTSEL, - .lock = COMP2_LOCK, - .csr = STM32_COMP2_CSR, +{ + .blanking = COMP2_BLANKING, + .pol = COMP2_POL, + .inm = COMP2_INM, + .out = COMP2_OUTSEL, + .lock = COMP2_LOCK, + .csr = STM32_COMP2_CSR, #ifndef CONFIG_STM32_STM32F33XX - .mode = COMP2_MODE, - .hyst = COMP2_HYST, + .mode = COMP2_MODE, + .hyst = COMP2_HYST, #endif - }; +}; #endif #ifdef CONFIG_STM32_COMP3 - static struct stm32_comp_s g_comp3priv = - { - .blanking = COMP3_BLANKING, - .pol = COMP3_POL, - .inm = COMP3_INM, - .out = COMP3_OUTSEL, - .lock = COMP3_LOCK, - .csr = STM32_COMP3_CSR, +static struct stm32_comp_s g_comp3priv = +{ + .blanking = COMP3_BLANKING, + .pol = COMP3_POL, + .inm = COMP3_INM, + .out = COMP3_OUTSEL, + .lock = COMP3_LOCK, + .csr = STM32_COMP3_CSR, #ifndef CONFIG_STM32_STM32F33XX - .mode = COMP3_MODE, - .hyst = COMP3_HYST, + .mode = COMP3_MODE, + .hyst = COMP3_HYST, #endif - }; +}; #endif #ifdef CONFIG_STM32_COMP4 - static struct stm32_comp_s g_comp4priv = - { - .blanking = COMP4_BLANKING, - .pol = COMP4_POL, - .inm = COMP4_INM, - .out = COMP4_OUTSEL, - .lock = COMP4_LOCK, - .csr = STM32_COMP4_CSR, +static struct stm32_comp_s g_comp4priv = +{ + .blanking = COMP4_BLANKING, + .pol = COMP4_POL, + .inm = COMP4_INM, + .out = COMP4_OUTSEL, + .lock = COMP4_LOCK, + .csr = STM32_COMP4_CSR, #ifndef CONFIG_STM32_STM32F33XX - .mode = COMP4_MODE, - .hyst = COMP4_HYST, + .mode = COMP4_MODE, + .hyst = COMP4_HYST, #endif - }; +}; #endif #ifdef CONFIG_STM32_COMP5 - static struct stm32_comp_s g_comp5priv = - { - .blanking = COMP5_BLANKING, - .pol = COMP5_POL, - .inm = COMP5_INM, - .out = COMP5_OUTSEL, - .lock = COMP5_LOCK, - .csr = STM32_COMP5_CSR, +static struct stm32_comp_s g_comp5priv = +{ + .blanking = COMP5_BLANKING, + .pol = COMP5_POL, + .inm = COMP5_INM, + .out = COMP5_OUTSEL, + .lock = COMP5_LOCK, + .csr = STM32_COMP5_CSR, #ifndef CONFIG_STM32_STM32F33XX - .mode = COMP5_MODE, - .hyst = COMP5_HYST, + .mode = COMP5_MODE, + .hyst = COMP5_HYST, #endif - }; +}; #endif #ifdef CONFIG_STM32_COMP6 - static struct stm32_comp_s g_comp6priv = - { - .blanking = COMP6_BLANKING, - .pol = COMP6_POL, - .inm = COMP6_INM, - .out = COMP6_OUTSEL, - .lock = COMP6_LOCK, - .csr = STM32_COMP6_CSR, +static struct stm32_comp_s g_comp6priv = +{ + .blanking = COMP6_BLANKING, + .pol = COMP6_POL, + .inm = COMP6_INM, + .out = COMP6_OUTSEL, + .lock = COMP6_LOCK, + .csr = STM32_COMP6_CSR, #ifndef CONFIG_STM32_STM32F33XX - .mode = COMP6_MODE, - .hyst = COMP6_HYST, + .mode = COMP6_MODE, + .hyst = COMP6_HYST, #endif - }; +}; #endif #ifdef CONFIG_STM32_COMP7 - static struct stm32_comp_s g_comp7priv = - { - .blanking = COMP7_BLANKING, - .pol = COMP7_POL, - .inm = COMP7_INM, - .out = COMP7_OUTSEL, - .lock = COMP7_LOCK, - .csr = STM32_COMP7_CSR, +static struct stm32_comp_s g_comp7priv = +{ + .blanking = COMP7_BLANKING, + .pol = COMP7_POL, + .inm = COMP7_INM, + .out = COMP7_OUTSEL, + .lock = COMP7_LOCK, + .csr = STM32_COMP7_CSR, #ifndef CONFIG_STM32_STM32F33XX - .mode = COMP7_MODE, - .hyst = COMP7_HYST, + .mode = COMP7_MODE, + .hyst = COMP7_HYST, #endif - }; +}; #endif /**************************************************************************** @@ -268,10 +268,6 @@ static inline void comp_putreg_csr(FAR struct stm32_comp_s *priv, uint32_t value); static bool stm32_complock_get(FAR struct stm32_comp_s *priv); -/**************************************************************************** - * Private Data - ****************************************************************************/ - /**************************************************************************** * Private Functions ****************************************************************************/ @@ -401,30 +397,37 @@ int stm32_compconfig(FAR struct stm32_comp_s *priv) index = 1; break; #endif + case STM32_COMP2_CSR: index = 2; break; + #ifdef CONFIG_STM32_COMP3 case STM32_COMP3_CSR: index = 3; break; #endif + case STM32_COMP4_CSR: index = 4; break; + #ifdef CONFIG_STM32_COMP5 case STM32_COMP5_CSR: index = 5; break; #endif + case STM32_COMP6_CSR: index = 6; break; + #ifdef CONFIG_STM32_COMP7 case STM32_COMP7_CSR: index = 7; break; #endif + default: return -EINVAL; } @@ -438,16 +441,19 @@ int stm32_compconfig(FAR struct stm32_comp_s *priv) stm32_configgpio(GPIO_COMP2_INP); break; #endif + #ifdef CONFIG_STM32_COMP4 case 4: stm32_configgpio(GPIO_COMP4_INP); break; #endif + #ifdef CONFIG_STM32_COMP6 case 6: stm32_configgpio(GPIO_COMP6_INP); break; #endif + default: return -EINVAL; } @@ -518,7 +524,7 @@ int stm32_compconfig(FAR struct stm32_comp_s *priv) return -EINVAL; } - break; + break; } default: @@ -567,9 +573,14 @@ int stm32_compconfig(FAR struct stm32_comp_s *priv) case COMP_OUTSEL_T2OCC: if (index == 2) - regval |= COMP2_CSR_OUTSEL_T2OCC; + { + regval |= COMP2_CSR_OUTSEL_T2OCC; + } else if (index == 6) - regval |= COMP6_CSR_OUTSEL_T2OCC; + { + regval |= COMP6_CSR_OUTSEL_T2OCC; + } + break; case COMP_OUTSEL_T16OCC: @@ -594,7 +605,6 @@ int stm32_compconfig(FAR struct stm32_comp_s *priv) default: return -EINVAL; - } /* Set Comparator output polarity */ @@ -648,7 +658,9 @@ int stm32_compconfig(FAR struct stm32_comp_s *priv) /* Lock Comparator if needed */ if (priv->lock == COMP_LOCK_RO) - stm32_complock(priv, true); + { + stm32_complock(priv, true); + } return OK; } @@ -684,42 +696,49 @@ FAR struct stm32_comp_s* stm32_compinitialize(int intf) priv = &g_comp1priv; break; #endif + #ifdef CONFIG_STM32_COMP2 case 2: ainfo("COMP2 selected\n"); priv = &g_comp2priv; break; #endif + #ifdef CONFIG_STM32_COMP3 case 3: ainfo("COMP3 selected\n"); priv = &g_comp3priv; break; #endif + #ifdef CONFIG_STM32_COMP4 case 4: ainfo("COMP4 selected\n"); priv = &g_comp4priv; break; #endif + #ifdef CONFIG_STM32_COMP5 case 5: ainfo("COMP5 selected\n"); priv = &g_comp5priv; break; #endif + #ifdef CONFIG_STM32_COMP6 case 6: ainfo("COMP6 selected\n"); priv = &g_comp6priv; break; #endif + #ifdef CONFIG_STM32_COMP7 case 7: ainfo("COMP7 selected\n"); priv = &g_comp7priv; break; #endif + default: aerr("ERROR: No COMP interface defined\n"); return NULL; diff --git a/arch/arm/src/stm32/stm32_comp.h b/arch/arm/src/stm32/stm32_comp.h index 3b858dbcc3d..99d45bad636 100644 --- a/arch/arm/src/stm32/stm32_comp.h +++ b/arch/arm/src/stm32/stm32_comp.h @@ -75,100 +75,100 @@ /* Blanking source */ enum stm32_comp_blanking_e - { - COMP_BLANKING_DIS, +{ + COMP_BLANKING_DIS, #if defined(CONFIG_STM32_STM32F33XX) - COMP_BLANKING_T1OC5, - COMP_BLANKING_T3OC4, - COMP_BLANKING_T2OC3, - COMP_BLANKING_T3OC3, - COMP_BLANKING_T15OC1, - COMP_BLANKING_T2OC4, - COMP_BLANKING_T15OC2, + COMP_BLANKING_T1OC5, + COMP_BLANKING_T3OC4, + COMP_BLANKING_T2OC3, + COMP_BLANKING_T3OC3, + COMP_BLANKING_T15OC1, + COMP_BLANKING_T2OC4, + COMP_BLANKING_T15OC2, #endif - }; +}; /* Output polarisation */ enum stm32_comp_pol_e - { - COMP_POL_NONINVERT, - COMP_POL_INVERTED - }; +{ + COMP_POL_NONINVERT, + COMP_POL_INVERTED +}; /* Inverting input */ enum stm32_comp_inm_e - { - COMP_INMSEL_1P4VREF, - COMP_INMSEL_1P2VREF, - COMP_INMSEL_3P4VREF, - COMP_INMSEL_VREF, - COMP_INMSEL_DAC1CH1, - COMP_INMSEL_DAC1CH2, - COMP_INMSEL_PIN - }; +{ + COMP_INMSEL_1P4VREF, + COMP_INMSEL_1P2VREF, + COMP_INMSEL_3P4VREF, + COMP_INMSEL_VREF, + COMP_INMSEL_DAC1CH1, + COMP_INMSEL_DAC1CH2, + COMP_INMSEL_PIN +}; /* Output selection */ enum stm32_comp_outsel_e - { - COMP_OUTSEL_NOSEL, +{ + COMP_OUTSEL_NOSEL, #if defined(CONFIG_STM32_STM32F33XX) - COMP_OUTSEL_BRKACTH, - COMP_OUTSEL_BRK2, - COMP_OUTSEL_T1OCC, /* COMP2 only */ - COMP_OUTSEL_T3CAP3, /* COMP4 only */ - COMP_OUTSEL_T2CAP2, /* COMP6 only */ - COMP_OUTSEL_T1CAP1, /* COMP2 only */ - COMP_OUTSEL_T2CAP4, /* COMP2 only */ - COMP_OUTSEL_T15CAP2, /* COMP4 only */ - COMP_OUTSEL_T2OCC, /* COMP6 only */ - COMP_OUTSEL_T16OCC, /* COMP2 only */ - COMP_OUTSEL_T3CAP1, /* COMP2 only */ - COMP_OUTSEL_T15OCC, /* COMP4 only */ - COMP_OUTSEL_T16CAP1, /* COMP6 only */ - COMP_OUTSEL_T3OCC, /* COMP2 and COMP4 only */ + COMP_OUTSEL_BRKACTH, + COMP_OUTSEL_BRK2, + COMP_OUTSEL_T1OCC, /* COMP2 only */ + COMP_OUTSEL_T3CAP3, /* COMP4 only */ + COMP_OUTSEL_T2CAP2, /* COMP6 only */ + COMP_OUTSEL_T1CAP1, /* COMP2 only */ + COMP_OUTSEL_T2CAP4, /* COMP2 only */ + COMP_OUTSEL_T15CAP2, /* COMP4 only */ + COMP_OUTSEL_T2OCC, /* COMP6 only */ + COMP_OUTSEL_T16OCC, /* COMP2 only */ + COMP_OUTSEL_T3CAP1, /* COMP2 only */ + COMP_OUTSEL_T15OCC, /* COMP4 only */ + COMP_OUTSEL_T16CAP1, /* COMP6 only */ + COMP_OUTSEL_T3OCC, /* COMP2 and COMP4 only */ #endif - }; +}; /* CSR register lock state */ enum stm32_comp_lock_e - { - COMP_LOCK_RW, - COMP_LOCK_RO - }; +{ + COMP_LOCK_RW, + COMP_LOCK_RO +}; #ifndef CONFIG_STM32_STM32F33XX /* Hysteresis */ enum stm32_comp_hyst_e - { - COMP_HYST_DIS, - COMP_HYST_LOW, - COMP_HYST_MEDIUM, - COMP_HYST_HIGH - }, +{ + COMP_HYST_DIS, + COMP_HYST_LOW, + COMP_HYST_MEDIUM, + COMP_HYST_HIGH +}, /* Power/Speed Modes */ enum stm32_comp_mode_e - { - COMP_MODE_HIGHSPEED, - COMP_MODE_MEDIUMSPEED, - COMP_MODE_LOWPOWER, - COMP_MODE_ULTRALOWPOWER - }; +{ + COMP_MODE_HIGHSPEED, + COMP_MODE_MEDIUMSPEED, + COMP_MODE_LOWPOWER, + COMP_MODE_ULTRALOWPOWER +}; /* Window mode */ enum stm32_comp_winmode_e - { - COMP_WINMODE_DIS, - COMP_WINMODE_EN - }; +{ + COMP_WINMODE_DIS, + COMP_WINMODE_EN +}; #endif diff --git a/configs/nucleo-f334r8/src/stm32_comp.c b/configs/nucleo-f334r8/src/stm32_comp.c index 392dd92d7a0..0f775e1f3dc 100644 --- a/configs/nucleo-f334r8/src/stm32_comp.c +++ b/configs/nucleo-f334r8/src/stm32_comp.c @@ -52,22 +52,6 @@ defined(CONFIG_STM32_COMP4) || \ defined(CONFIG_STM32_COMP6)) -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -116,7 +100,6 @@ int stm32_comp_setup(void) } #endif - #if 0 /* COMP driver not implemented yet */ @@ -134,7 +117,6 @@ int stm32_comp_setup(void) return OK; } - #endif /* CONFIG_COMP && (CONFIG_STM32_COMP1 || * CONFIG_STM32_COMP2 * CONFIG_STM32_COMP6) */ From c023d41522496c0049a0a1c2202bab2478f6059c Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 19 Mar 2017 13:47:27 -0600 Subject: [PATCH 50/81] XMC4xxx: Beginning of Ethernet register header file --- arch/arm/src/xmc4/chip/xmc4_ethernet.h | 223 +++++++++++++++++++++++++ 1 file changed, 223 insertions(+) create mode 100644 arch/arm/src/xmc4/chip/xmc4_ethernet.h diff --git a/arch/arm/src/xmc4/chip/xmc4_ethernet.h b/arch/arm/src/xmc4/chip/xmc4_ethernet.h new file mode 100644 index 00000000000..26291fa45ca --- /dev/null +++ b/arch/arm/src/xmc4/chip/xmc4_ethernet.h @@ -0,0 +1,223 @@ +/******************************************************************************************************************** + * arch/arm/src/xmc4/chip/xmc4_ethernet.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Reference: XMC4500 Reference Manual V1.5 2014-07 Microcontrollers. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * May include some logic from sample code provided by Infineon: + * + * Copyright (C) 2011-2015 Infineon Technologies AG. All rights reserved. + * + * Infineon Technologies AG (Infineon) is supplying this software for use with + * Infineon's microcontrollers. This file can be freely distributed within + * development tools that are supporting such microcontrollers. + * + * THIS SOFTWARE IS PROVIDED AS IS. NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, + * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ********************************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_XMC4_CHIP_XMC4_ETHERNET_H +#define __ARCH_ARM_SRC_XMC4_CHIP_XMC4_ETHERNET_H + +/******************************************************************************************************************** + * Included Files + ********************************************************************************************************************/ + +#include + +#include "chip/xmc4_memorymap.h" + +/******************************************************************************************************************** + * Pre-processor Definitions + ********************************************************************************************************************/ + +/* Register Offsets *************************************************************************************************/ + +/* MAC Configuration Registers */ + +#define XMC4_ETH_MAC_CONFIGURATION_OFFSET 0x0000 /* MAC Configuration Register */ +#define XMC4_ETH_MAC_FRAME_FILTER_OFFSET 0x0004 /* MAC Frame Filter */ +#define XMC4_ETH_HASH_TABLE_HIGH_OFFSET 0x0008 /* Hash Table High Register */ +#define XMC4_ETH_HASH_TABLE_LOW_OFFSET 0x000c /* Hash Table Low Register */ +#define XMC4_ETH_GMII_ADDRESS_OFFSET 0x0010 /* MII Address Register */ +#define XMC4_ETH_GMII_DATA_OFFSET 0x0014 /* MII Data Register */ +#define XMC4_ETH_FLOW_CONTROL_OFFSET 0x0018 /* Flow Control Register */ +#define XMC4_ETH_VLAN_TAG_OFFSET 0x001c /* VLAN Tag Register */ +#define XMC4_ETH_VERSION_OFFSET 0x0020 /* Version Register */ +#define XMC4_ETH_DEBUG_OFFSET 0x0024 /* Debug Register */ +#define XMC4_ETH_REMOTE_WAKE_UP_FRAME_FILTER_OFFSET 0x0028 /* Remote Wake Up Frame Filter Register */ +#define XMC4_ETH_PMT_CONTROL_STATUS_OFFSET 0x002c /* PMT Control and Status Register */ +#define XMC4_ETH_INTERRUPT_STATUS_OFFSET 0x0038 /* Interrupt Register */ +#define XMC4_ETH_INTERRUPT_MASK_OFFSET 0x003c /* Interrupt Mask Register */ +#define XMC4_ETH_MAC_ADDRESS0_HIGH_OFFSET 0x0040 /* MAC Address0 High Register */ +#define XMC4_ETH_MAC_ADDRESS0_LOW_OFFSET 0x0044 /* MAC Address0 Low Register */ +#define XMC4_ETH_MAC_ADDRESS1_HIGH_OFFSET 0x0048 /* MAC Address1 High Register */ +#define XMC4_ETH_MAC_ADDRESS1_LOW_OFFSET 0x004c /* MAC Address1 Low Register */ +#define XMC4_ETH_MAC_ADDRESS2_HIGH_OFFSET 0x0050 /* MAC Address2 High Register */ +#define XMC4_ETH_MAC_ADDRESS2_LOW_OFFSET 0x0054 /* MAC Address2 Low Register */ +#define XMC4_ETH_MAC_ADDRESS3_HIGH_OFFSET 0x0058 /* MAC Address3 High Register */ +#define XMC4_ETH_MAC_ADDRESS3_LOW_OFFSET 0x005c /* MAC Address3 Low Register */ + +/* MAC Management Counters */ + +#define XMC4_ETH_MMC_CONTROL_OFFSET 0x0100 /* MMC Control Register */ +#define XMC4_ETH_MMC_RECEIVE_INTERRUPT_OFFSET 0x0104 /* MMC Receive Interrupt Register */ +#define XMC4_ETH_MMC_TRANSMIT_INTERRUPT_OFFSET 0x0108 /* MMC Transmit Interrupt Register */ +#define XMC4_ETH_MMC_RECEIVE_INTERRUPT_MASK_OFFSET 0x010c /* MMC Reveive Interrupt Mask Register */ +#define XMC4_ETH_MMC_TRANSMIT_INTERRUPT_MASK_OFFSET 0x0110 /* MMC Transmit Interrupt Mask Register */ +#define XMC4_ETH_TX_OCTET_COUNT_OFFSET 0x0114 /* Transmit Octet Count for Good and Bad Frames Register */ +#define XMC4_ETH_TX_FRAME_COUNT_OFFSET 0x0118 /* Transmit Frame Count for Goodand Bad Frames Register */ +#define XMC4_ETH_TX_BROADCAST_FRAMES_OFFSET 0x011c /* Transmit Frame Count for Good Broadcast Frames */ +#define XMC4_ETH_TX_MULTICAST_FRAMES_OFFSET 0x0120 /* Transmit Frame Count for Good Multicast Frames */ +#define XMC4_ETH_TX_64OCTETS_FRAMES_OFFSET 0x0124 /* Transmit Octet Count for Good and Bad 64 Byte Frames */ +#define XMC4_ETH_TX_65TO127OCTETS_FRAMES_OFFSET 0x0128 /* Transmit Octet Count for Good and Bad 65 to 127 Bytes Frames */ +#define XMC4_ETH_TX_128TO255OCTETS_FRAMES_OFFSET 0x012c /* Transmit Octet Count for Good and Bad 128 to 255 Bytes Frames */ +#define XMC4_ETH_TX_256TO511OCTETS_FRAMES_OFFSET 0x0130 /* Transmit Octet Count for Good and Bad 256 to 511 Bytes Frames */ +#define XMC4_ETH_TX_512TO1023OCTETS_FRAMES_OFFSET 0x0134 /* Transmit Octet Count for Good and Bad 512 to 1023 Bytes Frames */ +#define XMC4_ETH_TX_1024TOMAXOCTETS_FRAMES_OFFSET 0x0138 /* Transmit Octet Count for Good and Bad 1024 to Maxsize Bytes Frames */ +#define XMC4_ETH_TX_UNICAST_FRAMES_OFFSET 0x013c /* Transmit Frame Count for Good and Bad Unicast Frames */ +#define XMC4_ETH_TX_MULTICAST_FRAMES_OFFSET 0x0140 /* Transmit Frame Count for Good and Bad Multicast Frames */ +#define XMC4_ETH_TX_BROADCAST_FRAMES_OFFSET 0x0144 /* Transmit Frame Count for Good and Bad Broadcast Frames */ +#define XMC4_ETH_TX_UNDERFLOW_ERROR_FRAMES_OFFSET 0x0148 /* Transmit Frame Count for Underflow Error Frames */ +#define XMC4_ETH_TX_SINGLE_COLLISION_FRAMES_OFFSET 0x014c /* Transmit Frame Count for Frames Transmitted after Single Collision */ +#define XMC4_ETH_TX_MULTIPLE_COLLISION_FRAMES_OFFSET 0x0150 /* Transmit Frame Count for Frames Transmitted after Multiple Collision */ +#define XMC4_ETH_TX_DEFERRED_FRAMES_OFFSET 0x0154 /* Tx Deferred Frames Register */ +#define XMC4_ETH_TX_LATE_COLLISION_FRAMES_OFFSET 0x0158 /* Transmit Frame Count for Late Collision Error Frames */ +#define XMC4_ETH_TX_EXCESSIVE_COLLISION_FRAMES_OFFSET 0x015c /* Transmit Frame Count for Excessive Collision Error Frames */ +#define XMC4_ETH_TX_CARRIER_ERROR_FRAMES_OFFSET 0x0160 /* Transmit Frame Count for Carrier Sense Error Frames */ +#define XMC4_ETH_TX_OCTET_COUNT_OFFSET 0x0164 /* Tx Octet Count Good Register */ +#define XMC4_ETH_TX_FRAME_COUNT_OFFSET 0x0168 /* Tx Frame Count Good Register */ +#define XMC4_ETH_TX_EXCESSIVE_DEFERRAL_ERROR_OFFSET 0x016c /* Transmit Frame Count for Excessive Deferral Error Frames */ +#define XMC4_ETH_TX_PAUSE_FRAMES_OFFSET 0x0170 /* Transmit Frame Count for Good PAUSE Frames */ +#define XMC4_ETH_TX_VLAN_FRAMES_OFFSET 0x0174 /* Transmit Frame Count for Good VLAN Frames */ +#define XMC4_ETH_TX_OSIZE_FRAMES_OFFSET 0x0178 /* Transmit Frame Count for Good Oversize Frames */ + +#define XMC4_ETH_RX_FRAMES_COUNT_OFFSET 0x0180 /* Receive Frame Count for Good and Bad Frames */ +#define XMC4_ETH_RX_OCTET_COUNT_OFFSET 0x0184 /* Receive Octet Count for Good and Bad Frames */ +#define XMC4_ETH_RX_OCTET_COUNT_OFFSET 0x0188 /* Rx Octet Count Good Register */ +#define XMC4_ETH_RX_BROADCAST_FRAMES_OFFSET 0x018c /* Receive Frame Count for Good Broadcast Frames */ +#define XMC4_ETH_RX_MULTICAST_FRAMES_OFFSET 0x0190 /* Receive Frame Count for Good Multicast Frames */ +#define XMC4_ETH_RX_CRC_ERROR_FRAMES_OFFSET 0x0194 /* Receive Frame Count for CRC Error Frames */ +#define XMC4_ETH_RX_ALIGNMENT_ERROR_FRAMES_OFFSET 0x0198 /* Receive Frame Count for Alignment Error Frames */ +#define XMC4_ETH_RX_RUNT_ERROR_FRAMES_OFFSET 0x019c /* Receive Frame Count for Runt Error Frames */ +#define XMC4_ETH_RX_JABBER_ERROR_FRAMES_OFFSET 0x01a0 /* Receive Frame Count for Jabber Error Frames */ +#define XMC4_ETH_RX_UNDERSIZE_FRAMES_OFFSET 0x01a4 /* Receive Frame Count for Undersize Frames */ +#define XMC4_ETH_RX_OVERSIZE_FRAMES_OFFSET 0x01a8 /* Rx Oversize Frames Good Register */ +#define XMC4_ETH_RX_64OCTETS_FRAMES_OFFSET 0x01ac /* Receive Frame Count for Good and Bad 64 Byte Frames */ +#define XMC4_ETH_RX_65TO127OCTETS_FRAMES_OFFSET 0x01b0 /* Receive Frame Count for Good and Bad 65 to 127 Bytes Frames */ +#define XMC4_ETH_RX_128TO255OCTETS_FRAMES_OFFSET 0x01b4 /* Receive Frame Count for Good and Bad 128 to 255 Bytes Frames */ +#define XMC4_ETH_RX_256TO511OCTETS_FRAMES_OFFSET 0x01b8 /* Receive Frame Count for Good and Bad 256 to 511 Bytes Frames */ +#define XMC4_ETH_RX_512TO1023OCTETS_FRAMES_OFFSET 0x01bc /* Receive Frame Count for Good and Bad 512 to 1,023 Bytes Frames */ +#define XMC4_ETH_RX_1024TOMAXOCTETS_FRAMES_OFFSET 0x01c0 /* Receive Frame Count for Good and Bad 1,024 to Maxsize Bytes Frames */ +#define XMC4_ETH_RX_UNICAST_FRAMES_OFFSET 0x01c4 /* Receive Frame Count for Good Unicast Frames */ +#define XMC4_ETH_RX_LENGTH_ERROR_FRAMES_OFFSET 0x01c8 /* Receive Frame Count for Length Error Frames */ +#define XMC4_ETH_RX_OUT_OF_RANGE_TYPE_FRAMES_OFFSET 0x01cc /* Receive Frame Count for Out of Range Frames */ +#define XMC4_ETH_RX_PAUSE_FRAMES_OFFSET 0x01d0 /* Receive Frame Count for PAUSE Frames */ +#define XMC4_ETH_RX_FIFO_OVERFLOW_FRAMES_OFFSET 0x01d4 /* Receive Frame Count for FIFO Overflow Frames */ +#define XMC4_ETH_RX_VLAN_FRAMES_OFFSET 0x01d8 /* Receive Frame Count for Good and Bad VLAN Frames */ +#define XMC4_ETH_RX_WATCHDOG_ERROR_FRAMES_OFFSET 0x01dc /* Receive Frame Count for Watchdog Error Frames */ +#define XMC4_ETH_RX_RECEIVE_ERROR_FRAMES_OFFSET 0x01e0 /* Receive Frame Count for Receive Error Frames */ +#define XMC4_ETH_RX_CONTROL_FRAMES_OFFSET 0x01e4 /* Receive Frame Count for Good Control Frames Frames */ +#define XMC4_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_OFFSET 0x0200 /* MMC Receive Checksum Offload Interrupt Mask Register */ +#define XMC4_ETH_MMC_IPC_RECEIVE_INTERRUPT_OFFSET 0x0208 /* MMC Receive Checksum Offload Interrupt Register */ +#define XMC4_ETH_RXIPV4_GOOD_FRAMES_OFFSET 0x0210 /* RxIPv4 Good Frames Register */ +#define XMC4_ETH_RXIPV4_HEADER_ERROR_FRAMES_OFFSET 0x0214 /* Receive IPV4 Header Error Frame Counter Register */ +#define XMC4_ETH_RXIPV4_NO_PAYLOAD_FRAMES_OFFSET 0x0218 /* Receive IPV4 No Payload Frame Counter Register */ +#define XMC4_ETH_RXIPV4_FRAGMENTED_FRAMES_OFFSET 0x021c /* Receive IPV4 Fragmented Frame Counter Register */ +#define XMC4_ETH_RXIPV4_UDP_CHECKSUM_DISABLED_FRAMES_OFFSET 0x0220 /* Receive IPV4 UDP Checksum Disabled Frame Counter Register */ +#define XMC4_ETH_RXIPV6_GOOD_FRAMES_OFFSET 0x0224 /* RxIPv6 Good Frames Register */ +#define XMC4_ETH_RXIPV6_HEADER_ERROR_FRAMES_OFFSET 0x0228 /* Receive IPV6 Header Error Frame Counter Register */ +#define XMC4_ETH_RXIPV6_NO_PAYLOAD_FRAMES_OFFSET 0x022c /* Receive IPV6 No Payload Frame Counter Register */ +#define XMC4_ETH_RXUDP_GOOD_FRAMES_OFFSET 0x0230 /* RxUDP Good Frames Register */ +#define XMC4_ETH_RXUDP_ERROR_FRAMES_OFFSET 0x0234 /* RxUDP Error Frames Register */ +#define XMC4_ETH_RXTCP_GOOD_FRAMES_OFFSET 0x0238 /* RxTCP Good Frames Register */ +#define XMC4_ETH_RXTCP_ERROR_FRAMES_OFFSET 0x023c /* RxTCP Error Frames Register */ +#define XMC4_ETH_RXICMP_GOOD_FRAMES_OFFSET 0x0240 /* RxICMP Good Frames Register */ +#define XMC4_ETH_RXICMP_ERROR_FRAMES_OFFSET 0x0244 /* RxICMP Error Frames Register */ +#define XMC4_ETH_RXIPV4_GOOD_OCTETS_OFFSET 0x0250 /* RxIPv4 Good Octets Register */ +#define XMC4_ETH_RXIPV4_HEADER_ERROR_OCTETS_OFFSET 0x0254 /* Receive IPV4 Header Error Octet Counter Register */ +#define XMC4_ETH_RXIPV4_NO_PAYLOAD_OCTETS_OFFSET 0x0258 /* Receive IPV4 No Payload Octet Counter Register */ +#define XMC4_ETH_RXIPV4_FRAGMENTED_OCTETS_OFFSET 0x025c /* Receive IPV4 Fragmented Octet Counter Register */ +#define XMC4_ETH_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_OFFSET 0x0260 /* Receive IPV4 Fragmented Octet Counter Register */ +#define XMC4_ETH_RXIPV6_GOOD_OCTETS_OFFSET 0x0264 /* RxIPv6 Good Octets Register */ +#define XMC4_ETH_RXIPV6_HEADER_ERROR_OCTETS_OFFSET 0x0268 /* Receive IPV6 Header Error Octet Counter Register */ +#define XMC4_ETH_RXIPV6_NO_PAYLOAD_OCTETS_OFFSET 0x026c /* Receive IPV6 No Payload Octet Counter Register */ +#define XMC4_ETH_RXUDP_GOOD_OCTETS_OFFSET 0x0270 /* Receive UDP Good Octets Register */ +#define XMC4_ETH_RXUDP_ERROR_OCTETS_OFFSET 0x0274 /* Receive UDP Error Octets Register */ +#define XMC4_ETH_RXTCP_GOOD_OCTETS_OFFSET 0x0278 /* Receive TCP Good Octets Register */ +#define XMC4_ETH_RXTCP_ERROR_OCTETS_OFFSET 0x027c /* Receive TCP Error Octets Register */ +#define XMC4_ETH_RXICMP_GOOD_OCTETS_OFFSET 0x0280 /* Receive ICMP Good Octets Register */ +#define XMC4_ETH_RXICMP_ERROR_OCTETS_OFFSET 0x0284 /* Receive ICMP Error Octets Register */ + +/* System Time Registers */ + +#define XMC4_ETH_TIMESTAMP_CONTROL_OFFSET 0x0700 /* Timestamp Control Register */ +#define XMC4_ETH_SUB_SECOND_INCREMENT_OFFSET 0x0704 /* Sub-Second Increment Register */ +#define XMC4_ETH_SYSTEM_TIME_SECONDS_OFFSET 0x0708 /* System Time - Seconds Register */ +#define XMC4_ETH_SYSTEM_TIME_NANOSECONDS_OFFSET 0x070c /* System Time Nanoseconds Register */ +#define XMC4_ETH_SYSTEM_TIME_SECONDS_UPDATE_OFFSET 0x0710 /* System Time - Seconds Update Register */ +#define XMC4_ETH_SYSTEM_TIME_NANOSECONDS_UPDATE_OFFSET 0x0714 /* System Time Nanoseconds Update Register */ +#define XMC4_ETH_TIMESTAMP_ADDEND_OFFSET 0x0718 /* Timestamp Addend Register */ +#define XMC4_ETH_TARGET_TIME_SECONDS_OFFSET 0x071c /* Target Time Seconds Register */ +#define XMC4_ETH_TARGET_TIME_NANOSECONDS_OFFSET 0x0720 /* Target Time Nanoseconds Register */ +#define XMC4_ETH_SYSTEM_TIME_HIGHER_WORD_SECONDS_OFFSET 0x0724 /* System Time - Higher Word Seconds Register */ +#define XMC4_ETH_TIMESTAMP_STATUS_OFFSET 0x0728 /* Timestamp Status Register */ + +/* DMA Registers*/ + +#define XMC4_ETH_BUS_MODE_OFFSET 0x1000 /* Bus Mode Register */ +#define XMC4_ETH_TRANSMIT_POLL_DEMAND_OFFSET 0x1004 /* Transmit Poll Demand Register */ +#define XMC4_ETH_RECEIVE_POLL_DEMAND_OFFSET 0x1008 /* Receive Poll Demand Register */ +#define XMC4_ETH_RECEIVE_DESCRIPTOR_LIST_ADDRESS_OFFSET 0x100c /* Receive Descriptor Address Register */ +#define XMC4_ETH_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_OFFSET 0x1010 /* Transmit descripter Address Register */ +#define XMC4_ETH_STATUS_OFFSET 0x1014 /* Status Register */ +#define XMC4_ETH_OPERATION_MODE_OFFSET 0x1018 /* Operation Mode Register */ +#define XMC4_ETH_INTERRUPT_ENABLE_OFFSET 0x101c /* Interrupt Enable Register */ +#define XMC4_ETH_MISSED_FRAME_BUFFER_OVERFLOW_COUNTER_OFFSET 0x1020 /* Missed Frame and Buffer Overflow Counter Register */ +#define XMC4_ETH_RECEIVE_INTERRUPT_WATCHDOG_TIMER_OFFSET 0x1024 /* Receive Interrupt Watchdog Timer Register */ +#define XMC4_ETH_AHB_STATUS_OFFSET 0x102c /* AHB Status Register */ +#define XMC4_ETH_CURRENT_HOST_TRANSMIT_DESCRIPTOR_OFFSET 0x1048 /* Current Host Transmit Descriptor Register */ +#define XMC4_ETH_CURRENT_HOST_RECEIVE_DESCRIPTOR_OFFSET 0x104c /* Current Host Receive Descriptor Register */ +#define XMC4_ETH_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS_OFFSET 0x1050 /* Current Host Transmit Buffer Address Register */ +#define XMC4_ETH_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS_OFFSET 0x1054 /* Current Host Receive Buffer Address Register */ +#define XMC4_ETH_HW_FEATURE_OFFSET 0x1058 /* HW Feature Register */ + +/* Register Addresses ***********************************************************************************************/ + +/* Register Bit-Field Definitions ***********************************************************************************/ + + +#endif /* __ARCH_ARM_SRC_XMC4_CHIP_XMC4_ETHERNET_H */ From e1e4af74542a51ff8a7f9403194d31a274e195b2 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 19 Mar 2017 16:25:46 -0600 Subject: [PATCH 51/81] XMC4xxx: More Ethernet definitions. --- arch/arm/src/xmc4/chip/xmc4_ethernet.h | 449 ++++++++++++++++++++++++- arch/arm/src/xmc4/xmc4_allocateheap.c | 12 - 2 files changed, 438 insertions(+), 23 deletions(-) diff --git a/arch/arm/src/xmc4/chip/xmc4_ethernet.h b/arch/arm/src/xmc4/chip/xmc4_ethernet.h index 26291fa45ca..22c163b661f 100644 --- a/arch/arm/src/xmc4/chip/xmc4_ethernet.h +++ b/arch/arm/src/xmc4/chip/xmc4_ethernet.h @@ -98,10 +98,10 @@ #define XMC4_ETH_MMC_TRANSMIT_INTERRUPT_OFFSET 0x0108 /* MMC Transmit Interrupt Register */ #define XMC4_ETH_MMC_RECEIVE_INTERRUPT_MASK_OFFSET 0x010c /* MMC Reveive Interrupt Mask Register */ #define XMC4_ETH_MMC_TRANSMIT_INTERRUPT_MASK_OFFSET 0x0110 /* MMC Transmit Interrupt Mask Register */ -#define XMC4_ETH_TX_OCTET_COUNT_OFFSET 0x0114 /* Transmit Octet Count for Good and Bad Frames Register */ -#define XMC4_ETH_TX_FRAME_COUNT_OFFSET 0x0118 /* Transmit Frame Count for Goodand Bad Frames Register */ -#define XMC4_ETH_TX_BROADCAST_FRAMES_OFFSET 0x011c /* Transmit Frame Count for Good Broadcast Frames */ -#define XMC4_ETH_TX_MULTICAST_FRAMES_OFFSET 0x0120 /* Transmit Frame Count for Good Multicast Frames */ +#define XMC4_ETH_TX_OCTET_OODBAD_COUNT_GOFFSET 0x0114 /* Transmit Octet Count for Good and Bad Frames Register */ +#define XMC4_ETH_TX_FRAME_GOODBAD_COUNT_OFFSET 0x0118 /* Transmit Frame Count for Good and Bad Frames Register */ +#define XMC4_ETH_TX_BROADCAST_GOOD_FRAMES_OFFSET 0x011c /* Transmit Frame Count for Good Broadcast Frames */ +#define XMC4_ETH_TX_MULTICAST_GOOD_FRAMES_OFFSET 0x0120 /* Transmit Frame Count for Good Multicast Frames */ #define XMC4_ETH_TX_64OCTETS_FRAMES_OFFSET 0x0124 /* Transmit Octet Count for Good and Bad 64 Byte Frames */ #define XMC4_ETH_TX_65TO127OCTETS_FRAMES_OFFSET 0x0128 /* Transmit Octet Count for Good and Bad 65 to 127 Bytes Frames */ #define XMC4_ETH_TX_128TO255OCTETS_FRAMES_OFFSET 0x012c /* Transmit Octet Count for Good and Bad 128 to 255 Bytes Frames */ @@ -109,8 +109,8 @@ #define XMC4_ETH_TX_512TO1023OCTETS_FRAMES_OFFSET 0x0134 /* Transmit Octet Count for Good and Bad 512 to 1023 Bytes Frames */ #define XMC4_ETH_TX_1024TOMAXOCTETS_FRAMES_OFFSET 0x0138 /* Transmit Octet Count for Good and Bad 1024 to Maxsize Bytes Frames */ #define XMC4_ETH_TX_UNICAST_FRAMES_OFFSET 0x013c /* Transmit Frame Count for Good and Bad Unicast Frames */ -#define XMC4_ETH_TX_MULTICAST_FRAMES_OFFSET 0x0140 /* Transmit Frame Count for Good and Bad Multicast Frames */ -#define XMC4_ETH_TX_BROADCAST_FRAMES_OFFSET 0x0144 /* Transmit Frame Count for Good and Bad Broadcast Frames */ +#define XMC4_ETH_TX_MULTICAST_GOODBAD_FRAMES_OFFSET 0x0140 /* Transmit Frame Count for Good and Bad Multicast Frames */ +#define XMC4_ETH_TX_BROADCAST_GOODBAD_FRAMES_OFFSET 0x0144 /* Transmit Frame Count for Good and Bad Broadcast Frames */ #define XMC4_ETH_TX_UNDERFLOW_ERROR_FRAMES_OFFSET 0x0148 /* Transmit Frame Count for Underflow Error Frames */ #define XMC4_ETH_TX_SINGLE_COLLISION_FRAMES_OFFSET 0x014c /* Transmit Frame Count for Frames Transmitted after Single Collision */ #define XMC4_ETH_TX_MULTIPLE_COLLISION_FRAMES_OFFSET 0x0150 /* Transmit Frame Count for Frames Transmitted after Multiple Collision */ @@ -118,16 +118,15 @@ #define XMC4_ETH_TX_LATE_COLLISION_FRAMES_OFFSET 0x0158 /* Transmit Frame Count for Late Collision Error Frames */ #define XMC4_ETH_TX_EXCESSIVE_COLLISION_FRAMES_OFFSET 0x015c /* Transmit Frame Count for Excessive Collision Error Frames */ #define XMC4_ETH_TX_CARRIER_ERROR_FRAMES_OFFSET 0x0160 /* Transmit Frame Count for Carrier Sense Error Frames */ -#define XMC4_ETH_TX_OCTET_COUNT_OFFSET 0x0164 /* Tx Octet Count Good Register */ -#define XMC4_ETH_TX_FRAME_COUNT_OFFSET 0x0168 /* Tx Frame Count Good Register */ +#define XMC4_ETH_TX_OCTET_GOOD_COUNT_OFFSET 0x0164 /* Tx Octet Count Good Register */ +#define XMC4_ETH_TX_FRAME_GOOD_COUNT_OFFSET 0x0168 /* Tx Frame Count Good Register */ #define XMC4_ETH_TX_EXCESSIVE_DEFERRAL_ERROR_OFFSET 0x016c /* Transmit Frame Count for Excessive Deferral Error Frames */ #define XMC4_ETH_TX_PAUSE_FRAMES_OFFSET 0x0170 /* Transmit Frame Count for Good PAUSE Frames */ #define XMC4_ETH_TX_VLAN_FRAMES_OFFSET 0x0174 /* Transmit Frame Count for Good VLAN Frames */ #define XMC4_ETH_TX_OSIZE_FRAMES_OFFSET 0x0178 /* Transmit Frame Count for Good Oversize Frames */ - #define XMC4_ETH_RX_FRAMES_COUNT_OFFSET 0x0180 /* Receive Frame Count for Good and Bad Frames */ -#define XMC4_ETH_RX_OCTET_COUNT_OFFSET 0x0184 /* Receive Octet Count for Good and Bad Frames */ -#define XMC4_ETH_RX_OCTET_COUNT_OFFSET 0x0188 /* Rx Octet Count Good Register */ +#define XMC4_ETH_RX_OCTET_GOODBAD_COUNT_OFFSET 0x0184 /* Receive Octet Count for Good and Bad Frames */ +#define XMC4_ETH_RX_OCTET_GOOD_COUNT_OFFSET 0x0188 /* Rx Octet Count Good Register */ #define XMC4_ETH_RX_BROADCAST_FRAMES_OFFSET 0x018c /* Receive Frame Count for Good Broadcast Frames */ #define XMC4_ETH_RX_MULTICAST_FRAMES_OFFSET 0x0190 /* Receive Frame Count for Good Multicast Frames */ #define XMC4_ETH_RX_CRC_ERROR_FRAMES_OFFSET 0x0194 /* Receive Frame Count for CRC Error Frames */ @@ -217,7 +216,435 @@ /* Register Addresses ***********************************************************************************************/ +/* MAC Configuration Registers */ + +#define XMC4_ETH_MAC_CONFIGURATION (XMC4_ETH0_BASE+XMC4_ETH_MAC_CONFIGURATION_OFFSET) +#define XMC4_ETH_MAC_FRAME_FILTER (XMC4_ETH0_BASE+XMC4_ETH_MAC_FRAME_FILTER_OFFSET) +#define XMC4_ETH_HASH_TABLE_HIGH (XMC4_ETH0_BASE+XMC4_ETH_HASH_TABLE_LOW_OFFSET) +#define XMC4_ETH_GMII_ADDRESS (XMC4_ETH0_BASE+XMC4_ETH_GMII_ADDRESS_OFFSET) +#define XMC4_ETH_GMII_DATA (XMC4_ETH0_BASE+XMC4_ETH_GMII_DATA_OFFSET) +#define XMC4_ETH_FLOW_CONTROL (XMC4_ETH0_BASE+XMC4_ETH_FLOW_CONTROL_OFFSET) +#define XMC4_ETH_VLAN_TAG (XMC4_ETH0_BASE+XMC4_ETH_VLAN_TAG_OFFSET) +#define XMC4_ETH_VERSION (XMC4_ETH0_BASE+XMC4_ETH_VERSION_OFFSET) +#define XMC4_ETH_DEBUG (XMC4_ETH0_BASE+XMC4_ETH_DEBUG_OFFSET) +#define XMC4_ETH_REMOTE_WAKE_UP_FRAME_FILTER (XMC4_ETH0_BASE+XMC4_ETH_REMOTE_WAKE_UP_FRAME_FILTER_OFFSET) +#define XMC4_ETH_PMT_CONTROL_STATUS (XMC4_ETH0_BASE+XMC4_ETH_PMT_CONTROL_STATUS_OFFSET) +#define XMC4_ETH_INTERRUPT_STATUS (XMC4_ETH0_BASE+XMC4_ETH_INTERRUPT_STATUS_OFFSET) +#define XMC4_ETH_INTERRUPT_MASK (XMC4_ETH0_BASE+XMC4_ETH_INTERRUPT_MASK_OFFSET) +#define XMC4_ETH_MAC_ADDRESS0_HIGH (XMC4_ETH0_BASE+XMC4_ETH_MAC_ADDRESS0_HIGH_OFFSET) +#define XMC4_ETH_MAC_ADDRESS0_LOW (XMC4_ETH0_BASE+XMC4_ETH_MAC_ADDRESS0_LOW_OFFSET) +#define XMC4_ETH_MAC_ADDRESS1_HIGH (XMC4_ETH0_BASE+XMC4_ETH_MAC_ADDRESS1_HIGH_OFFSET) +#define XMC4_ETH_MAC_ADDRESS1_LOW (XMC4_ETH0_BASE+XMC4_ETH_MAC_ADDRESS1_LOW_OFFSET) +#define XMC4_ETH_MAC_ADDRESS2_HIGH (XMC4_ETH0_BASE+XMC4_ETH_MAC_ADDRESS2_HIGH_OFFSET) +#define XMC4_ETH_MAC_ADDRESS2_LOW (XMC4_ETH0_BASE+XMC4_ETH_MAC_ADDRESS2_LOW_OFFSET) +#define XMC4_ETH_MAC_ADDRESS3_HIGH (XMC4_ETH0_BASE+XMC4_ETH_MAC_ADDRESS3_HIGH_OFFSET) +#define XMC4_ETH_MAC_ADDRESS3_LOW (XMC4_ETH0_BASE+XMC4_ETH_MAC_ADDRESS3_LOW_OFFSET) + +/* MAC Management Counters */ + +#define XMC4_ETH_MMC_CONTROL (XMC4_ETH0_BASE+XMC4_ETH_MMC_CONTROL_OFFSET) +#define XMC4_ETH_MMC_RECEIVE_INTERRUPT (XMC4_ETH0_BASE+XMC4_ETH_MMC_RECEIVE_INTERRUPT_OFFSET) +#define XMC4_ETH_MMC_TRANSMIT_INTERRUPT (XMC4_ETH0_BASE+XMC4_ETH_MMC_TRANSMIT_INTERRUPT_OFFSET) +#define XMC4_ETH_MMC_RECEIVE_INTERRUPT_MASK (XMC4_ETH0_BASE+XMC4_ETH_MMC_RECEIVE_INTERRUPT_MASK_OFFSET) +#define XMC4_ETH_MMC_TRANSMIT_INTERRUPT_MASK (XMC4_ETH0_BASE+XMC4_ETH_MMC_TRANSMIT_INTERRUPT_MASK_OFFSET) +#define XMC4_ETH_TX_OCTET_GOODBAD_COUNT (XMC4_ETH0_BASE+XMC4_ETH_TX_OCTET_GOODBAD_COUNT_OFFSET) +#define XMC4_ETH_TX_FRAME_GOODBAD_COUNT (XMC4_ETH0_BASE+XMC4_ETH_TX_FRAME_GOODBAD_COUNT_OFFSET) +#define XMC4_ETH_TX_BROADCAST_GOOD_FRAMES (XMC4_ETH0_BASE+XMC4_ETH_TX_BROADCAST_GOOD_FRAMES_OFFSET) +#define XMC4_ETH_TX_MULTICAST_GOOD_FRAMES (XMC4_ETH0_BASE+XMC4_ETH_TX_MULTICAST_GOOD_FRAMES_OFFSET) +#define XMC4_ETH_TX_64OCTETS_FRAMES (XMC4_ETH0_BASE+XMC4_ETH_TX_64OCTETS_FRAMES_OFFSET) +#define XMC4_ETH_TX_65TO127OCTETS_FRAMES (XMC4_ETH0_BASE+XMC4_ETH_TX_65TO127OCTETS_FRAMES_OFFSET) +#define XMC4_ETH_TX_128TO255OCTETS_FRAMES (XMC4_ETH0_BASE+XMC4_ETH_TX_128TO255OCTETS_FRAMES_OFFSET) +#define XMC4_ETH_TX_256TO511OCTETS_FRAMES (XMC4_ETH0_BASE+XMC4_ETH_TX_256TO511OCTETS_FRAMES_OFFSET) +#define XMC4_ETH_TX_512TO1023OCTETS_FRAMES (XMC4_ETH0_BASE+XMC4_ETH_TX_512TO1023OCTETS_FRAMES_OFFSET) +#define XMC4_ETH_TX_1024TOMAXOCTETS_FRAMES (XMC4_ETH0_BASE+XMC4_ETH_TX_1024TOMAXOCTETS_FRAMES_OFFSET) +#define XMC4_ETH_TX_UNICAST_FRAMES (XMC4_ETH0_BASE+XMC4_ETH_TX_UNICAST_FRAMES_OFFSET) +#define XMC4_ETH_TX_MULTICAST_GOODBAD_FRAMES (XMC4_ETH0_BASE+XMC4_ETH_TX_MULTICAST_GOODBAD_FRAMES_OFFSET) +#define XMC4_ETH_TX_BROADCAST_GOODBAD_FRAMES (XMC4_ETH0_BASE+XMC4_ETH_TX_BROADCAST_GOODBAD_FRAMES_OFFSET) +#define XMC4_ETH_TX_UNDERFLOW_ERROR_FRAMES (XMC4_ETH0_BASE+XMC4_ETH_TX_UNDERFLOW_ERROR_FRAMES_OFFSET) +#define XMC4_ETH_TX_SINGLE_COLLISION_FRAMES (XMC4_ETH0_BASE+XMC4_ETH_TX_SINGLE_COLLISION_FRAMES_OFFSET) +#define XMC4_ETH_TX_MULTIPLE_COLLISION_FRAMES (XMC4_ETH0_BASE+XMC4_ETH_TX_MULTIPLE_COLLISION_FRAMES_OFFSET) +#define XMC4_ETH_TX_DEFERRED_FRAMES (XMC4_ETH0_BASE+XMC4_ETH_TX_DEFERRED_FRAMES_OFFSET) +#define XMC4_ETH_TX_LATE_COLLISION_FRAMES (XMC4_ETH0_BASE+XMC4_ETH_TX_LATE_COLLISION_FRAMES_OFFSET) +#define XMC4_ETH_TX_EXCESSIVE_COLLISION_FRAMES (XMC4_ETH0_BASE+XMC4_ETH_TX_EXCESSIVE_COLLISION_FRAMES_OFFSET) +#define XMC4_ETH_TX_CARRIER_ERROR_FRAMES (XMC4_ETH0_BASE+XMC4_ETH_TX_CARRIER_ERROR_FRAMES_OFFSET) +#define XMC4_ETH_TX_OCTET_GOOD_COUNT (XMC4_ETH0_BASE+XMC4_ETH_TX_OCTET_GOOD_COUNT_OFFSET) +#define XMC4_ETH_TX_FRAME_GOOD_COUNT (XMC4_ETH0_BASE+XMC4_ETH_TX_FRAME_GOOD_COUNT_OFFSET) +#define XMC4_ETH_TX_EXCESSIVE_DEFERRAL_ERROR (XMC4_ETH0_BASE+XMC4_ETH_TX_EXCESSIVE_DEFERRAL_ERROR_OFFSET) +#define XMC4_ETH_TX_PAUSE_FRAMES (XMC4_ETH0_BASE+XMC4_ETH_TX_PAUSE_FRAMES_OFFSET) +#define XMC4_ETH_TX_VLAN_FRAMES (XMC4_ETH0_BASE+XMC4_ETH_TX_VLAN_FRAMES_OFFSET) +#define XMC4_ETH_TX_OSIZE_FRAMES (XMC4_ETH0_BASE+XMC4_ETH_TX_OSIZE_FRAMES_OFFSET) +#define XMC4_ETH_RX_FRAMES_COUNT (XMC4_ETH0_BASE+XMC4_ETH_RX_FRAMES_COUNT_OFFSET) +#define XMC4_ETH_RX_OCTET_GOODBAD_COUNT (XMC4_ETH0_BASE+XMC4_ETH_RX_OCTET_GOODBAD_COUNT_OFFSET) +#define XMC4_ETH_RX_OCTET_GOOD_COUNT (XMC4_ETH0_BASE+XMC4_ETH_RX_OCTET_GOOD_COUNT_OFFSET) +#define XMC4_ETH_RX_BROADCAST_FRAMES (XMC4_ETH0_BASE+XMC4_ETH_RX_BROADCAST_FRAMES_OFFSET) +#define XMC4_ETH_RX_MULTICAST_FRAMES (XMC4_ETH0_BASE+XMC4_ETH_RX_MULTICAST_FRAMES_OFFSET) +#define XMC4_ETH_RX_CRC_ERROR_FRAMES (XMC4_ETH0_BASE+XMC4_ETH_RX_CRC_ERROR_FRAMES_OFFSET) +#define XMC4_ETH_RX_ALIGNMENT_ERROR (XMC4_ETH0_BASE+XMC4_ETH_RX_ALIGNMENT_ERROR_FRAMES_OFFSET) +#define XMC4_ETH_RX_RUNT_ERROR_FRAMES (XMC4_ETH0_BASE+XMC4_ETH_RX_RUNT_ERROR_FRAMES_OFFSET) +#define XMC4_ETH_RX_JABBER_ERROR_FRAMES (XMC4_ETH0_BASE+XMC4_ETH_RX_JABBER_ERROR_FRAMES_OFFSET) +#define XMC4_ETH_RX_UNDERSIZE_FRAMES (XMC4_ETH0_BASE+XMC4_ETH_RX_UNDERSIZE_FRAMES_OFFSET) +#define XMC4_ETH_RX_OVERSIZE_FRAMES (XMC4_ETH0_BASE+XMC4_ETH_RX_OVERSIZE_FRAMES_OFFSET) +#define XMC4_ETH_RX_64OCTETS_FRAMES (XMC4_ETH0_BASE+XMC4_ETH_RX_64OCTETS_FRAMES_OFFSET) +#define XMC4_ETH_RX_65TO127OCTETS_FRAMES (XMC4_ETH0_BASE+XMC4_ETH_RX_65TO127OCTETS_FRAMES_OFFSET) +#define XMC4_ETH_RX_128TO255OCTETS_FRAMES (XMC4_ETH0_BASE+XMC4_ETH_RX_128TO255OCTETS_FRAMES_OFFSET) +#define XMC4_ETH_RX_256TO511OCTETS_FRAMES (XMC4_ETH0_BASE+XMC4_ETH_RX_256TO511OCTETS_FRAMES_OFFSET) +#define XMC4_ETH_RX_512TO1023OCTETS_FRAMES (XMC4_ETH0_BASE+XMC4_ETH_RX_512TO1023OCTETS_FRAMES_OFFSET) +#define XMC4_ETH_RX_1024TOMAXOCTETS_FRAMES (XMC4_ETH0_BASE+XMC4_ETH_RX_1024TOMAXOCTETS_FRAMES_OFFSET) +#define XMC4_ETH_RX_UNICAST_FRAMES (XMC4_ETH0_BASE+XMC4_ETH_RX_UNICAST_FRAMES_OFFSET) +#define XMC4_ETH_RX_LENGTH_ERROR (XMC4_ETH0_BASE+XMC4_ETH_RX_LENGTH_ERROR_FRAMES_OFFSET) +#define XMC4_ETH_RX_OUT_OF_RANGE_TYPE_FRAMES (XMC4_ETH0_BASE+XMC4_ETH_RX_OUT_OF_RANGE_TYPE_FRAMES_OFFSET) +#define XMC4_ETH_RX_PAUSE_FRAMES (XMC4_ETH0_BASE+XMC4_ETH_RX_PAUSE_FRAMES_OFFSET) +#define XMC4_ETH_RX_FIFO_OVERFLOW_FRAMES (XMC4_ETH0_BASE+XMC4_ETH_RX_FIFO_OVERFLOW_FRAMES_OFFSET) +#define XMC4_ETH_RX_VLAN_FRAMES (XMC4_ETH0_BASE+XMC4_ETH_RX_VLAN_FRAMES_OFFSET) +#define XMC4_ETH_RX_WATCHDOG_ERROR_FRAMES (XMC4_ETH0_BASE+XMC4_ETH_RX_WATCHDOG_ERROR_FRAMES_OFFSET) +#define XMC4_ETH_RX_RECEIVE_ERROR_FRAMES (XMC4_ETH0_BASE+XMC4_ETH_RX_RECEIVE_ERROR_FRAMES_OFFSET) +#define XMC4_ETH_RX_CONTROL_FRAMES (XMC4_ETH0_BASE+XMC4_ETH_RX_CONTROL_FRAMES_OFFSET) +#define XMC4_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK (XMC4_ETH0_BASE+XMC4_ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_OFFSET) +#define XMC4_ETH_MMC_IPC_RECEIVE_INTERRUPT (XMC4_ETH0_BASE+XMC4_ETH_MMC_IPC_RECEIVE_INTERRUPT_OFFSET) +#define XMC4_ETH_RXIPV4_GOOD_FRAMES (XMC4_ETH0_BASE+XMC4_ETH_RXIPV4_GOOD_FRAMES_OFFSET) +#define XMC4_ETH_RXIPV4_HEADER_ERROR_FRAMES (XMC4_ETH0_BASE+XMC4_ETH_RXIPV4_HEADER_ERROR_FRAMES_OFFSET) +#define XMC4_ETH_RXIPV4_NO_PAYLOAD_FRAMES (XMC4_ETH0_BASE+XMC4_ETH_RXIPV4_NO_PAYLOAD_FRAMES_OFFSET) +#define XMC4_ETH_RXIPV4_FRAGMENTED_FRAMES (XMC4_ETH0_BASE+XMC4_ETH_RXIPV4_FRAGMENTED_FRAMES_OFFSET) +#define XMC4_ETH_RXIPV4_UDP_CHECKSUM_DISABLED_FRAMES (XMC4_ETH0_BASE+XMC4_ETH_RXIPV4_UDP_CHECKSUM_DISABLED_FRAMES_OFFSET) +#define XMC4_ETH_RXIPV6_GOOD_FRAMES (XMC4_ETH0_BASE+XMC4_ETH_RXIPV6_GOOD_FRAMES_OFFSET) +#define XMC4_ETH_RXIPV6_HEADER_ERROR_FRAMES (XMC4_ETH0_BASE+XMC4_ETH_RXIPV6_HEADER_ERROR_FRAMES_OFFSET) +#define XMC4_ETH_RXIPV6_NO_PAYLOAD_FRAMES (XMC4_ETH0_BASE+XMC4_ETH_RXIPV6_NO_PAYLOAD_FRAMES_OFFSET) +#define XMC4_ETH_RXUDP_GOOD_FRAMES (XMC4_ETH0_BASE+XMC4_ETH_RXUDP_GOOD_FRAMES_OFFSET) +#define XMC4_ETH_RXUDP_ERROR_FRAMES (XMC4_ETH0_BASE+XMC4_ETH_RXUDP_ERROR_FRAMES_OFFSET) +#define XMC4_ETH_RXTCP_GOOD_FRAMES (XMC4_ETH0_BASE+XMC4_ETH_RXTCP_GOOD_FRAMES_OFFSET) +#define XMC4_ETH_RXTCP_ERROR_FRAMES (XMC4_ETH0_BASE+XMC4_ETH_RXTCP_ERROR_FRAMES_OFFSET) +#define XMC4_ETH_RXICMP_GOOD_FRAMES (XMC4_ETH0_BASE+XMC4_ETH_RXICMP_GOOD_FRAMES_OFFSET) +#define XMC4_ETH_RXICMP_ERROR_FRAMES (XMC4_ETH0_BASE+XMC4_ETH_RXICMP_ERROR_FRAMES_OFFSET) +#define XMC4_ETH_RXIPV4_GOOD_OCTETS (XMC4_ETH0_BASE+XMC4_ETH_RXIPV4_GOOD_OCTETS_OFFSET) +#define XMC4_ETH_RXIPV4_HEADER_ERROR_OCTETS (XMC4_ETH0_BASE+XMC4_ETH_RXIPV4_HEADER_ERROR_OCTETS_OFFSET) +#define XMC4_ETH_RXIPV4_NO_PAYLOAD_OCTETS (XMC4_ETH0_BASE+XMC4_ETH_RXIPV4_NO_PAYLOAD_OCTETS_OFFSET) +#define XMC4_ETH_RXIPV4_FRAGMENTED_OCTETS (XMC4_ETH0_BASE+XMC4_ETH_RXIPV4_FRAGMENTED_OCTETS_OFFSET) +#define XMC4_ETH_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS (XMC4_ETH0_BASE+XMC4_ETH_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_OFFSET) +#define XMC4_ETH_RXIPV6_GOOD_OCTETS (XMC4_ETH0_BASE+XMC4_ETH_RXIPV6_GOOD_OCTETS_OFFSET) +#define XMC4_ETH_RXIPV6_HEADER_ERROR_OCTETS (XMC4_ETH0_BASE+XMC4_ETH_RXIPV6_HEADER_ERROR_OCTETS_OFFSET) +#define XMC4_ETH_RXIPV6_NO_PAYLOAD_OCTETS (XMC4_ETH0_BASE+XMC4_ETH_RXIPV6_NO_PAYLOAD_OCTETS_OFFSET) +#define XMC4_ETH_RXUDP_GOOD_OCTETS (XMC4_ETH0_BASE+XMC4_ETH_RXUDP_GOOD_OCTETS_OFFSET) +#define XMC4_ETH_RXUDP_ERROR_OCTETS (XMC4_ETH0_BASE+XMC4_ETH_RXUDP_ERROR_OCTETS_OFFSET) +#define XMC4_ETH_RXTCP_GOOD_OCTETS (XMC4_ETH0_BASE+XMC4_ETH_RXTCP_GOOD_OCTETS_OFFSET) +#define XMC4_ETH_RXTCP_ERROR_OCTETS (XMC4_ETH0_BASE+XMC4_ETH_RXTCP_ERROR_OCTETS_OFFSET) +#define XMC4_ETH_RXICMP_GOOD_OCTETS (XMC4_ETH0_BASE+XMC4_ETH_RXICMP_GOOD_OCTETS_OFFSET) +#define XMC4_ETH_RXICMP_ERROR_OCTETS (XMC4_ETH0_BASE+XMC4_ETH_RXICMP_ERROR_OCTETS_OFFSET) + +/* System Time Registers */ + +#define XMC4_ETH_TIMESTAMP_CONTROL (XMC4_ETH0_BASE+XMC4_ETH_TIMESTAMP_CONTROL_OFFSET) +#define XMC4_ETH_SUB_SECOND_INCREMENT (XMC4_ETH0_BASE+XMC4_ETH_SUB_SECOND_INCREMENT_OFFSET) +#define XMC4_ETH_SYSTEM_TIME_SECONDS (XMC4_ETH0_BASE+XMC4_ETH_SYSTEM_TIME_SECONDS_OFFSET) +#define XMC4_ETH_SYSTEM_TIME_NANOSECONDS (XMC4_ETH0_BASE+XMC4_ETH_SYSTEM_TIME_NANOSECONDS_OFFSET) +#define XMC4_ETH_SYSTEM_TIME_SECONDS_UPDATE (XMC4_ETH0_BASE+XMC4_ETH_SYSTEM_TIME_SECONDS_UPDATE_OFFSET) +#define XMC4_ETH_SYSTEM_TIME_NANOSECONDS_UPDATE (XMC4_ETH0_BASE+XMC4_ETH_SYSTEM_TIME_NANOSECONDS_UPDATE_OFFSET) +#define XMC4_ETH_TIMESTAMP_ADDEND (XMC4_ETH0_BASE+XMC4_ETH_TIMESTAMP_ADDEND_OFFSET) +#define XMC4_ETH_TARGET_TIME_SECONDS (XMC4_ETH0_BASE+XMC4_ETH_TARGET_TIME_SECONDS_OFFSET) +#define XMC4_ETH_TARGET_TIME_NANOSECONDS (XMC4_ETH0_BASE+XMC4_ETH_TARGET_TIME_NANOSECONDS_OFFSET) +#define XMC4_ETH_SYSTEM_TIME_HIGHER_WORD_SECONDS (XMC4_ETH0_BASE+XMC4_ETH_SYSTEM_TIME_HIGHER_WORD_SECONDS_OFFSET) +#define XMC4_ETH_TIMESTAMP_STATUS (XMC4_ETH0_BASE+XMC4_ETH_TIMESTAMP_STATUS_OFFSET) + +/* DMA Registers*/ + +#define XMC4_ETH_BUS_MODE (XMC4_ETH0_BASE+XMC4_ETH_BUS_MODE_OFFSET) +#define XMC4_ETH_TRANSMIT_POLL_DEMAND (XMC4_ETH0_BASE+XMC4_ETH_TRANSMIT_POLL_DEMAND_OFFSET) +#define XMC4_ETH_RECEIVE_POLL_DEMAND (XMC4_ETH0_BASE+XMC4_ETH_RECEIVE_POLL_DEMAND_OFFSET) +#define XMC4_ETH_RECEIVE_DESCRIPTOR_LIST_ADDRESS (XMC4_ETH0_BASE+XMC4_ETH_RECEIVE_DESCRIPTOR_LIST_ADDRESS_OFFSET) +#define XMC4_ETH_TRANSMIT_DESCRIPTOR_LIST_ADDRESS (XMC4_ETH0_BASE+XMC4_ETH_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_OFFSET) +#define XMC4_ETH_STATUS (XMC4_ETH0_BASE+XMC4_ETH_STATUS_OFFSET) +#define XMC4_ETH_OPERATION_MODE (XMC4_ETH0_BASE+XMC4_ETH_OPERATION_MODE_OFFSET) +#define XMC4_ETH_INTERRUPT_ENABLE (XMC4_ETH0_BASE+XMC4_ETH_INTERRUPT_ENABLE_OFFSET) +#define XMC4_ETH_MISSED_FRAME_BUFFER_OVERFLOW_COUNTER (XMC4_ETH0_BASE+XMC4_ETH_MISSED_FRAME_BUFFER_OVERFLOW_COUNTER_OFFSET) +#define XMC4_ETH_RECEIVE_INTERRUPT_WATCHDOG_TIMER (XMC4_ETH0_BASE+XMC4_ETH_RECEIVE_INTERRUPT_WATCHDOG_TIMER_OFFSET) +#define XMC4_ETH_AHB_STATUS (XMC4_ETH0_BASE+XMC4_ETH_AHB_STATUS_OFFSET) +#define XMC4_ETH_CURRENT_HOST_TRANSMIT_DESCRIPTOR (XMC4_ETH0_BASE+XMC4_ETH_CURRENT_HOST_TRANSMIT_DESCRIPTOR_OFFSET) +#define XMC4_ETH_CURRENT_HOST_RECEIVE_DESCRIPTOR (XMC4_ETH0_BASE+XMC4_ETH_CURRENT_HOST_RECEIVE_DESCRIPTOR_OFFSET) +#define XMC4_ETH_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS (XMC4_ETH0_BASE+XMC4_ETH_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS_OFFSET) +#define XMC4_ETH_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS (XMC4_ETH0_BASE+XMC4_ETH_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS_OFFSET) +#define XMC4_ETH_HW_FEATURE (XMC4_ETH0_BASE+XMC4_ETH_HW_FEATURE_OFFSET) + /* Register Bit-Field Definitions ***********************************************************************************/ +/* MAC Configuration Registers */ + +/* MAC Configuration Register */ +#define ETH_MAC_CONFIGURATION_ +/* MAC Frame Filter */ +#define ETH_MAC_FRAME_FILTER_ +/* Hash Table High Register */ +#define ETH_HASH_TABLE_LOW_ +/* MII Address Register */ +#define ETH_GMII_ADDRESS_ +/* MII Data Register */ +#define ETH_GMII_DATA_ +/* Flow Control Register */ +#define ETH_FLOW_CONTROL_ +/* VLAN Tag Register */ +#define ETH_VLAN_TAG_ +/* Version Register */ +#define ETH_VERSION_ +/* Debug Register */ +#define ETH_DEBUG_ +/* Remote Wake Up Frame Filter Register */ +#define ETH_REMOTE_WAKE_UP_FRAME_FILTER_ +/* PMT Control and Status Register */ +#define ETH_PMT_CONTROL_STATUS_ +/* Interrupt Register */ +#define ETH_INTERRUPT_STATUS_ +/* Interrupt Mask Register */ +#define ETH_INTERRUPT_MASK_ +/* MAC Address0 High Register */ +#define ETH_MAC_ADDRESS0_HIGH_ +/* MAC Address0 Low Register */ +#define ETH_MAC_ADDRESS0_LOW_ +/* MAC Address1 High Register */ +#define ETH_MAC_ADDRESS1_HIGH_ +/* MAC Address1 Low Register */ +#define ETH_MAC_ADDRESS1_LOW_ +/* MAC Address2 High Register */ +#define ETH_MAC_ADDRESS2_HIGH_ +/* MAC Address2 Low Register */ +#define ETH_MAC_ADDRESS2_LOW_ +/* MAC Address3 High Register */ +#define ETH_MAC_ADDRESS3_HIGH_ +/* MAC Address3 Low Register */ +#define ETH_MAC_ADDRESS3_LOW_ + +/* MAC Management Counters */ + +/* MMC Control Register */ +#define ETH_MMC_CONTROL_ +/* MMC Receive Interrupt Register */ +#define ETH_MMC_RECEIVE_INTERRUPT_ +/* MMC Transmit Interrupt Register */ +#define ETH_MMC_TRANSMIT_INTERRUPT_ +/* MMC Reveive Interrupt Mask Register */ +#define ETH_MMC_RECEIVE_INTERRUPT_MASK_ +/* MMC Transmit Interrupt Mask Register */ +#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_ +/* Transmit Octet Count for Good and Bad Frames Register */ +#define ETH_TX_OCTET_GOODBAD_COUNT_ +/* Transmit Frame Count for Goodand Bad Frames Register */ +#define ETH_TX_FRAME_GOODBAD_COUNT_ +/* Transmit Frame Count for Good Broadcast Frames */ +#define ETH_TX_BROADCAST_GOOD_FRAMES_ +/* Transmit Frame Count for Good Multicast Frames */ +#define ETH_TX_MULTICAST_GOOD_FRAMES_ +/* Transmit Octet Count for Good and Bad 64 Byte Frames */ +#define ETH_TX_64OCTETS_FRAMES_ +/* Transmit Octet Count for Good and Bad 65 to 127 Bytes Frames */ +#define ETH_TX_65TO127OCTETS_FRAMES_ +/* Transmit Octet Count for Good and Bad 128 to 255 Bytes Frames */ +#define ETH_TX_128TO255OCTETS_FRAMES_ +/* Transmit Octet Count for Good and Bad 256 to 511 Bytes Frames */ +#define ETH_TX_256TO511OCTETS_FRAMES_ +/* Transmit Octet Count for Good and Bad 512 to 1023 Bytes Frames */ +#define ETH_TX_512TO1023OCTETS_FRAMES_ +/* Transmit Octet Count for Good and Bad 1024 to Maxsize Bytes Frames */ +#define ETH_TX_1024TOMAXOCTETS_FRAMES_ +/* Transmit Frame Count for Good and Bad Unicast Frames */ +#define ETH_TX_UNICAST_FRAMES_ +/* Transmit Frame Count for Good and Bad Multicast Frames */ +#define ETH_TX_MULTICAST_GOODBAD_FRAMES_ +/* Transmit Frame Count for Good and Bad Broadcast Frames */ +#define ETH_TX_BROADCAST_GOODBAD_FRAMES_ +/* Transmit Frame Count for Underflow Error Frames */ +#define ETH_TX_UNDERFLOW_ERROR_FRAMES_ +/* Transmit Frame Count for Frames Transmitted after Single Collision */ +#define ETH_TX_SINGLE_COLLISION_FRAMES_ +/* Transmit Frame Count for Frames Transmitted after Multiple Collision */ +#define ETH_TX_MULTIPLE_COLLISION_FRAMES_ +/* Tx Deferred Frames Register */ +#define ETH_TX_DEFERRED_FRAMES_ +/* Transmit Frame Count for Late Collision Error Frames */ +#define ETH_TX_LATE_COLLISION_FRAMES_ +/* Transmit Frame Count for Excessive Collision Error Frames */ +#define ETH_TX_EXCESSIVE_COLLISION_FRAMES_ +/* Transmit Frame Count for Carrier Sense Error Frames */ +#define ETH_TX_CARRIER_ERROR_FRAMES_ +/* Tx Octet Count Good Register */ +#define ETH_TX_OCTET_GOOD_COUNT_ +/* Tx Frame Count Good Register */ +#define ETH_TX_FRAME_GOOD_COUNT_ +/* Transmit Frame Count for Excessive Deferral Error Frames */ +#define ETH_TX_EXCESSIVE_DEFERRAL_ERROR_ +/* Transmit Frame Count for Good PAUSE Frames */ +#define ETH_TX_PAUSE_FRAMES_ +/* Transmit Frame Count for Good VLAN Frames */ +#define ETH_TX_VLAN_FRAMES_ +/* Transmit Frame Count for Good Oversize Frames */ +#define ETH_TX_OSIZE_FRAMES_ +/* Receive Frame Count for Goand Bad Frames */ +#define ETH_RX_FRAMES_COUNT_ +/* Receive Octet Count for Good and Bad Frames */ +#define ETH_RX_OCTET_GOODBAD_COUNT_ +/* Rx Octet Count Good Register */ +#define ETH_RX_OCTET_GOOD_COUNT_ +/* Receive Frame Count for Good Broadcast Frames */ +#define ETH_RX_BROADCAST_FRAMES_ +/* Receive Frame Count for Good Multicast Frames */ +#define ETH_RX_MULTICAST_FRAMES_ +/* Receive Frame Count for CRC Error Frames */ +#define ETH_RX_CRC_ERROR_FRAMES_ +/* Receive Frame Count for Alignment Error Frames */ +#define ETH_RX_ALIGNMENT_ERROR_FRAMES_ +/* Receive Frame Count for Runt Error Frames */ +#define ETH_RX_RUNT_ERROR_FRAMES_ +/* Receive Frame Count for Jabber Error Frames */ +#define ETH_RX_JABBER_ERROR_FRAMES_ +/* Receive Frame Count for Undersize Frames */ +#define ETH_RX_UNDERSIZE_FRAMES_ +/* Rx Oversize Frames Good Register */ +#define ETH_RX_OVERSIZE_FRAMES_ +/* Receive Frame Count for Good and Bad 64 Byte Frames */ +#define ETH_RX_64OCTETS_FRAMES_ +/* Receive Frame Count for Good and Bad 65 to 127 Bytes Frames */ +#define ETH_RX_65TO127OCTETS_FRAMES_ +/* Receive Frame Count for Good and Bad 128 to 255 Bytes Frames */ +#define ETH_RX_128TO255OCTETS_FRAMES_ +/* Receive Frame Count for Good and Bad 256 to 511 Bytes Frames */ +#define ETH_RX_256TO511OCTETS_FRAMES_ +/* Receive Frame Count for Good and Bad 512 to 1,023 Bytes Frames */ +#define ETH_RX_512TO1023OCTETS_FRAMES_ +/* Receive Frame Count for Good and Bad 1,024 to Maxsize Bytes Frames */ +#define ETH_RX_1024TOMAXOCTETS_FRAMES_ +/* Receive Frame Count for Good Unicast Frames */ +#define ETH_RX_UNICAST_FRAMES_ +/* Receive Frame Count for Length Error Frames */ +#define ETH_RX_LENGTH_ERROR_FRAMES_ +/* Receive Frame Count for Out of Range Frames */ +#define ETH_RX_OUT_OF_RANGE_TYPE_FRAMES_ +/* Receive Frame Count for PAUSE Frames */ +#define ETH_RX_PAUSE_FRAMES_ +/* Receive Frame Count for FIFO Overflow Frames */ +#define ETH_RX_FIFO_OVERFLOW_FRAMES_ +/* Receive Frame Count for Good and Bad VLAN Frames */ +#define ETH_RX_VLAN_FRAMES_ +/* Receive Frame Count for Watchdog Error Frames */ +#define ETH_RX_WATCHDOG_ERROR_FRAMES_ +/* Receive Frame Count for Receive Error Frames */ +#define ETH_RX_RECEIVE_ERROR_FRAMES_ +/* Receive Frame Count for Good Control Frames Frames */ +#define ETH_RX_CONTROL_FRAMES_ +/* MMC Receive Checksum Offload Interrupt Mask Register */ +#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_ +/* MMC Receive Checksum Offload Interrupt Register */ +#define ETH_MMC_IPC_RECEIVE_INTERRUPT_ +/* RxIPv4 Good Frames Register */ +#define ETH_RXIPV4_GOOD_FRAMES_ +/* Receive IPV4 Header Error Frame Counter Register */ +#define ETH_RXIPV4_HEADER_ERROR_FRAMES_ +/* Receive IPV4 No Payload Frame Counter Register */ +#define ETH_RXIPV4_NO_PAYLOAD_FRAMES_ +/* Receive IPV4 Fragmented Frame Counter Register */ +#define ETH_RXIPV4_FRAGMENTED_FRAMES_ +/* Receive IPV4 UDP Checksum Disabled Frame Counter Register */ +#define ETH_RXIPV4_UDP_CHECKSUM_DISABLED_FRAMES_ +/* RxIPv6 Good Frames Register */ +#define ETH_RXIPV6_GOOD_FRAMES_ +/* Receive IPV6 Header Error Frame Counter Register */ +#define ETH_RXIPV6_HEADER_ERROR_FRAMES_ +/* Receive IPV6 No Payload Frame Counter Register */ +#define ETH_RXIPV6_NO_PAYLOAD_FRAMES_ +/* RxUDP Good Frames Register */ +#define ETH_RXUDP_GOOD_FRAMES_ +/* RxUDP Error Frames Register */ +#define ETH_RXUDP_ERROR_FRAMES_ +/* RxTCP Good Frames Register */ +#define ETH_RXTCP_GOOD_FRAMES_ +/* RxTCP Error Frames Register */ +#define ETH_RXTCP_ERROR_FRAMES_ +/* RxICMP Good Frames Register */ +#define ETH_RXICMP_GOOD_FRAMES_ +/* RxICMP Error Frames Register */ +#define ETH_RXICMP_ERROR_FRAMES_ +/* RxIPv4 Good Octets Register */ +#define ETH_RXIPV4_GOOD_OCTETS_ +/* Receive IPV4 Header Error Octet Counter Register */ +#define ETH_RXIPV4_HEADER_ERROR_OCTETS_ +/* Receive IPV4 No Payload Octet Counter Register */ +#define ETH_RXIPV4_NO_PAYLOAD_OCTETS_ +/* Receive IPV4 Fragmented Octet Counter Register */ +#define ETH_RXIPV4_FRAGMENTED_OCTETS_ +/* Receive IPV4 Fragmented Octet Counter Register */ +#define ETH_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_ +/* RxIPv6 Good Octets Register */ +#define ETH_RXIPV6_GOOD_OCTETS_ +/* Receive IPV6 Header Error Octet Counter Register */ +#define ETH_RXIPV6_HEADER_ERROR_OCTETS_ +/* Receive IPV6 No Payload Octet Counter Register */ +#define ETH_RXIPV6_NO_PAYLOAD_OCTETS_ +/* Receive UDP Good Octets Register */ +#define ETH_RXUDP_GOOD_OCTETS_ +/* Receive UDP Error Octets Register */ +#define ETH_RXUDP_ERROR_OCTETS_ +/* Receive TCP Good Octets Register */ +#define ETH_RXTCP_GOOD_OCTETS_ +/* Receive TCP Error Octets Register */ +#define ETH_RXTCP_ERROR_OCTETS_ +/* Receive ICMP Good Octets Register */ +#define ETH_RXICMP_GOOD_OCTETS_ +/* Receive ICMP Error Octets Register */ +#define ETH_RXICMP_ERROR_OCTETS_ + +/* System Time Registers */ + +/* Timestamp Control Register */ +#define ETH_TIMESTAMP_CONTROL_ +/* Sub-Second Increment Register */ +#define ETH_SUB_SECOND_INCREMENT_ +/* System Time - Seconds Register */ +#define ETH_SYSTEM_TIME_SECONDS_ +/* System Time Nanoseconds Register */ +#define ETH_SYSTEM_TIME_NANOSECONDS_ +/* System Time - Seconds Update Register */ +#define ETH_SYSTEM_TIME_SECONDS_UPDATE_ +/* System Time Nanoseconds Update Register */ +#define ETH_SYSTEM_TIME_NANOSECONDS_UPDATE_ +/* Timestamp Addend Register */ +#define ETH_TIMESTAMP_ADDEND_ +/* Target Time Seconds Register */ +#define ETH_TARGET_TIME_SECONDS_ +/* Target Time Nanoseconds Register */ +#define ETH_TARGET_TIME_NANOSECONDS_ +/* System Time - Higher Word Seconds Register */ +#define ETH_SYSTEM_TIME_HIGHER_WORD_SECONDS_ +/* Timestamp Status Register */ +#define ETH_TIMESTAMP_STATUS_ + +/* DMA Registers*/ + +/* Bus Mode Register */ +#define ETH_BUS_MODE_ +/* Transmit Poll Demand Register */ +#define ETH_TRANSMIT_POLL_DEMAND_ +/* Receive Poll Demand Register */ +#define ETH_RECEIVE_POLL_DEMAND_ +/* Receive Descriptor Address Register */ +#define ETH_RECEIVE_DESCRIPTOR_LIST_ADDRESS_ +/* Transmit descripter Address Register */ +#define ETH_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_ +/* Status Register */ +#define ETH_STATUS_ +/* Operation Mode Register */ +#define ETH_OPERATION_MODE_ +/* Interrupt Enable Register */ +#define ETH_INTERRUPT_ENABLE_ +/* Missed Frame and Buffer Overflow Counter Register */ +#define ETH_MISSED_FRAME_BUFFER_OVERFLOW_COUNTER_ +/* Receive Interrupt Watchdog Timer Register */ +#define ETH_RECEIVE_INTERRUPT_WATCHDOG_TIMER_ +/* AHB Status Register */ +#define ETH_AHB_STATUS_ +/* Current Host Transmit Descriptor Register */ +#define ETH_CURRENT_HOST_TRANSMIT_DESCRIPTOR_ +/* Current Host Receive Descriptor Register */ +#define ETH_CURRENT_HOST_RECEIVE_DESCRIPTOR_ +/* Current Host Transmit Buffer Address Register */ +#define ETH_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS_ +/* Current Host Receive Buffer Address Register */ +#define ETH_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS_ +/* HW Feature Register */ +#define ETH_HW_FEATURE_ #endif /* __ARCH_ARM_SRC_XMC4_CHIP_XMC4_ETHERNET_H */ diff --git a/arch/arm/src/xmc4/xmc4_allocateheap.c b/arch/arm/src/xmc4/xmc4_allocateheap.c index cdbc8ef2d18..37ae505466a 100644 --- a/arch/arm/src/xmc4/xmc4_allocateheap.c +++ b/arch/arm/src/xmc4/xmc4_allocateheap.c @@ -55,18 +55,6 @@ #include "up_internal.h" #include "xmc4_mpuinit.h" -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - /**************************************************************************** * Public Functions ****************************************************************************/ From ae32905fe81fe8e3e85b49a67d4d6537493f412f Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 19 Mar 2017 17:06:44 -0600 Subject: [PATCH 52/81] XMC4xxx: Simply some USIC logic, add USIC interface to disable a channel. Add USIC enable logic to UART configuration (a lot more to do there). --- arch/arm/src/xmc4/xmc4_lowputc.c | 32 ++++- arch/arm/src/xmc4/xmc4_lowputc.h | 32 ++++- arch/arm/src/xmc4/xmc4_usic.c | 193 ++++++++++++------------------- arch/arm/src/xmc4/xmc4_usic.h | 32 +++++ 4 files changed, 157 insertions(+), 132 deletions(-) diff --git a/arch/arm/src/xmc4/xmc4_lowputc.c b/arch/arm/src/xmc4/xmc4_lowputc.c index 6df364565ca..305a43f657a 100644 --- a/arch/arm/src/xmc4/xmc4_lowputc.c +++ b/arch/arm/src/xmc4/xmc4_lowputc.c @@ -196,17 +196,37 @@ void xmc4_uart_reset(uintptr_t uart_base) * Name: xmc4_uart_configure * * Description: - * Configure a UART as a RS-232 UART. + * Enable and configure a USIC channel as a RS-232 UART. + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned to + * indicate the nature of any failure. * ****************************************************************************/ #ifdef HAVE_UART_DEVICE -void xmc4_uart_configure(uintptr_t uart_base, uint32_t baud, - uint32_t clock, unsigned int parity, - unsigned int nbits, unsigned int stop2) +int xmc4_uart_configure(enum usic_channel_e channel, uint32_t baud, + uint32_t clock, unsigned int parity, + unsigned int nbits, unsigned int stop2) { - /* Disable the transmitter and receiver throughout the reconfiguration */ -#warning Missing logic + uintptr_t base; + int ret; + + /* Get the base address of the USIC registers associated with this channel */ + + base = uintptr_t xmc4_channel_baseaddress(channel); + if (base == 0) + { + return -EINVAL; + } + + /* Enable the USIC channel */ + + ret = xmc4_enable_usic_channel(channel); + if (ret < 0) + { + return ret; + } /* Configure number of bits, stop bits and parity */ #warning Missing logic diff --git a/arch/arm/src/xmc4/xmc4_lowputc.h b/arch/arm/src/xmc4/xmc4_lowputc.h index 7287855a7be..fa9d8ce16bd 100644 --- a/arch/arm/src/xmc4/xmc4_lowputc.h +++ b/arch/arm/src/xmc4/xmc4_lowputc.h @@ -41,8 +41,11 @@ ****************************************************************************/ #include + #include + #include "xmc4_config.h" +#include "xmc4_usic.h" /**************************************************************************** * Public Function Prototypes @@ -76,15 +79,36 @@ void xmc4_uart_reset(uintptr_t uart_base); * Name: xmc4_uart_configure * * Description: - * Configure a UART as a RS-232 UART. + * Enable and configure a USIC channel as a RS-232 UART. + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned to + * indicate the nature of any failure. * ****************************************************************************/ #ifdef HAVE_UART_DEVICE -void xmc4_uart_configure(uintptr_t uart_base, uint32_t baud, - uint32_t clock, unsigned int parity, - unsigned int nbits, unsigned int stop2); +int xmc4_uart_configure(enum usic_channel_e channel, uint32_t baud, + uint32_t clock, unsigned int parity, + unsigned int nbits, unsigned int stop2); #endif +/**************************************************************************** + * Name: xmc4_uart_disable + * + * Description: + * Disable a USIC channel previously configured as a RS-232 UART. it will + * be necessary to again call xmc4_uart_configure() in order to use this + * UART channel again. + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned to + * indicate the nature of any failure. + * + ****************************************************************************/ + +#ifdef HAVE_UART_DEVICE +#define xmc4_uart_disable(c) xmc4_disable_usic_channel(c) +#endif #endif /* __ARCH_ARM_SRC_XMC4_XMC4_LOWPUTC_H */ diff --git a/arch/arm/src/xmc4/xmc4_usic.c b/arch/arm/src/xmc4/xmc4_usic.c index f252bb1a499..1480cdb7a8c 100644 --- a/arch/arm/src/xmc4/xmc4_usic.c +++ b/arch/arm/src/xmc4/xmc4_usic.c @@ -50,6 +50,31 @@ #include "chip/xmc4_scu.h" #include "xmc4_usic.h" +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Provides mapping of USIC enumeration value to USIC channel base address */ + +static uintptr_t g_channel_baseaddress[2 * XMC4_NUSIC] = +{ + XMC4_USIC0_CH0_BASE, + XMC4_USIC0_CH1_BASE +#if XMC4_NUSIC > 1 + , + XMC4_USIC1_CH0_BASE, + XMC4_USIC1_CH1_BASE +#if XMC4_NUSIC > 2 + , + XMC4_USIC2_CH0_BASE, + XMC4_USIC2_CH1_BASE +#if XMC4_NUSIC > 3 +# error Extend table values for addition USICs +#endif +#endif +#endif +}; + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -186,6 +211,29 @@ int xmc4_disable_usic(enum usic_e usic) return OK; } +/**************************************************************************** + * Name: xmc4_channel_baseaddress + * + * Description: + * Given a USIC channel enumeration value, return the base address of the + * channel registers. + * + * Returned Value: + * The non-zero address of the channel base registers is return on success. + * Zero is returned on any failure. + * + ****************************************************************************/ + +uintptr_t xmc4_channel_baseaddress(enum usic_channel_e channel) +{ + if ((usigned int)channel < (2 * XM4C_NUSICS)) + { + return g_channel_baseaddress[channel]; + } + + return 0; +} + /**************************************************************************** * Name: xmc4_enable_usic_channel * @@ -204,75 +252,22 @@ int xmc4_enable_usic_channel(enum usic_channel_e channel) uintptr_t base; uintptr_t regaddr; uint32_t regval; + int ret; - switch (channel) + /* Get the base address of the registers for this channel */ + + base = xmc4_channel_baseaddress(channel); + if (base == 0) { - case USIC0_CHAN0: - /* USIC0 Channel 0 base address */ + return -EINVAL; + } - base = XMC4_USIC0_CH0_BASE; + /* Enable the USIC module */ - /* Enable USIC0 */ - - xmc4_enable_usic(USIC0); - break; - - case USIC0_CHAN1: - /* USIC0 Channel 1 base address */ - - base = XMC4_USIC0_CH1_BASE; - - /* Enable USIC0 */ - - xmc4_enable_usic(USIC0); - break; - -#if XMC4_NUSIC > 1 - case USIC1_CHAN0: - /* USIC1 Channel 0 base address */ - - base = XMC4_USIC1_CH0_BASE; - - /* Enable USIC1 */ - - xmc4_enable_usic(USIC1); - break; - - case USIC1_CHAN1: - /* USIC1 Channel 1 base address */ - - base = XMC4_USIC1_CH1_BASE; - - /* Enable USIC1 */ - - xmc4_enable_usic(USIC1); - break; - -#if XMC4_NUSIC > 2 - case USIC2_CHAN0: - /* USIC2 Channel 0 base address */ - - base = XMC4_USIC2_CH0_BASE; - - /* Enable USIC2 */ - - xmc4_enable_usic(USIC2); - break; - - case USIC2_CHAN1: - /* USIC2 Channel 1 base address */ - - base = XMC4_USIC2_CH1_BASE; - - /* Enable USIC2 */ - - xmc4_enable_usic(USIC2); - break; -#endif -#endif - - default: - return -EINVAL; + xmc4_enable_usic(xmc4_channel2usic(channel)); + if (ret < 0) + { + return ret; } /* Enable USIC channel */ @@ -315,64 +310,13 @@ int xmc4_disable_usic_channel(enum usic_channel_e channel) uintptr_t other; uintptr_t regaddr; uint32_t regval; - enum usic_e usic; - switch (channel) + /* Get the base address of the registers for this channel */ + + base = xmc4_channel_baseaddress(channel); + if (base == 0) { - case USIC0_CHAN0: - /* Enable USIC0 Channel 0 base address */ - - base = XMC4_USIC0_CH0_BASE; - other = XMC4_USIC0_CH1_BASE; - usic = USIC0; - break; - - case USIC0_CHAN1: - /* Enable USIC0 Channel 1 base address */ - - base = XMC4_USIC0_CH1_BASE; - other = XMC4_USIC0_CH0_BASE; - usic = USIC0; - break; - -#if XMC4_NUSIC > 1 - case USIC1_CHAN0: - /* Enable USIC1 Channel 0 base address */ - - base = XMC4_USIC1_CH0_BASE; - other = XMC4_USIC1_CH1_BASE; - usic = USIC1; - break; - - case USIC1_CHAN1: - /* Enable USIC1 Channel 1 base address */ - - base = XMC4_USIC1_CH1_BASE; - other = XMC4_USIC1_CH0_BASE; - usic = USIC1; - break; - -#if XMC4_NUSIC > 2 - case USIC2_CHAN0: - /* Enable USIC2 Channel 0 base address */ - - base = XMC4_USIC2_CH0_BASE; - other = XMC4_USIC2_CH1_BASE; - usic = USIC2; - break; - - case USIC2_CHAN1: - /* Enable USIC2 Channel 1 base address */ - - base = XMC4_USIC2_CH1_BASE; - other = XMC4_USIC2_CH0_BASE; - usic = USIC2; - break; -#endif -#endif - - default: - return -EINVAL; + return -EINVAL; } /* Disable this channel */ @@ -383,6 +327,11 @@ int xmc4_disable_usic_channel(enum usic_channel_e channel) regval |= USIC_KSCFG_BPMODEN; putreg32(regval, regaddr); + /* Get the base address of other channel for this USIC module */ + + other = xmc4_channel_baseaddress(channel ^ 1); + DEBUASSERT(other != 0); + /* Check if the other channel has also been disabled */ regaddr = other + XMC4_USIC_KSCFG_OFFSET; @@ -390,7 +339,7 @@ int xmc4_disable_usic_channel(enum usic_channel_e channel) { /* Yes... Disable the USIC module */ - xmc4_disable_usic(usic); + xmc4_disable_usic(xmc4_channel2usic(channel)); } return OK; diff --git a/arch/arm/src/xmc4/xmc4_usic.h b/arch/arm/src/xmc4/xmc4_usic.h index e1bf78dc07f..07ab1fc2de4 100644 --- a/arch/arm/src/xmc4/xmc4_usic.h +++ b/arch/arm/src/xmc4/xmc4_usic.h @@ -105,6 +105,38 @@ int xmc4_enable_usic(enum usic_e usic); int xmc4_disable_usic(enum usic_e usic); +/**************************************************************************** + * Name: xmc4_channel2usic + * + * Description: + * Given a USIC channel enumeration value, return the corresponding USIC + * enumerication value. + * + * Returned Value: + * The corresponding USIC enumeration value. + * + ****************************************************************************/ + +static inline enum usic_e xmc4_channel2usic(enum usic_channel_e channel) +{ + return (enum usic_e)((unsigned int)channel >> 1); +} + +/**************************************************************************** + * Name: xmc4_channel_baseaddress + * + * Description: + * Given a USIC channel enumeration value, return the base address of the + * channel registers. + * + * Returned Value: + * The non-zero address of the channel base registers is return on success. + * Zero is returned on any failure. + * + ****************************************************************************/ + +uintptr_t xmc4_channel_baseaddress(enum usic_channel_e channel); + /**************************************************************************** * Name: xmc4_enable_usic_channel * From 5df421488c77ed48bb9521b1ddeca293adbcee83 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 19 Mar 2017 18:11:38 -0600 Subject: [PATCH 53/81] XMC4xxx: Add USIC baudrate calculation. --- arch/arm/src/xmc4/xmc4_clockconfig.h | 13 +++- arch/arm/src/xmc4/xmc4_clockutils.c | 80 ++++++++++++++------ arch/arm/src/xmc4/xmc4_lowputc.c | 23 +++--- arch/arm/src/xmc4/xmc4_usic.c | 109 ++++++++++++++++++++++++++- arch/arm/src/xmc4/xmc4_usic.h | 15 ++++ 5 files changed, 202 insertions(+), 38 deletions(-) diff --git a/arch/arm/src/xmc4/xmc4_clockconfig.h b/arch/arm/src/xmc4/xmc4_clockconfig.h index 6e03989cad0..5001683accb 100644 --- a/arch/arm/src/xmc4/xmc4_clockconfig.h +++ b/arch/arm/src/xmc4/xmc4_clockconfig.h @@ -70,10 +70,21 @@ void xmc4_clock_configure(void); * Name: xmc4_get_coreclock * * Description: - * Return the current core clock frequency. + * Return the current core clock frequency, fCPU. * ****************************************************************************/ uint32_t xmc4_get_coreclock(void); +/**************************************************************************** + * Name: xmc4_get_periphclock + * + * Description: + * The peripheral clock is either fCPU or fCPU/2, depending on the state + * of the peripheral divider. + * + ****************************************************************************/ + +uint32_t xmc4_get_periphclock(void); + #endif /* __ARCH_ARM_SRC_XMC4_XMC4_CLOCKCONFIG_H */ diff --git a/arch/arm/src/xmc4/xmc4_clockutils.c b/arch/arm/src/xmc4/xmc4_clockutils.c index cf9649099ed..4d334eaef53 100644 --- a/arch/arm/src/xmc4/xmc4_clockutils.c +++ b/arch/arm/src/xmc4/xmc4_clockutils.c @@ -101,36 +101,36 @@ uint32_t xmc4_get_coreclock(void) temp = BOARD_XTAL_FREQUENCY; } - /* Check if PLL is locked */ + /* Check if PLL is locked */ - regval = getreg32(XMC4_SCU_PLLSTAT); - if ((regval & SCU_PLLSTAT_VCOLOCK) != 0) - { - /* PLL normal mode */ + regval = getreg32(XMC4_SCU_PLLSTAT); + if ((regval & SCU_PLLSTAT_VCOLOCK) != 0) + { + /* PLL normal mode */ - regval = getreg32(XMC4_SCU_PLLCON1); - pdiv = ((regval & SCU_PLLCON1_PDIV_MASK) >> SCU_PLLCON1_PDIV_SHIFT) + 1; - ndiv = ((regval & SCU_PLLCON1_NDIV_MASK) >> SCU_PLLCON1_NDIV_SHIFT) + 1; - kdiv = ((regval & SCU_PLLCON1_K2DIV_MASK) >> SCU_PLLCON1_K2DIV_SHIFT) + 1; + regval = getreg32(XMC4_SCU_PLLCON1); + pdiv = ((regval & SCU_PLLCON1_PDIV_MASK) >> SCU_PLLCON1_PDIV_SHIFT) + 1; + ndiv = ((regval & SCU_PLLCON1_NDIV_MASK) >> SCU_PLLCON1_NDIV_SHIFT) + 1; + kdiv = ((regval & SCU_PLLCON1_K2DIV_MASK) >> SCU_PLLCON1_K2DIV_SHIFT) + 1; - temp = (temp / (pdiv * kdiv)) * ndiv; + temp = (temp / (pdiv * kdiv)) * ndiv; + } + else + { + /* PLL prescalar mode */ + + regval = getreg32(XMC4_SCU_PLLCON1); + kdiv = ((regval & SCU_PLLCON1_K1DIV_MASK) >> SCU_PLLCON1_K1DIV_SHIFT) + 1; + + temp = (temp / kdiv); + } } - else - { - /* PLL prescalar mode */ - - regval = getreg32(XMC4_SCU_PLLCON1); - kdiv = ((regval & SCU_PLLCON1_K1DIV_MASK) >> SCU_PLLCON1_K1DIV_SHIFT) + 1; - - temp = (temp / kdiv); - } - } else - { - /* fOFI is clock source for fSYS */ + { + /* fOFI is clock source for fSYS */ - temp = OFI_FREQUENCY; - } + temp = OFI_FREQUENCY; + } /* Divide by SYSDIV to get fSYS */ @@ -148,3 +148,35 @@ uint32_t xmc4_get_coreclock(void) return temp; } + +/**************************************************************************** + * Name: xmc4_get_periphclock + * + * Description: + * The peripheral clock is either fCPU or fCPU/2, depending on the state + * of the peripheral divider. + * + ****************************************************************************/ + +uint32_t xmc4_get_periphclock(void) +{ + uint32_t periphclock; + + /* Get the CPU clock frequency. Unless it is divided down, this also the + * peripheral clock frequency. + */ + + periphclock = xmc4_get_coreclock(); + + /* Get the peripheral clock divider */ + + periphclock = getreg32(XMC4_SCU_PBCLKCR); + if ((periphclock & SCU_PBCLKCR_PBDIV) != 0) + { + /* The peripheral clock is fCPU/2 */ + + periphclock <<= 1; + } + + return periphclock; +} diff --git a/arch/arm/src/xmc4/xmc4_lowputc.c b/arch/arm/src/xmc4/xmc4_lowputc.c index 305a43f657a..0c7a4fdc5ef 100644 --- a/arch/arm/src/xmc4/xmc4_lowputc.c +++ b/arch/arm/src/xmc4/xmc4_lowputc.c @@ -40,6 +40,7 @@ #include #include +#include #include #include @@ -50,6 +51,7 @@ #include "xmc4_config.h" #include "chip/xmc4_usic.h" #include "chip/xmc4_pinmux.h" +#include "xmc4_usic.h" #include "xmc4_lowputc.h" /**************************************************************************** @@ -60,42 +62,42 @@ #if defined(HAVE_UART_CONSOLE) # if defined(CONFIG_UART0_SERIAL_CONSOLE) -# define CONSOLE_BASE XMC4_USIC0_CH0_BASE +# define CONSOLE_CHAN USIC0_CHAN0 # define CONSOLE_FREQ BOARD_CORECLK_FREQ # define CONSOLE_BAUD CONFIG_UART0_BAUD # define CONSOLE_BITS CONFIG_UART0_BITS # define CONSOLE_2STOP CONFIG_UART0_2STOP # define CONSOLE_PARITY CONFIG_UART0_PARITY # elif defined(CONFIG_UART1_SERIAL_CONSOLE) -# define CONSOLE_BASE XMC4_USIC0_CH1_BASE +# define CONSOLE_CHAN USIC0_CHAN1 # define CONSOLE_FREQ BOARD_CORECLK_FREQ # define CONSOLE_BAUD CONFIG_UART1_BAUD # define CONSOLE_BITS CONFIG_UART1_BITS # define CONSOLE_2STOP CONFIG_UART1_2STOP # define CONSOLE_PARITY CONFIG_UART1_PARITY # elif defined(CONFIG_UART2_SERIAL_CONSOLE) -# define CONSOLE_BASE XMC4_USIC1_CH0_BASE +# define CONSOLE_CHAN USIC1_CHAN0 # define CONSOLE_FREQ BOARD_BUS_FREQ # define CONSOLE_BAUD CONFIG_UART2_BAUD # define CONSOLE_BITS CONFIG_UART2_BITS # define CONSOLE_2STOP CONFIG_UART2_2STOP # define CONSOLE_PARITY CONFIG_UART2_PARITY # elif defined(CONFIG_UART3_SERIAL_CONSOLE) -# define CONSOLE_BASE XMC4_USIC1_CH1_BASE +# define CONSOLE_CHAN USIC1_CHAN1 # define CONSOLE_FREQ BOARD_BUS_FREQ # define CONSOLE_BAUD CONFIG_UART3_BAUD # define CONSOLE_BITS CONFIG_UART3_BITS # define CONSOLE_2STOP CONFIG_UART3_2STOP # define CONSOLE_PARITY CONFIG_UART3_PARITY # elif defined(CONFIG_UART4_SERIAL_CONSOLE) -# define CONSOLE_BASE XMC4_USIC2_CH0_BASE +# define CONSOLE_CHAN USIC2_CHAN0 # define CONSOLE_FREQ BOARD_BUS_FREQ # define CONSOLE_BAUD CONFIG_UART4_BAUD # define CONSOLE_BITS CONFIG_UART4_BITS # define CONSOLE_2STOP CONFIG_UART4_2STOP # define CONSOLE_PARITY CONFIG_UART4_PARITY # elif defined(CONFIG_UART5_SERIAL_CONSOLE) -# define CONSOLE_BASE XMC4_USIC2_CH1_BASE +# define CONSOLE_CHAN USIC2_CHAN1 # define CONSOLE_FREQ BOARD_BUS_FREQ # define CONSOLE_BAUD CONFIG_UART5_BAUD # define CONSOLE_BITS CONFIG_UART5_BITS @@ -107,7 +109,7 @@ #endif /* HAVE_UART_CONSOLE */ /**************************************************************************** - * Private Data + * Private Functions ****************************************************************************/ /**************************************************************************** @@ -169,7 +171,7 @@ void xmc4_lowsetup(void) * when the serial driver is opened. */ - xmc4_uart_configure(CONSOLE_BASE, CONSOLE_BAUD, CONSOLE_FREQ, \ + xmc4_uart_configure(CONSOLE_CHAN, CONSOLE_BAUD, CONSOLE_FREQ, \ CONSOLE_PARITY, CONSOLE_BITS, CONSOLE_2STOP); #endif /* HAVE_UART_DEVICE */ } @@ -210,11 +212,12 @@ int xmc4_uart_configure(enum usic_channel_e channel, uint32_t baud, unsigned int nbits, unsigned int stop2) { uintptr_t base; + uint32_t oversampling; int ret; /* Get the base address of the USIC registers associated with this channel */ - base = uintptr_t xmc4_channel_baseaddress(channel); + base = xmc4_channel_baseaddress(channel); if (base == 0) { return -EINVAL; @@ -228,6 +231,8 @@ int xmc4_uart_configure(enum usic_channel_e channel, uint32_t baud, return ret; } + ret = xmc4_uisc_baudrate(channel, baud, oversampling); + /* Configure number of bits, stop bits and parity */ #warning Missing logic diff --git a/arch/arm/src/xmc4/xmc4_usic.c b/arch/arm/src/xmc4/xmc4_usic.c index 1480cdb7a8c..26347642403 100644 --- a/arch/arm/src/xmc4/xmc4_usic.c +++ b/arch/arm/src/xmc4/xmc4_usic.c @@ -31,6 +31,20 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * + * May include some logic from sample code provided by Infineon: + * + * Copyright (C) 2011-2015 Infineon Technologies AG. All rights reserved. + * + * Infineon Technologies AG (Infineon) is supplying this software for use with + * Infineon's microcontrollers. This file can be freely distributed within + * development tools that are supporting such microcontrollers. + * + * THIS SOFTWARE IS PROVIDED AS IS. NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, + * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * ****************************************************************************/ /**************************************************************************** @@ -42,12 +56,14 @@ #include #include #include +#include #include #include "up_arch.h" #include "chip/xmc4_usic.h" #include "chip/xmc4_scu.h" +#include "xmc4_clockconfig.h" #include "xmc4_usic.h" /**************************************************************************** @@ -226,7 +242,7 @@ int xmc4_disable_usic(enum usic_e usic) uintptr_t xmc4_channel_baseaddress(enum usic_channel_e channel) { - if ((usigned int)channel < (2 * XM4C_NUSICS)) + if ((unsigned int)channel < (2 * XMC4_NUSIC)) { return g_channel_baseaddress[channel]; } @@ -264,7 +280,7 @@ int xmc4_enable_usic_channel(enum usic_channel_e channel) /* Enable the USIC module */ - xmc4_enable_usic(xmc4_channel2usic(channel)); + ret = xmc4_enable_usic(xmc4_channel2usic(channel)); if (ret < 0) { return ret; @@ -330,7 +346,7 @@ int xmc4_disable_usic_channel(enum usic_channel_e channel) /* Get the base address of other channel for this USIC module */ other = xmc4_channel_baseaddress(channel ^ 1); - DEBUASSERT(other != 0); + DEBUGASSERT(other != 0); /* Check if the other channel has also been disabled */ @@ -343,4 +359,89 @@ int xmc4_disable_usic_channel(enum usic_channel_e channel) } return OK; -} \ No newline at end of file +} + +/**************************************************************************** + * Name: xmc4_uisc_baudrate + * + * Description: + * Set the USIC baudrate for the USIC channel + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned to + * indicate the nature of any failure. + * + ****************************************************************************/ + +int xmc4_uisc_baudrate(enum usic_channel_e channel, uint32_t baud, + uint32_t oversampling) +{ + uintptr_t base; + uint32_t periphclock; + uint32_t clkdiv; + uint32_t clkdiv_min; + uint32_t pdiv; + uint32_t pdiv_int; + uint32_t pdiv_int_min; + uint32_t pdiv_frac; + uint32_t pdiv_frac_min; + uint32_t regval; + int ret; + + /* Get the base address of the registers for this channel */ + + base = xmc4_channel_baseaddress(channel); + if (base == 0) + { + return -EINVAL; + } + + /* The baud and peripheral clock are divided by 100 to be able to use only + * 32-bit arithmetic. + */ + + if (baud >= 100 && oversampling != 0) + { + periphclock = xmc4_get_periphclock() / 100; + baud = baud / 100; + + clkdiv_min = 1; + pdiv_int_min = 1; + pdiv_frac_min = 0x3ff; + + for (clkdiv = 1023; clkdiv > 0; --clkdiv) + { + pdiv = ((periphclock * clkdiv) / (baud * oversampling)); + pdiv_int = pdiv >> 10; + pdiv_frac = pdiv & 0x3ff; + + if (pdiv_int < 1024 && pdiv_frac < pdiv_frac_min) + { + pdiv_frac_min = pdiv_frac; + pdiv_int_min = pdiv_int; + clkdiv_min = clkdiv; + } + } + + /* Select and setup the fractional divider */ + + regval = USIC_FDR_DM_FRACTIONAL | (clkdiv_min << USIC_FDR_STEP_SHIFT); + putreg32(regval, base + XMC4_USIC_FDR_OFFSET); + + /* Setup and enable the baud rate generator */ + + regval = getreg32(base + XMC4_USIC_BRG_OFFSET); + regval &= ~(USIC_BRG_DCTQ_MASK | USIC_BRG_PDIV_MASK | USIC_BRG_PCTQ_MASK | USIC_BRG_PPPEN); + regval |= (USIC_BRG_DCTQ(oversampling - 1) | USIC_BRG_PDIV(pdiv_int_min - 1)); + putreg32(regval, base + XMC4_USIC_BRG_OFFSET); + + ret = OK; + } + else + { + ret = -ERANGE; + } + + return ret; +} + diff --git a/arch/arm/src/xmc4/xmc4_usic.h b/arch/arm/src/xmc4/xmc4_usic.h index 07ab1fc2de4..5c5e78fdb90 100644 --- a/arch/arm/src/xmc4/xmc4_usic.h +++ b/arch/arm/src/xmc4/xmc4_usic.h @@ -167,4 +167,19 @@ int xmc4_enable_usic_channel(enum usic_channel_e channel); int xmc4_disable_usic_channel(enum usic_channel_e channel); +/**************************************************************************** + * Name: xmc4_uisc_baudrate + * + * Description: + * Set the USIC baudrate for the USIC channel + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned to + * indicate the nature of any failure. + * + ****************************************************************************/ + +int xmc4_uisc_baudrate(enum usic_channel_e channel, uint32_t baud, + uint32_t oversampling); + #endif /* __ARCH_ARM_SRC_XMC4_XMC4_USIC_H */ From 7d6ee0f2220194282b910a5572b6ebd55f316330 Mon Sep 17 00:00:00 2001 From: no1wudi <757509347@qq.com> Date: Mon, 20 Mar 2017 09:50:27 +0800 Subject: [PATCH 54/81] fix a typo --- arch/arm/src/stm32/stm32_comp.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/src/stm32/stm32_comp.h b/arch/arm/src/stm32/stm32_comp.h index 99d45bad636..c703689d171 100644 --- a/arch/arm/src/stm32/stm32_comp.h +++ b/arch/arm/src/stm32/stm32_comp.h @@ -150,7 +150,7 @@ enum stm32_comp_hyst_e COMP_HYST_LOW, COMP_HYST_MEDIUM, COMP_HYST_HIGH -}, +}; /* Power/Speed Modes */ From 8a3422f837a923e1cf1247a708ab2f9382c9690f Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 20 Mar 2017 11:21:32 -0600 Subject: [PATCH 55/81] XMC4xxx: Complete lowputc logic --- arch/arm/src/xmc4/chip/xmc4_usic.h | 40 ++-- arch/arm/src/xmc4/xmc4_lowputc.c | 296 ++++++++++++++++++++------ arch/arm/src/xmc4/xmc4_lowputc.h | 32 +-- arch/arm/src/xmc4/xmc4_serial.c | 164 +++++++------- arch/arm/src/xmc4/xmc4_usic.h | 23 +- configs/xmc4500-relax/include/board.h | 11 + 6 files changed, 383 insertions(+), 183 deletions(-) diff --git a/arch/arm/src/xmc4/chip/xmc4_usic.h b/arch/arm/src/xmc4/chip/xmc4_usic.h index 12d4bda2bcf..462ac44c955 100644 --- a/arch/arm/src/xmc4/chip/xmc4_usic.h +++ b/arch/arm/src/xmc4/chip/xmc4_usic.h @@ -515,15 +515,16 @@ */ #define USIC_DXCR_DSEL_SHIFT (0) /* Bits 0-2: Data Selection for Input Signal */ -#define USIC_DXCR_DSEL_MASK (7 << USIC_DX0CR_DSEL_SHIFT) -# define USIC_DXCR_DSEL_DXA (0 << USIC_DX0CR_DSEL_SHIFT) /* Data input DXnA selected */ -# define USIC_DXCR_DSEL_DXB (1 << USIC_DX0CR_DSEL_SHIFT) /* Data input DXnB selected */ -# define USIC_DXCR_DSEL_DXC (2 << USIC_DX0CR_DSEL_SHIFT) /* Data input DXnC selected */ -# define USIC_DXCR_DSEL_DXD (3 << USIC_DX0CR_DSEL_SHIFT) /* Data input DXnD selected */ -# define USIC_DXCR_DSEL_DXE (4 << USIC_DX0CR_DSEL_SHIFT) /* Data input DXnE selected */ -# define USIC_DXCR_DSEL_DXF (5 << USIC_DX0CR_DSEL_SHIFT) /* Data input DXnF selected */ -# define USIC_DXCR_DSEL_DXG (6 << USIC_DX0CR_DSEL_SHIFT) /* Data input DXnG selected */ -# define USIC_DXCR_DSEL_ONE (7 << USIC_DX0CR_DSEL_SHIFT) /* Data input is always 1 */ +#define USIC_DXCR_DSEL_MASK (7 << USIC_DXCR_DSEL_SHIFT) +# define USIC_DXCR_DSEL_DX(m) ((uint32_t)(m) << USIC_DXCR_DSEL_SHIFT) /* Data input DXnm selected */ +# define USIC_DXCR_DSEL_DXA (0 << USIC_DXCR_DSEL_SHIFT) /* Data input DXnA selected */ +# define USIC_DXCR_DSEL_DXB (1 << USIC_DXCR_DSEL_SHIFT) /* Data input DXnB selected */ +# define USIC_DXCR_DSEL_DXC (2 << USIC_DXCR_DSEL_SHIFT) /* Data input DXnC selected */ +# define USIC_DXCR_DSEL_DXD (3 << USIC_DXCR_DSEL_SHIFT) /* Data input DXnD selected */ +# define USIC_DXCR_DSEL_DXE (4 << USIC_DXCR_DSEL_SHIFT) /* Data input DXnE selected */ +# define USIC_DXCR_DSEL_DXF (5 << USIC_DXCR_DSEL_SHIFT) /* Data input DXnF selected */ +# define USIC_DXCR_DSEL_DXG (6 << USIC_DXCR_DSEL_SHIFT) /* Data input DXnG selected */ +# define USIC_DXCR_DSEL_ONE (7 << USIC_DXCR_DSEL_SHIFT) /* Data input is always 1 */ #define USIC_DX1CR_DCEN (1 << 3) /* Bit 3: Delay Compensation Enable (DX1CR only) */ #define USIC_DXCR_INSW (1 << 4) /* Bit 4: Input Switch */ #define USIC_DXCR_DFEN (1 << 5) /* Bit 5: Digital Filter Enable */ @@ -531,17 +532,19 @@ #define USIC_DXCR_DPOL (1 << 8) /* Bit 8: Data Polarity for DXn */ #define USIC_DXCR_SFSEL (1 << 9) /* Bit 9: Sampling Frequency Selection */ #define USIC_DXCR_CM_SHIFT (10) /* Bits 10-11: Combination Mode */ -#define USIC_DXCR_CM_MASK (3 << USIC_DX0CR_CM_SHIFT) -# define USIC_DXCR_CM_DISABLE (0 << USIC_DX0CR_CM_SHIFT) /* Trigger activation disabled */ -# define USIC_DXCR_CM_RISING (1 << USIC_DX0CR_CM_SHIFT) /* Rising edge activates DXnT */ -# define USIC_DXCR_CM_FALLING (2 << USIC_DX0CR_CM_SHIFT) /* Falling edge activates DXnT */ -# define USIC_DXCR_CM_BOTH (3 << USIC_DX0CR_CM_SHIFT) /* Both edges activate DXnT */ +#define USIC_DXCR_CM_MASK (3 << USIC_DXCR_CM_SHIFT) +# define USIC_DXCR_CM_DISABLE (0 << USIC_DXCR_CM_SHIFT) /* Trigger activation disabled */ +# define USIC_DXCR_CM_RISING (1 << USIC_DXCR_CM_SHIFT) /* Rising edge activates DXnT */ +# define USIC_DXCR_CM_FALLING (2 << USIC_DXCR_CM_SHIFT) /* Falling edge activates DXnT */ +# define USIC_DXCR_CM_BOTH (3 << USIC_DXCR_CM_SHIFT) /* Both edges activate DXnT */ #define USIC_DXCR_DXS (1 << 15) /* Bit 15: Synchronized Data Value */ /* Shift Control Register */ #define USIC_SCTR_SDIR (1 << 0) /* Bit 0: Shift Direction */ #define USIC_SCTR_PDL (1 << 1) /* Bit 1: Passive Data Level */ +# define USIC_SCTR_PDL0 (0) /* 0=Passive data level is 0 */ +# define USIC_SCTR_PDL1 (1 << 1) /* 1=Passive data level is 1 */ #define USIC_SCTR_DSM_SHIFT (2) /* Bits 2-3: Data Shift Mode */ #define USIC_SCTR_DSM_MASK (3 << USIC_SCTR_DSM_SHIFT) # define USIC_SCTR_DSM_1BIT (0 << USIC_SCTR_DSM_SHIFT) /* Data is shifted one bit at a time */ @@ -555,8 +558,8 @@ #define USIC_SCTR_TRM_SHIFT (8) /* Bits 8-9: Transmission Mode */ #define USIC_SCTR_TRM_MASK (3 << USIC_SCTR_TRM_SHIFT) # define USIC_SCTR_TRM_INACTIVE (0 << USIC_SCTR_TRM_SHIFT) /* Inactive */ -# define USIC_SCTR_TRM_0LEVEL (1 << USIC_SCTR_TRM_SHIFT) /* Active at 1-level */ -# define USIC_SCTR_TRM_1LEVEL (2 << USIC_SCTR_TRM_SHIFT) /* Active if it is at 0-level */ +# define USIC_SCTR_TRM_1LEVEL (1 << USIC_SCTR_TRM_SHIFT) /* Active at 1-level */ +# define USIC_SCTR_TRM_0LEVEL (2 << USIC_SCTR_TRM_SHIFT) /* Active at 0-level */ # define USIC_SCTR_TRM_ACTIVE (3 << USIC_SCTR_TRM_SHIFT) /* Active without regard to signal level */ #define USIC_SCTR_FLE_SHIFT (16) /* Bits 16-21: Frame Length */ #define USIC_SCTR_FLE_MASK (0x3f << USIC_SCTR_FLE_SHIFT) @@ -638,7 +641,8 @@ # define USIC_PCR_ASCMODE_SP(n) ((uint32_t)(n) << USIC_PCR_ASCMODE_SP_SHIFT) #define USIC_PCR_ASCMODE_PL_SHIFT (13) /* Bits 13-15: Pulse Length */ #define USIC_PCR_ASCMODE_PL_MASK (7 << USIC_PCR_ASCMODE_PL_SHIFT) - #define USIC_PCR_ASCMODE_PL(n) ((uint32_t)((n)-1) << USIC_PCR_ASCMODE_PL_SHIFT) + #define USIC_PCR_ASCMODE_PLBIT (0 << USIC_PCR_ASCMODE_PL_SHIFT) /* Pulse length = bit length */ + #define USIC_PCR_ASCMODE_PL(n) ((uint32_t)((n)-1) << USIC_PCR_ASCMODE_PL_SHIFT) /* Pulse length = n quanta */ #define USIC_PCR_ASCMODE_RSTEN (1 << 16) /* Bit 16: Receiver Status Enable */ #define USIC_PCR_ASCMODE_TSTEN (1 << 17) /* Bit 17: Transmitter Status Enable */ #define USIC_PCR_ASCMODE_MCLK (1 << 31) /* Bit 31: Master Clock Enable */ @@ -717,7 +721,7 @@ # define USIC_CCR_HPCEN_DX0_2 (3 << USIC_CCR_HPCEN_SHIFT) /* Port control enabled for DX0, DX[5:3] and DOUT[3:0] */ #define USIC_CCR_PM_SHIFT (8) /* Bits 8-9: Parity Mode */ #define USIC_CCR_PM_MASK (3 << USIC_CCR_PM_SHIFT) -# define USIC_CCR_PM_DISABLE (0 << USIC_CCR_PM_SHIFT) /* Parity generation is disabled */ +# define USIC_CCR_PM_NONE (0 << USIC_CCR_PM_SHIFT) /* Parity generation is disabled */ # define USIC_CCR_PM_EVEN (2 << USIC_CCR_PM_SHIFT) /* Even parity is selected */ # define USIC_CCR_PM_ODD (3 << USIC_CCR_PM_SHIFT) /* Odd parity is selected */ #define USIC_CCR_RSIEN (1 << 10) /* Bit 10: Receiver Start Interrupt Enable */ diff --git a/arch/arm/src/xmc4/xmc4_lowputc.c b/arch/arm/src/xmc4/xmc4_lowputc.c index 0c7a4fdc5ef..b92e723e66c 100644 --- a/arch/arm/src/xmc4/xmc4_lowputc.c +++ b/arch/arm/src/xmc4/xmc4_lowputc.c @@ -52,6 +52,7 @@ #include "chip/xmc4_usic.h" #include "chip/xmc4_pinmux.h" #include "xmc4_usic.h" +#include "xmc4_gpio.h" #include "xmc4_lowputc.h" /**************************************************************************** @@ -64,6 +65,7 @@ # if defined(CONFIG_UART0_SERIAL_CONSOLE) # define CONSOLE_CHAN USIC0_CHAN0 # define CONSOLE_FREQ BOARD_CORECLK_FREQ +# define CONSOLE_DX BOARD_UART0_DX # define CONSOLE_BAUD CONFIG_UART0_BAUD # define CONSOLE_BITS CONFIG_UART0_BITS # define CONSOLE_2STOP CONFIG_UART0_2STOP @@ -71,6 +73,7 @@ # elif defined(CONFIG_UART1_SERIAL_CONSOLE) # define CONSOLE_CHAN USIC0_CHAN1 # define CONSOLE_FREQ BOARD_CORECLK_FREQ +# define CONSOLE_DX BOARD_UART1_DX # define CONSOLE_BAUD CONFIG_UART1_BAUD # define CONSOLE_BITS CONFIG_UART1_BITS # define CONSOLE_2STOP CONFIG_UART1_2STOP @@ -78,6 +81,7 @@ # elif defined(CONFIG_UART2_SERIAL_CONSOLE) # define CONSOLE_CHAN USIC1_CHAN0 # define CONSOLE_FREQ BOARD_BUS_FREQ +# define CONSOLE_DX BOARD_UART2_DX # define CONSOLE_BAUD CONFIG_UART2_BAUD # define CONSOLE_BITS CONFIG_UART2_BITS # define CONSOLE_2STOP CONFIG_UART2_2STOP @@ -85,6 +89,7 @@ # elif defined(CONFIG_UART3_SERIAL_CONSOLE) # define CONSOLE_CHAN USIC1_CHAN1 # define CONSOLE_FREQ BOARD_BUS_FREQ +# define CONSOLE_DX BOARD_UART3_DX # define CONSOLE_BAUD CONFIG_UART3_BAUD # define CONSOLE_BITS CONFIG_UART3_BITS # define CONSOLE_2STOP CONFIG_UART3_2STOP @@ -92,6 +97,7 @@ # elif defined(CONFIG_UART4_SERIAL_CONSOLE) # define CONSOLE_CHAN USIC2_CHAN0 # define CONSOLE_FREQ BOARD_BUS_FREQ +# define CONSOLE_DX BOARD_UART4_DX # define CONSOLE_BAUD CONFIG_UART4_BAUD # define CONSOLE_BITS CONFIG_UART4_BITS # define CONSOLE_2STOP CONFIG_UART4_2STOP @@ -99,6 +105,7 @@ # elif defined(CONFIG_UART5_SERIAL_CONSOLE) # define CONSOLE_CHAN USIC2_CHAN1 # define CONSOLE_FREQ BOARD_BUS_FREQ +# define CONSOLE_DX BOARD_UART5_DX # define CONSOLE_BAUD CONFIG_UART5_BAUD # define CONSOLE_BITS CONFIG_UART5_BITS # define CONSOLE_2STOP CONFIG_UART5_2STOP @@ -108,10 +115,27 @@ # endif #endif /* HAVE_UART_CONSOLE */ +/* REVISIT: Oversampling is hardcoded to 16 here. Perhaps this should be in + * the config structure. + */ + +#define UART_OVERSAMPLING 16 + /**************************************************************************** - * Private Functions + * Private Data ****************************************************************************/ +#ifdef HAVE_UART_CONSOLE +static const struct uart_config_s g_console_config = +{ + .baud = CONSOLE_BAUD, + .dx = CONSOLE_DX, + .parity = CONSOLE_PARITY, + .nbits = CONSOLE_BITS, + .stop2 = CONSOLE_2STOP +}; +#endif + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -127,25 +151,26 @@ void up_lowputc(char ch) { #ifdef HAVE_UART_CONSOLE - /* Wait until the transmit data register is "empty" (TDRE). This state - * depends on the TX watermark setting and may not mean that the transmit - * buffer is truly empty. It just means that we can now add another - * character to the transmit buffer without exceeding the watermark. - * - * NOTE: UART0 has an 8-byte deep FIFO; the other UARTs have no FIFOs - * (1-deep). There appears to be no way to know when the FIFO is not - * full (other than reading the FIFO length and comparing the FIFO count). - * Hence, the FIFOs are not used in this implementation and, as a result - * TDRE indeed mean that the single output buffer is available. - * - * Performance on UART0 could be improved by enabling the FIFO and by - * redesigning all of the FIFO status logic. - */ -#warning Missing logic + uintptr_t base; + uint32_t regval; - /* Then write the character to the UART data register */ + /* Get the base address of the USIC registers associated with this channel */ -#warning Missing logic + base = xmc4_channel_baseaddress(CONSOLE_CHAN); + DEBUGASSERT(base != 0); + + /* Wait for the transmit buffer/fifo to be "not full." */ + + do + { + regval = getreg32(base + XMC4_USIC_TRBSR_OFFSET); + } + while ((regval & USIC_TRBSR_TFULL) != 0); + + /* Then write the character to the USIC IN register */ + + putreg32((uint32_t)ch, base + XMC4_USIC_IN_OFFSET); +#endif } /**************************************************************************** @@ -160,40 +185,55 @@ void up_lowputc(char ch) void xmc4_lowsetup(void) { - uint32_t regval; +#ifdef HAVE_UART_DEVICE + /* Configure UART pins for the all enabled UARTs. + * + * NOTE that the board must provide the definitions in the board.h header + * file of the form like: GPIO_UARTn_RXm and GPIO_UARTn_TXm where n is + * the USIC module, 0..(XMC_NUSIC-1), and m is the USIC channel number, 0 + * or 1. + * + * In additional, the board.h must provide the definition of + * BOARD_BOARD_UARTn_DX which indicates which input pin is selected, i.e. + * one of the 0=DXA, 1=DXB, ... 6=DXG. + */ - /* Enable peripheral clocking for all enabled UARTs. */ -#warning Missing logic - - /* Configure UART pins for the all enabled UARTs */ +#ifdef HAVE_UART0 + (void)xmc4_gpio_config(GPIO_UART0_RXD0); + (void)xmc4_gpio_config(GPIO_UART0_TXD0); +#endif +#ifdef HAVE_UART1 + (void)xmc4_gpio_config(GPIO_UART0_RXD1); + (void)xmc4_gpio_config(GPIO_UART0_TXD1); +#endif +#ifdef HAVE_UART2 + (void)xmc4_gpio_config(GPIO_UART0_RXD2); + (void)xmc4_gpio_config(GPIO_UART0_TXD2); +#endif +#ifdef HAVE_UART3 + (void)xmc4_gpio_config(GPIO_UART0_RXD3); + (void)xmc4_gpio_config(GPIO_UART0_TXD3); +#endif +#ifdef HAVE_UART4 + (void)xmc4_gpio_config(GPIO_UART0_RXD4); + (void)xmc4_gpio_config(GPIO_UART0_TXD4); +#endif +#ifdef HAVE_UART5 + (void)xmc4_gpio_config(GPIO_UART0_RXD5); + (void)xmc4_gpio_config(GPIO_UART0_TXD5); +#endif +#ifdef HAVE_UART_CONSOLE /* Configure the console (only) now. Other UARTs will be configured * when the serial driver is opened. */ - xmc4_uart_configure(CONSOLE_CHAN, CONSOLE_BAUD, CONSOLE_FREQ, \ - CONSOLE_PARITY, CONSOLE_BITS, CONSOLE_2STOP); + xmc4_uart_configure(CONSOLE_CHAN, &g_console_config); + +#endif /* HAVE_UART_CONSOLE */ #endif /* HAVE_UART_DEVICE */ } -/**************************************************************************** - * Name: xmc4_uart_reset - * - * Description: - * Reset a UART. - * - ****************************************************************************/ - -#ifdef HAVE_UART_DEVICE -void xmc4_uart_reset(uintptr_t uart_base) -{ - uint8_t regval; - - /* Just disable the transmitter and receiver */ -#warning Missing logic -} -#endif - /**************************************************************************** * Name: xmc4_uart_configure * @@ -207,12 +247,11 @@ void xmc4_uart_reset(uintptr_t uart_base) ****************************************************************************/ #ifdef HAVE_UART_DEVICE -int xmc4_uart_configure(enum usic_channel_e channel, uint32_t baud, - uint32_t clock, unsigned int parity, - unsigned int nbits, unsigned int stop2) +int xmc4_uart_configure(enum usic_channel_e channel, + FAR const struct uart_config_s *config) { uintptr_t base; - uint32_t oversampling; + uint32_t regval; int ret; /* Get the base address of the USIC registers associated with this channel */ @@ -231,30 +270,159 @@ int xmc4_uart_configure(enum usic_channel_e channel, uint32_t baud, return ret; } - ret = xmc4_uisc_baudrate(channel, baud, oversampling); + /* Configure the BAUD rate. + * REVISIT: Oversample is hardcoded to 16 here. Perhaps this should be in + * the config structure. + */ - /* Configure number of bits, stop bits and parity */ -#warning Missing logic + ret = xmc4_uisc_baudrate(channel, config->baud, UART_OVERSAMPLING); - /* Check for odd parity */ -#warning Missing logic + /* Configure frame format. + * + * - Pulse length for standard UART signaling, i.e. the 0 level is + * signaled during the complete bit time + * - Enable Sample Majority Decision sample mode + */ - /* Check for even parity */ -#warning Missing logic + regval = USIC_PCR_ASCMODE_PLBIT | USIC_PCR_ASCMODE_SMD; - /* Check for 9-bit operation */ -#warning Missing logic + /* - Sampling point set equal to the half of the oversampling period */ - /* Calculate baud settings (truncating) */ -#warning Missing logic + regval |= USIC_PCR_ASCMODE_SP((UART_OVERSAMPLING >> 1) + 1); - /* Configure FIFOs */ -#warning Missing logic + /* - Configure the number of stop bits */ - /* Enable RX and TX FIFOs */ -#warning Missing logic + if (config->stop2) + { + regval |= USIC_PCR_ASCMODE_STPB; + } - /* Now we can (re-)enable the transmitter and receiver */ -#warning Missing logic + putreg32(regval, base + XMC4_USIC_PCR_OFFSET); + + /* Configure Shift Control Register: + * + * - Set passive data level, high + * - Transmission Mode: The shift control signal is considered active if + * it is at 1-level. This is the setting to be programmed to allow + * data transfers. + * - Set word length + * - Set frame length equal to the word length + */ + + regval = USIC_SCTR_PDL0 | USIC_SCTR_TRM_1LEVEL | + USIC_SCTR_FLE(config->nbits) | USIC_SCTR_WLE(config->nbits); + putreg32(regval, base + XMC4_USIC_SCTR_OFFSET); + + /* Enable transfer buffer */ + + regval = USIC_TCSR_TDEN_TDIV | USIC_TCSR_TDSSM; + putreg32(regval, base + XMC4_USIC_TCSR_OFFSET); + + /* Clear protocol status */ + + putreg32(0xffffffff, base + XMC4_USIC_PSCR_OFFSET); + + /* Configure parity */ + + if (config->parity == 1) + { + /* Odd parrity */ + + regval = USIC_CCR_PM_ODD; + } + else if (config->parity == 2) + { + /* Even parity */ + + regval = USIC_CCR_PM_EVEN; + } + else + { + /* No parity */ + + DEBUGASSERT(config->parity == 0); + regval = USIC_CCR_PM_NONE; + } + + putreg32(regval, base + XMC4_USIC_CCR_OFFSET); + + /* Set DX0CR input source path */ + + regval = getreg32(base + XMC4_USIC_DX0CR_OFFSET); + regval &= ~USIC_DXCR_DSEL_MASK; + regval |= USIC_DXCR_DSEL_DX(config->dx); + putreg32(regval, base + XMC4_USIC_DX0CR_OFFSET); + + /* Disable transmit FIFO */ + + regval = getreg32(base + XMC4_USIC_TBCTR_OFFSET); + regval &= ~USIC_TBCTR_SIZE_MASK; + putreg32(regval, base + XMC4_USIC_TBCTR_OFFSET); + + /* Configure transmit FIFO + * + * - DPTR = 16 + * - LIMIT = 1 + * - STBTEN = 0, the trigger of the standard transmit buffer event is + * based on the transition of the fill level from equal to below the + * limit, not the fact being below + * - SIZE = 16 + * - LOF = 0, A standard transmit buffer event occurs when the filling + * level equals the limit value and gets lower due to transmission of + * a data word + */ + + regval &= ~(USIC_TBCTR_DPTR_MASK | USIC_TBCTR_LIMIT_MASK | USIC_RBCTR_SRBTEN | + USIC_TBCTR_SIZE_MASK | USIC_RBCTR_LOF); + regval |= (USIC_TBCTR_DPTR(16) | USIC_TBCTR_LIMIT(1) | USIC_TBCTR_SIZE_16); + putreg32(regval, base + XMC4_USIC_TBCTR_OFFSET); + + /* Disable the receive FIFO */ + + regval = getreg32(base + XMC4_USIC_RBCTR_OFFSET); + regval &= ~USIC_RBCTR_SIZE_MASK; + putreg32(regval, base + XMC4_USIC_RBCTR_OFFSET); + + /* Configure receive FIFO. + * + * - DPTR = 0 + * - LIMIT = 15 + * - SIZE = 16 + * - LOF = 1, A standard receive buffer event occurs when the filling + * level equals the limit value and gets bigger due to the reception + * of a new data word + */ + + regval &= ~(USIC_RBCTR_DPTR_MASK | USIC_RBCTR_LIMIT_MASK | USIC_RBCTR_SIZE_MASK); + regval |= (USIC_RBCTR_DPTR(0) | USIC_RBCTR_LIMIT(15) | USIC_RBCTR_SIZE_16 | USIC_RBCTR_LOF); + putreg32(regval, base + XMC4_USIC_RBCTR_OFFSET); + + /* Start UART */ + + regval = getreg32(base + XMC4_USIC_CCR_OFFSET); + regval &= ~USIC_CCR_MODE_MASK; + regval |= USIC_CCR_MODE_ASC; + putreg32(regval, base + XMC4_USIC_CCR_OFFSET); + + /* Set service request for UART protocol events. + * + * Set channel 0 protocol events on sevice request 0 + * Set channel 1 protocol events on sevice request 1 + */ + + regval = getreg32(base + XMC4_USIC_INPR_OFFSET); + regval &= ~USIC_INPR_PINP_MASK; + + if (((unsigned int)channel & 1) != 0) + { + regval |= USIC_INPR_PINP_SR0; + } + else + { + regval |= USIC_INPR_PINP_SR1; + } + + putreg32(regval, base + XMC4_USIC_INPR_OFFSET); + return OK; } #endif diff --git a/arch/arm/src/xmc4/xmc4_lowputc.h b/arch/arm/src/xmc4/xmc4_lowputc.h index fa9d8ce16bd..f8016c3d78e 100644 --- a/arch/arm/src/xmc4/xmc4_lowputc.h +++ b/arch/arm/src/xmc4/xmc4_lowputc.h @@ -47,6 +47,21 @@ #include "xmc4_config.h" #include "xmc4_usic.h" +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* This structure provides the configuration of one UART channel */ + +struct uart_config_s +{ + uint32_t baud; /* Desired BAUD rate */ + uint8_t dx; /* Input pin 0=DXA, 1=DXB, ... 6=DXG */ + uint8_t parity; /* Parity selection: 0=none, 1=odd, 2=even */ + uint8_t nbits; /* Number of bits per word */ + bool stop2; /* true=2 stop bits; false=1 stop bit */ +}; + /**************************************************************************** * Public Function Prototypes ****************************************************************************/ @@ -63,18 +78,6 @@ void xmc4_lowsetup(void); -/**************************************************************************** - * Name: xmc4_uart_reset - * - * Description: - * Reset a UART. - * - ****************************************************************************/ - -#ifdef HAVE_UART_DEVICE -void xmc4_uart_reset(uintptr_t uart_base); -#endif - /**************************************************************************** * Name: xmc4_uart_configure * @@ -88,9 +91,8 @@ void xmc4_uart_reset(uintptr_t uart_base); ****************************************************************************/ #ifdef HAVE_UART_DEVICE -int xmc4_uart_configure(enum usic_channel_e channel, uint32_t baud, - uint32_t clock, unsigned int parity, - unsigned int nbits, unsigned int stop2); +int xmc4_uart_configure(enum usic_channel_e channel, + FAR const struct uart_config_s *config); #endif /**************************************************************************** diff --git a/arch/arm/src/xmc4/xmc4_serial.c b/arch/arm/src/xmc4/xmc4_serial.c index 78db3fd792d..f1cccd78092 100644 --- a/arch/arm/src/xmc4/xmc4_serial.c +++ b/arch/arm/src/xmc4/xmc4_serial.c @@ -227,17 +227,18 @@ * Private Types ****************************************************************************/ +/* This structure provides the state of one UART device */ + struct xmc4_dev_s { uintptr_t uartbase; /* Base address of UART registers */ - uint32_t baud; /* Configured baud */ - uint32_t clock; /* Clocking frequency of the UART module */ uint8_t channel; /* USIC channel identification */ uint8_t irqs; /* Status IRQ associated with this UART (for enable) */ uint8_t ie; /* Interrupts enabled */ - uint8_t parity; /* 0=none, 1=odd, 2=even */ - uint8_t bits; /* Number of bits (8 or 9) */ - uint8_t stop2; /* Use 2 stop bits */ + + /* UART configuration */ + + struct uart_config_s config; }; /**************************************************************************** @@ -314,13 +315,16 @@ static char g_uart5txbuffer[CONFIG_UART5_TXBUFSIZE]; static struct xmc4_dev_s g_uart0priv = { .uartbase = XMC4_USIC0_CH0_BASE, - .clock = BOARD_CORECLK_FREQ, .channel = (uint8_t)USIC0_CHAN0, - .baud = CONFIG_UART0_BAUD, - .irqs = XMC4_IRQ_USIC0, - .parity = CONFIG_UART0_PARITY, - .bits = CONFIG_UART0_BITS, - .stop2 = CONFIG_UART0_2STOP, + .irqs = XMC4_IRQ_USIC0_SR0, + .config = + { + .baud = CONFIG_UART0_BAUD, + .dx = BOARD_UART0_DX, + .parity = CONFIG_UART0_PARITY, + .nbits = CONFIG_UART0_BITS, + .stop2 = CONFIG_UART0_2STOP, + } }; static uart_dev_t g_uart0port = @@ -346,13 +350,16 @@ static uart_dev_t g_uart0port = static struct xmc4_dev_s g_uart1priv = { .uartbase = XMC4_USIC0_CH1_BASE, - .clock = BOARD_CORECLK_FREQ, .channel = (uint8_t)USIC0_CHAN1, - .baud = CONFIG_UART1_BAUD, - .irqs = XMC4_IRQ_USIC1, - .parity = CONFIG_UART1_PARITY, - .bits = CONFIG_UART1_BITS, - .stop2 = CONFIG_UART1_2STOP, + .irqs = XMC4_IRQ_USIC0_SR1, + .config = + { + .baud = CONFIG_UART1_BAUD, + .dx = BOARD_UART1_DX, + .parity = CONFIG_UART1_PARITY, + .nbits = CONFIG_UART1_BITS, + .stop2 = CONFIG_UART1_2STOP, + } }; static uart_dev_t g_uart1port = @@ -378,13 +385,16 @@ static uart_dev_t g_uart1port = static struct xmc4_dev_s g_uart2priv = { .uartbase = XMC4_USIC1_CH0_BASE, - .clock = BOARD_BUS_FREQ, .channel = (uint8_t)USIC1_CHAN0, - .baud = CONFIG_UART2_BAUD, - .irqs = XMC4_IRQ_USIC2, - .parity = CONFIG_UART2_PARITY, - .bits = CONFIG_UART2_BITS, - .stop2 = CONFIG_UART2_2STOP, + .irqs = XMC4_IRQ_USIC1_SR0, + .config = + { + .baud = CONFIG_UART2_BAUD, + .dx = BOARD_UART2_DX, + .parity = CONFIG_UART2_PARITY, + .nbits = CONFIG_UART2_BITS, + .stop2 = CONFIG_UART2_2STOP, + } }; static uart_dev_t g_uart2port = @@ -410,13 +420,16 @@ static uart_dev_t g_uart2port = static struct xmc4_dev_s g_uart3priv = { .uartbase = XMC4_USIC1_CH1_BASE, - .clock = BOARD_BUS_FREQ, .channel = (uint8_t)USIC1_CHAN1, - .baud = CONFIG_UART3_BAUD, - .irqs = XMC4_IRQ_USIC3, - .parity = CONFIG_UART3_PARITY, - .bits = CONFIG_UART3_BITS, - .stop2 = CONFIG_UART3_2STOP, + .irqs = XMC4_IRQ_USIC1_SR1, + .config = + { + .baud = CONFIG_UART3_BAUD, + .dx = BOARD_UART3_DX, + .parity = CONFIG_UART3_PARITY, + .nbits = CONFIG_UART3_BITS, + .stop2 = CONFIG_UART3_2STOP, + } }; static uart_dev_t g_uart3port = @@ -442,13 +455,16 @@ static uart_dev_t g_uart3port = static struct xmc4_dev_s g_uart4priv = { .uartbase = XMC4_USIC2_CH0_BASE, - .clock = BOARD_BUS_FREQ, .channel = (uint8_t)USIC2_CHAN0, - .baud = CONFIG_UART4_BAUD, - .irqs = XMC4_IRQ_USIC4, - .parity = CONFIG_UART4_PARITY, - .bits = CONFIG_UART4_BITS, - .stop2 = CONFIG_UART4_2STOP, + .irqs = XMC4_IRQ_USIC2_SR0, + .config = + { + .baud = CONFIG_UART4_BAUD, + .dx = BOARD_UART4_DX, + .parity = CONFIG_UART4_PARITY, + .nbits = CONFIG_UART4_BITS, + .stop2 = CONFIG_UART4_2STOP, + } }; static uart_dev_t g_uart4port = @@ -474,13 +490,16 @@ static uart_dev_t g_uart4port = static struct xmc4_dev_s g_uart5priv = { .uartbase = XMC4_USIC2_CH1_BASE, - .clock = BOARD_BUS_FREQ, .channel = (uint8_t)USIC2_CHAN1, - .baud = CONFIG_UART5_BAUD, - .irqs = XMC4_IRQ_USIC5, - .parity = CONFIG_UART5_PARITY, - .bits = CONFIG_UART5_BITS, - .stop2 = CONFIG_UART5_2STOP, + .irqs = XMC4_IRQ_USIC2_SR1, + .config = + { + .baud = CONFIG_UART5_BAUD, + .dx = BOARD_UART5_DX, + .parity = CONFIG_UART5_PARITY, + .nbits = CONFIG_UART5_BITS, + .stop2 = CONFIG_UART5_2STOP, + } }; static uart_dev_t g_uart5port = @@ -508,7 +527,7 @@ static uart_dev_t g_uart5port = * Name: up_serialin ****************************************************************************/ -static inline uint8_t up_serialin(struct xmc4_dev_s *priv, int offset) +static inline uint32_t up_serialin(struct xmc4_dev_s *priv, int offset) { return getreg8(priv->uartbase + offset); } @@ -517,7 +536,7 @@ static inline uint8_t up_serialin(struct xmc4_dev_s *priv, int offset) * Name: up_serialout ****************************************************************************/ -static inline void up_serialout(struct xmc4_dev_s *priv, int offset, uint8_t value) +static inline void up_serialout(struct xmc4_dev_s *priv, int offset, uint32_t value) { putreg8(value, priv->uartbase + offset); } @@ -586,8 +605,7 @@ static int xmc4_setup(struct uart_dev_s *dev) /* Configure the UART as an RS-232 UART */ - xmc4_uart_configure(priv->uartbase, priv->baud, priv->clock, - priv->parity, priv->bits, priv->stop2); + xmc4_uart_configure(priv->uartbase, &priv->config); #endif /* Make sure that all interrupts are disabled */ @@ -615,7 +633,7 @@ static void xmc4_shutdown(struct uart_dev_s *dev) /* Reset hardware and disable Rx and Tx */ - xmc4_uart_reset(priv->uartbase); + xmc4_uart_disable(priv->channel); } /**************************************************************************** @@ -807,32 +825,23 @@ static int xmc4_ioctl(struct file *filep, int cmd, unsigned long arg) static int xmc4_receive(struct uart_dev_s *dev, uint32_t *status) { struct xmc4_dev_s *priv = (struct xmc4_dev_s *)dev->priv; - uint8_t s1; + uint32_t outr; - /* Get error status information: - * - * FE: Framing error. To clear FE, read S1 with FE set and then read - * read UART data register (D). - * NF: Noise flag. To clear NF, read S1 and then read the UART data - * register (D). - * PF: Parity error flag. To clear PF, read S1 and then read the UART - * data register (D). - */ + /* Get input data along with receiver control information */ - s1 = up_serialin(priv, XMC4_UART_S1_OFFSET); + outr = up_serialin(priv, XMC4_UART_S1_OFFSET); + up_serialout(priv, XMC4_USIC_OUTR_OFFSET, (uint32_t)ch); - /* Return status information */ + /* Return receiver control information */ if (status) { - *status = (uint32_t)s1; + *status = outr >> USIC_OUTR_RCI_SHIFT; } - /* Then return the actual received byte. Reading S1 then D clears all - * RX errors. - */ + /* Then return the actual received data. */ - return (int)up_serialin(priv, XMC4_UART_D_OFFSET); + return outr & USIC_OUTR_DSR_MASK; } /**************************************************************************** @@ -885,14 +894,12 @@ static void xmc4_rxint(struct uart_dev_s *dev, bool enable) static bool xmc4_rxavailable(struct uart_dev_s *dev) { struct xmc4_dev_s *priv = (struct xmc4_dev_s *)dev->priv; - /* Return true if the receive data register is full (RDRF). NOTE: If - * FIFOS are enabled, this does not mean that the FIFO is full, - * rather, it means that the number of bytes in the RX FIFO has - * exceeded the watermark setting. There may actually be RX data - * available! - */ + uint32_t regval; - return (up_serialin(priv, XMC4_UART_S1_OFFSET) & UART_S1_RDRF) != 0; + /* Return true if the transmit buffer/fifo is not "empty." */ + + regval = up_serialin(priv, XMC4_UART_TRBSR_OFFSET); + return ((regval & USIC_TRBSR_REMPTY) == 0); } /**************************************************************************** @@ -906,7 +913,7 @@ static bool xmc4_rxavailable(struct uart_dev_s *dev) static void xmc4_send(struct uart_dev_s *dev, int ch) { struct xmc4_dev_s *priv = (struct xmc4_dev_s *)dev->priv; - up_serialout(priv, XMC4_UART_D_OFFSET, (uint8_t)ch); + up_serialout(priv, XMC4_USIC_IN_OFFSET, (uint32_t)ch); } /**************************************************************************** @@ -960,15 +967,12 @@ static void xmc4_txint(struct uart_dev_s *dev, bool enable) static bool xmc4_txready(struct uart_dev_s *dev) { struct xmc4_dev_s *priv = (struct xmc4_dev_s *)dev->priv; + uint32_t regval; - /* Return true if the transmit data register is "empty." NOTE: If - * FIFOS are enabled, this does not mean that the FIFO is empty, - * rather, it means that the number of bytes in the TX FIFO is - * below the watermark setting. There may actually be space for - * additional TX data. - */ + /* Return true if the transmit buffer/fifo is "not full." */ - return (up_serialin(priv, XMC4_UART_S1_OFFSET) & UART_S1_TDRE) != 0; + regval = up_serialin(priv, XMC4_UART_TRBSR_OFFSET); + return ((regval & USIC_TRBSR_TFULL) == 0); } /**************************************************************************** @@ -982,10 +986,12 @@ static bool xmc4_txready(struct uart_dev_s *dev) static bool xmc4_txempty(struct uart_dev_s *dev) { struct xmc4_dev_s *priv = (struct xmc4_dev_s *)dev->priv; + uint32_t regval; /* Return true if the transmit buffer/fifo is "empty." */ - return (up_serialin(priv, XMC4_UART_SFIFO_OFFSET) & UART_SFIFO_TXEMPT) != 0; + regval = up_serialin(priv, XMC4_UART_TRBSR_OFFSET); + return ((regval & USIC_TRBSR_TEMPTY) != 0); } /**************************************************************************** diff --git a/arch/arm/src/xmc4/xmc4_usic.h b/arch/arm/src/xmc4/xmc4_usic.h index 5c5e78fdb90..910846bc85e 100644 --- a/arch/arm/src/xmc4/xmc4_usic.h +++ b/arch/arm/src/xmc4/xmc4_usic.h @@ -44,10 +44,6 @@ #include #include "xmc4_config.h" -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - /**************************************************************************** * Public Types ****************************************************************************/ @@ -56,9 +52,9 @@ enum usic_e { - USIC0 = 0, /* USIC0 */ - USIC1 = 1, /* USIC1 */ - USIC2 = 2 /* USIC2 */ + USIC0 = 0, /* USIC0 */ + USIC1 = 1, /* USIC1 */ + USIC2 = 2 /* USIC2 */ }; /* This enumeration identifies USIC channels */ @@ -73,6 +69,19 @@ enum usic_channel_e USIC2_CHAN1 = 5 /* USIC2, Channel 1 */ }; +/* This enumeration defines values for the dx input selection */ + +enum uart_dx_e +{ + USIC_DXA = 0, /* USICn_DXmA */ + USIC_DXB = 1, /* USICn_DXmB */ + USIC_DXC = 2, /* USICn_DXmC */ + USIC_DXD = 3, /* USICn_DXmD */ + USIC_DXE = 4, /* USICn_DXmE */ + USIC_DXF = 5, /* USICn_DXmF */ + USIC_DXG = 6 /* USICn_DXmG */ +}; + /**************************************************************************** * Public Function Prototypes ****************************************************************************/ diff --git a/configs/xmc4500-relax/include/board.h b/configs/xmc4500-relax/include/board.h index dbc2440902d..e90e3f730c6 100644 --- a/configs/xmc4500-relax/include/board.h +++ b/configs/xmc4500-relax/include/board.h @@ -192,6 +192,17 @@ #define BUTTON_0_BIT (1 << BUTTON_0) #define BUTTON_1_BIT (1 << BUTTON_1) +/* USIC0 ****************************************************************************/ +/* USIC0 CH0 is used as UART0 + * + * RX - P1.4 + * TX - P1.5 + */ + +#define BOARD_UART0_DX USIC_DXB +#define GPIO_UART0_RXD0 GPIO_U0C0_DX0B +#define GPIO_UART0_TXD0 (GPIO_U0C0_DOUT0_3 | GPIO_PADA1P_STRONGSOFT | GPIO_OUTPUT_SET) + /************************************************************************************ * Public Data ************************************************************************************/ From 4519b679af9c23df140469ba8ff39e0ed5b4d9fa Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 20 Mar 2017 12:47:26 -0600 Subject: [PATCH 56/81] XMC4xxx: Finish code for USIC serial driver. --- arch/arm/src/xmc4/xmc4_lowputc.c | 12 +- arch/arm/src/xmc4/xmc4_serial.c | 236 ++++++++++++++++--------------- 2 files changed, 128 insertions(+), 120 deletions(-) diff --git a/arch/arm/src/xmc4/xmc4_lowputc.c b/arch/arm/src/xmc4/xmc4_lowputc.c index b92e723e66c..fcb930d1b90 100644 --- a/arch/arm/src/xmc4/xmc4_lowputc.c +++ b/arch/arm/src/xmc4/xmc4_lowputc.c @@ -404,22 +404,22 @@ int xmc4_uart_configure(enum usic_channel_e channel, regval |= USIC_CCR_MODE_ASC; putreg32(regval, base + XMC4_USIC_CCR_OFFSET); - /* Set service request for UART protocol events. + /* Set service request for UART protocol, receiver, and transmitter events. * - * Set channel 0 protocol events on sevice request 0 - * Set channel 1 protocol events on sevice request 1 + * Set channel 0 events on sevice request 0 + * Set channel 1 events on sevice request 1 */ regval = getreg32(base + XMC4_USIC_INPR_OFFSET); - regval &= ~USIC_INPR_PINP_MASK; + regval &= ~(USIC_INPR_TBINP_MASK | USIC_INPR_RINP_MASK | USIC_INPR_PINP_MASK); if (((unsigned int)channel & 1) != 0) { - regval |= USIC_INPR_PINP_SR0; + regval |= (USIC_INPR_TBINP_SR1 | USIC_INPR_RINP_SR1 | USIC_INPR_PINP_SR1); } else { - regval |= USIC_INPR_PINP_SR1; + regval |= (USIC_INPR_TBINP_SR0 | USIC_INPR_RINP_SR0 | USIC_INPR_PINP_SR0); } putreg32(regval, base + XMC4_USIC_INPR_OFFSET); diff --git a/arch/arm/src/xmc4/xmc4_serial.c b/arch/arm/src/xmc4/xmc4_serial.c index f1cccd78092..82d53b730b6 100644 --- a/arch/arm/src/xmc4/xmc4_serial.c +++ b/arch/arm/src/xmc4/xmc4_serial.c @@ -223,6 +223,17 @@ # define UART5_ASSIGNED 1 #endif +/* Event sets */ + +#ifdef CONFIG_DEBUG_FEATURES +# define CCR_RX_EVENTS (USIC_CCR_RIEN | USIC_CCR_DLIEN) +#else +# define CCR_RX_EVENTS (USIC_CCR_RIEN) +#endif + +#define CCR_TX_EVENTS (USIC_CCR_TBIEN) +#define CCR_ALL_EVENTS (CCR_RX_EVENTS | CCR_TX_EVENTS) + /**************************************************************************** * Private Types ****************************************************************************/ @@ -233,8 +244,8 @@ struct xmc4_dev_s { uintptr_t uartbase; /* Base address of UART registers */ uint8_t channel; /* USIC channel identification */ - uint8_t irqs; /* Status IRQ associated with this UART (for enable) */ - uint8_t ie; /* Interrupts enabled */ + uint8_t irq; /* Status IRQ associated with this UART (for enable) */ + uint8_t ccr; /* Interrupts enabled in CCR */ /* UART configuration */ @@ -316,7 +327,7 @@ static struct xmc4_dev_s g_uart0priv = { .uartbase = XMC4_USIC0_CH0_BASE, .channel = (uint8_t)USIC0_CHAN0, - .irqs = XMC4_IRQ_USIC0_SR0, + .irq = XMC4_IRQ_USIC0_SR0, .config = { .baud = CONFIG_UART0_BAUD, @@ -351,7 +362,7 @@ static struct xmc4_dev_s g_uart1priv = { .uartbase = XMC4_USIC0_CH1_BASE, .channel = (uint8_t)USIC0_CHAN1, - .irqs = XMC4_IRQ_USIC0_SR1, + .irq = XMC4_IRQ_USIC0_SR1, .config = { .baud = CONFIG_UART1_BAUD, @@ -386,7 +397,7 @@ static struct xmc4_dev_s g_uart2priv = { .uartbase = XMC4_USIC1_CH0_BASE, .channel = (uint8_t)USIC1_CHAN0, - .irqs = XMC4_IRQ_USIC1_SR0, + .irq = XMC4_IRQ_USIC1_SR0, .config = { .baud = CONFIG_UART2_BAUD, @@ -421,7 +432,7 @@ static struct xmc4_dev_s g_uart3priv = { .uartbase = XMC4_USIC1_CH1_BASE, .channel = (uint8_t)USIC1_CHAN1, - .irqs = XMC4_IRQ_USIC1_SR1, + .irq = XMC4_IRQ_USIC1_SR1, .config = { .baud = CONFIG_UART3_BAUD, @@ -456,7 +467,7 @@ static struct xmc4_dev_s g_uart4priv = { .uartbase = XMC4_USIC2_CH0_BASE, .channel = (uint8_t)USIC2_CHAN0, - .irqs = XMC4_IRQ_USIC2_SR0, + .irq = XMC4_IRQ_USIC2_SR0, .config = { .baud = CONFIG_UART4_BAUD, @@ -491,7 +502,7 @@ static struct xmc4_dev_s g_uart5priv = { .uartbase = XMC4_USIC2_CH1_BASE, .channel = (uint8_t)USIC2_CHAN1, - .irqs = XMC4_IRQ_USIC2_SR1, + .irq = XMC4_IRQ_USIC2_SR1, .config = { .baud = CONFIG_UART5_BAUD, @@ -524,68 +535,96 @@ static uart_dev_t g_uart5port = ****************************************************************************/ /**************************************************************************** - * Name: up_serialin + * Name: xmc4_serialin ****************************************************************************/ -static inline uint32_t up_serialin(struct xmc4_dev_s *priv, int offset) +static inline uint32_t xmc4_serialin(struct xmc4_dev_s *priv, + unsigned int offset) { - return getreg8(priv->uartbase + offset); + return getreg32(priv->uartbase + offset); } /**************************************************************************** - * Name: up_serialout + * Name: xmc4_serialout ****************************************************************************/ -static inline void up_serialout(struct xmc4_dev_s *priv, int offset, uint32_t value) +static inline void xmc4_serialout(struct xmc4_dev_s *priv, + unsigned int offset, uint32_t value) { - putreg8(value, priv->uartbase + offset); + putreg32(value, priv->uartbase + offset); } /**************************************************************************** - * Name: up_setuartint + * Name: xmc4_modifyreg ****************************************************************************/ -static void up_setuartint(struct xmc4_dev_s *priv) +static inline void xmc4_modifyreg(struct xmc4_dev_s *priv, unsigned int offset, + uint32_t setbits, uint32_t clrbits) { irqstate_t flags; - uint8_t regval; + uintptr_t regaddr = priv->uartbase + offset; + uint32_t regval; - /* Re-enable/re-disable interrupts corresponding to the state of bits in ie */ -#warning Missing logic + flags = enter_critical_section(); + + regval = getreg32(regaddr); + regval &= ~clrbits; + regval |= setbits; + putreg32(regval, regaddr); leave_critical_section(flags); } /**************************************************************************** - * Name: up_restoreuartint + * Name: xmc4_setuartint ****************************************************************************/ -static void up_restoreuartint(struct xmc4_dev_s *priv, uint8_t ie) +static void xmc4_setuartint(struct xmc4_dev_s *priv) { irqstate_t flags; - /* Re-enable/re-disable interrupts corresponding to the state of bits in ie */ + /* Re-enable/re-disable event interrupts corresponding to the state of + * bits in priv->ccr. + */ - flags = enter_critical_section(); -#warning Missing logic + flags = enter_critical_section(); + xmc4_modifyreg(priv, XMC4_USIC_CCR_OFFSET, CCR_ALL_EVENTS, priv->ccr); leave_critical_section(flags); } /**************************************************************************** - * Name: up_disableuartint + * Name: xmc4_restoreuartint ****************************************************************************/ -static void up_disableuartint(struct xmc4_dev_s *priv, uint8_t *ie) +static void xmc4_restoreuartint(struct xmc4_dev_s *priv, uint32_t ccr) +{ + irqstate_t flags; + + /* Re-enable/re-disable event interrupts corresponding to the state of bits + * in the ccr argument. + */ + + flags = enter_critical_section(); + priv->ccr = ccr; + xmc4_setuartint(priv); + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: xmc4_disableuartint + ****************************************************************************/ + +static void xmc4_disableuartint(struct xmc4_dev_s *priv, uint32_t *ccr) { irqstate_t flags; flags = enter_critical_section(); - if (ie) + if (ccr) { - *ie = priv->ie; + *ccr = priv->ccr; } - up_restoreuartint(priv, 0); + xmc4_restoreuartint(priv, 0); leave_critical_section(flags); } @@ -610,7 +649,7 @@ static int xmc4_setup(struct uart_dev_s *dev) /* Make sure that all interrupts are disabled */ - up_restoreuartint(priv, 0); + xmc4_restoreuartint(priv, 0); return OK; } @@ -629,7 +668,7 @@ static void xmc4_shutdown(struct uart_dev_s *dev) /* Disable interrupts */ - up_restoreuartint(priv, 0); + xmc4_restoreuartint(priv, 0); /* Reset hardware and disable Rx and Tx */ @@ -660,10 +699,10 @@ static int xmc4_attach(struct uart_dev_s *dev) * disabled in the C2 register. */ - ret = irq_attach(priv->irqs, xmc4_interrupt, dev); + ret = irq_attach(priv->irq, xmc4_interrupt, dev); if (ret == OK) { - up_enable_irq(priv->irqs); + up_enable_irq(priv->irq); } return ret; @@ -685,12 +724,12 @@ static void xmc4_detach(struct uart_dev_s *dev) /* Disable interrupts */ - up_restoreuartint(priv, 0); - up_disable_irq(priv->irqs); + xmc4_restoreuartint(priv, 0); + up_disable_irq(priv->irq); /* Detach from the interrupt(s) */ - irq_detach(priv->irqs); + irq_detach(priv->irq); } /**************************************************************************** @@ -708,10 +747,10 @@ static void xmc4_detach(struct uart_dev_s *dev) static int xmc4_interrupt(int irq, void *context, FAR void *arg) { struct uart_dev_s *dev = (struct uart_dev_s *)arg; - struct xmc4_dev_s *priv; - int passes; - uint8_t s1; - bool handled; + struct xmc4_dev_s *priv; + int passes; + uint32_t regval; + bool handled; DEBUGASSERT(dev != NULL && dev->priv != NULL); priv = (struct xmc4_dev_s *)dev->priv; @@ -725,23 +764,12 @@ static int xmc4_interrupt(int irq, void *context, FAR void *arg) { handled = false; - /* Read status register 1 */ - - s1 = up_serialin(priv, XMC4_UART_S1_OFFSET); - - /* Handle incoming, receive bytes */ - - /* Check if the receive data register is full (RDRF). NOTE: If - * FIFOS are enabled, this does not mean that the FIFO is full, - * rather, it means that the number of bytes in the RX FIFO has - * exceeded the watermark setting. There may actually be RX data - * available! - * - * The RDRF status indication is cleared when the data is read from - * the RX data register. + /* Handle incoming, receive bytes. + * Check if the received FIFO is not empty. */ -#warning Missing logic + regval = xmc4_serialin(priv, XMC4_USIC_TRBSR_OFFSET); + if ((regval & USIC_TRBSR_REMPTY) == 0) { /* Process incoming bytes */ @@ -749,25 +777,23 @@ static int xmc4_interrupt(int irq, void *context, FAR void *arg) handled = true; } - /* Handle outgoing, transmit bytes */ - - /* Check if the transmit data register is "empty." NOTE: If FIFOS - * are enabled, this does not mean that the FIFO is empty, rather, - * it means that the number of bytes in the TX FIFO is below the - * watermark setting. There could actually be space for additional TX - * data. - * - * The TDRE status indication is cleared when the data is written to - * the TX data register. + /* Handle outgoing, transmit bytes. + * Check if the received FIFO is not full. */ -#warning Missing logic + regval = xmc4_serialin(priv, XMC4_USIC_TRBSR_OFFSET); + if ((regval & USIC_TRBSR_TFULL) == 0) { /* Process outgoing bytes */ uart_xmitchars(dev); handled = true; } + +#ifdef CONFIG_DEBUG_FEATURES + /* Check for error conditions */ +#warning Misssing logic +#endif } return OK; @@ -829,8 +855,7 @@ static int xmc4_receive(struct uart_dev_s *dev, uint32_t *status) /* Get input data along with receiver control information */ - outr = up_serialin(priv, XMC4_UART_S1_OFFSET); - up_serialout(priv, XMC4_USIC_OUTR_OFFSET, (uint32_t)ch); + outr = xmc4_serialin(priv, XMC4_USIC_OUTR_OFFSET); /* Return receiver control information */ @@ -860,24 +885,19 @@ static void xmc4_rxint(struct uart_dev_s *dev, bool enable) flags = enter_critical_section(); if (enable) { +#ifndef CONFIG_SUPPRESS_SERIAL_INTS /* Receive an interrupt when their is anything in the Rx data register (or an Rx * timeout occurs). */ -#ifndef CONFIG_SUPPRESS_SERIAL_INTS - priv->ie |= UART_C2_RIE; - up_setuartint(priv); + priv->ccr |= CCR_RX_EVENTS; + xmc4_setuartint(priv); #endif } else { -#ifdef CONFIG_DEBUG_FEATURES -# warning "Revisit: How are errors enabled?" - priv->ie &= ~UART_C2_RIE; -#else - priv->ie &= ~UART_C2_RIE; -#endif - up_setuartint(priv); + priv->ccr &= ~CCR_RX_EVENTS; + xmc4_setuartint(priv); } leave_critical_section(flags); @@ -898,7 +918,7 @@ static bool xmc4_rxavailable(struct uart_dev_s *dev) /* Return true if the transmit buffer/fifo is not "empty." */ - regval = up_serialin(priv, XMC4_UART_TRBSR_OFFSET); + regval = xmc4_serialin(priv, XMC4_USIC_TRBSR_OFFSET); return ((regval & USIC_TRBSR_REMPTY) == 0); } @@ -913,7 +933,7 @@ static bool xmc4_rxavailable(struct uart_dev_s *dev) static void xmc4_send(struct uart_dev_s *dev, int ch) { struct xmc4_dev_s *priv = (struct xmc4_dev_s *)dev->priv; - up_serialout(priv, XMC4_USIC_IN_OFFSET, (uint32_t)ch); + xmc4_serialout(priv, XMC4_USIC_IN_OFFSET, (uint32_t)ch); } /**************************************************************************** @@ -932,11 +952,11 @@ static void xmc4_txint(struct uart_dev_s *dev, bool enable) flags = enter_critical_section(); if (enable) { +#ifndef CONFIG_SUPPRESS_SERIAL_INTS /* Enable the TX interrupt */ -#ifndef CONFIG_SUPPRESS_SERIAL_INTS - priv->ie |= UART_C2_TIE; - up_setuartint(priv); + priv->ccr |= CCR_TX_EVENTS; + xmc4_setuartint(priv); /* Fake a TX interrupt here by just calling uart_xmitchars() with * interrupts disabled (note this may recurse). @@ -949,8 +969,8 @@ static void xmc4_txint(struct uart_dev_s *dev, bool enable) { /* Disable the TX interrupt */ - priv->ie &= ~UART_C2_TIE; - up_setuartint(priv); + priv->ccr &= ~CCR_TX_EVENTS; + xmc4_setuartint(priv); } leave_critical_section(flags); @@ -971,7 +991,7 @@ static bool xmc4_txready(struct uart_dev_s *dev) /* Return true if the transmit buffer/fifo is "not full." */ - regval = up_serialin(priv, XMC4_UART_TRBSR_OFFSET); + regval = xmc4_serialin(priv, XMC4_USIC_TRBSR_OFFSET); return ((regval & USIC_TRBSR_TFULL) == 0); } @@ -990,7 +1010,7 @@ static bool xmc4_txempty(struct uart_dev_s *dev) /* Return true if the transmit buffer/fifo is "empty." */ - regval = up_serialin(priv, XMC4_UART_TRBSR_OFFSET); + regval = xmc4_serialin(priv, XMC4_USIC_TRBSR_OFFSET); return ((regval & USIC_TRBSR_TEMPTY) != 0); } @@ -1004,9 +1024,9 @@ static bool xmc4_txempty(struct uart_dev_s *dev) * Description: * Performs the low level UART initialization early in debug so that the * serial console will be available during bootup. This must be called - * before up_serialinit. NOTE: This function depends on GPIO pin - * configuration performed in up_consoleinit() and main clock iniialization - * performed in up_clkinitialize(). + * before xmc4_serialinit. NOTE: This function depends on GPIO pin + * configuration performed in xmc_lowsetup() and main clock iniialization + * performed in xmc_clock_configure(). * ****************************************************************************/ @@ -1017,21 +1037,21 @@ void xmc4_earlyserialinit(void) * pic32mx_consoleinit() */ - up_restoreuartint(TTYS0_DEV.priv, 0); + xmc4_restoreuartint(TTYS0_DEV.priv, 0); #ifdef TTYS1_DEV - up_restoreuartint(TTYS1_DEV.priv, 0); + xmc4_restoreuartint(TTYS1_DEV.priv, 0); #endif #ifdef TTYS2_DEV - up_restoreuartint(TTYS2_DEV.priv, 0); + xmc4_restoreuartint(TTYS2_DEV.priv, 0); #endif #ifdef TTYS3_DEV - up_restoreuartint(TTYS3_DEV.priv, 0); + xmc4_restoreuartint(TTYS3_DEV.priv, 0); #endif #ifdef TTYS4_DEV - up_restoreuartint(TTYS4_DEV.priv, 0); + xmc4_restoreuartint(TTYS4_DEV.priv, 0); #endif #ifdef TTYS5_DEV - up_restoreuartint(TTYS5_DEV.priv, 0); + xmc4_restoreuartint(TTYS5_DEV.priv, 0); #endif /* Configuration whichever one is the console */ @@ -1060,11 +1080,9 @@ void xmc4_earlyserialinit(void) void up_serialinit(void) { - char devname[] = "/dev/ttySx"; - - /* Register the console */ - #ifdef HAVE_UART_CONSOLE + /* Register the serial console */ + (void)uart_register("/dev/console", &CONSOLE_DEV); #endif @@ -1072,26 +1090,20 @@ void up_serialinit(void) (void)uart_register("/dev/ttyS0", &TTYS0_DEV); #ifdef TTYS1_DEV - devname[(sizeof(devname)/sizeof(devname[0]))-2] = '0' + first++; (void)uart_register("/dev/ttyS1", &TTYS1_DEV); #endif #ifdef TTYS2_DEV - devname[(sizeof(devname)/sizeof(devname[0]))-2] = '0' + first++; (void)uart_register("/dev/ttyS2", &TTYS2_DEV); #endif #ifdef TTYS3_DEV - devname[(sizeof(devname)/sizeof(devname[0]))-2] = '0' + first++; (void)uart_register("/dev/ttyS3", &TTYS3_DEV); #endif #ifdef TTYS4_DEV - devname[(sizeof(devname)/sizeof(devname[0]))-2] = '0' + first++; (void)uart_register("/dev/ttyS4", &TTYS4_DEV); #endif #ifdef TTYS5_DEV - devname[(sizeof(devname)/sizeof(devname[0]))-2] = '0' + first++; (void)uart_register("/dev/ttyS5", &TTYS5_DEV); #endif - return first; } /**************************************************************************** @@ -1102,14 +1114,13 @@ void up_serialinit(void) * ****************************************************************************/ -#ifdef HAVE_UART_PUTC int up_putc(int ch) { #ifdef HAVE_UART_CONSOLE struct xmc4_dev_s *priv = (struct xmc4_dev_s *)CONSOLE_DEV.priv; - uint8_t ie; + uint32_t ccr; - up_disableuartint(priv, &ie); + xmc4_disableuartint(priv, &ccr); /* Check for LF */ @@ -1121,11 +1132,11 @@ int up_putc(int ch) } up_lowputc(ch); - up_restoreuartint(priv, ie); + xmc4_restoreuartint(priv, ccr); #endif + return ch; } -#endif #else /* USE_SERIALDRIVER */ @@ -1137,7 +1148,6 @@ int up_putc(int ch) * ****************************************************************************/ -#ifdef HAVE_UART_PUTC int up_putc(int ch) { #ifdef HAVE_UART_CONSOLE @@ -1151,10 +1161,8 @@ int up_putc(int ch) } up_lowputc(ch); -#endif return ch; } #endif #endif /* HAVE_UART_DEVICE && USE_SERIALDRIVER */ - From 985c137b784e0a1e1f9c448567629d858275c27b Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 20 Mar 2017 13:20:31 -0600 Subject: [PATCH 57/81] XMC4xxx: Finishes system timer logic. --- arch/arm/src/xmc4/xmc4_serial.c | 4 +-- arch/arm/src/xmc4/xmc4_start.c | 6 ++-- arch/arm/src/xmc4/xmc4_timerisr.c | 39 +++++++++++++++++++----- configs/xmc4500-relax/include/board.h | 3 +- configs/xmc4500-relax/src/xmc4_appinit.c | 4 +++ configs/xmc4500-relax/src/xmc4_bringup.c | 2 ++ 6 files changed, 44 insertions(+), 14 deletions(-) diff --git a/arch/arm/src/xmc4/xmc4_serial.c b/arch/arm/src/xmc4/xmc4_serial.c index 82d53b730b6..8f4fb4026d3 100644 --- a/arch/arm/src/xmc4/xmc4_serial.c +++ b/arch/arm/src/xmc4/xmc4_serial.c @@ -1019,7 +1019,7 @@ static bool xmc4_txempty(struct uart_dev_s *dev) ****************************************************************************/ /**************************************************************************** - * Name: xmc4_earlyserialinit + * Name: up_earlyserialinit * * Description: * Performs the low level UART initialization early in debug so that the @@ -1031,7 +1031,7 @@ static bool xmc4_txempty(struct uart_dev_s *dev) ****************************************************************************/ #if defined(USE_EARLYSERIALINIT) -void xmc4_earlyserialinit(void) +void up_earlyserialinit(void) { /* Disable interrupts from all UARTS. The console is enabled in * pic32mx_consoleinit() diff --git a/arch/arm/src/xmc4/xmc4_start.c b/arch/arm/src/xmc4/xmc4_start.c index aade30978f1..d1a1b4a1c3f 100644 --- a/arch/arm/src/xmc4/xmc4_start.c +++ b/arch/arm/src/xmc4/xmc4_start.c @@ -51,8 +51,9 @@ #include "up_internal.h" #include "chip/xmc4_flash.h" -#include "xmc4_userspace.h" +#include "xmc4_clockconfig.h" #include "xmc4_lowputc.h" +#include "xmc4_userspace.h" #include "xmc4_start.h" #ifdef CONFIG_ARCH_FPU @@ -319,8 +320,7 @@ void __start(void) #endif /* Disable the watchdog timer */ - - xmc4_wddisable(); + /* TODO - add logic to disable the watchdog timer */ /* Enable unaligned memory access */ diff --git a/arch/arm/src/xmc4/xmc4_timerisr.c b/arch/arm/src/xmc4/xmc4_timerisr.c index ba9e98596c8..dd23b8e2db1 100644 --- a/arch/arm/src/xmc4/xmc4_timerisr.c +++ b/arch/arm/src/xmc4/xmc4_timerisr.c @@ -57,23 +57,41 @@ * Pre-processor Definitions ****************************************************************************/ +/* The SysTick counter runs on the clock selected by SYST_CSR.CLKSOURCE. + * That selection may be either: + * + * CLKSOURCE=0: fSTDBY / 2 + * CLKSOURCE=1: fCPU + * + * In the first case, the SysTick counter would run at 16.384Khz. The most + * common system clock of 10 msec/tick cannot be exactly represented with + * that value. + * + * In the second case, the SysTick counter may run to rapidly to support + * longer timer tick intervals. For example, if the CPU clock is 144Mhz, + * then that 10 msec interval would correspond to a reload value of 1,440,000 + * or 0x0015f900. + */ + /* The desired timer interrupt frequency is provided by the definition * CLK_TCK (see include/time.h). CLK_TCK defines the desired number of * system clock ticks per second. That value is a user configurable setting * that defaults to 100 (100 ticks per second = 10 MS interval). * - * The Clock Source: The System Tick Timer's clock source is always the core - * clock + * Lets try fCPU first: */ -#define SYSTICK_RELOAD ((BOARD_CORECLK_FREQ / CLK_TCK) - 1) +#define SYSTICK_RELOAD ((BOARD_CPU_FREQUENCY / CLK_TCK) - 1) +#undef USE_STDBY_CLOCK -/* The size of the reload field is 24 bits. Verify that the reload value - * will fit in the reload register. - */ +/* Verify that the reload value will fit in the reload register. */ #if SYSTICK_RELOAD > 0x00ffffff -# error SYSTICK_RELOAD exceeds the range of the RELOAD register + /* No, then revert to fSTDBY */ + +# undef SYSTICK_RELOAD +# define SYSTICK_RELOAD ((BOARD_STDBY_FREQUENCY / CLK_TCK) - 1) +# define USE_STDBY_CLOCK 1 #endif /**************************************************************************** @@ -121,12 +139,17 @@ void arm_timer_initialize(void) regval |= (NVIC_SYSH_PRIORITY_DEFAULT << NVIC_SYSH_PRIORITY_PR15_SHIFT); putreg32(regval, NVIC_SYSH12_15_PRIORITY); +#ifndef USE_STDBY_CLOCK /* Note that is should not be neccesary to set the SYSTICK clock source: * "The CLKSOURCE bit in SysTick Control and Status register is always set * to select the core clock." + * + * For the XMC4xx, fhat selection may be either: + * + * CLKSOURCE=0: fSTDBY / 2 + * CLKSOURCE=1: fCPU */ -#if 0 regval = getreg32(NVIC_SYSTICK_CTRL); regval |= NVIC_SYSTICK_CTRL_CLKSOURCE; putreg32(regval, NVIC_SYSTICK_CTRL); diff --git a/configs/xmc4500-relax/include/board.h b/configs/xmc4500-relax/include/board.h index e90e3f730c6..6be8e787f23 100644 --- a/configs/xmc4500-relax/include/board.h +++ b/configs/xmc4500-relax/include/board.h @@ -107,12 +107,13 @@ /* Standby clock source selection * - * BOARD_STDBY_CLOCKSRC_OSI - Internal slow oscillator (32768Hz) + * BOARD_STDBY_CLOCKSRC_OSI - Internal 32.768KHz slow oscillator * BOARD_STDBY_CLOCKSRC_OSCULP - External 32.768KHz crystal */ #define BOARD_STDBY_CLOCKSRC_OSI 1 #undef BOARD_STDBY_CLOCKSRC_OSCULP +#define BOARD_STDBY_FREQUENCY 32768 /* USB PLL settings. * diff --git a/configs/xmc4500-relax/src/xmc4_appinit.c b/configs/xmc4500-relax/src/xmc4_appinit.c index 8e1fa87efe0..0c8ffcf2c63 100644 --- a/configs/xmc4500-relax/src/xmc4_appinit.c +++ b/configs/xmc4500-relax/src/xmc4_appinit.c @@ -39,6 +39,10 @@ #include +#include + +#include + /**************************************************************************** * Public Functions ****************************************************************************/ diff --git a/configs/xmc4500-relax/src/xmc4_bringup.c b/configs/xmc4500-relax/src/xmc4_bringup.c index ae7b5a593eb..151099f9ed2 100644 --- a/configs/xmc4500-relax/src/xmc4_bringup.c +++ b/configs/xmc4500-relax/src/xmc4_bringup.c @@ -39,6 +39,8 @@ #include +#include + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ From 3a91ba52647f63241c7a1343eaedcb594a30a687 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 20 Mar 2017 13:46:02 -0600 Subject: [PATCH 58/81] XMC4xxx: Plug last holes to get a first, clean build. --- arch/arm/src/xmc4/xmc4_lowputc.h | 17 +++ arch/arm/src/xmc4/xmc4_serial.c | 6 +- arch/arm/src/xmc4/xmc4_start.h | 6 +- configs/xmc4500-relax/nsh/Make.defs | 6 +- configs/xmc4500-relax/scripts/flash.ld | 134 +++++++++++++++++++++++ configs/xmc4500-relax/src/Makefile | 2 +- configs/xmc4500-relax/src/xmc4_appinit.c | 2 + configs/xmc4500-relax/src/xmc4_boot.c | 4 +- 8 files changed, 163 insertions(+), 14 deletions(-) create mode 100644 configs/xmc4500-relax/scripts/flash.ld diff --git a/arch/arm/src/xmc4/xmc4_lowputc.h b/arch/arm/src/xmc4/xmc4_lowputc.h index f8016c3d78e..61d850f7ba7 100644 --- a/arch/arm/src/xmc4/xmc4_lowputc.h +++ b/arch/arm/src/xmc4/xmc4_lowputc.h @@ -44,6 +44,7 @@ #include +#include "up_internal.h" #include "xmc4_config.h" #include "xmc4_usic.h" @@ -78,6 +79,22 @@ struct uart_config_s void xmc4_lowsetup(void); +/**************************************************************************** + * Name: xmc4_earlyserialinit + * + * Description: + * Performs the low level UART initialization early in debug so that the + * serial console will be available during bootup. This must be called + * before xmc4_serialinit. NOTE: This function depends on GPIO pin + * configuration performed in xmc_lowsetup() and main clock iniialization + * performed in xmc_clock_configure(). + * + ****************************************************************************/ + +#ifdef USE_EARLYSERIALINIT +void xmc4_earlyserialinit(void); +#endif + /**************************************************************************** * Name: xmc4_uart_configure * diff --git a/arch/arm/src/xmc4/xmc4_serial.c b/arch/arm/src/xmc4/xmc4_serial.c index 8f4fb4026d3..d9eaf0db53d 100644 --- a/arch/arm/src/xmc4/xmc4_serial.c +++ b/arch/arm/src/xmc4/xmc4_serial.c @@ -1019,7 +1019,7 @@ static bool xmc4_txempty(struct uart_dev_s *dev) ****************************************************************************/ /**************************************************************************** - * Name: up_earlyserialinit + * Name: xmc4_earlyserialinit * * Description: * Performs the low level UART initialization early in debug so that the @@ -1031,7 +1031,7 @@ static bool xmc4_txempty(struct uart_dev_s *dev) ****************************************************************************/ #if defined(USE_EARLYSERIALINIT) -void up_earlyserialinit(void) +void xmc4_earlyserialinit(void) { /* Disable interrupts from all UARTS. The console is enabled in * pic32mx_consoleinit() @@ -1068,7 +1068,7 @@ void up_earlyserialinit(void) * * Description: * Register serial console and serial ports. This assumes - * that up_earlyserialinit was called previously. + * that xmc4_earlyserialinit was called previously. * * Input Parameters: * None diff --git a/arch/arm/src/xmc4/xmc4_start.h b/arch/arm/src/xmc4/xmc4_start.h index 2be470640bf..ec76e2bf645 100644 --- a/arch/arm/src/xmc4/xmc4_start.h +++ b/arch/arm/src/xmc4/xmc4_start.h @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_XMC4_XMC4_CLOCKCONFIG_H -#define __ARCH_ARM_SRC_XMC4_XMC4_CLOCKCONFIG_H +#ifndef __ARCH_ARM_SRC_XMC4_XMC4_START_H +#define __ARCH_ARM_SRC_XMC4_XMC4_START_H /************************************************************************************ * Included Files @@ -58,4 +58,4 @@ void xmc4_board_initialize(void); -#endif /* __ARCH_ARM_SRC_XMC4_XMC4_CLOCKCONFIG_H */ +#endif /* __ARCH_ARM_SRC_XMC4_XMC4_START_H */ diff --git a/configs/xmc4500-relax/nsh/Make.defs b/configs/xmc4500-relax/nsh/Make.defs index 2d795a8ee1d..4f4b4d98c8d 100644 --- a/configs/xmc4500-relax/nsh/Make.defs +++ b/configs/xmc4500-relax/nsh/Make.defs @@ -37,11 +37,7 @@ include ${TOPDIR}/.config include ${TOPDIR}/tools/Config.mk include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs -ifeq ($(CONFIG_ARMV7M_DTCM),y) - LDSCRIPT = flash-dtcm.ld -else - LDSCRIPT = flash-sram.ld -endif +LDSCRIPT = flash.ld ifeq ($(WINTOOL),y) # Windows-native toolchains diff --git a/configs/xmc4500-relax/scripts/flash.ld b/configs/xmc4500-relax/scripts/flash.ld new file mode 100644 index 00000000000..f805eeafafd --- /dev/null +++ b/configs/xmc4500-relax/scripts/flash.ld @@ -0,0 +1,134 @@ +/**************************************************************************** + * configs/xmc4500-relax/scripts/flash.ld + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* The XMC4500 has 1024Kb of FLASH beginning at address 0x0800:0000 and + * 64Kb of SRAM beginning at 0x2000:0000. + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address + * range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 1024K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K +} + +OUTPUT_ARCH(arm) +ENTRY(_stext) +SECTIONS +{ + .text : + { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : + { + _sinit = ABSOLUTE(.); + *(.init_array .init_array.*) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : + { + *(.ARM.extab*) + } > flash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : + { + *(.ARM.exidx*) + } > flash + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : + { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : + { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + _ebss = ABSOLUTE(.); + } > sram + + /* Global data not cleared after reset. */ + + .noinit : + { + _snoinit = ABSOLUTE(.); + *(.noinit*) + _enoinit = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/configs/xmc4500-relax/src/Makefile b/configs/xmc4500-relax/src/Makefile index d609e49ac8e..f7a63f46309 100644 --- a/configs/xmc4500-relax/src/Makefile +++ b/configs/xmc4500-relax/src/Makefile @@ -42,7 +42,7 @@ ifeq ($(CONFIG_BUTTONS),y) CSRCS += xmc4_buttons.c endif -ifeq ($(CONFIG_USERLED),y) +ifeq ($(CONFIG_ARCH_LEDS),y) CSRCS += xmc4_autoleds.c else CSRCS += xmc4_userleds.c diff --git a/configs/xmc4500-relax/src/xmc4_appinit.c b/configs/xmc4500-relax/src/xmc4_appinit.c index 0c8ffcf2c63..1621317d4d0 100644 --- a/configs/xmc4500-relax/src/xmc4_appinit.c +++ b/configs/xmc4500-relax/src/xmc4_appinit.c @@ -43,6 +43,8 @@ #include +#include "xmc4500-relax.h" + /**************************************************************************** * Public Functions ****************************************************************************/ diff --git a/configs/xmc4500-relax/src/xmc4_boot.c b/configs/xmc4500-relax/src/xmc4_boot.c index 994cdf86c6a..cc5fec0c197 100644 --- a/configs/xmc4500-relax/src/xmc4_boot.c +++ b/configs/xmc4500-relax/src/xmc4_boot.c @@ -49,7 +49,7 @@ ************************************************************************************/ /************************************************************************************ - * Name: xmc4_boardinitialize + * Name: xmc4_board_initialize * * Description: * All STM32 architectures must provide the following entry point. This entry point @@ -58,7 +58,7 @@ * ************************************************************************************/ -void xmc4_boardinitialize(void) +void xmc4_board_initialize(void) { #ifdef CONFIG_ARCH_LEDS /* Configure on-board LEDs if LED support has been selected. */ From e1f86f407feb482d5eb631dbb5c1588da876bc4f Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 20 Mar 2017 14:33:48 -0600 Subject: [PATCH 59/81] XMC4500-Relax: Add LED support. --- configs/xmc4500-relax/src/xmc4500-relax.h | 22 +++- configs/xmc4500-relax/src/xmc4_autoleds.c | 118 +++++++++++++++++++++- configs/xmc4500-relax/src/xmc4_userleds.c | 32 +++++- 3 files changed, 162 insertions(+), 10 deletions(-) diff --git a/configs/xmc4500-relax/src/xmc4500-relax.h b/configs/xmc4500-relax/src/xmc4500-relax.h index 7934462b70e..156d6f8c179 100644 --- a/configs/xmc4500-relax/src/xmc4500-relax.h +++ b/configs/xmc4500-relax/src/xmc4500-relax.h @@ -42,6 +42,8 @@ #include +#include "xmc4_gpio.h" + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -50,18 +52,30 @@ * * The XMC4500 Relax Lite v1 board has two LEDs: * - * LED1 P1.1 High output illuminates - * LED2 P1.0 High output illuminates + * LED1 P1.1, Pad type A1+, High output illuminates + * LED2 P1.0, Pad type A1+ High output illuminates */ +#define GPIO_LED1 (GPIO_OUTPUT | GPIO_OUTPUT_PUSHPULL | \ + GPIO_PADA1P_STRONGSOFT | GPIO_PINCTRL_SOFTWARE | \ + GPIO_OUTPUT_CLEAR | GPIO_PORT1 | GPIO_PIN1) +#define GPIO_LED2 (GPIO_OUTPUT | GPIO_OUTPUT_PUSHPULL | \ + GPIO_PADA1P_STRONGSOFT | GPIO_PINCTRL_SOFTWARE | \ + GPIO_OUTPUT_CLEAR | GPIO_PORT1 | GPIO_PIN0) + /* BUTTONS * * The XMC4500 Relax Lite v1 board has two buttons: * - * BUTTON1 P1.14 Low input sensed when button pressed - * BUTTON2 P1.15 Low input sensed when button pressed + * BUTTON1 P1.14, Pad type A2, Low input sensed when button pressed + * BUTTON2 P1.15, Pad type A2, Low input sensed when button pressed */ +#define GPIO_BUTTON1 (GPIO_INPUT | GPIO_PINCTRL_SOFTWARE | \ + GPIO_PORT1 | GPIO_PIN14) +#define GPIO_BUTTON2 (GPIO_INPUT | GPIO_PINCTRL_SOFTWARE | \ + GPIO_PORT1 | GPIO_PIN15) + /**************************************************************************** * Public Types ****************************************************************************/ diff --git a/configs/xmc4500-relax/src/xmc4_autoleds.c b/configs/xmc4500-relax/src/xmc4_autoleds.c index 7fd88f7866b..694007c5e5e 100644 --- a/configs/xmc4500-relax/src/xmc4_autoleds.c +++ b/configs/xmc4500-relax/src/xmc4_autoleds.c @@ -33,6 +33,30 @@ * ****************************************************************************/ +/* The XMC4500 Relax Lite v1 board has two LEDs: + * + * LED1 P1.1 High output illuminates + * LED2 P1.0 High output illuminates + * + * These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is + * defined. In that case, the usage by the board port is defined in + * include/board.h and src/sam_autoleds.c. The LEDs are used to encode + * OS-related events as follows: + * + * SYMBOL Meaning LED state + * LED2 LED1 + * --------------------- -------------------------- ------ ------ */ + +#define LED_STARTED 0 /* NuttX has been started OFF OFF */ +#define LED_HEAPALLOCATE 0 /* Heap has been allocated OFF OFF */ +#define LED_IRQSENABLED 0 /* Interrupts enabled OFF OFF */ +#define LED_STACKCREATED 1 /* Idle stack created ON OFF */ +#define LED_INIRQ 2 /* In an interrupt No change */ +#define LED_SIGNAL 2 /* In a signal handler No change */ +#define LED_ASSERTION 2 /* An assertion failed No change */ +#define LED_PANIC 3 /* The system has crashed N/C Blinking */ +#undef LED_IDLE /* MCU is is sleep mode Not used */ + /**************************************************************************** * Included Files ****************************************************************************/ @@ -42,10 +66,93 @@ #include #include +#include "xmc4_gpio.h" #include "xmc4500-relax.h" #ifdef CONFIG_ARCH_LEDS +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static void board_led1_on(int led) +{ + bool ledon = false; + + switch (led) + { + case 0: /* LED1=OFF */ + break; + + case 1: /* LED1=ON */ + ledon = true; + break; + + case 2: /* LED1=N/C */ + case 3: /* LED1=N/C */ + default: + return; + } + + xmc4_gpio_write(GPIO_LED1, ledon); +} + +static void board_led2_on(int led) +{ + bool ledon = false; + + switch (led) + { + case 0: /* LED2=OFF */ + case 1: /* LED2=OFF */ + break; + + case 3: /* LED2=ON */ + ledon = true; + break; + + case 2: /* LED2=N/C */ + default: + return; + } + + xmc4_gpio_write(GPIO_LED2, ledon); +} + +void board_led1_off(int led) +{ + switch (led) + { + case 0: /* LED1=OFF */ + case 1: /* LED1=OFF */ + break; + + case 2: /* LED1=N/C */ + case 3: /* LED1=N/C */ + default: + return; + } + + xmc4_gpio_write(GPIO_LED1, false); +} + +void board_led2_off(int led) +{ + switch (led) + { + case 0: /* LED2=OFF */ + case 1: /* LED2=OFF */ + case 3: /* LED2=OFF */ + break; + + case 2: /* LED2=N/C */ + default: + return; + } + + xmc4_gpio_write(GPIO_LED2, false); +} + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -56,7 +163,10 @@ void board_autoled_initialize(void) { -#warning Missing logic + /* Configure LED1-2 GPIOs for output */ + + (void)xmc4_gpio_config(GPIO_LED1); + (void)xmc4_gpio_config(GPIO_LED2); } /**************************************************************************** @@ -65,7 +175,8 @@ void board_autoled_initialize(void) void board_autoled_on(int led) { -#warning Missing logic + board_led1_on(led); + board_led2_on(led); } /**************************************************************************** @@ -74,7 +185,8 @@ void board_autoled_on(int led) void board_autoled_off(int led) { -#warning Missing logic + board_led1_off(led); + board_led2_off(led); } #endif /* CONFIG_ARCH_LEDS */ diff --git a/configs/xmc4500-relax/src/xmc4_userleds.c b/configs/xmc4500-relax/src/xmc4_userleds.c index 8bb69336f7e..4d9d0cb0902 100644 --- a/configs/xmc4500-relax/src/xmc4_userleds.c +++ b/configs/xmc4500-relax/src/xmc4_userleds.c @@ -41,6 +41,8 @@ #include #include + +#include "xmc4_gpio.h" #include "xmc4500-relax.h" /**************************************************************************** @@ -53,7 +55,10 @@ void board_userled_initialize(void) { -#warning Missing logic + /* Configure LED1-2 GPIOs for output */ + + (void)xmc4_gpio_config(GPIO_LED1); + (void)xmc4_gpio_config(GPIO_LED2); } /**************************************************************************** @@ -62,7 +67,22 @@ void board_userled_initialize(void) void board_userled(int led, bool ledon) { -#warning Missing logic + gpioconfig_t ledcfg; + + if (led == BOARD_LED1) + { + ledcfg = GPIO_LED1; + } + else if (led == BOARD_LED2) + { + ledcfg = GPIO_LED2; + } + else + { + return; + } + + xmc4_gpio_write(ledcfg, ledon); } /**************************************************************************** @@ -71,5 +91,11 @@ void board_userled(int led, bool ledon) void board_userled_all(uint8_t ledset) { -#warning Missing logic + bool ledon; + + ledon = ((ledset & BOARD_LED1_BIT) != 0); + xmc4_gpio_write(GPIO_LED1, ledon); + + ledon = ((ledset & BOARD_LED2_BIT) != 0); + xmc4_gpio_write(GPIO_LED2, ledon); } From 4ba091933e9098db19e0ebe66ffe88a140ed2f82 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 20 Mar 2017 16:31:35 -0600 Subject: [PATCH 60/81] XMC4xxx: Fix for early bringup problems --- arch/arm/include/xmc4/chip.h | 5 +- arch/arm/src/xmc4/Kconfig | 3 + arch/arm/src/xmc4/chip/xmc4_scu.h | 114 +++++++++++++++------------ arch/arm/src/xmc4/xmc4_clockconfig.c | 6 +- arch/arm/src/xmc4/xmc4_usic.c | 31 +++++++- configs/xmc4500-relax/nsh/defconfig | 4 +- 6 files changed, 102 insertions(+), 61 deletions(-) diff --git a/arch/arm/include/xmc4/chip.h b/arch/arm/include/xmc4/chip.h index 76cd0c4cd6f..c0ef4884a02 100644 --- a/arch/arm/include/xmc4/chip.h +++ b/arch/arm/include/xmc4/chip.h @@ -50,7 +50,10 @@ #if defined(CONFIG_ARCH_CHIP_XMC4500) # define XMC4_NUSIC 3 /* Three USIC modules: USCI0-2 */ - +# undef XMC4_SCU_GATING /* No clock gating registers */ +#elif defined(CONFIG_ARCH_CHIP_XMC4700) +# define XMC4_NUSIC 3 /* Three USIC modules: USCI0-2 */ +# define XMC4_SCU_GATING 1 /* Has clock gating registers */ #else # error "Unsupported XMC4xxx chip" #endif diff --git a/arch/arm/src/xmc4/Kconfig b/arch/arm/src/xmc4/Kconfig index c73e281fb50..99493b04012 100644 --- a/arch/arm/src/xmc4/Kconfig +++ b/arch/arm/src/xmc4/Kconfig @@ -13,6 +13,9 @@ choice config ARCH_CHIP_XMC4500 bool "XMC4500" +config ARCH_CHIP_XMC4700 + bool "XMC4700" + endchoice # These "hidden" settings determine is a peripheral option is available for diff --git a/arch/arm/src/xmc4/chip/xmc4_scu.h b/arch/arm/src/xmc4/chip/xmc4_scu.h index d916b8330c5..38d26051b77 100644 --- a/arch/arm/src/xmc4/chip/xmc4_scu.h +++ b/arch/arm/src/xmc4/chip/xmc4_scu.h @@ -163,18 +163,20 @@ #define XMC4_SCU_EXTCLKCR_OFFSET 0x0028 /* External clock Control Register */ #define XMC4_SCU_SLEEPCR_OFFSET 0x0030 /* Sleep Control Register */ #define XMC4_SCU_DSLEEPCR_OFFSET 0x0034 /* Deep Sleep Control Register */ -#define XMC4_SCU_CGATSTAT0_OFFSET 0x0040 /* Peripheral 0 Clock Gating Status */ -#define XMC4_SCU_CGATSET0_OFFSET 0x0044 /* Peripheral 0 Clock Gating Set */ -#define XMC4_SCU_CGATCLR0_OFFSET 0x0048 /* Peripheral 0 Clock Gating Clear */ -#define XMC4_SCU_CGATSTAT1_OFFSET 0x004c /* Peripheral 1 Clock Gating Status */ -#define XMC4_SCU_CGATSET1_OFFSET 0x0050 /* Peripheral 1 Clock Gating Set */ -#define XMC4_SCU_CGATCLR1_OFFSET 0x0054 /* Peripheral 1 Clock Gating Clear */ -#define XMC4_SCU_CGATSTAT2_OFFSET 0x0058 /* Peripheral 2 Clock Gating Status */ -#define XMC4_SCU_CGATSET2_OFFSET 0x005c /* Peripheral 2 Clock Gating Set */ -#define XMC4_SCU_CGATCLR2_OFFSET 0x0060 /* Peripheral 2 Clock Gating Clear */ -#define XMC4_SCU_CGATSTAT3_OFFSET 0x0064 /* Peripheral 3 Clock Gating Status */ -#define XMC4_SCU_CGATSET3_OFFSET 0x0068 /* Peripheral 3 Clock Gating Set */ -#define XMC4_SCU_CGATCLR3_OFFSET 0x006c /* Peripheral 3 Clock Gating Clear */ +#ifdef XMC4_SCU_GATING +# define XMC4_SCU_CGATSTAT0_OFFSET 0x0040 /* Peripheral 0 Clock Gating Status */ +# define XMC4_SCU_CGATSET0_OFFSET 0x0044 /* Peripheral 0 Clock Gating Set */ +# define XMC4_SCU_CGATCLR0_OFFSET 0x0048 /* Peripheral 0 Clock Gating Clear */ +# define XMC4_SCU_CGATSTAT1_OFFSET 0x004c /* Peripheral 1 Clock Gating Status */ +# define XMC4_SCU_CGATSET1_OFFSET 0x0050 /* Peripheral 1 Clock Gating Set */ +# define XMC4_SCU_CGATCLR1_OFFSET 0x0054 /* Peripheral 1 Clock Gating Clear */ +# define XMC4_SCU_CGATSTAT2_OFFSET 0x0058 /* Peripheral 2 Clock Gating Status */ +# define XMC4_SCU_CGATSET2_OFFSET 0x005c /* Peripheral 2 Clock Gating Set */ +# define XMC4_SCU_CGATCLR2_OFFSET 0x0060 /* Peripheral 2 Clock Gating Clear */ +# define XMC4_SCU_CGATSTAT3_OFFSET 0x0064 /* Peripheral 3 Clock Gating Status */ +# define XMC4_SCU_CGATSET3_OFFSET 0x0068 /* Peripheral 3 Clock Gating Set */ +# define XMC4_SCU_CGATCLR3_OFFSET 0x006c /* Peripheral 3 Clock Gating Clear */ +#endif /* Oscillator Control SCU Registers */ @@ -292,18 +294,20 @@ #define XMC4_SCU_EXTCLKCR (XMC4_SCU_CLK_BASE+XMC4_SCU_EXTCLKCR_OFFSET) #define XMC4_SCU_SLEEPCR (XMC4_SCU_CLK_BASE+XMC4_SCU_SLEEPCR_OFFSET) #define XMC4_SCU_DSLEEPCR (XMC4_SCU_CLK_BASE+XMC4_SCU_DSLEEPCR_OFFSET) -#define XMC4_SCU_CGATSTAT0 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATSTAT0_OFFSET) -#define XMC4_SCU_CGATSET0 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATSET0_OFFSET) -#define XMC4_SCU_CGATCLR0 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATCLR0_OFFSET) -#define XMC4_SCU_CGATSTAT1 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATSTAT1_OFFSET) -#define XMC4_SCU_CGATSET1 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATSET1_OFFSET) -#define XMC4_SCU_CGATCLR1 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATCLR1_OFFSET) -#define XMC4_SCU_CGATSTAT2 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATSTAT2_OFFSET) -#define XMC4_SCU_CGATSET2 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATSET2_OFFSET) -#define XMC4_SCU_CGATCLR2 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATCLR2_OFFSET) -#define XMC4_SCU_CGATSTAT3 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATSTAT3_OFFSET) -#define XMC4_SCU_CGATSET3 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATSET3_OFFSET) -#define XMC4_SCU_CGATCLR3 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATCLR3_OFFSET) +#ifdef XMC4_SCU_GATING +# define XMC4_SCU_CGATSTAT0 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATSTAT0_OFFSET) +# define XMC4_SCU_CGATSET0 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATSET0_OFFSET) +# define XMC4_SCU_CGATCLR0 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATCLR0_OFFSET) +# define XMC4_SCU_CGATSTAT1 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATSTAT1_OFFSET) +# define XMC4_SCU_CGATSET1 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATSET1_OFFSET) +# define XMC4_SCU_CGATCLR1 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATCLR1_OFFSET) +# define XMC4_SCU_CGATSTAT2 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATSTAT2_OFFSET) +# define XMC4_SCU_CGATSET2 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATSET2_OFFSET) +# define XMC4_SCU_CGATCLR2 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATCLR2_OFFSET) +# define XMC4_SCU_CGATSTAT3 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATSTAT3_OFFSET) +# define XMC4_SCU_CGATSET3 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATSET3_OFFSET) +# define XMC4_SCU_CGATCLR3 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATCLR3_OFFSET) +#endif /* Oscillator Control SCU Registers */ @@ -959,42 +963,50 @@ /* Peripheral 0 Clock Gating Status, Peripheral 0 Clock Gating Set, Peripheral 0 Clock Gating Clear */ -#define SCU_CGAT0_VADC (1 << 0) /* Bit 0: VADC Gating Status */ -#define SCU_CGAT0_DSD (1 << 1) /* Bit 1: DSD Gating Status */ -#define SCU_CGAT0_CCU40 (1 << 2) /* Bit 2: CCU40 Gating Status */ -#define SCU_CGAT0_CCU41 (1 << 3) /* Bit 3: CCU41 Gating Status */ -#define SCU_CGAT0_CCU42 (1 << 4) /* Bit 4: CCU42 Gating Status */ -#define SCU_CGAT0_CCU80 (1 << 7) /* Bit 7: CCU80 Gating Status */ -#define SCU_CGAT0_CCU81 (1 << 8) /* Bit 8: CCU81 Gating Status */ -#define SCU_CGAT0_POSIF0 (1 << 9) /* Bit 9: POSIF0 Gating Status */ -#define SCU_CGAT0_POSIF1 (1 << 10) /* Bit 10: POSIF1 Gating Status */ -#define SCU_CGAT0_USIC0 (1 << 11) /* Bit 11: USIC0 Gating Status */ -#define SCU_CGAT0_ERU1 (1 << 16) /* Bit 16: ERU1 Gating Status */ +#ifdef XMC4_SCU_GATING +# define SCU_CGAT0_VADC (1 << 0) /* Bit 0: VADC Gating Status */ +# define SCU_CGAT0_DSD (1 << 1) /* Bit 1: DSD Gating Status */ +# define SCU_CGAT0_CCU40 (1 << 2) /* Bit 2: CCU40 Gating Status */ +# define SCU_CGAT0_CCU41 (1 << 3) /* Bit 3: CCU41 Gating Status */ +# define SCU_CGAT0_CCU42 (1 << 4) /* Bit 4: CCU42 Gating Status */ +# define SCU_CGAT0_CCU80 (1 << 7) /* Bit 7: CCU80 Gating Status */ +# define SCU_CGAT0_CCU81 (1 << 8) /* Bit 8: CCU81 Gating Status */ +# define SCU_CGAT0_POSIF0 (1 << 9) /* Bit 9: POSIF0 Gating Status */ +# define SCU_CGAT0_POSIF1 (1 << 10) /* Bit 10: POSIF1 Gating Status */ +# define SCU_CGAT0_USIC0 (1 << 11) /* Bit 11: USIC0 Gating Status */ +# define SCU_CGAT0_ERU1 (1 << 16) /* Bit 16: ERU1 Gating Status */ +#endif /* Peripheral 1 Clock Gating Status, Peripheral 1 Clock Gating Set, Peripheral 1 Clock Gating Clear */ -#define SCU_CGAT1_CCU43 (1 << 0) /* Bit 0: CCU43 Gating Status */ -#define SCU_CGAT1_LEDTSCU0 (1 << 3) /* Bit 3: LEDTS Gating Status */ -#define SCU_CGAT1_MCAN0 (1 << 4) /* Bit 4: MultiCAN Gating Status */ -#define SCU_CGAT1_DAC (1 << 5) /* Bit 5: DAC Gating Status */ -#define SCU_CGAT1_MMCI (1 << 6) /* Bit 6: MMC Interface Gating Status */ -#define SCU_CGAT1_USIC1 (1 << 7) /* Bit 7: USIC1 Gating Status */ -#define SCU_CGAT1_USIC2 (1 << 8) /* Bit 8: USIC1 Gating Status */ -#define SCU_CGAT1_PPORTS (1 << 9) /* Bit 9: PORTS Gating Status */ +#ifdef XMC4_SCU_GATING +# define SCU_CGAT1_CCU43 (1 << 0) /* Bit 0: CCU43 Gating Status */ +# define SCU_CGAT1_LEDTSCU0 (1 << 3) /* Bit 3: LEDTS Gating Status */ +# define SCU_CGAT1_MCAN0 (1 << 4) /* Bit 4: MultiCAN Gating Status */ +# define SCU_CGAT1_DAC (1 << 5) /* Bit 5: DAC Gating Status */ +# define SCU_CGAT1_MMCI (1 << 6) /* Bit 6: MMC Interface Gating Status */ +# define SCU_CGAT1_USIC1 (1 << 7) /* Bit 7: USIC1 Gating Status */ +# define SCU_CGAT1_USIC2 (1 << 8) /* Bit 8: USIC1 Gating Status */ +# define SCU_CGAT1_PPORTS (1 << 9) /* Bit 9: PORTS Gating Status */ +#endif /* Peripheral 2 Clock Gating Status, Peripheral 2 Clock Gating Set, Peripheral 2 Clock Gating Clear */ -#define SCU_CGAT2_WDT (1 << 1) /* Bit 1: WDT Gating Status */ -#define SCU_CGAT2_ETH0 (1 << 2) /* Bit 2: ETH0 Gating Status */ -#define SCU_CGAT2_DMA0 (1 << 4) /* Bit 4: DMA0 Gating Status */ -#define SCU_CGAT2_DMA1 (1 << 5) /* Bit 5: DMA1 Gating Status */ -#define SCU_CGAT2_FCE (1 << 6) /* Bit 6: FCE Gating Status */ -#define SCU_CGAT2_USB (1 << 7) /* Bit 7: USB Gating Status */ -#define SCU_CGAT2_ECAT (1 << 10) /* Bit 10: ECAT Gating Status */ +#ifdef XMC4_SCU_GATING +# define SCU_CGAT2_WDT (1 << 1) /* Bit 1: WDT Gating Status */ +# define SCU_CGAT2_ETH0 (1 << 2) /* Bit 2: ETH0 Gating Status */ +# define SCU_CGAT2_DMA0 (1 << 4) /* Bit 4: DMA0 Gating Status */ +# define SCU_CGAT2_DMA1 (1 << 5) /* Bit 5: DMA1 Gating Status */ +# define SCU_CGAT2_FCE (1 << 6) /* Bit 6: FCE Gating Status */ +# define SCU_CGAT2_USB (1 << 7) /* Bit 7: USB Gating Status */ +# define SCU_CGAT2_ECAT (1 << 10) /* Bit 10: ECAT Gating Status */ +#endif /* Peripheral 3 Clock Gating Status, Peripheral 3 Clock Gating Set, Peripheral 3 Clock Gating Clear */ -#define SCU_CGAT3_EBU (1 << 2) /* Bit 2: EBU Gating Status */ +#ifdef XMC4_SCU_GATING +# define SCU_CGAT3_EBU (1 << 2) /* Bit 2: EBU Gating Status */ +#endif /* Oscillator Control SCU Registers */ diff --git a/arch/arm/src/xmc4/xmc4_clockconfig.c b/arch/arm/src/xmc4/xmc4_clockconfig.c index d663ea9f82d..db72a3cdf9c 100644 --- a/arch/arm/src/xmc4/xmc4_clockconfig.c +++ b/arch/arm/src/xmc4/xmc4_clockconfig.c @@ -313,9 +313,9 @@ void xmc4_clock_configure(void) { } - regval = getreg32(SCU_TRAP_SOSCWDGT); - regval &= ~bitset; - putreg32(regval, SCU_TRAP_SOSCWDGT); + regval = getreg32(XMC4_SCU_TRAPDIS); + regval &= ~SCU_TRAP_SOSCWDGT; + putreg32(regval, XMC4_SCU_TRAPDIS); } #else /* BOARD_PLL_CLOCKSRC_XTAL */ diff --git a/arch/arm/src/xmc4/xmc4_usic.c b/arch/arm/src/xmc4/xmc4_usic.c index 26347642403..dd69cf318dd 100644 --- a/arch/arm/src/xmc4/xmc4_usic.c +++ b/arch/arm/src/xmc4/xmc4_usic.c @@ -112,6 +112,7 @@ int xmc4_enable_usic(enum usic_e usic) switch (usic) { case USIC0: +#ifdef XMC4_SCU_GATING /* Check if USIC0 is already ungated */ if ((getreg32(XMC4_SCU_CGATSTAT0) & SCU_CGAT0_USIC0) == 0) @@ -124,11 +125,16 @@ int xmc4_enable_usic(enum usic_e usic) putreg32(SCU_PR0_USIC0RS, XMC4_SCU_PRCLR0); } +#else + /* De-assert peripheral reset USIC0 */ + putreg32(SCU_PR0_USIC0RS, XMC4_SCU_PRCLR0); +#endif break; #if XMC4_NUSIC > 1 case USIC1: +#ifdef XMC4_SCU_GATING /* Check if USIC1 is already ungated */ if ((getreg32(XMC4_SCU_CGATSTAT1) & SCU_CGAT1_USIC1) == 0) @@ -141,11 +147,16 @@ int xmc4_enable_usic(enum usic_e usic) putreg32(SCU_PR1_USIC1RS, XMC4_SCU_PRCLR1); } +#else + /* De-assert peripheral reset USIC1 */ + putreg32(SCU_PR1_USIC1RS, XMC4_SCU_PRCLR1); +#endif break; #if XMC4_NUSIC > 2 case USIC2: +#ifdef XMC4_SCU_GATING /* Check if USIC2 is already ungated */ if ((getreg32(XMC4_SCU_CGATSTAT1) & SCU_CGAT1_USIC2) == 0) @@ -158,10 +169,15 @@ int xmc4_enable_usic(enum usic_e usic) putreg32(SCU_PR1_USIC2RS, XMC4_SCU_PRCLR1); } +#else + /* De-assert peripheral reset USIC2 */ + putreg32(SCU_PR1_USIC2RS, XMC4_SCU_PRCLR1); +#endif break; -#endif -#endif + +#endif /* XMC4_NUSIC > 2 */ +#endif /* XMC4_NUSIC > 1 */ default: return -EINVAL; @@ -191,9 +207,11 @@ int xmc4_disable_usic(enum usic_e usic) putreg32(SCU_PR0_USIC0RS, XMC4_SCU_PRSET0); +#ifdef XMC4_SCU_GATING /* Gate USIC0 clocking */ putreg32(SCU_CGAT0_USIC0, XMC4_SCU_CGATSET0); +#endif break; #if XMC4_NUSIC > 1 @@ -202,9 +220,11 @@ int xmc4_disable_usic(enum usic_e usic) putreg32(SCU_PR1_USIC1RS, XMC4_SCU_PRSET1); +#ifdef XMC4_SCU_GATING /* Gate USIC0 clocking */ putreg32(SCU_CGAT1_USIC1, XMC4_SCU_CGATSET1); +#endif break; #if XMC4_NUSIC > 2 @@ -213,12 +233,15 @@ int xmc4_disable_usic(enum usic_e usic) putreg32(SCU_PR1_USIC2RS, XMC4_SCU_PRSET1); +#ifdef XMC4_SCU_GATING /* Gate USIC0 clocking */ putreg32(SCU_CGAT1_USIC2, XMC4_SCU_CGATSET1); +#endif break; -#endif -#endif + +#endif /* XMC4_NUSIC > 2 */ +#endif /* XMC4_NUSIC > 1 */ default: return -EINVAL; diff --git a/configs/xmc4500-relax/nsh/defconfig b/configs/xmc4500-relax/nsh/defconfig index f938e18bc4f..d5543652090 100644 --- a/configs/xmc4500-relax/nsh/defconfig +++ b/configs/xmc4500-relax/nsh/defconfig @@ -250,8 +250,8 @@ CONFIG_BOOT_RUNFROMFLASH=y # # Boot Memory Configuration # -CONFIG_RAM_START=0x20400000 -CONFIG_RAM_SIZE=393216 +CONFIG_RAM_START=0x20000000 +CONFIG_RAM_SIZE=65536 # CONFIG_ARCH_HAVE_SDRAM is not set # From b9e29d108373e5fd0f300a47c4a9bdb2173d4b3f Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 20 Mar 2017 17:08:09 -0600 Subject: [PATCH 61/81] XMC4xxx: Clean up memory map --- arch/arm/include/xmc4/chip.h | 6 ++ arch/arm/src/xmc4/Kconfig | 3 + arch/arm/src/xmc4/chip/xmc4_memorymap.h | 106 +++++++++++++----------- 3 files changed, 68 insertions(+), 47 deletions(-) diff --git a/arch/arm/include/xmc4/chip.h b/arch/arm/include/xmc4/chip.h index c0ef4884a02..5c3fcdabfa2 100644 --- a/arch/arm/include/xmc4/chip.h +++ b/arch/arm/include/xmc4/chip.h @@ -51,9 +51,15 @@ #if defined(CONFIG_ARCH_CHIP_XMC4500) # define XMC4_NUSIC 3 /* Three USIC modules: USCI0-2 */ # undef XMC4_SCU_GATING /* No clock gating registers */ +# define XMC4_NECATN 0 /* No EtherCAT support */ #elif defined(CONFIG_ARCH_CHIP_XMC4700) # define XMC4_NUSIC 3 /* Three USIC modules: USCI0-2 */ # define XMC4_SCU_GATING 1 /* Has clock gating registers */ +# define XMC4_NECATN 0 /* No EtherCAT support */ +#elif defined(CONFIG_ARCH_CHIP_XMC4700) +# define XMC4_NUSIC 3 /* Three USIC modules: USCI0-2 */ +# define XMC4_SCU_GATING 1 /* Has clock gating registers */ +# define XMC4_NECATN 1 /* One EtherCAT module */ #else # error "Unsupported XMC4xxx chip" #endif diff --git a/arch/arm/src/xmc4/Kconfig b/arch/arm/src/xmc4/Kconfig index 99493b04012..f50652cd966 100644 --- a/arch/arm/src/xmc4/Kconfig +++ b/arch/arm/src/xmc4/Kconfig @@ -16,6 +16,9 @@ config ARCH_CHIP_XMC4500 config ARCH_CHIP_XMC4700 bool "XMC4700" +config ARCH_CHIP_XMC4800 + bool "XMC4700" + endchoice # These "hidden" settings determine is a peripheral option is available for diff --git a/arch/arm/src/xmc4/chip/xmc4_memorymap.h b/arch/arm/src/xmc4/chip/xmc4_memorymap.h index fb8dcbf183b..a2df7e405ce 100644 --- a/arch/arm/src/xmc4/chip/xmc4_memorymap.h +++ b/arch/arm/src/xmc4/chip/xmc4_memorymap.h @@ -79,58 +79,58 @@ * USCI - Universal Serial Interface */ -#define XMC4_PBA0_BASE 0x40000000 -#define XMC4_VADC_BASE 0x40004000 +#define XMC4_PBA0_BASE 0x40000000 /* PBA0 */ +#define XMC4_VADC_BASE 0x40004000 /* VADC */ #define XMC4_VADC_G0_BASE 0x40004400 #define XMC4_VADC_G1_BASE 0x40004800 #define XMC4_VADC_G2_BASE 0x40004c00 #define XMC4_VADC_G3_BASE 0x40005000 -#define XMC4_DSD_BASE 0x40008000 +#define XMC4_DSD_BASE 0x40008000 /* DSD */ #define XMC4_DSD_CH0_BASE 0x40008100 #define XMC4_DSD_CH1_BASE 0x40008200 #define XMC4_DSD_CH2_BASE 0x40008300 #define XMC4_DSD_CH3_BASE 0x40008400 -#define XMC4_CCU40_BASE 0x4000c000 +#define XMC4_CCU40_BASE 0x4000c000 /* CCU40 */ #define XMC4_CCU40_CC40_BASE 0x4000c100 #define XMC4_CCU40_CC41_BASE 0x4000c200 #define XMC4_CCU40_CC42_BASE 0x4000c300 #define XMC4_CCU40_CC43_BASE 0x4000c400 -#define XMC4_CCU41_BASE 0x40010000 +#define XMC4_CCU41_BASE 0x40010000 /* CCU41 */ #define XMC4_CCU41_CC40_BASE 0x40010100 #define XMC4_CCU41_CC41_BASE 0x40010200 #define XMC4_CCU41_CC42_BASE 0x40010300 #define XMC4_CCU41_CC43_BASE 0x40010400 -#define XMC4_CCU42_BASE 0x40014000 +#define XMC4_CCU42_BASE 0x40014000 /* CCU42 */ #define XMC4_CCU42_CC40_BASE 0x40014100 #define XMC4_CCU42_CC41_BASE 0x40014200 #define XMC4_CCU42_CC42_BASE 0x40014300 #define XMC4_CCU42_CC43_BASE 0x40014400 -#define XMC4_CCU80_BASE 0x40020000 +#define XMC4_CCU80_BASE 0x40020000 /* CCU80 */ #define XMC4_CCU80_CC80_BASE 0x40020100 #define XMC4_CCU80_CC81_BASE 0x40020200 #define XMC4_CCU80_CC82_BASE 0x40020300 #define XMC4_CCU80_CC83_BASE 0x40020400 -#define XMC4_CCU81_BASE 0x40024000 +#define XMC4_CCU81_BASE 0x40024000 /* CCU81 */ #define XMC4_CCU81_CC80_BASE 0x40024100 #define XMC4_CCU81_CC81_BASE 0x40024200 #define XMC4_CCU81_CC82_BASE 0x40024300 #define XMC4_CCU81_CC83_BASE 0x40024400 -#define XMC4_POSIF0_BASE 0x40028000 -#define XMC4_POSIF1_BASE 0x4002c000 -#define XMC4_USIC0_BASE 0x40030000 +#define XMC4_POSIF0_BASE 0x40028000 /* POSIF0 */ +#define XMC4_POSIF1_BASE 0x4002c000 /* POSIF1 */ +#define XMC4_USIC0_BASE 0x40030000 /* USIC0 */ #define XMC4_USIC0_CH0_BASE 0x40030000 #define XMC4_USIC0_CH1_BASE 0x40030200 #define XMC4_USIC0_RAM_BASE 0x40030400 -#define XMC4_ERU1_BASE 0x40044000 +#define XMC4_ERU1_BASE 0x40044000 /* ERU1 */ -#define XMC4_PBA1_BASE 0x48000000 -#define XMC4_CCU43_BASE 0x48004000 +#define XMC4_PBA1_BASE 0x48000000 /* PBA1 */ +#define XMC4_CCU43_BASE 0x48004000 /* CCU43 */ #define XMC4_CCU43_CC40_BASE 0x48004100 #define XMC4_CCU43_CC41_BASE 0x48004200 #define XMC4_CCU43_CC42_BASE 0x48004300 #define XMC4_CCU43_CC43_BASE 0x48004400 -#define XMC4_LEDTS0_BASE 0x48010000 -#define XMC4_CAN_BASE 0x48014000 +#define XMC4_LEDTS0_BASE 0x48010000 /* LEDTS0 */ +#define XMC4_CAN_BASE 0x48014000 /* MultiCAN */ #define XMC4_CAN_NODE0_BASE 0x48014200 #define XMC4_CAN_NODE1_BASE 0x48014300 #define XMC4_CAN_NODE2_BASE 0x48014400 @@ -138,18 +138,18 @@ #define XMC4_CAN_NODE4_BASE 0x48014600 #define XMC4_CAN_NODE5_BASE 0x48014700 #define XMC4_CAN_MO_BASE 0x48015000 -#define XMC4_DAC_BASE 0x48018000 -#define XMC4_SDMMC_BASE 0x4801c000 -#define XMC4_USIC1_BASE 0x48020000 +#define XMC4_DAC_BASE 0x48018000 /* DAC */ +#define XMC4_SDMMC_BASE 0x4801c000 /* SDMMC */ +#define XMC4_USIC1_BASE 0x48020000 /* USIC1 */ #define XMC4_USIC1_CH0_BASE 0x48020000 #define XMC4_USIC1_CH1_BASE 0x48020200 #define XMC4_USIC1_RAM_BASE 0x48020400 -#define XMC4_USIC2_BASE 0x48024000 +#define XMC4_USIC2_BASE 0x48024000 /* USIC2 */ #define XMC4_USIC2_CH0_BASE 0x48024000 #define XMC4_USIC2_CH1_BASE 0x48024200 #define XMC4_USIC2_RAM_BASE 0x48024400 #define XMC4_PORT_BASE(n) (0x48028000 + ((n) << 8)) -#define XMC4_PORT0_BASE 0x48028000 +#define XMC4_PORT0_BASE 0x48028000 /* PORTS */ #define XMC4_PORT1_BASE 0x48028100 #define XMC4_PORT2_BASE 0x48028200 #define XMC4_PORT3_BASE 0x48028300 @@ -162,7 +162,8 @@ #define XMC4_PORT14_BASE 0x48028e00 #define XMC4_PORT15_BASE 0x48028f00 -#define XMC4_SCU_GENERAL_BASE 0x50004000 +#define XMC4_PBA2_BASE 0x50000000 /* PBA2 */ +#define XMC4_SCU_GENERAL_BASE 0x50004000 /* SCU & RTC */ #define XMC4_ETH0_CON_BASE 0x50004040 #define XMC4_SCU_INTERRUPT_BASE 0x50004074 #define XMC4_SDMMC_CON_BASE 0x500040b4 @@ -177,9 +178,28 @@ #define XMC4_ERU0_BASE 0x50004800 #define XMC4_DLR_BASE 0x50004900 #define XMC4_RTC_BASE 0x50004a00 -#define XMC4_WDT_BASE 0x50008000 -#define XMC4_ETH0_BASE 0x5000c000 -#define XMC4_USB0_BASE 0x50040000 +#define XMC4_WDT_BASE 0x50008000 /* WDT */ +#define XMC4_ETH0_BASE 0x5000c000 /* ETH */ +#define XMC4_GPDMA0_CH0_BASE 0x50014000 /* GPDMA0 */ +#define XMC4_GPDMA0_CH1_BASE 0x50014058 +#define XMC4_GPDMA0_CH2_BASE 0x500140b0 +#define XMC4_GPDMA0_CH3_BASE 0x50014108 +#define XMC4_GPDMA0_CH4_BASE 0x50014160 +#define XMC4_GPDMA0_CH5_BASE 0x500141b8 +#define XMC4_GPDMA0_CH6_BASE 0x50014210 +#define XMC4_GPDMA0_CH7_BASE 0x50014268 +#define XMC4_GPDMA0_BASE 0x500142c0 +#define XMC4_GPDMA1_CH0_BASE 0x50018000 /* GPDMA1 */ +#define XMC4_GPDMA1_CH1_BASE 0x50018058 +#define XMC4_GPDMA1_CH2_BASE 0x500180b0 +#define XMC4_GPDMA1_CH3_BASE 0x50018108 +#define XMC4_GPDMA1_BASE 0x500182c0 +#define XMC4_FCE_BASE 0x50020000 /* FCE */ +#define XMC4_FCE_KE0_BASE 0x50020020 +#define XMC4_FCE_KE1_BASE 0x50020040 +#define XMC4_FCE_KE2_BASE 0x50020060 +#define XMC4_FCE_KE3_BASE 0x50020080 +#define XMC4_USB0_BASE 0x50040000 /* USB0 */ #define XMC4_USB0_CH0_BASE 0x50040500 #define XMC4_USB0_CH1_BASE 0x50040520 #define XMC4_USB0_CH2_BASE 0x50040540 @@ -201,30 +221,22 @@ #define XMC4_USB0_EP4_BASE 0x50040980 #define XMC4_USB0_EP5_BASE 0x500409a0 #define XMC4_USB0_EP6_BASE 0x500409c0 -#define XMC4_GPDMA0_CH0_BASE 0x50014000 -#define XMC4_GPDMA0_CH1_BASE 0x50014058 -#define XMC4_GPDMA0_CH2_BASE 0x500140b0 -#define XMC4_GPDMA0_CH3_BASE 0x50014108 -#define XMC4_GPDMA0_CH4_BASE 0x50014160 -#define XMC4_GPDMA0_CH5_BASE 0x500141b8 -#define XMC4_GPDMA0_CH6_BASE 0x50014210 -#define XMC4_GPDMA0_CH7_BASE 0x50014268 -#define XMC4_GPDMA0_BASE 0x500142c0 -#define XMC4_GPDMA1_CH0_BASE 0x50018000 -#define XMC4_GPDMA1_CH1_BASE 0x50018058 -#define XMC4_GPDMA1_CH2_BASE 0x500180b0 -#define XMC4_GPDMA1_CH3_BASE 0x50018108 -#define XMC4_GPDMA1_BASE 0x500182c0 -#define XMC4_FCE_BASE 0x50020000 -#define XMC4_FCE_KE0_BASE 0x50020020 -#define XMC4_FCE_KE1_BASE 0x50020040 -#define XMC4_FCE_KE2_BASE 0x50020060 -#define XMC4_FCE_KE3_BASE 0x50020080 +#define XMC4_USB0_EP6_BASE 0x50100000 /* ECAT0 */ -#define XMC4_PMU0_BASE 0x58000500 +#define XMC4_PMU0_BASE 0x58000000 /* PMU0 registers */ #define XMC4_FLASH0_BASE 0x58001000 -#define XMC4_PREF_BASE 0x58004000 -#define XMC4_EBU_BASE 0x58008000 +#define XMC4_PREF_BASE 0x58004000 /* PMU0 prefetch */ +#define XMC4_EBU_BASE 0x58008000 /* EBU registers */ + +#define XMC4_EBUMEM_CS0 0x60000000 /* EBU memory CS0 */ +#define XMC4_EBUMEM_CS1 0x64000000 /* EBU memory CS1 */ +#define XMC4_EBUMEM_CS2 0x68000000 /* EBU memory CS2 */ +#define XMC4_EBUMEM_CS3 0x6c000000 /* EBU memory CS3 */ + +#define XMC4_EBUDEV_CS0 0xa0000000 /* EBU devices CS0 */ +#define XMC4_EBUDEV_CS1 0xa4000000 /* EBU devices CS1 */ +#define XMC4_EBUDEV_CS2 0xa8000000 /* EBU devices CS2 */ +#define XMC4_EBUDEV_CS3 0xac000000 /* EBU devices CS3 */ #define XMC4_PPB_BASE 0xe000e000 From 886dadae0aa4994cb092003a0c60a1423b90b409 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 20 Mar 2017 18:10:23 -0600 Subject: [PATCH 62/81] XMC4xxx: Minor updates to naming and comments --- arch/arm/include/xmc4/chip.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/include/xmc4/chip.h b/arch/arm/include/xmc4/chip.h index 5c3fcdabfa2..6507917fe6b 100644 --- a/arch/arm/include/xmc4/chip.h +++ b/arch/arm/include/xmc4/chip.h @@ -51,23 +51,23 @@ #if defined(CONFIG_ARCH_CHIP_XMC4500) # define XMC4_NUSIC 3 /* Three USIC modules: USCI0-2 */ # undef XMC4_SCU_GATING /* No clock gating registers */ -# define XMC4_NECATN 0 /* No EtherCAT support */ +# define XMC4_NECAT 0 /* No EtherCAT support */ #elif defined(CONFIG_ARCH_CHIP_XMC4700) # define XMC4_NUSIC 3 /* Three USIC modules: USCI0-2 */ # define XMC4_SCU_GATING 1 /* Has clock gating registers */ -# define XMC4_NECATN 0 /* No EtherCAT support */ +# define XMC4_NECAT 0 /* No EtherCAT support */ #elif defined(CONFIG_ARCH_CHIP_XMC4700) # define XMC4_NUSIC 3 /* Three USIC modules: USCI0-2 */ # define XMC4_SCU_GATING 1 /* Has clock gating registers */ -# define XMC4_NECATN 1 /* One EtherCAT module */ +# define XMC4_NECAT 1 /* One EtherCAT module */ #else # error "Unsupported XMC4xxx chip" #endif /* NVIC priority levels *************************************************************/ -/* Each priority field holds a priority value, 0-15. The lower the value, the greater - * the priority of the corresponding interrupt. The XMC4500 implements only - * bits[7:2] of this field, bits[1:0] read as zero and ignore writes. +/* Each priority field holds a priority value. The lower the value, the greater the + * priority of the corresponding interrupt. The XMC4500 implements only bits[7:2] + * of this field, bits[1:0] read as zero and ignore writes. */ #define NVIC_SYSH_PRIORITY_MIN 0xfc /* All bits[7:2] set is minimum priority */ From 591f91ebd33b2107880fdafbcca0c4b1d96a3677 Mon Sep 17 00:00:00 2001 From: Masayuki Ishikawa Date: Tue, 21 Mar 2017 15:30:23 +0900 Subject: [PATCH 63/81] drivers/lcd/st7565.c: Extend to include support for the AQM_1248A --- drivers/lcd/Kconfig | 6 ++++++ drivers/lcd/st7565.c | 21 +++++++++++++++++++++ drivers/lcd/st7565.h | 4 ++++ 3 files changed, 31 insertions(+) diff --git a/drivers/lcd/Kconfig b/drivers/lcd/Kconfig index b3abcaeabd8..565ab07301b 100644 --- a/drivers/lcd/Kconfig +++ b/drivers/lcd/Kconfig @@ -48,6 +48,7 @@ config LCD_NOGETRUN config LCD_MAXCONTRAST int "LCD maximum contrast" + default 31 if AQM_1248A default 63 if NOKIA6100_S1D15G10 || LCD_SHARP_MEMLCD default 127 if NOKIA6100_PCF8833 default 255 if LCD_P14201 || LCD_LCD1602 @@ -596,6 +597,9 @@ config NHD_C12864KGZ config ERC_12864_3 bool "like ERC12864-3" +config AQM_1248A + bool "like AQM1248A" + endchoice config ST7565_NINTERFACES @@ -613,6 +617,7 @@ config ST7565_XRES config ST7565_YRES int "ST7565 Y Resolution" + default 48 if AQM_1248A default 64 ---help--- Specifies the Y resolution of the LCD. @@ -625,6 +630,7 @@ config ST7565_MIRROR_X config ST7565_MIRROR_Y bool "ST7565 apply mirror on Y" + default y if AQM_1248A default n ---help--- Mirror Y on LCD. diff --git a/drivers/lcd/st7565.c b/drivers/lcd/st7565.c index 0e52b58a3ec..1153c1568bb 100644 --- a/drivers/lcd/st7565.c +++ b/drivers/lcd/st7565.c @@ -1030,6 +1030,27 @@ FAR struct lcd_dev_s *st7565_initialize(FAR struct st7565_lcd_s *lcd, (void)st7565_send_one_data(priv, ST7565_SETEVREG(0x24)); (void)st7565_send_one_data(priv, ST7565_SETSTARTLINE); +#elif defined(CONFIG_AQM_1248A) + + (void)st7565_send_one_data(priv, ST7565_DISPOFF); + (void)st7565_send_one_data(priv, ST7565_ADCNORMAL); + (void)st7565_send_one_data(priv, ST7565_SETCOMREVERSE); + (void)st7565_send_one_data(priv, ST7565_BIAS_1_7); + + (void)st7565_send_one_data(priv, ST7565_POWERCTRL_B); + up_mdelay(2); + (void)st7565_send_one_data(priv, ST7565_POWERCTRL_BR); + up_mdelay(2); + (void)st7565_send_one_data(priv, ST7565_POWERCTRL_BRF); + + (void)st7565_send_one_data(priv, ST7565_REG_RES_4_5); + (void)st7565_send_one_data(priv, ST7565_SETEVMODE); + (void)st7565_send_one_data(priv, ST7565_SETEVREG(0x1c)); + (void)st7565_send_one_data(priv, ST7565_DISPRAM); + (void)st7565_send_one_data(priv, ST7565_SETSTARTLINE); + (void)st7565_send_one_data(priv, ST7565_DISPNORMAL); + (void)st7565_send_one_data(priv, ST7565_DISPON); + #else # error "No initialization sequence selected" #endif diff --git a/drivers/lcd/st7565.h b/drivers/lcd/st7565.h index 0855f5e8ecc..e4788379b9e 100644 --- a/drivers/lcd/st7565.h +++ b/drivers/lcd/st7565.h @@ -100,6 +100,10 @@ #define ST7565_POWERCTRL_VR 0x2b /* 0x2b: Only the voltage regulator circuit and the * voltage follower circuit are used */ +#define ST7565_POWERCTRL_B 0x2c /* 0x2c: Booster=ON */ +#define ST7565_POWERCTRL_BR 0x2e /* 0x2e: Booster=ON V/R=ON */ +#define ST7565_POWERCTRL_BRF 0x2f /* 0x23: Booster=ON V/R=ON V/F=ON */ + #define ST7565_POWERCTRL_INT 0x2f /* 0x2f: Only the internal power supply is used */ /* Regulation Resistior ratio V0 = (1+Rb/Ra)*Vev */ From c3d9b86662ceec2f8e9e3c6fe0092fb7f11e0aa5 Mon Sep 17 00:00:00 2001 From: Juha Niskanen Date: Tue, 21 Mar 2017 07:12:07 -0600 Subject: [PATCH 64/81] input/mxt: prevent overriding i2c transfer return value put_reg/get_reg function was overriding i2c transfer error code with i2creset return value, that lead to OK status although actual transfer failed. Signed-off-by: Juha Niskanen Reported-by: Harri Luhtala --- drivers/input/mxt.c | 44 +++++++++++++++++++++++++++++--------------- 1 file changed, 29 insertions(+), 15 deletions(-) diff --git a/drivers/input/mxt.c b/drivers/input/mxt.c index f19c2bb0be5..dcd26a2b198 100644 --- a/drivers/input/mxt.c +++ b/drivers/input/mxt.c @@ -88,6 +88,10 @@ #define INVALID_POSITION 0x1000 +/* Maximum number of retries */ + +#define MAX_RETRIES 3 + /* Get a 16-bit value in little endian order (not necessarily aligned). The * source data is in little endian order. The host byte order does not * matter in this case. @@ -311,7 +315,7 @@ static int mxt_getreg(FAR struct mxt_dev_s *priv, uint16_t regaddr, /* Try up to three times to read the register */ - for (retries = 1; retries <= 3; retries++) + for (retries = 1; retries <= MAX_RETRIES; retries++) { iinfo("retries=%d regaddr=%04x buflen=%d\n", retries, regaddr, buflen); @@ -342,15 +346,20 @@ static int mxt_getreg(FAR struct mxt_dev_s *priv, uint16_t regaddr, if (ret < 0) { #ifdef CONFIG_I2C_RESET - /* Perhaps the I2C bus is locked up? Try to shake the bus free */ + /* Perhaps the I2C bus is locked up? Try to shake the bus free. + * Don't bother with the reset if this was the last attempt. + */ - iwarn("WARNING: I2C_TRANSFER failed: %d ... Resetting\n", ret); - - ret = I2C_RESET(priv->i2c); - if (ret < 0) + if (retries < MAX_RETRIES) { - ierr("ERROR: I2C_RESET failed: %d\n", ret); - break; + iwarn("WARNING: I2C_TRANSFER failed: %d ... Resetting\n", ret); + + ret = I2C_RESET(priv->i2c); + if (ret < 0) + { + ierr("ERROR: I2C_RESET failed: %d\n", ret); + break; + } } #else ierr("ERROR: I2C_TRANSFER failed: %d\n", ret); @@ -385,7 +394,7 @@ static int mxt_putreg(FAR struct mxt_dev_s *priv, uint16_t regaddr, /* Try up to three times to read the register */ - for (retries = 1; retries <= 3; retries++) + for (retries = 1; retries <= MAX_RETRIES; retries++) { iinfo("retries=%d regaddr=%04x buflen=%d\n", retries, regaddr, buflen); @@ -416,14 +425,19 @@ static int mxt_putreg(FAR struct mxt_dev_s *priv, uint16_t regaddr, if (ret < 0) { #ifdef CONFIG_I2C_RESET - /* Perhaps the I2C bus is locked up? Try to shake the bus free */ + /* Perhaps the I2C bus is locked up? Try to shake the bus free. + * Don't bother with the reset if this was the last attempt. + */ - iwarn("WARNING: I2C_TRANSFER failed: %d ... Resetting\n", ret); - - ret = I2C_RESET(priv->i2c); - if (ret < 0) + if (retries < MAX_RETRIES) { - ierr("ERROR: I2C_RESET failed: %d\n", ret); + iwarn("WARNING: I2C_TRANSFER failed: %d ... Resetting\n", ret); + + ret = I2C_RESET(priv->i2c); + if (ret < 0) + { + ierr("ERROR: I2C_RESET failed: %d\n", ret); + } } #else ierr("ERROR: I2C_TRANSFER failed: %d\n", ret); From 3872055daa9e9d8410a3e356a0a61248239ed43f Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 21 Mar 2017 07:20:45 -0600 Subject: [PATCH 65/81] drivers/audio/wm8904: WM8904 has same problem as that fixed by Juha Niskanen in the MaxTouch driver. --- drivers/audio/wm8904.c | 52 ++++++++++++++++++++++++++++-------------- drivers/input/mxt.c | 2 +- 2 files changed, 36 insertions(+), 18 deletions(-) diff --git a/drivers/audio/wm8904.c b/drivers/audio/wm8904.c index 4489ae0f221..23da3ce9a9d 100644 --- a/drivers/audio/wm8904.c +++ b/drivers/audio/wm8904.c @@ -3,7 +3,7 @@ * * Audio device driver for Wolfson Microelectronics WM8904 Audio codec. * - * Copyright (C) 2014, 2016 Gregory Nutt. All rights reserved. + * Copyright (C) 2014, 2016-2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * References: @@ -73,6 +73,14 @@ #include "wm8904.h" +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Maximum number of retries */ + +#define MAX_RETRIES 3 + /**************************************************************************** * Private Function Prototypes ****************************************************************************/ @@ -251,7 +259,7 @@ uint16_t wm8904_readreg(FAR struct wm8904_dev_s *priv, uint8_t regaddr) /* Try up to three times to read the register */ - for (retries = 1; retries <= 3; retries++) + for (retries = 1; retries <= MAX_RETRIES; retries++) { struct i2c_msg_s msg[2]; uint8_t data[2]; @@ -281,15 +289,20 @@ uint16_t wm8904_readreg(FAR struct wm8904_dev_s *priv, uint8_t regaddr) if (ret < 0) { #ifdef CONFIG_I2C_RESET - /* Perhaps the I2C bus is locked up? Try to shake the bus free */ + /* Perhaps the I2C bus is locked up? Try to shake the bus free. + * Don't bother with the reset if this was the last attempt. + */ - audwarn("WARNING: I2C_TRANSFER failed: %d ... Resetting\n", ret); - - ret = I2C_RESET(priv->i2c); - if (ret < 0) + if (retries < MAX_RETRIES) { - auderr("ERROR: I2C_RESET failed: %d\n", ret); - break; + audwarn("WARNING: I2C_TRANSFER failed: %d ... Resetting\n", ret); + + ret = I2C_RESET(priv->i2c); + if (ret < 0) + { + auderr("ERROR: I2C_RESET failed: %d\n", ret); + break; + } } #else auderr("ERROR: I2C_TRANSFER failed: %d\n", ret); @@ -338,7 +351,7 @@ static void wm8904_writereg(FAR struct wm8904_dev_s *priv, uint8_t regaddr, /* Try up to three times to read the register */ - for (retries = 1; retries <= 3; retries++) + for (retries = 1; retries <= MAX_RETRIES; retries++) { uint8_t data[3]; int ret; @@ -357,15 +370,20 @@ static void wm8904_writereg(FAR struct wm8904_dev_s *priv, uint8_t regaddr, if (ret < 0) { #ifdef CONFIG_I2C_RESET - /* Perhaps the I2C bus is locked up? Try to shake the bus free */ + /* Perhaps the I2C bus is locked up? Try to shake the bus free. + * Don't bother with the reset if this was the last attempt. + */ - audwarn("WARNING: i2c_write failed: %d ... Resetting\n", ret); - - ret = I2C_RESET(priv->i2c); - if (ret < 0) + if (retries < MAX_RETRIES) { - auderr("ERROR: I2C_RESET failed: %d\n", ret); - break; + audwarn("WARNING: i2c_write failed: %d ... Resetting\n", ret); + + ret = I2C_RESET(priv->i2c); + if (ret < 0) + { + auderr("ERROR: I2C_RESET failed: %d\n", ret); + break; + } } #else auderr("ERROR: I2C_TRANSFER failed: %d\n", ret); diff --git a/drivers/input/mxt.c b/drivers/input/mxt.c index dcd26a2b198..e1152851719 100644 --- a/drivers/input/mxt.c +++ b/drivers/input/mxt.c @@ -1,7 +1,7 @@ /**************************************************************************** * drivers/input/mxt.c * - * Copyright (C) 2014, 2016 Gregory Nutt. All rights reserved. + * Copyright (C) 2014, 2016-2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without From 805a4f65e97f1f082bb66f8c5f2a7cd684620a40 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 21 Mar 2017 09:31:44 -0600 Subject: [PATCH 66/81] XMC4xxx: Fixes to HIB domain setup, GPIO pin configuration. --- arch/arm/include/xmc4/xmc4500_irq.h | 2 +- arch/arm/src/xmc4/chip/xmc4_memorymap.h | 2 +- arch/arm/src/xmc4/chip/xmc4_ports.h | 4 ++-- arch/arm/src/xmc4/xmc4_clockconfig.c | 8 ++++---- arch/arm/src/xmc4/xmc4_gpio.h | 8 ++++---- 5 files changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arm/include/xmc4/xmc4500_irq.h b/arch/arm/include/xmc4/xmc4500_irq.h index dfd21d6c21d..b35a1b3f8a2 100644 --- a/arch/arm/include/xmc4/xmc4500_irq.h +++ b/arch/arm/include/xmc4/xmc4500_irq.h @@ -184,7 +184,7 @@ #define XMC4_IRQ_SDMMC_SR0 (XMC4_IRQ_FIRST+106) /* 106: SDMMC, SR0 */ #define XMC4_IRQ_USB0_SR0 (XMC4_IRQ_FIRST+107) /* 107: USB, SR0 */ #define XMC4_IRQ_ETH0_SR0 (XMC4_IRQ_FIRST+108) /* 108: Ethernet, module 0, SR0 */ -#define XMC4_IRQ_RESVD109 (XMC4_IRQ_FIRST+109) /* 109: Reserved */ +#define XMC4_IRQ_ECAT0_SR0 (XMC4_IRQ_FIRST+109) /* 109: EtherCAT, module 0, SR0 */ #define XMC4_IRQ_GPCMA1_SR0 (XMC4_IRQ_FIRST+110) /* 110: GPDMA1, SR0 */ #define XMC4_IRQ_RESVD111 (XMC4_IRQ_FIRST+111) /* 111: Reserved */ diff --git a/arch/arm/src/xmc4/chip/xmc4_memorymap.h b/arch/arm/src/xmc4/chip/xmc4_memorymap.h index a2df7e405ce..a326460cc7b 100644 --- a/arch/arm/src/xmc4/chip/xmc4_memorymap.h +++ b/arch/arm/src/xmc4/chip/xmc4_memorymap.h @@ -221,7 +221,7 @@ #define XMC4_USB0_EP4_BASE 0x50040980 #define XMC4_USB0_EP5_BASE 0x500409a0 #define XMC4_USB0_EP6_BASE 0x500409c0 -#define XMC4_USB0_EP6_BASE 0x50100000 /* ECAT0 */ +#define XMC4_ECAT0_BASE 0x50100000 /* ECAT0 */ #define XMC4_PMU0_BASE 0x58000000 /* PMU0 registers */ #define XMC4_FLASH0_BASE 0x58001000 diff --git a/arch/arm/src/xmc4/chip/xmc4_ports.h b/arch/arm/src/xmc4/chip/xmc4_ports.h index bdd90c2902b..d42665b908c 100644 --- a/arch/arm/src/xmc4/chip/xmc4_ports.h +++ b/arch/arm/src/xmc4/chip/xmc4_ports.h @@ -71,7 +71,7 @@ #define XMC4_PORT_OUT_OFFSET 0x0000 /* Port Output Register */ #define XMC4_PORT_OMR_OFFSET 0x0004 /* Port Output Modification Register */ -#define XMC4_PORT_IOCR_OFFSET(n) (0x0010 + ((n) & 3)) +#define XMC4_PORT_IOCR_OFFSET(n) (0x0010 + ((n) & ~3)) #define XMC4_PORT_IOCR0_OFFSET 0x0010 /* Port Input/Output Control Register 0 */ #define XMC4_PORT_IOCR4_OFFSET 0x0014 /* Port Input/Output Control Register 4 */ #define XMC4_PORT_IOCR8_OFFSET 0x0018 /* Port Input/Output Control Register 8 */ @@ -79,7 +79,7 @@ #define XMC4_PORT_IN_OFFSET 0x0024 /* Port Input Register */ -#define XMC4_PORT_PDR_OFFSET(n) (0x0010 + (((n) >> 1) & 3)) +#define XMC4_PORT_PDR_OFFSET(n) (0x0010 + (((n) >> 1) & ~3)) #define XMC4_PORT_PDR0_OFFSET 0x0040 /* Port Pad Driver Mode 0 Register */ #define XMC4_PORT_PDR1_OFFSET 0x0044 /* Port Pad Driver Mode 1 Register */ diff --git a/arch/arm/src/xmc4/xmc4_clockconfig.c b/arch/arm/src/xmc4/xmc4_clockconfig.c index db72a3cdf9c..a28cf7fd51f 100644 --- a/arch/arm/src/xmc4/xmc4_clockconfig.c +++ b/arch/arm/src/xmc4/xmc4_clockconfig.c @@ -182,9 +182,9 @@ void xmc4_clock_configure(void) regval = getreg32(XMC4_SCU_PWRSTAT); if ((regval & SCU_PWR_HIBEN) == 0) { - regval = getreg32(XMC4_SCU_PWRSET); - regval |= SCU_PWR_HIBEN; - putreg32(regval, XMC4_SCU_PWRSTAT); + /* Enable the HIB domain */ + + putreg32(SCU_PWR_HIBEN, XMC4_SCU_PWRSET); /* Wait until HIB domain is enabled */ @@ -193,7 +193,7 @@ void xmc4_clock_configure(void) } } - /* Remove the reset only if HIB domain were in a state of reset */ + /* Remove the reset only if HIB domain was in a state of reset */ regval = getreg32(XMC4_SCU_RSTSTAT); if ((regval & SCU_RSTSTAT_HIBRS) != 0) diff --git a/arch/arm/src/xmc4/xmc4_gpio.h b/arch/arm/src/xmc4/xmc4_gpio.h index 4595fe6a795..0dce7af73cd 100644 --- a/arch/arm/src/xmc4/xmc4_gpio.h +++ b/arch/arm/src/xmc4/xmc4_gpio.h @@ -79,8 +79,8 @@ # define GPIO_OUTPUT_ALT4 (IOCR_OUTPUT_ALT4 << GPIO_PINTYPE_SHIFT) # define _GPIO_OUTPUT_BIT (16 << GPIO_PINTYPE_SHIFT) -# define GPIO_ISINPUT(p) (((p) & _GPIO_OUTPUT_BIT) != 0) -# define GPIO_ISOUTPUT(p) (((p) & _GPIO_OUTPUT_BIT) == 0) +# define GPIO_ISINPUT(p) (((p) & _GPIO_OUTPUT_BIT) == 0) +# define GPIO_ISOUTPUT(p) (((p) & _GPIO_OUTPUT_BIT) != 0) /* Pin type modifier: * @@ -160,7 +160,7 @@ */ #define GPIO_PORT_SHIFT (4) /* Bit 4-7: Port number */ -#define GPIO_PORT_MASK (7 << GPIO_PORT_SHIFT) +#define GPIO_PORT_MASK (15 << GPIO_PORT_SHIFT) # define GPIO_PORT0 (0 << GPIO_PORT_SHIFT) # define GPIO_PORT1 (1 << GPIO_PORT_SHIFT) # define GPIO_PORT2 (2 << GPIO_PORT_SHIFT) @@ -180,7 +180,7 @@ */ #define GPIO_PIN_SHIFT (0) /* Bits 0-3: GPIO pin: 0-15 */ -#define GPIO_PIN_MASK (31 << GPIO_PIN_SHIFT) +#define GPIO_PIN_MASK (15 << GPIO_PIN_SHIFT) #define GPIO_PIN0 (0 << GPIO_PIN_SHIFT) #define GPIO_PIN1 (1 << GPIO_PIN_SHIFT) #define GPIO_PIN2 (2 << GPIO_PIN_SHIFT) From 1e9bc166d4d658491a8f1f353402172f70cfe510 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 21 Mar 2017 10:02:23 -0600 Subject: [PATCH 67/81] XMC4500 Relax: Add README.txt file. Fix some comments. --- Documentation/README.html | 4 +- README.txt | 2 + configs/xmc4500-relax/README.txt | 154 ++++++++++++++++++++++ configs/xmc4500-relax/include/board.h | 7 +- configs/xmc4500-relax/src/xmc4_autoleds.c | 26 ++-- 5 files changed, 174 insertions(+), 19 deletions(-) create mode 100644 configs/xmc4500-relax/README.txt diff --git a/Documentation/README.html b/Documentation/README.html index 2f9ba9066b2..4430ef211f7 100644 --- a/Documentation/README.html +++ b/Documentation/README.html @@ -8,7 +8,7 @@

NuttX README Files

-

Last Updated: February 19, 2017

+

Last Updated: March 21, 2017

@@ -297,6 +297,8 @@ nuttx/ | | `- README.txt | |- viewtool-stm32f107/ | | `- README.txt + | |- xmc4500-relax/ + | | `- README.txt | |- xtrs/ | | `- README.txt | |- z16f2800100zcog/ diff --git a/README.txt b/README.txt index ed3d41c30f8..4bab1306ff7 100644 --- a/README.txt +++ b/README.txt @@ -1681,6 +1681,8 @@ nuttx/ | | `- README.txt | |- viewtool-stm32f107/ | | `- README.txt + | |- xmc5400-relax/ + | | `- README.txt | |- xtrs/ | | `- README.txt | |- z16f2800100zcog/ diff --git a/configs/xmc4500-relax/README.txt b/configs/xmc4500-relax/README.txt new file mode 100644 index 00000000000..0ee63341d44 --- /dev/null +++ b/configs/xmc4500-relax/README.txt @@ -0,0 +1,154 @@ +README for the XMC4500 Relax +============================ + + The directory provides board support for the Infinion XMC4500 Relax v1 + boards. There are to variants of this board: There is a Lite version + that has fewer features, for example, no 32.768KHz crystal. + + The current configurations support only the Lite version of the board. + +Serial Console +============== + + Be default, UART0 (aka, USIC0, channel 0) is used as the serial console. + The RX and TX pins is available: + + RX - P1.4, Connector X2, pin 17 + TX - P1.5, Connector X2, pin 17 + GND - Available on pins 1-4 of either connector X1 or X2 + VDD3.3 - Available on pins 37-38 of either connector X1 or X2 + VDD5 - Available on pins 39-40 of either connector X1 or X2 + +LEDs +==== + + The XMC4500 Relax Lite v1 board has two LEDs: + + LED1 P1.1 High output illuminates + LED2 P1.0 High output illuminates + + If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in + any way. The definitions provided in the board.h header file can be used + to access individual LEDs. + + These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is + defined. In that case, the usage by the board port is defined in + include/board.h and src/sam_autoleds.c. The LEDs are used to encode + OS-related events as follows: + + SYMBOL Meaning LED state + LED1 LED2 + ------------------ ------------------------ ------ ------ + LED_STARTED NuttX has been started OFF OFF + LED_HEAPALLOCATE Heap has been allocated OFF OFF + LED_IRQSENABLED Interrupts enabled OFF OFF + LED_STACKCREATED Idle stack created ON OFF + LED_INIRQ In an interrupt No change + LED_SIGNAL In a signal handler No change + LED_ASSERTION An assertion failed No change + LED_PANIC The system has crashed N/C Blinking + LED_IDLE MCU is is sleep mode Not used + + Thus if LED1 is statically on, NuttX has successfully booted and is, + apparently, running normally. If LED2 is flashing at approximately + 2Hz, then a fatal error has been detected and the system has halted. + +Buttons +======= + + The XMC4500 Relax Lite v1 board has two buttons: + + BUTTON1 P1.14 Low input sensed when button pressed + BUTTON2 P1.15 Low input sensed when button pressed + +Configurations +============== + + Information Common to All Configurations + ---------------------------------------- + Each XMC4500 Relax configuration is maintained in a sub-directory and + can be selected as follow: + + cd tools + ./configure.sh xmc5400-relax/ + cd - + . ./setenv.sh + + Before sourcing the setenv.sh file above, you should examine it and + perform edits as necessary so that TOOLCHAIN_BIN is the correct path + to the directory than holds your toolchain binaries. + + And then build NuttX by simply typing the following. At the conclusion of + the make, the nuttx binary will reside in an ELF file called, simply, nuttx. + + make oldconfig + make + + The that is provided above as an argument to the tools/configure.sh + must be is one of the following. + + NOTES: + + 1. These configurations use the mconf-based configuration tool. To + change any of these configurations using that tool, you should: + + a. Build and install the kconfig-mconf tool. See nuttx/README.txt + see additional README.txt files in the NuttX tools repository. + + b. Execute 'make menuconfig' in nuttx/ in order to start the + reconfiguration process. + + 2. Unless stated otherwise, all configurations generate console + output on UART0 (aka USIC0, channel 0) as described above under + "Serial Console". The relevant configuration settings are listed + below: + + CONFIG_XMC4_USIC0=y + CONFIG_XMC4_USIC0_CHAN0_ISUART=y + CONFIG_XMC4_USIC0_CHAN1_NONE=y + + CONFIG_UART0_SERIALDRIVER=y + CONFIG_UART0_SERIAL_CONSOLE=y + + CONFIG_UART0_RXBUFSIZE=256 + CONFIG_UART0_TXBUFSIZE=256 + CONFIG_UART0_BAUD=115200 + CONFIG_UART0_BITS=8 + CONFIG_UART0_PARITY=0 + CONFIG_UART0_2STOP=0 + + + 3. All of these configurations are set up to build under Windows using the + "GNU Tools for ARM Embedded Processors" that is maintained by ARM + (unless stated otherwise in the description of the configuration). + + https://launchpad.net/gcc-arm-embedded + + That toolchain selection can easily be reconfigured using + 'make menuconfig'. Here are the relevant current settings: + + Build Setup: + CONFIG_HOST_WINDOWS=y : Window environment + CONFIG_WINDOWS_CYGWIN=y : Cywin under Windows + + System Type -> Toolchain: + CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIW=y : GNU ARM EABI toolchain + + Configuration sub-directories + ----------------------------- + + nsh: + + Configures the NuttShell (nsh) located at examples/nsh. This + configuration is focused on low level, command-line driver testing. It + has no network. + + NOTES: + + 1. NSH built-in applications are supported. + + Binary Formats: + CONFIG_BUILTIN=y : Enable support for built-in programs + + Application Configuration: + CONFIG_NSH_BUILTIN_APPS=y : Enable starting apps from NSH command line diff --git a/configs/xmc4500-relax/include/board.h b/configs/xmc4500-relax/include/board.h index 6be8e787f23..9c3121a4b63 100644 --- a/configs/xmc4500-relax/include/board.h +++ b/configs/xmc4500-relax/include/board.h @@ -171,12 +171,9 @@ #define LED_PANIC 3 /* The system has crashed N/C Blinking */ #undef LED_IDLE /* MCU is is sleep mode Not used */ -/* Thus if LED0 is statically on, NuttX has successfully booted and is, - * apparently, running normally. If LED1 is flashing at approximately +/* Thus if LED1 is statically on, NuttX has successfully booted and is, + * apparently, running normally. If LED2 is flashing at approximately * 2Hz, then a fatal error has been detected and the system has halted. - * - * NOTE: That LED0 is not used after completion of booting and may - * be used by other board-specific logic. */ /* Button definitions ***************************************************************/ diff --git a/configs/xmc4500-relax/src/xmc4_autoleds.c b/configs/xmc4500-relax/src/xmc4_autoleds.c index 694007c5e5e..69eda6dee93 100644 --- a/configs/xmc4500-relax/src/xmc4_autoleds.c +++ b/configs/xmc4500-relax/src/xmc4_autoleds.c @@ -43,19 +43,19 @@ * include/board.h and src/sam_autoleds.c. The LEDs are used to encode * OS-related events as follows: * - * SYMBOL Meaning LED state - * LED2 LED1 - * --------------------- -------------------------- ------ ------ */ - -#define LED_STARTED 0 /* NuttX has been started OFF OFF */ -#define LED_HEAPALLOCATE 0 /* Heap has been allocated OFF OFF */ -#define LED_IRQSENABLED 0 /* Interrupts enabled OFF OFF */ -#define LED_STACKCREATED 1 /* Idle stack created ON OFF */ -#define LED_INIRQ 2 /* In an interrupt No change */ -#define LED_SIGNAL 2 /* In a signal handler No change */ -#define LED_ASSERTION 2 /* An assertion failed No change */ -#define LED_PANIC 3 /* The system has crashed N/C Blinking */ -#undef LED_IDLE /* MCU is is sleep mode Not used */ + * SYMBOL Meaning LED state + * LED1 LED2 + * ------------------ ------------------------ ------ ------ + * LED_STARTED NuttX has been started OFF OFF + * LED_HEAPALLOCATE Heap has been allocated OFF OFF + * LED_IRQSENABLED Interrupts enabled OFF OFF + * LED_STACKCREATED Idle stack created ON OFF + * LED_INIRQ In an interrupt No change + * LED_SIGNAL In a signal handler No change + * LED_ASSERTION An assertion failed No change + * LED_PANIC The system has crashed N/C Blinking + * LED_IDLE MCU is is sleep mode Not used + */ /**************************************************************************** * Included Files From 21a626878a75f2fd2915ec2bb882443e35485fb7 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 21 Mar 2017 10:55:52 -0600 Subject: [PATCH 68/81] XMC4xxx: Clean up problems associated with USIC initialization. USIC still does not work in UART mode. --- arch/arm/src/xmc4/xmc4_clockutils.c | 7 ++++--- arch/arm/src/xmc4/xmc4_gpio.c | 15 ++++++++++----- arch/arm/src/xmc4/xmc4_usic.c | 18 +++++++++--------- configs/xmc4500-relax/README.txt | 4 +++- 4 files changed, 26 insertions(+), 18 deletions(-) diff --git a/arch/arm/src/xmc4/xmc4_clockutils.c b/arch/arm/src/xmc4/xmc4_clockutils.c index 4d334eaef53..2a391ca3861 100644 --- a/arch/arm/src/xmc4/xmc4_clockutils.c +++ b/arch/arm/src/xmc4/xmc4_clockutils.c @@ -161,6 +161,7 @@ uint32_t xmc4_get_coreclock(void) uint32_t xmc4_get_periphclock(void) { uint32_t periphclock; + uint32_t regval; /* Get the CPU clock frequency. Unless it is divided down, this also the * peripheral clock frequency. @@ -170,12 +171,12 @@ uint32_t xmc4_get_periphclock(void) /* Get the peripheral clock divider */ - periphclock = getreg32(XMC4_SCU_PBCLKCR); - if ((periphclock & SCU_PBCLKCR_PBDIV) != 0) + regval = getreg32(XMC4_SCU_PBCLKCR); + if ((regval & SCU_PBCLKCR_PBDIV) != 0) { /* The peripheral clock is fCPU/2 */ - periphclock <<= 1; + periphclock >>= 1; } return periphclock; diff --git a/arch/arm/src/xmc4/xmc4_gpio.c b/arch/arm/src/xmc4/xmc4_gpio.c index e26967f06f3..b104def53c3 100644 --- a/arch/arm/src/xmc4/xmc4_gpio.c +++ b/arch/arm/src/xmc4/xmc4_gpio.c @@ -234,7 +234,7 @@ static inline void xmc4_gpio_hwsel(uintptr_t portbase, unsigned int pin, ****************************************************************************/ static inline void xmc4_gpio_pdisc(uintptr_t portbase, unsigned int pin, - bool value) + bool enable) { uint32_t regval; uint32_t mask; @@ -243,16 +243,21 @@ static inline void xmc4_gpio_pdisc(uintptr_t portbase, unsigned int pin, regval = xmc4_gpio_getreg(portbase, XMC4_PORT_PDISC_OFFSET); - /* Set/clear the enable/disable (or analg) value for this field */ + /* Set or clear the pin field in the PDISC register. + * + * Disable = set + * Analog = set + * Enable = clear + */ mask = PORT_PIN(pin); - if (value) + if (enable) { - regval |= mask; + regval &= ~mask; } else { - regval &= ~mask; + regval |= mask; } xmc4_gpio_putreg(portbase, XMC4_PORT_PDISC_OFFSET, regval); diff --git a/arch/arm/src/xmc4/xmc4_usic.c b/arch/arm/src/xmc4/xmc4_usic.c index dd69cf318dd..1b82b9e16d5 100644 --- a/arch/arm/src/xmc4/xmc4_usic.c +++ b/arch/arm/src/xmc4/xmc4_usic.c @@ -121,12 +121,12 @@ int xmc4_enable_usic(enum usic_e usic) putreg32(SCU_CGAT0_USIC0, XMC4_SCU_CGATCLR0); - /* De-assert peripheral reset USIC0 */ + /* Set bit in PRCLR0 to de-assert USIC0 peripheral reset */ putreg32(SCU_PR0_USIC0RS, XMC4_SCU_PRCLR0); } #else - /* De-assert peripheral reset USIC0 */ + /* Set bit in PRCLR0 to de-assert USIC0 peripheral reset */ putreg32(SCU_PR0_USIC0RS, XMC4_SCU_PRCLR0); #endif @@ -143,12 +143,12 @@ int xmc4_enable_usic(enum usic_e usic) putreg32(SCU_CGAT1_USIC1, XMC4_SCU_CGATCLR1); - /* De-assert peripheral reset USIC1 */ + /* Set bit in PRCLR1 to de-assert USIC1 peripheral reset */ putreg32(SCU_PR1_USIC1RS, XMC4_SCU_PRCLR1); } #else - /* De-assert peripheral reset USIC1 */ + /* Set bit in PRCLR1 to de-assert USIC1 peripheral reset */ putreg32(SCU_PR1_USIC1RS, XMC4_SCU_PRCLR1); #endif @@ -165,12 +165,12 @@ int xmc4_enable_usic(enum usic_e usic) putreg32(SCU_CGAT1_USIC2, XMC4_SCU_CGATCLR1); - /* De-assert peripheral reset USIC2 */ + /* Set bit in PRCLR1 to de-assert USIC2 peripheral reset */ putreg32(SCU_PR1_USIC2RS, XMC4_SCU_PRCLR1); } #else - /* De-assert peripheral reset USIC2 */ + /* Set bit in PRCLR1 to de-assert USIC2 peripheral reset */ putreg32(SCU_PR1_USIC2RS, XMC4_SCU_PRCLR1); #endif @@ -203,7 +203,7 @@ int xmc4_disable_usic(enum usic_e usic) switch (usic) { case USIC0: - /* Assert peripheral reset USIC0 */ + /* Set bit in PRSET0 to assert USIC0 peripheral reset */ putreg32(SCU_PR0_USIC0RS, XMC4_SCU_PRSET0); @@ -216,7 +216,7 @@ int xmc4_disable_usic(enum usic_e usic) #if XMC4_NUSIC > 1 case USIC1: - /* Assert peripheral reset USIC0 */ + /* Set bit in PRSET1 to assert USIC1 peripheral reset */ putreg32(SCU_PR1_USIC1RS, XMC4_SCU_PRSET1); @@ -229,7 +229,7 @@ int xmc4_disable_usic(enum usic_e usic) #if XMC4_NUSIC > 2 case USIC2: - /* Assert peripheral reset USIC0 */ + /* Set bit in PRSET1 to assert USIC2 peripheral reset */ putreg32(SCU_PR1_USIC2RS, XMC4_SCU_PRSET1); diff --git a/configs/xmc4500-relax/README.txt b/configs/xmc4500-relax/README.txt index 0ee63341d44..c6d014b6665 100644 --- a/configs/xmc4500-relax/README.txt +++ b/configs/xmc4500-relax/README.txt @@ -14,11 +14,13 @@ Serial Console The RX and TX pins is available: RX - P1.4, Connector X2, pin 17 - TX - P1.5, Connector X2, pin 17 + TX - P1.5, Connector X2, pin 16 GND - Available on pins 1-4 of either connector X1 or X2 VDD3.3 - Available on pins 37-38 of either connector X1 or X2 VDD5 - Available on pins 39-40 of either connector X1 or X2 + A TTL to RS-232 convertor or a USB TTL-to-USB serial adaptor is required. + LEDs ==== From 602bdd13fb6b7981fa587a409fef791f4b9de338 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 21 Mar 2017 11:24:04 -0600 Subject: [PATCH 69/81] XMC4xxx: Fix a pin configuration problem. Fix some mispellings. --- arch/arm/src/xmc4/chip/xmc4_ports.h | 22 +++++++++++----------- arch/arm/src/xmc4/xmc4_gpio.c | 18 +++++++++--------- arch/arm/src/xmc4/xmc4_lowputc.c | 2 +- arch/arm/src/xmc4/xmc4_usic.c | 4 ++-- arch/arm/src/xmc4/xmc4_usic.h | 4 ++-- 5 files changed, 25 insertions(+), 25 deletions(-) diff --git a/arch/arm/src/xmc4/chip/xmc4_ports.h b/arch/arm/src/xmc4/chip/xmc4_ports.h index d42665b908c..a769ddf73c9 100644 --- a/arch/arm/src/xmc4/chip/xmc4_ports.h +++ b/arch/arm/src/xmc4/chip/xmc4_ports.h @@ -79,7 +79,7 @@ #define XMC4_PORT_IN_OFFSET 0x0024 /* Port Input Register */ -#define XMC4_PORT_PDR_OFFSET(n) (0x0010 + (((n) >> 1) & ~3)) +#define XMC4_PORT_PDR_OFFSET(n) (0x0040 + (((n) >> 1) & ~3)) #define XMC4_PORT_PDR0_OFFSET 0x0040 /* Port Pad Driver Mode 0 Register */ #define XMC4_PORT_PDR1_OFFSET 0x0044 /* Port Pad Driver Mode 1 Register */ @@ -399,19 +399,19 @@ #define PORT_PDR0_PD2_SHIFT (8) /* Bit 8-10: Pad Driver Mode for Port n Pin 2 */ #define PORT_PDR0_PD2_MASK (7 << PORT_PDR0_PD2_SHIFT) # define PORT_PDR0_PD2(n) ((uint32_t)(n) << PORT_PDR0_PD2_SHIFT) -#define PORT_PDR0_PD3_SHIFT (12) /* Bit 12-14: Pad Driver Mode for Port 0 Pin 3 */ +#define PORT_PDR0_PD3_SHIFT (12) /* Bit 12-14: Pad Driver Mode for Port n Pin 3 */ #define PORT_PDR0_PD3_MASK (7 << PORT_PDR0_PD3_SHIFT) # define PORT_PDR0_PD3(n) ((uint32_t)(n) << PORT_PDR0_PD3_SHIFT) -#define PORT_PDR0_PD4_SHIFT (16) /* Bit 16-18: Pad Driver Mode for Port 0 Pin 4 */ +#define PORT_PDR0_PD4_SHIFT (16) /* Bit 16-18: Pad Driver Mode for Port n Pin 4 */ #define PORT_PDR0_PD4_MASK (7 << PORT_PDR0_PD4_SHIFT) # define PORT_PDR0_PD4(n) ((uint32_t)(n) << PORT_PDR0_PD4_SHIFT) -#define PORT_PDR0_PD5_SHIFT (20) /* Bit 20-22: Pad Driver Mode for Port 0 Pin 5 */ +#define PORT_PDR0_PD5_SHIFT (20) /* Bit 20-22: Pad Driver Mode for Port n Pin 5 */ #define PORT_PDR0_PD5_MASK (7 << PORT_PDR0_PD5_SHIFT) # define PORT_PDR0_PD5(n) ((uint32_t)(n) << PORT_PDR0_PD5_SHIFT) -#define PORT_PDR0_PD6_SHIFT (24) /* Bit 24-26: Pad Driver Mode for Port 0 Pin 6 */ +#define PORT_PDR0_PD6_SHIFT (24) /* Bit 24-26: Pad Driver Mode for Port n Pin 6 */ #define PORT_PDR0_PD6_MASK (7 << PORT_PDR0_PD6_SHIFT) # define PORT_PDR0_PD6(n) ((uint32_t)(n) << PORT_PDR0_PD6_SHIFT) -#define PORT_PDR0_PD7_SHIFT (28) /* Bit 28-30: Pad Driver Mode for Port 0 Pin 7 */ +#define PORT_PDR0_PD7_SHIFT (28) /* Bit 28-30: Pad Driver Mode for Port n Pin 7 */ #define PORT_PDR0_PD7_MASK (7 << PORT_PDR0_PD7_SHIFT) # define PORT_PDR0_PD7(n) ((uint32_t)(n) << PORT_PDR0_PD7_SHIFT) @@ -429,19 +429,19 @@ #define PORT_PDR1_PD10_SHIFT (8) /* Bit 8-10: Pad Driver Mode for Port n Pin 10 */ #define PORT_PDR1_PD10_MASK (7 << PORT_PDR1_PD10_SHIFT) # define PORT_PDR1_PD10(n) ((uint32_t)(n) << PORT_PDR1_PD10_SHIFT) -#define PORT_PDR1_PD11_SHIFT (12) /* Bit 12-14: Pad Driver Mode for Port 0 Pin 11 */ +#define PORT_PDR1_PD11_SHIFT (12) /* Bit 12-14: Pad Driver Mode for Port n Pin 11 */ #define PORT_PDR1_PD11_MASK (7 << PORT_PDR1_PD11_SHIFT) # define PORT_PDR1_PD11(n) ((uint32_t)(n) << PORT_PDR1_PD11_SHIFT) -#define PORT_PDR1_PD12_SHIFT (16) /* Bit 16-18: Pad Driver Mode for Port 0 Pin 12 */ +#define PORT_PDR1_PD12_SHIFT (16) /* Bit 16-18: Pad Driver Mode for Port n Pin 12 */ #define PORT_PDR1_PD12_MASK (7 << PORT_PDR1_PD12_SHIFT) # define PORT_PDR1_PD12(n) ((uint32_t)(n) << PORT_PDR1_PD12_SHIFT) -#define PORT_PDR1_PD13_SHIFT (20) /* Bit 20-22: Pad Driver Mode for Port 0 Pin 13 */ +#define PORT_PDR1_PD13_SHIFT (20) /* Bit 20-22: Pad Driver Mode for Port n Pin 13 */ #define PORT_PDR1_PD13_MASK (7 << PORT_PDR1_PD13_SHIFT) # define PORT_PDR1_PD13(n) ((uint32_t)(n) << PORT_PDR1_PD13_SHIFT) -#define PORT_PDR1_PD14_SHIFT (24) /* Bit 24-26: Pad Driver Mode for Port 0 Pin 14 */ +#define PORT_PDR1_PD14_SHIFT (24) /* Bit 24-26: Pad Driver Mode for Port n Pin 14 */ #define PORT_PDR1_PD14_MASK (7 << PORT_PDR1_PD14_SHIFT) # define PORT_PDR1_PD14(n) ((uint32_t)(n) << PORT_PDR1_PD14_SHIFT) -#define PORT_PDR1_PD15_SHIFT (28) /* Bit 28-30: Pad Driver Mode for Port 0 Pin 15 */ +#define PORT_PDR1_PD15_SHIFT (28) /* Bit 28-30: Pad Driver Mode for Port n Pin 15 */ #define PORT_PDR1_PD15_MASK (7 << PORT_PDR1_PD15_SHIFT) # define PORT_PDR1_PD15(n) ((uint32_t)(n) << PORT_PDR1_PD15_SHIFT) diff --git a/arch/arm/src/xmc4/xmc4_gpio.c b/arch/arm/src/xmc4/xmc4_gpio.c index b104def53c3..d88e73c7adc 100644 --- a/arch/arm/src/xmc4/xmc4_gpio.c +++ b/arch/arm/src/xmc4/xmc4_gpio.c @@ -247,7 +247,7 @@ static inline void xmc4_gpio_pdisc(uintptr_t portbase, unsigned int pin, * * Disable = set * Analog = set - * Enable = clear + * Enable = clear */ mask = PORT_PIN(pin); @@ -272,7 +272,7 @@ static inline void xmc4_gpio_pdisc(uintptr_t portbase, unsigned int pin, ****************************************************************************/ static inline void xmc4_gpio_pps(uintptr_t portbase, unsigned int pin, - bool value) + bool powersave) { uint32_t regval; uint32_t mask; @@ -281,10 +281,10 @@ static inline void xmc4_gpio_pps(uintptr_t portbase, unsigned int pin, regval = xmc4_gpio_getreg(portbase, XMC4_PORT_PPS_OFFSET); - /* Set/clear the enable/disable (or analg) value for this field */ + /* Set/clear the enable/disable power save value for this field */ mask = PORT_PIN(pin); - if (value) + if (powersave) { regval |= mask; } @@ -312,7 +312,7 @@ static void xmc4_gpio_pdr(uintptr_t portbase, unsigned int pin, unsigned int offset; unsigned int shift; - /* Read the PDRregister */ + /* Read the PDR register */ offset = XMC4_PORT_PDR_OFFSET(pin); regval = xmc4_gpio_getreg(portbase, offset); @@ -417,18 +417,18 @@ int xmc4_gpio_config(gpioconfig_t pinconfig) value = xmc4_gpio_pinctrl(pinconfig); xmc4_gpio_hwsel(portbase, pin, value); - /* Select drive strength */ + /* Select drive strength (PDR) */ value = xmc4_gpio_padtype(pinconfig); xmc4_gpio_pdr(portbase, pin, value); /* Enable/enable pad or Analog only (PDISC) */ - xmc4_gpio_pdisc(portbase, pin, ((pinconfig & GPIO_PAD_DISABLE) != 0)); + xmc4_gpio_pdisc(portbase, pin, ((pinconfig & GPIO_PAD_DISABLE) == 0)); - /* Make sure pin is not in power save mode (PDR) */ + /* Make sure pin is not in power save mode (PPS) */ - xmc4_gpio_pdisc(portbase, pin, false); + xmc4_gpio_pps(portbase, pin, false); leave_critical_section(flags); return OK; diff --git a/arch/arm/src/xmc4/xmc4_lowputc.c b/arch/arm/src/xmc4/xmc4_lowputc.c index fcb930d1b90..c1416194fc3 100644 --- a/arch/arm/src/xmc4/xmc4_lowputc.c +++ b/arch/arm/src/xmc4/xmc4_lowputc.c @@ -275,7 +275,7 @@ int xmc4_uart_configure(enum usic_channel_e channel, * the config structure. */ - ret = xmc4_uisc_baudrate(channel, config->baud, UART_OVERSAMPLING); + ret = xmc4_usic_baudrate(channel, config->baud, UART_OVERSAMPLING); /* Configure frame format. * diff --git a/arch/arm/src/xmc4/xmc4_usic.c b/arch/arm/src/xmc4/xmc4_usic.c index 1b82b9e16d5..e22434a637f 100644 --- a/arch/arm/src/xmc4/xmc4_usic.c +++ b/arch/arm/src/xmc4/xmc4_usic.c @@ -385,7 +385,7 @@ int xmc4_disable_usic_channel(enum usic_channel_e channel) } /**************************************************************************** - * Name: xmc4_uisc_baudrate + * Name: xmc4_usic_baudrate * * Description: * Set the USIC baudrate for the USIC channel @@ -396,7 +396,7 @@ int xmc4_disable_usic_channel(enum usic_channel_e channel) * ****************************************************************************/ -int xmc4_uisc_baudrate(enum usic_channel_e channel, uint32_t baud, +int xmc4_usic_baudrate(enum usic_channel_e channel, uint32_t baud, uint32_t oversampling) { uintptr_t base; diff --git a/arch/arm/src/xmc4/xmc4_usic.h b/arch/arm/src/xmc4/xmc4_usic.h index 910846bc85e..291fb81fb01 100644 --- a/arch/arm/src/xmc4/xmc4_usic.h +++ b/arch/arm/src/xmc4/xmc4_usic.h @@ -177,7 +177,7 @@ int xmc4_enable_usic_channel(enum usic_channel_e channel); int xmc4_disable_usic_channel(enum usic_channel_e channel); /**************************************************************************** - * Name: xmc4_uisc_baudrate + * Name: xmc4_usic_baudrate * * Description: * Set the USIC baudrate for the USIC channel @@ -188,7 +188,7 @@ int xmc4_disable_usic_channel(enum usic_channel_e channel); * ****************************************************************************/ -int xmc4_uisc_baudrate(enum usic_channel_e channel, uint32_t baud, +int xmc4_usic_baudrate(enum usic_channel_e channel, uint32_t baud, uint32_t oversampling); #endif /* __ARCH_ARM_SRC_XMC4_XMC4_USIC_H */ From d76157db7bd22595be5bdb5822031d68106806bf Mon Sep 17 00:00:00 2001 From: David Sidrane Date: Tue, 21 Mar 2017 08:03:06 -1000 Subject: [PATCH 70/81] sem_holder:Clean up from Review Spelling and backward DEBUGASSERT along with one gem if (sem->holder[0].htcb != NULL || sem->holder[**1**].htcb != NULL) --- sched/semaphore/sem_holder.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/sched/semaphore/sem_holder.c b/sched/semaphore/sem_holder.c index bc5c186e6bf..7b4e3e3dd16 100644 --- a/sched/semaphore/sem_holder.c +++ b/sched/semaphore/sem_holder.c @@ -156,7 +156,7 @@ static FAR struct semholder_s *sem_findholder(sem_t *sem, int i; pholder = NULL; - /* We have two hard-allocated holder structuse in sem_t */ + /* We have two hard-allocated holder structures in sem_t */ for (i = 0; i < 2; i++) { @@ -338,7 +338,7 @@ static int sem_boostholderprio(FAR struct semholder_s *pholder, if (!sched_verifytcb(htcb)) { serr("ERROR: TCB 0x%08x is a stale handle, counts lost\n", htcb); - DEBUGASSERT(!sched_verifytcb(htcb)); + DEBUGASSERT(sched_verifytcb(htcb)); sem_freeholder(sem, pholder); } @@ -498,7 +498,7 @@ static int sem_restoreholderprio(FAR struct tcb_s *htcb, if (!sched_verifytcb(htcb)) { serr("ERROR: TCB 0x%08x is a stale handle, counts lost\n", htcb); - DEBUGASSERT(!sched_verifytcb(htcb)); + DEBUGASSERT(sched_verifytcb(htcb)); pholder = sem_findholder(sem, htcb); if (pholder != NULL) { @@ -905,13 +905,13 @@ void sem_destroyholder(FAR sem_t *sem) if (sem->hhead != NULL) { serr("ERROR: Semaphore destroyed with holders\n"); - DEBUGASSERT(sem->hhead != NULL); + DEBUGASSERT(sem->hhead == NULL); (void)sem_foreachholder(sem, sem_recoverholders, NULL); } #else - if (sem->holder[0].htcb != NULL || sem->holder[0].htcb != NULL) + if (sem->holder[0].htcb != NULL || sem->holder[1].htcb != NULL) { - DEBUGASSERT(sem->holder[0].htcb != NULL || sem->holder[0].htcb != NULL); + DEBUGASSERT(sem->holder[0].htcb == NULL || sem->holder[1].htcb == NULL); serr("ERROR: Semaphore destroyed with holder\n"); } From 248c821730429333cbb37588b5971866dc7805f0 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 21 Mar 2017 12:28:34 -0600 Subject: [PATCH 71/81] Update a README file. --- configs/xmc4500-relax/README.txt | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/configs/xmc4500-relax/README.txt b/configs/xmc4500-relax/README.txt index c6d014b6665..e1fd46fa839 100644 --- a/configs/xmc4500-relax/README.txt +++ b/configs/xmc4500-relax/README.txt @@ -7,6 +7,15 @@ README for the XMC4500 Relax The current configurations support only the Lite version of the board. +Status +====== + + 2017-03-21: The XMC4500 Relax boots into NSH, provides the NSH prompt, + and the LEDs are working. But there is a problem with the USIC baud + (probably); I get garbage on the serial console. This probably means + that either the peripheral clocking is wrong or the baud configuration + is wrong. + Serial Console ============== @@ -20,6 +29,9 @@ Serial Console VDD5 - Available on pins 39-40 of either connector X1 or X2 A TTL to RS-232 convertor or a USB TTL-to-USB serial adaptor is required. + The notion of what is TX and what is RX depends on your point of view. + With the TTL to RS-232 converter, I connect pin 17 to the pin labeled + TX on the converter and pin 16 to the RX pin on the converter. LEDs ==== From e8e3c2f362e228f162cb939c62361ac5b6d769b3 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 21 Mar 2017 13:34:17 -0600 Subject: [PATCH 72/81] sched/semaphore: Convert strange use of DEBUGASSERT to DEBUGPANIC. --- sched/semaphore/sem_holder.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/sched/semaphore/sem_holder.c b/sched/semaphore/sem_holder.c index 7b4e3e3dd16..a9159c1537e 100644 --- a/sched/semaphore/sem_holder.c +++ b/sched/semaphore/sem_holder.c @@ -338,7 +338,7 @@ static int sem_boostholderprio(FAR struct semholder_s *pholder, if (!sched_verifytcb(htcb)) { serr("ERROR: TCB 0x%08x is a stale handle, counts lost\n", htcb); - DEBUGASSERT(sched_verifytcb(htcb)); + DEBUGPANIC(); sem_freeholder(sem, pholder); } @@ -498,7 +498,7 @@ static int sem_restoreholderprio(FAR struct tcb_s *htcb, if (!sched_verifytcb(htcb)) { serr("ERROR: TCB 0x%08x is a stale handle, counts lost\n", htcb); - DEBUGASSERT(sched_verifytcb(htcb)); + DEBUGPANIC(); pholder = sem_findholder(sem, htcb); if (pholder != NULL) { @@ -905,14 +905,14 @@ void sem_destroyholder(FAR sem_t *sem) if (sem->hhead != NULL) { serr("ERROR: Semaphore destroyed with holders\n"); - DEBUGASSERT(sem->hhead == NULL); + DEBUGPANIC(); (void)sem_foreachholder(sem, sem_recoverholders, NULL); } #else if (sem->holder[0].htcb != NULL || sem->holder[1].htcb != NULL) { - DEBUGASSERT(sem->holder[0].htcb == NULL || sem->holder[1].htcb == NULL); serr("ERROR: Semaphore destroyed with holder\n"); + DEBUGPANIC(); } sem->holder[0].htcb = NULL; From 6893843cc516bd211b4da257a2d86e831024ee56 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 21 Mar 2017 13:47:56 -0600 Subject: [PATCH 73/81] sched/semaphore: Fix a warning aout an unused variable when priority inheritance is enabled. --- sched/semaphore/sem_holder.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/sched/semaphore/sem_holder.c b/sched/semaphore/sem_holder.c index a9159c1537e..a46cf3a8be4 100644 --- a/sched/semaphore/sem_holder.c +++ b/sched/semaphore/sem_holder.c @@ -787,7 +787,6 @@ static inline void sem_restorebaseprio_task(FAR struct tcb_s *stcb, FAR sem_t *sem) { FAR struct tcb_s *rtcb = this_task(); - FAR struct semholder_s *pholder; /* Perform the following actions only if a new thread was given a count. * The thread that received the count should be the highest priority @@ -831,7 +830,6 @@ static inline void sem_restorebaseprio_task(FAR struct tcb_s *stcb, */ sem_findandfreeholder(sem, rtcb); - } /**************************************************************************** @@ -908,6 +906,7 @@ void sem_destroyholder(FAR sem_t *sem) DEBUGPANIC(); (void)sem_foreachholder(sem, sem_recoverholders, NULL); } + #else if (sem->holder[0].htcb != NULL || sem->holder[1].htcb != NULL) { From 343f7ceab24c9551717c4a151356756c11c65b8b Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 21 Mar 2017 15:05:17 -0600 Subject: [PATCH 74/81] XMC4xxx: Misc clock clean-up; PBDIV should be controllable from board.h --- arch/arm/src/xmc4/xmc4_clockconfig.c | 9 +++++++-- arch/arm/src/xmc4/xmc4_usic.c | 4 ++-- configs/xmc4500-relax/include/board.h | 21 +++++++++++++-------- 3 files changed, 22 insertions(+), 12 deletions(-) diff --git a/arch/arm/src/xmc4/xmc4_clockconfig.c b/arch/arm/src/xmc4/xmc4_clockconfig.c index a28cf7fd51f..519276f2cdc 100644 --- a/arch/arm/src/xmc4/xmc4_clockconfig.c +++ b/arch/arm/src/xmc4/xmc4_clockconfig.c @@ -105,13 +105,18 @@ #define CLKSET_VALUE (0x00000000) #define SYSCLKCR_VALUE (0x00010001) #define CPUCLKCR_VALUE (0x00000000) -#define PBCLKCR_VALUE (0x00000000) #define CCUCLKCR_VALUE (0x00000000) #define WDTCLKCR_VALUE (0x00000000) #define EBUCLKCR_VALUE (0x00000003) #define USBCLKCR_VALUE (0x00010000) #define EXTCLKCR_VALUE (0x01200003) +#if BOARD_PBDIV == 1 +# define PBCLKCR_VALUE SCU_PBCLKCR_PBDIV_FCPU +#else /* BOARD_PBDIV == 2 */ +# define PBCLKCR_VALUE SCU_PBCLKCR_PBDIV_DIV2 +#endif + #if ((USBCLKCR_VALUE & SCU_USBCLKCR_USBSEL) == SCU_USBCLKCR_USBSEL_USBPLL) # define USB_DIV 3 #else @@ -387,7 +392,7 @@ void xmc4_clock_configure(void) /* Before scaling to final frequency we need to setup the clock dividers */ putreg32(SYSCLKCR_VALUE, XMC4_SCU_SYSCLKCR); - putreg32(PBCLKCR_VALUE, XMC4_SCU_PBCLKCR); + putreg32(PBCLKCR_VALUE, XMC4_SCU_PBCLKCR); putreg32(CPUCLKCR_VALUE, XMC4_SCU_CPUCLKCR); putreg32(CCUCLKCR_VALUE, XMC4_SCU_CCUCLKCR); putreg32(WDTCLKCR_VALUE, XMC4_SCU_WDTCLKCR); diff --git a/arch/arm/src/xmc4/xmc4_usic.c b/arch/arm/src/xmc4/xmc4_usic.c index e22434a637f..925c9c0f411 100644 --- a/arch/arm/src/xmc4/xmc4_usic.c +++ b/arch/arm/src/xmc4/xmc4_usic.c @@ -448,14 +448,14 @@ int xmc4_usic_baudrate(enum usic_channel_e channel, uint32_t baud, /* Select and setup the fractional divider */ - regval = USIC_FDR_DM_FRACTIONAL | (clkdiv_min << USIC_FDR_STEP_SHIFT); + regval = USIC_FDR_DM_FRACTIONAL | USIC_FDR_STEP(clkdiv_min); putreg32(regval, base + XMC4_USIC_FDR_OFFSET); /* Setup and enable the baud rate generator */ regval = getreg32(base + XMC4_USIC_BRG_OFFSET); regval &= ~(USIC_BRG_DCTQ_MASK | USIC_BRG_PDIV_MASK | USIC_BRG_PCTQ_MASK | USIC_BRG_PPPEN); - regval |= (USIC_BRG_DCTQ(oversampling - 1) | USIC_BRG_PDIV(pdiv_int_min - 1)); + regval |= (USIC_BRG_DCTQ(oversampling - 1) | USIC_BRG_PDIV(pdiv_int_min - 1)); putreg32(regval, base + XMC4_USIC_BRG_OFFSET); ret = OK; diff --git a/configs/xmc4500-relax/include/board.h b/configs/xmc4500-relax/include/board.h index 9c3121a4b63..f45120a0f25 100644 --- a/configs/xmc4500-relax/include/board.h +++ b/configs/xmc4500-relax/include/board.h @@ -53,10 +53,10 @@ /* Clocking *************************************************************************/ /* Default clock initialization - * fPLL = 288MHz => fSYS = 288MHz => fCPU = 144MHz - * => fPB = 144MHz - * => fCCU = 144MHz - * => fETH = 72MHz + * fPLL = 288MHz => fSYS = 288MHz => fCPU = 144MHz + * => fPERIPH = 144MHz + * => fCCU = 144MHz + * => fETH = 72MHz * => fUSB = 48MHz * => fEBU = 72MHz * @@ -79,7 +79,7 @@ /* Select the external crystal as the PLL clock source */ #define BOARD_PLL_CLOCKSRC_XTAL 1 /* PLL Clock source == extnernal crystal */ -#undef BOARD_PLL_CLOCKSRC_OFI /* PLL Clock source != internal fast oscillator */ +#undef BOARD_PLL_CLOCKSRC_OFI /* PLL Clock source != internal fast oscillator */ /* PLL Configuration: * @@ -95,16 +95,21 @@ #define BOARD_PLL_K2DIV 1 #define BOARD_PLL_FREQUENCY 288000000 -/* System frequency is divided down from PLL output */ +/* System frequency, fSYS, is divided down from PLL output */ #define BOARD_SYSDIV 1 /* PLL Output divider to get fSYS */ #define BOARD_SYS_FREQUENCY 288000000 -/* CPU frequency may be divided down from system frequency */ +/* CPU frequency, fCPU, may be divided down from system frequency */ #define BOARD_CPUDIV_ENABLE 1 /* Enable PLL dive by 2 for fCPU */ #define BOARD_CPU_FREQUENCY 144000000 +/* The peripheral clock, fPERIPH, derives from fCPU with no division */ + +#define BOARD_PBDIV 1 /* No division */ +#define BOARD_PERIPH_FREQUENCY 144000000 + /* Standby clock source selection * * BOARD_STDBY_CLOCKSRC_OSI - Internal 32.768KHz slow oscillator @@ -112,7 +117,7 @@ */ #define BOARD_STDBY_CLOCKSRC_OSI 1 -#undef BOARD_STDBY_CLOCKSRC_OSCULP +#undef BOARD_STDBY_CLOCKSRC_OSCULP #define BOARD_STDBY_FREQUENCY 32768 /* USB PLL settings. From 9919e33705c6912f3ab482cf383db5fbeee4c671 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 21 Mar 2017 15:31:53 -0600 Subject: [PATCH 75/81] Trivial changes to comments. --- configs/xmc4500-relax/include/board.h | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/configs/xmc4500-relax/include/board.h b/configs/xmc4500-relax/include/board.h index f45120a0f25..751e8031703 100644 --- a/configs/xmc4500-relax/include/board.h +++ b/configs/xmc4500-relax/include/board.h @@ -53,16 +53,21 @@ /* Clocking *************************************************************************/ /* Default clock initialization - * fPLL = 288MHz => fSYS = 288MHz => fCPU = 144MHz - * => fPERIPH = 144MHz - * => fCCU = 144MHz - * => fETH = 72MHz - * => fUSB = 48MHz - * => fEBU = 72MHz + * + * fXTAL = 12Mhz + * -> fPLL = (fXTAL / (2 * 1) * 48) = 288MHz + * -> fSYS = (fPLL / 1) = 288MHz + * -> fCPU = (fSYS / 2) = 144MHz + * -> fPERIPH = (fCPU / 1) = 144MHz + * -> fCCU = (fSYS / 2) = 144MHz + * -> fETH = 72MHz (REVISIT) + * -> fUSB = 48MHz (REVISIT) + * -> fEBU = 72MHz (REVISIT) * * fUSBPLL Disabled, only enabled if SCU_CLK_USBCLKCR_USBSEL_USBPLL is selected * - * fOFI = 24MHz => fWDT = 24MHz + * fOFI = 24MHz + * -> fWDT = 24MHz (REVISIT) */ #undef BOARD_FOFI_CALIBRATION /* Enable factory calibration */ From 82a5dfddb4a4bab6211f142857b87cdb3375ac32 Mon Sep 17 00:00:00 2001 From: rg Date: Tue, 21 Mar 2017 16:44:11 -0600 Subject: [PATCH 76/81] The attached .patch implements DMA support for the stm32f4 I2C. Max and I have verified that it works on our systems. --- arch/arm/src/stm32/Kconfig | 10 + arch/arm/src/stm32/stm32f40xxx_i2c.c | 347 +++++++++++++++++++++++++-- 2 files changed, 332 insertions(+), 25 deletions(-) diff --git a/arch/arm/src/stm32/Kconfig b/arch/arm/src/stm32/Kconfig index 8dea045fda5..de2c8fe23be 100644 --- a/arch/arm/src/stm32/Kconfig +++ b/arch/arm/src/stm32/Kconfig @@ -6190,6 +6190,16 @@ config STM32_I2C_DUTY16_9 default n depends on STM32_I2C +config STM32_I2C_DMA + bool "I2C DMA Support" + default n + depends on STM32_I2C && STM32_STM32F40XX && STM32_DMA1 + ---help--- + This option enables the DMA for I2C transfers. + Note: The user can define CONFIG_I2C_DMAPRIO: a custom priority value for the + I2C dma streams, else the default priority level is set to medium. + Note: This option is compatible with CONFIG_I2C_POLLED. + endmenu menu "SDIO Configuration" diff --git a/arch/arm/src/stm32/stm32f40xxx_i2c.c b/arch/arm/src/stm32/stm32f40xxx_i2c.c index c0d1a2d6fd0..3d7d5567f89 100644 --- a/arch/arm/src/stm32/stm32f40xxx_i2c.c +++ b/arch/arm/src/stm32/stm32f40xxx_i2c.c @@ -63,7 +63,6 @@ * - 1 x 10 bit addresses + 1 x 7 bit address (?) * - plus the broadcast address (general call) * - Multi-master support - * - DMA (to get rid of too many CPU wake-ups and interventions) * - Be ready for IPMI */ @@ -95,6 +94,7 @@ #include "stm32_rcc.h" #include "stm32_i2c.h" #include "stm32_waste.h" +#include "stm32_dma.h" /* At least one I2C peripheral must be enabled */ @@ -162,6 +162,21 @@ #define MKI2C_OUTPUT(p) (((p) & (GPIO_PORT_MASK | GPIO_PIN_MASK)) | I2C_OUTPUT) +/* I2C DMA priority */ + +#ifdef CONFIG_STM32_I2C_DMA + +# if defined(CONFIG_I2C_DMAPRIO) +# if (CONFIG_I2C_DMAPRIO & ~DMA_SCR_PL_MASK) != 0 +# error "Illegal value for CONFIG_I2C_DMAPRIO" +# endif +# define I2C_DMA_PRIO CONFIG_I2C_DMAPRIO +# else +# define I2C_DMA_PRIO DMA_SCR_PRIMED +# endif + +#endif + /* Debug ****************************************************************************/ /* I2C event trace logic. NOTE: trace uses the internal, non-standard, low-level @@ -253,7 +268,7 @@ struct stm32_i2c_priv_s struct i2c_msg_s *msgv; /* Message list */ uint8_t *ptr; /* Current message buffer */ uint32_t frequency; /* Current I2C frequency */ - int dcnt; /* Current message length */ + volatile int dcnt; /* Current message length */ uint16_t flags; /* Current message flags */ bool check_addr_ACK; /* Flag to signal if on next interrupt address has ACKed */ uint8_t total_msg_len; /* Flag to signal a short read sequence */ @@ -270,6 +285,15 @@ struct stm32_i2c_priv_s #endif uint32_t status; /* End of transfer SR2|SR1 status */ + + /* I2C DMA support */ + +#ifdef CONFIG_STM32_I2C_DMA + DMA_HANDLE txdma; /* TX DMA handle */ + DMA_HANDLE rxdma; /* RX DMA handle */ + uint8_t txch; /* TX DMA channel */ + uint8_t rxch; /* RX DMA channel */ +#endif }; /************************************************************************************ @@ -337,6 +361,13 @@ static int stm32_i2c_transfer(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s static int stm32_i2c_reset(FAR struct i2c_master_s *dev); #endif +/* DMA support */ + +#ifdef CONFIG_STM32_I2C_DMA +static void stm32_i2c_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg); +static void stm32_i2c_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg); +#endif + /************************************************************************************ * Private Data ************************************************************************************/ @@ -398,7 +429,16 @@ static struct stm32_i2c_priv_s stm32_i2c1_priv = .ptr = NULL, .dcnt = 0, .flags = 0, - .status = 0 + .status = 0, +#ifdef CONFIG_STM32_I2C_DMA +# ifndef CONFIG_STM32_DMA1 +# error "I2C1 enabled with DMA but corresponding DMA controller 1 is not enabled!" +# endif + /* TODO: ch for i2c 1 and 2 could be *X_2 based on stream priority */ + + .rxch = DMAMAP_I2C1_RX, + .txch = DMAMAP_I2C1_TX, +#endif }; #endif @@ -428,7 +468,14 @@ static struct stm32_i2c_priv_s stm32_i2c2_priv = .ptr = NULL, .dcnt = 0, .flags = 0, - .status = 0 + .status = 0, +#ifdef CONFIG_STM32_I2C_DMA +# ifndef CONFIG_STM32_DMA1 +# error "I2C2 enabled with DMA but corresponding DMA controller 1 is not enabled!" +# endif + .rxch = DMAMAP_I2C2_RX, + .txch = DMAMAP_I2C2_TX, +#endif }; #endif @@ -458,7 +505,14 @@ static struct stm32_i2c_priv_s stm32_i2c3_priv = .ptr = NULL, .dcnt = 0, .flags = 0, - .status = 0 + .status = 0, +#ifdef CONFIG_STM32_I2C_DMA +# ifndef CONFIG_STM32_DMA1 +# error "I2C3 enabled with DMA but corresponding DMA controller 1 is not enabled!" +# endif + .rxch = DMAMAP_I2C3_RX, + .txch = DMAMAP_I2C3_TX, +#endif }; #endif @@ -521,7 +575,7 @@ static inline void stm32_i2c_sem_wait(FAR struct stm32_i2c_priv_s *priv) { while (sem_wait(&priv->sem_excl) != 0) { - ASSERT(errno == EINTR); + DEBUGASSERT(errno == EINTR); } } @@ -1185,6 +1239,12 @@ static inline void stm32_i2c_enablefsmc(uint32_t ahbenr) static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv) { uint32_t status; +#ifndef CONFIG_I2C_POLLED + uint32_t regval; +#endif +#ifdef CONFIG_STM32_I2C_DMA + uint16_t cr2; +#endif i2cinfo("I2C ISR called\n"); @@ -1228,6 +1288,23 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv) * stm32_i2c_sem_waitdone() waiting process. */ +#ifdef CONFIG_STM32_I2C_DMA + /* If ISR gets called (ex. polling mode) while DMA is still in + * progress, we should just return and let the DMA finish. + */ + + cr2 = stm32_i2c_getreg(priv, STM32_I2C_CR2_OFFSET); + if ((cr2 & I2C_CR2_DMAEN) != 0) + { +#ifdef CONFIG_DEBUG_I2C_INFO + size_t left = stm32_dmaresidual(priv->rxdma); + + i2cinfo("DMA in progress: %ld [bytes] remainining. Returning.\n", left); +#endif + return OK; + } +#endif + if (priv->dcnt == -1 && priv->msgc > 0) { i2cinfo("Switch to new message\n"); @@ -1484,6 +1561,46 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv) /* Trace */ stm32_i2c_traceevent(priv, I2CEVENT_ADDRESS_ACKED, 0); + +#ifdef CONFIG_STM32_I2C_DMA + /* DMA only when not doing a short read */ + + i2cinfo("Starting dma transfer and disabling interrupts\n"); + + /* The DMA must be initialized and enabled before the I2C data transfer. + * The DMAEN bit must be set in the I2C_CR2 register before the ADDR event. + */ + + stm32_dmasetup(priv->rxdma, priv->config->base+STM32_I2C_DR_OFFSET, + (uint32_t) priv->ptr, priv->dcnt, + DMA_SCR_DIR_P2M | + DMA_SCR_MSIZE_8BITS | + DMA_SCR_PSIZE_8BITS | + DMA_SCR_MINC | + I2C_DMA_PRIO); + + /* Do not enable the ITBUFEN bit in the I2C_CR2 register if DMA is + * used. + */ + + stm32_i2c_modifyreg(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_ITBUFEN, 0); + +#ifndef CONFIG_I2C_POLLED + /* Now let DMA do all the work, disable i2c interrupts */ + + regval = stm32_i2c_getreg(priv, STM32_I2C_CR2_OFFSET); + regval &= ~I2C_CR2_ALLINTS; + stm32_i2c_putreg(priv, STM32_I2C_CR2_OFFSET, regval); +#endif + + /* The user can generate a Stop condition in the DMA Transfer Complete + * interrupt routine if enabled. This will be done in the dma rx callback + * Start DMA. + */ + + stm32_dmastart(priv->rxdma, stm32_i2c_dmarxcallback, priv, false); + stm32_i2c_modifyreg(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_DMAEN); +#endif } } @@ -1520,19 +1637,67 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv) if (priv->dcnt >= 1) { - /* Transmitting message. Send byte == write data into write register */ +#ifdef CONFIG_STM32_I2C_DMA + /* if DMA is enabled, only makes sense to make use of it for longer + than 1 B transfers.. */ - stm32_i2c_putreg(priv, STM32_I2C_DR_OFFSET, *priv->ptr++); + if (priv->dcnt > 1) + { + i2cinfo("Starting dma transfer and disabling interrupts\n"); - /* Decrease current message length */ + /* The DMA must be initialized and enabled before the I2C data transfer. + * The DMAEN bit must be set in the I2C_CR2 register before the ADDR event. + */ - stm32_i2c_traceevent(priv, I2CEVENT_WRITE_TO_DR, priv->dcnt); - priv->dcnt--; + stm32_dmasetup(priv->txdma, priv->config->base+STM32_I2C_DR_OFFSET, + (uint32_t) priv->ptr, priv->dcnt, + DMA_SCR_DIR_M2P | + DMA_SCR_MSIZE_8BITS | + DMA_SCR_PSIZE_8BITS | + DMA_SCR_MINC | + I2C_DMA_PRIO ); + /* Do not enable the ITBUFEN bit in the I2C_CR2 register if DMA is + * used. + */ + + stm32_i2c_modifyreg(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_ITBUFEN, 0); + +#ifndef CONFIG_I2C_POLLED + /* Now let DMA do all the work, disable i2c interrupts */ + + regval = stm32_i2c_getreg(priv, STM32_I2C_CR2_OFFSET); + regval &= ~I2C_CR2_ALLINTS; + stm32_i2c_putreg(priv, STM32_I2C_CR2_OFFSET, regval); +#endif + + /* In the interrupt routine after the EOT interrupt, disable DMA + * requests then wait for a BTF event before programming the Stop + * condition. To do this, we'll just call the ISR again in + * dma tx callback, in which point we fall into the msgc==0 case + * which ultimately sends the stop..TODO: but we don't explicitly + * wait for BTF bit being set... + * Start DMA. + */ + + stm32_i2c_modifyreg(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_DMAEN); + stm32_dmastart(priv->txdma, stm32_i2c_dmatxcallback, priv, false); + } + else +#endif /* CONFIG_STM32_I2C_DMA */ + { + /* Transmitting message. Send byte == write data into write register */ + + stm32_i2c_putreg(priv, STM32_I2C_DR_OFFSET, *priv->ptr++); + + /* Decrease current message length */ + + stm32_i2c_traceevent(priv, I2CEVENT_WRITE_TO_DR, priv->dcnt); + priv->dcnt--; + } } else if (priv->dcnt == 0) { - /* After last byte, check what to do based on next message flags */ if (priv->msgc == 0) @@ -1678,6 +1843,7 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv) stm32_i2c_traceevent(priv, I2CEVENT_READ_2, 0); } +#ifndef CONFIG_STM32_I2C_DMA /* Case total message length >= 3 */ else if (priv->dcnt >= 4 && priv->total_msg_len >= 3) @@ -1757,6 +1923,7 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv) priv->dcnt = -1; } +#endif /* CONFIG_STM32_I2C_DMA */ /* Error handling for read mode */ @@ -1765,7 +1932,8 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv) i2cinfo("I2C read mode no correct state detected\n"); i2cinfo(" state %i, dcnt=%i\n", status, priv->dcnt); - /* set condition to terminate ISR and wake waiting thread */ + /* Set condition to terminate ISR and wake waiting thread */ + priv->dcnt = -1; priv->msgc = 0; stm32_i2c_traceevent(priv, I2CEVENT_READ_ERROR, 0); @@ -1804,9 +1972,9 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv) else { - #ifdef CONFIG_I2C_POLLED +#ifdef CONFIG_I2C_POLLED stm32_i2c_traceevent(priv, I2CEVENT_POLL_DEV_NOT_RDY, 0); - #else +#else /* Read rest of the state */ status |= (stm32_i2c_getreg(priv, STM32_I2C_SR2_OFFSET) << 16); @@ -1814,12 +1982,12 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv) i2cinfo(" No correct state detected(start bit, read or write) \n"); i2cinfo(" state %i\n", status); - /* set condition to terminate ISR and wake waiting thread */ + /* Set condition to terminate ISR and wake waiting thread */ priv->dcnt = -1; priv->msgc = 0; stm32_i2c_traceevent(priv, I2CEVENT_STATE_ERROR, 0); - #endif +#endif } /* Messages handling(2/2) @@ -1842,9 +2010,9 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv) priv->msgv = NULL; - #ifdef CONFIG_I2C_POLLED +#ifdef CONFIG_I2C_POLLED priv->intstate = INTSTATE_DONE; - #else +#else /* Clear all interrupts */ uint32_t regval; @@ -1863,12 +2031,98 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv) sem_post(&priv->sem_isr); priv->intstate = INTSTATE_DONE; } - #endif +#endif } return OK; } +/***************************************************************************** + * Name: stm32_i2c_dmarxcallback + * + * Description: + * Called when the RX DMA completes + * + *****************************************************************************/ + +#ifdef CONFIG_STM32_I2C_DMA +static void stm32_i2c_dmarxcallback(DMA_HANDLE handle, uint8_t status, void *arg) +{ +#ifndef CONFIG_I2C_POLLED + uint32_t regval; +#endif + + i2cinfo("DMA rx callback, status = %d \n", status); + + FAR struct stm32_i2c_priv_s *priv = (FAR struct stm32_i2c_priv_s *)arg; + + priv->dcnt = -1; + + /* The user can generate a Stop condition in the DMA Transfer Complete + * interrupt routine if enabled. + */ + + stm32_i2c_sendstop(priv); + + /* Let the I2C periph know to stop DMA transfers, also is used by ISR to check + * if DMA is done. + */ + + stm32_i2c_modifyreg(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_DMAEN, 0); + +#ifndef CONFIG_I2C_POLLED + /* Re-enable interrupts */ + + regval = stm32_i2c_getreg(priv, STM32_I2C_CR2_OFFSET); + regval |= (I2C_CR2_ITERREN | I2C_CR2_ITEVFEN); + stm32_i2c_putreg(priv, STM32_I2C_CR2_OFFSET, regval); +#endif + + /* let the ISR routine take care of shutting down or switching to next msg */ + + stm32_i2c_isr(priv); +} +#endif /* ifdef CONFIG_STM32_I2C_DMA */ + +/***************************************************************************** + * Name: stm32_i2c_dmarxcallback + * + * Description: + * Called when the RX DMA completes + * + *****************************************************************************/ + +#ifdef CONFIG_STM32_I2C_DMA +static void stm32_i2c_dmatxcallback(DMA_HANDLE handle, uint8_t status, void *arg) +{ +#ifndef CONFIG_I2C_POLLED + uint32_t regval; +#endif + + i2cinfo("DMA tx callback, status = %d \n", status); + + FAR struct stm32_i2c_priv_s *priv = (FAR struct stm32_i2c_priv_s *)arg; + + priv->dcnt = 0; + + /* In the interrupt routine after the EOT interrupt, disable DMA requests */ + + stm32_i2c_modifyreg(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_DMAEN, 0); + +#ifndef CONFIG_I2C_POLLED + /* re-enable interrupts */ + + regval = stm32_i2c_getreg(priv, STM32_I2C_CR2_OFFSET); + regval |= (I2C_CR2_ITERREN | I2C_CR2_ITEVFEN); + stm32_i2c_putreg(priv, STM32_I2C_CR2_OFFSET, regval); +#endif + + /* let the ISR routine take care of shutting down or switching to next msg */ + + stm32_i2c_isr(priv); +} +#endif /* ifdef CONFIG_STM32_I2C_DMA */ + /************************************************************************************ * Name: stm32_i2c1_isr * @@ -1914,7 +2168,7 @@ static int stm32_i2c3_isr(int irq, void *context, FAR void *arg) return stm32_i2c_isr(&stm32_i2c3_priv); } #endif -#endif +#endif /* CONFIG_I2C_POLLED */ /************************************************************************************ * Private Initialization and Deinitialization @@ -1972,6 +2226,15 @@ static int stm32_i2c_init(FAR struct stm32_i2c_priv_s *priv) stm32_i2c_setclock(priv, 100000); +#ifdef CONFIG_STM32_I2C_DMA + /* If, in the I2C_CR2 register, the LAST bit is set, I2C automatically + * sends a NACK after the next byte following EOT_1. + * Clear DMA en just in case. + */ + + stm32_i2c_modifyreg(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_DMAEN, I2C_CR2_LAST); +#endif + /* Enable I2C */ stm32_i2c_putreg(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_PE); @@ -1991,6 +2254,7 @@ static int stm32_i2c_deinit(FAR struct stm32_i2c_priv_s *priv) /* Disable I2C */ stm32_i2c_putreg(priv, STM32_I2C_CR1_OFFSET, 0); + stm32_i2c_putreg(priv, STM32_I2C_CR2_OFFSET, 0); /* Unconfigure GPIO pins */ @@ -2006,6 +2270,13 @@ static int stm32_i2c_deinit(FAR struct stm32_i2c_priv_s *priv) irq_detach(priv->config->er_irq); #endif +#ifdef CONFIG_STM32_I2C_DMA + /* Disable DMA */ + + stm32_dmastop(priv->txdma); + stm32_dmastop(priv->rxdma); +#endif + /* Disable clocking */ modifyreg32(STM32_RCC_APB1ENR, priv->config->clk_bit, 0); @@ -2035,7 +2306,15 @@ static int stm32_i2c_transfer(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s #endif int ret = 0; - ASSERT(count); + DEBUGASSERT(count); + +#ifdef CONFIG_STM32_I2C_DMA + /* stop DMA just in case */ + + stm32_i2c_modifyreg(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_DMAEN, 0); + stm32_dmastop(priv->rxdma); + stm32_dmastop(priv->txdma); +#endif #ifdef I2C1_FSMC_CONFLICT /* Disable FSMC that shares a pin with I2C1 (LBAR) */ @@ -2246,11 +2525,11 @@ static int stm32_i2c_reset(FAR struct i2c_master_s *dev) uint32_t frequency; int ret = ERROR; - ASSERT(dev); + DEBUGASSERT(dev); /* Our caller must own a ref */ - ASSERT(priv->refs > 0); + DEBUGASSERT(priv->refs > 0); /* Lock out other clients */ @@ -2412,6 +2691,19 @@ FAR struct i2c_master_s *stm32_i2cbus_initialize(int port) { stm32_i2c_sem_init(priv); stm32_i2c_init(priv); + +#ifdef CONFIG_STM32_I2C_DMA + /* Get DMA channels. NOTE: stm32_dmachannel() will always assign the DMA channel. + * if the channel is not available, then stm32_dmachannel() will block and wait + * until the channel becomes available. WARNING: If you have another device sharing + * a DMA channel with SPI and the code never releases that channel, then the call + * to stm32_dmachannel() will hang forever in this function! Don't let your + * design do that! + */ + priv->rxdma = stm32_dmachannel(priv->rxch); + priv->txdma = stm32_dmachannel(priv->txch); + DEBUGASSERT(priv->rxdma && priv->txdma); +#endif /* #ifdef CONFIG_STM32_I2C_DMA */ } leave_critical_section(flags); @@ -2431,7 +2723,7 @@ int stm32_i2cbus_uninitialize(FAR struct i2c_master_s *dev) FAR struct stm32_i2c_priv_s *priv = (struct stm32_i2c_priv_s *)dev; irqstate_t flags; - ASSERT(dev); + DEBUGASSERT(dev); /* Decrement reference count and check for underflow */ @@ -2454,6 +2746,11 @@ int stm32_i2cbus_uninitialize(FAR struct i2c_master_s *dev) stm32_i2c_deinit(priv); +#ifdef CONFIG_STM32_I2C_DMA + stm32_dmafree(priv->rxdma); + stm32_dmafree(priv->txdma); +#endif + /* Release unused resources */ stm32_i2c_sem_destroy(priv); From ea93357a1ede3e82e7333f4790b322ad3d1ec5d2 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 21 Mar 2017 17:05:47 -0600 Subject: [PATCH 77/81] XMC4xxx: Fix a typo in the SCU header file --- arch/arm/src/xmc4/chip/xmc4_scu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/src/xmc4/chip/xmc4_scu.h b/arch/arm/src/xmc4/chip/xmc4_scu.h index 38d26051b77..2d22084252d 100644 --- a/arch/arm/src/xmc4/chip/xmc4_scu.h +++ b/arch/arm/src/xmc4/chip/xmc4_scu.h @@ -889,7 +889,7 @@ #define SCU_PBCLKCR_PBDIV (1 << 0) /* Bit 0: PB Clock Divider Enable */ # define SCU_PBCLKCR_PBDIV_FCPU (0) /* 0=fCPU */ -# define SCU_PBCLKCR_PBDIV_DIV2 ((1 << 0) /* 1=fCPU/2 */ +# define SCU_PBCLKCR_PBDIV_DIV2 (1 << 0) /* 1=fCPU/2 */ /* USB Clock Control */ From e336d248980a9514dbeac11946a49670d6d2ee41 Mon Sep 17 00:00:00 2001 From: Masayuki Ishikawa Date: Wed, 22 Mar 2017 08:21:22 +0900 Subject: [PATCH 78/81] drivers/lcd/st7565.c: Use ST7565_POWERCTRL_INT instead of ST7565_POWERCTRL_BRF --- drivers/lcd/st7565.c | 2 +- drivers/lcd/st7565.h | 2 -- 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/lcd/st7565.c b/drivers/lcd/st7565.c index 1153c1568bb..d25583a7452 100644 --- a/drivers/lcd/st7565.c +++ b/drivers/lcd/st7565.c @@ -1041,7 +1041,7 @@ FAR struct lcd_dev_s *st7565_initialize(FAR struct st7565_lcd_s *lcd, up_mdelay(2); (void)st7565_send_one_data(priv, ST7565_POWERCTRL_BR); up_mdelay(2); - (void)st7565_send_one_data(priv, ST7565_POWERCTRL_BRF); + (void)st7565_send_one_data(priv, ST7565_POWERCTRL_INT); (void)st7565_send_one_data(priv, ST7565_REG_RES_4_5); (void)st7565_send_one_data(priv, ST7565_SETEVMODE); diff --git a/drivers/lcd/st7565.h b/drivers/lcd/st7565.h index e4788379b9e..cc9d17dd0f4 100644 --- a/drivers/lcd/st7565.h +++ b/drivers/lcd/st7565.h @@ -102,8 +102,6 @@ */ #define ST7565_POWERCTRL_B 0x2c /* 0x2c: Booster=ON */ #define ST7565_POWERCTRL_BR 0x2e /* 0x2e: Booster=ON V/R=ON */ -#define ST7565_POWERCTRL_BRF 0x2f /* 0x23: Booster=ON V/R=ON V/F=ON */ - #define ST7565_POWERCTRL_INT 0x2f /* 0x2f: Only the internal power supply is used */ /* Regulation Resistior ratio V0 = (1+Rb/Ra)*Vev */ From 3f3aa73b8f7bea426f10c3085cf7ed0379a8e464 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 21 Mar 2017 17:51:55 -0600 Subject: [PATCH 79/81] XMC4xxx: USIC SCTR register, appears taht both WLE and FLE fields hold value - 1. --- arch/arm/src/xmc4/chip/xmc4_usic.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/src/xmc4/chip/xmc4_usic.h b/arch/arm/src/xmc4/chip/xmc4_usic.h index 462ac44c955..274d0fae53b 100644 --- a/arch/arm/src/xmc4/chip/xmc4_usic.h +++ b/arch/arm/src/xmc4/chip/xmc4_usic.h @@ -563,7 +563,7 @@ # define USIC_SCTR_TRM_ACTIVE (3 << USIC_SCTR_TRM_SHIFT) /* Active without regard to signal level */ #define USIC_SCTR_FLE_SHIFT (16) /* Bits 16-21: Frame Length */ #define USIC_SCTR_FLE_MASK (0x3f << USIC_SCTR_FLE_SHIFT) -# define USIC_SCTR_FLE(n) ((uint32_t)(n) << USIC_SCTR_FLE_SHIFT) +# define USIC_SCTR_FLE(n) ((uint32_t)((n)-1) << USIC_SCTR_FLE_SHIFT) #define USIC_SCTR_WLE_SHIFT (24) /* Bits 24-27: Word Length */ #define USIC_SCTR_WLE_MASK (15 << USIC_SCTR_WLE_SHIFT) # define USIC_SCTR_WLE(n) ((uint32_t)((n)-1) << USIC_SCTR_WLE_SHIFT) From 4af55cee6e377f5fddf287f8e1d7fc4a9cca206f Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 22 Mar 2017 00:55:44 +0000 Subject: [PATCH 80/81] README.txt edited online with Bitbucket --- configs/xmc4500-relax/README.txt | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/configs/xmc4500-relax/README.txt b/configs/xmc4500-relax/README.txt index e1fd46fa839..9fb7e29c2e9 100644 --- a/configs/xmc4500-relax/README.txt +++ b/configs/xmc4500-relax/README.txt @@ -11,10 +11,8 @@ Status ====== 2017-03-21: The XMC4500 Relax boots into NSH, provides the NSH prompt, - and the LEDs are working. But there is a problem with the USIC baud - (probably); I get garbage on the serial console. This probably means - that either the peripheral clocking is wrong or the baud configuration - is wrong. + and the LEDs are working. But there is a problem with sserial input. + The most likely reason for this is there are no serial RX interripts. Serial Console ============== From a1f0802855d995d1202bdaed42844b07c4077673 Mon Sep 17 00:00:00 2001 From: Masayuki Ishikawa Date: Wed, 22 Mar 2017 10:04:37 +0900 Subject: [PATCH 81/81] Kconfig: Change the minimum SMP_NCPUS to 1 --- sched/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sched/Kconfig b/sched/Kconfig index 3dc0e91eba3..68eea620cff 100644 --- a/sched/Kconfig +++ b/sched/Kconfig @@ -263,7 +263,7 @@ if SMP config SMP_NCPUS int "Number of CPUs" default 4 - range 2 32 + range 1 32 ---help--- This value identifies the number of CPUs supported by the processor that will be used for SMP.