From 676d35f007f9f942d0d1f824f6815257c4a5abc2 Mon Sep 17 00:00:00 2001 From: Huang Qi Date: Mon, 17 Jan 2022 10:21:10 +0800 Subject: [PATCH] risc-v: Make exception_common 8 byte align Some SoC like bl602 require the exception entry 8 byte align, it should be safe for other chips so we can apply it globally. Signed-off-by: Huang Qi --- arch/risc-v/src/common/riscv_exception_common.S | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/risc-v/src/common/riscv_exception_common.S b/arch/risc-v/src/common/riscv_exception_common.S index 1317c5751d8..73850069028 100644 --- a/arch/risc-v/src/common/riscv_exception_common.S +++ b/arch/risc-v/src/common/riscv_exception_common.S @@ -43,6 +43,7 @@ .section .text .global exception_common + .align 8 exception_common: