mirror of
https://github.com/apache/nuttx.git
synced 2026-05-25 01:39:44 +08:00
risc-v/mpfs: add dma support
This commit is contained in:
Janne Rosberg
committed by
Xiang Xiao
Xiang Xiao
parent
502210e98c
commit
673f9519eb
@@ -105,7 +105,15 @@ config MPFS_I2C1
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endmenu
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config MPFS_DMA
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bool "MPFS DMA (PDMA)"
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default n
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select ARCH_DMA
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---help---
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Enable DMA Support. MPFS DMA is Memory-to-Memory only.
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menu "MPFS Others"
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endmenu
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@@ -54,6 +54,10 @@ CHIP_CSRCS += mpfs_lowputc.c mpfs_serial.c
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CHIP_CSRCS += mpfs_start.c mpfs_timerisr.c
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CHIP_CSRCS += mpfs_gpio.c mpfs_systemreset.c
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ifeq ($(CONFIG_MPFS_DMA),y)
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CHIP_CSRCS += mpfs_dma.c
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endif
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ifeq ($(CONFIG_BUILD_PROTECTED),y)
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CMN_CSRCS += riscv_task_start.c riscv_pthread_start.c
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CMN_CSRCS += riscv_signal_dispatch.c riscv_pmp.c
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Executable
+136
@@ -0,0 +1,136 @@
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/****************************************************************************
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* arch/risc-v/src/mpfs/hardware/mpfs_dma.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_RISCV_SRC_MPFS_HARDWARE_MPFS_DMA_H
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#define __ARCH_RISCV_SRC_MPFS_HARDWARE_MPFS_DMA_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include "hardware/mpfs_memorymap.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Register offsets *********************************************************/
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#define MPFS_DMA_CONTROL_OFFSET 0x0000 /* Channel control register */
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#define MPFS_DMA_NEXT_CONFIG_OFFSET 0x0004 /* Next transfer type */
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#define MPFS_DMA_NEXT_BYTES_OFFSET 0x0008 /* Number of bytes to move */
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#define MPFS_DMA_NEXT_DESTINATION_OFFSET 0x0010 /* Destination start address */
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#define MPFS_DMA_NEXT_SOURCE_OFFSET 0x0018 /* Source start address */
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#define MPFS_DMA_EXEC_CONFIG_OFFSET 0x0104 /* Active transfer type */
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#define MPFS_DMA_EXEC_BYTES_OFFSET 0x0108 /* Number of bytes remaining */
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#define MPFS_DMA_EXEC_DESTINATION_OFFSET 0x0110 /* Destination current address */
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#define MPFS_DMA_EXEC_SOURCE_OFFSET 0x0118 /* Source current address */
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#define MPFS_DMA_CHANNEL_OFFSET 0x1000 /* Offset to channels */
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#define MPFS_DMA_REG_OFFSET(x) \
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(uint64_t)(MPFS_PDMA_BASE + (MPFS_DMA_CHANNEL_OFFSET * (x)))
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/* Register bit field definitions *******************************************/
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/* Control register */
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/* Indicates that the channel is in use. Setting this bit clears all of the
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* channel’s Next registers (NextConfig, NextBytes, NextDestination, and
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* NextSource). This bit can only be cleared when run (CR bit 0) is low.
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*/
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#define DMA_CONTROL_CLAIM_SHIFT (0) /* Bit: 0: claim */
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#define DMA_CONTROL_CLAIM_MASK (1 << DMA_CONTROL_CLAIM_SHIFT)
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# define DMA_CONTROL_CLAIM (0 << DMA_CONTROL_CLAIM_SHIFT)
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/* Setting this bit starts a DMA transfer by copying the Next registers
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* into their Exec counterparts.
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*/
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#define DMA_CONTROL_RUN_SHIFT (1) /* Bit: 1: run */
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#define DMA_CONTROL_RUN_MASK (1 << DMA_CONTROL_RUN_SHIFT)
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# define DMA_CONTROL_RUN (1 << DMA_CONTROL_RUN_SHIFT)
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/* Setting this bit will trigger the channel’s Done interrupt once
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* a transfer is complete.
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*/
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#define DMA_CONTROL_DONEIE_SHIFT (14) /* Bit: 14: Done Irq enable */
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#define DMA_CONTROL_DONEIE_MASK (1 << DMA_CONTROL_DONEIE_SHIFT)
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# define DMA_CONTROL_DONEIE (1 << DMA_CONTROL_DONEIE_SHIFT)
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/* Setting this bit will trigger the channel’s Done interrupt once
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* a transfer is complete.
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*/
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#define DMA_CONTROL_ERRORIE_SHIFT (15) /* Bit: 15: Error Irq enable */
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#define DMA_CONTROL_ERRORIE_MASK (1 << DMA_CONTROL_ERRORIE_SHIFT)
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# define DMA_CONTROL_ERRORIE (1 << DMA_CONTROL_ERRORIE_SHIFT)
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/* Indicates that a transfer has completed since the channel was claimed */
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#define DMA_CONTROL_DONE_SHIFT (30) /* Bit: 30: Done */
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#define DMA_CONTROL_DONE_MASK (1 << DMA_CONTROL_DONE_SHIFT)
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# define DMA_CONTROL_DONE (1 << DMA_CONTROL_DONE_SHIFT)
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/* Indicates that a transfer error has occurred since the channel
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* was claimed
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*/
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#define DMA_CONTROL_ERROR_SHIFT (31) /* Bit: 31: Error */
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#define DMA_CONTROL_ERROR_MASK (1 << DMA_CONTROL_ERROR_SHIFT)
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# define DMA_CONTROL_ERROR (1 << DMA_CONTROL_ERROR_SHIFT)
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/* Channel Next Configuration Register */
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/* If set, the Exec registers are reloaded from the Next registers once a
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* transfer is complete. The repeat bit must be cleared by software
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* for the sequence to stop
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*/
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#define DMA_NEXT_CONFIG_REPEAT_SHIFT (2) /* Bit: 2: repeat */
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#define DMA_NEXT_CONFIG_REPEAT_MASK (1 << DMA_NEXT_CONFIG_REPEAT_SHIFT)
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# define DMA_NEXT_CONFIG_REPEAT (1 << DMA_NEXT_CONFIG_REPEAT_SHIFT)
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/* Enforces strict ordering by only allowing one of each transfer type
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* in-flight at a time
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*/
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#define DMA_NEXT_CONFIG_ORDER_SHIFT (3) /* Bit: 3: order */
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#define DMA_NEXT_CONFIG_ORDER_MASK (1 << DMA_NEXT_CONFIG_ORDER_SHIFT)
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# define DMA_NEXT_CONFIG_ORDER (1 << DMA_NEXT_CONFIG_ORDER_SHIFT)
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/* WSIZE and RSIZE. Base 2 Logarithm of DMA transaction sizes.
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* Example: 0 is 1 byte, 3 is 8 bytes, 5 is 32 bytes
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* These fields are WARL (Write-Any Read-Legal), so the actual size used
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* can be determined by reading the field after writing the requested size.
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* */
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#define DMA_NEXT_CONFIG_WSIZE_SHIFT (24) /* Bits: 24-27: write size */
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#define DMA_NEXT_CONFIG_WSIZE_MASK (15 << DMA_NEXT_CONFIG_WSIZE_SHIFT)
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# define DMA_NEXT_CONFIG_WSIZE(x) (x << DMA_NEXT_CONFIG_WSIZE_SHIFT)
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#define DMA_NEXT_CONFIG_RSIZE_SHIFT (28) /* Bits: 28-31: read size */
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#define DMA_NEXT_CONFIG_RSIZE_MASK (15 << DMA_NEXT_CONFIG_RSIZE_SHIFT)
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# define DMA_NEXT_CONFIG_RSIZE(x) (x << DMA_NEXT_CONFIG_RSIZE_SHIFT)
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#endif /* __ARCH_RISCV_SRC_MPFS_HARDWARE_MPFS_DMA_H */
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@@ -27,8 +27,9 @@
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/* Register Base Address ****************************************************/
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#define MPFS_PLIC_BASE (0x0C000000UL)
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#define MPFS_CLINT_BASE (0x02000000UL)
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#define MPFS_PDMA_BASE (0x03000000UL)
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#define MPFS_PLIC_BASE (0x0C000000UL)
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#define MPFS_UART0_LO_BASE (0x20000000UL)
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#define MPFS_WDOG0_LO_BASE (0x20001000UL)
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Executable
+516
File diff suppressed because it is too large
Load Diff
Executable
+93
@@ -0,0 +1,93 @@
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/****************************************************************************
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* arch/risc-v/src/mpfs/mpfs_dma.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_RISCV_SRC_MPFS_MPFS_DMA_H
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#define __ARCH_RISCV_SRC_MPFS_MPFS_DMA_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <stdint.h>
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#include "mpfs_memorymap.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#define MPFS_DMA_NUM_CHANNELS (4)
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/****************************************************************************
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* Public Types
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****************************************************************************/
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#ifndef __ASSEMBLY__
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struct mpfs_dma_channel_config
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{
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uint64_t src_addr; /* source address */
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uint64_t dest_addr; /* destination address */
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uint64_t num_bytes; /* Number of bytes to be transfered. (Base-2) */
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uint8_t enable_done_int; /* enable transfer complete interrupt */
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uint8_t enable_err_int; /* enable transfer error interrupt */
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uint8_t repeat; /* repeat the transaction */
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uint8_t force_order; /* Enforces strict ordering by only
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* allowing one of each transfer type
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* in-flight at a time */
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};
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/****************************************************************************
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* Public Data
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****************************************************************************/
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#ifdef __cplusplus
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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EXTERN int mpfs_dma_setup_transfer(unsigned int channel,
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struct mpfs_dma_channel_config *config);
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EXTERN int mpfs_dma_set_transaction_size(unsigned int channel,
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uint8_t write_size,
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uint8_t read_size);
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EXTERN int mpfs_dma_start(unsigned int channel);
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EXTERN uint32_t mpfs_dma_get_transfer_type(unsigned int channel);
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EXTERN uint64_t mpfs_dma_get_bytes_remaining(unsigned int channel);
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EXTERN uint64_t mpfs_dma_get_current_destination(unsigned int channel);
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EXTERN uint64_t mpfs_dma_get_current_source(unsigned int channel);
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EXTERN int mpfs_dma_get_complete_status(unsigned int channel);
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EXTERN int mpfs_dma_get_error_status(unsigned int channel);
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EXTERN int mpfs_dma_clear_complete_status(unsigned int channel);
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EXTERN int mpfs_dma_clear_error_status(unsigned int channel);
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#if defined(__cplusplus)
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}
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#endif
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#undef EXTERN
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#endif /* __ASSEMBLY__ */
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#endif /* __ARCH_RISCV_SRC_MPFS_MPFS_DMA_H */
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