diff --git a/arch/arm/src/xmc4/chip/xmc4_flash.h b/arch/arm/src/xmc4/chip/xmc4_flash.h new file mode 100644 index 00000000000..e68e7078e9c --- /dev/null +++ b/arch/arm/src/xmc4/chip/xmc4_flash.h @@ -0,0 +1,203 @@ +/************************************************************************************ + * arch/arm/src/xmc4/chip/xmc4_flash.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Reference: XMC4500 Reference Manual V1.5 2014-07 Microcontrollers. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * May include some logic from sample code provided by Infineon: + * + * Copyright (C) 2011-2015 Infineon Technologies AG. All rights reserved. + * + * Infineon Technologies AG (Infineon) is supplying this software for use with + * Infineon's microcontrollers. This file can be freely distributed within + * development tools that are supporting such microcontrollers. + * + * THIS SOFTWARE IS PROVIDED AS IS. NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, + * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_XMC4_CHIP_XMC4_FLASH_H +#define __ARCH_ARM_SRC_XMC4_CHIP_XMC4_FLASH_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register Offsets *****************************************************************/ + +/* PMU Registers -- See ID register */ +/* Prefetch Registers -- See PCON register */ + +/* FLASH Registers */ + +#define XMC4_FLASH_ID_OFFSET 0x1008 /* Flash Module Identification Register */ +#define XMC4_FLASH_FSR_OFFSET 0x1010 /* Flash Status Register */ +#define XMC4_FLASH_FCON_OFFSET 0x1014 /* Flash Configuration Register */ +#define XMC4_FLASH_MARP_OFFSET 0x1018 /* Flash Margin Control Register PFLASH */ +#define XMC4_FLASH_PROCON0_OFFSET 0x1020 /* Flash Protection Configuration User 0 */ +#define XMC4_FLASH_PROCON1_OFFSET 0x1024 /* Flash Protection Configuration User 1 */ +#define XMC4_FLASH_PROCON2_OFFSET 0x1028 /* Flash Protection Configuration User 2 */ + +/* Register Addresses ****************************************************************/ + +/* FLASH Registers */ + +#define XMC4_FLASH_ID (XMC4_FLASH0_BASE+XMC4_FLASH_ID_OFFSET) +#define XMC4_FLASH_FSR (XMC4_FLASH0_BASE+XMC4_FLASH_FSR_OFFSET) +#define XMC4_FLASH_FCON (XMC4_FLASH0_BASE+XMC4_FLASH_FCON_OFFSET) +#define XMC4_FLASH_MARP (XMC4_FLASH0_BASE+XMC4_FLASH_MARP_OFFSET) +#define XMC4_FLASH_PROCON0 (XMC4_FLASH0_BASE+XMC4_FLASH_PROCON0_OFFSET) +#define XMC4_FLASH_PROCON1 (XMC4_FLASH0_BASE+XMC4_FLASH_PROCON1_OFFSET) +#define XMC4_FLASH_PROCON2 (XMC4_FLASH0_BASE+XMC4_FLASH_PROCON2_OFFSET) + +/* Register Bit-Field Definitions **************************************************/ + +/* FLASH Registers */ + +/* Flash Module Identification Register */ + +#define FLASH_ID_MOD_REV_SHIFT (0) /* Bits 0-7: Module Revision Number */ +#define FLASH_ID_MOD_REV_MASK (0xff << FLASH_ID_MOD_REV_SHIFT) +#define FLASH_ID_MOD_TYPE_SHIFT (8) /* Bits 8-15: Module Type */ +#define FLASH_ID_MOD_TYPE_MASK (0xff << FLASH_ID_MOD_REV_SHIFT) +#define FLASH_ID_MOD_NUMBER_SHIFT (16) /* Bits 16-31: Module Number Value */ +#define FLASH_ID_MOD_NUMBER_MASK (0xffff << FLASH_ID_MOD_NUMBER_SHIFT) + +/* Flash Status Register */ + +#define FLASH_FSR_PBUSY (1 << 0) /* Bit 0: Program Flash Busy */ +#define FLASH_FSR_FABUSY (1 << 1) /* Bit 1: Flash Array Busy */ +#define FLASH_FSR_PROG (1 << 4) /* Bit 4: Programming State */ +#define FLASH_FSR_ERASE (1 << 5) /* Bit 5: Erase State */ +#define FLASH_FSR_PFPAGE (1 << 6) /* Bit 6: Program Flash in Page Mode */ +#define FLASH_FSR_PFOPER (1 << 8) /* Bit 8: Program Flash Operation Error */ +#define FLASH_FSR_SQER (1 << 10) /* Bit 10: Command Sequence Error */ +#define FLASH_FSR_PROER (1 << 11) /* Bit 11: Protection Error */ +#define FLASH_FSR_PFSBER (1 << 12) /* Bit 12: PFLASH Single-Bit Error and Correction */ +#define FLASH_FSR_PFDBER (1 << 14) /* Bit 14: PFLASH Double-Bit Error */ +#define FLASH_FSR_PROIN (1 << 16) /* Bit 16: Protection Installed */ +#define FLASH_FSR_RPROIN (1 << 18) /* Bit 18: Read Protection Installed */ +#define FLASH_FSR_RPRODIS (1 << 19) /* Bit 19: Read Protection Disable State */ +#define FLASH_FSR_WPROIN0 (1 << 21) /* Bit 21: Sector Write Protection Installed for User 0 */ +#define FLASH_FSR_WPROIN1 (1 << 22) /* Bit 22: Sector Write Protection Installed for User 1 */ +#define FLASH_FSR_WPROIN2 (1 << 23) /* Bit 23: Sector Write Protection Installed for User 2 */ +#define FLASH_FSR_WPRODIS0 (1 << 25) /* Bit 25: Sector Write Protection Disabled for User 0 */ +#define FLASH_FSR_WPRODIS1 (1 << 26) /* Bit 26: Sector Write Protection Disabled for User 1 */ +#define FLASH_FSR_SLM (1 << 28) /* Bit 28: Flash Sleep Mode */ +#define FLASH_FSR_VER (1 << 31) /* Bit 31: Verify Error */ + +/* Flash Configuration Register */ + +#define FLASH_FCON_WSPFLASH_SHIFT (0) /* Bits 0-3: Wait States for read access to PFLASH */ +#define FLASH_FCON_WSPFLASH_MASK (15 << FLASH_FCON_WSPFLASH_SHIFT) +# define FLASH_FCON_WSPFLASH(n) ((uint32_t)((n)-1) << FLASH_FCON_WSPFLASH_SHIFT) +#define FLASH_FCON_WSECPF (1 << 4) /* Bit 4: Wait State for Error Correction of PFLASH */ +#define FLASH_FCON_IDLE (1 << 13) /* Bit 13: Dynamic Flash Idle */ +#define FLASH_FCON_ESLDIS (1 << 14) /* Bit 14: External Sleep Request Disable */ +#define FLASH_FCON_SLEEP (1 << 15) /* Bit 15: Flash SLEEP */ +#define FLASH_FCON_RPA (1 << 16) /* Bit 16: Read Protection Activated */ +#define FLASH_FCON_DCF (1 << 17) /* Bit 17: Disable Code Fetch from Flash Memory */ +#define FLASH_FCON_DDF (1 << 18) /* Bit 18: Disable Any Data Fetch from Flash */ +#define FLASH_FCON_VOPERM (1 << 24) /* Bit 24: Verify and Operation Error Interrupt Mask */ +#define FLASH_FCON_SQERM (1 << 25) /* Bit 25: Command Sequence Error Interrupt Mask */ +#define FLASH_FCON_PROERM (1 << 26) /* Bit 26: Protection Error Interrupt Mask */ +#define FLASH_FCON_PFSBERM (1 << 27) /* Bit 27: PFLASH Single-Bit Error Interrupt Mask */ +#define FLASH_FCON_PFDBERM (1 << 29) /* Bit 29: PFLASH Double-Bit Error Interrupt Mask */ +#define FLASH_FCON_EOBM (1 << 31) /* Bit 31: End of Busy Interrupt Mask */ + +/* Flash Margin Control Register PFLASH */ + +#define FLASH_MARP_MARGIN_SHIFT (0) /* Bits 0-3: PFLASH Margin Selection */ +#define FLASH_MARP_MARGIN_MASK (15 << FLASH_MARP_MARGIN_SHIFT) +#define FLASH_MARP_TRAPDIS (1 << 15) /* Bit 15: PFLASH Double-Bit Error Trap Disable */ + +/* Flash Protection Configuration User 0 */ + +#define FLASH_PROCON0_S0L (1 << 0) /* Bit 0: Sector 0 Locked for Write Protection by User 0 */ +#define FLASH_PROCON0_S1L (1 << 1) /* Bit 1: Sector 1 Locked for Write Protection by User 0 */ +#define FLASH_PROCON0_S2L (1 << 2) /* Bit 2: Sector 2 Locked for Write Protection by User 0 */ +#define FLASH_PROCON0_S3L (1 << 3) /* Bit 3: Sector 3 Locked for Write Protection by User 0 */ +#define FLASH_PROCON0_S4L (1 << 4) /* Bit 4: Sector 4 Locked for Write Protection by User 0 */ +#define FLASH_PROCON0_S5L (1 << 5) /* Bit 5: Sector 5 Locked for Write Protection by User 0 */ +#define FLASH_PROCON0_S6L (1 << 6) /* Bit 6: Sector 6 Locked for Write Protection by User 0 */ +#define FLASH_PROCON0_S7L (1 << 7) /* Bit 7: Sector 7 Locked for Write Protection by User 0 */ +#define FLASH_PROCON0_S8L (1 << 8) /* Bit 8: Sector 8 Locked for Write Protection by User 0 */ +#define FLASH_PROCON0_S9L (1 << 9) /* Bit 9: Sector 9 Locked for Write Protection by User 0 */ +#define FLASH_PROCON0_S10_S11L (1 << 10) /* Bit 10: Sectors 10 and 11 Locked for Write Protection by User 0 */ +#define FLASH_PROCON0_S12_S13L (1 << 11) /* Bit 11: Sectors 12 and 13 Locked for Write Protection by User 0 */ +#define FLASH_PROCON0_S14_S15L (1 << 12) /* Bit 12: Sectors 14 and 15 Locked for Write Protection by User 0 */ +#define FLASH_PROCON0_RPRO (1 << 15) /* Bit 15: Read Protection Configuration */ + +/* Flash Protection Configuration User 1 */ + +#define FLASH_PROCON1_S0L (1 << 0) /* Bit 0: Sector 0 Locked for Write Protection by User 1 */ +#define FLASH_PROCON1_S1L (1 << 1) /* Bit 1: Sector 1 Locked for Write Protection by User 1 */ +#define FLASH_PROCON1_S2L (1 << 2) /* Bit 2: Sector 2 Locked for Write Protection by User 1 */ +#define FLASH_PROCON1_S3L (1 << 3) /* Bit 3: Sector 3 Locked for Write Protection by User 1 */ +#define FLASH_PROCON1_S4L (1 << 4) /* Bit 4: Sector 4 Locked for Write Protection by User 1 */ +#define FLASH_PROCON1_S5L (1 << 5) /* Bit 5: Sector 5 Locked for Write Protection by User 1 */ +#define FLASH_PROCON1_S6L (1 << 6) /* Bit 6: Sector 6 Locked for Write Protection by User 1 */ +#define FLASH_PROCON1_S7L (1 << 7) /* Bit 7: Sector 7 Locked for Write Protection by User 1 */ +#define FLASH_PROCON1_S8L (1 << 8) /* Bit 8: Sector 8 Locked for Write Protection by User 1 */ +#define FLASH_PROCON1_S9L (1 << 9) /* Bit 9: Sector 9 Locked for Write Protection by User 1 */ +#define FLASH_PROCON1_S10_S11L (1 << 10) /* Bit 10: Sectors 10 and 11 Locked for Write Protection by User 1 */ +#define FLASH_PROCON1_S12_S13L (1 << 11) /* Bit 11: Sectors 12 and 13 Locked for Write Protection by User 1 */ +#define FLASH_PROCON1_S14_S15L (1 << 12) /* Bit 12: Sectors 14 and 15 Locked for Write Protection by User 1 */ +#define FLASH_PROCON1_PSR (1 << 16) /* Bit 16: */ + +/* Flash Protection Configuration User 2 */ + +#define FLASH_PROCON2_S0ROM (1 << 0) /* Bit 0: Sector 0 Locked Forever by User 2 */ +#define FLASH_PROCON2_S1ROM (1 << 1) /* Bit 1: Sector 1 Locked Forever by User 2 */ +#define FLASH_PROCON2_S2ROM (1 << 2) /* Bit 2: Sector 2 Locked Forever by User 2 */ +#define FLASH_PROCON2_S3ROM (1 << 3) /* Bit 3: Sector 3 Locked Forever by User 2 */ +#define FLASH_PROCON2_S4ROM (1 << 4) /* Bit 4: Sector 4 Locked Forever by User 2 */ +#define FLASH_PROCON2_S5ROM (1 << 5) /* Bit 5: Sector 5 Locked Forever by User 2 */ +#define FLASH_PROCON2_S6ROM (1 << 6) /* Bit 6: Sector 6 Locked Forever by User 2 */ +#define FLASH_PROCON2_S7ROM (1 << 7) /* Bit 7: Sector 7 Locked Forever by User 2 */ +#define FLASH_PROCON2_S8ROM (1 << 8) /* Bit 8: Sector 8 Locked Forever by User 2 */ +#define FLASH_PROCON2_S9ROM (1 << 9) /* Bit 9: Sector 9 Locked Forever by User 2 */ +#define FLASH_PROCON2_S10_S11ROM (1 << 10) /* Bit 10: Sectors 10 and 11 Locked Forever by User 2 */ +#define FLASH_PROCON2_S12_S13ROM (1 << 11) /* Bit 11: Sectors 12 and 13 Locked Forever by User 2 */ +#define FLASH_PROCON2_S14_S15ROM (1 << 12) /* Bit 12: Sectors 14 and 15 Locked Forever by User 2 */ + +#endif /* __ARCH_ARM_SRC_XMC4_CHIP_XMC4_SCU_H */ diff --git a/arch/arm/src/xmc4/chip/xmc4_memorymap.h b/arch/arm/src/xmc4/chip/xmc4_memorymap.h index 8cf50174b9a..19dd637ab59 100644 --- a/arch/arm/src/xmc4/chip/xmc4_memorymap.h +++ b/arch/arm/src/xmc4/chip/xmc4_memorymap.h @@ -1,227 +1,227 @@ -/************************************************************************************ - * arch/arm/src/xmc4/chip/xmc4_memorymap.h - * - * Copyright (C) 2017 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Reference: XMC4500 Reference Manual V1.5 2014-07 Microcontrollers. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * May include some logic from sample code provided by Infineon: - * - * Copyright (C) 2011-2015 Infineon Technologies AG. All rights reserved. - * - * Infineon Technologies AG (Infineon) is supplying this software for use with - * Infineon's microcontrollers. This file can be freely distributed within - * development tools that are supporting such microcontrollers. - * - * THIS SOFTWARE IS PROVIDED AS IS. NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, - * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_XMC4_CHIP_XMC4_MEMORYMAP_H -#define __ARCH_ARM_SRC_XMC4_CHIP_XMC4_MEMORYMAP_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Peripheral Memory Map ************************************************************/ -/* Acronyms: - * ADC - Analog to Digital Converter - * CCU - Capture Compare Unit - * DAC - Digital to Analog Converter - * DSD - Delta Sigmoid Demodulator - * ERU - External Request Unit - * FCE - Flexible CRC Engine - * GPDMA - General Purpose DMA - * LEDTS - LED and Touch Sense Control Unit - * PMU - Program Management Unit - * POSIF - Position Interface - * SDMMC - Multi Media Card Interface - * USB - Universal Serial Bus - * USCI - Universal Serial Interface - */ - -#define XMC4_PBA0_BASE 0x40000000 -#define XMC4_VADC_BASE 0x40004000 -#define XMC4_VADC_G0_BASE 0x40004400 -#define XMC4_VADC_G1_BASE 0x40004800 -#define XMC4_VADC_G2_BASE 0x40004c00 -#define XMC4_VADC_G3_BASE 0x40005000 -#define XMC4_DSD_BASE 0x40008000 -#define XMC4_DSD_CH0_BASE 0x40008100 -#define XMC4_DSD_CH1_BASE 0x40008200 -#define XMC4_DSD_CH2_BASE 0x40008300 -#define XMC4_DSD_CH3_BASE 0x40008400 -#define XMC4_CCU40_BASE 0x4000c000 -#define XMC4_CCU40_CC40_BASE 0x4000c100 -#define XMC4_CCU40_CC41_BASE 0x4000c200 -#define XMC4_CCU40_CC42_BASE 0x4000c300 -#define XMC4_CCU40_CC43_BASE 0x4000c400 -#define XMC4_CCU41_BASE 0x40010000 -#define XMC4_CCU41_CC40_BASE 0x40010100 -#define XMC4_CCU41_CC41_BASE 0x40010200 -#define XMC4_CCU41_CC42_BASE 0x40010300 -#define XMC4_CCU41_CC43_BASE 0x40010400 -#define XMC4_CCU42_BASE 0x40014000 -#define XMC4_CCU42_CC40_BASE 0x40014100 -#define XMC4_CCU42_CC41_BASE 0x40014200 -#define XMC4_CCU42_CC42_BASE 0x40014300 -#define XMC4_CCU42_CC43_BASE 0x40014400 -#define XMC4_CCU80_BASE 0x40020000 -#define XMC4_CCU80_CC80_BASE 0x40020100 -#define XMC4_CCU80_CC81_BASE 0x40020200 -#define XMC4_CCU80_CC82_BASE 0x40020300 -#define XMC4_CCU80_CC83_BASE 0x40020400 -#define XMC4_CCU81_BASE 0x40024000 -#define XMC4_CCU81_CC80_BASE 0x40024100 -#define XMC4_CCU81_CC81_BASE 0x40024200 -#define XMC4_CCU81_CC82_BASE 0x40024300 -#define XMC4_CCU81_CC83_BASE 0x40024400 -#define XMC4_POSIF0_BASE 0x40028000 -#define XMC4_POSIF1_BASE 0x4002c000 -#define XMC4_USIC0_BASE 0x40030008 -#define XMC4_USIC0_CH0_BASE 0x40030000 -#define XMC4_USIC0_CH1_BASE 0x40030200 -#define XMC4_ERU1_BASE 0x40044000 - -#define XMC4_PBA1_BASE 0x48000000 -#define XMC4_CCU43_BASE 0x48004000 -#define XMC4_CCU43_CC40_BASE 0x48004100 -#define XMC4_CCU43_CC41_BASE 0x48004200 -#define XMC4_CCU43_CC42_BASE 0x48004300 -#define XMC4_CCU43_CC43_BASE 0x48004400 -#define XMC4_LEDTS0_BASE 0x48010000 -#define XMC4_CAN_BASE 0x48014000 -#define XMC4_CAN_NODE0_BASE 0x48014200 -#define XMC4_CAN_NODE1_BASE 0x48014300 -#define XMC4_CAN_NODE2_BASE 0x48014400 -#define XMC4_CAN_NODE3_BASE 0x48014500 -#define XMC4_CAN_NODE4_BASE 0x48014600 -#define XMC4_CAN_NODE5_BASE 0x48014700 -#define XMC4_CAN_MO_BASE 0x48015000 -#define XMC4_DAC_BASE 0x48018000 -#define XMC4_SDMMC_BASE 0x4801c000 -#define XMC4_USIC1_CH0_BASE 0x48020000 -#define XMC4_USIC1_BASE 0x48020008 -#define XMC4_USIC1_CH1_BASE 0x48020200 -#define XMC4_USIC2_CH0_BASE 0x48024000 -#define XMC4_USIC2_BASE 0x48024008 -#define XMC4_USIC2_CH1_BASE 0x48024200 -#define XMC4_PORT0_BASE 0x48028000 -#define XMC4_PORT1_BASE 0x48028100 -#define XMC4_PORT2_BASE 0x48028200 -#define XMC4_PORT3_BASE 0x48028300 -#define XMC4_PORT4_BASE 0x48028400 -#define XMC4_PORT5_BASE 0x48028500 -#define XMC4_PORT6_BASE 0x48028600 -#define XMC4_PORT7_BASE 0x48028700 -#define XMC4_PORT8_BASE 0x48028800 -#define XMC4_PORT9_BASE 0x48028900 -#define XMC4_PORT14_BASE 0x48028e00 -#define XMC4_PORT15_BASE 0x48028f00 - -#define XMC4_SCU_GENERAL_BASE 0x50004000 -#define XMC4_ETH0_CON_BASE 0x50004040 -#define XMC4_SCU_INTERRUPT_BASE 0x50004074 -#define XMC4_SDMMC_CON_BASE 0x500040b4 -#define XMC4_SCU_PARITY_BASE 0x5000413c -#define XMC4_SCU_TRAP_BASE 0x50004160 -#define XMC4_SCU_POWER_BASE 0x50004200 -#define XMC4_SCU_HIBERNATE_BASE 0x50004300 -#define XMC4_SCU_RESET_BASE 0x50004400 -#define XMC4_SCU_CLK_BASE 0x50004600 -#define XMC4_SCU_OSC_BASE 0x50004700 -#define XMC4_SCU_PLL_BASE 0x50004710 -#define XMC4_ERU0_BASE 0x50004800 -#define XMC4_DLR_BASE 0x50004900 -#define XMC4_RTC_BASE 0x50004a00 -#define XMC4_WDT_BASE 0x50008000 -#define XMC4_ETH0_BASE 0x5000c000 -#define XMC4_USB0_BASE 0x50040000 -#define XMC4_USB0_CH0_BASE 0x50040500 -#define XMC4_USB0_CH1_BASE 0x50040520 -#define XMC4_USB0_CH2_BASE 0x50040540 -#define XMC4_USB0_CH3_BASE 0x50040560 -#define XMC4_USB0_CH4_BASE 0x50040580 -#define XMC4_USB0_CH5_BASE 0x500405a0 -#define XMC4_USB0_CH6_BASE 0x500405c0 -#define XMC4_USB0_CH7_BASE 0x500405e0 -#define XMC4_USB0_CH8_BASE 0x50040600 -#define XMC4_USB0_CH9_BASE 0x50040620 -#define XMC4_USB0_CH10_BASE 0x50040640 -#define XMC4_USB0_CH11_BASE 0x50040660 -#define XMC4_USB0_CH12_BASE 0x50040680 -#define XMC4_USB0_CH13_BASE 0x500406a0 -#define XMC4_USB_EP_BASE 0x50040900 -#define XMC4_USB0_EP1_BASE 0x50040920 -#define XMC4_USB0_EP2_BASE 0x50040940 -#define XMC4_USB0_EP3_BASE 0x50040960 -#define XMC4_USB0_EP4_BASE 0x50040980 -#define XMC4_USB0_EP5_BASE 0x500409a0 -#define XMC4_USB0_EP6_BASE 0x500409c0 -#define XMC4_GPDMA0_CH0_BASE 0x50014000 -#define XMC4_GPDMA0_CH1_BASE 0x50014058 -#define XMC4_GPDMA0_CH2_BASE 0x500140b0 -#define XMC4_GPDMA0_CH3_BASE 0x50014108 -#define XMC4_GPDMA0_CH4_BASE 0x50014160 -#define XMC4_GPDMA0_CH5_BASE 0x500141b8 -#define XMC4_GPDMA0_CH6_BASE 0x50014210 -#define XMC4_GPDMA0_CH7_BASE 0x50014268 -#define XMC4_GPDMA0_BASE 0x500142c0 -#define XMC4_GPDMA1_CH0_BASE 0x50018000 -#define XMC4_GPDMA1_CH1_BASE 0x50018058 -#define XMC4_GPDMA1_CH2_BASE 0x500180b0 -#define XMC4_GPDMA1_CH3_BASE 0x50018108 -#define XMC4_GPDMA1_BASE 0x500182c0 -#define XMC4_FCE_BASE 0x50020000 -#define XMC4_FCE_KE0_BASE 0x50020020 -#define XMC4_FCE_KE1_BASE 0x50020040 -#define XMC4_FCE_KE2_BASE 0x50020060 -#define XMC4_FCE_KE3_BASE 0x50020080 - -#define XMC4_PMU0_BASE 0x58000508 -#define XMC4_FLASH0_BASE 0x58001000 -#define XMC4_PREF_BASE 0x58004000 -#define XMC4_EBU_BASE 0x58008000 - -#define XMC4_PPB_BASE 0xe000e000 - -#endif /* __ARCH_ARM_SRC_XMC4_CHIP_XMC4_SCU_H */ +/************************************************************************************ + * arch/arm/src/xmc4/chip/xmc4_memorymap.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Reference: XMC4500 Reference Manual V1.5 2014-07 Microcontrollers. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * May include some logic from sample code provided by Infineon: + * + * Copyright (C) 2011-2015 Infineon Technologies AG. All rights reserved. + * + * Infineon Technologies AG (Infineon) is supplying this software for use with + * Infineon's microcontrollers. This file can be freely distributed within + * development tools that are supporting such microcontrollers. + * + * THIS SOFTWARE IS PROVIDED AS IS. NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, + * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_XMC4_CHIP_XMC4_MEMORYMAP_H +#define __ARCH_ARM_SRC_XMC4_CHIP_XMC4_MEMORYMAP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Peripheral Memory Map ************************************************************/ +/* Acronyms: + * ADC - Analog to Digital Converter + * CCU - Capture Compare Unit + * DAC - Digital to Analog Converter + * DSD - Delta Sigmoid Demodulator + * ERU - External Request Unit + * FCE - Flexible CRC Engine + * GPDMA - General Purpose DMA + * LEDTS - LED and Touch Sense Control Unit + * PMU - Program Management Unit + * POSIF - Position Interface + * SDMMC - Multi Media Card Interface + * USB - Universal Serial Bus + * USCI - Universal Serial Interface + */ + +#define XMC4_PBA0_BASE 0x40000000 +#define XMC4_VADC_BASE 0x40004000 +#define XMC4_VADC_G0_BASE 0x40004400 +#define XMC4_VADC_G1_BASE 0x40004800 +#define XMC4_VADC_G2_BASE 0x40004c00 +#define XMC4_VADC_G3_BASE 0x40005000 +#define XMC4_DSD_BASE 0x40008000 +#define XMC4_DSD_CH0_BASE 0x40008100 +#define XMC4_DSD_CH1_BASE 0x40008200 +#define XMC4_DSD_CH2_BASE 0x40008300 +#define XMC4_DSD_CH3_BASE 0x40008400 +#define XMC4_CCU40_BASE 0x4000c000 +#define XMC4_CCU40_CC40_BASE 0x4000c100 +#define XMC4_CCU40_CC41_BASE 0x4000c200 +#define XMC4_CCU40_CC42_BASE 0x4000c300 +#define XMC4_CCU40_CC43_BASE 0x4000c400 +#define XMC4_CCU41_BASE 0x40010000 +#define XMC4_CCU41_CC40_BASE 0x40010100 +#define XMC4_CCU41_CC41_BASE 0x40010200 +#define XMC4_CCU41_CC42_BASE 0x40010300 +#define XMC4_CCU41_CC43_BASE 0x40010400 +#define XMC4_CCU42_BASE 0x40014000 +#define XMC4_CCU42_CC40_BASE 0x40014100 +#define XMC4_CCU42_CC41_BASE 0x40014200 +#define XMC4_CCU42_CC42_BASE 0x40014300 +#define XMC4_CCU42_CC43_BASE 0x40014400 +#define XMC4_CCU80_BASE 0x40020000 +#define XMC4_CCU80_CC80_BASE 0x40020100 +#define XMC4_CCU80_CC81_BASE 0x40020200 +#define XMC4_CCU80_CC82_BASE 0x40020300 +#define XMC4_CCU80_CC83_BASE 0x40020400 +#define XMC4_CCU81_BASE 0x40024000 +#define XMC4_CCU81_CC80_BASE 0x40024100 +#define XMC4_CCU81_CC81_BASE 0x40024200 +#define XMC4_CCU81_CC82_BASE 0x40024300 +#define XMC4_CCU81_CC83_BASE 0x40024400 +#define XMC4_POSIF0_BASE 0x40028000 +#define XMC4_POSIF1_BASE 0x4002c000 +#define XMC4_USIC0_BASE 0x40030008 +#define XMC4_USIC0_CH0_BASE 0x40030000 +#define XMC4_USIC0_CH1_BASE 0x40030200 +#define XMC4_ERU1_BASE 0x40044000 + +#define XMC4_PBA1_BASE 0x48000000 +#define XMC4_CCU43_BASE 0x48004000 +#define XMC4_CCU43_CC40_BASE 0x48004100 +#define XMC4_CCU43_CC41_BASE 0x48004200 +#define XMC4_CCU43_CC42_BASE 0x48004300 +#define XMC4_CCU43_CC43_BASE 0x48004400 +#define XMC4_LEDTS0_BASE 0x48010000 +#define XMC4_CAN_BASE 0x48014000 +#define XMC4_CAN_NODE0_BASE 0x48014200 +#define XMC4_CAN_NODE1_BASE 0x48014300 +#define XMC4_CAN_NODE2_BASE 0x48014400 +#define XMC4_CAN_NODE3_BASE 0x48014500 +#define XMC4_CAN_NODE4_BASE 0x48014600 +#define XMC4_CAN_NODE5_BASE 0x48014700 +#define XMC4_CAN_MO_BASE 0x48015000 +#define XMC4_DAC_BASE 0x48018000 +#define XMC4_SDMMC_BASE 0x4801c000 +#define XMC4_USIC1_CH0_BASE 0x48020000 +#define XMC4_USIC1_BASE 0x48020008 +#define XMC4_USIC1_CH1_BASE 0x48020200 +#define XMC4_USIC2_CH0_BASE 0x48024000 +#define XMC4_USIC2_BASE 0x48024008 +#define XMC4_USIC2_CH1_BASE 0x48024200 +#define XMC4_PORT0_BASE 0x48028000 +#define XMC4_PORT1_BASE 0x48028100 +#define XMC4_PORT2_BASE 0x48028200 +#define XMC4_PORT3_BASE 0x48028300 +#define XMC4_PORT4_BASE 0x48028400 +#define XMC4_PORT5_BASE 0x48028500 +#define XMC4_PORT6_BASE 0x48028600 +#define XMC4_PORT7_BASE 0x48028700 +#define XMC4_PORT8_BASE 0x48028800 +#define XMC4_PORT9_BASE 0x48028900 +#define XMC4_PORT14_BASE 0x48028e00 +#define XMC4_PORT15_BASE 0x48028f00 + +#define XMC4_SCU_GENERAL_BASE 0x50004000 +#define XMC4_ETH0_CON_BASE 0x50004040 +#define XMC4_SCU_INTERRUPT_BASE 0x50004074 +#define XMC4_SDMMC_CON_BASE 0x500040b4 +#define XMC4_SCU_PARITY_BASE 0x5000413c +#define XMC4_SCU_TRAP_BASE 0x50004160 +#define XMC4_SCU_POWER_BASE 0x50004200 +#define XMC4_SCU_HIBERNATE_BASE 0x50004300 +#define XMC4_SCU_RESET_BASE 0x50004400 +#define XMC4_SCU_CLK_BASE 0x50004600 +#define XMC4_SCU_OSC_BASE 0x50004700 +#define XMC4_SCU_PLL_BASE 0x50004710 +#define XMC4_ERU0_BASE 0x50004800 +#define XMC4_DLR_BASE 0x50004900 +#define XMC4_RTC_BASE 0x50004a00 +#define XMC4_WDT_BASE 0x50008000 +#define XMC4_ETH0_BASE 0x5000c000 +#define XMC4_USB0_BASE 0x50040000 +#define XMC4_USB0_CH0_BASE 0x50040500 +#define XMC4_USB0_CH1_BASE 0x50040520 +#define XMC4_USB0_CH2_BASE 0x50040540 +#define XMC4_USB0_CH3_BASE 0x50040560 +#define XMC4_USB0_CH4_BASE 0x50040580 +#define XMC4_USB0_CH5_BASE 0x500405a0 +#define XMC4_USB0_CH6_BASE 0x500405c0 +#define XMC4_USB0_CH7_BASE 0x500405e0 +#define XMC4_USB0_CH8_BASE 0x50040600 +#define XMC4_USB0_CH9_BASE 0x50040620 +#define XMC4_USB0_CH10_BASE 0x50040640 +#define XMC4_USB0_CH11_BASE 0x50040660 +#define XMC4_USB0_CH12_BASE 0x50040680 +#define XMC4_USB0_CH13_BASE 0x500406a0 +#define XMC4_USB_EP_BASE 0x50040900 +#define XMC4_USB0_EP1_BASE 0x50040920 +#define XMC4_USB0_EP2_BASE 0x50040940 +#define XMC4_USB0_EP3_BASE 0x50040960 +#define XMC4_USB0_EP4_BASE 0x50040980 +#define XMC4_USB0_EP5_BASE 0x500409a0 +#define XMC4_USB0_EP6_BASE 0x500409c0 +#define XMC4_GPDMA0_CH0_BASE 0x50014000 +#define XMC4_GPDMA0_CH1_BASE 0x50014058 +#define XMC4_GPDMA0_CH2_BASE 0x500140b0 +#define XMC4_GPDMA0_CH3_BASE 0x50014108 +#define XMC4_GPDMA0_CH4_BASE 0x50014160 +#define XMC4_GPDMA0_CH5_BASE 0x500141b8 +#define XMC4_GPDMA0_CH6_BASE 0x50014210 +#define XMC4_GPDMA0_CH7_BASE 0x50014268 +#define XMC4_GPDMA0_BASE 0x500142c0 +#define XMC4_GPDMA1_CH0_BASE 0x50018000 +#define XMC4_GPDMA1_CH1_BASE 0x50018058 +#define XMC4_GPDMA1_CH2_BASE 0x500180b0 +#define XMC4_GPDMA1_CH3_BASE 0x50018108 +#define XMC4_GPDMA1_BASE 0x500182c0 +#define XMC4_FCE_BASE 0x50020000 +#define XMC4_FCE_KE0_BASE 0x50020020 +#define XMC4_FCE_KE1_BASE 0x50020040 +#define XMC4_FCE_KE2_BASE 0x50020060 +#define XMC4_FCE_KE3_BASE 0x50020080 + +#define XMC4_PMU0_BASE 0x58000500 +#define XMC4_FLASH0_BASE 0x58001000 +#define XMC4_PREF_BASE 0x58004000 +#define XMC4_EBU_BASE 0x58008000 + +#define XMC4_PPB_BASE 0xe000e000 + +#endif /* __ARCH_ARM_SRC_XMC4_CHIP_XMC4_SCU_H */ diff --git a/arch/arm/src/xmc4/chip/xmc4_scu.h b/arch/arm/src/xmc4/chip/xmc4_scu.h index 8f6f89cc4a9..e08a64a48c0 100644 --- a/arch/arm/src/xmc4/chip/xmc4_scu.h +++ b/arch/arm/src/xmc4/chip/xmc4_scu.h @@ -626,18 +626,26 @@ #define SCU_SYSCLKCR_SYSDIV_MASK (0xff << SCU_CLK_SYSCLKCR_SYSDIV_SHIFT) # define SCU_SYSCLKCR_SYSDIV(n) ((uint32_t)((n)-1) << SCU_CLK_SYSCLKCR_SYSDIV_SHIFT) -#define SCU_SYSCLKCR_SYSSEL (1 << 16) /* Bit 16: System Clock Selection Value */ -# define SCU_SYSCLKCR_SYSSEL_OFI (0) /* 0=OFI clock */ -# define SCU_SYSCLKCR_SYSSEL_PLL (1 << 16) /* 1=PLL clock */ +#define SCU_SYSCLKCR_SYSSEL (1 << 16) /* Bit 16: System Clock Selection Value */ +# define SCU_SYSCLKCR_SYSSEL_OFI (0) /* 0=OFI clock */ +# define SCU_SYSCLKCR_SYSSEL_PLL (1 << 16) /* 1=PLL clock */ /* CPU Clock Control */ -#define SCU_CPUCLKCR_CPUDIV (1 << 0) /* Bit 0: CPU Clock Divider Enable */ +#define SCU_CPUCLKCR_CPUDIV (1 << 0) /* Bit 0: CPU Clock Divider Enable */ /* Peripheral Bus Clock Control */ #define SCU_PBCLKCR_ + /* USB Clock Control */ -#define SCU_USBCLKCR_ + +#define SCU_USBCLKCR_USBDIV_SHIFT (0) /* Bits 0-2: USB Clock Divider Value */ +#define SCU_USBCLKCR_USBDIV_MASK (7 << SCU_CLK_USBCLKCR_USBDIV_SHIFT) +# define SCU_SYSCLKCR_USBDIV(n) ((uint32_t)((n)-1) << SCU_CLK_USBCLKCR_USBDIV_SHIFT) +#define SCU_USBCLKCR_USBSEL (1 << 16) /* Bit 16: USB Clock Selection Value */ +# define SCU_USBCLKCR_USBSEL_USBPLL (0) /* 0=USB PLL Clock */ +# define SCU_USBCLKCR_USBSEL_PLL (1 << 16) /* 1= PLL Clock */ + /* EBU Clock Control */ #define SCU_EBUCLKCR_ /* CCU Clock Control */ @@ -752,10 +760,34 @@ # define SCU_PLLCON2_K1INSEL_OFI (1 << 8) /* 1=Backup clock source selected */ /* USB PLL Status Register */ -#define SCU_USBPLLSTAT_ + +#define SCU_USBPLLSTAT_VCOBYST (1 << 0) /* Bit 0: VCO Bypass Status */ +#define SCU_USBPLLSTAT_PWDSTAT (1 << 1) /* Bit 1: PLL Power-saving Mode Status */ +#define SCU_USBPLLSTAT_VCOLOCK (1 << 2) /* Bit 2: PLL VCO Lock Status */ +#define SCU_USBPLLSTAT_BY (1 << 6) /* Bit 6: Bypass Mode Status */ +#define SCU_USBPLLSTAT_VCOLOCKED (1 << 7) /* Bit 7: PLL LOCK Status */ + /* USB PLL Control Register */ -#define SCU_USBPLLCON_ + +#define SCU_USBPLLCON_VCOBYP (1 << 0) /* Bit 0: VCO Bypass */ +#define SCU_USBPLLCON_VCOPWD (1 << 1) /* Bit 1: VCO Power Saving Mode */ +#define SCU_USBPLLCON_VCOTR (1 << 2) /* Bit 2: VCO Trim Control */ +#define SCU_USBPLLCON_FINDIS (1 << 4) /* Bit 4: Disconnect Oscillator from VCO */ +#define SCU_USBPLLCON_OSCDISCDIS (1 << 6) /* Bit 6: Oscillator Disconnect Disable */ +#define SCU_USBPLLCON_NDIV_SHIFT (8) /* Bits 8-14: N-Divider Val */ +#define SCU_USBPLLCON_NDIV_MASK (0x7f << SCU_USBPLLCON_NDIV_SHIFT) +# define SCU_USBPLLCON_NDIV(n) ((uint32_t)((n)-1) << SCU_USBPLLCON_NDIV_SHIFT) +#define SCU_USBPLLCON_PLLPWD (1 << 16) /* Bit 16: PLL Power Saving Mode */ +#define SCU_USBPLLCON_RESLD (1 << 18) /* Bit 18: Restart VCO Lock Detection */ +#define SCU_USBPLLCON_PDIV_SHIFT (24) /* Bits 24-27: P-Divider Value */ +#define SCU_USBPLLCON_PDIV_MASK (15 << SCU_USBPLLCON_PDIV_SHIFT) +# define SCU_USBPLLCON_PDIV(n) ((uint32_t)((n)-1) << SCU_USBPLLCON_PDIV_SHIFT) + /* Clock Multiplexing Status Register */ -#define SCU_CLKMXSTAT_ + +#define SCU_CLKMXSTAT_SYSCLKMUX_SHIFT (0) /* Bits 0-1: System Clock Multiplexing Status */ +#define SCU_CLKMXSTAT_SYSCLKMUX_MASK (3 << SCU_CLKMXSTAT_SYSCLKMUX_SHIFT) +# define SCU_CLKMXSTAT_SYSCLKMUX_OFI (1 << SCU_CLKMXSTAT_SYSCLKMUX_SHIFT) +# define SCU_CLKMXSTAT_SYSCLKMUX_PLL (2 << SCU_CLKMXSTAT_SYSCLKMUX_SHIFT) #endif /* __ARCH_ARM_SRC_XMC4_CHIP_XMC4_SCU_H */ diff --git a/arch/arm/src/xmc4/xmc4_clockconfig.c b/arch/arm/src/xmc4/xmc4_clockconfig.c index d7d5a8bc7df..6667ceca861 100644 --- a/arch/arm/src/xmc4/xmc4_clockconfig.c +++ b/arch/arm/src/xmc4/xmc4_clockconfig.c @@ -56,6 +56,7 @@ #include #include "up_arch.h" +#include "chip/xmc4_scu.h" #include @@ -63,10 +64,77 @@ * Pre-processor Definitions ****************************************************************************/ +/* Oscilator reference frequency */ + +#define FOSCREF (2500000U) + +/* Loop delays at different CPU frequencies */ + +#define DELAY_CNT_50US_50MHZ (2500) +#define DELAY_CNT_150US_50MHZ (7500) +#define DELAY_CNT_50US_48MHZ (2400) +#define DELAY_CNT_50US_72MHZ (3600) +#define DELAY_CNT_50US_96MHZ (4800) +#define DELAY_CNT_50US_120MHZ (6000) +#define DELAY_CNT_50US_144MHZ (7200) + +/* PLL settings */ + +#define SCU_PLLSTAT_OSC_USABLE \ + (SCU_PLLSTAT_PLLHV | SCU_PLLSTAT_PLLLV | SCU_PLLSTAT_PLLSP) + +#ifndef BOARD_PLL_CLOCKSRC_XTAL +# define VCO ((BOARD_XTAL_FREQUENCY / BOARD_PLL_PDIV) * BOARD_PLL_NDIV) +#else /* BOARD_PLL_CLOCKSRC_XTAL */ + +# define BOARD_PLL_PDIV 2 +# define BOARD_PLL_NDIV 24 +# define BOARD_PLL_K2DIV 1 + +# define VCO ((OFI_FREQUENCY / BOARD_PLL_PDIV) * BOARD_PLL_NDIV) + +#endif /* !BOARD_PLL_CLOCKSRC_XTAL */ + +#define PLL_K2DIV_24MHZ (VCO / OFI_FREQUENCY) +#define PLL_K2DIV_48MHZ (VCO / 48000000) +#define PLL_K2DIV_72MHZ (VCO / 72000000) +#define PLL_K2DIV_96MHZ (VCO / 96000000) +#define PLL_K2DIV_120MHZ (VCO / 120000000) + +#define CLKSET_VALUE (0x00000000) +#define SYSCLKCR_VALUE (0x00010001) +#define CPUCLKCR_VALUE (0x00000000) +#define PBCLKCR_VALUE (0x00000000) +#define CCUCLKCR_VALUE (0x00000000) +#define WDTCLKCR_VALUE (0x00000000) +#define EBUCLKCR_VALUE (0x00000003) +#define USBCLKCR_VALUE (0x00010000) +#define EXTCLKCR_VALUE (0x01200003) + +#if ((USBCLKCR_VALUE & SCU_USBCLKCR_USBSEL) == SCU_USBCLKCR_USBSEL_USBPLL) +# define USB_DIV 3 +#else +# define USB_DIV 5 +#endif + /**************************************************************************** * Private Functions ****************************************************************************/ +/**************************************************************************** + * Name: delay + ****************************************************************************/ + +static void delay(uint32_t cycles) +{ + volatile uint32_t i; + + for (i = 0; i < cycles ;++i) + { + __asm__ __volatile__ ("nop"); + } +} + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -83,6 +151,383 @@ void xmc4_clock_configure(void) { + uint32_t regval; + uint32_t bitset; + + /* Disable and clear OSC_HP Oscillator Watchdog, System VCO Lock, USB VCO + * Lock, and OSC_ULP Oscillator Watchdog traps. + */ + + bitset = SCU_TRAP_SOSCWDGT | SCU_TRAP_SVCOLCKT | SCU_TRAP_UVCOLCKT | + SCU_TRAP_ULPWDGT; + + regval = getreg32(XMC4_SCU_TRAPDIS); + regval |= bitset; + putreg32(regval, XMC4_SCU_TRAPDIS); + putreg32(bitset, XMC4_SCU_TRAPCLR); + +#ifdef BOARD_FOFI_CALIBRATION + /* Enable factory calibration */ + + regval = getreg32(XMC4_SCU_PLLCON0); + regval |= SCU_PLLCON0_FOTR; + putreg(regval, XMC4_SCU_PLLCON0); +#else + /* Automatic calibration uses the fSTDBY */ + + /* Enable HIB domain */ + /* Power up HIB domain if and only if it is currently powered down */ + + regval = getreg32(XMC4_SCU_PWRSTAT); + if ((regval & SCU_PWR_HIBEN) == 0) + { + regval = getreg32(XMC4_SCU_PWRSET); + regval |= SCU_PWR_HIBEN; + putreg32(regval, XMC4_SCU_PWRSTAT); + + /* Wait until HIB domain is enabled */ + + while((getreg32(XMC4_SCU_PWRSTAT) & SCU_PWR_HIBEN) == 0) + { + } + } + + /* Remove the reset only if HIB domain were in a state of reset */ + + regval = getreg32(XMC4_SCU_RSTSTAT); + if ((regval & SCU_RSTSTAT_HIBRS) ! = 0) + { + regval = getreg32(XMC4_SCU_RSTSTAT); + SCU_RESET->RSTCLR |= SCU_RESET_RSTCLR_HIBRS_Msk; + delay(DELAY_CNT_150US_50MHZ); + } + +#ifdef BOARD_STDBY_CLOCKSRC_OSCULP + /* Enable OSC_ULP */ + + regval = getreg32(XMC4_SCU_OSCULCTRL); + if ((regval & SCU_OSCULCTRL_MODE_MASK) != 0) + { + /* Check SCU_MIRRSTS to ensure that no transfer over serial interface + * is pending. + */ + + while ((getreg32(XMC4_SCU_MIRRSTS) & SCU_MIRRSTS_OSCULCTRL) != 0) + { + } + + /* Enable OSC_ULP */ + + regval &= ~SCU_OSCULCTRL_MODE_MASK; + putreg32(regval, XMC4_SCU_OSCULCTRL); + + /* Check if the clock is OK using OSCULP Oscillator Watchdog */ + + while ((getreg32(XMC4_SCU_MIRRSTS) & SCU_MIRRSTS_HDCR) != 0) + { + } + + regval = getreg32(XMC4_SCU_HDCR); + regval |= SCU_HDCR_ULPWDGEN; + putreg32(regval, XMC4_SCU_HDCR) + + /* Wait till clock is stable */ + + do + { + /* Check SCU_MIRRSTS to ensure that no transfer over serial interface + * is pending. + */ + + while ((getreg32(XMC4_SCU_MIRRSTS) & SCU_MIRRSTS_HDCLR) != 0) + { + } + + putreg32(SCU_HDCLR_ULPWDG, XMC4_SCU_HDCLR) + delay(DELAY_CNT_50US_50MHZ); + } + while ((getreg32(XMC4_SCU_HDSTAT) & SCU_HDSTAT_ULPWDG) != 0); + } + + /* Now OSC_ULP is running and can be used */ + + while ((getreg32(XMC4_SCU_MIRRSTS) & SCU_MIRRSTS_HDCR) != 0) + { + } + + /* Select OSC_ULP as the clock source for RTC and STDBY */ + + regval = getreg32(XMC4_SCU_HDCR); + regval |= (SCU_HDCR_RCS_ULP | SCU_HDCR_STDBYSEL_ULP); + putreg32(regval, XMC4_SCU_HDCR) + + regval = getreg32(XMC4_SCU_TRAPDIS); + regval &= ~SCU_TRAP_ULPWDGT; + putreg32(regval, XMC4_SCU_TRAPDIS); + +#endif /* BOARD_STDBY_CLOCKSRC_OSCULP */ + + /* Enable automatic calibration of internal fast oscillator */ + + regval = getreg32(XMC4_SCU_PLLCON0); + regval |= SCU_PLLCON0_AOTREN; + putreg(regval, XMC4_SCU_PLLCON0); + +#endif /* BOARD_FOFI_CALIBRATION */ + + delay(DELAY_CNT_50US_50MHZ); + +#if BOARD_ENABLE_PLL + + /* Enable PLL */ + + regval = getreg32(XMC4_SCU_PLLCON0); + regval &= ~(SCU_PLLCON0_VCOPWD | SCU_PLLCON0_PLLPWD); + putreg(regval, XMC4_SCU_PLLCON0); + +#ifdef BOARD_PLL_CLOCKSRC_XTAL + /* Enable OSC_HP */ + + if ((getreg32(XMC4_SCU_OSCHPCTRL) & SCU_OSCHPCTRL_MODE_MASK) != 0U) + { + regval = getreg32(XMC4_SCU_OSCHPCTRL); + regval &= ~(SCU_OSCHPCTRL_MODE_MASK | SCU_OSCHPCTRL_OSCVAL_MASK); + regval |= ((OSCHP_GetFrequency() / FOSCREF) - 1) << SCU_OSCHPCTRL_OSCVAL_SHIFT; + putreg32(regval, XMC4_SCU_OSCHPCTRL); + + /* Select OSC_HP clock as PLL input */ + + regval = getreg32(XMC4_SCU_PLLCON2); + regval &= ~SCU_PLLCON2_PINSEL; + putreg32(regval, XMC4_SCU_PLLCON2); + + /* Restart OSC Watchdog */ + + regval = getreg32(XMC4_SCU_PLLCON0); + regval &= ~SCU_PLLCON0_OSCRES; + putreg(regval, XMC4_SCU_PLLCON0); + + /* Wait till OSC_HP output frequency is usable */ + + while ((getreg32(XMC4_SCU_PLLSTAT) & SCU_PLLSTAT_OSC_USABLE) != SCU_PLLSTAT_OSC_USABLE) + { + } + + regval = getreg32(SCU_TRAP_SOSCWDGT); + regval &= ~bitset; + putreg32(regval, SCU_TRAP_SOSCWDGT); + } +#else /* BOARD_PLL_CLOCKSRC_XTAL */ + + /* Select backup clock as PLL input */ + + regval = getreg32(XMC4_SCU_PLLCON2); + regval |= SCU_PLLCON2_PINSEL; + putreg32(regval, XMC4_SCU_PLLCON2); +#endif + + /* Go to bypass the Main PLL */ + + regval = getreg32(XMC4_SCU_PLLCON0); + regval |= SCU_PLLCON0_VCOBYP; + putreg(regval, XMC4_SCU_PLLCON0); + + /* Disconnect Oscillator from PLL */ + + regval |= SCU_PLLCON0_FINDIS; + putreg(regval, XMC4_SCU_PLLCON0); + + /* Setup divider settings for main PLL */ + + regval = (SCU_PLLCON1_NDIV(BOARD_PLL_NDIV) | + SCU_PLLCON1_K2DIV(PLL_K2DIV_24MHZ) | + SCU_PLLCON1_PDIV(BOARD_PLL_PDIV); + putreg32(regval, XMC4_SCU_PLLCON1); + + /* Set OSCDISCDIS */ + + regval = getreg32(XMC4_SCU_PLLCON0); + regval |= SCU_PLLCON0_OSCDISCDIS; + putreg(regval, XMC4_SCU_PLLCON0); + + /* Connect Oscillator to PLL */ + + regval = getreg32(XMC4_SCU_PLLCON0); + regval &= ~SCU_PLLCON0_FINDIS; + putreg(regval, XMC4_SCU_PLLCON0); + + /* Restart PLL Lock detection */ + + regval |= SCU_PLLCON0_RESLD; + putreg(regval, XMC4_SCU_PLLCON0); + + /* wait for PLL Lock at 24MHz*/ + + while ((getreg32(XMC4_SCU_PLLSTAT) & SCU_PLLSTAT_VCOLOCK) == 0) + { + } + + /* Disable bypass- put PLL clock back */ + + regval = getreg32(XMC4_SCU_PLLCON0); + regval &= ~SCU_PLLCON0_VCOBYP; + putreg(regval, XMC4_SCU_PLLCON0); + + /* Wait for normal mode */ + + while ((getreg32(XMC4_SCU_PLLSTAT) & SCU_PLLSTAT_VCOBYST) != 0) + { + } + + regval = getreg32(XMC4_SCU_TRAPDIS); + regval &= ~SCU_TRAP_UVCOLCKT; + putreg32(regval, XMC4_SCU_TRAPDIS); +#endif /* BOARD_ENABLE_PLL */ + + /* Before scaling to final frequency we need to setup the clock dividers */ + + putreg32(SYSCLKCR_VALUE, XMC4_SCU_SYSCLKCR); + putreg32(PBCLKCR_VALUE, XMC4_SCU_PBCLKCR); + putreg32(CPUCLKCR_VALUE, XMC4_SCU_CPUCLKCR); + putreg32(CCUCLKCR_VALUE, XMC4_SCU_CCUCLKCR); + putreg32(WDTCLKCR_VALUE, XMC4_SCU_WDTCLKCR); + putreg32(EBUCLKCR_VALUE, XMC4_SCU_EBUCLKCR); + putreg32(USBCLKCR_VALUE | USB_DIV, XMC4_SCU_USBCLKCR); + putreg32(EXTCLKCR_VALUE, EXTCLKCR); + +#if BOARD_ENABLE_PLL + /* PLL frequency stepping...*/ + /* Reset OSCDISCDIS */ + + regval = getreg32(XMC4_SCU_PLLCON0); + regval &= ~SCU_PLLCON0_OSCDISCDIS; + putreg(regval, XMC4_SCU_PLLCON0); + + regval = (SCU_PLLCON1_NDIV(BOARD_PLL_NDIV) | + SCU_PLLCON1_K2DIV(PLL_K2DIV_48MHZ) | + SCU_PLLCON1_PDIV(BOARD_PLL_PDIV)); + putreg32(regval, XMC4_SCU_PLLCON1); + + delay(DELAY_CNT_50US_48MHZ); + + regval = (SCU_PLLCON1_NDIV(BOARD_PLL_NDIV) | + SCU_PLLCON1_K2DIV(PLL_K2DIV_72MHZ) | + SCU_PLLCON1_PDIV(BOARD_PLL_PDIV)); + putreg32(regval, XMC4_SCU_PLLCON1); + + delay(DELAY_CNT_50US_72MHZ); + + regval = (SCU_PLLCON1_NDIV(BOARD_PLL_NDIV) | + SCU_PLLCON1_K2DIV(PLL_K2DIV_96MHZ) | + SCU_PLLCON1_PDIV(BOARD_PLL_PDIV)); + putreg32(regval, XMC4_SCU_PLLCON1); + + delay(DELAY_CNT_50US_96MHZ); + + regval = (SCU_PLLCON1_NDIV(BOARD_PLL_NDIV) | + SCU_PLLCON1_K2DIV(PLL_K2DIV_120MHZ) | + SCU_PLLCON1_PDIV(BOARD_PLL_PDIV)); + putreg32(regval, XMC4_SCU_PLLCON1); + + delay(DELAY_CNT_50US_120MHZ); + + regval = (SCU_PLLCON1_NDIV(BOARD_PLL_NDIV) | + SCU_PLLCON1_K2DIV(BOARD_PLL_K2DIV) | + SCU_PLLCON1_PDIV(BOARD_PLL_PDIV)); + putreg32(regval, XMC4_SCU_PLLCON1); + + delay(DELAY_CNT_50US_144MHZ); + +#endif /* BOARD_ENABLE_PLL */ + +#if BOARD_ENABLE_USBPLL + /* Enable USB PLL first */ + + regval = getreg32(XMC4_SCU_USBPLLCON); + regval &= ~(SCU_USBPLLCON_VCOPWD | SCU_USBPLLCON_PLLPWD); + getreg32(regval, XMC4_SCU_USBPLLCON); + + /* USB PLL uses as clock input the OSC_HP */ + /* check and if not already running enable OSC_HP */ + + if ((getreg32(XMC4_SCU_OSCHPCTRL) & SCU_OSCHPCTRL_MODE_MASK) != 0U) + { + /* Check if Main PLL is switched on for OSC WDG */ + + regval = getreg32(XMC4_SCU_PLLCON0); + if ((regval & (SCU_PLLCON0_VCOPWD | SCU_PLLCON0_PLLPWD)) != 0) + { + /* Enable PLL first */ + + regval = getreg32(XMC4_SCU_PLLCON0); + regval &= ~(SCU_PLLCON0_VCOPWD | SCU_PLLCON0_PLLPWD); + putreg(regval, XMC4_SCU_PLLCON0); + } + + regval = getreg32(XMC4_SCU_OSCHPCTRL); + regval &= ~(SCU_OSCHPCTRL_MODE_MASK | SCU_OSCHPCTRL_OSCVAL_MASK); + regval |= ((OSCHP_GetFrequency() / FOSCREF) - 1) << SCU_OSCHPCTRL_OSCVAL_SHIFT; + putreg32(regval, XMC4_SCU_OSCHPCTRL); + + /* Restart OSC Watchdog */ + + regval = getreg32(XMC4_SCU_PLLCON0); + regval &= ~SCU_PLLCON0_OSCRES; + putreg(regval, XMC4_SCU_PLLCON0); + + /* Wait till OSC_HP output frequency is usable */ + + while ((getreg32(XMC4_SCU_PLLSTAT) & SCU_PLLSTAT_OSC_USABLE) != SCU_PLLSTAT_OSC_USABLE) + { + } + } + + /* Setup USB PLL */ + /* Go to bypass the USB PLL */ + + regval = getreg32(XMC4_SCU_USBPLLCON); + regval |= SCU_USBPLLCON_VCOBYP; + putreg32(regval, XMC4_SCU_USBPLLCON); + + /* Disconnect Oscillator from USB PLL */ + + regval |= SCU_USBPLLCON_FINDIS; + putreg32(regval, XMC4_SCU_USBPLLCON); + + /* Setup Divider settings for USB PLL */ + + regval = (SCU_USBPLLCON_NDIV(BOARD_USB_NDIV) | SCU_USBPLLCON_PDIV(BOARD_USB_PDIV)); + putreg32(regval, XMC4_SCU_USBPLLCON); + + /* Set OSCDISCDIS */ + + regval |= SCU_USBPLLCON_OSCDISCDIS; + putreg32(regval, XMC4_SCU_USBPLLCON); + + /* Connect Oscillator to USB PLL */ + + regval &= ~SCU_USBPLLCON_FINDIS; + putreg32(regval, XMC4_SCU_USBPLLCON); + + /* Restart PLL Lock detection */ + + regval |= SCU_USBPLLCON_RESLD; + putreg32(regval, XMC4_SCU_USBPLLCON); + + /* Wait for PLL Lock */ + + while ((getreg32(XMC4_SCU_USBPLLSTAT) & SCU_USBPLLSTAT_VCOLOCK) == 0) + { + } + + regval = getreg32(XMC4_SCU_TRAPDIS); + regval &= ~SCU_TRAP_UVCOLCKT; + putreg32(regval, XMC4_SCU_TRAPDIS); +#endif + + /* Enable selected clocks */ + + putreg32(CLKSET_VALUE, XMC4_SCU_CLKSET) } /**************************************************************************** diff --git a/arch/arm/src/xmc4/xmc4_start.c b/arch/arm/src/xmc4/xmc4_start.c index 77e792847e9..e712f97dd37 100644 --- a/arch/arm/src/xmc4/xmc4_start.c +++ b/arch/arm/src/xmc4/xmc4_start.c @@ -48,6 +48,7 @@ #include "up_arch.h" #include "up_internal.h" +#include "chip/xmc4_flash.h" #include "xmc4_userspace.h" @@ -62,6 +63,8 @@ #ifdef CONFIG_ARCH_FPU static inline void xmc4_fpu_config(void); #endif +static inline void xmc4_unaligned(void); +static inline void xmc4_flash_waitstates(void); #ifdef CONFIG_STACK_COLORATION static void go_os_start(void *pv, unsigned int nbytes) __attribute__ ((naked, no_instrument_function, noreturn)); @@ -214,6 +217,41 @@ static inline void xmc4_fpu_config(void) # define xmc4_fpu_config() #endif +/**************************************************************************** + * Name: xmc4_unaligned + * + * Description: + * Enable unaligned memory access by setting SCB_CCR.UNALIGN_TRP = 0 + * + ****************************************************************************/ + +static inline void xmc4_unaligned(void) +{ + uint32_t regval; + + regval = getreg32(NVIC_CFGCON); + regval &= ~NVIC_CFGCON_UNALIGNTRP; + putreg32(regval, NVIC_CFGCON); +} + +/**************************************************************************** + * Name: xmc4_flash_waitstates + * + * Description: + * Enable unaligned memory access by setting SCB_CCR.UNALIGN_TRP = 0 + * + ****************************************************************************/ + +static inline void xmc4_flash_waitstates(void) +{ + uint32_t regval; + + regval = getreg32(XMC4_FLASH_FCON); + regval &= ~FLASH_FCON_WSPFLASH_MASK; + regval |= FLASH_FCON_WSPFLASH(BOARD_FLASH_WS); + putreg32(regval, XMC4_FLASH_FCON); +} + /**************************************************************************** * Name: go_os_start * @@ -281,6 +319,10 @@ void __start(void) xmc4_wddisable(); + /* Enable unaligned memory access */ + + xmc4_unaligned(); + /* Clear .bss. We'll do this inline (vs. calling memset) just to be * certain that there are no issues with the state of global variables. */ @@ -314,6 +356,10 @@ void __start(void) } #endif + /* Set FLASH wait states prior to the configuration of clocking */ + + xmc4_flash_waitstates(); + /* Perform clock and Kinetis module initialization (This depends on * RAM functions having been copied to RAM). */ diff --git a/configs/xmc4500-relax/include/board.h b/configs/xmc4500-relax/include/board.h index a448469bca7..f3616a21e2c 100644 --- a/configs/xmc4500-relax/include/board.h +++ b/configs/xmc4500-relax/include/board.h @@ -65,6 +65,8 @@ * fOFI = 24MHz => fWDT = 24MHz */ +#undef BOARD_FOFI_CALIBRATION /* Enable factory calibration */ + /* On-board crystals * * NOTE: Only the XMC4500 Relax Kit-V1 provides the 32.768KHz RTC crystal. It @@ -87,6 +89,7 @@ * = 288MHz */ +#define BOARD_ENABLE_PLL 1 #define BOARD_PLL_PDIV 2 #define BOARD_PLL_NDIV 48 #define BOARD_PLL_K2DIV 1 @@ -119,9 +122,14 @@ * fUSBPLLVCO <= 520 MHz */ +#undef BOARD_ENABLE_USBPLL #define BOARD_USB_PDIV 2 #define BOARD_USB_NDIV 64 +/* FLASH wait states */ + +#define BOARD_FLASH_WS 5 + /************************************************************************************ * Public Data ************************************************************************************/