From 669196910cb5a9c69b887e5ef30e8cc5e6627b30 Mon Sep 17 00:00:00 2001
From: Ville Juven <ville.juven@unikie.com>
Date: Thu, 1 Jun 2023 15:37:57 +0300
Subject: [PATCH] riscv/saveusercontext: Fix FPU state save

---
 arch/risc-v/src/common/riscv_saveusercontext.S | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/arch/risc-v/src/common/riscv_saveusercontext.S b/arch/risc-v/src/common/riscv_saveusercontext.S
index b89508b3dd6..bbdeca21e0f 100644
--- a/arch/risc-v/src/common/riscv_saveusercontext.S
+++ b/arch/risc-v/src/common/riscv_saveusercontext.S
@@ -56,7 +56,10 @@ up_saveusercontext:
   REGSTORE   sp, REG_X2(a0)       /* original SP */
   REGSTORE   x1, REG_EPC(a0)
 
-  riscv_savefpu   a0
+#ifdef CONFIG_ARCH_FPU
+  addi       a0, a0, INT_XCPT_SIZE /* Save FPU after integer regs */
+  riscv_savefpu a0
+#endif
 
   li         a0, 0
   jr         ra