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Fix PLLSAI clock frequency
This commit is contained in:
committed by
Xiang Xiao
parent
f9386282dc
commit
65ad9c2b7e
@@ -39,7 +39,7 @@
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/* Clocking *****************************************************************/
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/* Clocking *****************************************************************/
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/* The STM32F7 Discovery board provides the following clock sources:
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/* The Meadow board provides the following clock sources:
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*
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*
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* X2: 25 MHz oscillator for STM32F777ZIT6 microcontroller
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* X2: 25 MHz oscillator for STM32F777ZIT6 microcontroller
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* and Ethernet PHY.
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* and Ethernet PHY.
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@@ -146,8 +146,9 @@
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/* Configure factors for PLLSAI clock */
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/* Configure factors for PLLSAI clock */
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#define STM32_RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN(192)
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#define CONFIG_STM32F7_PLLSAI 1
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#define STM32_RCC_PLLSAICFGR_PLLSAIP RCC_PLLSAICFGR_PLLSAIP(2)
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#define STM32_RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN(384)
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#define STM32_RCC_PLLSAICFGR_PLLSAIP RCC_PLLSAICFGR_PLLSAIP(8)
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#define STM32_RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ(2)
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#define STM32_RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ(2)
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#define STM32_RCC_PLLSAICFGR_PLLSAIR RCC_PLLSAICFGR_PLLSAIR(2)
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#define STM32_RCC_PLLSAICFGR_PLLSAIR RCC_PLLSAICFGR_PLLSAIR(2)
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