diff --git a/arch/risc-v/src/rv32im/riscv_assert.c b/arch/risc-v/src/rv32im/riscv_assert.c index 2dfe3c5f034..736c9fbde31 100644 --- a/arch/risc-v/src/rv32im/riscv_assert.c +++ b/arch/risc-v/src/rv32im/riscv_assert.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/rv32im/up_assert.c + * arch/risc-v/src/rv32im/riscv_assert.c * * Copyright (C) 2011-2015, 2018 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/arch/risc-v/src/rv32im/riscv_blocktask.c b/arch/risc-v/src/rv32im/riscv_blocktask.c index 2b141833a17..6f5df0ea9d4 100644 --- a/arch/risc-v/src/rv32im/riscv_blocktask.c +++ b/arch/risc-v/src/rv32im/riscv_blocktask.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/rv32im/up_blocktask.c + * arch/risc-v/src/rv32im/riscv_blocktask.c * * Copyright (C) 2011, 2013-2015 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/arch/risc-v/src/rv32im/riscv_copystate.c b/arch/risc-v/src/rv32im/riscv_copystate.c index caec942fc4d..66e734a2d6c 100644 --- a/arch/risc-v/src/rv32im/riscv_copystate.c +++ b/arch/risc-v/src/rv32im/riscv_copystate.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/rv32im/up_copystate.c + * arch/risc-v/src/rv32im/riscv_copystate.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/arch/risc-v/src/rv32im/riscv_doirq.c b/arch/risc-v/src/rv32im/riscv_doirq.c index 77ce6b9c94e..fc970276af9 100644 --- a/arch/risc-v/src/rv32im/riscv_doirq.c +++ b/arch/risc-v/src/rv32im/riscv_doirq.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/rv32im/up_doirq.c + * arch/risc-v/src/rv32im/riscv_doirq.c * * Copyright (C) 2011, 2014-2015 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/arch/risc-v/src/rv32im/riscv_fpu.S b/arch/risc-v/src/rv32im/riscv_fpu.S index f2a9766134d..a4e3902e439 100644 --- a/arch/risc-v/src/rv32im/riscv_fpu.S +++ b/arch/risc-v/src/rv32im/riscv_fpu.S @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/risc-v/src/rv32im/up_fpu.S + * arch/risc-v/src/rv32im/riscv_fpu.S * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/arch/risc-v/src/rv32im/riscv_initialstate.c b/arch/risc-v/src/rv32im/riscv_initialstate.c index 8c59d638a92..4723dea0636 100644 --- a/arch/risc-v/src/rv32im/riscv_initialstate.c +++ b/arch/risc-v/src/rv32im/riscv_initialstate.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/rv32im/up_initialstate.c + * arch/risc-v/src/rv32im/riscv_initialstate.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/arch/risc-v/src/rv32im/riscv_releasepending.c b/arch/risc-v/src/rv32im/riscv_releasepending.c index d8c0de1a6cb..3f992c661e8 100644 --- a/arch/risc-v/src/rv32im/riscv_releasepending.c +++ b/arch/risc-v/src/rv32im/riscv_releasepending.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/rv32im/up_releasepending.c + * arch/risc-v/src/rv32im/riscv_releasepending.c * * Copyright (C) 2011, 2014-2015 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/arch/risc-v/src/rv32im/riscv_reprioritizertr.c b/arch/risc-v/src/rv32im/riscv_reprioritizertr.c index 4c42e5822a2..11b073e5155 100644 --- a/arch/risc-v/src/rv32im/riscv_reprioritizertr.c +++ b/arch/risc-v/src/rv32im/riscv_reprioritizertr.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/rv32im/up_reprioritizertr.c + * arch/risc-v/src/rv32im/riscv_reprioritizertr.c * * Copyright (C) 2011, 2013-2015 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/arch/risc-v/src/rv32im/riscv_sigdeliver.c b/arch/risc-v/src/rv32im/riscv_sigdeliver.c index cdb2741e02a..b48d75c3622 100644 --- a/arch/risc-v/src/rv32im/riscv_sigdeliver.c +++ b/arch/risc-v/src/rv32im/riscv_sigdeliver.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/rv32im/up_sigdeliver.c + * arch/risc-v/src/rv32im/riscv_sigdeliver.c * * Copyright (C) 2011, 2015, 2018-2018 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/arch/risc-v/src/rv32im/riscv_syscall.S b/arch/risc-v/src/rv32im/riscv_syscall.S index 5545fa7ffac..52e69ecf4bf 100644 --- a/arch/risc-v/src/rv32im/riscv_syscall.S +++ b/arch/risc-v/src/rv32im/riscv_syscall.S @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/riscv/src/rv32im/up_syscall.S + * arch/riscv/src/rv32im/riscv_syscall.S * * Copyright (C) 2011, 2015 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/arch/risc-v/src/rv32im/riscv_unblocktask.c b/arch/risc-v/src/rv32im/riscv_unblocktask.c index 3b67cf82611..69c8c6e214b 100644 --- a/arch/risc-v/src/rv32im/riscv_unblocktask.c +++ b/arch/risc-v/src/rv32im/riscv_unblocktask.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/rv32im/up_unblocktask.c + * arch/risc-v/src/rv32im/riscv_unblocktask.c * * Copyright (C) 2011, 2013-2015 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/arch/risc-v/src/rv64gc/riscv_assert.c b/arch/risc-v/src/rv64gc/riscv_assert.c index 67071dae55d..161326a11fe 100644 --- a/arch/risc-v/src/rv64gc/riscv_assert.c +++ b/arch/risc-v/src/rv64gc/riscv_assert.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/rv64gc/up_assert.c + * arch/risc-v/src/rv64gc/riscv_assert.c * * Copyright (C) 2011-2015, 2018 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/arch/risc-v/src/rv64gc/riscv_blocktask.c b/arch/risc-v/src/rv64gc/riscv_blocktask.c index 24b98ca4b30..63bed2ce9b9 100644 --- a/arch/risc-v/src/rv64gc/riscv_blocktask.c +++ b/arch/risc-v/src/rv64gc/riscv_blocktask.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/rv64gc/up_blocktask.c + * arch/risc-v/src/rv64gc/riscv_blocktask.c * * Copyright (C) 2011, 2013-2015 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/arch/risc-v/src/rv64gc/riscv_copystate.c b/arch/risc-v/src/rv64gc/riscv_copystate.c index 8b8fe6d905b..37df1b82da1 100644 --- a/arch/risc-v/src/rv64gc/riscv_copystate.c +++ b/arch/risc-v/src/rv64gc/riscv_copystate.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/rv64gc/up_copystate.c + * arch/risc-v/src/rv64gc/riscv_copystate.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/arch/risc-v/src/rv64gc/riscv_fault.c b/arch/risc-v/src/rv64gc/riscv_fault.c index d60710fcbc7..1b18e31bb3e 100644 --- a/arch/risc-v/src/rv64gc/riscv_fault.c +++ b/arch/risc-v/src/rv64gc/riscv_fault.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/rv64gc/up_fault.c + * arch/risc-v/src/rv64gc/riscv_fault.c * * Copyright (C) 2020 Masayuki Ishikawa. All rights reserved. * Author: Masayuki Ishikawa diff --git a/arch/risc-v/src/rv64gc/riscv_initialstate.c b/arch/risc-v/src/rv64gc/riscv_initialstate.c index 2fd491320ae..c92f31e05c4 100644 --- a/arch/risc-v/src/rv64gc/riscv_initialstate.c +++ b/arch/risc-v/src/rv64gc/riscv_initialstate.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/rv64gc/up_initialstate.c + * arch/risc-v/src/rv64gc/riscv_initialstate.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/arch/risc-v/src/rv64gc/riscv_releasepending.c b/arch/risc-v/src/rv64gc/riscv_releasepending.c index eff977cb09d..2663e22af11 100644 --- a/arch/risc-v/src/rv64gc/riscv_releasepending.c +++ b/arch/risc-v/src/rv64gc/riscv_releasepending.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/rv64gc/up_releasepending.c + * arch/risc-v/src/rv64gc/riscv_releasepending.c * * Copyright (C) 2011, 2014-2015 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/arch/risc-v/src/rv64gc/riscv_reprioritizertr.c b/arch/risc-v/src/rv64gc/riscv_reprioritizertr.c index a415766f1fd..e268de83656 100644 --- a/arch/risc-v/src/rv64gc/riscv_reprioritizertr.c +++ b/arch/risc-v/src/rv64gc/riscv_reprioritizertr.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/rv64gc/up_reprioritizertr.c + * arch/risc-v/src/rv64gc/riscv_reprioritizertr.c * * Copyright (C) 2011, 2013-2015 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/arch/risc-v/src/rv64gc/riscv_sigdeliver.c b/arch/risc-v/src/rv64gc/riscv_sigdeliver.c index b08dff18efe..f773bee9503 100644 --- a/arch/risc-v/src/rv64gc/riscv_sigdeliver.c +++ b/arch/risc-v/src/rv64gc/riscv_sigdeliver.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/rv64gc/up_sigdeliver.c + * arch/risc-v/src/rv64gc/riscv_sigdeliver.c * * Copyright (C) 2011, 2015, 2018-2018 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/arch/risc-v/src/rv64gc/riscv_signal_dispatch.c b/arch/risc-v/src/rv64gc/riscv_signal_dispatch.c index 3dadf009ecc..46f6670d0b2 100644 --- a/arch/risc-v/src/rv64gc/riscv_signal_dispatch.c +++ b/arch/risc-v/src/rv64gc/riscv_signal_dispatch.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/rv64gc/up_signal_dispatch.c + * arch/risc-v/src/rv64gc/riscv_signal_dispatch.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/arch/risc-v/src/rv64gc/riscv_signal_handler.S b/arch/risc-v/src/rv64gc/riscv_signal_handler.S index 231dcc86e37..531752393e5 100644 --- a/arch/risc-v/src/rv64gc/riscv_signal_handler.S +++ b/arch/risc-v/src/rv64gc/riscv_signal_handler.S @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/rv64gc/up_signal_handler.S + * arch/risc-v/src/rv64gc/riscv_signal_handler.S * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/arch/risc-v/src/rv64gc/riscv_swint.c b/arch/risc-v/src/rv64gc/riscv_swint.c index 8fe94359e55..45031dc05de 100644 --- a/arch/risc-v/src/rv64gc/riscv_swint.c +++ b/arch/risc-v/src/rv64gc/riscv_swint.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/riscv/src/rv64gc/up_swint.c + * arch/riscv/src/rv64gc/riscv_swint.c * * Copyright (C) 2011-2012, 2015, 2019 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/arch/risc-v/src/rv64gc/riscv_testset.S b/arch/risc-v/src/rv64gc/riscv_testset.S index 688e445d2fd..8bff0366b80 100644 --- a/arch/risc-v/src/rv64gc/riscv_testset.S +++ b/arch/risc-v/src/rv64gc/riscv_testset.S @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/rv64gc/up_testset.S + * arch/risc-v/src/rv64gc/riscv_testset.S * * Copyright (C) 2020 Masayuki Ishikawa. All rights reserved. * Author: Masayuki Ishikawa diff --git a/arch/risc-v/src/rv64gc/riscv_unblocktask.c b/arch/risc-v/src/rv64gc/riscv_unblocktask.c index 0dfd147df3e..5f4d990dcc3 100644 --- a/arch/risc-v/src/rv64gc/riscv_unblocktask.c +++ b/arch/risc-v/src/rv64gc/riscv_unblocktask.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/rv64gc/up_unblocktask.c + * arch/risc-v/src/rv64gc/riscv_unblocktask.c * * Copyright (C) 2011, 2013-2015 Gregory Nutt. All rights reserved. * Author: Gregory Nutt