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arch/: Unify the cache interface for all architectures

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This commit is contained in:
Xiang Xiao
2019-03-19 10:37:13 -06:00
committed by Gregory Nutt
parent 2f208fdde8
commit 64252a298f
103 changed files with 2198 additions and 2935 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/Kconfig
+6 -2
View File
@@ -171,11 +171,15 @@ config ARCH_HAVE_IRQPRIO
bool bool
default n default n
config ARCH_L2CACHE config ARCH_ICACHE
bool bool
default n default n
config ARCH_HAVE_COHERENT_DCACHE config ARCH_DCACHE
bool
default n
config ARCH_L2CACHE
bool bool
default n default n
arch/arm/Kconfig
+24 -7
View File
@@ -405,6 +405,8 @@ endchoice
config ARCH_ARM7TDMI config ARCH_ARM7TDMI
bool bool
default n default n
select ARCH_DCACHE
select ARCH_ICACHE
---help--- ---help---
The Arm7TDMI-S is an excellent workhorse processor capable of a wide The Arm7TDMI-S is an excellent workhorse processor capable of a wide
array of applications. Traditionally used in mobile handsets, the array of applications. Traditionally used in mobile handsets, the
@@ -413,6 +415,8 @@ config ARCH_ARM7TDMI
config ARCH_ARM920T config ARCH_ARM920T
bool bool
default n default n
select ARCH_DCACHE
select ARCH_ICACHE
select ARCH_HAVE_MMU select ARCH_HAVE_MMU
select ARCH_USE_MMU select ARCH_USE_MMU
---help--- ---help---
@@ -428,6 +432,8 @@ config ARCH_ARM920T
config ARCH_ARM926EJS config ARCH_ARM926EJS
bool bool
default n default n
select ARCH_DCACHE
select ARCH_ICACHE
select ARCH_HAVE_MMU select ARCH_HAVE_MMU
select ARCH_USE_MMU select ARCH_USE_MMU
---help--- ---help---
@@ -449,6 +455,8 @@ config ARCH_ARM926EJS
config ARCH_ARM1136J config ARCH_ARM1136J
bool bool
default n default n
select ARCH_DCACHE
select ARCH_ICACHE
select ARCH_HAVE_MMU select ARCH_HAVE_MMU
select ARCH_USE_MMU select ARCH_USE_MMU
---help--- ---help---
@@ -459,6 +467,8 @@ config ARCH_ARM1136J
config ARCH_ARM1156T2 config ARCH_ARM1156T2
bool bool
default n default n
select ARCH_DCACHE
select ARCH_ICACHE
select ARCH_HAVE_MMU select ARCH_HAVE_MMU
select ARCH_USE_MMU select ARCH_USE_MMU
---help--- ---help---
@@ -468,6 +478,8 @@ config ARCH_ARM1156T2
config ARCH_ARM1176JZ config ARCH_ARM1176JZ
bool bool
default n default n
select ARCH_DCACHE
select ARCH_ICACHE
select ARCH_HAVE_MMU select ARCH_HAVE_MMU
select ARCH_USE_MMU select ARCH_USE_MMU
---help--- ---help---
@@ -527,54 +539,59 @@ config ARCH_CORTEXM7
select ARCH_HAVE_HIPRI_INTERRUPT select ARCH_HAVE_HIPRI_INTERRUPT
select ARCH_HAVE_RESET select ARCH_HAVE_RESET
select ARCH_HAVE_TESTSET select ARCH_HAVE_TESTSET
select ARCH_HAVE_COHERENT_DCACHE if ELF || MODULE
select ARCH_HAVE_HARDFAULT_DEBUG select ARCH_HAVE_HARDFAULT_DEBUG
select ARCH_HAVE_MEMFAULT_DEBUG select ARCH_HAVE_MEMFAULT_DEBUG
config ARCH_CORTEXA5 config ARCH_CORTEXA5
bool bool
default n default n
select ARCH_DCACHE
select ARCH_ICACHE
select ARCH_HAVE_MMU select ARCH_HAVE_MMU
select ARCH_USE_MMU select ARCH_USE_MMU
select ARCH_HAVE_TESTSET select ARCH_HAVE_TESTSET
select ARCH_HAVE_COHERENT_DCACHE if ELF || MODULE
config ARCH_CORTEXA8 config ARCH_CORTEXA8
bool bool
default n default n
select ARCH_DCACHE
select ARCH_ICACHE
select ARCH_HAVE_MMU select ARCH_HAVE_MMU
select ARCH_USE_MMU select ARCH_USE_MMU
select ARCH_HAVE_TESTSET select ARCH_HAVE_TESTSET
select ARCH_HAVE_COHERENT_DCACHE if ELF || MODULE
config ARCH_CORTEXA9 config ARCH_CORTEXA9
bool bool
default n default n
select ARCH_DCACHE
select ARCH_ICACHE
select ARCH_HAVE_MMU select ARCH_HAVE_MMU
select ARCH_USE_MMU select ARCH_USE_MMU
select ARCH_HAVE_TESTSET select ARCH_HAVE_TESTSET
select ARCH_HAVE_COHERENT_DCACHE if ELF || MODULE
config ARCH_CORTEXR4 config ARCH_CORTEXR4
bool bool
default n default n
select ARCH_DCACHE
select ARCH_ICACHE
select ARCH_HAVE_MPU select ARCH_HAVE_MPU
select ARCH_HAVE_TESTSET select ARCH_HAVE_TESTSET
select ARCH_HAVE_COHERENT_DCACHE if ELF || MODULE
config ARCH_CORTEXR5 config ARCH_CORTEXR5
bool bool
default n default n
select ARCH_DCACHE
select ARCH_ICACHE
select ARCH_HAVE_MPU select ARCH_HAVE_MPU
select ARCH_HAVE_TESTSET select ARCH_HAVE_TESTSET
select ARCH_HAVE_COHERENT_DCACHE if ELF || MODULE
config ARCH_CORTEXR7 config ARCH_CORTEXR7
bool bool
default n default n
select ARCH_DCACHE
select ARCH_ICACHE
select ARCH_HAVE_MPU select ARCH_HAVE_MPU
select ARCH_HAVE_TESTSET select ARCH_HAVE_TESTSET
select ARCH_HAVE_COHERENT_DCACHE if ELF || MODULE
config ARCH_FAMILY config ARCH_FAMILY
string string
arch/arm/src/a1x/Make.defs
+1 -5
View File
@@ -111,11 +111,7 @@ CMN_CSRCS += arm_virtpgaddr.c
endif endif
endif endif
ifeq ($(CONFIG_ELF),y) CMN_CSRCS += arm_cache.c
CMN_CSRCS += arm_coherent_dcache.c
else ifeq ($(CONFIG_MODULE),y)
CMN_CSRCS += arm_coherent_dcache.c
endif
ifeq ($(CONFIG_ARCH_FPU),y) ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += arm_savefpu.S arm_restorefpu.S CMN_ASRCS += arm_savefpu.S arm_restorefpu.S
arch/arm/src/am335x/Make.defs
+1 -5
View File
@@ -107,11 +107,7 @@ CMN_CSRCS += arm_virtpgaddr.c
endif endif
endif endif
ifeq ($(CONFIG_ELF),y) CMN_CSRCS += arm_cache.c
CMN_CSRCS += arm_coherent_dcache.c
else ifeq ($(CONFIG_MODULE),y)
CMN_CSRCS += arm_coherent_dcache.c
endif
ifeq ($(CONFIG_ARCH_FPU),y) ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += arm_savefpu.S arm_restorefpu.S CMN_ASRCS += arm_savefpu.S arm_restorefpu.S
arch/arm/src/am335x/am335x_boot.c
+3 -3
View File
@@ -43,6 +43,7 @@
#include <assert.h> #include <assert.h>
#include <debug.h> #include <debug.h>
#include <nuttx/cache.h>
#ifdef CONFIG_PAGING #ifdef CONFIG_PAGING
# include <nuttx/page.h> # include <nuttx/page.h>
#endif #endif
@@ -52,7 +53,6 @@
#include "chip.h" #include "chip.h"
#include "arm.h" #include "arm.h"
#include "mmu.h" #include "mmu.h"
#include "cache.h"
#include "fpu.h" #include "fpu.h"
#include "up_internal.h" #include "up_internal.h"
#include "up_arch.h" #include "up_arch.h"
@@ -348,8 +348,8 @@ static void am335x_copyvectorblock(void)
#else #else
/* Flush the DCache to assure that the vector data is in physical RAM */ /* Flush the DCache to assure that the vector data is in physical RAM */
arch_clean_dcache((uintptr_t)AM335X_VECTOR_VSRAM, up_clean_dcache((uintptr_t)AM335X_VECTOR_VSRAM,
(uintptr_t)AM335X_VECTOR_VSRAM + am335x_vectorsize()); (uintptr_t)AM335X_VECTOR_VSRAM + am335x_vectorsize());
#endif #endif
} }
arch/arm/src/arm/arm.h
-6
View File
@@ -44,12 +44,6 @@
* Pre-processor Definitions * Pre-processor Definitions
************************************************************************************/ ************************************************************************************/
#undef CONFIG_ALIGNMENT_TRAP
#undef CONFIG_DCACHE_WRITETHROUGH
#undef CONFIG_CACHE_ROUND_ROBIN
#undef CONFIG_DCACHE_DISABLE
#undef CONFIG_ICACHE_DISABLE
/* ARM9EJS **************************************************************************/ /* ARM9EJS **************************************************************************/
/* PSR bits */ /* PSR bits */
arch/arm/src/arm/cache.h
-78
View File
@@ -1,78 +0,0 @@
/****************************************************************************
* arch/arm/src/arm/cache.h
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Several of these cache operations come from Atmel sample code with
* modifications for better integration with NuttX. The Atmel sample code
* has a BSD compatibile license that requires this copyright notice:
*
* Copyright (c) 2008, Atmel Corporation
*
* [Actually, I think that all of the Atmel functions are commented out now]
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the names NuttX nor Atmel nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_ARM_CACHE_H
#define __ARCH_ARM_SRC_ARM_CACHE_H
/****************************************************************************
* Included Files
****************************************************************************/
/****************************************************************************
* Pre-processor Defintiions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
void cp15_flush_idcache(uint32_t start, uint32_t end);
#if 0 /* Not used */
void cp15_invalidate_idcache(void);
void cp15_invalidate_icache(void);
#endif
void cp15_invalidate_dcache(uint32_t start, uint32_t end);
#if 0 /* Not used */
void cp15_invalidate_dcache_all(void);
void cp15_prefetch_icacheline(unsigned int value);
void cp15_testcleaninvalidate_dcache(void);
void cp15_drain_writebuffer(void);
unsigned int cp15_read_dcachelockdown(void);
void cp15_write_dcachelockdown(unsigned int value);
unsigned int cp15_read_icachelockdown(void);
void cp15_write_icachelockdown(unsigned int value);
#endif
#endif /* __ARCH_ARM_SRC_ARM_CACHE_H */
arch/arm/src/arm/up_cache.S
+68 -141
View File
@@ -41,7 +41,7 @@
* *
****************************************************************************/ ****************************************************************************/
.file "up_cp15.S" .file "up_cache.S"
/**************************************************************************** /****************************************************************************
* Included Files * Included Files
@@ -93,10 +93,10 @@
* the corresponding I-Cache lines. * the corresponding I-Cache lines.
*/ */
.globl cp15_flush_idcache .globl up_coherent_dcache
.type cp15_flush_idcache, function .type up_coherent_dcache, function
cp15_flush_idcache: up_coherent_dcache:
bic r0, r0, #CACHE_DLINESIZE - 1 bic r0, r0, #CACHE_DLINESIZE - 1
1: mcr p15, 0, r0, c7, c10, 1 /* Clean D entry */ 1: mcr p15, 0, r0, c7, c10, 1 /* Clean D entry */
mcr p15, 0, r0, c7, c5, 1 /* Invalidate I entry */ mcr p15, 0, r0, c7, c5, 1 /* Invalidate I entry */
@@ -105,34 +105,28 @@ cp15_flush_idcache:
blo 1b blo 1b
mcr p15, 0, r0, c7, c10, 4 /* Drain WB */ mcr p15, 0, r0, c7, c10, 4 /* Drain WB */
mov pc, lr mov pc, lr
.size cp15_flush_idcache, .-cp15_flush_idcache .size up_coherent_dcache, .-up_coherent_dcache
#if 0 /* Not used */ /* Invalidate ICache in the region described by r0=start and r1=end. */
/* Invalidate all of Icache and Dcache */
.globl cp15_invalidate_idcache .globl up_invalidate_icache
.type cp15_invalidate_idcache, function .type up_invalidate_icache, function
cp15_invalidate_idcache: up_invalidate_icache:
mov r0, #0 bic r0, r0, #CACHE_DLINESIZE - 1
mcr p15, 0, r0, c7, c7, 0 1: mcr p15, 0, r0, c7, c5, 1 /* Invalidate I entry */
nop add r0, r0, #CACHE_DLINESIZE
nop cmp r0, r1
nop blo 1b
nop mov pc, lr
nop .size up_invalidate_icache, .-up_invalidate_icache
nop
nop
nop
bx lr
.size cp15_invalidate_idcache, . - cp15_invalidate_idcache
/* Invalidate all of Icache */ /* Invalidate all of Icache */
.globl cp15_invalidate_icache .globl up_invalidate_icache_all
.type cp15_invalidate_icache, function .type up_invalidate_icache_all, function
cp15_invalidate_icache: up_invalidate_icache_all:
mov r0, #0 mov r0, #0
mcr p15, 0, r0, c7, c5, 0 mcr p15, 0, r0, c7, c5, 0
nop nop
@@ -144,30 +138,28 @@ cp15_invalidate_icache:
nop nop
nop nop
bx lr bx lr
.size cp15_invalidate_icache, . - cp15_invalidate_icache .size up_invalidate_icache_all, . - up_invalidate_icache_all
#endif /* Not used */
/* Invalidate D-Cache in the region described by r0=start and r1=end. */ /* Invalidate D-Cache in the region described by r0=start and r1=end. */
.globl cp15_invalidate_dcache .globl up_invalidate_dcache
.type cp15_invalidate_dcache, function .type up_invalidate_dcache, function
cp15_invalidate_dcache: up_invalidate_dcache:
bic r0, r0, #CACHE_DLINESIZE - 1 bic r0, r0, #CACHE_DLINESIZE - 1
1: mcr p15, 0, r0, c7, c6, 1 /* Invalidate D entry */ 1: mcr p15, 0, r0, c7, c6, 1 /* Invalidate D entry */
add r0, r0, #CACHE_DLINESIZE add r0, r0, #CACHE_DLINESIZE
cmp r0, r1 cmp r0, r1
blo 1b blo 1b
mov pc, lr mov pc, lr
.size cp15_invalidate_dcache, .-cp15_invalidate_dcache .size up_invalidate_dcache, .-up_invalidate_dcache
#if 0 /* Not used */
/* Invalidate Dcache */ /* Invalidate Dcache */
.globl cp15_invalidate_dcache_all .globl up_invalidate_dcache_all
.type cp15_invalidate_dcache_all, function .type up_invalidate_dcache_all, function
cp15_invalidate_dcache_all: up_invalidate_dcache_all:
mov r0, #0 mov r0, #0
mcr p15, 0, r0, c7, c6, 0 mcr p15, 0, r0, c7, c6, 0
nop nop
@@ -179,124 +171,59 @@ cp15_invalidate_dcache_all:
nop nop
nop nop
bx lr bx lr
.size cp15_invalidate_dcache_all, . - cp15_invalidate_dcache_all .size up_invalidate_dcache_all, . - up_invalidate_dcache_all
/* CP15 Prefetch Icache line c7 /* Clean D-Cache in the region described by r0=start and r1=end. */
* Performs an Icache lookup of the specified modified virtual address.
* If the cache misses, and the region is cacheable, a linefill is performed.
* Prefetch Icache line (MVA): MCR p15, 0, <Rd>, c7, c13, 1
*/
.globl cp15_prefetch_icacheline .globl up_clean_dcache
.type cp15_prefetch_icacheline, function .type up_clean_dcache, function
cp15_prefetch_icacheline: up_clean_dcache:
mcr p15, 0, r0, c7, c13, 1 bic r0, r0, #CACHE_DLINESIZE - 1
1: mcr p15, 0, r0, c7, c10, 1 /* Clean D entry */
add r0, r0, #CACHE_DLINESIZE
cmp r0, r1
blo 1b
mov pc, lr
.size up_clean_dcache, .-up_clean_dcache
/* Clean D-cache */
.globl up_clean_dcache_all
.type up_clean_dcache_all, function
up_clean_dcache_all:
mrc p15, 0, r0, c7, c10, 3
bne up_clean_dcache_all
bx lr bx lr
.size cp15_prefetch_icacheline, . - cp15_prefetch_icacheline .size up_clean_dcache_all, . - up_clean_dcache_all
/* Clean & invalidate D-Cache in the region described by r0=start and r1=end. */
.globl up_flush_dcache
.type up_flush_dcache, function
up_flush_dcache:
bic r0, r0, #CACHE_DLINESIZE - 1
1: mcr p15, 0, r0, c7, c14, 1 /* Clean & invalidate D entry */
add r0, r0, #CACHE_DLINESIZE
cmp r0, r1
blo 1b
mov pc, lr
.size up_flush_dcache, .-up_flush_dcache
/* CP15 Test, clean, and invalidate Dcache c7 /* CP15 Test, clean, and invalidate Dcache c7
* As for test and clean, except that when the entire cache has * As for test and clean, except that when the entire cache has
* been tested and cleaned, it is invalidated. * been tested and cleaned, it is invalidated.
*/ */
.globl cp15_testcleaninvalidate_dcache .globl up_flush_dcache_all
.type cp15_testcleaninvalidate_dcache, function .type up_flush_dcache_all, function
cp15_testcleaninvalidate_dcache: up_flush_dcache_all:
mrc p15, 0, r0, c7, c14, 3 mrc p15, 0, r0, c7, c14, 3
bne cp15_testcleaninvalidate_dcache bne up_flush_dcache_all
bx lr bx lr
.size cp15_testcleaninvalidate_dcache, . - cp15_testcleaninvalidate_dcache .size up_flush_dcache_all, . - up_flush_dcache_all
/* CP15 Drain write buffer c7
* This instruction acts as an explicit memory barrier. It drains
* the contents of the write buffers of all memory stores
* occurring in program order before this instruction is
* completed. No instructions occurring in program order
* after this instruction are executed until it completes. This
* can be used when timing of specific stores to the level two
* memory system has to be controlled (for example, when a
* store to an interrupt acknowledge location has to complete
* before interrupts are enabled).
*/
.globl cp15_drain_writebuffer
.type cp15_drain_writebuffer, function
cp15_drain_writebuffer:
mov r0, #0
mcr p15, 0, r0, c7, c10, 4
bx lr
.size cp15_drain_writebuffer, . - cp15_drain_writebuffer
/****************************************************************************
* Cache Lockdown
****************************************************************************/
/* Cache Lockdown Register c9
* The Cache Lockdown Register uses a cache-way-based locking scheme (Format C) that
* enables you to control each cache way independently.
* These registers enable you to control which cache ways of the four-way cache are used
* for the allocation on a linefill. When the registers are defined, subsequent linefills are
* only placed in the specified target cache way. This gives you some control over the
* cache pollution caused by particular applications, and provides a traditional lockdown
* operation for locking critical code into the cache.
*
* Read Dcache Lockdown Register MRC p15,0,<Rd>,c9,c0,0
* Write Dcache Lockdown Register MCR p15,0,<Rd>,c9,c0,0
* Read Icache Lockdown Register MRC p15,0,<Rd>,c9,c0,1
* Write Icache Lockdown Register MCR p15,0,<Rd>,c9,c0,1
*/
.globl cp15_read_dcachelockdown
.type cp15_read_dcachelockdown, function
cp15_read_dcachelockdown:
mov r0, #0
mrc p15, 0, r0, c9, c0, 0
bx lr
.size cp15_read_dcachelockdown, . - cp15_read_dcachelockdown
.globl cp15_write_dcachelockdown
.type cp15_write_dcachelockdown, function
cp15_write_dcachelockdown:
mcr p15, 0, r0, c9, c0, 0
nop
nop
nop
nop
nop
nop
nop
nop
bx lr
.size cp15_write_dcachelockdown, . - cp15_write_dcachelockdown
.globl cp15_read_icachelockdown
.type cp15_read_icachelockdown, function
cp15_read_icachelockdown:
mov r0, #0
mrc p15, 0, r0, c9, c0, 1
bx lr
.size cp15_read_icachelockdown, . - cp15_read_icachelockdown
.globl cp15_write_icachelockdown
.type cp15_write_icachelockdown, function
cp15_write_icachelockdown:
mcr p15, 0, r0, c9, c0, 1
nop
nop
nop
nop
nop
nop
nop
nop
bx lr
.size cp15_write_icachelockdown, . - cp15_write_icachelockdown
#endif /* Not used */
.end .end
arch/arm/src/armv7-a/arm_addrenv.c
+12 -13
View File
@@ -118,7 +118,6 @@
#include <nuttx/irq.h> #include <nuttx/irq.h>
#include "pgalloc.h" #include "pgalloc.h"
#include "cache.h"
#include "mmu.h" #include "mmu.h"
#include "addrenv.h" #include "addrenv.h"
@@ -181,8 +180,8 @@ static int up_addrenv_initdata(uintptr_t l2table)
/* Invalidate D-Cache so that we read from the physical memory */ /* Invalidate D-Cache so that we read from the physical memory */
arch_invalidate_dcache((uintptr_t)virtptr, up_invalidate_dcache((uintptr_t)virtptr,
(uintptr_t)virtptr + sizeof(uint32_t)); (uintptr_t)virtptr + sizeof(uint32_t));
/* Get the physical address of the first page of of .bss/.data */ /* Get the physical address of the first page of of .bss/.data */
@@ -208,8 +207,8 @@ static int up_addrenv_initdata(uintptr_t l2table)
/* Make sure that the initialized data is flushed to physical memory. */ /* Make sure that the initialized data is flushed to physical memory. */
arch_flush_dcache((uintptr_t)virtptr, up_flush_dcache((uintptr_t)virtptr,
(uintptr_t)virtptr + ARCH_DATA_RESERVE_SIZE); (uintptr_t)virtptr + ARCH_DATA_RESERVE_SIZE);
#ifndef CONFIG_ARCH_PGPOOL_MAPPING #ifndef CONFIG_ARCH_PGPOOL_MAPPING
/* Restore the scratch section L1 page table entry */ /* Restore the scratch section L1 page table entry */
@@ -715,18 +714,18 @@ int up_addrenv_coherent(FAR const group_addrenv_t *addrenv)
#warning REVISIT... causes crashes #warning REVISIT... causes crashes
#if 0 #if 0
arch_clean_dcache(CONFIG_ARCH_TEXT_VBASE, up_clean_dcache(CONFIG_ARCH_TEXT_VBASE,
CONFIG_ARCH_TEXT_VBASE + CONFIG_ARCH_TEXT_VBASE +
CONFIG_ARCH_TEXT_NPAGES * MM_PGSIZE - 1); CONFIG_ARCH_TEXT_NPAGES * MM_PGSIZE - 1);
arch_clean_dcache(CONFIG_ARCH_DATA_VBASE, up_clean_dcache(CONFIG_ARCH_DATA_VBASE,
CONFIG_ARCH_DATA_VBASE + CONFIG_ARCH_DATA_VBASE +
CONFIG_ARCH_DATA_NPAGES * MM_PGSIZE - 1); CONFIG_ARCH_DATA_NPAGES * MM_PGSIZE - 1);
#endif #endif
#ifdef CONFIG_BUILD_KERNEL #ifdef CONFIG_BUILD_KERNEL
arch_clean_dcache(CONFIG_ARCH_HEAP_VBASE, up_clean_dcache(CONFIG_ARCH_HEAP_VBASE,
CONFIG_ARCH_HEAP_VBASE + addrenv->heapsize); CONFIG_ARCH_HEAP_VBASE + addrenv->heapsize);
#endif #endif
return OK; return OK;
arch/arm/src/armv7-a/arm_addrenv_shm.c
+6 -7
View File
@@ -49,7 +49,6 @@
#include <nuttx/addrenv.h> #include <nuttx/addrenv.h>
#include "mmu.h" #include "mmu.h"
#include "cache.h"
#include "addrenv.h" #include "addrenv.h"
#include "pgalloc.h" #include "pgalloc.h"
@@ -195,9 +194,9 @@ int up_shmat(FAR uintptr_t *pages, unsigned int npages, uintptr_t vaddr)
* flush the entire L2 page table numerous times. * flush the entire L2 page table numerous times.
*/ */
arch_flush_dcache((uintptr_t)l2table, up_flush_dcache((uintptr_t)l2table,
(uintptr_t)l2table + (uintptr_t)l2table +
ENTRIES_PER_L2TABLE * sizeof(uint32_t)); ENTRIES_PER_L2TABLE * sizeof(uint32_t));
#ifndef CONFIG_ARCH_PGPOOL_MAPPING #ifndef CONFIG_ARCH_PGPOOL_MAPPING
/* Restore the scratch section L1 page table entry */ /* Restore the scratch section L1 page table entry */
@@ -313,9 +312,9 @@ int up_shmdt(uintptr_t vaddr, unsigned int npages)
* flush the entire L2 page table numerous times. * flush the entire L2 page table numerous times.
*/ */
arch_flush_dcache((uintptr_t)l2table, up_flush_dcache((uintptr_t)l2table,
(uintptr_t)l2table + (uintptr_t)l2table +
ENTRIES_PER_L2TABLE * sizeof(uint32_t)); ENTRIES_PER_L2TABLE * sizeof(uint32_t));
#ifndef CONFIG_ARCH_PGPOOL_MAPPING #ifndef CONFIG_ARCH_PGPOOL_MAPPING
/* Restore the scratch section L1 page table entry */ /* Restore the scratch section L1 page table entry */
arch/arm/src/armv7-a/arm_addrenv_utils.c
+3 -5
View File
@@ -43,10 +43,8 @@
#include <debug.h> #include <debug.h>
#include <nuttx/pgalloc.h> #include <nuttx/pgalloc.h>
#include <nuttx/irq.h> #include <nuttx/irq.h>
#include "cache.h"
#include "mmu.h" #include "mmu.h"
#include "pgalloc.h" #include "pgalloc.h"
#include "addrenv.h" #include "addrenv.h"
@@ -166,9 +164,9 @@ int arm_addrenv_create_region(FAR uintptr_t **list, unsigned int listlen,
* memory. * memory.
*/ */
arch_flush_dcache((uintptr_t)l2table, up_flush_dcache((uintptr_t)l2table,
(uintptr_t)l2table + (uintptr_t)l2table +
ENTRIES_PER_L2TABLE * sizeof(uint32_t)); ENTRIES_PER_L2TABLE * sizeof(uint32_t));
#ifndef CONFIG_ARCH_PGPOOL_MAPPING #ifndef CONFIG_ARCH_PGPOOL_MAPPING
/* Restore the scratch section L1 page table entry */ /* Restore the scratch section L1 page table entry */
arch/arm/src/armv7-r/cache.h → arch/arm/src/armv7-a/arm_cache.c
+114 -91
View File
@@ -1,7 +1,7 @@
/************************************************************************************ /****************************************************************************
* arch/arm/src/armv7-r/cache.h * arch/arm/src/armv7-a/arm_cache.c
* *
* Copyright (C) 2015 Gregory Nutt. All rights reserved. * Copyright (C) 2014, 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org> * Author: Gregory Nutt <gnutt@nuttx.org>
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
@@ -31,25 +31,22 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE. * POSSIBILITY OF SUCH DAMAGE.
* *
************************************************************************************/ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_ARMV7_R_CACHE_H /****************************************************************************
#define __ARCH_ARM_SRC_ARMV7_R_CACHE_H
/************************************************************************************
* Included Files * Included Files
************************************************************************************/ ****************************************************************************/
#include <nuttx/config.h> #include <nuttx/config.h>
#include <nuttx/cache.h>
#include <nuttx/irq.h> #include <nuttx/irq.h>
#include "sctlr.h"
#include "cp15_cacheops.h" #include "cp15_cacheops.h"
#include "l2cc.h" #include "l2cc.h"
/************************************************************************************ /****************************************************************************
* Pre-processor Definitions * Pre-processor Definitions
************************************************************************************/ ****************************************************************************/
/* Intrinsics are used in these inline functions */ /* Intrinsics are used in these inline functions */
@@ -61,14 +58,12 @@
#define ARM_ISB() arm_isb(15) #define ARM_ISB() arm_isb(15)
#define ARM_DMB() arm_dmb(15) #define ARM_DMB() arm_dmb(15)
/************************************************************************************ /****************************************************************************
* Inline Functions * Public Functions
************************************************************************************/ ****************************************************************************/
#ifndef __ASSEMBLY__
/**************************************************************************** /****************************************************************************
* Name: arch_invalidate_dcache * Name: up_invalidate_dcache
* *
* Description: * Description:
* Invalidate the data cache within the specified region; we will be * Invalidate the data cache within the specified region; we will be
@@ -89,14 +84,14 @@
* *
****************************************************************************/ ****************************************************************************/
static inline void arch_invalidate_dcache(uintptr_t start, uintptr_t end) void up_invalidate_dcache(uintptr_t start, uintptr_t end)
{ {
cp15_invalidate_dcache(start, end); cp15_invalidate_dcache(start, end);
l2cc_invalidate(start, end); l2cc_invalidate(start, end);
} }
/**************************************************************************** /****************************************************************************
* Name: arch_invalidate_dcache_all * Name: up_invalidate_dcache_all
* *
* Description: * Description:
* Invalidate the entire contents of D cache. * Invalidate the entire contents of D cache.
@@ -112,7 +107,7 @@ static inline void arch_invalidate_dcache(uintptr_t start, uintptr_t end)
* *
****************************************************************************/ ****************************************************************************/
static inline void arch_invalidate_dcache_all(void) void up_invalidate_dcache_all(void)
{ {
#ifdef CONFIG_ARCH_L2CACHE #ifdef CONFIG_ARCH_L2CACHE
irqstate_t flags = enter_critical_section(); irqstate_t flags = enter_critical_section();
@@ -124,11 +119,12 @@ static inline void arch_invalidate_dcache_all(void)
#endif #endif
} }
/************************************************************************************ /****************************************************************************
* Name: arch_invalidate_icache * Name: up_invalidate_icache_all
* *
* Description: * Description:
* Invalidate all instruction caches to PoU, also flushes branch target cache * Invalidate all instruction caches to PoU, also flushes branch target
* cache
* *
* Input Parameters: * Input Parameters:
* None * None
@@ -136,12 +132,15 @@ static inline void arch_invalidate_dcache_all(void)
* Returned Value: * Returned Value:
* None * None
* *
************************************************************************************/ ****************************************************************************/
#define arch_invalidate_icache() cp15_invalidate_icache() void up_invalidate_icache_all(void)
{
cp15_invalidate_icache();
}
/**************************************************************************** /****************************************************************************
* Name: arch_clean_dcache * Name: up_clean_dcache
* *
* Description: * Description:
* Clean the data cache within the specified region by flushing the * Clean the data cache within the specified region by flushing the
@@ -161,14 +160,14 @@ static inline void arch_invalidate_dcache_all(void)
* *
****************************************************************************/ ****************************************************************************/
static inline void arch_clean_dcache(uintptr_t start, uintptr_t end) void up_clean_dcache(uintptr_t start, uintptr_t end)
{ {
cp15_clean_dcache(start, end); cp15_clean_dcache(start, end);
l2cc_clean(start, end); l2cc_clean(start, end);
} }
/**************************************************************************** /****************************************************************************
* Name: arch_flush_dcache * Name: up_flush_dcache
* *
* Description: * Description:
* Flush the data cache within the specified region by cleaning and * Flush the data cache within the specified region by cleaning and
@@ -188,14 +187,14 @@ static inline void arch_clean_dcache(uintptr_t start, uintptr_t end)
* *
****************************************************************************/ ****************************************************************************/
static inline void arch_flush_dcache(uintptr_t start, uintptr_t end) void up_flush_dcache(uintptr_t start, uintptr_t end)
{ {
cp15_flush_dcache(start, end); cp15_flush_dcache(start, end);
l2cc_flush(start, end); l2cc_flush(start, end);
} }
/**************************************************************************** /****************************************************************************
* Name: arch_enable_icache * Name: up_enable_icache
* *
* Description: * Description:
* Enable the I-Cache * Enable the I-Cache
@@ -208,76 +207,100 @@ static inline void arch_flush_dcache(uintptr_t start, uintptr_t end)
* *
****************************************************************************/ ****************************************************************************/
static inline void arch_enable_icache(void) void up_enable_icache(void)
{ {
#ifdef CONFIG_ARMV7R_ICACHE cp15_enable_icache();
uint32_t regval;
ARM_DSB();
ARM_ISB();
/* Enable the I-Cache */
regval = cp15_rdsctlr();
if ((regval & SCTLR_I) == 0)
{
cp15_wrsctlr(regval | SCTLR_I);
}
ARM_DSB();
ARM_ISB();
#endif
} }
/**************************************************************************** /****************************************************************************
* Name: arch_enable_dcache * Name: up_disable_icache
* *
* Description: * Description:
* Enable the D-Cache * Disable the I-Cache
* *
* Input Parameters: * Input Parameters:
* None * None
* *
* Returned Value: * Returned Value:
* None * None
* *
****************************************************************************/
static inline void arch_enable_dcache(void)
{
#ifdef CONFIG_ARMV7R_DCACHE
uint32_t regval;
/* Enable the D-Cache */
regval = cp15_rdsctlr();
if ((regval & SCTLR_C) == 0)
{
cp15_wrsctlr(regval | SCTLR_C);
}
#endif
}
/****************************************************************************
* Public Data
****************************************************************************/ ****************************************************************************/
#ifdef __cplusplus void up_disable_icache(void)
#define EXTERN extern "C"
extern "C"
{ {
#else cp15_disable_icache();
#define EXTERN extern }
#endif
/**************************************************************************** /****************************************************************************
* Public Function Prototypes * Name: up_enable_dcache
*
* Description:
* Enable the D-Cache
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/ ****************************************************************************/
#undef EXTERN void up_enable_dcache(void)
#ifdef __cplusplus {
cp15_enable_dcache();
l2cc_enable();
} }
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_ARMV7_R_CACHE_H */ /****************************************************************************
* Name: up_disable_dcache
*
* Description:
* Disable the D-Cache
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void up_disable_dcache(void)
{
cp15_disable_dcache();
l2cc_disable();
}
/****************************************************************************
* Name: up_coherent_dcache
*
* Description:
* Ensure that the I and D caches are coherent within specified region
* by cleaning the D cache (i.e., flushing the D cache contents to memory
* and invalidating the I cache. This is typically used when code has been
* written to a memory region, and will be executed.
*
* Input Parameters:
* addr - virtual start address of region
* len - Size of the address region in bytes
*
* Returned Value:
* None
*
****************************************************************************/
void up_coherent_dcache(uintptr_t addr, size_t len)
{
if (len > 0)
{
/* Perform the operation on the L1 cache */
cp15_coherent_dcache(addr, addr + len);
#ifdef CONFIG_ARCH_L2CACHE
/* If we have an L2 cache, then there more things that need to done */
# warning This is insufficient
#endif
}
}
arch/arm/src/armv7-a/arm_coherent_dcache.c
-85
View File
@@ -1,85 +0,0 @@
/****************************************************************************
* arch/arm/src/armv7-a/up_coherent_dcache.c
*
* Copyright (C) 2014 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdint.h>
#include "cp15_cacheops.h"
#include <nuttx/arch.h>
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_coherent_dcache
*
* Description:
* Ensure that the I and D caches are coherent within specified region
* by cleaning the D cache (i.e., flushing the D cache contents to memory
* and invalidating the I cache. This is typically used when code has been
* written to a memory region, and will be executed.
*
* Input Parameters:
* addr - virtual start address of region
* len - Size of the address region in bytes
*
* Returned Value:
* None
*
****************************************************************************/
void up_coherent_dcache(uintptr_t addr, size_t len)
{
if (len > 0)
{
/* Perform the operation on the L1 cache */
cp15_coherent_dcache(addr, addr + len - 1);
#ifdef CONFIG_ARCH_L2CACHE
/* If we have an L2 cache, then there more things that need to done */
# warning This is insufficient
#endif
}
}
arch/arm/src/armv7-a/arm_mmu.c
+1 -1
View File
@@ -41,7 +41,7 @@
#include <stdint.h> #include <stdint.h>
#include "cache.h" #include "cp15_cacheops.h"
#include "mmu.h" #include "mmu.h"
/**************************************************************************** /****************************************************************************
arch/arm/src/armv7-a/arm_pgalloc.c
+4 -5
View File
@@ -48,7 +48,6 @@
#include <nuttx/arch.h> #include <nuttx/arch.h>
#include <nuttx/addrenv.h> #include <nuttx/addrenv.h>
#include "cache.h"
#include "mmu.h" #include "mmu.h"
#include "pgalloc.h" #include "pgalloc.h"
@@ -105,8 +104,8 @@ static uintptr_t alloc_pgtable(void)
* memory. * memory.
*/ */
arch_flush_dcache((uintptr_t)l2table, up_flush_dcache((uintptr_t)l2table,
(uintptr_t)l2table + MM_PGSIZE); (uintptr_t)l2table + MM_PGSIZE);
#ifndef CONFIG_ARCH_PGPOOL_MAPPING #ifndef CONFIG_ARCH_PGPOOL_MAPPING
/* Restore the scratch section page table entry */ /* Restore the scratch section page table entry */
@@ -297,8 +296,8 @@ uintptr_t pgalloc(uintptr_t brkaddr, unsigned int npages)
* memory. * memory.
*/ */
arch_flush_dcache((uintptr_t)&l2table[index], up_flush_dcache((uintptr_t)&l2table[index],
(uintptr_t)&l2table[index] + sizeof(uint32_t)); (uintptr_t)&l2table[index] + sizeof(uint32_t));
#ifndef CONFIG_ARCH_PGPOOL_MAPPING #ifndef CONFIG_ARCH_PGPOOL_MAPPING
/* Restore the scratch L1 page table entry */ /* Restore the scratch L1 page table entry */
arch/arm/src/armv7-a/arm_physpgaddr.c
+2 -3
View File
@@ -49,7 +49,6 @@
#include "chip.h" #include "chip.h"
#include "mmu.h" #include "mmu.h"
#include "cache.h"
#include "pgalloc.h" #include "pgalloc.h"
@@ -115,8 +114,8 @@ uintptr_t arm_physpgaddr(uintptr_t vaddr)
*/ */
index = (vaddr & SECTION_MASK) >> MM_PGSHIFT; index = (vaddr & SECTION_MASK) >> MM_PGSHIFT;
arch_invalidate_dcache((uintptr_t)&l2table[index], up_invalidate_dcache((uintptr_t)&l2table[index],
(uintptr_t)&l2table[index] + sizeof(uint32_t)); (uintptr_t)&l2table[index] + sizeof(uint32_t));
/* Get the Level 2 page table entry corresponding to this virtual /* Get the Level 2 page table entry corresponding to this virtual
* address. Extract the physical address of the page containing * address. Extract the physical address of the page containing
arch/arm/src/armv7-a/arm_scu.c
-1
View File
@@ -44,7 +44,6 @@
#include "up_arch.h" #include "up_arch.h"
#include "cp15_cacheops.h" #include "cp15_cacheops.h"
#include "sctlr.h" #include "sctlr.h"
#include "cache.h"
#include "scu.h" #include "scu.h"
#ifdef CONFIG_SMP #ifdef CONFIG_SMP
arch/arm/src/armv7-a/cp15_cacheops.h
+101 -9
View File
@@ -193,6 +193,26 @@
#ifdef __ASSEMBLY__ #ifdef __ASSEMBLY__
/************************************************************************************
* Name: cp15_enable_dcache
*
* Description:
* Enable L1 D Cache
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
************************************************************************************/
.macro cp15_enable_dcache, tmp
mrc p15, 0, \tmp, c1, c0, 0 /* Read SCTLR */
orr \tmp, \tmp, #(0x1 << 2) /* Enable D cache */
mcr p15, 0, \tmp, c1, c0, 0 /* Update the SCTLR */
.endm
/************************************************************************************ /************************************************************************************
* Name: cp15_disable_dcache * Name: cp15_disable_dcache
* *
@@ -214,10 +234,10 @@
.endm .endm
/************************************************************************************ /************************************************************************************
* Name: cp15_disable_caches * Name: cp15_enable_icache
* *
* Description: * Description:
* Disable L1 Caches * Enable L1 I Cache
* *
* Input Parameters: * Input Parameters:
* None * None
@@ -227,10 +247,29 @@
* *
************************************************************************************/ ************************************************************************************/
.macro cp15_disable_caches, tmp .macro cp15_enable_icache, tmp
mrc p15, 0, \tmp, c1, c0, 0 /* Read SCTLR */
orr \tmp, \tmp, #(0x1 << 12) /* Enable I cache */
mcr p15, 0, \tmp, c1, c0, 0 /* Update the SCTLR */
.endm
/************************************************************************************
* Name: cp15_disable_icache
*
* Description:
* Disable L1 I Cache
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
************************************************************************************/
.macro cp15_disable_icache, tmp
mrc p15, 0, \tmp, c1, c0, 0 /* Read SCTLR */ mrc p15, 0, \tmp, c1, c0, 0 /* Read SCTLR */
bic \tmp, \tmp, #(0x1 << 12) /* Disable I cache */ bic \tmp, \tmp, #(0x1 << 12) /* Disable I cache */
bic \tmp, \tmp, #(0x1 << 2) /* Disable D cache */
mcr p15, 0, \tmp, c1, c0, 0 /* Update the SCTLR */ mcr p15, 0, \tmp, c1, c0, 0 /* Update the SCTLR */
.endm .endm
@@ -481,11 +520,38 @@
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__
/************************************************************************************
* Name: cp15_enable_dcache
*
* Description:
* Enable L1 D Cache
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
************************************************************************************/
static inline void cp15_enable_dcache(void)
{
__asm__ __volatile__
(
"\tmrc p15, 0, r0, c1, c0, 0\n" /* Read SCTLR */
"\torr r0, r0, #(1 << 2)\n" /* Enable D cache */
"\tmcr p15, 0, r0, c1, c0, 0\n" /* Update the SCTLR */
:
:
: "r0", "memory"
);
}
/************************************************************************************ /************************************************************************************
* Name: cp15_disable_dcache * Name: cp15_disable_dcache
* *
* Description: * Description:
* Disable L1 Caches * Disable L1 D Cache
* *
* Input Parameters: * Input Parameters:
* None * None
@@ -509,10 +575,10 @@ static inline void cp15_disable_dcache(void)
} }
/************************************************************************************ /************************************************************************************
* Name: cp15_disable_caches * Name: cp15_enable_icache
* *
* Description: * Description:
* Disable L1 Caches * Enable L1 I Cache
* *
* Input Parameters: * Input Parameters:
* None * None
@@ -522,13 +588,39 @@ static inline void cp15_disable_dcache(void)
* *
************************************************************************************/ ************************************************************************************/
static inline void cp15_disable_caches(void) static inline void cp15_enable_icache(void)
{
__asm__ __volatile__
(
"\tmrc p15, 0, r0, c1, c0, 0\n" /* Read SCTLR */
"\torr r0, r0, #(1 << 12)\n" /* Enable I cache */
"\tmcr p15, 0, r0, c1, c0, 0\n" /* Update the SCTLR */
:
:
: "r0", "memory"
);
}
/************************************************************************************
* Name: cp15_disable_icache
*
* Description:
* Disable L1 I Cache
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
************************************************************************************/
static inline void cp15_disable_icache(void)
{ {
__asm__ __volatile__ __asm__ __volatile__
( (
"\tmrc p15, 0, r0, c1, c0, 0\n" /* Read SCTLR */ "\tmrc p15, 0, r0, c1, c0, 0\n" /* Read SCTLR */
"\tbic r0, r0, #(1 << 12)\n" /* Disable I cache */ "\tbic r0, r0, #(1 << 12)\n" /* Disable I cache */
"\tbic r0, r0, #(1 << 2)\n" /* Disable D cache */
"\tmcr p15, 0, r0, c1, c0, 0\n" /* Update the SCTLR */ "\tmcr p15, 0, r0, c1, c0, 0\n" /* Update the SCTLR */
: :
: :
arch/arm/src/armv7-m/Kconfig
+2
View File
@@ -89,11 +89,13 @@ config ARMV7M_ICACHE
bool "Use I-Cache" bool "Use I-Cache"
default n default n
depends on ARMV7M_HAVE_ICACHE depends on ARMV7M_HAVE_ICACHE
select ARCH_ICACHE
config ARMV7M_DCACHE config ARMV7M_DCACHE
bool "Use D-Cache" bool "Use D-Cache"
default n default n
depends on ARMV7M_HAVE_DCACHE depends on ARMV7M_HAVE_DCACHE
select ARCH_DCACHE
config ARMV7M_DCACHE_WRITETHROUGH config ARMV7M_DCACHE_WRITETHROUGH
bool "D-Cache Write-Through" bool "D-Cache Write-Through"
arch/arm/src/armv7-m/arch_clean_dcache.c
-149
View File
@@ -1,149 +0,0 @@
/****************************************************************************
* arch/arm/src/armv7-m/arch_clean_dcache.c
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Some logic in this header file derives from the ARM CMSIS core_cm7.h
* header file which has a compatible 3-clause BSD license:
*
* Copyright (c) 2009 - 2014 ARM LIMITED. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name ARM, NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "cache.h"
#if defined(CONFIG_ARMV7M_DCACHE) && !defined(CONFIG_ARMV7M_DCACHE_WRITETHROUGH)
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: arch_clean_dcache
*
* Description:
* Clean the data cache within the specified region by flushing the
* contents of the data cache to memory.
*
* Input Parameters:
* start - virtual start address of region
* end - virtual end address of region + 1
*
* Returned Value:
* None
*
* Assumptions:
* This operation is not atomic. This function assumes that the caller
* has exclusive access to the address range so that no harm is done if
* the operation is pre-empted.
*
****************************************************************************/
void arch_clean_dcache(uintptr_t start, uintptr_t end)
{
uint32_t ccsidr;
uint32_t smask;
uint32_t sshift;
uint32_t ways;
uint32_t wshift;
uint32_t ssize;
uint32_t set;
uint32_t sw;
/* Get the characteristics of the D-Cache */
ccsidr = getreg32(NVIC_CCSIDR);
smask = CCSIDR_SETS(ccsidr); /* (Number of sets) - 1 */
sshift = CCSIDR_LSSHIFT(ccsidr) + 4; /* log2(cache-line-size-in-bytes) */
ways = CCSIDR_WAYS(ccsidr); /* (Number of ways) - 1 */
/* Calculate the bit offset for the way field in the DCCSW register by
* counting the number of leading zeroes. For example:
*
* Number of Value of ways Field
* Ways 'ways' Offset
* 2 1 31
* 4 3 30
* 8 7 29
* ...
*/
wshift = arm_clz(ways) & 0x1f;
/* Clean the D-Cache over the range of addresses */
ssize = (1 << sshift);
start &= ~(ssize - 1);
ARM_DSB();
do
{
int32_t tmpways = ways;
/* Isolate the cache line associated with this address. For example
* if the cache line size is 32 bytes and the cache size is 16KB, then
*
* sshift = 5 : Offset to the beginning of the set field
* smask = 0x007f : Mask of the set field
*/
set = ((uint32_t)start >> sshift) & smask;
/* Clean and invalidate each way for this cacheline */
do
{
sw = ((tmpways << wshift) | (set << sshift));
putreg32(sw, NVIC_DCCSW);
}
while (tmpways--);
/* Increment the address by the size of one cache line. */
start += ssize;
}
while (start < end);
ARM_DSB();
ARM_ISB();
}
#endif /* CONFIG_ARMV7M_DCACHE && !CONFIG_ARMV7M_DCACHE_WRITETHROUGH */
arch/arm/src/armv7-m/arch_clean_dcache_all.c
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@@ -1,129 +0,0 @@
/****************************************************************************
* arch/arm/src/armv7-m/arch_clean_dcache_all.c
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Some logic in this header file derives from the ARM CMSIS core_cm7.h
* header file which has a compatible 3-clause BSD license:
*
* Copyright (c) 2009 - 2014 ARM LIMITED. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name ARM, NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "cache.h"
#if defined(CONFIG_ARMV7M_DCACHE) && !defined(CONFIG_ARMV7M_DCACHE_WRITETHROUGH)
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: arch_clean_dcache_all
*
* Description:
* Clean the entire data cache within the specified region by flushing the
* contents of the data cache to memory.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
* Assumptions:
* This operation is not atomic. This function assumes that the caller
* has exclusive access to the address range so that no harm is done if
* the operation is pre-empted.
*
****************************************************************************/
void arch_clean_dcache_all(void)
{
uint32_t ccsidr;
uint32_t sshift;
uint32_t wshift;
uint32_t sw;
uint32_t sets;
uint32_t ways;
/* Get the characteristics of the D-Cache */
ccsidr = getreg32(NVIC_CCSIDR);
sets = CCSIDR_SETS(ccsidr); /* (Number of sets) - 1 */
sshift = CCSIDR_LSSHIFT(ccsidr) + 4; /* log2(cache-line-size-in-bytes) */
ways = CCSIDR_WAYS(ccsidr); /* (Number of ways) - 1 */
/* Calculate the bit offset for the way field in the DCCSW register by
* counting the number of leading zeroes. For example:
*
* Number of Value of ways Field
* Ways 'ways' Offset
* 2 1 31
* 4 3 30
* 8 7 29
* ...
*/
wshift = arm_clz(ways) & 0x1f;
ARM_DSB();
/* Clean the entire D-Cache */
do
{
int32_t tmpways = ways;
do
{
sw = ((tmpways << wshift) | (sets << sshift));
putreg32(sw, NVIC_DCCSW);
}
while (tmpways--);
}
while (sets--);
ARM_DSB();
ARM_ISB();
}
#endif /* CONFIG_ARMV7M_DCACHE && !CONFIG_ARMV7M_DCACHE_WRITETHROUGH */
arch/arm/src/armv7-m/arch_disable_dcache.c
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@@ -1,130 +0,0 @@
/****************************************************************************
* arch/arm/src/armv7-m/arch_disable_dcache.c
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Some logic in this header file derives from the ARM CMSIS core_cm7.h
* header file which has a compatible 3-clause BSD license:
*
* Copyright (c) 2009 - 2014 ARM LIMITED. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name ARM, NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "cache.h"
#ifdef CONFIG_ARMV7M_DCACHE
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: arch_disable_dcache
*
* Description:
* Disable the D-Cache
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void arch_disable_dcache(void)
{
uint32_t ccsidr;
uint32_t ccr;
uint32_t sshift;
uint32_t wshift;
uint32_t sw;
uint32_t sets;
uint32_t ways;
/* Get the characteristics of the D-Cache */
ccsidr = getreg32(NVIC_CCSIDR);
sets = CCSIDR_SETS(ccsidr); /* (Number of sets) - 1 */
sshift = CCSIDR_LSSHIFT(ccsidr) + 4; /* log2(cache-line-size-in-bytes) */
ways = CCSIDR_WAYS(ccsidr); /* (Number of ways) - 1 */
/* Calculate the bit offset for the way field in the DCCISW register by
* counting the number of leading zeroes. For example:
*
* Number of Value of ways Field
* Ways 'ways' Offset
* 2 1 31
* 4 3 30
* 8 7 29
* ...
*/
wshift = arm_clz(ways) & 0x1f;
ARM_DSB();
/* Disable the D-Cache */
ccr = getreg32(NVIC_CFGCON);
ccr &= ~NVIC_CFGCON_DC;
putreg32(ccr, NVIC_CFGCON);
/* Clean and invalidate the entire D-Cache */
do
{
int32_t tmpways = ways;
do
{
sw = ((tmpways << wshift) | (sets << sshift));
putreg32(sw, NVIC_DCCISW);
}
while (tmpways--);
}
while (sets--);
ARM_DSB();
ARM_ISB();
}
#endif /* CONFIG_ARMV7M_DCACHE */
arch/arm/src/armv7-m/arch_enable_dcache.c
-131
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@@ -1,131 +0,0 @@
/****************************************************************************
* arch/arm/src/armv7-m/arch_enable_dcache.c
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Some logic in this header file derives from the ARM CMSIS core_cm7.h
* header file which has a compatible 3-clause BSD license:
*
* Copyright (c) 2009 - 2014 ARM LIMITED. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name ARM, NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "cache.h"
#ifdef CONFIG_ARMV7M_DCACHE
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: arch_enable_dcache
*
* Description:
* Enable the D-Cache
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void arch_enable_dcache(void)
{
uint32_t ccsidr;
uint32_t ccr;
uint32_t sshift;
uint32_t wshift;
uint32_t sw;
uint32_t sets;
uint32_t ways;
/* Get the characteristics of the D-Cache */
ccsidr = getreg32(NVIC_CCSIDR);
sets = CCSIDR_SETS(ccsidr); /* (Number of sets) - 1 */
sshift = CCSIDR_LSSHIFT(ccsidr) + 4; /* log2(cache-line-size-in-bytes) */
ways = CCSIDR_WAYS(ccsidr); /* (Number of ways) - 1 */
/* Calculate the bit offset for the way field in the DCISW register by
* counting the number of leading zeroes. For example:
*
* Number of Value of ways Field
* Ways 'ways' Offset
* 2 1 31
* 4 3 30
* 8 7 29
* ...
*/
wshift = arm_clz(ways) & 0x1f;
/* Invalidate the entire D-Cache */
ARM_DSB();
do
{
int32_t tmpways = ways;
do
{
sw = ((tmpways << wshift) | (sets << sshift));
putreg32(sw, NVIC_DCISW);
}
while (tmpways--);
}
while (sets--);
ARM_DSB();
/* Enable the D-Cache */
ccr = getreg32(NVIC_CFGCON);
ccr |= NVIC_CFGCON_DC;
putreg32(ccr, NVIC_CFGCON);
ARM_DSB();
ARM_ISB();
}
#endif /* CONFIG_ARMV7M_DCACHE */
arch/arm/src/armv7-m/arch_flush_dcache.c
-149
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@@ -1,149 +0,0 @@
/****************************************************************************
* arch/arm/src/armv7-m/arch_flush_dcache.c
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Some logic in this header file derives from the ARM CMSIS core_cm7.h
* header file which has a compatible 3-clause BSD license:
*
* Copyright (c) 2009 - 2014 ARM LIMITED. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name ARM, NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "cache.h"
#if defined(CONFIG_ARMV7M_DCACHE) && !defined(CONFIG_ARMV7M_DCACHE_WRITETHROUGH)
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: arch_flush_dcache
*
* Description:
* Flush the data cache within the specified region by cleaning and
* invalidating the D cache.
*
* Input Parameters:
* start - virtual start address of region
* end - virtual end address of region + 1
*
* Returned Value:
* None
*
* Assumptions:
* This operation is not atomic. This function assumes that the caller
* has exclusive access to the address range so that no harm is done if
* the operation is pre-empted.
*
****************************************************************************/
void arch_flush_dcache(uintptr_t start, uintptr_t end)
{
uint32_t ccsidr;
uint32_t smask;
uint32_t sshift;
uint32_t ways;
uint32_t wshift;
uint32_t ssize;
uint32_t set;
uint32_t sw;
/* Get the characteristics of the D-Cache */
ccsidr = getreg32(NVIC_CCSIDR);
smask = CCSIDR_SETS(ccsidr); /* (Number of sets) - 1 */
sshift = CCSIDR_LSSHIFT(ccsidr) + 4; /* log2(cache-line-size-in-bytes) */
ways = CCSIDR_WAYS(ccsidr); /* (Number of ways) - 1 */
/* Calculate the bit offset for the way field in the DCCISW register by
* counting the number of leading zeroes. For example:
*
* Number of Value of ways Field
* Ways 'ways' Offset
* 2 1 31
* 4 3 30
* 8 7 29
* ...
*/
wshift = arm_clz(ways) & 0x1f;
/* Clean and invalidate the D-Cache over the range of addresses */
ssize = (1 << sshift);
start &= ~(ssize - 1);
ARM_DSB();
do
{
int32_t tmpways = ways;
/* Isolate the cache line associated with this address. For example
* if the cache line size is 32 bytes and the cache size is 16KB, then
*
* sshift = 5 : Offset to the beginning of the set field
* smask = 0x007f : Mask of the set field
*/
set = ((uint32_t)start >> sshift) & smask;
/* Clean and invalidate each way for this cacheline */
do
{
sw = ((tmpways << wshift) | (set << sshift));
putreg32(sw, NVIC_DCCISW);
}
while (tmpways--);
/* Increment the address by the size of one cache line. */
start += ssize;
}
while (start < end);
ARM_DSB();
ARM_ISB();
}
#endif /* CONFIG_ARMV7M_DCACHE && !CONFIG_ARMV7M_DCACHE_WRITETHROUGH */
arch/arm/src/armv7-m/arch_flush_dcache_all.c
-128
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@@ -1,128 +0,0 @@
/****************************************************************************
* arch/arm/src/armv7-m/arch_flush_dcache_all.c
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Some logic in this header file derives from the ARM CMSIS core_cm7.h
* header file which has a compatible 3-clause BSD license:
*
* Copyright (c) 2009 - 2014 ARM LIMITED. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name ARM, NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "cache.h"
#if defined(CONFIG_ARMV7M_DCACHE) && !defined(CONFIG_ARMV7M_DCACHE_WRITETHROUGH)
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: arch_flush_dcache_all
*
* Description:
* Flush the entire data cache by cleaning and invalidating the D cache.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
* Assumptions:
* This operation is not atomic. This function assumes that the caller
* has exclusive access to the address range so that no harm is done if
* the operation is pre-empted.
*
****************************************************************************/
void arch_flush_dcache_all(void)
{
uint32_t ccsidr;
uint32_t sshift;
uint32_t wshift;
uint32_t sw;
uint32_t sets;
uint32_t ways;
/* Get the characteristics of the D-Cache */
ccsidr = getreg32(NVIC_CCSIDR);
sets = CCSIDR_SETS(ccsidr); /* (Number of sets) - 1 */
sshift = CCSIDR_LSSHIFT(ccsidr) + 4; /* log2(cache-line-size-in-bytes) */
ways = CCSIDR_WAYS(ccsidr); /* (Number of ways) - 1 */
/* Calculate the bit offset for the way field in the DCCISW register by
* counting the number of leading zeroes. For example:
*
* Number of Value of ways Field
* Ways 'ways' Offset
* 2 1 31
* 4 3 30
* 8 7 29
* ...
*/
wshift = arm_clz(ways) & 0x1f;
ARM_DSB();
/* Clean and invalidate the entire D-Cache */
do
{
int32_t tmpways = ways;
do
{
sw = ((tmpways << wshift) | (sets << sshift));
putreg32(sw, NVIC_DCCISW);
}
while (tmpways--);
}
while (sets--);
ARM_DSB();
ARM_ISB();
}
#endif /* CONFIG_ARMV7M_DCACHE && !CONFIG_ARMV7M_DCACHE_WRITETHROUGH */
arch/arm/src/armv7-m/arch_invalidate_dcache.c
-217
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@@ -1,217 +0,0 @@
/****************************************************************************
* arch/arm/src/armv7-m/arch_invalidate_dcache.c
*
* Copyright (C) 2015, 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* Bob Feretich <bob.feretich@rafresearch.com>
*
* Some logic in this header file derives from the ARM CMSIS core_cm7.h
* header file which has a compatible 3-clause BSD license:
*
* Copyright (c) 2009 - 2014 ARM LIMITED. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name ARM, NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "cache.h"
#ifdef CONFIG_ARMV7M_DCACHE
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: arch_invalidate_dcache
*
* Description:
* Invalidate the data cache within the specified region; we will be
* performing a DMA operation in this region and we want to purge old data
* in the cache. Note that this function invalidates all cache ways
* in sets that could be associated with the address range, regardless of
* whether the address range is contained in the cache or not.
*
* Input Parameters:
* start - virtual start address of region
* end - virtual end address of region + 1
*
* Returned Value:
* None
*
* Assumptions:
* This operation is not atomic. This function assumes that the caller
* has exclusive access to the address range so that no harm is done if
* the operation is pre-empted.
*
****************************************************************************/
void arch_invalidate_dcache(uintptr_t start, uintptr_t end)
{
uint32_t ccsidr;
uint32_t smask;
uint32_t sshift;
uint32_t ways;
uint32_t wshift;
uint32_t ssize;
uint32_t set;
uint32_t sw;
/* Get the characteristics of the D-Cache */
ccsidr = getreg32(NVIC_CCSIDR);
smask = CCSIDR_SETS(ccsidr); /* (Number of sets) - 1 */
sshift = CCSIDR_LSSHIFT(ccsidr) + 4; /* log2(cache-line-size-in-bytes) */
ways = CCSIDR_WAYS(ccsidr); /* (Number of ways) - 1 */
/* Calculate the bit offset for the way field in the DCISW register by
* counting the number of leading zeroes. For example:
*
* Number of Value of ways Field
* Ways 'ways' Offset
* 2 1 31
* 4 3 30
* 8 7 29
* ...
*/
wshift = arm_clz(ways) & 0x1f;
/* Invalidate the D-Cache over the range of addresses */
ssize = (1 << sshift);
start &= ~(ssize - 1);
ARM_DSB();
do
{
int32_t tmpways = ways;
/* Isolate the cache line associated with this address. For example
* if the cache line size is 32 bytes and the cache size is 16KB, then
*
* sshift = 5 : Offset to the beginning of the set field
* smask = 0x007f : Mask of the set field
*/
set = ((uint32_t)start >> sshift) & smask;
/* Clean and invalidate each way for this cacheline */
do
{
sw = ((tmpways << wshift) | (set << sshift));
putreg32(sw, NVIC_DCISW);
}
while (tmpways--);
/* Increment the address by the size of one cache line. */
start += ssize;
}
while (start < end);
ARM_DSB();
ARM_ISB();
}
/****************************************************************************
* Name: arch_invalidate_dcache_by_addr
*
* Description:
* Invalidate the data cache within the specified region; we will be
* performing a DMA operation in this region and we want to purge old data
* in the cache. Note that this function only invalidates cache sets that
* contain data from this address range.
*
* Input Parameters:
* start - virtual start address of region
* end - virtual end address of region + 1
*
* Returned Value:
* None
*
* Assumptions:
* This operation is not atomic. This function assumes that the caller
* has exclusive access to the address range so that no harm is done if
* the operation is pre-empted.
*
****************************************************************************/
void arch_invalidate_dcache_by_addr(uintptr_t start, uintptr_t end)
{
uint32_t ccsidr;
uint32_t sshift;
uint32_t ssize;
/* Get the characteristics of the D-Cache */
ccsidr = getreg32(NVIC_CCSIDR);
sshift = CCSIDR_LSSHIFT(ccsidr) + 4; /* log2(cache-line-size-in-bytes) */
/* Invalidate the D-Cache containing this range of addresses */
ssize = (1 << sshift);
/* Round down the start address to the nearest cache line boundary.
*
* sshift = 5 : Offset to the beginning of the set field
* (ssize - 1) = 0x007f : Mask of the set field
*/
start &= ~(ssize - 1);
ARM_DSB();
do
{
/* The below store causes the cache to check its directory and
* determine if this address is contained in the cache. If so, it
* invalidate that cache line. Only the cache way containing the
* address is invalidated. If the address is not in the cache, then
* nothing is invalidated.
*/
putreg32(start, NVIC_DCIMVAC);
/* Increment the address by the size of one cache line. */
start += ssize;
}
while (start < end);
ARM_DSB();
ARM_ISB();
}
#endif /* CONFIG_ARMV7M_DCACHE */
arch/arm/src/armv7-m/arch_invalidate_dcache_all.c
-123
View File
@@ -1,123 +0,0 @@
/****************************************************************************
* arch/arm/src/armv7-m/arch_invalidate_dcache_all.c
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Some logic in this header file derives from the ARM CMSIS core_cm7.h
* header file which has a compatible 3-clause BSD license:
*
* Copyright (c) 2009 - 2014 ARM LIMITED. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name ARM, NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "cache.h"
#ifdef CONFIG_ARMV7M_DCACHE
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: arch_invalidate_dcache_all
*
* Description:
* Invalidate the entire contents of D cache.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void arch_invalidate_dcache_all(void)
{
uint32_t ccsidr;
uint32_t sshift;
uint32_t wshift;
uint32_t sw;
uint32_t sets;
uint32_t ways;
/* Get the characteristics of the D-Cache */
ccsidr = getreg32(NVIC_CCSIDR);
sets = CCSIDR_SETS(ccsidr); /* (Number of sets) - 1 */
sshift = CCSIDR_LSSHIFT(ccsidr) + 4; /* log2(cache-line-size-in-bytes) */
ways = CCSIDR_WAYS(ccsidr); /* (Number of ways) - 1 */
/* Calculate the bit offset for the way field in the DCISW register by
* counting the number of leading zeroes. For example:
*
* Number of Value of ways Field
* Ways 'ways' Offset
* 2 1 31
* 4 3 30
* 8 7 29
* ...
*/
wshift = arm_clz(ways) & 0x1f;
ARM_DSB();
/* Invalidate the entire D-Cache */
do
{
int32_t tmpways = ways;
do
{
sw = ((tmpways << wshift) | (sets << sshift));
putreg32(sw, NVIC_DCISW);
}
while (tmpways--);
}
while (sets--);
ARM_DSB();
ARM_ISB();
}
#endif /* CONFIG_ARMV7M_DCACHE */
arch/arm/src/armv7-m/cache.h
-507
View File
File diff suppressed because it is too large Load Diff
arch/arm/src/armv7-m/mpu.h
-2
View File
@@ -268,7 +268,6 @@ static inline void mpu_control(bool enable, bool hfnmiena, bool privdefena)
* *
****************************************************************************/ ****************************************************************************/
#if defined(CONFIG_ARMV7M_HAVE_ICACHE) || defined(CONFIG_ARMV7M_DCACHE)
static inline void mpu_priv_stronglyordered(uintptr_t base, size_t size) static inline void mpu_priv_stronglyordered(uintptr_t base, size_t size)
{ {
unsigned int region = mpu_allocregion(); unsigned int region = mpu_allocregion();
@@ -300,7 +299,6 @@ static inline void mpu_priv_stronglyordered(uintptr_t base, size_t size)
MPU_RASR_AP_RWNO; /* P:RW U:None */ MPU_RASR_AP_RWNO; /* P:RW U:None */
putreg32(regval, MPU_RASR); putreg32(regval, MPU_RASR);
} }
#endif
/**************************************************************************** /****************************************************************************
* Name: mpu_user_flash * Name: mpu_user_flash
arch/arm/src/armv7-m/up_cache.c
+832
View File
File diff suppressed because it is too large Load Diff
arch/arm/src/armv7-m/up_coherent_dcache.c
-87
View File
@@ -1,87 +0,0 @@
/****************************************************************************
* arch/arm/src/armv7-m/up_coherent_dcache.c
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdint.h>
#include "cache.h"
#include <nuttx/arch.h>
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_coherent_dcache
*
* Description:
* Ensure that the I and D caches are coherent within specified region
* by cleaning the D cache (i.e., flushing the D cache contents to memory
* and invalidating the I cache. This is typically used when code has been
* written to a memory region, and will be executed.
*
* Input Parameters:
* addr - virtual start address of region
* len - Size of the address region in bytes
*
* Returned Value:
* None
*
****************************************************************************/
void up_coherent_dcache(uintptr_t addr, size_t len)
{
uintptr_t end;
if (len > 0)
{
/* Flush any dirtcy D-Cache lines to memory */
end = addr + len;
arch_clean_dcache(addr, end);
UNUSED(end);
/* Invalidate the entire I-Cache */
arch_invalidate_icache_all();
}
}
arch/arm/src/armv7-r/Kconfig
-23
View File
@@ -26,29 +26,6 @@ config ARMV7R_MEMINIT
the memory initialization first, then explicitly call the memory initialization first, then explicitly call
arm_data_initialize(). arm_data_initialize().
config ARMV7R_HAVE_ICACHE
bool
default n
config ARMV7R_HAVE_DCACHE
bool
default n
config ARMV7R_ICACHE
bool "Use I-Cache"
default n
depends on ARMV7R_HAVE_ICACHE
config ARMV7R_DCACHE
bool "Use D-Cache"
default n
depends on ARMV7R_HAVE_DCACHE
config ARMV7R_DCACHE_WRITETHROUGH
bool "D-Cache Write-Through"
default n
depends on ARMV7R_DCACHE
config ARMV7R_HAVE_L2CC config ARMV7R_HAVE_L2CC
bool bool
default n default n
arch/arm/src/armv7-a/cache.h → arch/arm/src/armv7-r/arm_cache.c
+130 -42
View File
@@ -1,7 +1,7 @@
/************************************************************************************ /****************************************************************************
* arch/arm/src/armv7-a/cache.h * arch/arm/src/armv7-r/arm_cache.c
* *
* Copyright (C) 2014 Gregory Nutt. All rights reserved. * Copyright (C) 2015, 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org> * Author: Gregory Nutt <gnutt@nuttx.org>
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
@@ -31,24 +31,22 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE. * POSSIBILITY OF SUCH DAMAGE.
* *
************************************************************************************/ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_ARMV7_A_CACHE_H /****************************************************************************
#define __ARCH_ARM_SRC_ARMV7_A_CACHE_H
/************************************************************************************
* Included Files * Included Files
************************************************************************************/ ****************************************************************************/
#include <nuttx/config.h> #include <nuttx/config.h>
#include <nuttx/cache.h>
#include <nuttx/irq.h> #include <nuttx/irq.h>
#include "cp15_cacheops.h" #include "cp15_cacheops.h"
#include "l2cc.h" #include "l2cc.h"
/************************************************************************************ /****************************************************************************
* Pre-processor Definitions * Pre-processor Definitions
************************************************************************************/ ****************************************************************************/
/* Intrinsics are used in these inline functions */ /* Intrinsics are used in these inline functions */
@@ -60,14 +58,12 @@
#define ARM_ISB() arm_isb(15) #define ARM_ISB() arm_isb(15)
#define ARM_DMB() arm_dmb(15) #define ARM_DMB() arm_dmb(15)
/************************************************************************************ /****************************************************************************
* Inline Functions * Public Functions
************************************************************************************/ ****************************************************************************/
#ifndef __ASSEMBLY__
/**************************************************************************** /****************************************************************************
* Name: arch_invalidate_dcache * Name: up_invalidate_dcache
* *
* Description: * Description:
* Invalidate the data cache within the specified region; we will be * Invalidate the data cache within the specified region; we will be
@@ -88,14 +84,14 @@
* *
****************************************************************************/ ****************************************************************************/
static inline void arch_invalidate_dcache(uintptr_t start, uintptr_t end) void up_invalidate_dcache(uintptr_t start, uintptr_t end)
{ {
cp15_invalidate_dcache(start, end); cp15_invalidate_dcache(start, end);
l2cc_invalidate(start, end); l2cc_invalidate(start, end);
} }
/**************************************************************************** /****************************************************************************
* Name: arch_invalidate_dcache_all * Name: up_invalidate_dcache_all
* *
* Description: * Description:
* Invalidate the entire contents of D cache. * Invalidate the entire contents of D cache.
@@ -111,7 +107,7 @@ static inline void arch_invalidate_dcache(uintptr_t start, uintptr_t end)
* *
****************************************************************************/ ****************************************************************************/
static inline void arch_invalidate_dcache_all(void) void up_invalidate_dcache_all(void)
{ {
#ifdef CONFIG_ARCH_L2CACHE #ifdef CONFIG_ARCH_L2CACHE
irqstate_t flags = enter_critical_section(); irqstate_t flags = enter_critical_section();
@@ -123,11 +119,12 @@ static inline void arch_invalidate_dcache_all(void)
#endif #endif
} }
/************************************************************************************ /****************************************************************************
* Name: arch_invalidate_icache * Name: up_invalidate_icache_all
* *
* Description: * Description:
* Invalidate all instruction caches to PoU, also flushes branch target cache * Invalidate all instruction caches to PoU, also flushes branch target
* cache
* *
* Input Parameters: * Input Parameters:
* None * None
@@ -135,12 +132,15 @@ static inline void arch_invalidate_dcache_all(void)
* Returned Value: * Returned Value:
* None * None
* *
************************************************************************************/ ****************************************************************************/
#define arch_invalidate_icache() cp15_invalidate_icache() void up_invalidate_icache_all(void)
{
cp15_invalidate_icache();
}
/**************************************************************************** /****************************************************************************
* Name: arch_clean_dcache * Name: up_clean_dcache
* *
* Description: * Description:
* Clean the data cache within the specified region by flushing the * Clean the data cache within the specified region by flushing the
@@ -160,14 +160,14 @@ static inline void arch_invalidate_dcache_all(void)
* *
****************************************************************************/ ****************************************************************************/
static inline void arch_clean_dcache(uintptr_t start, uintptr_t end) void up_clean_dcache(uintptr_t start, uintptr_t end)
{ {
cp15_clean_dcache(start, end); cp15_clean_dcache(start, end);
l2cc_clean(start, end); l2cc_clean(start, end);
} }
/**************************************************************************** /****************************************************************************
* Name: arch_flush_dcache * Name: up_flush_dcache
* *
* Description: * Description:
* Flush the data cache within the specified region by cleaning and * Flush the data cache within the specified region by cleaning and
@@ -187,32 +187,120 @@ static inline void arch_clean_dcache(uintptr_t start, uintptr_t end)
* *
****************************************************************************/ ****************************************************************************/
static inline void arch_flush_dcache(uintptr_t start, uintptr_t end) void up_flush_dcache(uintptr_t start, uintptr_t end)
{ {
cp15_flush_dcache(start, end); cp15_flush_dcache(start, end);
l2cc_flush(start, end); l2cc_flush(start, end);
} }
/**************************************************************************** /****************************************************************************
* Public Data * Name: up_enable_icache
*
* Description:
* Enable the I-Cache
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/ ****************************************************************************/
#ifdef __cplusplus void up_enable_icache(void)
#define EXTERN extern "C"
extern "C"
{ {
#else cp15_enable_icache();
#define EXTERN extern }
#endif
/**************************************************************************** /****************************************************************************
* Public Function Prototypes * Name: up_disable_icache
*
* Description:
* Disable the I-Cache
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/ ****************************************************************************/
#undef EXTERN void up_disable_icache(void)
#ifdef __cplusplus {
cp15_disable_icache();
} }
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_ARMV7_A_CACHE_H */ /****************************************************************************
* Name: up_enable_dcache
*
* Description:
* Enable the D-Cache
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void up_enable_dcache(void)
{
cp15_enable_dcache();
l2cc_enable();
}
/****************************************************************************
* Name: up_disable_dcache
*
* Description:
* Disable the D-Cache
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void up_disable_dcache(void)
{
cp15_disable_dcache();
l2cc_disable();
}
/****************************************************************************
* Name: up_coherent_dcache
*
* Description:
* Ensure that the I and D caches are coherent within specified region
* by cleaning the D cache (i.e., flushing the D cache contents to memory
* and invalidating the I cache. This is typically used when code has been
* written to a memory region, and will be executed.
*
* Input Parameters:
* addr - virtual start address of region
* len - Size of the address region in bytes
*
* Returned Value:
* None
*
****************************************************************************/
void up_coherent_dcache(uintptr_t addr, size_t len)
{
if (len > 0)
{
/* Perform the operation on the L1 cache */
cp15_coherent_dcache(addr, addr + len);
#ifdef CONFIG_ARCH_L2CACHE
/* If we have an L2 cache, then there more things that need to done */
# warning This is insufficient
#endif
}
}
arch/arm/src/armv7-r/arm_coherent_dcache.c
-97
View File
@@ -1,97 +0,0 @@
/****************************************************************************
* arch/arm/src/armv7-r/up_coherent_dcache.c
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdint.h>
#include "cp15_cacheops.h"
#include <nuttx/arch.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_coherent_dcache
*
* Description:
* Ensure that the I and D caches are coherent within specified region
* by cleaning the D cache (i.e., flushing the D cache contents to memory
* and invalidating the I cache. This is typically used when code has been
* written to a memory region, and will be executed.
*
* Input Parameters:
* addr - virtual start address of region
* len - Size of the address region in bytes
*
* Returned Value:
* None
*
****************************************************************************/
void up_coherent_dcache(uintptr_t addr, size_t len)
{
if (len > 0)
{
/* Perform the operation on the L1 cache */
cp15_coherent_dcache(addr, addr + len - 1);
#ifdef CONFIG_ARCH_L2CACHE
/* If we have an L2 cache, then there more things that need to done */
# warning This is insufficient
#endif
}
}
arch/arm/src/armv7-r/arm_head.S
+1 -1
View File
@@ -467,7 +467,7 @@ arm_data_initialize:
adr r3, ..Lramfunc adr r3, ..Lramfunc
ldmia r3, {r0, r1} ldmia r3, {r0, r1}
ldr r3, =arch_clean_dcache ldr r3, =up_clean_dcache
b r3 b r3
#else #else
/* Otherwise return to the caller */ /* Otherwise return to the caller */
arch/arm/src/armv7-r/cp15_cacheops.h
+101 -9
View File
@@ -201,6 +201,26 @@
#ifdef __ASSEMBLY__ #ifdef __ASSEMBLY__
/************************************************************************************
* Name: cp15_enable_dcache
*
* Description:
* Enable L1 D Cache
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
************************************************************************************/
.macro cp15_enable_dcache, tmp
mrc p15, 0, \tmp, c1, c0, 0 /* Read SCTLR */
orr \tmp, \tmp, #(0x1 << 2) /* Enable D cache */
mcr p15, 0, \tmp, c1, c0, 0 /* Update the SCTLR */
.endm
/************************************************************************************ /************************************************************************************
* Name: cp15_disable_dcache * Name: cp15_disable_dcache
* *
@@ -222,10 +242,10 @@
.endm .endm
/************************************************************************************ /************************************************************************************
* Name: cp15_disable_caches * Name: cp15_enable_icache
* *
* Description: * Description:
* Disable L1 Caches * Enable L1 I Cache
* *
* Input Parameters: * Input Parameters:
* None * None
@@ -235,10 +255,29 @@
* *
************************************************************************************/ ************************************************************************************/
.macro cp15_disable_caches, tmp .macro cp15_enable_icache, tmp
mrc p15, 0, \tmp, c1, c0, 0 /* Read SCTLR */
orr \tmp, \tmp, #(0x1 << 12) /* Enable I cache */
mcr p15, 0, \tmp, c1, c0, 0 /* Update the SCTLR */
.endm
/************************************************************************************
* Name: cp15_disable_icache
*
* Description:
* Disable L1 I Cache
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
************************************************************************************/
.macro cp15_disable_icache, tmp
mrc p15, 0, \tmp, c1, c0, 0 /* Read SCTLR */ mrc p15, 0, \tmp, c1, c0, 0 /* Read SCTLR */
bic \tmp, \tmp, #(0x1 << 12) /* Disable I cache */ bic \tmp, \tmp, #(0x1 << 12) /* Disable I cache */
bic \tmp, \tmp, #(0x1 << 2) /* Disable D cache */
mcr p15, 0, \tmp, c1, c0, 0 /* Update the SCTLR */ mcr p15, 0, \tmp, c1, c0, 0 /* Update the SCTLR */
.endm .endm
@@ -489,11 +528,38 @@
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__
/************************************************************************************
* Name: cp15_enable_dcache
*
* Description:
* Enable L1 D Cache
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
************************************************************************************/
static inline void cp15_enable_dcache(void)
{
__asm__ __volatile__
(
"\tmrc p15, 0, r0, c1, c0, 0\n" /* Read SCTLR */
"\torr r0, r0, #(1 << 2)\n" /* Enable D cache */
"\tmcr p15, 0, r0, c1, c0, 0\n" /* Update the SCTLR */
:
:
: "r0", "memory"
);
}
/************************************************************************************ /************************************************************************************
* Name: cp15_disable_dcache * Name: cp15_disable_dcache
* *
* Description: * Description:
* Disable L1 Caches * Disable L1 D Cache
* *
* Input Parameters: * Input Parameters:
* None * None
@@ -517,10 +583,10 @@ static inline void cp15_disable_dcache(void)
} }
/************************************************************************************ /************************************************************************************
* Name: cp15_disable_caches * Name: cp15_enable_icache
* *
* Description: * Description:
* Disable L1 Caches * Enable L1 I Cache
* *
* Input Parameters: * Input Parameters:
* None * None
@@ -530,13 +596,39 @@ static inline void cp15_disable_dcache(void)
* *
************************************************************************************/ ************************************************************************************/
static inline void cp15_disable_caches(void) static inline void cp15_enable_icache(void)
{
__asm__ __volatile__
(
"\tmrc p15, 0, r0, c1, c0, 0\n" /* Read SCTLR */
"\torr r0, r0, #(1 << 12)\n" /* Enable I cache */
"\tmcr p15, 0, r0, c1, c0, 0\n" /* Update the SCTLR */
:
:
: "r0", "memory"
);
}
/************************************************************************************
* Name: cp15_disable_icache
*
* Description:
* Disable L1 I Cache
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
************************************************************************************/
static inline void cp15_disable_icache(void)
{ {
__asm__ __volatile__ __asm__ __volatile__
( (
"\tmrc p15, 0, r0, c1, c0, 0\n" /* Read SCTLR */ "\tmrc p15, 0, r0, c1, c0, 0\n" /* Read SCTLR */
"\tbic r0, r0, #(1 << 12)\n" /* Disable I cache */ "\tbic r0, r0, #(1 << 12)\n" /* Disable I cache */
"\tbic r0, r0, #(1 << 2)\n" /* Disable D cache */
"\tmcr p15, 0, r0, c1, c0, 0\n" /* Update the SCTLR */ "\tmcr p15, 0, r0, c1, c0, 0\n" /* Update the SCTLR */
: :
: :
arch/arm/src/armv7-r/mpu.h
-3
View File
@@ -49,7 +49,6 @@
# include <debug.h> # include <debug.h>
# include "up_arch.h" # include "up_arch.h"
# include "cache.h"
# include "sctlr.h" # include "sctlr.h"
# include "cp15.h" # include "cp15.h"
#endif #endif
@@ -410,7 +409,6 @@ static inline void mpu_control(bool enable)
* *
****************************************************************************/ ****************************************************************************/
#if defined(CONFIG_ARMV7R_HAVE_ICACHE) || defined(CONFIG_ARMV7R_DCACHE)
static inline void mpu_priv_stronglyordered(uintptr_t base, size_t size) static inline void mpu_priv_stronglyordered(uintptr_t base, size_t size)
{ {
unsigned int region = mpu_allocregion(); unsigned int region = mpu_allocregion();
@@ -444,7 +442,6 @@ static inline void mpu_priv_stronglyordered(uintptr_t base, size_t size)
((uint32_t)subregions << MPU_RASR_SRD_SHIFT); /* Sub-regions */ ((uint32_t)subregions << MPU_RASR_SRD_SHIFT); /* Sub-regions */
mpu_set_drsr(regval); mpu_set_drsr(regval);
} }
#endif
/**************************************************************************** /****************************************************************************
* Name: mpu_user_flash * Name: mpu_user_flash
arch/arm/src/imx6/Make.defs
+1 -5
View File
@@ -123,11 +123,7 @@ CMN_CSRCS += arm_virtpgaddr.c
endif endif
endif endif
ifeq ($(CONFIG_ELF),y) CMN_CSRCS += arm_cache.c
CMN_CSRCS += arm_coherent_dcache.c
else ifeq ($(CONFIG_MODULE),y)
CMN_CSRCS += arm_coherent_dcache.c
endif
ifeq ($(CONFIG_ARCH_FPU),y) ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += arm_savefpu.S arm_restorefpu.S CMN_ASRCS += arm_savefpu.S arm_restorefpu.S
arch/arm/src/imx6/imx_boot.c
+4 -4
View File
@@ -43,6 +43,7 @@
#include <assert.h> #include <assert.h>
#include <debug.h> #include <debug.h>
#include <nuttx/cache.h>
#ifdef CONFIG_PAGING #ifdef CONFIG_PAGING
# include <nuttx/page.h> # include <nuttx/page.h>
#endif #endif
@@ -53,7 +54,6 @@
#include "arm.h" #include "arm.h"
#include "mmu.h" #include "mmu.h"
#include "scu.h" #include "scu.h"
#include "cache.h"
#include "fpu.h" #include "fpu.h"
#include "up_internal.h" #include "up_internal.h"
#include "up_arch.h" #include "up_arch.h"
@@ -287,8 +287,8 @@ static void imx_copyvectorblock(void)
#else #else
/* Flush the DCache to assure that the vector data is in physical RAM */ /* Flush the DCache to assure that the vector data is in physical RAM */
arch_clean_dcache((uintptr_t)IMX_VECTOR_VSRAM, up_clean_dcache((uintptr_t)IMX_VECTOR_VSRAM,
(uintptr_t)IMX_VECTOR_VSRAM + imx_vectorsize()); (uintptr_t)IMX_VECTOR_VSRAM + imx_vectorsize());
#endif #endif
} }
@@ -453,7 +453,7 @@ void arm_boot(void)
* be available when fetched into the I-Cache. * be available when fetched into the I-Cache.
*/ */
arch_clean_dcache((uintptr_t)&_sramfuncs, (uintptr_t)&_eramfuncs) up_clean_dcache((uintptr_t)&_sramfuncs, (uintptr_t)&_eramfuncs)
PROGRESS('F'); PROGRESS('F');
#endif #endif
arch/arm/src/imxrt/Make.defs
+1 -8
View File
@@ -79,14 +79,7 @@ ifeq ($(CONFIG_STACK_COLORATION),y)
CMN_CSRCS += up_checkstack.c CMN_CSRCS += up_checkstack.c
endif endif
ifeq ($(CONFIG_ARMV7M_DCACHE),y) CMN_CSRCS += up_cache.c
CMN_CSRCS += arch_enable_dcache.c arch_disable_dcache.c
CMN_CSRCS += arch_invalidate_dcache.c arch_invalidate_dcache_all.c
ifneq ($(CONFIG_ARMV7M_DCACHE_WRITETHROUGH),y)
CMN_CSRCS += arch_clean_dcache.c arch_clean_dcache_all.c
CMN_CSRCS += arch_flush_dcache.c arch_flush_dcache_all.c
endif
endif
ifeq ($(CONFIG_ARCH_FPU),y) ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += up_fpu.S CMN_ASRCS += up_fpu.S
arch/arm/src/imxrt/imxrt_edma.c
+8 -9
View File
@@ -58,7 +58,6 @@
#include <nuttx/arch.h> #include <nuttx/arch.h>
#include "up_arch.h" #include "up_arch.h"
#include "cache.h"
#include "up_internal.h" #include "up_internal.h"
#include "sched/sched.h" #include "sched/sched.h"
@@ -1105,8 +1104,8 @@ int imxrt_dmach_xfrsetup(DMACH_HANDLE *handle,
/* Clean cache associated with the previous TCD memory */ /* Clean cache associated with the previous TCD memory */
arch_clean_dcache((uintptr_t)prev, up_clean_dcache((uintptr_t)prev,
(uintptr_t)prev + sizeof(struct imxrt_edmatcd_s)); (uintptr_t)prev + sizeof(struct imxrt_edmatcd_s));
/* Check if the TCD block in the DMA channel registers is the same as /* Check if the TCD block in the DMA channel registers is the same as
* the previous previous TCD. This can happen if the previous TCD was * the previous previous TCD. This can happen if the previous TCD was
@@ -1130,8 +1129,8 @@ int imxrt_dmach_xfrsetup(DMACH_HANDLE *handle,
/* Clean cache associated with the TCD memory */ /* Clean cache associated with the TCD memory */
arch_clean_dcache((uintptr_t)tcd, up_clean_dcache((uintptr_t)tcd,
(uintptr_t)tcd + sizeof(struct imxrt_edmatcd_s)); (uintptr_t)tcd + sizeof(struct imxrt_edmatcd_s));
#else #else
/* Scatter/gather DMA is NOT supported */ /* Scatter/gather DMA is NOT supported */
@@ -1168,8 +1167,8 @@ int imxrt_dmach_xfrsetup(DMACH_HANDLE *handle,
* is one. * is one.
*/ */
arch_invalidate_dcache((uintptr_t)config->daddr, up_invalidate_dcache((uintptr_t)config->daddr,
(uintptr_t)config->daddr + config->nbytes); (uintptr_t)config->daddr + config->nbytes);
} }
/* Check for an Tx (peripheral-to-memory/memory-to-memory) DMA transfer */ /* Check for an Tx (peripheral-to-memory/memory-to-memory) DMA transfer */
@@ -1183,8 +1182,8 @@ int imxrt_dmach_xfrsetup(DMACH_HANDLE *handle,
*/ */
#warning Missing logic #warning Missing logic
arch_clean_dcache((uintptr_t)config->saddr, up_clean_dcache((uintptr_t)config->saddr,
(uintptr_t)config->saddr + config->nbytes); (uintptr_t)config->saddr + config->nbytes);
} }
dmach->state = IMXRT_DMA_CONFIGURED; dmach->state = IMXRT_DMA_CONFIGURED;
arch/arm/src/imxrt/imxrt_enet.c
+8 -9
View File
@@ -64,7 +64,6 @@
#endif #endif
#include "up_arch.h" #include "up_arch.h"
#include "cache.h"
#include "chip.h" #include "chip.h"
#include "imxrt_config.h" #include "imxrt_config.h"
#include "chip/imxrt_enet.h" #include "chip/imxrt_enet.h"
@@ -502,8 +501,8 @@ static int imxrt_transmit(FAR struct imxrt_driver_s *priv)
} }
#ifdef CONFIG_DEBUG_ASSERTIONS #ifdef CONFIG_DEBUG_ASSERTIONS
arch_invalidate_dcache((uintptr_t)txdesc, up_invalidate_dcache((uintptr_t)txdesc,
(uintptr_t)txdesc + sizeof(struct enet_desc_s)); (uintptr_t)txdesc + sizeof(struct enet_desc_s));
DEBUGASSERT(priv->txtail != priv->txhead && DEBUGASSERT(priv->txtail != priv->txhead &&
(txdesc->status1 & TXDESC_R) == 0); (txdesc->status1 & TXDESC_R) == 0);
@@ -816,8 +815,8 @@ static void imxrt_receive(FAR struct imxrt_driver_s *priv)
*/ */
rxdesc = &priv->rxdesc[priv->rxtail]; rxdesc = &priv->rxdesc[priv->rxtail];
arch_invalidate_dcache((uintptr_t)rxdesc, up_invalidate_dcache((uintptr_t)rxdesc,
(uintptr_t)rxdesc + sizeof(struct enet_desc_s)); (uintptr_t)rxdesc + sizeof(struct enet_desc_s));
/* Check if the data buffer associated with the descriptor has /* Check if the data buffer associated with the descriptor has
* been filled with valid data. * been filled with valid data.
@@ -837,8 +836,8 @@ static void imxrt_receive(FAR struct imxrt_driver_s *priv)
* from memory when the packet content is accessed. * from memory when the packet content is accessed.
*/ */
arch_invalidate_dcache((uintptr_t)priv->dev.d_buf, up_invalidate_dcache((uintptr_t)priv->dev.d_buf,
(uintptr_t)priv->dev.d_buf + priv->dev.d_len); (uintptr_t)priv->dev.d_buf + priv->dev.d_len);
/* Dispatch (or drop) the newly received packet */ /* Dispatch (or drop) the newly received packet */
@@ -911,8 +910,8 @@ static void imxrt_txdone(FAR struct imxrt_driver_s *priv)
*/ */
txdesc = &priv->txdesc[priv->txtail]; txdesc = &priv->txdesc[priv->txtail];
arch_invalidate_dcache((uintptr_t)txdesc, up_invalidate_dcache((uintptr_t)txdesc,
(uintptr_t)txdesc + sizeof(struct enet_desc_s)); (uintptr_t)txdesc + sizeof(struct enet_desc_s));
txdone = false; txdone = false;
if ((txdesc->status1 & TXDESC_R) == 0 && priv->txtail != priv->txhead) if ((txdesc->status1 & TXDESC_R) == 0 && priv->txtail != priv->txhead)
arch/arm/src/imxrt/imxrt_lpspi.c
-1
View File
@@ -82,7 +82,6 @@
#include "up_internal.h" #include "up_internal.h"
#include "up_arch.h" #include "up_arch.h"
#include "cache.h"
#include "chip.h" #include "chip.h"
#include "imxrt_lpspi.h" #include "imxrt_lpspi.h"
arch/arm/src/imxrt/imxrt_mpuinit.c
-1
View File
@@ -44,7 +44,6 @@
#include <nuttx/userspace.h> #include <nuttx/userspace.h>
#include "mpu.h" #include "mpu.h"
#include "cache.h"
#include "chip/imxrt_memorymap.h" #include "chip/imxrt_memorymap.h"
#include "imxrt_mpuinit.h" #include "imxrt_mpuinit.h"
arch/arm/src/imxrt/imxrt_start.c
+3 -4
View File
@@ -43,13 +43,13 @@
#include <assert.h> #include <assert.h>
#include <debug.h> #include <debug.h>
#include <nuttx/cache.h>
#include <nuttx/init.h> #include <nuttx/init.h>
#include <arch/board/board.h> #include <arch/board/board.h>
#include "up_arch.h" #include "up_arch.h"
#include "up_internal.h" #include "up_internal.h"
#include "cache.h"
#ifdef CONFIG_ARCH_FPU #ifdef CONFIG_ARCH_FPU
# include "nvic.h" # include "nvic.h"
#endif #endif
@@ -377,9 +377,8 @@ void __start(void)
/* Enable I- and D-Caches */ /* Enable I- and D-Caches */
arch_dcache_writethrough(); up_enable_icache();
arch_enable_icache(); up_enable_dcache();
arch_enable_dcache();
/* Perform early serial initialization */ /* Perform early serial initialization */
arch/arm/src/imxrt/imxrt_usdhc.c
+2 -3
View File
@@ -59,7 +59,6 @@
#include <nuttx/irq.h> #include <nuttx/irq.h>
#include <arch/board/board.h> #include <arch/board/board.h>
#include "cache.h"
#include "chip.h" #include "chip.h"
#include "up_arch.h" #include "up_arch.h"
@@ -996,8 +995,8 @@ static void imxrt_endtransfer(struct imxrt_dev_s *priv,
/* DMA modified the buffer, so we need to flush its cache lines. */ /* DMA modified the buffer, so we need to flush its cache lines. */
arch_invalidate_dcache((uintptr_t)priv->buffer, up_invalidate_dcache((uintptr_t)priv->buffer,
(uintptr_t)priv->bufferend); (uintptr_t)priv->bufferend);
/* Debug instrumentation */ /* Debug instrumentation */
arch/arm/src/kinetis/kinetis_serial.c
+2 -3
View File
@@ -61,7 +61,6 @@
#include <arch/board/board.h> #include <arch/board/board.h>
#include "cache.h"
#include "up_arch.h" #include "up_arch.h"
#include "up_internal.h" #include "up_internal.h"
@@ -1582,8 +1581,8 @@ static int up_dma_receive(struct uart_dev_s *dev, unsigned int *status)
{ {
/* Invalidate the DMA buffer */ /* Invalidate the DMA buffer */
arch_invalidate_dcache((uintptr_t)priv->rxfifo, up_invalidate_dcache((uintptr_t)priv->rxfifo,
(uintptr_t)priv->rxfifo + RXDMA_BUFFER_SIZE); (uintptr_t)priv->rxfifo + RXDMA_BUFFER_SIZE);
/* Now read from the DMA buffer */ /* Now read from the DMA buffer */
arch/arm/src/lpc31xx/lpc31_ehci.c
+32 -39
View File
@@ -61,8 +61,6 @@
#include <nuttx/usb/usbhost_trace.h> #include <nuttx/usb/usbhost_trace.h>
#include "up_arch.h" #include "up_arch.h"
#include "cache.h"
#include "chip.h" #include "chip.h"
#include "lpc31.h" #include "lpc31.h"
#include "lpc31_cgudrvr.h" #include "lpc31_cgudrvr.h"
@@ -1371,8 +1369,8 @@ static int lpc31_qtd_invalidate(struct lpc31_qtd_s *qtd, uint32_t **bp, void *ar
* memory over the specified address range. * memory over the specified address range.
*/ */
cp15_invalidate_dcache((uintptr_t)&qtd->hw, up_invalidate_dcache((uintptr_t)&qtd->hw,
(uintptr_t)&qtd->hw + sizeof(struct ehci_qtd_s)); (uintptr_t)&qtd->hw + sizeof(struct ehci_qtd_s));
return OK; return OK;
} }
#endif #endif
@@ -1390,8 +1388,8 @@ static int lpc31_qh_invalidate(struct lpc31_qh_s *qh)
{ {
/* Invalidate the QH first so that we reload the qTD list head */ /* Invalidate the QH first so that we reload the qTD list head */
cp15_invalidate_dcache((uintptr_t)&qh->hw, up_invalidate_dcache((uintptr_t)&qh->hw,
(uintptr_t)&qh->hw + sizeof(struct ehci_qh_s)); (uintptr_t)&qh->hw + sizeof(struct ehci_qh_s));
/* Then invalidate all of the qTD entries in the queue */ /* Then invalidate all of the qTD entries in the queue */
@@ -1415,10 +1413,8 @@ static int lpc31_qtd_flush(struct lpc31_qtd_s *qtd, uint32_t **bp, void *arg)
* to force re-loading of the data from memory when next accessed. * to force re-loading of the data from memory when next accessed.
*/ */
cp15_flush_idcache((uintptr_t)&qtd->hw, up_flush_dcache((uintptr_t)&qtd->hw,
(uintptr_t)&qtd->hw + sizeof(struct ehci_qtd_s)); (uintptr_t)&qtd->hw + sizeof(struct ehci_qtd_s));
cp15_invalidate_dcache((uintptr_t)&qtd->hw,
(uintptr_t)&qtd->hw + sizeof(struct ehci_qtd_s));
return OK; return OK;
} }
@@ -1438,10 +1434,8 @@ static int lpc31_qh_flush(struct lpc31_qh_s *qh)
* reloaded from D-Cache. * reloaded from D-Cache.
*/ */
cp15_flush_idcache((uintptr_t)&qh->hw, up_flush_dcache((uintptr_t)&qh->hw,
(uintptr_t)&qh->hw + sizeof(struct ehci_qh_s)); (uintptr_t)&qh->hw + sizeof(struct ehci_qh_s));
cp15_invalidate_dcache((uintptr_t)&qh->hw,
(uintptr_t)&qh->hw + sizeof(struct ehci_qh_s));
/* Then flush all of the qTD entries in the queue */ /* Then flush all of the qTD entries in the queue */
@@ -1672,8 +1666,8 @@ static void lpc31_qh_enqueue(struct lpc31_qh_s *qhead, struct lpc31_qh_s *qh)
physaddr = (uintptr_t)lpc31_physramaddr((uintptr_t)qh); physaddr = (uintptr_t)lpc31_physramaddr((uintptr_t)qh);
qhead->hw.hlp = lpc31_swap32(physaddr | QH_HLP_TYP_QH); qhead->hw.hlp = lpc31_swap32(physaddr | QH_HLP_TYP_QH);
cp15_flush_idcache((uintptr_t)&qhead->hw, up_clean_dcache((uintptr_t)&qhead->hw,
(uintptr_t)&qhead->hw + sizeof(struct ehci_qh_s)); (uintptr_t)&qhead->hw + sizeof(struct ehci_qh_s));
} }
/**************************************************************************** /****************************************************************************
@@ -1832,8 +1826,7 @@ static int lpc31_qtd_addbpl(struct lpc31_qtd_s *qtd, const void *buffer, size_t
* will be accessed for an OUT DMA. * will be accessed for an OUT DMA.
*/ */
cp15_flush_idcache((uintptr_t)buffer, (uintptr_t)buffer + buflen); up_flush_dcache((uintptr_t)buffer, (uintptr_t)buffer + buflen);
cp15_invalidate_dcache((uintptr_t)buffer, (uintptr_t)buffer + buflen);
/* Loop, adding the aligned physical addresses of the buffer to the buffer page /* Loop, adding the aligned physical addresses of the buffer to the buffer page
* list. Only the first entry need not be aligned (because only the first * list. Only the first entry need not be aligned (because only the first
@@ -2523,7 +2516,7 @@ static ssize_t lpc31_transfer_wait(struct lpc31_epinfo_s *epinfo)
* invalid in this memory region. * invalid in this memory region.
*/ */
cp15_invalidate_dcache((uintptr_t)buffer, (uintptr_t)buffer + buflen); up_invalidate_dcache((uintptr_t)buffer, (uintptr_t)buffer + buflen);
} }
#endif #endif
@@ -2673,8 +2666,8 @@ static int lpc31_qtd_ioccheck(struct lpc31_qtd_s *qtd, uint32_t **bp, void *arg)
/* Make sure we reload the QH from memory */ /* Make sure we reload the QH from memory */
cp15_invalidate_dcache((uintptr_t)&qtd->hw, up_invalidate_dcache((uintptr_t)&qtd->hw,
(uintptr_t)&qtd->hw + sizeof(struct ehci_qtd_s)); (uintptr_t)&qtd->hw + sizeof(struct ehci_qtd_s));
lpc31_qtd_print(qtd); lpc31_qtd_print(qtd);
/* Remove the qTD from the list /* Remove the qTD from the list
@@ -2724,8 +2717,8 @@ static int lpc31_qh_ioccheck(struct lpc31_qh_s *qh, uint32_t **bp, void *arg)
/* Make sure we reload the QH from memory */ /* Make sure we reload the QH from memory */
cp15_invalidate_dcache((uintptr_t)&qh->hw, up_invalidate_dcache((uintptr_t)&qh->hw,
(uintptr_t)&qh->hw + sizeof(struct ehci_qh_s)); (uintptr_t)&qh->hw + sizeof(struct ehci_qh_s));
lpc31_qh_print(qh); lpc31_qh_print(qh);
/* Get the endpoint info pointer from the extended QH data. Only the /* Get the endpoint info pointer from the extended QH data. Only the
@@ -2778,7 +2771,7 @@ static int lpc31_qh_ioccheck(struct lpc31_qh_s *qh, uint32_t **bp, void *arg)
*/ */
**bp = qh->hw.hlp; **bp = qh->hw.hlp;
cp15_flush_idcache((uintptr_t)*bp, (uintptr_t)*bp + sizeof(uint32_t)); up_clean_dcache((uintptr_t)*bp, (uintptr_t)*bp + sizeof(uint32_t));
/* Check for errors, update the data toggle */ /* Check for errors, update the data toggle */
@@ -2878,8 +2871,8 @@ static int lpc31_qtd_cancel(struct lpc31_qtd_s *qtd, uint32_t **bp, void *arg)
/* Make sure we reload the QH from memory */ /* Make sure we reload the QH from memory */
cp15_invalidate_dcache((uintptr_t)&qtd->hw, up_invalidate_dcache((uintptr_t)&qtd->hw,
(uintptr_t)&qtd->hw + sizeof(struct ehci_qtd_s)); (uintptr_t)&qtd->hw + sizeof(struct ehci_qtd_s));
lpc31_qtd_print(qtd); lpc31_qtd_print(qtd);
/* Remove the qTD from the list /* Remove the qTD from the list
@@ -2923,8 +2916,8 @@ static int lpc31_qh_cancel(struct lpc31_qh_s *qh, uint32_t **bp, void *arg)
/* Make sure we reload the QH from memory */ /* Make sure we reload the QH from memory */
cp15_invalidate_dcache((uintptr_t)&qh->hw, up_invalidate_dcache((uintptr_t)&qh->hw,
(uintptr_t)&qh->hw + sizeof(struct ehci_qh_s)); (uintptr_t)&qh->hw + sizeof(struct ehci_qh_s));
lpc31_qh_print(qh); lpc31_qh_print(qh);
/* Check if this is the QH that we are looking for */ /* Check if this is the QH that we are looking for */
@@ -2953,7 +2946,7 @@ static int lpc31_qh_cancel(struct lpc31_qh_s *qh, uint32_t **bp, void *arg)
*/ */
**bp = qh->hw.hlp; **bp = qh->hw.hlp;
cp15_flush_idcache((uintptr_t)*bp, (uintptr_t)*bp + sizeof(uint32_t)); up_clean_dcache((uintptr_t)*bp, (uintptr_t)*bp + sizeof(uint32_t));
/* Re-enable the schedules (if they were enabled before. */ /* Re-enable the schedules (if they were enabled before. */
@@ -3003,8 +2996,8 @@ static inline void lpc31_ioc_bottomhalf(void)
/* Check the Asynchronous Queue */ /* Check the Asynchronous Queue */
/* Make sure that the head of the asynchronous queue is invalidated */ /* Make sure that the head of the asynchronous queue is invalidated */
cp15_invalidate_dcache((uintptr_t)&g_asynchead.hw, up_invalidate_dcache((uintptr_t)&g_asynchead.hw,
(uintptr_t)&g_asynchead.hw + sizeof(struct ehci_qh_s)); (uintptr_t)&g_asynchead.hw + sizeof(struct ehci_qh_s));
/* Set the back pointer to the forward QH pointer of the asynchronous /* Set the back pointer to the forward QH pointer of the asynchronous
* queue head. * queue head.
@@ -3034,8 +3027,8 @@ static inline void lpc31_ioc_bottomhalf(void)
/* Check the Interrupt Queue */ /* Check the Interrupt Queue */
/* Make sure that the head of the interrupt queue is invalidated */ /* Make sure that the head of the interrupt queue is invalidated */
cp15_invalidate_dcache((uintptr_t)&g_intrhead.hw, up_invalidate_dcache((uintptr_t)&g_intrhead.hw,
(uintptr_t)&g_intrhead.hw + sizeof(struct ehci_qh_s)); (uintptr_t)&g_intrhead.hw + sizeof(struct ehci_qh_s));
/* Set the back pointer to the forward qTD pointer of the asynchronous /* Set the back pointer to the forward qTD pointer of the asynchronous
* queue head. * queue head.
@@ -5200,8 +5193,8 @@ FAR struct usbhost_connection_s *lpc31_ehci_initialize(int controller)
g_asynchead.hw.overlay.token = lpc31_swap32(QH_TOKEN_HALTED); g_asynchead.hw.overlay.token = lpc31_swap32(QH_TOKEN_HALTED);
g_asynchead.fqp = lpc31_swap32(QTD_NQP_T); g_asynchead.fqp = lpc31_swap32(QTD_NQP_T);
cp15_flush_idcache((uintptr_t)&g_asynchead.hw, up_clean_dcache((uintptr_t)&g_asynchead.hw,
(uintptr_t)&g_asynchead.hw + sizeof(struct ehci_qh_s)); (uintptr_t)&g_asynchead.hw + sizeof(struct ehci_qh_s));
/* Set the Current Asynchronous List Address. */ /* Set the Current Asynchronous List Address. */
@@ -5231,10 +5224,10 @@ FAR struct usbhost_connection_s *lpc31_ehci_initialize(int controller)
/* Set the Periodic Frame List Base Address. */ /* Set the Periodic Frame List Base Address. */
cp15_flush_idcache((uintptr_t)&g_intrhead.hw, up_clean_dcache((uintptr_t)&g_intrhead.hw,
(uintptr_t)&g_intrhead.hw + sizeof(struct ehci_qh_s)); (uintptr_t)&g_intrhead.hw + sizeof(struct ehci_qh_s));
cp15_flush_idcache((uintptr_t)g_framelist, up_clean_dcache((uintptr_t)g_framelist,
(uintptr_t)g_framelist + FRAME_LIST_SIZE * sizeof(uint32_t)); (uintptr_t)g_framelist + FRAME_LIST_SIZE * sizeof(uint32_t));
physaddr = lpc31_physramaddr((uintptr_t)g_framelist); physaddr = lpc31_physramaddr((uintptr_t)g_framelist);
lpc31_putreg(lpc31_swap32(physaddr), &HCOR->periodiclistbase); lpc31_putreg(lpc31_swap32(physaddr), &HCOR->periodiclistbase);
arch/arm/src/lpc43xx/lpc43_can.c
-1
View File
@@ -52,7 +52,6 @@
#include "up_internal.h" #include "up_internal.h"
#include "up_arch.h" #include "up_arch.h"
#include "cache.h"
#include "chip.h" #include "chip.h"
#include "lpc43_gpio.h" #include "lpc43_gpio.h"
arch/arm/src/nrf52/nrf52_nvmc.c
-1
View File
@@ -44,7 +44,6 @@
#include <nuttx/config.h> #include <nuttx/config.h>
#include <stdbool.h> #include <stdbool.h>
#include "cache.h"
#include "chip/nrf52_ficr.h" #include "chip/nrf52_ficr.h"
#include "chip/nrf52_nvmc.h" #include "chip/nrf52_nvmc.h"

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