Revamp the way external memory regions are configured; Add logic to add SAMA5 external memory regions to the heap

arch/Kconfig

@@ -103,147 +103,6 @@ source arch/x86/Kconfig
 source arch/z16/Kconfig
 source arch/z80/Kconfig
 
-menu "External Memory Configuration"
-
-config ARCH_HAVE_EXTNAND
-	bool
-
-config ARCH_HAVE_EXTNOR
-	bool
-
-config ARCH_HAVE_EXTDRAM
-	bool
-
-config ARCH_HAVE_EXTSRAM0
-	bool
-
-config ARCH_HAVE_EXTSRAM1
-	bool
-
-config ARCH_EXTNAND
-	bool "Configure external NAND"
-	default n
-	depends on ARCH_HAVE_EXTNAND
-	---help---
-		Configure external NAND memory and, if applicable, map then external
-		NAND into the memory map.
-
-if ARCH_EXTNAND
-
-config ARCH_EXTNANDSIZE
-	int "External NAND size"
-	default 0
-	---help---
-		Size of the external NAND in bytes.
-
-endif
-
-config ARCH_EXTNOR
-	bool "Configure external NOR memory"
-	default n
-	depends on ARCH_HAVE_EXTNOR
-	---help---
-		Configure external NOR memory and, if applicable, map then external
-		NOR into the memory map.
-
-if ARCH_EXTNOR
-
-config ARCH_EXTNORSIZE
-	int "External NOR size"
-	default 0
-	---help---
-		Size of the external NOR in bytes.
-
-endif
-
-config ARCH_EXTDRAM
-	bool "Configure external DRAM"
-	default n
-	depends on ARCH_HAVE_EXTDRAM
-	---help---
-		Configure external DRAM memory and, if applicable, map then external
-		DRAM into the memory map.
-
-if ARCH_EXTDRAM
-
-config ARCH_EXTDRAMSIZE
-	int "External SDRAM size"
-	default 0
-	---help---
-		Size of the external SDRAM in bytes.
-
-choice
-	prompt "SDRAM Width Selection"
-	default ARCH_SDRAM_16BIT
-
-config ARCH_SDRAM_8BIT
-	bool "8-bit"
-
-config ARCH_SDRAM_16BIT
-	bool "16-bit"
-
-config ARCH_SDRAM_32BIT
-	bool "32-bit"
-
-endchoice
-
-config ARCH_EXTDRAMHEAP
-	bool "Add external SDRAM to the heap"
-	default y
-	---help---
-		Add the external SDRAM into the heap.
-
-endif
-
-config ARCH_EXTSRAM0
-	bool "Configure external SRAM (Bank 0)"
-	default n
-	depends on ARCH_HAVE_EXTSRAM0
-	---help---
-		Configure external SRAM Bank 0 memory and, if applicable, map then
-		external SRAM Bank 0 into the memory map.
-
-if ARCH_EXTSRAM0
-
-config ARCH_EXTSRAM0SIZE
-	int "External SRAM size"
-	default 0
-	---help---
-		Size of the external SRAM Bank 0 in bytes.
-
-config ARCH_EXTSRAM0HEAP
-	bool "Add external SRAM (Bank 0) to the heap"
-	default y
-	---help---
-		Add external SRAM Bank 0 into the heap.
-
-endif
-
-config ARCH_EXTSRAM1
-	bool "Configure external SRAM (Bank 1)"
-	default n
-	depends on ARCH_HAVE_EXTSRAM1
-	---help---
-		Configure external SRAM Bank 1 memory and, if applicable, map then
-		external SRAM Bank 1 into the memory map.
-
-if ARCH_EXTSRAM1
-
-config ARCH_EXTSRAM1SIZE
-	int "External SRAM1 size"
-	default 0
-	---help---
-		Size of the external SRAM Bank 1 in bytes.
-
-config ARCH_EXTSRAM1HEAP
-	bool "Add external SRAM (Bank 1) to the heap"
-	default y
-	---help---
-		Add external SRAM Bank 1 into the heap.
-
-endif
-endmenu
-
 comment "Architecture Options"
 
 config ARCH_NOINTC

arch/arm/src/lpc17xx/Kconfig

@@ -323,6 +323,120 @@ config LPC17_EEPROM
 
 endmenu
 
+menu "External Memory Configuration"
+
+config ARCH_HAVE_EXTNAND
+	bool
+
+config ARCH_HAVE_EXTNOR
+	bool
+
+config ARCH_HAVE_EXTDRAM
+	bool
+
+config ARCH_HAVE_EXTSRAM0
+	bool
+
+config LPC17_EXTNAND
+	bool "Configure external NAND"
+	default n
+	depends on ARCH_HAVE_EXTNAND
+	---help---
+		Configure external NAND memory and, if applicable, map then external
+		NAND into the memory map.
+
+if LPC17_EXTNAND
+
+config LPC17_EXTNANDSIZE
+	int "External NAND size"
+	default 0
+	---help---
+		Size of the external NAND in bytes.
+
+endif
+
+config LPC17_EXTNOR
+	bool "Configure external NOR memory"
+	default n
+	depends on ARCH_HAVE_EXTNOR
+	---help---
+		Configure external NOR memory and, if applicable, map then external
+		NOR into the memory map.
+
+if LPC17_EXTNOR
+
+config LPC17_EXTNORSIZE
+	int "External NOR size"
+	default 0
+	---help---
+		Size of the external NOR in bytes.
+
+endif
+
+config LPC17_EXTDRAM
+	bool "Configure external DRAM"
+	default n
+	depends on ARCH_HAVE_EXTDRAM
+	---help---
+		Configure external DRAM memory and, if applicable, map then external
+		DRAM into the memory map.
+
+if LPC17_EXTDRAM
+
+config LPC17_EXTDRAMSIZE
+	int "External SDRAM size"
+	default 0
+	---help---
+		Size of the external SDRAM in bytes.
+
+choice
+	prompt "SDRAM Width Selection"
+	default LPC17_SDRAM_16BIT
+
+config LPC17_SDRAM_8BIT
+	bool "8-bit"
+
+config LPC17_SDRAM_16BIT
+	bool "16-bit"
+
+config LPC17_SDRAM_32BIT
+	bool "32-bit"
+
+endchoice
+
+config LPC17_EXTDRAMHEAP
+	bool "Add external SDRAM to the heap"
+	default y
+	---help---
+		Add the external SDRAM into the heap.
+
+endif
+
+config LPC17_EXTSRAM0
+	bool "Configure external SRAM (Bank 0)"
+	default n
+	depends on ARCH_HAVE_EXTSRAM0
+	---help---
+		Configure external SRAM Bank 0 memory and, if applicable, map then
+		external SRAM Bank 0 into the memory map.
+
+if LPC17_EXTSRAM0
+
+config LPC17_EXTSRAM0SIZE
+	int "External SRAM size"
+	default 0
+	---help---
+		Size of the external SRAM Bank 0 in bytes.
+
+config LPC17_EXTSRAM0HEAP
+	bool "Add external SRAM (Bank 0) to the heap"
+	default y
+	---help---
+		Add external SRAM Bank 0 into the heap.
+
+endif
+endmenu
+
 menu "Serial driver options"
 	depends on LPC17_UART0 || LPC17_UART1 || LPC17_UART2 || LPC17_UART3 || LPC17_UART4
 

arch/arm/src/lpc31xx/Kconfig

@@ -38,7 +38,7 @@ config ARCH_CHIP_LPC3154
 	select ARCH_HAVE_EXTSRAM1
 	select ARCH_HAVE_EXTDRAM
 
-endchoice
+endchoice # LPC31xx Configuration Options
 
 choice
 	prompt "Toolchain Selection"
@@ -62,11 +62,11 @@ config LPC31_BUILDROOT
 	bool "Buildroot"
 	depends on !WINDOWS_NATIVE
 
-endchoice
+endchoice # Toolchain Selection
 
 config LPC31_SDRAMHCLK
 	int "External SDRAM HCLK"
-	depends on ARCH_EXTSDRAM
+	depends on LPC31_EXTSDRAM
 	---help---
 		The SDRAM HCLK may be specified here (if not, it will be calculated).
 
@@ -89,7 +89,127 @@ config LPC31_MCI
 	bool "MCI"
 	default n
 
-endmenu
+endmenu # LPC31xx Peripheral Support
+
+menu "External Memory Configuration"
+
+config ARCH_HAVE_EXTNAND
+	bool
+
+config ARCH_HAVE_EXTDRAM
+	bool
+
+config ARCH_HAVE_EXTSRAM0
+	bool
+
+config ARCH_HAVE_EXTSRAM1
+	bool
+
+config LPC31_EXTNAND
+	bool "Configure external NAND"
+	default n
+	depends on ARCH_HAVE_EXTNAND
+	---help---
+		Configure external NAND memory and, if applicable, map then external
+		NAND into the memory map.
+
+if LPC31_EXTNAND
+
+config LPC31_EXTNANDSIZE
+	int "External NAND size"
+	default 0
+	---help---
+		Size of the external NAND in bytes.
+
+endif # LPC31_EXTNAND
+
+config LPC31_EXTDRAM
+	bool "Configure external DRAM"
+	default n
+	depends on ARCH_HAVE_EXTDRAM
+	---help---
+		Configure external DRAM memory and, if applicable, map then external
+		DRAM into the memory map.
+
+if LPC31_EXTDRAM
+
+config LPC31_EXTDRAMSIZE
+	int "External SDRAM size"
+	default 0
+	---help---
+		Size of the external SDRAM in bytes.
+
+choice
+	prompt "SDRAM Width Selection"
+	default LPC31_SDRAM_16BIT
+
+config LPC31_SDRAM_8BIT
+	bool "8-bit"
+
+config LPC31_SDRAM_16BIT
+	bool "16-bit"
+
+config LPC31_SDRAM_32BIT
+	bool "32-bit"
+
+endchoice # SDRAM Width Selection
+
+config LPC31_EXTDRAMHEAP
+	bool "Add external SDRAM to the heap"
+	default y
+	---help---
+		Add the external SDRAM into the heap.
+
+endif # LPC31_EXTDRAM
+
+config LPC31_EXTSRAM0
+	bool "Configure external SRAM (Bank 0)"
+	default n
+	depends on ARCH_HAVE_EXTSRAM0
+	---help---
+		Configure external SRAM Bank 0 memory and, if applicable, map then
+		external SRAM Bank 0 into the memory map.
+
+if LPC31_EXTSRAM0
+
+config LPC31_EXTSRAM0SIZE
+	int "External SRAM size"
+	default 0
+	---help---
+		Size of the external SRAM Bank 0 in bytes.
+
+config LPC31_EXTSRAM0HEAP
+	bool "Add external SRAM (Bank 0) to the heap"
+	default y
+	---help---
+		Add external SRAM Bank 0 into the heap.
+
+endif # LPC31_EXTSRAM0
+
+config LPC31_EXTSRAM1
+	bool "Configure external SRAM (Bank 1)"
+	default n
+	depends on ARCH_HAVE_EXTSRAM1
+	---help---
+		Configure external SRAM Bank 1 memory and, if applicable, map then
+		external SRAM Bank 1 into the memory map.
+
+if LPC31_EXTSRAM1
+
+config LPC31_EXTSRAM1SIZE
+	int "External SRAM1 size"
+	default 0
+	---help---
+		Size of the external SRAM Bank 1 in bytes.
+
+config LPC31_EXTSRAM1HEAP
+	bool "Add external SRAM (Bank 1) to the heap"
+	default y
+	---help---
+		Add external SRAM Bank 1 into the heap.
+
+endif # LPC31_EXTSRAM1
+endmenu # External Memory Configuration
 
 menu "LPC31xx UART Configuration"
 	depends on LPC31_UART
@@ -109,7 +229,7 @@ config LPC31_UART_MULVAL
 	---help---
 		BAUD multiplier
 
-endmenu
+endmenu # LPC31xx UART Configuration
 
 menu "USB device driver options"
 
@@ -143,7 +263,7 @@ config LPC31_USBDEV_REGDEBUG
 	---help---
 		Output detailed register-level USB device debug information.  Requires also DEBUG.
 
-endmenu
+endmenu # USB device driver options
 
 menu "SPI device driver options"
 
@@ -154,5 +274,4 @@ config LPC31_SPI_REGDEBUG
 	---help---
 		Output detailed register-level SPI device debug information.  Requires also DEBUG.
 
-endmenu
+endmenu # SPI device driver options
-

arch/arm/src/lpc31xx/lpc31_allocateheap.c

@@ -68,31 +68,31 @@
  * memory regions that we have been asked to add to the heap.
  */
 
-#if defined(CONFIG_ARCH_EXTSRAM0) && defined(CONFIG_ARCH_EXTSRAM0HEAP)
+#if defined(CONFIG_LPC31_EXTSRAM0) && defined(CONFIG_LPC31_EXTSRAM0HEAP)
-#  if defined(CONFIG_ARCH_EXTSRAM1) && defined(CONFIG_ARCH_EXTSRAM1HEAP)
+#  if defined(CONFIG_LPC31_EXTSRAM1) && defined(CONFIG_LPC31_EXTSRAM1HEAP)
-#    if defined(CONFIG_ARCH_EXTDRAM) && defined(CONFIG_ARCH_EXTDRAMHEAP)
+#    if defined(CONFIG_LPC31_EXTDRAM) && defined(CONFIG_LPC31_EXTDRAMHEAP)
 #      /* SRAM+EXTSRAM0+EXTSRAM1+EXTSDRAM */
 #      define LPC31_NEXT_REGIONS 4
 #    else
 #      /* SRAM+EXTSRAM0+EXTSRAM1 */
 #      define LPC31_NEXT_REGIONS 3
 #    endif
-#  elif defined(CONFIG_ARCH_EXTDRAM) && defined(CONFIG_ARCH_EXTDRAMHEAP)
+#  elif defined(CONFIG_LPC31_EXTDRAM) && defined(CONFIG_LPC31_EXTDRAMHEAP)
 #      /* SRAM+EXTSRAM0+EXTSDRAM */
 #      define LPC31_NEXT_REGIONS 3
 #  else
 #      /* SRAM+EXTSRAM0 */
 #      define LPC31_NEXT_REGIONS 2
 #  endif
-#elif defined(CONFIG_ARCH_EXTSRAM1) && defined(CONFIG_ARCH_EXTSRAM1HEAP)
+#elif defined(CONFIG_LPC31_EXTSRAM1) && defined(CONFIG_LPC31_EXTSRAM1HEAP)
-#  if defined(CONFIG_ARCH_EXTDRAM) && defined(CONFIG_ARCH_EXTDRAMHEAP)
+#  if defined(CONFIG_LPC31_EXTDRAM) && defined(CONFIG_LPC31_EXTDRAMHEAP)
 #      /* SRAM+EXTSRAM1+EXTSDRAM */
 #      define LPC31_NEXT_REGIONS 3
 #  else
 #      /* SRAM+EXTSRAM1 */
 #      define LPC31_NEXT_REGIONS 2
 #  endif
-#elif defined(CONFIG_ARCH_EXTDRAM) && defined(CONFIG_ARCH_EXTDRAMHEAP)
+#elif defined(CONFIG_LPC31_EXTDRAM) && defined(CONFIG_LPC31_EXTDRAMHEAP)
 #      /* SRAM+EXTSDRAM */
 #      define LPC31_NEXT_REGIONS 2
 #else
@@ -106,13 +106,13 @@
 #  else
 #    error "CONFIG_MM_REGIONS is too large for the selected memory regions"
 #  endif
-#  if defined(CONFIG_ARCH_EXTSRAM0) && defined(CONFIG_ARCH_EXTSRAM0HEAP)
+#  if defined(CONFIG_LPC31_EXTSRAM0) && defined(CONFIG_LPC31_EXTSRAM0HEAP)
 #    error "External SRAM0 is selected for heap"
 #  endif
-#  if defined(CONFIG_ARCH_EXTSRAM1) && defined(CONFIG_ARCH_EXTSRAM1HEAP)
+#  if defined(CONFIG_LPC31_EXTSRAM1) && defined(CONFIG_LPC31_EXTSRAM1HEAP)
 #    error "External SRAM1 is selected for heap"
 #  endif
-#  if defined(CONFIG_ARCH_EXTDRAM) && defined(CONFIG_ARCH_EXTDRAMHEAP)
+#  if defined(CONFIG_LPC31_EXTDRAM) && defined(CONFIG_LPC31_EXTDRAMHEAP)
 #    error "External SRAM1 is selected for heap"
 #  endif
 #endif
@@ -196,16 +196,16 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
 #if CONFIG_MM_REGIONS > 1
 void up_addregion(void)
 {
-#if defined(CONFIG_ARCH_EXTSRAM0) && defined(CONFIG_ARCH_EXTSRAM0HEAP)
+#if defined(CONFIG_LPC31_EXTSRAM0) && defined(CONFIG_LPC31_EXTSRAM0HEAP)
-  kmm_addregion((FAR void*)LPC31_EXTSRAM0_VSECTION, CONFIG_ARCH_EXTSRAM0SIZE);
+  kmm_addregion((FAR void*)LPC31_EXTSRAM0_VSECTION, CONFIG_LPC31_EXTSRAM0SIZE);
 #endif
 
-#if defined(CONFIG_ARCH_EXTSRAM1) && defined(CONFIG_ARCH_EXTSRAM1HEAP)
+#if defined(CONFIG_LPC31_EXTSRAM1) && defined(CONFIG_LPC31_EXTSRAM1HEAP)
-  kmm_addregion((FAR void*)LPC31_EXTSRAM1_VSECTION, CONFIG_ARCH_EXTSRAM1SIZE);
+  kmm_addregion((FAR void*)LPC31_EXTSRAM1_VSECTION, CONFIG_LPC31_EXTSRAM1SIZE);
 #endif
 
-#if defined(CONFIG_ARCH_EXTDRAM) && defined(CONFIG_ARCH_EXTDRAMHEAP)
+#if defined(CONFIG_LPC31_EXTDRAM) && defined(CONFIG_LPC31_EXTDRAMHEAP)
-  kmm_addregion((FAR void*)LPC31_EXTSDRAM_VSECTION, CONFIG_ARCH_EXTDRAMSIZE);
+  kmm_addregion((FAR void*)LPC31_EXTSDRAM_VSECTION, CONFIG_LPC31_EXTDRAMSIZE);
 #endif
 }
 #endif

arch/arm/src/lpc31xx/lpc31_boot.c

@@ -112,17 +112,17 @@ static const struct section_mapping_s section_mapping[] =
     LPC31_MCI_MMUFLAGS, LPC31_MCI_NSECTIONS},
   { LPC31_USBOTG_PSECTION, LPC31_USBOTG_VSECTION, 
     LPC31_USBOTG_MMUFLAGS, LPC31_USBOTG_NSECTIONS},
-#if defined(CONFIG_ARCH_EXTSRAM0) && CONFIG_ARCH_EXTSRAM0SIZE > 0
+#if defined(CONFIG_LPC31_EXTSRAM0) && CONFIG_LPC31_EXTSRAM0SIZE > 0
   { LPC31_EXTSRAM_PSECTION, LPC31_EXTSRAM_VSECTION, 
     LPC31_EXTSDRAM_MMUFLAGS, LPC31_EXTSRAM_NSECTIONS},
 #endif
-#if defined(CONFIG_ARCH_EXTDRAM) && CONFIG_ARCH_EXTDRAMSIZE > 0
+#if defined(CONFIG_LPC31_EXTDRAM) && CONFIG_LPC31_EXTDRAMSIZE > 0
   { LPC31_EXTSDRAM0_PSECTION, LPC31_EXTSDRAM0_VSECTION, 
     LPC31_EXTSDRAM_MMUFLAGS, LPC31_EXTSDRAM0_NSECTIONS},
 #endif
   { LPC31_INTC_PSECTION, LPC31_INTC_VSECTION, 
     LPC31_INTC_MMUFLAGS, LPC31_INTC_NSECTIONS},
-#ifdef CONFIG_ARCH_EXTNAND
+#ifdef CONFIG_LPC31_EXTNAND
   { LPC31_NAND_PSECTION, LPC31_NAND_VSECTION 
     LPC31_NAND_MMUFLAGS, LPC31_NAND_NSECTIONS},
 #endif

arch/arm/src/lpc31xx/lpc31_memorymap.h

@@ -81,7 +81,7 @@
                                                 /* 0x60001000-0x6fffffff: Reserved */
 #define LPC31_NAND_PSECTION          0x70000000 /* 0x70000000-0x700007ff: NANDFLASH Ctrl 2Kb */
                                                 /* 0x70000800-0xffffffff: Reserved */
-#ifdef CONFIG_ARCH_EXTNAND                      /* End of the physical address space */
+#ifdef CONFIG_LPC31_EXTNAND                     /* End of the physical address space */
 #  define LPC31_LAST_PSECTION        (LPC31_NAND_PSECTION + (1 << 20))
 #else
 #  define LPC31_LAST_PSECTION        (LPC31_INTC_PSECTION + (1 << 20))
@@ -176,8 +176,8 @@
  * the size of the SDRAM installed.
  */
 
-#if defined(CONFIG_ARCH_EXTDRAM) && CONFIG_ARCH_EXTDRAMSIZE > 0
+#if defined(CONFIG_LPC31_EXTDRAM) && CONFIG_LPC31_EXTDRAMSIZE > 0
-#  define LPC31_EXTSDRAM0_NSECTIONS  _NSECTIONS(CONFIG_ARCH_EXTDRAMSIZE)
+#  define LPC31_EXTSDRAM0_NSECTIONS  _NSECTIONS(CONFIG_LPC31_EXTDRAMSIZE)
 #endif
 
 /* Section MMU Flags */
@@ -233,7 +233,7 @@
 #  define LPC31_INTC_VSECTION        0x60000000 /* 0x60000000-0x60000fff: Interrupt controller 4Kb */
 #  define LPC31_NAND_VSECTION        0x70000000 /* 0x70000000-0x700007ff: NANDFLASH Ctrl 2Kb */
 #
-#  ifdef CONFIG_ARCH_EXTNAND                    /* End of the virtual address space */
+#  ifdef CONFIG_LPC31_EXTNAND                   /* End of the virtual address space */
 #    define LPC31_LAST_VSECTION      (LPC31_NAND_VSECTION + (1 << 20))
 #  else
 #    define LPC31_LAST_VSECTION      (LPC31_INTC_VSECTION + (1 << 20))

arch/arm/src/sam34/Kconfig

@@ -163,7 +163,7 @@ config ARCH_CHIP_ATSAM4S8B
 	select ARCH_CORTEXM4
 	select ARCH_CHIP_SAM4S
 
-endchoice
+endchoice # AT91SAM3/4 Chip Selection
 
 config ARCH_CHIP_SAM3U
 	bool
@@ -520,7 +520,7 @@ config SAM34_HSMCI
 	default n
 	depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4S
 
-endmenu
+endmenu # AT91SAM3/4 Peripheral Support
 
 if ARCH_CHIP_SAM4L
 menu "AT91SAM3/4 Clock Configuration"
@@ -587,8 +587,8 @@ config SAM34_RCFAST8M
 config SAM34_RCFAST4M
 	bool "4MHz"
 
-endchoice
+endchoice # Fast RC Oscillator Speed
-endif
+endif # SAM34_RCFAST
 
 config SAM34_RC1M
 	bool "1MHz RC oscillator"
@@ -610,8 +610,149 @@ config SAM34_RC32K
 		you can also force the clock to be enabled at boot time for other
 		purposes.
 
-endmenu
+endmenu # AT91SAM3/4 Clock Configuration
-endif
+endif # ARCH_CHIP_SAM4L
+
+menu "External Memory Configuration"
+
+config ARCH_HAVE_EXTNAND
+	bool
+
+config ARCH_HAVE_EXTNOR
+	bool
+
+config ARCH_HAVE_EXTDRAM
+	bool
+
+config ARCH_HAVE_EXTSRAM0
+	bool
+
+config ARCH_HAVE_EXTSRAM1
+	bool
+
+config SAM34_EXTNAND
+	bool "Configure external NAND"
+	default n
+	depends on ARCH_HAVE_EXTNAND
+	---help---
+		Configure external NAND memory and, if applicable, map then external
+		NAND into the memory map.
+
+if SAM34_EXTNAND
+
+config SAM34_EXTNANDSIZE
+	int "External NAND size"
+	default 0
+	---help---
+		Size of the external NAND in bytes.
+
+endif # SAM34_EXTNAND
+
+config SAM34_EXTNOR
+	bool "Configure external NOR memory"
+	default n
+	depends on ARCH_HAVE_EXTNOR
+	---help---
+		Configure external NOR memory and, if applicable, map then external
+		NOR into the memory map.
+
+if SAM34_EXTNOR
+
+config SAM34_EXTNORSIZE
+	int "External NOR size"
+	default 0
+	---help---
+		Size of the external NOR in bytes.
+
+endif # SAM34_EXTNOR
+
+config SAM34_EXTDRAM
+	bool "Configure external DRAM"
+	default n
+	depends on ARCH_HAVE_EXTDRAM
+	---help---
+		Configure external DRAM memory and, if applicable, map then external
+		DRAM into the memory map.
+
+if SAM34_EXTDRAM
+
+config SAM34_EXTDRAMSIZE
+	int "External SDRAM size"
+	default 0
+	---help---
+		Size of the external SDRAM in bytes.
+
+choice
+	prompt "SDRAM Width Selection"
+	default SAM34_SDRAM_16BIT
+
+config SAM34_SDRAM_8BIT
+	bool "8-bit"
+
+config SAM34_SDRAM_16BIT
+	bool "16-bit"
+
+config SAM34_SDRAM_32BIT
+	bool "32-bit"
+
+endchoice # SDRAM Width Selection
+
+config SAM34_EXTDRAMHEAP
+	bool "Add external SDRAM to the heap"
+	default y
+	---help---
+		Add the external SDRAM into the heap.
+
+endif # SAM34_EXTDRAM
+
+config SAM34_EXTSRAM0
+	bool "Configure external SRAM (Bank 0)"
+	default n
+	depends on ARCH_HAVE_EXTSRAM0
+	---help---
+		Configure external SRAM Bank 0 memory and, if applicable, map then
+		external SRAM Bank 0 into the memory map.
+
+if SAM34_EXTSRAM0
+
+config SAM34_EXTSRAM0SIZE
+	int "External SRAM size"
+	default 0
+	---help---
+		Size of the external SRAM Bank 0 in bytes.
+
+config SAM34_EXTSRAM0HEAP
+	bool "Add external SRAM (Bank 0) to the heap"
+	default y
+	---help---
+		Add external SRAM Bank 0 into the heap.
+
+endif # SAM34_EXTSRAM0
+
+config SAM34_EXTSRAM1
+	bool "Configure external SRAM (Bank 1)"
+	default n
+	depends on ARCH_HAVE_EXTSRAM1
+	---help---
+		Configure external SRAM Bank 1 memory and, if applicable, map then
+		external SRAM Bank 1 into the memory map.
+
+if SAM34_EXTSRAM1
+
+config SAM34_EXTSRAM1SIZE
+	int "External SRAM1 size"
+	default 0
+	---help---
+		Size of the external SRAM Bank 1 in bytes.
+
+config SAM34_EXTSRAM1HEAP
+	bool "Add external SRAM (Bank 1) to the heap"
+	default y
+	---help---
+		Add external SRAM Bank 1 into the heap.
+
+endif # SAM34_EXTSRAM1
+endmenu # External Memory Configuration
 
 comment "AT91SAM3/4 USART Configuration"
 
@@ -675,7 +816,7 @@ config GPIOF_IRQ
 	default n
 	depends on ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A
 
-endif
+endif # GPIO_IRQ
 
 if SAM34_WDT
 comment "AT91SAM3/4 Watchdog Configuration"|
@@ -701,4 +842,4 @@ config WDT_DISABLE_ON_RESET
 		configure and disable the watchdog timer very early in the boot
 		sequence.
 
-endif
+endif # SAM34_WDT

arch/arm/src/sam34/sam_allocateheap.c

@@ -75,24 +75,24 @@
  * to be used as heap.
  */
 
-#if !defined(CONFIG_ARCH_EXTSRAM0) || !defined(CONFIG_ARCH_EXTSRAM0HEAP)
+#if !defined(CONFIG_SAM34_EXTSRAM0) || !defined(CONFIG_SAM34_EXTSRAM0HEAP)
-#  undef CONFIG_ARCH_EXTSRAM0SIZE
+#  undef CONFIG_SAM34_EXTSRAM0SIZE
-#  define CONFIG_ARCH_EXTSRAM0SIZE 0
+#  define CONFIG_SAM34_EXTSRAM0SIZE 0
 #endif
 
-#if !defined(CONFIG_ARCH_EXTSRAM1) || !defined(CONFIG_ARCH_EXTSRAM1HEAP)
+#if !defined(CONFIG_SAM34_EXTSRAM1) || !defined(CONFIG_SAM34_EXTSRAM1HEAP)
-#  undef CONFIG_ARCH_EXTSRAM1SIZE
+#  undef CONFIG_SAM34_EXTSRAM1SIZE
-#  define CONFIG_ARCH_EXTSRAM1SIZE 0
+#  define CONFIG_SAM34_EXTSRAM1SIZE 0
 #endif
 
-#if !defined(CONFIG_ARCH_EXTSRAM2) || !defined(CONFIG_ARCH_EXTSRAM2HEAP)
+#if !defined(CONFIG_SAM34_EXTSRAM2) || !defined(CONFIG_SAM34_EXTSRAM2HEAP)
-#  undef CONFIG_ARCH_EXTSRAM2SIZE
+#  undef CONFIG_SAM34_EXTSRAM2SIZE
-#  define CONFIG_ARCH_EXTSRAM2SIZE 0
+#  define CONFIG_SAM34_EXTSRAM2SIZE 0
 #endif
 
-#if !defined(CONFIG_ARCH_EXTSRAM3) || !defined(CONFIG_ARCH_EXTSRAM3HEAP)
+#if !defined(CONFIG_SAM34_EXTSRAM3) || !defined(CONFIG_SAM34_EXTSRAM3HEAP)
-#  undef CONFIG_ARCH_EXTSRAM3SIZE
+#  undef CONFIG_SAM34_EXTSRAM3SIZE
-#  define CONFIG_ARCH_EXTSRAM3SIZE 0
+#  define CONFIG_SAM34_EXTSRAM3SIZE 0
 #endif
 
 /* SAM3U, SAM3X, and SAM3A Unique memory configurations */
@@ -119,7 +119,7 @@
 #      warning "CONFIG_MM_REGIONS < 3: NFC SRAM not included in HEAP"
 #    endif
 
-#    if CONFIG_ARCH_EXTSRAM0SIZE > 0
+#    if CONFIG_SAM34_EXTSRAM0SIZE > 0
 #      if CONFIG_MM_REGIONS > 3
 #        define HAVE_EXTSRAM0_REGION 1
 #      else
@@ -127,7 +127,7 @@
 #      endif
 #    endif
 
-#  elif CONFIG_ARCH_EXTSRAM0SIZE > 0
+#  elif CONFIG_SAM34_EXTSRAM0SIZE > 0
 #    if CONFIG_MM_REGIONS > 2
 #       define HAVE_EXTSRAM0_REGION 1
 #    else
@@ -138,7 +138,7 @@
 
 /* The SAM4S and SAM4L may have only internal SRAM0 and external SRAM0 */
 
-#  if CONFIG_ARCH_EXTSRAM0SIZE > 0
+#  if CONFIG_SAM34_EXTSRAM0SIZE > 0
 #    if CONFIG_MM_REGIONS > 1
 #       define HAVE_EXTSRAM0_REGION 1
 #    else
@@ -340,44 +340,44 @@ void up_addregion(void)
 #ifdef HAVE_EXTSRAM0_REGION
   /* Allow user access to the heap memory */
 
-  sam_mpu_uheap(SAM_EXTCS0_BASE, CONFIG_ARCH_EXTSRAM0SIZE);
+  sam_mpu_uheap(SAM_EXTCS0_BASE, CONFIG_SAM34_EXTSRAM0SIZE);
 
   /* Add the region */
 
-  kumm_addregion((FAR void*)SAM_EXTCS0_BASE, CONFIG_ARCH_EXTSRAM0SIZE);
+  kumm_addregion((FAR void*)SAM_EXTCS0_BASE, CONFIG_SAM34_EXTSRAM0SIZE);
 
 #endif /* HAVE_EXTSRAM0_REGION */
 
 #ifdef HAVE_EXTSRAM1_REGION
   /* Allow user access to the heap memory */
 
-  sam_mpu_uheap(SAM_EXTCS1_BASE, CONFIG_ARCH_EXTSRAM1SIZE);
+  sam_mpu_uheap(SAM_EXTCS1_BASE, CONFIG_SAM34_EXTSRAM1SIZE);
 
   /* Add the region */
 
-  kumm_addregion((FAR void*)SAM_EXTCS1_BASE, CONFIG_ARCH_EXTSRAM1SIZE);
+  kumm_addregion((FAR void*)SAM_EXTCS1_BASE, CONFIG_SAM34_EXTSRAM1SIZE);
 
 #endif /* HAVE_EXTSRAM0_REGION */
 
 #ifdef HAVE_EXTSRAM2_REGION
   /* Allow user access to the heap memory */
 
-  sam_mpu_uheap(SAM_EXTCS2_BASE, CONFIG_ARCH_EXTSRAM2SIZE);
+  sam_mpu_uheap(SAM_EXTCS2_BASE, CONFIG_SAM34_EXTSRAM2SIZE);
 
   /* Add the region */
 
-  kumm_addregion((FAR void*)SAM_EXTCS2_BASE, CONFIG_ARCH_EXTSRAM2SIZE);
+  kumm_addregion((FAR void*)SAM_EXTCS2_BASE, CONFIG_SAM34_EXTSRAM2SIZE);
 
 #endif /* HAVE_EXTSRAM0_REGION */
 
 #ifdef HAVE_EXTSRAM3_REGION
   /* Allow user access to the heap memory */
 
-  sam_mpu_uheap(SAM_EXTCS3_BASE, CONFIG_ARCH_EXTSRAM3SIZE);
+  sam_mpu_uheap(SAM_EXTCS3_BASE, CONFIG_SAM34_EXTSRAM3SIZE);
 
   /* Add the region */
 
-  kumm_addregion((FAR void*)SAM_EXTCS3_BASE, CONFIG_ARCH_EXTSRAM3SIZE);
+  kumm_addregion((FAR void*)SAM_EXTCS3_BASE, CONFIG_SAM34_EXTSRAM3SIZE);
 
 #endif /* HAVE_EXTSRAM0_REGION */
 }

arch/arm/src/sama5/Kconfig

@@ -27,7 +27,7 @@ config ARCH_CHIP_ATSAMA5D35
 	bool "Atmel ATSAMA5D35"
 	select ARCH_CHIP_SAMA5D3
 
-endchoice
+endchoice # Atmel AT91SAMA5 Chip Selection
 
 menu "ATSAMA5 Peripheral Support"
 
@@ -205,7 +205,7 @@ config SAMA5_MPDDRC
 	bool "MPDDR controller (MPDDRC)"
 	default n
 
-endmenu
+endmenu # ATSAMA5 Peripheral Support
 
 config PIO_IRQ
 	bool "PIO pin interrupts"
@@ -234,35 +234,364 @@ config PIOE_IRQ
 	bool "PIOE interrupts"
 	default n
 
-endif
+endif # PIO_IRQ
+
+menu "External Memory Configuration"
+
+config SAMA5_DDRCS
+	bool "External DDR-SDRAM Memory"
+	default n
+	---help---
+		Build in support for DDR-SDRAM memory resources.
+
+if SAMA5_DDRCS
+
+config SAMA5_DDRCS_SIZE
+	int "DDR-SDRAM Memory size"
+	default 0
+	---help---
+		Mapped size of the DDR-SDRAM memory region.
+
+choice
+	prompt "DDR-SDRAM Memory Type"
+	default SAMA5_DDRCS_LPDDR1
+	---help---
+		Select the type of DDR-SDRAM memory present
+
+config SAMA5_DDRCS_LPDDR1
+	bool "Low-power DDR1-SDRAM (LPDDR1)"
+
+config SAMA5_DDRCS_LPDDR2
+	bool "Low-power DDR2-SDRAM-S4 (LPDDR2)"
+
+endchoice # DDR-SDRAM Memory Type
+endif # SAMA5_DDRCS
+
+config SAMA5_EBICS0
+	bool "External CS0 Memory"
+	default n
+	---help---
+		Build in support for memory resources in the chip select 0 (CS0)
+		memory region.
+
+if SAMA5_EBICS0
+
+config SAMA5_EBICS0_SIZE
+	int "CS0 Memory size"
+	default 0
+	---help---
+		Mapped size of the memory region at CS0.
+
+choice
+	prompt "CS0 Memory Type"
+	default SAMA5_EBICS0_NOR
+	---help---
+		Select the type of memory present on CS0
+
+config SAMA5_EBICS0_SRAM
+	bool "SRAM"
+
+config SAMA5_EBICS0_PSRAM
+	bool "PSRAM"
+
+config SAMA5_EBICS0_PROM
+	bool "PROM"
+
+config SAMA5_EBICS0_EEPROM
+	bool "EEPROM"
+
+config SAMA5_EBICS0_EPROM
+	bool "EPROM"
+
+config SAMA5_EBICS0_LCD
+	bool "LCD"
+
+config SAMA5_EBICS0_NOR
+	bool "NOR Flash"
+
+config SAMA5_EBICS0_NAND
+	bool "NAND Flash"
+
+endchoice # CS0 Memory Type
+endif # SAMA5_EBICS0
+
+config SAMA5_EBICS1
+	bool "External CS1 Memory"
+	default n
+	---help---
+		Build in support for memory resources in the chip select 1 (CS1)
+		memory region.
+
+if SAMA5_EBICS1
+
+config SAMA5_EBICS1_SIZE
+	int "CS1 Memory size"
+	default 0
+	---help---
+		Mapped size of the memory region at CS1.
+
+choice
+	prompt "CS1 Memory Type"
+	default SAMA5_EBICS1_NOR
+	---help---
+		Select the type of memory present on CS1
+
+config SAMA5_EBICS1_SRAM
+	bool "SRAM"
+
+config SAMA5_EBICS1_PSRAM
+	bool "PSRAM"
+
+config SAMA5_EBICS1_PROM
+	bool "PROM"
+
+config SAMA5_EBICS1_EEPROM
+	bool "EEPROM"
+
+config SAMA5_EBICS1_EPROM
+	bool "EPROM"
+
+config SAMA5_EBICS1_LCD
+	bool "LCD"
+
+config SAMA5_EBICS1_NOR
+	bool "NOR Flash"
+
+config SAMA5_EBICS1_NAND
+	bool "NAND Flash"
+
+endchoice # CS1 Memory Type
+endif # SAMA5_EBICS1
+
+config SAMA5_EBICS2
+	bool "External CS2 Memory"
+	default n
+	---help---
+		Build in support for memory resources in the chip select 2 (CS2)
+		memory region.
+
+if SAMA5_EBICS2
+
+config SAMA5_EBICS2_SIZE
+	int "CS2 Memory size"
+	default 0
+	---help---
+		Mapped size of the memory region at CS2.
+
+choice
+	prompt "CS2 Memory Type"
+	default SAMA5_EBICS2_NOR
+	---help---
+		Select the type of memory present on CS2
+
+config SAMA5_EBICS2_SRAM
+	bool "SRAM"
+
+config SAMA5_EBICS2_PSRAM
+	bool "PSRAM"
+
+config SAMA5_EBICS2_PROM
+	bool "PROM"
+
+config SAMA5_EBICS2_EEPROM
+	bool "EEPROM"
+
+config SAMA5_EBICS2_EPROM
+	bool "EPROM"
+
+config SAMA5_EBICS2_LCD
+	bool "LCD"
+
+config SAMA5_EBICS2_NOR
+	bool "NOR Flash"
+
+config SAMA5_EBICS2_NAND
+	bool "NAND Flash"
+
+endchoice # CS2 Memory Type
+endif # SAMA5_EBICS2
+
+config SAMA5_EBICS3
+	bool "External CS3 Memory"
+	default n
+	---help---
+		Build in support for memory resources in the chip select 3 (CS3)
+		memory region.
+
+if SAMA5_EBICS3
+
+config SAMA5_EBICS3_SIZE
+	int "CS3 Memory size"
+	default 0
+	---help---
+		Mapped size of the memory region at CS3.
+
+choice
+	prompt "CS3 Memory Type"
+	default SAMA5_EBICS3_NOR
+	---help---
+		Select the type of memory present on CS3
+
+config SAMA5_EBICS3_SRAM
+	bool "SRAM"
+
+config SAMA5_EBICS3_PSRAM
+	bool "PSRAM"
+
+config SAMA5_EBICS3_PROM
+	bool "PROM"
+
+config SAMA5_EBICS3_EEPROM
+	bool "EEPROM"
+
+config SAMA5_EBICS3_EPROM
+	bool "EPROM"
+
+config SAMA5_EBICS3_LCD
+	bool "LCD"
+
+config SAMA5_EBICS3_NOR
+	bool "NOR Flash"
+
+config SAMA5_EBICS3_NAND
+	bool "NAND Flash"
+
+endchoice # CS3 Memory Type
+endif # SAMA5_EBICS3
+endmenu # External Memory Configuration
 
 choice
 	prompt "SAMA5 Boot Configuration"
-	default SAMA5_BOOT_SRAM
+	default SAMA5_BOOT_ISRAM
 	---help---
 		The startup code needs to know if the code is running from internal SRAM,
 		external SRAM, or CS0-3 in order to initialize properly.  Note that the
-		boot device is not specified for cases where the code is copied into SRAM;
+		boot device is not specified for cases where the code is copied into
-		those cases are all covered by SAMA5_BOOT_SRAM.
+		internal SRAM; those cases are all covered by SAMA5_BOOT_ISRAM.
 
-config SAMA5_BOOT_SRAM
+config SAMA5_BOOT_ISRAM
 	bool "Running from internal SRAM"
 
 config SAMA5_BOOT_SDRAM
 	bool "Running from external SDRAM"
+	depends on SAMA5_DDRCS
 
 config SAMA5_BOOT_CS0FLASH
 	bool "Running in external FLASH CS0"
+	depends on SAMA5_EBICS0_NOR
+
+config SAMA5_BOOT_CS0SRAM
+	bool "Running in external FLASH CS0"
+	depends on SAMA5_EBICS0_SRAM || SAMA5_EBICS0_PSRAM
 
 config SAMA5_BOOT_CS1FLASH
 	bool "Running in external FLASH CS1"
+	depends on SAMA5_EBICS1_NOR
+
+config SAMA5_BOOT_CS1SRAM
+	bool "Running in external FLASH CS1"
+	depends on SAMA5_EBICS1_SRAM || SAMA5_EBICS1_PSRAM
 
 config SAMA5_BOOT_CS2FLASH
 	bool "Running in external FLASH CS2"
+	depends on SAMA5_EBICS2_NOR
 
-config SAMA5_BOOT_CS3FLASH
+config SAMA5_BOOT_CS2SRAM
+	bool "Running in external FLASH CS2"
+	depends on SAMA5_EBICS2_SRAM || SAMA5_EBICS2_PSRAM
+
+config SAMA5_BOOT_CS2FLASH
 	bool "Running in external FLASH CS3"
+	depends on SAMA5_EBICS3_NOR
 
-endchoice
+config SAMA5_BOOT_CS3SRAM
+	bool "Running in external FLASH CS3"
+	depends on SAMA5_EBICS3_SRAM || SAMA5_EBICS3_PSRAM
 
-endif
+endchoice # SAMA5 Boot Configuration
+
+menu "Heap Configuration"
+
+config SAMA5_ISRAM_HEAP
+	bool "Include ISRAM in heap"
+	default y
+	depends on !SAMA5_BOOT_ISRAM
+	---help---
+		Include the internal SRAM memory in the heap.
+
+		NOTE:  MM_REGIONS must also be set to indicate the total number of
+		memory regions to be added to the heap.
+
+		*** DO NOT SELECT THIS OPTION IF YOU ARE EXECUTING FROM INTERNAL SRAM!!**
+		In this case, the remaining ISRAM will automatically be added to the
+		heap (using DRAM_END).
+
+config SAMA5_DDRCS_HEAP
+	bool "Include DDR-SDRAM in heap"
+	default y
+	depends on SAMA5_DDRCS && !SAMA5_BOOT_SDRAM
+	---help---
+		Include the DDR-SDRAM memory in the heap.
+
+		NOTE:  MM_REGIONS must also be set to indicate the total number of
+		memory regions to be added to the heap.
+
+		*** DO NOT SELECT THIS OPTION IF YOU ARE EXECUTING FROM SDRAM!!**
+		In this case, the remaining SDRAM will automatically be added to the
+		heap (using DRAM_END)
+
+config SAMA5_EBICS0_HEAP
+	bool "Include SRAM/PSRAM in heap"
+	default y
+	depends on (SAMA5_EBICS0_SRAM || SAMA5_EBICS0_PSRAM) && !SAMA5_BOOT_CS0SRAM
+	---help---
+		Include the CS0 SRAM/PSREAM memory in the heap.
+
+		NOTE:  MM_REGIONS must also be set to indicate the total number of
+		memory regions to be added to the heap.
+
+		*** DO NOT SELECT THIS OPTION IF YOU ARE EXECUTING FROM CS0 SRAM!!**
+		In this case, the remaining SRAM will automatically be added to the
+		heap (using DRAM_END).
+
+config SAMA5_EBICS1_HEAP
+	bool "Include SRAM/PSRAM in heap"
+	default y
+	depends on (SAMA5_EBICS1_SRAM || SAMA5_EBICS1_PSRAM) && !SAMA5_BOOT_CS1SRAM
+	---help---
+		Include the CS1 SRAM/PSREAM memory in the heap.
+
+		NOTE:  MM_REGIONS must also be set to indicate the total number of
+		memory regions to be added to the heap.
+
+		*** DO NOT SELECT THIS OPTION IF YOU ARE EXECUTING FROM CS1 SRAM!!**
+		In this case, the remaining SRAM will automatically be added to the
+		heap (using DRAM_END).
+
+config SAMA5_EBICS2_HEAP
+	bool "Include SRAM/PSRAM in heap"
+	default y
+	depends on (SAMA5_EBICS2_SRAM || SAMA5_EBICS2_PSRAM) && !SAMA5_BOOT_CS2SRAM
+	---help---
+		Include the CS2 SRAM/PSREAM memory in the heap.
+
+		NOTE:  MM_REGIONS must also be set to indicate the total number of
+		memory regions to be added to the heap.
+
+		*** DO NOT SELECT THIS OPTION IF YOU ARE EXECUTING FROM CS2 SRAM!!**
+		In this case, the remaining SRAM will automatically be added to the
+		heap (using DRAM_END).
+
+config SAMA5_EBICS3_HEAP
+	bool "Include SRAM/PSRAM in heap"
+	default y
+	depends on (SAMA5_EBICS3_SRAM || SAMA5_EBICS3_PSRAM) && !SAMA5_BOOT_CS3SRAM
+	---help---
+		Include the CS3 SRAM/PSREAM memory in the heap.
+
+		*** DO NOT SELECT THIS OPTION IF YOU ARE EXECUTING FROM CS3 SRAM!!**
+		In this case, the remaining SRAM will automatically be added to the
+		heap (using DRAM_END).
+
+endmenu # Heap Configuration
+endif # ARCH_CHIP_SAMA5

arch/arm/src/sama5/Make.defs

@@ -43,7 +43,6 @@ CMN_CSRCS  = up_initialize.c up_idle.c up_interruptcontext.c up_exit.c
 CMN_CSRCS += up_createstack.c up_releasestack.c up_usestack.c up_vfork.c
 CMN_CSRCS += up_mdelay.c up_udelay.c
 CMN_CSRCS += up_modifyreg8.c up_modifyreg16.c up_modifyreg32.c
-CMN_CSRCS += up_allocateheap.c
 
 CMN_CSRCS += arm_assert.c arm_blocktask.c arm_copyfullstate.c arm_dataabort.c
 CMN_CSRCS += arm_doirq.c arm_initialstate.c arm_prefetchabort.c
@@ -67,5 +66,5 @@ endif
 
 CHIP_ASRCS  =
 
-CHIP_CSRCS  = sam_boot.c sam_clockconfig.c sam_gpio.c sam_irq.c
+CHIP_CSRCS  = sam_allocateheap.c sam_boot.c sam_clockconfig.c sam_gpio.c
-CHIP_CSRCS += sam_lowputc.c sam_serial.c sam_timerisr.c
+CHIP_CSRCS += sam_irq.c sam_lowputc.c sam_serial.c sam_timerisr.c

arch/arm/src/sama5/chip/sama5d3x_memorymap.h

@@ -210,11 +210,11 @@
 #define SAM_AXIMX_NSECTIONS      _NSECTIONS(SAM_AXIMX_SIZE)
 #define SAM_DAP_NSECTIONS        _NSECTIONS(SAM_DAP_SIZE)
 
-#define SAM_EBICS0_NSECTIONS     _NSECTIONS(CONFIG_SAMA5_EBISC0_SIZE)
+#define SAM_EBICS0_NSECTIONS     _NSECTIONS(CONFIG_SAMA5_EBICS0_SIZE)
 #define SAM_DDRCS_NSECTIONS      _NSECTIONS(CONFIG_SAMA5_DDRCS_SIZE)
-#define SAM_EBICS1_NSECTIONS     _NSECTIONS(CONFIG_SAMA5_EBISC1_SIZE)
+#define SAM_EBICS1_NSECTIONS     _NSECTIONS(CONFIG_SAMA5_EBICS1_SIZE)
-#define SAM_EBICS2_NSECTIONS     _NSECTIONS(CONFIG_SAMA5_EBISC2_SIZE)
+#define SAM_EBICS2_NSECTIONS     _NSECTIONS(CONFIG_SAMA5_EBICS2_SIZE)
-#define SAM_EBICS3_NSECTIONS     _NSECTIONS(CONFIG_SAMA5_EBISC3_SIZE)
+#define SAM_EBICS3_NSECTIONS     _NSECTIONS(CONFIG_SAMA5_EBICS3_SIZE)
 #define SAM_NFCCR_NSECTIONS      _NSECTIONS(SAM_NFCCR_SIZE)
 
 #define SAM_PERIPHA_NSECTIONS    _NSECTIONS(SAM_PERIPHA_SIZE)

arch/arm/src/sama5/sam_allocateheap.c

@@ -0,0 +1,368 @@
+/****************************************************************************
+ * arch/arm/src/sama5/sam_allocateheap.c
+ *
+ *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <assert.h>
+#include <debug.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/userspace.h>
+
+#include <arch/board/board.h>
+
+#include "up_arch.h"
+#include "up_internal.h"
+
+/****************************************************************************
+ * Private Definitions
+ ****************************************************************************/
+/* We cannot use the memory for heap if it is not enabled.  Or, if it is
+ * enabled, but does not hold SDRAM, SRAM, or PSRAM.
+ *
+ * We cannot add the region if it is if we are executing from it!  In that
+ * case, the remainder of the memory will automatically be added to the heap
+ * based on g_idle_topstack and CONFIG_DRAM_END
+ */
+
+#if defined(CONFIG_SAMA5_BOOT_ISRAM)
+#  undef CONFIG_SAMA5_ISRAM_HEAP
+#endif
+
+#if !defined(CONFIG_SAMA5_DDRCS) || defined(CONFIG_SAMA5_BOOT_SDRAM)
+#  undef CONFIG_SAMA5_DDRCS_HEAP
+#endif
+
+#if !defined(CONFIG_SAMA5_EBICS0) || defined(CONFIG_SAMA5_BOOT_CS0SRAM) || \
+   (!defined(CONFIG_SAMA5_EBICS0_SRAM) && !defined(CONFIG_SAMA5_EBICS0_PSRAM))
+   
+#  undef SAMA5_EBICS0_HEAP
+#endif
+
+#if !defined(CONFIG_SAMA5_EBICS1) || defined(CONFIG_SAMA5_BOOT_CS1SRAM) || \
+   (!defined(CONFIG_SAMA5_EBICS1_SRAM) && !defined(CONFIG_SAMA5_EBICS1_PSRAM))
+   
+#  undef SAMA5_EBICS1_HEAP
+#endif
+
+#if !defined(CONFIG_SAMA5_EBICS2) || defined(CONFIG_SAMA5_BOOT_CS2SRAM) || \
+   (!defined(CONFIG_SAMA5_EBICS2_SRAM) && !defined(CONFIG_SAMA5_EBICS2_PSRAM))
+   
+#  undef SAMA5_EBICS2_HEAP
+#endif
+
+#if !defined(SAMA5_CONFIG_EBICS3) || defined(CONFIG_SAMA5_BOOT_CS3SRAM) || \
+   (!defined(SAMA5_CONFIG_EBICS3_SRAM) && !defined(CONFIG_SAMA5_EBICS3_PSRAM))
+   
+#  undef SAMA5_EBICS3_HEAP
+#endif
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_allocate_heap
+ *
+ * Description:
+ *   This function will be called to dynamically set aside the heap region.
+ *
+ *   For the kernel build (CONFIG_NUTTX_KERNEL=y) with both kernel- and
+ *   user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function provides the
+ *   size of the unprotected, user-space heap.
+ *
+ *   If a protected kernel-space heap is provided, the kernel heap must be
+ *   allocated by an analogous up_allocate_kheap(). A custom version of this
+ *   file is needed if memory protection of the kernel heap is required.
+ *
+ *   The following memory map is assumed for the flat build:
+ *
+ *     .data region.  Size determined at link time.
+ *     .bss  region  Size determined at link time.
+ *     IDLE thread stack.  Size determined by CONFIG_IDLETHREAD_STACKSIZE.
+ *     Heap.  Extends to the end of SRAM.
+ *
+ *   The following memory map is assumed for the kernel build:
+ *
+ *     Kernel .data region.  Size determined at link time.
+ *     Kernel .bss  region  Size determined at link time.
+ *     Kernel IDLE thread stack.  Size determined by CONFIG_IDLETHREAD_STACKSIZE.
+ *     Padding for alignment
+ *     User .data region.  Size determined at link time.
+ *     User .bss region  Size determined at link time.
+ *     Kernel heap.  Size determined by CONFIG_MM_KERNEL_HEAPSIZE.
+ *     User heap.  Extends to the end of SRAM.
+ *
+ ****************************************************************************/
+
+void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
+{
+#if defined(CONFIG_NUTTX_KERNEL) && defined(CONFIG_MM_KERNEL_HEAP)
+  /* Get the unaligned size and position of the user-space heap.
+   * This heap begins after the user-space .bss section at an offset
+   * of CONFIG_MM_KERNEL_HEAPSIZE (subject to alignment).
+   */
+
+  uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + CONFIG_MM_KERNEL_HEAPSIZE;
+  size_t    usize = CONFIG_DRAM_END - ubase;
+  int       log2;
+
+  DEBUGASSERT(ubase < (uintptr_t)CONFIG_DRAM_END);
+
+  /* Return the user-space heap settings */
+
+  up_ledon(LED_HEAPALLOCATE);
+  *heap_start = (FAR void*)ubase;
+  *heap_size  = usize;
+#else
+
+  /* Return the heap settings */
+
+  up_ledon(LED_HEAPALLOCATE);
+  *heap_start = (FAR void*)g_idle_topstack;
+  *heap_size  = CONFIG_DRAM_END - g_idle_topstack;
+#endif
+}
+
+/****************************************************************************
+ * Name: up_allocate_kheap
+ *
+ * Description:
+ *   For the kernel build (CONFIG_NUTTX_KERNEL=y) with both kernel- and
+ *   user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function allocates
+ *   the kernel-space heap.  A custom version of this function is need if
+ *   memory protection of the kernel heap is required.
+ *
+ ****************************************************************************/
+
+#if defined(CONFIG_NUTTX_KERNEL) && defined(CONFIG_MM_KERNEL_HEAP)
+void up_allocate_kheap(FAR void **heap_start, size_t *heap_size)
+{
+  /* Get the unaligned size and position of the user-space heap.
+   * This heap begins after the user-space .bss section at an offset
+   * of CONFIG_MM_KERNEL_HEAPSIZE (subject to alignment).
+   */
+
+  uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + CONFIG_MM_KERNEL_HEAPSIZE;
+  size_t    usize = CONFIG_DRAM_END - ubase;
+  int       log2;
+
+  DEBUGASSERT(ubase < (uintptr_t)CONFIG_DRAM_END);
+
+  /* Return the kernel heap settings (i.e., the part of the heap region
+   * that was not dedicated to the user heap).
+   */
+
+  *heap_start = (FAR void*)USERSPACE->us_bssend;
+  *heap_size  = ubase - (uintptr_t)USERSPACE->us_bssend;
+}
+#endif
+
+/****************************************************************************
+ * Name: up_addregion
+ *
+ * Description:
+ *   Memory may be added in non-contiguous chunks.  Additional chunks are
+ *   added by calling this function.
+ *
+ ****************************************************************************/
+
+#if CONFIG_MM_REGIONS > 1
+void up_addregion(void)
+{
+  int nregions = CONFIG_MM_REGIONS;
+  size_t size;
+
+#ifdef CONFIG_SAMA5_ISRAM_HEAP
+#if defined(CONFIG_NUTTX_KERNEL) && defined(CONFIG_MM_KERNEL_HEAP)
+
+  /* Allow user-mode access to the ISRAM heap */
+
+  size = SAM_ISRAM0_SIZE + SAM_ISRAM1_SIZE;
+  sam_uheap((uintptr_t)SAM_ISRAM0_VADDR, size);
+
+#endif
+
+  /* Add the ISRAM user heap region. */
+
+  kumm_addregion((FAR void*)SAM_ISRAM0_VADDR, size);
+
+  nregions--;
+#endif
+
+#ifdef CONFIG_SAMA5_DDRCS_HEAP
+  if (nregions > 0)
+    {
+#if defined(CONFIG_NUTTX_KERNEL) && defined(CONFIG_MM_KERNEL_HEAP)
+      /* Allow user-mode access to the ISRAM heap */
+
+      size = CONFIG_SAMA5_DDRCS_SIZE;
+      sam_uheap((uintptr_t)SAM_DDRCS_VSECTION, size);
+#endif
+
+      /* Add the ISRAM user heap region. */
+
+      kumm_addregion((FAR void*)SAM_DDRCS_VSECTION, size);
+
+      nregions--;
+    }
+  else
+    {
+      lldbg("ERROR: SDRAM memory not added to heap.  CONFIG_MM_NREGIONS=%d\n",
+            CONFIG_MM_REGIONS);
+      lldbg("       Increase the size of CONFIG_MM_NREGIONS\n");
+    }
+#endif
+
+#ifdef SAMA5_EBICS0_HEAP
+  if (nregions > 0)
+    {
+#if defined(CONFIG_NUTTX_KERNEL) && defined(CONFIG_MM_KERNEL_HEAP)
+      /* Allow user-mode access to the ISRAM heap */
+
+      size = CONFIG_SAMA5_EBICS0_SIZE;
+      sam_uheap((uintptr_t)SAM_EBICS0_VSECTION, size);
+#endif
+
+      /* Add the ISRAM user heap region. */
+
+      kumm_addregion((FAR void*)SAM_EBICS0_VSECTION, size);
+
+      nregions--;
+    }
+  else
+    {
+      lldbg("ERROR: CS0 memory not added to heap.  CONFIG_MM_NREGIONS=%d\n",
+            CONFIG_MM_REGIONS);
+      lldbg("       Increase the size of CONFIG_MM_NREGIONS\n");
+    }
+#endif
+
+#ifdef SAMA5_EBICS1_HEAP
+  if (nregions > 0)
+    {
+#if defined(CONFIG_NUTTX_KERNEL) && defined(CONFIG_MM_KERNEL_HEAP)
+      /* Allow user-mode access to the ISRAM heap */
+
+      size = CONFIG_SAMA5_EBICS1_SIZE;
+      sam_uheap((uintptr_t)SAM_EBICS1_VSECTION, size);
+#endif
+
+      /* Add the ISRAM user heap region. */
+
+      kumm_addregion((FAR void*)SAM_EBICS1_VSECTION, size);
+
+      nregions--;
+    }
+  else
+    {
+      lldbg("ERROR: CS1 memory not added to heap.  CONFIG_MM_NREGIONS=%d\n",
+            CONFIG_MM_REGIONS);
+      lldbg("       Increase the size of CONFIG_MM_NREGIONS\n");
+    }
+#endif
+
+#ifdef SAMA5_EBICS2_HEAP
+  if (nregions > 0)
+    {
+#if defined(CONFIG_NUTTX_KERNEL) && defined(CONFIG_MM_KERNEL_HEAP)
+      /* Allow user-mode access to the ISRAM heap */
+
+      size = CONFIG_SAMA5_EBICS2_SIZE;
+      sam_uheap((uintptr_t)SAM_EBICS2_VSECTION, size);
+#endif
+
+      /* Add the ISRAM user heap region. */
+
+      kumm_addregion((FAR void*)SAM_EBICS2_VSECTION, size);
+
+      nregions--;
+    }
+  else
+    {
+      lldbg("ERROR: CS2 memory not added to heap.  CONFIG_MM_NREGIONS=%d\n",
+            CONFIG_MM_REGIONS);
+      lldbg("       Increase the size of CONFIG_MM_NREGIONS\n");
+    }
+#endif
+
+#ifdef SAMA5_EBICS3_HEAP
+  if (nregions > 0)
+    {
+#if defined(CONFIG_NUTTX_KERNEL) && defined(CONFIG_MM_KERNEL_HEAP)
+      /* Allow user-mode access to the ISRAM heap */
+
+      size = CONFIG_SAMA5_EBICS3_SIZE;
+      sam_uheap((uintptr_t)SAM_EBICS3_VSECTION, size);
+#endif
+
+      /* Add the ISRAM user heap region. */
+
+      kumm_addregion((FAR void*)SAM_EBICS3_VSECTION, size);
+
+      nregions--;
+    }
+  else
+    {
+      lldbg("ERROR: CS3 memory not added to heap.  CONFIG_MM_NREGIONS=%d\n",
+            CONFIG_MM_REGIONS);
+      lldbg("       Increase the size of CONFIG_MM_NREGIONS\n");
+    }
+#endif
+
+  /* Did we add all of the requestion regions */
+
+  if (nregions > 0)
+    {
+      lldbg("ERROR: Not all regions added to heap: %d added, but CONFIG_MM_NREGIONS=%d\n",
+            CONFIG_MM_REGIONS - nregions, CONFIG_MM_REGIONS);
+      lldbg("       Decrease the size of CONFIG_MM_NREGIONS\n");
+    }
+}
+#endif

arch/arm/src/sama5/sam_boot.c

@@ -120,7 +120,7 @@ static const struct section_mapping_s section_mapping[] =
 
 /* SAMA5 External Memories */
 
-#ifdef CONFIG_SAMA5_EBISC0
+#ifdef CONFIG_SAMA5_EBICS0
   { SAM_EBICS0_PSECTION, SAM_EBICS0_VSECTION, 
     SAM_EBICS0_MMUFLAGS, SAM_EBICS0_NSECTIONS},
 #endif
@@ -128,15 +128,15 @@ static const struct section_mapping_s section_mapping[] =
   { SAM_DDRCS_PSECTION, SAM_DDRCS_VSECTION, 
     SAM_DDRCS_MMUFLAGS, SAM_DDRCS_NSECTIONS},
 #endif
-#ifdef CONFIG_SAMA5_EBISC1
+#ifdef CONFIG_SAMA5_EBICS1
   { SAM_EBICS1_PSECTION, SAM_EBICS1_VSECTION, 
     SAM_EBICS1_MMUFLAGS, SAM_EBICS1_NSECTIONS},
 #endif
-#ifdef CONFIG_SAMA5_EBISC2
+#ifdef CONFIG_SAMA5_EBICS2
   { SAM_EBICS2_PSECTION, SAM_EBICS2_VSECTION, 
     SAM_EBICS2_MMUFLAGS, SAM_EBICS2_NSECTIONS},
 #endif
-#ifdef CONFIG_SAMA5_EBISC3
+#ifdef CONFIG_SAMA5_EBICS3
   { SAM_EBICS3_PSECTION, SAM_EBICS3_VSECTION, 
     SAM_EBICS3_MMUFLAGS, SAM_EBICS3_NSECTIONS},
 #endif

arch/arm/src/sama5/sam_clockconfig.c

@@ -464,7 +464,7 @@ void sam_clockconfig(void)
 
 #ifdef CONFIG_SAMA5_BOOT_CS0FLASH
   if (config)
-#if define(CONFIG_SAMA5_BOOT_SRAM) || defined(CONFIG_SAMA5_BOOT_CS0FLASH)
+#if define(CONFIG_SAMA5_BOOT_ISRAM) || defined(CONFIG_SAMA5_BOOT_CS0FLASH)
     {
       /* Enable main oscillator (if it has not already been selected) */
 
@@ -501,6 +501,6 @@ void sam_clockconfig(void)
 
       sam_upllsetup();
     }
-#endif /* CONFIG_SAMA5_BOOT_SRAM || CONFIG_SAMA5_BOOT_CS0FLASH */
+#endif /* CONFIG_SAMA5_BOOT_ISRAM || CONFIG_SAMA5_BOOT_CS0FLASH */
 #endif /* CONFIG_SAMA5_BOOT_CS0FLASH */
 }