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arch: mips: nxstyle fixes

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fixes for errors reported by nxstyle

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
This commit is contained in:
Alin Jerpelea
2021-04-08 11:04:28 +02:00
committed by Alan Carvalho de Assis
parent 63ca633aef
commit 628d8ca9e1
1 changed files with 200 additions and 195 deletions
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arch/mips/src/pic32mz/pic32mz_excptmacros.h
+31 -26
View File
@@ -99,12 +99,13 @@
rdpgpr sp, sp
#endif
/* "When entering the interrupt handler routine, the interrupt controller must first
* save the current priority and exception PC counter from Interrupt Priority (IPL)
* bits (Status<15:10>) and the ErrorEPC register, respectively, on the stack. ..."
/* "When entering the interrupt handler routine, the interrupt controller
* must first save the current priority and exception PC counter from
* Interrupt Priority (IPL) bits (Status<15:10>) and the ErrorEPC
* register, respectively, on the stack. ..."
*/
#ifdef CONFIG_PIC32MZ_NESTED_INTERRUPTS // Does not work!
#ifdef CONFIG_PIC32MZ_NESTED_INTERRUPTS /* Does not work! */
mfc0 k0, MIPS32_CP0_CAUSE
mfc0 k1, MIPS32_CP0_EPC
@@ -112,8 +113,8 @@
srl k0, k0, CP0_CAUSE_IP_SHIFT
/* Create the register context stack frame large enough to hold the entire register save
* array.
/* Create the register context stack frame large enough to hold the entire
* register save array.
*/
addiu sp, sp, -XCPTCONTEXT_SIZE
@@ -124,8 +125,9 @@
mfc0 k1, MIPS32_CP0_STATUS
sw k1, REG_STATUS(sp)
/* Then insert pending interrupt level as the current mask level in the CP0 status
* register. Also clear bits 1-4 in new value of the status register:
/* Then insert pending interrupt level as the current mask level in the CP0
* status register.
* Also clear bits 1-4 in new value of the status register:
*
* Bit 1: Exception Level
* Bit 2: Error Level
@@ -140,15 +142,15 @@
mtc0 k1, MIPS32_CP0_STATUS
#else
/* Get the EPC and STATUS register (Don't bother with the CAUSE register if we are
* not supporting nested interrupts)
/* Get the EPC and STATUS register (Don't bother with the CAUSE register if
* we are not supporting nested interrupts)
*/
mfc0 k0, MIPS32_CP0_EPC
mfc0 k1, MIPS32_CP0_STATUS
/* Create the register context stack frame large enough to hold the entire register
* save array.
/* Create the register context stack frame large enough to hold the entire
* register save array.
*/
addiu sp, sp, -XCPTCONTEXT_SIZE
@@ -167,6 +169,7 @@
sw k0, REG_MFLO(sp)
/* Save general purpose registers */
/* $1: at_reg, assembler temporary */
sw $1, REG_AT(sp)
@@ -210,11 +213,11 @@
sw t8, REG_T8(sp)
sw t9, REG_T9(sp)
/* $26-$27 = ko-k1: Reserved for use in exception handers. These do not need to be
* saved.
/* $26-$27 = ko-k1: Reserved for use in exception handers. These do
* not need to be saved.
*
* $28 = gp: Only needs to be saved under conditions where there are multiple, per-
* thread values for the GP.
* $28 = gp: Only needs to be saved under conditions where there are
* multiple, per- thread values for the GP.
*/
#ifdef MIPS32_SAVE_GP
@@ -259,8 +262,8 @@
.macro EXCPT_EPILOGUE, regs
.set noat
/* Since interrupts are disabled via di can now use k0 and k1 again. Use k1 as the
* pointer to the register save array.
/* Since interrupts are disabled via di can now use k0 and k1 again. Use
* k1 as the pointer to the register save array.
*/
move k1, \regs
@@ -273,6 +276,7 @@
mthi k0
/* Restore general purpose registers */
/* $1: at_reg, assembler temporary */
lw $1, REG_AT(k1)
@@ -316,11 +320,11 @@
lw t8, REG_T8(k1)
lw t9, REG_T9(k1)
/* $26-$27 = ko-k1: Reserved for use in exception handers. These do not need to be
* saved.
/* $26-$27 = ko-k1: Reserved for use in exception handers. These do
* not need to be saved.
*
* $28 = gp: Only needs to be saved under conditions where there are multiple, per-
* thread values for the GP.
* $28 = gp: Only needs to be saved under conditions where there are
* multiple, per- thread values for the GP.
*/
#ifdef MIPS32_SAVE_GP
@@ -362,8 +366,8 @@
* All interrupts should still be disabled.
*
* At completion:
* If the nesting level is 0, then (1) the user stack pointer is saved at the base of the
* interrupt stack and sp points to the interrupt stack.
* If the nesting level is 0, then (1) the user stack pointer is saved at
* the base of the interrupt stack and sp points to the interrupt stack.
* The values of tmp1, tmp2, tmp3, and sp have been altered
*
****************************************************************************/
@@ -383,8 +387,8 @@
nop
#endif
/* Use the interrupt stack, pushing the user stack pointer onto the interrupt
* stack first.
/* Use the interrupt stack, pushing the user stack pointer onto the
* interrupt stack first.
*/
la \tmp3, g_intstackbase
@@ -394,6 +398,7 @@
#ifdef CONFIG_PIC32MZ_NESTED_INTERRUPTS
1:
/* Increment the interrupt nesting level */
addiu \tmp2, \tmp2, 1