diff --git a/configs/fire-stm32v2/src/stm32_selectlcd.c b/configs/fire-stm32v2/src/stm32_selectlcd.c
index 273dedf28bd..209d0e9205b 100644
--- a/configs/fire-stm32v2/src/stm32_selectlcd.c
+++ b/configs/fire-stm32v2/src/stm32_selectlcd.c
@@ -193,7 +193,7 @@ void stm32_selectlcd(void)
 
   /* Bank1 NOR/SRAM timing register configuration */
 
-  putreg32(FSMC_BTR_ADDSET(1)|FSMC_BTR_ADDHLD(0)|FSMC_BTR_DATAST(2)|FSMC_BTR_BUSTRUN(0)|
+  putreg32(FSMC_BTR_ADDSET(1)|FSMC_BTR_ADDHLD(0)|FSMC_BTR_DATAST(2)|FSMC_BTR_BUSTURN(0)|
            FSMC_BTR_CLKDIV(0)|FSMC_BTR_DATLAT(0)|FSMC_BTR_ACCMODA, STM32_FSMC_BTR1);
 
   putreg32(0xffffffff, STM32_FSMC_BWTR4);
diff --git a/configs/hymini-stm32v/src/stm32_r61505u.c b/configs/hymini-stm32v/src/stm32_r61505u.c
index c519abb0579..23727c2e05f 100644
--- a/configs/hymini-stm32v/src/stm32_r61505u.c
+++ b/configs/hymini-stm32v/src/stm32_r61505u.c
@@ -353,7 +353,7 @@ static void stm32_selectlcd(void)
   /* Bank1 NOR/SRAM timing register configuration */
 
   putreg32(
-      FSMC_BTR_ADDSET(2)|FSMC_BTR_ADDHLD(0)|FSMC_BTR_DATAST(2)|FSMC_BTR_BUSTRUN(0)|
+      FSMC_BTR_ADDSET(2)|FSMC_BTR_ADDHLD(0)|FSMC_BTR_DATAST(2)|FSMC_BTR_BUSTURN(0)|
       FSMC_BTR_CLKDIV(0)|FSMC_BTR_DATLAT(0)|FSMC_BTR_ACCMODA,
       STM32_FSMC_BTR1);
 
diff --git a/configs/hymini-stm32v/src/stm32_ssd1289.c b/configs/hymini-stm32v/src/stm32_ssd1289.c
index faa37bc8735..bdabbcf88d9 100644
--- a/configs/hymini-stm32v/src/stm32_ssd1289.c
+++ b/configs/hymini-stm32v/src/stm32_ssd1289.c
@@ -406,7 +406,7 @@ static void stm32_selectlcd(void)
   /* Bank1 NOR/SRAM timing register configuration */
 
   putreg32(
-      FSMC_BTR_ADDSET(1)|FSMC_BTR_ADDHLD(0)|FSMC_BTR_DATAST(2)|FSMC_BTR_BUSTRUN(0)| FSMC_BTR_CLKDIV(0)|FSMC_BTR_DATLAT(0)|FSMC_BTR_ACCMODA,
+      FSMC_BTR_ADDSET(1)|FSMC_BTR_ADDHLD(0)|FSMC_BTR_DATAST(2)|FSMC_BTR_BUSTURN(0)| FSMC_BTR_CLKDIV(0)|FSMC_BTR_DATLAT(0)|FSMC_BTR_ACCMODA,
       STM32_FSMC_BTR1);
 
   /* As ext mode is not active the write timing is ignored!! */
diff --git a/configs/stm3210e-eval/src/stm32_selectlcd.c b/configs/stm3210e-eval/src/stm32_selectlcd.c
index 003caef8517..cead59ae571 100644
--- a/configs/stm3210e-eval/src/stm32_selectlcd.c
+++ b/configs/stm3210e-eval/src/stm32_selectlcd.c
@@ -130,7 +130,7 @@ void stm32_selectlcd(void)
 
   /* Bank4 NOR/SRAM timing register configuration */
 
-  putreg32(FSMC_BTR_ADDSET(1)|FSMC_BTR_ADDHLD(0)|FSMC_BTR_DATAST(2)|FSMC_BTR_BUSTRUN(0)|
+  putreg32(FSMC_BTR_ADDSET(1)|FSMC_BTR_ADDHLD(0)|FSMC_BTR_DATAST(2)|FSMC_BTR_BUSTURN(0)|
            FSMC_BTR_CLKDIV(0)|FSMC_BTR_DATLAT(0)|FSMC_BTR_ACCMODA, STM32_FSMC_BTR4);
 
   putreg32(0xffffffff, STM32_FSMC_BWTR4);
diff --git a/configs/stm3210e-eval/src/stm32_selectnor.c b/configs/stm3210e-eval/src/stm32_selectnor.c
index aa754a97a72..3d16203c073 100644
--- a/configs/stm3210e-eval/src/stm32_selectnor.c
+++ b/configs/stm3210e-eval/src/stm32_selectnor.c
@@ -127,7 +127,7 @@ void stm32_selectnor(void)
 
   /* Bank1 NOR/SRAM timing register configuration */
 
-  putreg32(FSMC_BTR_ADDSET(3)|FSMC_BTR_ADDHLD(1)|FSMC_BTR_DATAST(6)|FSMC_BTR_BUSTRUN(1)|
+  putreg32(FSMC_BTR_ADDSET(3)|FSMC_BTR_ADDHLD(1)|FSMC_BTR_DATAST(6)|FSMC_BTR_BUSTURN(1)|
            FSMC_BTR_CLKDIV(1)|FSMC_BTR_DATLAT(2)|FSMC_BTR_ACCMODB, STM32_FSMC_BTR2);
 
   putreg32(0x0fffffff, STM32_FSMC_BWTR2);
diff --git a/configs/stm3210e-eval/src/stm32_selectsram.c b/configs/stm3210e-eval/src/stm32_selectsram.c
index b59e68e762c..305f29e8eb1 100644
--- a/configs/stm3210e-eval/src/stm32_selectsram.c
+++ b/configs/stm3210e-eval/src/stm32_selectsram.c
@@ -130,7 +130,7 @@ void stm32_selectsram(void)
 
   /* Bank1 NOR/SRAM timing register configuration */
 
-  putreg32(FSMC_BTR_ADDSET(1)|FSMC_BTR_ADDHLD(1)|FSMC_BTR_DATAST(3)|FSMC_BTR_BUSTRUN(1)|
+  putreg32(FSMC_BTR_ADDSET(1)|FSMC_BTR_ADDHLD(1)|FSMC_BTR_DATAST(3)|FSMC_BTR_BUSTURN(1)|
            FSMC_BTR_CLKDIV(1)|FSMC_BTR_DATLAT(2)|FSMC_BTR_ACCMODA, STM32_FSMC_BTR3);
 
   putreg32(0xffffffff, STM32_FSMC_BWTR3);
diff --git a/configs/stm3220g-eval/src/stm32_selectlcd.c b/configs/stm3220g-eval/src/stm32_selectlcd.c
index 67943bd32cd..4c7ad56d0c9 100644
--- a/configs/stm3220g-eval/src/stm32_selectlcd.c
+++ b/configs/stm3220g-eval/src/stm32_selectlcd.c
@@ -153,7 +153,7 @@ void stm32_selectlcd(void)
 
   /* Bank3 NOR/SRAM timing register configuration */
 
-  putreg32(FSMC_BTR_ADDSET(5) | FSMC_BTR_ADDHLD(0) | FSMC_BTR_DATAST(9) | FSMC_BTR_BUSTRUN(0) |
+  putreg32(FSMC_BTR_ADDSET(5) | FSMC_BTR_ADDHLD(0) | FSMC_BTR_DATAST(9) | FSMC_BTR_BUSTURN(0) |
            FSMC_BTR_CLKDIV(0) | FSMC_BTR_DATLAT(0) | FSMC_BTR_ACCMODA, STM32_FSMC_BTR3);
 
   putreg32(0xffffffff, STM32_FSMC_BWTR3);
diff --git a/configs/stm3220g-eval/src/stm32_selectsram.c b/configs/stm3220g-eval/src/stm32_selectsram.c
index c9abfd5f033..44247582f44 100644
--- a/configs/stm3220g-eval/src/stm32_selectsram.c
+++ b/configs/stm3220g-eval/src/stm32_selectsram.c
@@ -174,7 +174,7 @@ void stm32_selectsram(void)
   /* Bank1 NOR/SRAM timing register configuration */
 
   putreg32((FSMC_BTR_ADDSET(SRAM_ADDRESS_SETUP_TIME) | FSMC_BTR_ADDHLD(SRAM_ADDRESS_HOLD_TIME) |
-            FSMC_BTR_DATAST(SRAM_DATA_SETUP_TIME)    | FSMC_BTR_BUSTRUN(SRAM_BUS_TURNAROUND_DURATION) |
+            FSMC_BTR_DATAST(SRAM_DATA_SETUP_TIME)    | FSMC_BTR_BUSTURN(SRAM_BUS_TURNAROUND_DURATION) |
             FSMC_BTR_CLKDIV(SRAM_CLK_DIVISION)       | FSMC_BTR_DATLAT(SRAM_DATA_LATENCY) |
             FSMC_BTR_ACCMODA),
            STM32_FSMC_BTR2);
diff --git a/configs/stm3240g-eval/src/stm32_selectlcd.c b/configs/stm3240g-eval/src/stm32_selectlcd.c
index 0587cdd152c..d418a5fadb4 100644
--- a/configs/stm3240g-eval/src/stm32_selectlcd.c
+++ b/configs/stm3240g-eval/src/stm32_selectlcd.c
@@ -153,7 +153,7 @@ void stm32_selectlcd(void)
 
   /* Bank3 NOR/SRAM timing register configuration */
 
-  putreg32(FSMC_BTR_ADDSET(5) | FSMC_BTR_ADDHLD(0) | FSMC_BTR_DATAST(9) | FSMC_BTR_BUSTRUN(0) |
+  putreg32(FSMC_BTR_ADDSET(5) | FSMC_BTR_ADDHLD(0) | FSMC_BTR_DATAST(9) | FSMC_BTR_BUSTURN(0) |
            FSMC_BTR_CLKDIV(0) | FSMC_BTR_DATLAT(0) | FSMC_BTR_ACCMODA, STM32_FSMC_BTR3);
 
   putreg32(0xffffffff, STM32_FSMC_BWTR3);
diff --git a/configs/stm3240g-eval/src/stm32_selectsram.c b/configs/stm3240g-eval/src/stm32_selectsram.c
index 90f10154e13..fcbef4d9c81 100644
--- a/configs/stm3240g-eval/src/stm32_selectsram.c
+++ b/configs/stm3240g-eval/src/stm32_selectsram.c
@@ -174,7 +174,7 @@ void stm32_selectsram(void)
   /* Bank1 NOR/SRAM timing register configuration */
 
   putreg32((FSMC_BTR_ADDSET(SRAM_ADDRESS_SETUP_TIME) | FSMC_BTR_ADDHLD(SRAM_ADDRESS_HOLD_TIME) |
-            FSMC_BTR_DATAST(SRAM_DATA_SETUP_TIME)    | FSMC_BTR_BUSTRUN(SRAM_BUS_TURNAROUND_DURATION) |
+            FSMC_BTR_DATAST(SRAM_DATA_SETUP_TIME)    | FSMC_BTR_BUSTURN(SRAM_BUS_TURNAROUND_DURATION) |
             FSMC_BTR_CLKDIV(SRAM_CLK_DIVISION)       | FSMC_BTR_DATLAT(SRAM_DATA_LATENCY) |
             FSMC_BTR_ACCMODA),
            STM32_FSMC_BTR2);
diff --git a/configs/stm32f4discovery/src/stm32_ssd1289.c b/configs/stm32f4discovery/src/stm32_ssd1289.c
index 741a5b59099..588b9ee82bc 100644
--- a/configs/stm32f4discovery/src/stm32_ssd1289.c
+++ b/configs/stm32f4discovery/src/stm32_ssd1289.c
@@ -325,7 +325,7 @@ void stm32_selectlcd(void)
 
   /* Bank1 NOR/SRAM timing register configuration */
 
-  putreg32(FSMC_BTR_ADDSET(5) | FSMC_BTR_ADDHLD(0) | FSMC_BTR_DATAST(9) | FSMC_BTR_BUSTRUN(0) |
+  putreg32(FSMC_BTR_ADDSET(5) | FSMC_BTR_ADDHLD(0) | FSMC_BTR_DATAST(9) | FSMC_BTR_BUSTURN(0) |
            FSMC_BTR_CLKDIV(0) | FSMC_BTR_DATLAT(0) | FSMC_BTR_ACCMODA, STM32_FSMC_BTR1);
 
   putreg32(0xffffffff, STM32_FSMC_BWTR1);
diff --git a/configs/viewtool-stm32f107/src/stm32_ssd1289.c b/configs/viewtool-stm32f107/src/stm32_ssd1289.c
index 7e42cf854b5..c938e80852d 100644
--- a/configs/viewtool-stm32f107/src/stm32_ssd1289.c
+++ b/configs/viewtool-stm32f107/src/stm32_ssd1289.c
@@ -472,7 +472,7 @@ static void stm32_selectlcd(void)
   /* Bank1 NOR/SRAM timing register configuration */
 
   putreg32(
-      FSMC_BTR_ADDSET(1)|FSMC_BTR_ADDHLD(0)|FSMC_BTR_DATAST(2)|FSMC_BTR_BUSTRUN(0)| FSMC_BTR_CLKDIV(0)|FSMC_BTR_DATLAT(0)|FSMC_BTR_ACCMODA,
+      FSMC_BTR_ADDSET(1)|FSMC_BTR_ADDHLD(0)|FSMC_BTR_DATAST(2)|FSMC_BTR_BUSTURN(0)| FSMC_BTR_CLKDIV(0)|FSMC_BTR_DATLAT(0)|FSMC_BTR_ACCMODA,
       STM32_FSMC_BTR1);
 
   /* As ext mode is not active the write timing is ignored!! */