diff --git a/arch/arm/src/stm32/chip/stm32f33xxx_hrtim.h b/arch/arm/src/stm32/chip/stm32f33xxx_hrtim.h index 0bc6b93c5ef..fcf56524188 100644 --- a/arch/arm/src/stm32/chip/stm32f33xxx_hrtim.h +++ b/arch/arm/src/stm32/chip/stm32f33xxx_hrtim.h @@ -132,79 +132,6 @@ #define STM32_HRTIM_CMN_BDTEUPR_OFFSET 0x006C /* HRTIM Timer E Update Register */ #define STM32_HRTIM_CMN_BDMADR_OFFSET 0x0070 /* HRTIM DMA Data Register */ -/* Register Addresses *******************************************************************************/ - -/* HRTIM1 Timer A */ -/* remove ? */ - -#define STM32_HRTIM1_TIMERA_CR (STM32_HRTIM_TIM_CR_OFFSET+STM32_HRTIM1_TIMERA_BASE) -#define STM32_HRTIM1_TIMERA_ISR (STM32_HRTIM_TIM_ISR_OFFSET+STM32_HRTIM1_TIMERA_BASE) -#define STM32_HRTIM1_TIMERA_ICR (STM32_HRTIM_TIM_ICR_OFFSET+STM32_HRTIM1_TIMERA_BASE) -#define STM32_HRTIM1_TIMERA_DIER (STM32_HRTIM_TIM_DIER_OFFSET+STM32_HRTIM1_TIMERA_BASE) -#define STM32_HRTIM1_TIMERA_CNTR (STM32_HRTIM_TIM_CNTR_OFFSET+STM32_HRTIM1_TIMERA_BASE) -#define STM32_HRTIM1_TIMERA_PER (STM32_HRTIM_TIM_PER_OFFSET+STM32_HRTIM1_TIMERA_BASE) -#define STM32_HRTIM1_TIMERA_REP (STM32_HRTIM_TIM_REP_OFFSET+STM32_HRTIM1_TIMERA_BASE) -#define STM32_HRTIM1_TIMERA_CMP1R (STM32_HRTIM_TIM_CMP1R_OFFSET+STM32_HRTIM1_TIMERA_BASE) -#define STM32_HRTIM1_TIMERA_CMP1CR (STM32_HRTIM_TIM_CMP1CR_OFFSET+STM32_HRTIM1_TIMERA_BASE) -#define STM32_HRTIM1_TIMERA_CMP2R (STM32_HRTIM_TIM_CMP2R_OFFSET+STM32_HRTIM1_TIMERA_BASE) -#define STM32_HRTIM1_TIMERA_CMP3R (STM32_HRTIM_TIM_CMP3R_OFFSET+STM32_HRTIM1_TIMERA_BASE) -#define STM32_HRTIM1_TIMERA_CMP4R (STM32_HRTIM_TIM_CMP4R_OFFSET+STM32_HRTIM1_TIMERA_BASE) -#define STM32_HRTIM1_TIMERA_CPT1R (STM32_HRTIM_TIM_CMPT1R_OFFSET+STM32_HRTIM1_TIMERA_BASE) -#define STM32_HRTIM1_TIMERA_CPT2R (STM32_HRTIM_TIM_CMPT2R_OFFSET+STM32_HRTIM1_TIMERA_BASE) -#define STM32_HRTIM1_TIMERA_DTR (STM32_HRTIM_TIM_DTR_OFFSET+STM32_HRTIM1_TIMERA_BASE) -#define STM32_HRTIM1_TIMERA_SET1R (STM32_HRTIM_TIM_SET1R_OFFSET+STM32_HRTIM1_TIMERA_BASE) -#define STM32_HRTIM1_TIMERA_RST1R (STM32_HRTIM_TIM_RST1R_OFFSET+STM32_HRTIM1_TIMERA_BASE) -#define STM32_HRTIM1_TIMERA_SET2R (STM32_HRTIM_TIM_SET2R_OFFSET+STM32_HRTIM1_TIMERA_BASE) -#define STM32_HRTIM1_TIMERA_RST2R (STM32_HRTIM_TIM_RST2R_OFFSET+STM32_HRTIM1_TIMERA_BASE) -#define STM32_HRTIM1_TIMERA_EEFR1 (STM32_HRTIM_TIM_EEFR1_OFFSET+STM32_HRTIM1_TIMERA_BASE) -#define STM32_HRTIM1_TIMERA_EEFR2 (STM32_HRTIM_TIM_EEFR2_OFFSET+STM32_HRTIM1_TIMERA_BASE) -#define STM32_HRTIM1_TIMERA_RSTR (STM32_HRTIM_TIM_RSTR_OFFSET+STM32_HRTIM1_TIMERA_BASE) -#define STM32_HRTIM1_TIMERA_CHPR (STM32_HRTIM_TIM_CHPR_OFFSET+STM32_HRTIM1_TIMERA_BASE) -#define STM32_HRTIM1_TIMERA_CPT1CR (STM32_HRTIM_TIM_CPT1CR_OFFSET+STM32_HRTIM1_TIMERA_BASE) -#define STM32_HRTIM1_TIMERA_CPT2CR (STM32_HRTIM_TIM_CPT2CR_OFFSET+STM32_HRTIM1_TIMERA_BASE) -#define STM32_HRTIM1_TIMERA_OUTR (STM32_HRTIM_TIM_OUTR_OFFSET+STM32_HRTIM1_TIMERA_BASE) -#define STM32_HRTIM1_TIMERA_FLTR (STM32_HRTIM_TIM_FLTR_OFFSET+STM32_HRTIM1_TIMERA_BASE) - -/* HRTIM1 Timer B */ - -/* HRTIM1 Timer C */ - -/* HRTIM1 Timer D */ - -/* HRTIM1 Timer E */ - -/* HRTIM1 Common Registers */ - -#define STM32_HRTIM_CMN_CR1 (STM32_HRTIM_CMN_CR1_OFFSET+STM32_HRTIM1_CMN_BASE) -#define STM32_HRTIM_CMN_CR2 (STM32_HRTIM_CMN_CR2_OFFSET+STM32_HRTIM1_CMN_BASE) -#define STM32_HRTIM_CMN_ISR (STM32_HRTIM_CMN_ISR_OFFSET+STM32_HRTIM1_CMN_BASE) -#define STM32_HRTIM_CMN_ICR (STM32_HRTIM_CMN_ICR_OFFSET+STM32_HRTIM1_CMN_BASE) -#define STM32_HRTIM_CMN_IER (STM32_HRTIM_CMN_IER_OFFSET+STM32_HRTIM1_CMN_BASE) -#define STM32_HRTIM_CMN_OENR (STM32_HRTIM_CMN_OENR_OFFSET+STM32_HRTIM1_CMN_BASE) -#define STM32_HRTIM_CMN_DISR (STM32_HRTIM_CMN_DISR_OFFSET+STM32_HRTIM1_CMN_BASE) -#define STM32_HRTIM_CMN_ODSR (STM32_HRTIM_CMN_ODSR_OFFSET+STM32_HRTIM1_CMN_BASE) -#define STM32_HRTIM_CMN_BMCR (STM32_HRTIM_CMN_BMCR_OFFSET+STM32_HRTIM1_CMN_BASE) -#define STM32_HRTIM_CMN_BMTGR (STM32_HRTIM_CMN_BMTGR_OFFSET+STM32_HRTIM1_CMN_BASE) -#define STM32_HRTIM_CMN_BMCMPR (STM32_HRTIM_CMN_MBCMPR_OFFSET+STM32_HRTIM1_CMN_BASE) -#define STM32_HRTIM_CMN_BMPER (STM32_HRTIM_CMN_BMPER_OFFSET+STM32_HRTIM1_CMN_BASE) -#define STM32_HRTIM_CMN_EECR1 (STM32_HRTIM_CMN_EECR1_OFFSET+STM32_HRTIM1_CMN_BASE) -#define STM32_HRTIM_CMN_EECR2 (STM32_HRTIM_CMN_EECR2_OFFSET+STM32_HRTIM1_CMN_BASE) -#define STM32_HRTIM_CMN_EECR3 (STM32_HRTIM_CMN_EECR3_OFFSET+STM32_HRTIM1_CMN_BASE) -#define STM32_HRTIM_CMN_ADC1R (STM32_HRTIM_CMN_ADC1R_OFFSET+STM32_HRTIM1_CMN_BASE) -#define STM32_HRTIM_CMN_ADC2R (STM32_HRTIM_CMN_ADC2R_OFFSET+STM32_HRTIM1_CMN_BASE) -#define STM32_HRTIM_CMN_ADC3R (STM32_HRTIM_CMN_ADC3R_OFFSET+STM32_HRTIM1_CMN_BASE) -#define STM32_HRTIM_CMN_ADC4R (STM32_HRTIM_CMN_ADC4R_OFFSET+STM32_HRTIM1_CMN_BASE) -#define STM32_HRTIM_CMN_DLLCR (STM32_HRTIM_CMN_DLLCR_OFFSET+STM32_HRTIM1_CMN_BASE) -#define STM32_HRTIM_CMN_FLTINR1 (STM32_HRTIM_CMN_FTLINR1_OFFSET+STM32_HRTIM1_CMN_BASE) -#define STM32_HRTIM_CMN_FLTINR2 (STM32_HRTIM_CMN_FLTINR2_OFFSET+STM32_HRTIM1_CMN_BASE) -#define STM32_HRTIM_CMN_BDMUPDR (STM32_HRTIM_CMN_BDMUPDR_OFFSET+STM32_HRTIM1_CMN_BASE) -#define STM32_HRTIM_CMN_BDTAUPR (STM32_HRTIM_CMN_BDTAUPR_OFFSET+STM32_HRTIM1_CMN_BASE) -#define STM32_HRTIM_CMN_BDTBUPR (STM32_HRTIM_CMN_BDTBUR_OFFSET+STM32_HRTIM1_CMN_BASE) -#define STM32_HRTIM_CMN_BDTCUPR (STM32_HRTIM_CMN_BDTCUPR_OFFSET+STM32_HRTIM1_CMN_BASE) -#define STM32_HRTIM_CMN_BDTDUPR (STM32_HRTIM_CMN_BDTDUPR_OFFSET+STM32_HRTIM1_CMN_BASE) -#define STM32_HRTIM_CMN_BDTEUPR (STM32_HRTIM_CMN_BDTEUPR_OFFSET+STM32_HRTIM1_CMN_BASE) -#define STM32_HRTIM_CMN_BDMADR (STM32_HRTIM_CMN_BDMADR_OFFSET+STM32_HRTIM1_CMN_BASE) - /* Register Bitfield Definitions ****************************************************/ /* Control Register Bits Common to Master Timer and Timer A-E */ diff --git a/arch/arm/src/stm32/stm32_hrtim.c b/arch/arm/src/stm32/stm32_hrtim.c index 81692322bfb..109cf19da36 100644 --- a/arch/arm/src/stm32/stm32_hrtim.c +++ b/arch/arm/src/stm32/stm32_hrtim.c @@ -89,6 +89,25 @@ # define HRTIM_MASTER_PRESCALER HRTIM_PRESCALER_2 #endif +#ifndef HRTIM_MASTER_MODE +# define HRTIM_MASTER_MODE 0 +#endif +#ifndef HRTIM_TIMA_MODE +# define HRTIM_TIMA_MODE 0 +#endif +#ifndef HRTIM_TIMB_MODE +# define HRTIM_TIMB_MODE 0 +#endif +#ifndef HRTIM_TIMC_MODE +# define HRTIM_TIMC_MODE 0 +#endif +#ifndef HRTIM_TIMD_MODE +# define HRTIM_TIMD_MODE 0 +#endif +#ifndef HRTIM_TIME_MODE +# define HRTIM_TIME_MODE 0 +#endif + #ifndef HRTIM_TIMA_UPDATE # define HRTIM_TIMA_UPDATE 0 #endif @@ -148,61 +167,6 @@ # endif #endif -#if defined(CONFIG_STM32_HRTIM_TIMA) || defined(CONFIG_STM32_HRTIM_TIMB) || \ - defined(CONFIG_STM32_HRTIM_TIMC) || defined(CONFIG_STM32_HRTIM_TIMD) || \ - defined(CONFIG_STM32_HRTIM_TIME) -# define HRTIM_HAVE_SLAVE 1 -#endif - -#if defined(CONFIG_STM32_HRTIM_TIMA_PWM) || defined(CONFIG_STM32_HRTIM_TIMB_PWM) || \ - defined(CONFIG_STM32_HRTIM_TIMC_PWM) || defined(CONFIG_STM32_HRTIM_TIMD_PWM) || \ - defined(CONFIG_STM32_HRTIM_TIME_PWM) -# define HRTIM_HAVE_PWM 1 -#endif - -#if defined(CONFIG_STM32_HRTIM_TIMA_CAP) || defined(CONFIG_STM32_HRTIM_TIMB_CAP) || \ - defined(CONFIG_STM32_HRTIM_TIMC_CAP) || defined(CONFIG_STM32_HRTIM_TIMD_CAP) || \ - defined(CONFIG_STM32_HRTIM_TIME_CAP) -# define HRTIM_HAVE_CAPTURE 1 -#endif - -#if defined(CONFIG_STM32_HRTIM_TIMA_DT) || defined(CONFIG_STM32_HRTIM_TIMB_DT) || \ - defined(CONFIG_STM32_HRTIM_TIMC_DT) || defined(CONFIG_STM32_HRTIM_TIMD_DT) || \ - defined(CONFIG_STM32_HRTIM_TIME_DT) -# define HRTIM_HAVE_DEADTIME 1 -#endif - -#if defined(CONFIG_STM32_HRTIM_TIMA_CHOP) || defined(CONFIG_STM32_HRTIM_TIMB_CHOP) || \ - defined(CONFIG_STM32_HRTIM_TIMC_CHOP) || defined(CONFIG_STM32_HRTIM_TIMD_CHOP) || \ - defined(CONFIG_STM32_HRTIM_TIME_CHOP) -# define HRTIM_HAVE_CHOPPER 1 -#endif - -#if defined(CONFIG_STM32_HRTIM_SCOUT) || defined(CONFIG_STM32_HRTIM_SCIN) -# define HRTIM_HAVE_SYNC 1 -#endif - -#if defined(CONFIG_STM32_HRTIM_FAULT1) || defined(CONFIG_STM32_HRTIM_FAULT2) || \ - defined(CONFIG_STM32_HRTIM_FAULT3) || defined(CONFIG_STM32_HRTIM_FAULT4) || \ - defined(CONFIG_STM32_HRTIM_FAULT5) -# define HRTIM_HAVE_FAULTS 1 -#endif - -#if defined(CONFIG_STM32_HRTIM_EEV1) || defined(CONFIG_STM32_HRTIM_EEV2) || \ - defined(CONFIG_STM32_HRTIM_EEV3) || defined(CONFIG_STM32_HRTIM_EEV4) || \ - defined(CONFIG_STM32_HRTIM_EEV5) || defined(CONFIG_STM32_HRTIM_EEV6) || \ - defined(CONFIG_STM32_HRTIM_EEV7) || defined(CONFIG_STM32_HRTIM_EEV8) || \ - defined(CONFIG_STM32_HRTIM_EEV9) || defined(CONFIG_STM32_HRTIM_EEV10) -# define HRTIM_HAVE_EEV 1 -#endif - -#if defined(CONFIG_STM32_HRTIM_MASTER_IRQ) || defined(CONFIG_STM32_HRTIM_TIMA_IRQ) || \ - defined(CONFIG_STM32_HRTIM_TIMB_IRQ) || defined(CONFIG_STM32_HRTIM_TIMC_IRQ) || \ - defined(CONFIG_STM32_HRTIM_TIMD_IRQ) || defined(CONFIG_STM32_HRTIM_TIME_IRQ) || \ - defined(CONFIG_STM32_HRTIM_CMN_IRQ) -# defined HRTIM_HAVE_INTERRUPTS -#endif - /**************************************************************************** * Private Types ****************************************************************************/ @@ -273,8 +237,11 @@ struct stm32_hrtim_timcmn_s uint32_t pclk; /* The frequency of the peripheral clock * that drives the timer module. */ + uint8_t mode; /* Timer mode */ + uint8_t dac:2; /* DAC triggering */ + uint8_t reserved:6; #ifdef HRTIM_HAVE_INTERRUPTS - uint16_t irq; /* interrupts configuration */ + uint16_t irq; /* interrupts configuration */ #endif #ifdef CONFIG_STM32_HRTIM_DMA uint32_t dmaburst; @@ -305,6 +272,9 @@ struct stm32_hrtim_slave_priv_s * First five bits are fault sources, * last bit is lock configuration. */ +#ifdef HRTIM_HAVE_AUTO_DELAYED + uint8_t auto_delayed; /* Auto-delayed mode configuration */ +#endif #endif uint16_t update; /* Update configuration */ uint32_t reset; /* Timer reset events */ @@ -402,6 +372,24 @@ struct stm32_hrtim_eev_s }; #endif +/* Structure describes HRTIM ADC triggering configuration */ + +struct stm32_hrtim_adc_s +{ +#ifdef CONFIG_STM32_HRTIM_ADC_TRG1 + uint32_t trg1; +#endif +#ifdef CONFIG_STM32_HRTIM_ADC_TRG2 + uint32_t trg2; +#endif +#ifdef CONFIG_STM32_HRTIM_ADC_TRG3 + uint32_t trg3; +#endif +#ifdef CONFIG_STM32_HRTIM_ADC_TRG4 + uint32_t trg4; +#endif +}; + /* This structure describes the configuration of HRTIM device */ struct stm32_hrtim_s @@ -424,10 +412,13 @@ struct stm32_hrtim_s struct stm32_hrtim_tim_s *time; /* HRTIM Timer E */ #endif #ifdef HRTIM_HAVE_FAULTS - struct stm32_hrtim_faults_s *flt; + struct stm32_hrtim_faults_s *flt; /* Faults configuration */ #endif #ifdef HRTIM_HAVE_EEV - struct stm32_hrtim_eev_s *eev; + struct stm32_hrtim_eev_s *eev; /* External Events configuration */ +#endif +#ifdef HRTIM_HAVE_ADC + struct stm32_hrtim_adc_s *adc; /* ADC triggering configuration */ #endif #ifdef CONFIG_STM32_HRTIM_CMN_IRQ uint32_t irq; /* Common interrupts configuration */ @@ -450,8 +441,8 @@ static int stm32_hrtim_ioctl(FAR struct file *filep, int cmd, unsigned long arg) static void stm32_modifyreg32(unsigned int addr, uint32_t clrbits, uint32_t setbits); #endif -static uint32_t hrtim_getreg(FAR struct stm32_hrtim_s *priv, int offset); -static void hrtim_putreg(FAR struct stm32_hrtim_s *priv, int offset, +static uint32_t hrtim_cmn_getreg(FAR struct stm32_hrtim_s *priv, int offset); +static void hrtim_cmn_putreg(FAR struct stm32_hrtim_s *priv, int offset, uint32_t value); static void hrtim_modifyreg(FAR struct stm32_hrtim_s *priv, int offset, uint32_t clrbits, uint32_t setbits); @@ -477,7 +468,6 @@ static int hrtim_tim_clocks_config(FAR struct stm32_hrtim_s *priv); #if defined(HRTIM_HAVE_CAPTURE) || defined(HRTIM_HAVE_PWM) || defined(HRTIM_HAVE_SYNC) static int hrtim_gpios_config(FAR struct stm32_hrtim_s *priv); #endif -static void hrtim_preload_config(FAR struct stm32_hrtim_s *priv); #if defined(HRTIM_HAVE_CAPTURE) static int hrtim_inputs_config(FAR struct stm32_hrtim_s *priv); #endif @@ -486,33 +476,45 @@ static int hrtim_synch_config(FAR struct stm32_hrtim_s *priv); #endif #if defined(HRTIM_HAVE_PWM) static int hrtim_outputs_config(FAR struct stm32_hrtim_s *priv); -static int hrtim_outputs_enable(FAR struct stm32_hrtim_s *priv, uint16_t outputs, +static int hrtim_outputs_enable(FAR struct hrtim_dev_s *dev, uint16_t outputs, bool state); #endif #ifdef HRTIM_HAVE_ADC static int hrtim_adc_config(FAR struct stm32_hrtim_s *priv); #endif +#ifdef HRTIM_HAVE_DAC +static int hrtim_dac_config(FAR struct stm32_hrtim_s *priv); +#endif #ifdef HRTIM_HAVE_FAULTS static int hrtim_faults_config(FAR struct stm32_hrtim_s *priv); static int hrtim_flt_cfg(FAR struct stm32_hrtim_s *priv, uint8_t index); -static int hrtim_tim_flts_cfg(FAR struct stm32_hrtim_s *priv, uint8_t timer); +static int hrtim_tim_faults_cfg(FAR struct stm32_hrtim_s *priv, uint8_t timer); #endif #ifdef HRTIM_HAVE_EEV static int hrtim_events_config(FAR struct stm32_hrtim_s *priv); static int hrtim_eev_cfg(FAR struct stm32_hrtim_s *priv, uint8_t index); - #endif #ifdef HRTIM_HAVE_INTERRUPTS static int hrtim_irq_config(FAR struct stm32_hrtim_s *priv); +void hrtim_irq_ack(FAR struct hrtim_dev_s *dev, uint8_t timer, int source); #endif -static int hrtim_cmp_update(FAR struct stm32_hrtim_s *priv, uint8_t timer, +static int hrtim_cmp_update(FAR struct hrtim_dev_s *dev, uint8_t timer, uint8_t index, uint16_t cmp); -static int hrtim_per_update(FAR struct stm32_hrtim_s *priv, uint8_t timer, +static int hrtim_per_update(FAR struct hrtim_dev_s *dev, uint8_t timer, uint16_t per); -static uint16_t hrtim_per_get(FAR struct stm32_hrtim_s *priv, uint8_t timer); -static uint16_t hrtim_cmp_get(FAR struct stm32_hrtim_s *priv, uint8_t timer, +static uint16_t hrtim_per_get(FAR struct hrtim_dev_s *dev, uint8_t timer); +static uint16_t hrtim_cmp_get(FAR struct hrtim_dev_s *dev, uint8_t timer, uint8_t index); -static int hrtim_reset_set(FAR struct stm32_hrtim_s *priv, uint8_t timer, uint32_t reset); +static int hrtim_tim_reset_set(FAR struct stm32_hrtim_s *priv, uint8_t timer, + uint32_t reset); +static int hrtim_reset_config(FAR struct stm32_hrtim_s *priv); +static int hrtim_tim_update_set(FAR struct stm32_hrtim_s *priv, uint8_t timer, + uint32_t update); +static int hrtim_update_config(FAR struct stm32_hrtim_s *priv); + +static void hrtim_tim_mode_set(FAR struct stm32_hrtim_s *priv, uint8_t timer, + uint8_t mode); +static void hrtim_mode_config(FAR struct stm32_hrtim_s *priv); /* Initialization */ @@ -546,6 +548,10 @@ static struct stm32_hrtim_tim_s g_master = { .base = STM32_HRTIM1_MASTER_BASE, .pclk = HRTIM_CLOCK/HRTIM_MASTER_PRESCALER, + .mode = HRTIM_MASTER_MODE, +#ifdef CONFIG_STM32_HRTIM_MASTER_DAC + .dac = HRTIM_MASTER_DAC, +#endif #ifdef CONFIG_STM32_HRTIM_MASTER_IRQ .irq = HRTIM_IRQ_MASTER #endif @@ -609,7 +615,11 @@ static struct stm32_hrtim_tim_s g_tima = .tim = { .base = STM32_HRTIM1_TIMERA_BASE, - .pclk = HRTIM_CLOCK/HRTIM_TIMA_PRESCALER + .pclk = HRTIM_CLOCK/HRTIM_TIMA_PRESCALER, + .mode = HRTIM_TIMA_MODE, +#ifdef CONFIG_STM32_HRTIM_TIMA_DAC + .dac = HRTIM_TIMA_DAC, +#endif #ifdef CONFIG_STM32_HRTIM_MASTER_IRQ .irq = HRTIM_IRQ_TIMA, #endif @@ -780,6 +790,24 @@ struct stm32_hrtim_eev_s g_eev = }; #endif +/* ADC triggering data */ + +struct stm32_hrtim_adc_s g_adc = +{ +#ifdef CONFIG_STM32_HRTIM_ADC_TRG1 + .trg1 = HRTIM_ADC_TRG1, +#endif +#ifdef CONFIG_STM32_HRTIM_ADC_TRG2 + .trg2 = HRTIM_ADC_TRG2, +#endif +#ifdef CONFIG_STM32_HRTIM_ADC_TRG3 + .trg3 = HRTIM_ADC_TRG3, +#endif +#ifdef CONFIG_STM32_HRTIM_ADC_TRG4 + .trg4 = HRTIM_ADC_TRG4 +#endif +}; + /* HRTIM1 private data */ static struct stm32_hrtim_s g_hrtim1priv = @@ -802,18 +830,40 @@ static struct stm32_hrtim_s g_hrtim1priv = .time = &g_time, #endif #ifdef HRTIM_HAVE_FAULTS - .flt = &g_flt, + .flt = &g_flt, #endif #ifdef HRTIM_HAVE_EEV - .eev = &g_eev, + .eev = &g_eev, +#endif +#ifdef HRTIM_HAVE_ADC + .adc = &g_adc, #endif #ifdef CONFIG_STM32_HRTIM_CMN_IRQ - .irq = HRTIM_IRQ_COMMON, + .irq = HRTIM_IRQ_COMMON, #endif }; +/* HRTIM interface */ + +static const struct stm32_hrtim_ops_s g_hrtim1ops = +{ + .cmp_update = hrtim_cmp_update, + .per_update = hrtim_per_update, + .per_get = hrtim_per_get, + .cmp_get = hrtim_cmp_get, +#ifdef HRTIM_HAVE_INTERRUPTS + .irq_ack = hrtim_irq_ack, +#endif +#ifdef HRTIM_HAVE_PWM + .outputs_enable = hrtim_outputs_enable, +#endif +}; + +/* HRTIM device structure */ + struct hrtim_dev_s g_hrtim1dev = { + .hd_ops = &g_hrtim1ops, .hd_priv = &g_hrtim1priv, .initialized = false, }; @@ -913,7 +963,7 @@ static void stm32_modifyreg32(unsigned int addr, uint32_t clrbits, #endif /**************************************************************************** - * Name: hrtim_getreg + * Name: hrtim_cmn_getreg * * Description: * Read the value of an HRTIM register. @@ -927,13 +977,13 @@ static void stm32_modifyreg32(unsigned int addr, uint32_t clrbits, * ****************************************************************************/ -static uint32_t hrtim_getreg(FAR struct stm32_hrtim_s *priv, int offset) +static uint32_t hrtim_cmn_getreg(FAR struct stm32_hrtim_s *priv, int offset) { - return getreg32(priv->base + offset); + return getreg32(priv->base + STM32_HRTIM_CMN_OFFSET + offset); } /**************************************************************************** - * Name: hrtim_putreg + * Name: hrtim_cmn_putreg * * Description: * Write a value to an HRTIM register. @@ -948,10 +998,10 @@ static uint32_t hrtim_getreg(FAR struct stm32_hrtim_s *priv, int offset) * ****************************************************************************/ -static void hrtim_putreg(FAR struct stm32_hrtim_s *priv, int offset, +static void hrtim_cmn_putreg(FAR struct stm32_hrtim_s *priv, int offset, uint32_t value) { - putreg32(value, priv->base + offset); + putreg32(value, priv->base + STM32_HRTIM_CMN_OFFSET + offset); } /**************************************************************************** @@ -974,10 +1024,9 @@ static void hrtim_putreg(FAR struct stm32_hrtim_s *priv, int offset, static void hrtim_modifyreg(FAR struct stm32_hrtim_s *priv, int offset, uint32_t clrbits, uint32_t setbits) { - hrtim_putreg(priv, offset, (hrtim_getreg(priv, offset) & ~clrbits) | setbits); + hrtim_cmn_putreg(priv, offset, (hrtim_cmn_getreg(priv, offset) & ~clrbits) | setbits); } - /**************************************************************************** * Name: hrtim_tim_get * @@ -1076,7 +1125,7 @@ static uint32_t hrtim_base_get(FAR struct stm32_hrtim_s* priv, uint8_t timer) FAR struct stm32_hrtim_tim_s* tim; uint32_t base; - tim = hrtim_tim_get(priv, imer); + tim = hrtim_tim_get(priv, timer); if (tim == NULL) { base = 0; @@ -1201,17 +1250,19 @@ static int hrtim_dll_cal(FAR struct stm32_hrtim_s *priv) regval |= HRTIM_DLLCR_CALEN; + /* CALEN must not be set simultaneously with CAL bit */ + + hrtim_cmn_putreg(priv, STM32_HRTIM_CMN_DLLCR_OFFSET, regval); + #endif /* DLL Calibration Start */ regval |= HRTIM_DLLCR_CAL; - hrtim_putreg(priv, STM32_HRTIM_CMN_DLLCR, regval); + hrtim_cmn_putreg(priv, STM32_HRTIM_CMN_DLLCR_OFFSET, regval); - /* Wait for HRTIM ready flag */ - - while(!(hrtim_getreg(priv, STM32_HRTIM_CMN_ISR) & HRTIM_ISR_DLLRDY)); + while(!(hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_ISR_OFFSET) & HRTIM_ISR_DLLRDY)); return OK; } @@ -1600,7 +1651,6 @@ static int hrtim_inputs_config(FAR struct stm32_hrtim_s *priv) } #endif - /**************************************************************************** * Name: hrtim_synch_config * @@ -1770,7 +1820,7 @@ errout: * Enable/disable HRTIM outputs (bulk operation) * * Input Parameters: - * priv - A reference to the HRTIM structure + * dev - HRTIM device structure * outputs - outputs to set * state - Enable/disable operation * @@ -1779,9 +1829,10 @@ errout: * ****************************************************************************/ -static int hrtim_outputs_enable(FAR struct stm32_hrtim_s *priv, uint16_t outputs, +static int hrtim_outputs_enable(FAR struct hrtim_dev_s *dev, uint16_t outputs, bool state) { + FAR struct stm32_hrtim_s *priv = (FAR struct stm32_hrtim_s *)dev->hd_priv; uint32_t reg = 0; /* Get register offset */ @@ -1797,7 +1848,7 @@ static int hrtim_outputs_enable(FAR struct stm32_hrtim_s *priv, uint16_t outputs /* Write register */ - hrtim_putreg(priv, reg, outputs); + hrtim_cmn_putreg(priv, reg, outputs); return OK; } @@ -1820,7 +1871,107 @@ static int hrtim_outputs_enable(FAR struct stm32_hrtim_s *priv, uint16_t outputs #ifdef HRTIM_HAVE_ADC static int hrtim_adc_config(FAR struct stm32_hrtim_s *priv) { -#warning "hrtim_adc_config: missing logic" + +#ifdef CONFIG_STM32_HRTIM_ADC_TRG1 + hrtim_cmn_putreg(priv, STM32_HRTIM_CMN_ADC1R_OFFSET, priv->adc->trg1); +#endif +#ifdef CONFIG_STM32_HRTIM_ADC_TRG2 + hrtim_cmn_putreg(priv, STM32_HRTIM_CMN_ADC2R_OFFSET, priv->adc->trg2); +#endif +#ifdef CONFIG_STM32_HRTIM_ADC_TRG3 + hrtim_cmn_putreg(priv, STM32_HRTIM_CMN_ADC3R_OFFSET, priv->adc->trg3); +#endif +#ifdef CONFIG_STM32_HRTIM_ADC_TRG4 + hrtim_cmn_putreg(priv, STM32_HRTIM_CMN_ADC4R_OFFSET, priv->adc->trg4); +#endif + + return OK; +} +#endif + +#ifdef HRTIM_HAVE_DAC + +/**************************************************************************** + * Name: hrtim_tim_dac_cfg + * + * Description: + * Configure single HRTIM Timer DAC synchronization event + * + * Input Parameters: + * priv - A reference to the HRTIM structure + * timer - Timer index + * dac - DAC synchronisation event configuration + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +static int hrtim_tim_dac_cfg(FAS struct stm32_hrtim_s *priv, uint8_t timer, + uint8_t dac) +{ + FAR struct stm32_hrtim_tim_s *tim; + uint32_t regval = 0; + + tim = hrtim_tim_get(priv, timer); + + regval = hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_CR_OFFSET); + + regval |= (dac << HRTIM_CMNCR_DACSYNC_SHIFT); + + hrtim_tim_putreg(priv, timer, STM32_HRTIM_TIM_CR_OFFSET, regval); + + return OK; +} + +/**************************************************************************** + * Name: hrtim_dac_config + * + * Description: + * Configure HRTIM DAC triggers + * + * Input Parameters: + * priv - A reference to the HRTIM structure + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +static int hrtim_dac_config(FAR struct stm32_hrtim_s *priv) +{ + FAR struct stm32_hrtim_slave_priv_s *slave_priv; + +#ifdef CONFIG_STM32_HRTIM_MASTER_DAC + slave_priv = (struct stm32_hrtim_slave_priv_s*)priv->master->priv; + hrtim_tim_dac_cfg(priv, HRTIM_TIMER_MASTER, dac); +#endif + +#ifdef CONFIG_STM32_HRTIM_TIMA_DAC + slave_priv = (struct stm32_hrtim_slave_priv_s*)priv->tima->priv; + hrtim_tim_dac_cfg(priv, HRTIM_TIMER_TIMA, dac); +#endif + +#ifdef CONFIG_STM32_HRTIM_TIMB_DAC + slave_priv = (struct stm32_hrtim_slave_priv_s*)priv->timb->priv; + hrtim_tim_dac_cfg(priv, HRTIM_TIMER_TIMB, dac); +#endif + +#ifdef CONFIG_STM32_HRTIM_TIMC_DAC + slave_priv = (struct stm32_hrtim_slave_priv_s*)priv->timc->priv; + hrtim_tim_dac_cfg(priv, HRTIM_TIMER_TIMC, dac); +#endif + +#ifdef CONFIG_STM32_HRTIM_TIMD_DAC + slave_priv = (struct stm32_hrtim_slave_priv_s*)priv->timd->priv; + hrtim_tim_dac_cfg(priv, HRTIM_TIMER_TIMD, dac); +#endif + +#ifdef CONFIG_STM32_HRTIM_TIME_DAC + slave_priv = (struct stm32_hrtim_slave_priv_s*)priv->time->priv; + hrtim_tim_dac_cfg(priv, HRTIM_TIMER_TIME, dac); +#endif + return OK; } #endif @@ -1828,7 +1979,7 @@ static int hrtim_adc_config(FAR struct stm32_hrtim_s *priv) #ifdef HRTIM_HAVE_FAULTS /**************************************************************************** - * Name: hrtim_tim_flts_cfg + * Name: hrtim_tim_faults_cfg * * Description: * Configure HRTIM Slave Timer faults sources. @@ -1842,7 +1993,7 @@ static int hrtim_adc_config(FAR struct stm32_hrtim_s *priv) * ****************************************************************************/ -static int hrtim_tim_flts_cfg(FAR struct stm32_hrtim_s *priv, uint8_t timer) +static int hrtim_tim_faults_cfg(FAR struct stm32_hrtim_s *priv, uint8_t timer) { FAR struct stm32_hrtim_tim_s *tim; FAR struct stm32_hrtim_slave_priv_s *slave_priv; @@ -1945,7 +2096,7 @@ static int hrtim_flt_cfg(FAR struct stm32_hrtim_s *priv, uint8_t index) case 3: case 4: { - regval = hrtim_getreg(priv, STM32_HRTIM_CMN_FLTINR1_OFFSET); + regval = hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_FLTINR1_OFFSET); /* Configure polarity */ @@ -1965,7 +2116,7 @@ static int hrtim_flt_cfg(FAR struct stm32_hrtim_s *priv, uint8_t index) /* Write register */ - hrtim_putreg(priv, STM32_HRTIM_CMN_FLTINR1_OFFSET, regval); + hrtim_cmn_putreg(priv, STM32_HRTIM_CMN_FLTINR1_OFFSET, regval); break; } @@ -1974,7 +2125,7 @@ static int hrtim_flt_cfg(FAR struct stm32_hrtim_s *priv, uint8_t index) case 5: { - regval = hrtim_getreg(priv, STM32_HRTIM_CMN_FLTINR2_OFFSET); + regval = hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_FLTINR2_OFFSET); /* Configure polarity */ @@ -1994,7 +2145,7 @@ static int hrtim_flt_cfg(FAR struct stm32_hrtim_s *priv, uint8_t index) /* Write register */ - hrtim_putreg(priv, STM32_HRTIM_CMN_FLTINR2_OFFSET, regval); + hrtim_cmn_putreg(priv, STM32_HRTIM_CMN_FLTINR2_OFFSET, regval); break; } @@ -2053,30 +2204,30 @@ static int hrtim_faults_config(FAR struct stm32_hrtim_s *priv) /* Configure fault sources in Slave Timers */ #ifdef CONFIG_STM32_HRTIM_TIMA_FLT - hrtim_tim_flts_cfg(priv, HRTIM_TIMER_TIMA); + hrtim_tim_faults_cfg(priv, HRTIM_TIMER_TIMA); #endif #ifdef CONFIG_STM32_HRTIM_TIMB_FLT - hrtim_tim_flts_cfg(priv, HRTIM_TIMER_TIMA); + hrtim_tim_faults_cfg(priv, HRTIM_TIMER_TIMA); #endif #ifdef CONFIG_STM32_HRTIM_TIMC_FLT - hrtim_tim_flts_cfg(priv, HRTIM_TIMER_TIMA); + hrtim_tim_faults_cfg(priv, HRTIM_TIMER_TIMA); #endif #ifdef CONFIG_STM32_HRTIM_TIMD_FLT - hrtim_tim_flts_cfg(priv, HRTIM_TIMER_TIMA); + hrtim_tim_faults_cfg(priv, HRTIM_TIMER_TIMA); #endif #ifdef CONFIG_STM32_HRTIM_TIME_FLT - hrtim_tim_flts_cfg(priv, HRTIM_TIMER_TIMA); + hrtim_tim_faults_cfg(priv, HRTIM_TIMER_TIMA); #endif /* Configure fault sampling clock division */ - regval = hrtim_getreg(priv, STM32_HRTIM_CMN_FLTINR2_OFFSET); + regval = hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_FLTINR2_OFFSET); regval |= HRTIM_FAULT_SAMPLING << HRTIM_FLTINR1_FLT1F_SHIFT; - hrtim_putreg(priv, STM32_HRTIM_CMN_FLTINR2_OFFSET, regval); + hrtim_cmn_putreg(priv, STM32_HRTIM_CMN_FLTINR2_OFFSET, regval); return OK; } @@ -2195,7 +2346,7 @@ static int hrtim_eev_cfg(FAR struct stm32_hrtim_s *priv, uint8_t index) case 5: case 6: { - regval = hrtim_getreg(priv, STM32_HRTIM_CMN_EECR1_OFFSET); + regval = hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_EECR1_OFFSET); /* Configure source */ @@ -2215,7 +2366,7 @@ static int hrtim_eev_cfg(FAR struct stm32_hrtim_s *priv, uint8_t index) /* Write register */ - hrtim_putreg(priv, STM32_HRTIM_CMN_EECR1_OFFSET, regval); + hrtim_cmn_putreg(priv, STM32_HRTIM_CMN_EECR1_OFFSET, regval); break; } @@ -2224,7 +2375,7 @@ static int hrtim_eev_cfg(FAR struct stm32_hrtim_s *priv, uint8_t index) case 9: case 10: { - regval = hrtim_getreg(priv, STM32_HRTIM_CMN_EECR2_OFFSET); + regval = hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_EECR2_OFFSET); /* Configure source */ @@ -2244,7 +2395,7 @@ static int hrtim_eev_cfg(FAR struct stm32_hrtim_s *priv, uint8_t index) /* Write register */ - hrtim_putreg(priv, STM32_HRTIM_CMN_EECR2_OFFSET, regval); + hrtim_cmn_putreg(priv, STM32_HRTIM_CMN_EECR2_OFFSET, regval); break; } @@ -2322,9 +2473,9 @@ static int hrtim_events_config(FAR struct stm32_hrtim_s *priv) /* External Event Sampling clock */ - regval = hrtim_getreg(priv, STM32_HRTIM_CMN_EECR3_OFFSET); + regval = hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_EECR3_OFFSET); regval |= (HRTIM_EEV_SAMPLING << HRTIM_EECR3_EEVSD_SHIFT); - hrtim_putreg(priv, STM32_HRTIM_CMN_EECR3_OFFSET, regval); + hrtim_cmn_putreg(priv, STM32_HRTIM_CMN_EECR3_OFFSET, regval); return OK; } @@ -2350,13 +2501,82 @@ static int hrtim_irq_config(FAR struct stm32_hrtim_s *priv) #warning "hrtim_irq_config: missing logic" return OK; } + +void hrtim_irq_ack(FAR struct hrtim_dev_s *dev, uint8_t timer, int source); +{ +#warning "hrtim_irq_ack: missing logic" +} #endif /**************************************************************************** - * Name: hrtim_preload_config + * Name: hrtim_tim_mode_set * * Description: - * Configure HRTIM preload registers + * Set HRTIM Timer mode + * + * Input parameters: + * priv - A reference to the HRTIM block + * timer - HRTIM Timer index + * mode - Timer mode configuration + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void hrtim_tim_mode_set(FAR struct stm32_hrtim_s *priv, uint8_t timer, + uint8_t mode) +{ + uint32_t regval = 0; + + regval = hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_CR_OFFSET); + + /* Configure preload */ + + if (mode & HRTIM_MODE_PRELOAD) + { + regval |= HRTIM_CMNCR_PREEN; + } + + /* Configure half mode */ + + if (mode & HRTIM_MODE_HALF) + { + regval |= HRTIM_CMNCR_HALF; + } + + /* Configure re-triggerable mode */ + + if (mode & HRTIM_MODE_RETRIG) + { + regval |= HRTIM_CMNCR_RETRIG; + } + + /* Configure continuous mode */ + + if (mode & HRTIM_MODE_CONT) + { + regval |= HRTIM_CMNCR_CONT; + } + + /* Configure push-pull mode. Only Slaves */ + + if (mode & HRTIM_MODE_PSHPLL && timer != HRTIM_TIMER_MASTER) + { + regval |= HRTIM_TIMCR_PSHPLL; + } + + /* Write register */ + + hrtim_tim_putreg(priv, timer, STM32_HRTIM_TIM_CR_OFFSET, regval); + +} + +/**************************************************************************** + * Name: hrtim_mode_config + * + * Description: + * Configure HRTIM Timers mode * * Input Parameters: * priv - A reference to the HRTIM structure @@ -2366,38 +2586,33 @@ static int hrtim_irq_config(FAR struct stm32_hrtim_s *priv) * ****************************************************************************/ -static void hrtim_preload_config(FAR struct stm32_hrtim_s *priv) +static void hrtim_mode_config(FAR struct stm32_hrtim_s *priv) { -#ifndef CONFIG_STM32_HRTIM_MASTER_PRELOAD_DIS - hrtim_tim_modifyreg(priv, HRTIM_TIMER_MASTER, STM32_HRTIM_TIM_CR_OFFSET, - 0, HRTIM_CMNCR_PREEN); +#ifdef CONFIG_STM32_HRTIM_MASTER + hrtim_tim_mode_set(priv, HRTIM_TIMER_MASTER, priv->master->tim.mode); #endif -#if defined(CONFIG_ST32_HRTIM_TIMA) && defined(CONFIG_STM32_HRTIM_TIMA_PRELOAD_DIS) - hrtim_tim_modifyreg(priv, HRTIM_TIMER_TIMA, STM32_HRTIM_TIM_CR_OFFSET, - 0, HRTIM_CMNCR_PREEN); +#ifdef CONFIG_STM32_HRTIM_TIMA + hrtim_tim_mode_set(priv, HRTIM_TIMER_TIMA, priv->tima->tim.mode); #endif -#if defined(CONFIG_ST32_HRTIM_TIMB) && defined(CONFIG_STM32_HRTIM_TIMB_PRELOAD_DIS) - hrtim_tim_modifyreg(priv, HRTIM_TIMER_TIMB, STM32_HRTIM_TIM_CR_OFFSET, - 0, HRTIM_CMNCR_PREEN); +#ifdef CONFIG_STM32_HRTIM_TIMB + hrtim_tim_mode_set(priv, HRTIM_TIMER_TIMB, priv->timb->tim.mode); #endif -#if defined(CONFIG_ST32_HRTIM_TIMC) && defined(CONFIG_STM32_HRTIM_TIMC_PRELOAD_DIS) - hrtim_tim_modifyreg(priv, HRTIM_TIMER_TIMC, STM32_HRTIM_TIM_CR_OFFSET, - 0, HRTIM_CMNCR_PREEN); +#ifdef CONFIG_STM32_HRTIM_TIMC + hrtim_tim_mode_set(priv, HRTIM_TIMER_TIMC, priv->timc->tim.mode); #endif -#if defined(CONFIG_ST32_HRTIM_TIMD) && defined(CONFIG_STM32_HRTIM_TIMD_PRELOAD_DIS) - hrtim_tim_modifyreg(priv, HRTIM_TIMER_TIMD, STM32_HRTIM_TIM_CR_OFFSET, - 0, HRTIM_CMNCR_PREEN); +#ifdef CONFIG_STM32_HRTIM_TIMD + hrtim_tim_mode_set(priv, HRTIM_TIMER_TIMD, priv->timd->tim.mode); #endif -#if defined(CONFIG_ST32_HRTIM_TIME) && defined(CONFIG_STM32_HRTIM_TIME_PRELOAD_DIS) - hrtim_tim_modifyreg(priv, HRTIM_TIMER_TIME, STM32_HRTIM_TIM_CR_OFFSET, - 0, HRTIM_CMNCR_PREEN); +#ifdef CONFIG_STM32_HRTIM_TIME + hrtim_tim_mode_set(priv, HRTIM_TIMER_TIME, priv->time->tim.mode); #endif + } /**************************************************************************** @@ -2407,7 +2622,7 @@ static void hrtim_preload_config(FAR struct stm32_hrtim_s *priv) * Try update HRTIM Timer compare register. * * Input parameters: - * priv - A reference to the HRTIM block + * dev - HRTIM device structure * timer - HRTIM Timer index * index - Compare register timer * cmp - New compare register value @@ -2417,9 +2632,10 @@ static void hrtim_preload_config(FAR struct stm32_hrtim_s *priv) * ****************************************************************************/ -static int hrtim_cmp_update(FAR struct stm32_hrtim_s *priv, uint8_t timer, +static int hrtim_cmp_update(FAR struct hrtim_dev_s *dev, uint8_t timer, uint8_t index, uint16_t cmp) { + FAR struct stm32_hrtim_s *priv = (FAR struct stm32_hrtim_s *)dev->hd_priv; int ret = OK; uint32_t offset = 0; @@ -2469,7 +2685,7 @@ errout: * Try update HRTIM Timer period register. * * Input parameters: - * priv - A reference to the HRTIM block + * dev - HRTIM device structure * timer - HRTIM Timer index * per - New period register value * @@ -2478,9 +2694,10 @@ errout: * ****************************************************************************/ -static int hrtim_per_update(FAR struct stm32_hrtim_s *priv, uint8_t timer, +static int hrtim_per_update(FAR struct hrtim_dev_s *dev, uint8_t timer, uint16_t per) { + FAR struct stm32_hrtim_s *priv = (FAR struct stm32_hrtim_s *)dev->hd_priv; hrtim_tim_putreg(priv, timer, STM32_HRTIM_TIM_PER_OFFSET, per); return OK; @@ -2493,7 +2710,7 @@ static int hrtim_per_update(FAR struct stm32_hrtim_s *priv, uint8_t timer, * Get HRTIM Timer period value * * Input parameters: - * priv - A reference to the HRTIM block + * dev - HRTIM device structure * timer - HRTIM Timer index * * Returned Value: @@ -2501,8 +2718,10 @@ static int hrtim_per_update(FAR struct stm32_hrtim_s *priv, uint8_t timer, * ****************************************************************************/ -static uint16_t hrtim_per_get(FAR struct stm32_hrtim_s *priv, uint8_t timer) +static uint16_t hrtim_per_get(FAR struct hrtim_dev_s *dev, uint8_t timer) { + FAR struct stm32_hrtim_s *priv = (FAR struct stm32_hrtim_s *)dev->hd_priv; + return (uint16_t)hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_PER_OFFSET); } @@ -2522,9 +2741,10 @@ static uint16_t hrtim_per_get(FAR struct stm32_hrtim_s *priv, uint8_t timer) * ****************************************************************************/ -static uint16_t hrtim_cmp_get(FAR struct stm32_hrtim_s *priv, uint8_t timer, +static uint16_t hrtim_cmp_get(FAR struct hrtim_dev_s *dev, uint8_t timer, uint8_t index) { + FAR struct stm32_hrtim_s *priv = (FAR struct stm32_hrtim_s *)dev->hd_priv; uint16_t cmpx = 0; uint32_t offset = 0; @@ -2568,7 +2788,7 @@ errout: } /**************************************************************************** - * Name: hrtim_reset_set + * Name: hrtim_tim_reset_set * * Description: * Set HRTIM Timer Reset events @@ -2583,7 +2803,8 @@ errout: * ****************************************************************************/ -static int hrtim_reset_set(FAR struct stm32_hrtim_s *priv, uint8_t timer, uint32_t reset) +static int hrtim_tim_reset_set(FAR struct stm32_hrtim_s *priv, uint8_t timer, + uint32_t reset) { int ret = OK; @@ -2601,25 +2822,81 @@ errout: static int hrtim_reset_config(FAR struct stm32_hrtim_s *priv) { + FAR struct stm32_hrtim_slave_priv_s *slave_priv; -#ifdef CONFIG_ST32_HRTIM_TIMA - hrtim_reset_set(priv, HRTIM_TIMER_TIMA, priv->tima->reset); +#ifdef CONFIG_STM32_HRTIM_TIMA + slave_priv = (struct stm32_hrtim_slave_priv_s*)priv->tima->priv; + hrtim_tim_reset_set(priv, HRTIM_TIMER_TIMA, slave_priv->reset); #endif -#ifdef CONFIG_ST32_HRTIM_TIMB - hrtim_reset_set(priv, HRTIM_TIMER_TIMB, priv->timb->reset); +#ifdef CONFIG_STM32_HRTIM_TIMB + slave_priv = (struct stm32_hrtim_slave_priv_s*)priv->timb->priv; + hrtim_tim_reset_set(priv, HRTIM_TIMER_TIMB, slave_priv->reset); #endif -#ifdef CONFIG_ST32_HRTIM_TIMC - hrtim_reset_set(priv, HRTIM_TIMER_TIMC, priv->timc->reset); +#ifdef CONFIG_STM32_HRTIM_TIMC + slave_priv = (struct stm32_hrtim_slave_priv_s*)priv->timc->priv; + hrtim_tim_reset_set(priv, HRTIM_TIMER_TIMC, slave_priv->reset); #endif -#ifdef CONFIG_ST32_HRTIM_TIMD - hrtim_reset_set(priv, HRTIM_TIMER_TIMD, priv->timd->reset); +#ifdef CONFIG_STM32_HRTIM_TIMD + slave_priv = (struct stm32_hrtim_slave_priv_s*)priv->timd->priv; + hrtim_tim_reset_set(priv, HRTIM_TIMER_TIMD, slave_priv->reset); #endif -#ifdef CONFIG_ST32_HRTIM_TIME - hrtim_reset_set(priv, HRTIM_TIMER_TIME, priv->time->reset); +#ifdef CONFIG_STM32_HRTIM_TIME + slave_priv = (struct stm32_hrtim_slave_priv_s*)priv->time->priv; + hrtim_tim_reset_set(priv, HRTIM_TIMER_TIME, slave_priv->reset); +#endif + + return OK; +} + +static int hrtim_tim_update_set(FAR struct stm32_hrtim_s *priv, uint8_t timer, + uint32_t update) +{ + uint32_t regval = 0; + + regval = hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_CR_OFFSET); + + /* TODO: Configure update events */ + + /* TODO: Configure update gating */ + + /* Write register */ + + hrtim_tim_putreg(priv, timer, STM32_HRTIM_TIM_CR_OFFSET, regval); + + return OK; +} + +static int hrtim_update_config(FAR struct stm32_hrtim_s *priv) +{ + FAR struct stm32_hrtim_slave_priv_s *slave_priv; + +#ifdef CONFIG_STM32_HRTIM_TIMA + slave_priv = (struct stm32_hrtim_slave_priv_s*)priv->tima->priv; + hrtim_tim_update_set(priv, HRTIM_TIMER_TIMA, slave_priv->update); +#endif + +#ifdef CONFIG_STM32_HRTIM_TIMB + slave_priv = (struct stm32_hrtim_slave_priv_s*)priv->timb->priv; + hrtim_tim_update_set(priv, HRTIM_TIMER_TIMB, slave_priv->update); +#endif + +#ifdef CONFIG_STM32_HRTIM_TIMC + slave_priv = (struct stm32_hrtim_slave_priv_s*)priv->timc->priv; + hrtim_tim_update_set(priv, HRTIM_TIMER_TIMC, slave_priv->update); +#endif + +#ifdef CONFIG_STM32_HRTIM_TIMD + slave_priv = (struct stm32_hrtim_slave_priv_s*)priv->timd->priv; + hrtim_tim_update_set(priv, HRTIM_TIMER_TIMD, slave_priv->update); +#endif + +#ifdef CONFIG_STM32_HRTIM_TIME + slave_priv = (struct stm32_hrtim_slave_priv_s*)priv->time->priv; + hrtim_tim_update_set(priv, HRTIM_TIMER_TIME, slave_priv->update); #endif return OK; @@ -2668,10 +2945,24 @@ static int stm32_hrtimconfig(FAR struct stm32_hrtim_s *priv) goto errout; } - /* Configure reset events */ + /* Configure Timers reset events */ hrtim_reset_config(priv); + /* Configure Timers update events */ + + hrtim_update_config(priv); + + /* Configure Timers mode */ + + hrtim_mode_config(priv); + + /* Configure auto-delayed mode */ + +#ifdef HRTIM_HAVE_AUTODELAYED + hrtim_autodelayed_config(priv); +#endif + /* Configure HRTIM GPIOs */ #if defined(HRTIM_HAVE_CAPTURE) || defined(HRTIM_HAVE_PWM) || defined(HRTIM_HAVE_SYNC) @@ -2727,6 +3018,17 @@ static int stm32_hrtimconfig(FAR struct stm32_hrtim_s *priv) } #endif + /* Configure DAC synchronization */ + +#ifdef HRTIM_HAVE_DAC + ret = hrtim_dac_config(priv); + if (ret != OK) + { + tmrerr("ERROR: HRTIM ADC configuration failed!\n"); + goto errout; + } +#endif + /* Configure Faults */ #ifdef HRTIM_HAVE_FAULTS @@ -2760,10 +3062,6 @@ static int stm32_hrtimconfig(FAR struct stm32_hrtim_s *priv) } #endif - /* Enable registers preload */ - - hrtim_preload_config(priv); - /* Enable Master Timer */ regval |= HRTIM_MCR_MCEN; @@ -2829,7 +3127,7 @@ FAR struct hrtim_dev_s* stm32_hrtiminitialize(void) /* configure HRTIM only once */ - if (dev->initialized) + if (!dev->initialized) { ret = stm32_hrtimconfig(hrtim); if (ret < 0) diff --git a/arch/arm/src/stm32/stm32_hrtim.h b/arch/arm/src/stm32/stm32_hrtim.h index 3919932d2c4..e036262dc1b 100644 --- a/arch/arm/src/stm32/stm32_hrtim.h +++ b/arch/arm/src/stm32/stm32_hrtim.h @@ -56,6 +56,66 @@ * Pre-processor definitions ************************************************************************************/ +#if defined(CONFIG_STM32_HRTIM_TIMA) || defined(CONFIG_STM32_HRTIM_TIMB) || \ + defined(CONFIG_STM32_HRTIM_TIMC) || defined(CONFIG_STM32_HRTIM_TIMD) || \ + defined(CONFIG_STM32_HRTIM_TIME) +# define HRTIM_HAVE_SLAVE 1 +#endif + +#if defined(CONFIG_STM32_HRTIM_TIMA_PWM) || defined(CONFIG_STM32_HRTIM_TIMB_PWM) || \ + defined(CONFIG_STM32_HRTIM_TIMC_PWM) || defined(CONFIG_STM32_HRTIM_TIMD_PWM) || \ + defined(CONFIG_STM32_HRTIM_TIME_PWM) +# define HRTIM_HAVE_PWM 1 +#endif + +#if defined(CONFIG_STM32_HRTIM_TIMA_CAP) || defined(CONFIG_STM32_HRTIM_TIMB_CAP) || \ + defined(CONFIG_STM32_HRTIM_TIMC_CAP) || defined(CONFIG_STM32_HRTIM_TIMD_CAP) || \ + defined(CONFIG_STM32_HRTIM_TIME_CAP) +# define HRTIM_HAVE_CAPTURE 1 +#endif + +#if defined(CONFIG_STM32_HRTIM_TIMA_DT) || defined(CONFIG_STM32_HRTIM_TIMB_DT) || \ + defined(CONFIG_STM32_HRTIM_TIMC_DT) || defined(CONFIG_STM32_HRTIM_TIMD_DT) || \ + defined(CONFIG_STM32_HRTIM_TIME_DT) +# define HRTIM_HAVE_DEADTIME 1 +#endif + +#if defined(CONFIG_STM32_HRTIM_TIMA_CHOP) || defined(CONFIG_STM32_HRTIM_TIMB_CHOP) || \ + defined(CONFIG_STM32_HRTIM_TIMC_CHOP) || defined(CONFIG_STM32_HRTIM_TIMD_CHOP) || \ + defined(CONFIG_STM32_HRTIM_TIME_CHOP) +# define HRTIM_HAVE_CHOPPER 1 +#endif + +#if defined(CONFIG_STM32_HRTIM_SCOUT) || defined(CONFIG_STM32_HRTIM_SCIN) +# define HRTIM_HAVE_SYNC 1 +#endif + +#if defined(CONFIG_STM32_HRTIM_FAULT1) || defined(CONFIG_STM32_HRTIM_FAULT2) || \ + defined(CONFIG_STM32_HRTIM_FAULT3) || defined(CONFIG_STM32_HRTIM_FAULT4) || \ + defined(CONFIG_STM32_HRTIM_FAULT5) +# define HRTIM_HAVE_FAULTS 1 +#endif + +#if defined(CONFIG_STM32_HRTIM_EEV1) || defined(CONFIG_STM32_HRTIM_EEV2) || \ + defined(CONFIG_STM32_HRTIM_EEV3) || defined(CONFIG_STM32_HRTIM_EEV4) || \ + defined(CONFIG_STM32_HRTIM_EEV5) || defined(CONFIG_STM32_HRTIM_EEV6) || \ + defined(CONFIG_STM32_HRTIM_EEV7) || defined(CONFIG_STM32_HRTIM_EEV8) || \ + defined(CONFIG_STM32_HRTIM_EEV9) || defined(CONFIG_STM32_HRTIM_EEV10) +# define HRTIM_HAVE_EEV 1 +#endif + +#if defined(CONFIG_STM32_HRTIM_MASTER_IRQ) || defined(CONFIG_STM32_HRTIM_TIMA_IRQ) || \ + defined(CONFIG_STM32_HRTIM_TIMB_IRQ) || defined(CONFIG_STM32_HRTIM_TIMC_IRQ) || \ + defined(CONFIG_STM32_HRTIM_TIMD_IRQ) || defined(CONFIG_STM32_HRTIM_TIME_IRQ) || \ + defined(CONFIG_STM32_HRTIM_CMN_IRQ) +# defined HRTIM_HAVE_INTERRUPTS +#endif + +#if defined(CONFIG_STM32_HRTIM_ADC_TRG1) || defined(CONFIG_STM32_HRTIM_ADC_TRG2) || \ + defined(CONFIG_STM32_HRTIM_ADC_TRG3) || defined(CONFIG_STM32_HRTIM_ADC_TRG4) +# define HRTIM_HAVE_ADC +#endif + /************************************************************************************ * Public Types ************************************************************************************/ @@ -223,6 +283,39 @@ enum stm32_hrtim_tim_prescaler_e HRTIM_PRESCALER_128 }; +/* HRTIM Timer Master/Slave mode */ + +enum stm32_hrtim_mode_e +{ + HRTIM_MODE_PRELOAD = (1 << 0), /* Preload enable */ + HRTIM_MODE_HALF = (1 << 1), /* Half mode */ + HRTIM_MODE_RETRIG = (1 << 2), /* Re-triggerable mode */ + HRTIM_MODE_CONT = (1 << 3), /* Continuous mode */ + + /* Only slave Timers */ + + HRTIM_MODE_PSHPLL = (1 << 7), /* Push-Pull mode */ +}; + +/* HRTIM Slave Timer auto-delayed mode + * NOTE: details in STM32F334 Manual + */ + +enum stm32_hrtim_autodelayed_e +{ + /* CMP2 auto-delayed mode */ + + HRTIM_AUTODELAYED_CMP2_MODE1 = 1, /* DELCMP2 = 01 */ + HRTIM_AUTODELAYED_CMP2_MODE2 = 2, /* DELCMP2 = 10 */ + HRTIM_AUTODELAYED_CMP2_MODE3 = 3, /* DELCMP2 = 11 */ + + /* CMP4 auto-delayed mode */ + + HRTIM_AUTODELAYED_CMP4_MODE1 = (1 << 2), /* DELCMP4 = 01 */ + HRTIM_AUTODELAYED_CMP4_MODE2 = (2 << 2), /* DELCMP4 = 10 */ + HRTIM_AUTODELAYED_CMP4_MODE3 = (3 << 2), /* DELCMP4 = 11 */ +}; + /* HRTIM Slave Timer fault sources Lock */ enum stm32_hrtim_tim_fault_lock_e @@ -371,7 +464,7 @@ enum stm32_hrtim_dacsync_e /* HRTIM Deadtime Locks */ -enum stm32_deadtime_lock_e +enum stm32_hrtim_deadtime_lock_e { HRTIM_DT_VALUE_LOCK = (1 << 0), /* Lock Deadtime value */ HRTIM_DT_SIGN_LOCK = (1 << 1) /* Lock Deadtime sign */ @@ -379,7 +472,7 @@ enum stm32_deadtime_lock_e /* HRTIM Deadtime types */ -enum stm32_deadtime_edge_e +enum stm32_hrtim_deadtime_edge_e { HRTIM_DT_RISING = 0, HRTIM_DT_FALLING = 1 @@ -387,7 +480,7 @@ enum stm32_deadtime_edge_e /* Chopper start pulsewidth */ -enum stm32_chopper_start_e +enum stm32_hrtim_chopper_start_e { HRTIM_CHP_START_16, HRTIM_CHP_START_32, @@ -408,7 +501,7 @@ enum stm32_chopper_start_e /* Chopper duty cycle */ -enum stm32_chopper_duty_e +enum stm32_hrtim_chopper_duty_e { HRTIM_CHP_DUTY_0, HRTIM_CHP_DUTY_1, @@ -422,7 +515,7 @@ enum stm32_chopper_duty_e /* Chopper carrier frequency */ -enum stm32_chopper_freq_e +enum stm32_hrtim_chopper_freq_e { HRTIM_CHP_FREQ_d16, HRTIM_CHP_FREQ_d32, @@ -442,7 +535,172 @@ enum stm32_chopper_freq_e HRTIM_CHP_FREQ_d256 }; -/* */ +/* HRTIM ADC Trigger 1/3 */ + +enum stm32_hrtim_adc_trq13_e +{ + HRTIM_ADCTRG13_MC1 = (1 << 0), + HRTIM_ADCTRG13_MC2 = (1 << 1), + HRTIM_ADCTRG13_MC3 = (1 << 2), + HRTIM_ADCTRG13_MC4 = (1 << 3), + HRTIM_ADCTRG13_MPER = (1 << 4), + + HRTIM_ADCTRG13_EEV1 = (1 << 5), + HRTIM_ADCTRG13_EEV2 = (1 << 6), + HRTIM_ADCTRG13_EEV3 = (1 << 7), + HRTIM_ADCTRG13_EEV4 = (1 << 8), + HRTIM_ADCTRG13_EEV5 = (1 << 9), + + HRTIM_ADCTRG13_AC2 = (1 << 10), + HRTIM_ADCTRG13_AC3 = (1 << 11), + HRTIM_ADCTRG13_AC4 = (1 << 12), + HRTIM_ADCTRG13_APER = (1 << 13), + HRTIM_ADCTRG13_ARST = (1 << 14), + + HRTIM_ADCTRG13_BC2 = (1 << 15), + HRTIM_ADCTRG13_BC3 = (1 << 16), + HRTIM_ADCTRG13_BC4 = (1 << 17), + HRTIM_ADCTRG13_BPER = (1 << 18), + HRTIM_ADCTRG13_BRST = (1 << 19), + + HRTIM_ADCTRG13_CC2 = (1 << 20), + HRTIM_ADCTRG13_CC3 = (1 << 21), + HRTIM_ADCTRG13_CC4 = (1 << 22), + HRTIM_ADCTRG13_CPER = (1 << 23), + + HRTIM_ADCTRG13_DC2 = (1 << 24), + HRTIM_ADCTRG13_DC3 = (1 << 25), + HRTIM_ADCTRG13_DC4 = (1 << 26), + HRTIM_ADCTRG13_DPER = (1 << 27), + + HRTIM_ADCTRG13_EC2 = (1 << 28), + HRTIM_ADCTRG13_EC3 = (1 << 29), + HRTIM_ADCTRG13_EC4 = (1 << 30), + HRTIM_ADCTRG13_ERST = (1 << 31), +}; + +/* HRTIM ADC Trigger 2/4 */ + +enum stm32_hrtim_adc_trq24_e +{ + HRTIM_ADCTRG24_MC1 = (1 << 0), + HRTIM_ADCTRG24_MC2 = (1 << 1), + HRTIM_ADCTRG24_MC3 = (1 << 2), + HRTIM_ADCTRG24_MC4 = (1 << 3), + HRTIM_ADCTRG24_MPER = (1 << 4), + + HRTIM_ADCTRG24_EEV6 = (1 << 5), + HRTIM_ADCTRG24_EEV7 = (1 << 6), + HRTIM_ADCTRG24_EEV8 = (1 << 7), + HRTIM_ADCTRG24_EEV9 = (1 << 8), + HRTIM_ADCTRG24_EEV10 = (1 << 9), + + HRTIM_ADCTRG24_AC2 = (1 << 10), + HRTIM_ADCTRG24_AC3 = (1 << 11), + HRTIM_ADCTRG24_AC4 = (1 << 12), + HRTIM_ADCTRG24_APER = (1 << 13), + + HRTIM_ADCTRG24_BC2 = (1 << 14), + HRTIM_ADCTRG24_BC3 = (1 << 15), + HRTIM_ADCTRG24_BC4 = (1 << 16), + HRTIM_ADCTRG24_BPER = (1 << 17), + + HRTIM_ADCTRG24_CC2 = (1 << 18), + HRTIM_ADCTRG24_CC3 = (1 << 19), + HRTIM_ADCTRG24_CC4 = (1 << 20), + HRTIM_ADCTRG24_CPER = (1 << 21), + HRTIM_ADCTRG24_CRST = (1 << 22), + + HRTIM_ADCTRG24_DC2 = (1 << 23), + HRTIM_ADCTRG24_DC3 = (1 << 24), + HRTIM_ADCTRG24_DC4 = (1 << 25), + HRTIM_ADCTRG24_DPER = (1 << 26), + HRTIM_ADCTRG24_DRST = (1 << 27), + + HRTIM_ADCTRG24_EC2 = (1 << 28), + HRTIM_ADCTRG24_EC3 = (1 << 29), + HRTIM_ADCTRG24_EC4 = (1 << 30), + HRTIM_ADCTRG24_ERST = (1 << 31), +}; + +/* HRTIM DAC synchronization */ + +enum stm32_hrtim_dac_e +{ + HRTIM_DAC_SYNC_DIS = 0, + HRTIM_DAC_SYNC_1 = 1, + HRTIM_DAC_SYNC_2 = 2, + HRTIM_DAC_SYNC_3 = 3 +}; + +/* HRTIM Master Timer interrupts */ + +enum stm32_irq_master_e +{ + HRTIM_IRQ_MCMP1 = (1 << 0), /* Master Compare 1 Interrupt */ + HRTIM_IRQ_MCMP2 = (1 << 1), /* Master Compare 2 Interrupt */ + HRTIM_IRQ_MCMP3 = (1 << 2), /* Master Compare 3 Interrupt */ + HRTIM_IRQ_MCMP4 = (1 << 3), /* Master Compare 4 Interrupt */ + HRTIM_IRQ_MREP = (1 << 4), /* Master Repetition Interrupt */ + HRTIM_IRQ_MSYNC = (1 << 5), /* Sync Input Interrupt */ + HRTIM_IRQ_MUPD = (1 << 6) /* Master Update Interrupt */ +}; + +/* HRTIM Slave Timer interrupts */ + +enum stm32_irq_slave_e +{ + HRTIM_IRQ_CMP1 = (1 << 0), /* Slave Compare 1 Interrupt */ + HRTIM_IRQ_CMP2 = (1 << 1), /* Slave Compare 2 Interrupt */ + HRTIM_IRQ_CMP3 = (1 << 2), /* Slave Compare 3 Interrupt */ + HRTIM_IRQ_CMP4 = (1 << 3), /* Slave Compare 4 Interrupt */ + HRTIM_IRQ_REP = (1 << 4), /* Slave Repetition Interrupt */ + HRTIM_IRQ_UPD = (1 << 6), /* Slave Update Interrupt */ + HRTIM_IRQ_CPT1 = (1 << 7), /* Slave Capture 1 Interrupt */ + HRTIM_IRQ_CPT2 = (1 << 8), /* Slave Capture 2 Interrupt */ + HRTIM_IRQ_SETX1 = (1 << 9), /* Slave Output 1 Set Interrupt */ + HRTIM_IRQ_RSTX1 = (1 << 10), /* Slave Output 1 Reset Interrupt */ + HRTIM_IRQ_SETX2 = (1 << 11), /* Slave Output 2 Set Interrupt */ + HRTIM_IRQ_RSTX2 = (1 << 12), /* Slave Output 2 Reset Interrupt */ + HRTIM_IRQ_RST = (1 << 13), /* Slave Reset/roll-over Interrupt */ + HRTIM_IRQ_DLYPRT = (1 << 14) /* Slave Delayed Protection Interrupt */ +}; + +/* HRTIM Common Interrupts */ + +enum stm32_irq_cmn_e +{ + HRTIM_IRQ_FLT1 = (1 << 0), /* Fault 1 Interrupt */ + HRTIM_IRQ_FLT2 = (1 << 1), /* Fault 2 Interrupt */ + HRTIM_IRQ_FLT3 = (1 << 2), /* Fault 3 Interrupt */ + HRTIM_IRQ_FLT4 = (1 << 3), /* Fault 4 Interrupt */ + HRTIM_IRQ_FLT5 = (1 << 4), /* Fault 5 Interrupt */ + HRTIM_IRQ_SYSFLT = (1 << 5), /* System Fault Interrupt */ + HRTIM_IRQ_DLLRDY = (1 << 16), /* DLL Ready Interrupt */ + HRTIM_IRQ_BMPER = (1 << 17) /* Burst Mode Period Interrupt */ +}; + +/* HRTIM vtable */ + +struct hrtim_dev_s; +struct stm32_hrtim_ops_s +{ + int (*cmp_update)(FAR struct hrtim_dev_s *dev, uint8_t timer, + uint8_t index, uint16_t cmp); + int (*per_update)(FAR struct hrtim_dev_s *dev, uint8_t timer, uint16_t per); + uint16_t (*per_get)(FAR struct hrtim_dev_s *dev, uint8_t timer); + uint16_t (*cmp_get)(FAR struct hrtim_dev_s *dev, uint8_t timer, + uint8_t index); +#ifdef HRTIM_HAVE_INTERRUPTS + void (*irq_ack)(FAR struct hrtim_dev_s *dev, uint8_t timer, int source); +#endif +#ifdef HRTIM_HAVE_PWM + int (*outputs_enable)(FAR struct hrtim_dev_s *dev, uint16_t outputs, + bool state); +#endif +}; + +/* HRTIM device structure */ struct hrtim_dev_s { @@ -455,8 +713,9 @@ struct hrtim_dev_s /* Fields provided by lower half HRTIM logic */ - FAR void *hd_priv; /* Used by the arch-specific logic */ - bool initialized; /* true: HRTIM driver has been initialized */ + FAR const struct stm32_hrtim_ops_s *hd_ops; /* HRTIM operations */ + FAR void *hd_priv; /* Used by the arch-specific logic */ + bool initialized; /* true: HRTIM driver has been initialized */ }; /************************************************************************************