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Update all STM32 F2 files so that they are the same as the corresponding F4 files

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4778 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
2012-05-28 18:10:41 +00:00
parent a1edf7977d
commit 602cdebea9
13 changed files with 602 additions and 265 deletions
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ChangeLog
+2
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@@ -2824,3 +2824,5 @@
messages. Added a "hack" to work around missing TxFIFO empty interrupts. The messages. Added a "hack" to work around missing TxFIFO empty interrupts. The
hack is basically to poll for space in the TxFIFO instead of of setting up hack is basically to poll for space in the TxFIFO instead of of setting up
the interrupt. the interrupt.
* arch/arm/src/stm32/stm32f2* and chip/stm32f2*: Update all STM32 F2 file so
that they are equivalent to F4 files. This is kind of a maintenance nightmare.
arch/arm/include/stm32/chip.h
+2 -2
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@@ -202,8 +202,8 @@
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */ # undef CONFIG_STM32_MEDIUMDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F101x and STM32F103x w/ 256/512 Kbytes */ # undef CONFIG_STM32_HIGHDENSITY /* STM32F101x and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # define CONFIG_STM32_STM32F20XX 1 /* STM32F205x and STM32F207x */
# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */ # undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */
# define STM32_NFSMC 1 /* FSMC */ # define STM32_NFSMC 1 /* FSMC */
# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ # define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA # define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
arch/arm/src/stm32/chip/stm32f20xxx_dma.h
+24 -3
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@@ -1,7 +1,7 @@
/************************************************************************************ /************************************************************************************
* arch/arm/src/stm32/chip/stm32f20xxx_dma.h * arch/arm/src/stm32/chip/stm32f20xxx_dma.h
* *
* Copyright (C) 2011 Gregory Nutt. All rights reserved. * Copyright (C) 2012 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org> * Author: Gregory Nutt <gnutt@nuttx.org>
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
@@ -355,6 +355,27 @@
#define DMA_SNDTR_NDT_SHIFT (0) /* Bits 15-0: Number of data to Transfer */ #define DMA_SNDTR_NDT_SHIFT (0) /* Bits 15-0: Number of data to Transfer */
#define DMA_SNDTR_NDT_MASK (0xffff << DMA_SNDTR_NDT_SHIFT) #define DMA_SNDTR_NDT_MASK (0xffff << DMA_SNDTR_NDT_SHIFT)
/* DMA stream n FIFO control register */
#define DMA_SFCR_FTH_SHIFT (0) /* Bits 0-1: FIFO threshold selection */
#define DMA_SFCR_FTH_MASK (3 << DMA_SFCR_FTH_SHIFT)
# define DMA_SFCR_FTH_QUARTER (0 << DMA_SFCR_FTH_SHIFT) /* 1/4 full FIFO */
# define DMA_SFCR_FTH_HALF (1 << DMA_SFCR_FTH_SHIFT) /* 1/2 full FIFO */
# define DMA_SFCR_FTH_3QUARTER (2 << DMA_SFCR_FTH_SHIFT) /* 3/4 full FIFO */
# define DMA_SFCR_FTH_FULL (3 << DMA_SFCR_FTH_SHIFT) /* full FIFO */
#define DMA_SFCR_DMDIS (1 << 2) /* Bit 2: Direct mode disable */
#define DMA_SFCR_FS_SHIFT (3) /* Bits 3-5: FIFO status */
#define DMA_SFCR_FS_MASK (7 << DMA_SFCR_FS_SHIFT)
# define DMA_SFCR_FS_QUARTER (0 << DMA_SFCR_FS_SHIFT) /* 0 < fifo_level < 1/4 */
# define DMA_SFCR_FS_HALF (1 << DMA_SFCR_FS_SHIFT) /* 1/4 = fifo_level < 1/2 */
# define DMA_SFCR_FS_3QUARTER (2 << DMA_SFCR_FS_SHIFT) /* 1/2 = fifo_level < 3/4 */
# define DMA_SFCR_FS_ALMOSTFULL (3 << DMA_SFCR_FS_SHIFT) /* 3/4 = fifo_level < full */
# define DMA_SFCR_FS_EMPTY (4 << DMA_SFCR_FS_SHIFT) /* FIFO is empty */
# define DMA_SFCR_FS_FULL (5 << DMA_SFCR_FS_SHIFT) /* FIFO is full */
/* Bit 6: Reserved */
#define DMA_SFCR_FEIE (1 << 7) /* Bit 7: FIFO error interrupt enable */
/* Bits 8-31: Reserved */
/* DMA Stream mapping. Each DMA stream has a mapping to several possible /* DMA Stream mapping. Each DMA stream has a mapping to several possible
* sources/sinks of data. The requests from peripherals assigned to a stream * sources/sinks of data. The requests from peripherals assigned to a stream
* are simply OR'ed together before entering the DMA block. This means that only * are simply OR'ed together before entering the DMA block. This means that only
@@ -369,10 +390,10 @@
* #define DMAMAP_SPI3_RX DMAMAP_SPI3_RX_1 * #define DMAMAP_SPI3_RX DMAMAP_SPI3_RX_1
*/ */
#define STM32_DMA_MAP(d,c,s) ((d) << 6 | (s) << 3 | (c)) #define STM32_DMA_MAP(d,s,c) ((d) << 6 | (s) << 3 | (c))
#define STM32_DMA_CONTROLLER(m) (((m) >> 6) & 1) #define STM32_DMA_CONTROLLER(m) (((m) >> 6) & 1)
#define STM32_DMA_STREAM(m) (((m) >> 3) & 7) #define STM32_DMA_STREAM(m) (((m) >> 3) & 7)
#define STM32_DMA_CHAN(c) ((c) & 7) #define STM32_DMA_CHANNEL(m) ((m) & 7)
#define DMAMAP_SPI3_RX_1 STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN0) #define DMAMAP_SPI3_RX_1 STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN0)
#define DMAMAP_SPI3_RX_2 STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN0) #define DMAMAP_SPI3_RX_2 STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN0)
arch/arm/src/stm32/chip/stm32f20xxx_gpio.h
+2 -2
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@@ -1,8 +1,8 @@
/************************************************************************************ /************************************************************************************
* arch/arm/src/stm32/chip/stm32f20xxx_gpio.h * arch/arm/src/stm32/chip/stm32f20xxx_gpio.h
* *
* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. * Copyright (C) 2012 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr> * Author: Gregory Nutt <gnutt@nuttx.org>
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions * modification, are permitted provided that the following conditions
arch/arm/src/stm32/chip/stm32f20xxx_memorymap.h
+2 -2
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@@ -1,7 +1,7 @@
/************************************************************************************ /************************************************************************************
* arch/arm/src/stm32/chip/stm32f20xxx_memorymap.h * arch/arm/src/stm32/chip/stm32f20xxx_memorymap.h
* *
* Copyright (C) 2011 Gregory Nutt. All rights reserved. * Copyright (C) 2012 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org> * Author: Gregory Nutt <gnutt@nuttx.org>
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
@@ -39,7 +39,7 @@
/************************************************************************************ /************************************************************************************
* Pre-processor Definitions * Pre-processor Definitions
************************************************************************************/ ************************************************************************************/
/* STM32F20XXX Address Blocks *******************************************************/ /* STM32F20XXX Address Blocks *******************************************************/
#define STM32_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */ #define STM32_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */
arch/arm/src/stm32/chip/stm32f20xxx_pinmap.h
+214 -147
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@@ -1,7 +1,7 @@
/************************************************************************************ /************************************************************************************
* arch/arm/src/stm32/chip/stm32f20xxx_pinmap.h * arch/arm/src/stm32/chip/stm32f20xxx_pinmap.h
* *
* Copyright (C) 2011 Gregory Nutt. All rights reserved. * Copyright (C) 2012 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr> * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
@@ -62,7 +62,7 @@
* The driver will then automatically configre PA11 as the CAN1 RX pin. * The driver will then automatically configre PA11 as the CAN1 RX pin.
*/ */
/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! /* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
* Additional effort is required to select specific GPIO options such as frequency, * Additional effort is required to select specific GPIO options such as frequency,
* open-drain/push-pull, and pull-up/down! Just the basics are defined for most * open-drain/push-pull, and pull-up/down! Just the basics are defined for most
* pins in this file. * pins in this file.
@@ -236,70 +236,70 @@
/* Flexible Static Memory Controller (FSMC) */ /* Flexible Static Memory Controller (FSMC) */
#define GPIO_FSMC_A0 (GPIO_ALT|GPIO_AF12|GPIO_PORTF|GPIO_PIN0) #define GPIO_FSMC_A0 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN0)
#define GPIO_FSMC_A1 (GPIO_ALT|GPIO_AF12|GPIO_PORTF|GPIO_PIN1) #define GPIO_FSMC_A1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN1)
#define GPIO_FSMC_A2 (GPIO_ALT|GPIO_AF12|GPIO_PORTF|GPIO_PIN2) #define GPIO_FSMC_A2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN2)
#define GPIO_FSMC_A3 (GPIO_ALT|GPIO_AF12|GPIO_PORTF|GPIO_PIN3) #define GPIO_FSMC_A3 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN3)
#define GPIO_FSMC_A4 (GPIO_ALT|GPIO_AF12|GPIO_PORTF|GPIO_PIN4) #define GPIO_FSMC_A4 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN4)
#define GPIO_FSMC_A5 (GPIO_ALT|GPIO_AF12|GPIO_PORTF|GPIO_PIN5) #define GPIO_FSMC_A5 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN5)
#define GPIO_FSMC_A6 (GPIO_ALT|GPIO_AF12|GPIO_PORTF|GPIO_PIN12) #define GPIO_FSMC_A6 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN12)
#define GPIO_FSMC_A7 (GPIO_ALT|GPIO_AF12|GPIO_PORTF|GPIO_PIN13) #define GPIO_FSMC_A7 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN13)
#define GPIO_FSMC_A8 (GPIO_ALT|GPIO_AF12|GPIO_PORTF|GPIO_PIN14) #define GPIO_FSMC_A8 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN14)
#define GPIO_FSMC_A9 (GPIO_ALT|GPIO_AF12|GPIO_PORTF|GPIO_PIN15) #define GPIO_FSMC_A9 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN15)
#define GPIO_FSMC_A10 (GPIO_ALT|GPIO_AF12|GPIO_PORTG|GPIO_PIN0) #define GPIO_FSMC_A10 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN0)
#define GPIO_FSMC_A11 (GPIO_ALT|GPIO_AF12|GPIO_PORTG|GPIO_PIN1) #define GPIO_FSMC_A11 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN1)
#define GPIO_FSMC_A12 (GPIO_ALT|GPIO_AF12|GPIO_PORTG|GPIO_PIN2) #define GPIO_FSMC_A12 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN2)
#define GPIO_FSMC_A13 (GPIO_ALT|GPIO_AF12|GPIO_PORTG|GPIO_PIN3) #define GPIO_FSMC_A13 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN3)
#define GPIO_FSMC_A14 (GPIO_ALT|GPIO_AF12|GPIO_PORTG|GPIO_PIN4) #define GPIO_FSMC_A14 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN4)
#define GPIO_FSMC_A15 (GPIO_ALT|GPIO_AF12|GPIO_PORTG|GPIO_PIN5) #define GPIO_FSMC_A15 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN5)
#define GPIO_FSMC_A16 (GPIO_ALT|GPIO_AF12|GPIO_PORTD|GPIO_PIN11) #define GPIO_FSMC_A16 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN11)
#define GPIO_FSMC_A17 (GPIO_ALT|GPIO_AF12|GPIO_PORTD|GPIO_PIN12) #define GPIO_FSMC_A17 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN12)
#define GPIO_FSMC_A18 (GPIO_ALT|GPIO_AF12|GPIO_PORTD|GPIO_PIN13) #define GPIO_FSMC_A18 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN13)
#define GPIO_FSMC_A19 (GPIO_ALT|GPIO_AF12|GPIO_PORTE|GPIO_PIN3) #define GPIO_FSMC_A19 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN3)
#define GPIO_FSMC_A20 (GPIO_ALT|GPIO_AF12|GPIO_PORTE|GPIO_PIN4) #define GPIO_FSMC_A20 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN4)
#define GPIO_FSMC_A21 (GPIO_ALT|GPIO_AF12|GPIO_PORTE|GPIO_PIN5) #define GPIO_FSMC_A21 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN5)
#define GPIO_FSMC_A22 (GPIO_ALT|GPIO_AF12|GPIO_PORTE|GPIO_PIN6) #define GPIO_FSMC_A22 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN6)
#define GPIO_FSMC_A23 (GPIO_ALT|GPIO_AF12|GPIO_PORTE|GPIO_PIN2) #define GPIO_FSMC_A23 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN2)
#define GPIO_FSMC_A24 (GPIO_ALT|GPIO_AF12|GPIO_PORTG|GPIO_PIN13) #define GPIO_FSMC_A24 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN13)
#define GPIO_FSMC_A25 (GPIO_ALT|GPIO_AF12|GPIO_PORTG|GPIO_PIN14) #define GPIO_FSMC_A25 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN14)
#define GPIO_FSMC_BLN1 (GPIO_ALT|GPIO_AF12|GPIO_PORTE|GPIO_PIN1) #define GPIO_FSMC_NBL1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN1)
#define GPIO_FSMC_CD (GPIO_ALT|GPIO_AF12|GPIO_PORTF|GPIO_PIN9) #define GPIO_FSMC_CD (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN9)
#define GPIO_FSMC_CLK (GPIO_ALT|GPIO_AF12|GPIO_PORTD|GPIO_PIN3) #define GPIO_FSMC_CLK (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN3)
#define GPIO_FSMC_D0 (GPIO_ALT|GPIO_AF12|GPIO_PORTD|GPIO_PIN14) #define GPIO_FSMC_D0 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN14)
#define GPIO_FSMC_D1 (GPIO_ALT|GPIO_AF12|GPIO_PORTD|GPIO_PIN15) #define GPIO_FSMC_D1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN15)
#define GPIO_FSMC_D2 (GPIO_ALT|GPIO_AF12|GPIO_PORTD|GPIO_PIN0) #define GPIO_FSMC_D2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN0)
#define GPIO_FSMC_D3 (GPIO_ALT|GPIO_AF12|GPIO_PORTD|GPIO_PIN1) #define GPIO_FSMC_D3 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN1)
#define GPIO_FSMC_D4 (GPIO_ALT|GPIO_AF12|GPIO_PORTE|GPIO_PIN7) #define GPIO_FSMC_D4 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN7)
#define GPIO_FSMC_D5 (GPIO_ALT|GPIO_AF12|GPIO_PORTE|GPIO_PIN8) #define GPIO_FSMC_D5 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN8)
#define GPIO_FSMC_D6 (GPIO_ALT|GPIO_AF12|GPIO_PORTE|GPIO_PIN9) #define GPIO_FSMC_D6 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN9)
#define GPIO_FSMC_D7 (GPIO_ALT|GPIO_AF12|GPIO_PORTE|GPIO_PIN10) #define GPIO_FSMC_D7 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN10)
#define GPIO_FSMC_D8 (GPIO_ALT|GPIO_AF12|GPIO_PORTE|GPIO_PIN11) #define GPIO_FSMC_D8 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN11)
#define GPIO_FSMC_D9 (GPIO_ALT|GPIO_AF12|GPIO_PORTE|GPIO_PIN12) #define GPIO_FSMC_D9 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN12)
#define GPIO_FSMC_D10 (GPIO_ALT|GPIO_AF12|GPIO_PORTE|GPIO_PIN13) #define GPIO_FSMC_D10 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN13)
#define GPIO_FSMC_D11 (GPIO_ALT|GPIO_AF12|GPIO_PORTE|GPIO_PIN14) #define GPIO_FSMC_D11 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN14)
#define GPIO_FSMC_D12 (GPIO_ALT|GPIO_AF12|GPIO_PORTE|GPIO_PIN15) #define GPIO_FSMC_D12 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN15)
#define GPIO_FSMC_D13 (GPIO_ALT|GPIO_AF12|GPIO_PORTD|GPIO_PIN8) #define GPIO_FSMC_D13 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN8)
#define GPIO_FSMC_D14 (GPIO_ALT|GPIO_AF12|GPIO_PORTD|GPIO_PIN9) #define GPIO_FSMC_D14 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN9)
#define GPIO_FSMC_D15 (GPIO_ALT|GPIO_AF12|GPIO_PORTD|GPIO_PIN10) #define GPIO_FSMC_D15 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN10)
#define GPIO_FSMC_INT2 (GPIO_ALT|GPIO_AF12|GPIO_PORTG|GPIO_PIN6) #define GPIO_FSMC_INT2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN6)
#define GPIO_FSMC_INT3 (GPIO_ALT|GPIO_AF12|GPIO_PORTG|GPIO_PIN7) #define GPIO_FSMC_INT3 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN7)
#define GPIO_FSMC_INTR (GPIO_ALT|GPIO_AF12|GPIO_PORTF|GPIO_PIN10) #define GPIO_FSMC_INTR (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN10)
#define GPIO_FSMC_NBL0 (GPIO_ALT|GPIO_AF12|GPIO_PORTE|GPIO_PIN0) #define GPIO_FSMC_NBL0 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN0)
#define GPIO_FSMC_NCE2 (GPIO_ALT|GPIO_AF12|GPIO_PORTD|GPIO_PIN7) #define GPIO_FSMC_NCE2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN7)
#define GPIO_FSMC_NCE3 (GPIO_ALT|GPIO_AF12|GPIO_PORTG|GPIO_PIN9) #define GPIO_FSMC_NCE3 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN9)
#define GPIO_FSMC_NCE4_1 (GPIO_ALT|GPIO_AF12|GPIO_PORTG|GPIO_PIN10) #define GPIO_FSMC_NCE4_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN10)
#define GPIO_FSMC_NCE4_2 (GPIO_ALT|GPIO_AF12|GPIO_PORTG|GPIO_PIN11) #define GPIO_FSMC_NCE4_2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN11)
#define GPIO_FSMC_NE1 (GPIO_ALT|GPIO_AF12|GPIO_PORTD|GPIO_PIN7) #define GPIO_FSMC_NE1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN7)
#define GPIO_FSMC_NE2 (GPIO_ALT|GPIO_AF12|GPIO_PORTG|GPIO_PIN9) #define GPIO_FSMC_NE2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN9)
#define GPIO_FSMC_NE3 (GPIO_ALT|GPIO_AF12|GPIO_PORTG|GPIO_PIN10) #define GPIO_FSMC_NE3 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN10)
#define GPIO_FSMC_NE4 (GPIO_ALT|GPIO_AF12|GPIO_PORTG|GPIO_PIN12) #define GPIO_FSMC_NE4 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN12)
#define GPIO_FSMC_NIORD (GPIO_ALT|GPIO_AF12|GPIO_PORTF|GPIO_PIN6) #define GPIO_FSMC_NIORD (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN6)
#define GPIO_FSMC_NIOWR (GPIO_ALT|GPIO_AF12|GPIO_PORTF|GPIO_PIN8) #define GPIO_FSMC_NIOWR (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN8)
#define GPIO_FSMC_NL (GPIO_ALT|GPIO_AF12|GPIO_PORTB|GPIO_PIN7) #define GPIO_FSMC_NL (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTB|GPIO_PIN7)
#define GPIO_FSMC_NOE (GPIO_ALT|GPIO_AF12|GPIO_PORTD|GPIO_PIN4) #define GPIO_FSMC_NOE (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN4)
#define GPIO_FSMC_NREG (GPIO_ALT|GPIO_AF12|GPIO_PORTF|GPIO_PIN7) #define GPIO_FSMC_NREG (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN7)
#define GPIO_FSMC_NWAIT (GPIO_ALT|GPIO_AF12|GPIO_PORTD|GPIO_PIN6) #define GPIO_FSMC_NWAIT (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN6)
#define GPIO_FSMC_NWE (GPIO_ALT|GPIO_AF12|GPIO_PORTD|GPIO_PIN5) #define GPIO_FSMC_NWE (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN5)
/* I2C */ /* I2C */
@@ -367,12 +367,12 @@
/* OTG FS/HS */ /* OTG FS/HS */
#define GPIO_OTGFS_DM (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN11) #define GPIO_OTGFS_DM (GPIO_ALT|GPIO_FLOAT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN11)
#define GPIO_OTGFS_DP (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN12) #define GPIO_OTGFS_DP (GPIO_ALT|GPIO_FLOAT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN12)
#define GPIO_OTGFS_ID (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN10) #define GPIO_OTGFS_ID (GPIO_ALT|GPIO_PULLUP|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN10)
#define GPIO_OTGFS_SCL (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN8) #define GPIO_OTGFS_SCL (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN8)
#define GPIO_OTGFS_SDA (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN9) #define GPIO_OTGFS_SDA (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN9)
#define GPIO_OTGFS_SOF (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN8) #define GPIO_OTGFS_SOF (GPIO_ALT|GPIO_FLOAT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN8)
#define GPIO_OTGHS_DM (GPIO_ALT|GPIO_AF12|GPIO_PORTB|GPIO_PIN14) #define GPIO_OTGHS_DM (GPIO_ALT|GPIO_AF12|GPIO_PORTB|GPIO_PIN14)
#define GPIO_OTGHS_DP (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN15) #define GPIO_OTGHS_DP (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN15)
@@ -455,111 +455,178 @@
#define GPIO_TIM1_CH1N_1 (GPIO_ALT|GPIO_AF1|GPIO_PORTA|GPIO_PIN7) #define GPIO_TIM1_CH1N_1 (GPIO_ALT|GPIO_AF1|GPIO_PORTA|GPIO_PIN7)
#define GPIO_TIM1_CH1N_2 (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN13) #define GPIO_TIM1_CH1N_2 (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN13)
#define GPIO_TIM1_CH1N_3 (GPIO_ALT|GPIO_AF1|GPIO_PORTE|GPIO_PIN8) #define GPIO_TIM1_CH1N_3 (GPIO_ALT|GPIO_AF1|GPIO_PORTE|GPIO_PIN8)
#define GPIO_TIM1_CH1OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_PORTA|GPIO_PIN8) #define GPIO_TIM1_CH1IN_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN8)
#define GPIO_TIM1_CH1OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_PORTE|GPIO_PIN9) #define GPIO_TIM1_CH1IN_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN9)
#define GPIO_TIM1_CH1OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN8)
#define GPIO_TIM1_CH1OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN9)
#define GPIO_TIM1_CH2N_1 (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN0) #define GPIO_TIM1_CH2N_1 (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN0)
#define GPIO_TIM1_CH2N_2 (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN14) #define GPIO_TIM1_CH2N_2 (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN14)
#define GPIO_TIM1_CH2N_3 (GPIO_ALT|GPIO_AF1|GPIO_PORTE|GPIO_PIN10) #define GPIO_TIM1_CH2N_3 (GPIO_ALT|GPIO_AF1|GPIO_PORTE|GPIO_PIN10)
#define GPIO_TIM1_CH2OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_PORTA|GPIO_PIN9) #define GPIO_TIM1_CH2IN_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN9)
#define GPIO_TIM1_CH2OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_PORTE|GPIO_PIN11) #define GPIO_TIM1_CH2IN_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN11)
#define GPIO_TIM1_CH2OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN9)
#define GPIO_TIM1_CH2OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN11)
#define GPIO_TIM1_CH3N_1 (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN1) #define GPIO_TIM1_CH3N_1 (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN1)
#define GPIO_TIM1_CH3N_2 (GPIO_ALT|GPIO_AF1|GPIO_PORTC|GPIO_PIN15) #define GPIO_TIM1_CH3N_2 (GPIO_ALT|GPIO_AF1|GPIO_PORTC|GPIO_PIN15)
#define GPIO_TIM1_CH3N_3 (GPIO_ALT|GPIO_AF1|GPIO_PORTE|GPIO_PIN12) #define GPIO_TIM1_CH3N_3 (GPIO_ALT|GPIO_AF1|GPIO_PORTE|GPIO_PIN12)
#define GPIO_TIM1_CH3OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_PORTA|GPIO_PIN10) #define GPIO_TIM1_CH3IN_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN10)
#define GPIO_TIM1_CH3OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_PORTE|GPIO_PIN13) #define GPIO_TIM1_CH3IN_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN13)
#define GPIO_TIM1_CH4OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_PORTA|GPIO_PIN11) #define GPIO_TIM1_CH3OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN10)
#define GPIO_TIM1_CH4OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_PORTE|GPIO_PIN14) #define GPIO_TIM1_CH3OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN13)
#define GPIO_TIM1_ETR_1 (GPIO_ALT|GPIO_AF1|GPIO_PORTA|GPIO_PIN12) #define GPIO_TIM1_CH4IN_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN11)
#define GPIO_TIM1_ETR_2 (GPIO_ALT|GPIO_AF1|GPIO_PORTE|GPIO_PIN7) #define GPIO_TIM1_CH4IN_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN14)
#define GPIO_TIM1_CH4OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN11)
#define GPIO_TIM1_CH4OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN14)
#define GPIO_TIM1_ETR_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN12)
#define GPIO_TIM1_ETR_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN7)
#define GPIO_TIM2_CH1OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_PORTA|GPIO_PIN0) #define GPIO_TIM2_CH1IN_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN0)
#define GPIO_TIM2_CH1OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_PORTA|GPIO_PIN15) #define GPIO_TIM2_CH1IN_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN15)
#define GPIO_TIM2_CH1OUT_3 (GPIO_ALT|GPIO_AF1|GPIO_PORTA|GPIO_PIN5) #define GPIO_TIM2_CH1IN_3 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN5)
#define GPIO_TIM2_CH2OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_PORTA|GPIO_PIN1) #define GPIO_TIM2_CH1OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN0)
#define GPIO_TIM2_CH2OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN3) #define GPIO_TIM2_CH1OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN15)
#define GPIO_TIM2_CH3OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_PORTA|GPIO_PIN2) #define GPIO_TIM2_CH1OUT_3 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN5)
#define GPIO_TIM2_CH3OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN10) #define GPIO_TIM2_CH2IN_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN1)
#define GPIO_TIM2_CH4OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_PORTA|GPIO_PIN3) #define GPIO_TIM2_CH2IN_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN3)
#define GPIO_TIM2_CH4OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN11) #define GPIO_TIM2_CH2OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN1)
#define GPIO_TIM2_ETR_1 (GPIO_ALT|GPIO_AF1|GPIO_PORTA|GPIO_PIN0) #define GPIO_TIM2_CH2OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN3)
#define GPIO_TIM2_ETR_2 (GPIO_ALT|GPIO_AF1|GPIO_PORTA|GPIO_PIN15) #define GPIO_TIM2_CH3IN_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN2)
#define GPIO_TIM2_ETR_3 (GPIO_ALT|GPIO_AF1|GPIO_PORTA|GPIO_PIN5) #define GPIO_TIM2_CH3IN_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN10)
#define GPIO_TIM2_CH3OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN2)
#define GPIO_TIM2_CH3OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN10)
#define GPIO_TIM2_CH4IN_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN3)
#define GPIO_TIM2_CH4IN_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN11)
#define GPIO_TIM2_CH4OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN3)
#define GPIO_TIM2_CH4OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN11)
#define GPIO_TIM2_ETR_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN0)
#define GPIO_TIM2_ETR_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN15)
#define GPIO_TIM2_ETR_3 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN5)
#define GPIO_TIM3_CH1OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_PORTA|GPIO_PIN6) #define GPIO_TIM3_CH1IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN6)
#define GPIO_TIM3_CH1OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_PORTB|GPIO_PIN4) #define GPIO_TIM3_CH1IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN4)
#define GPIO_TIM3_CH1OUT_3 (GPIO_ALT|GPIO_AF2|GPIO_PORTC|GPIO_PIN6) #define GPIO_TIM3_CH1IN_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN6)
#define GPIO_TIM3_CH2OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_PORTA|GPIO_PIN7) #define GPIO_TIM3_CH1OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN6)
#define GPIO_TIM3_CH2OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_PORTB|GPIO_PIN5) #define GPIO_TIM3_CH1OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN4)
#define GPIO_TIM3_CH2OUT_3 (GPIO_ALT|GPIO_AF2|GPIO_PORTC|GPIO_PIN7) #define GPIO_TIM3_CH1OUT_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN6)
#define GPIO_TIM3_CH3OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_PORTB|GPIO_PIN0) #define GPIO_TIM3_CH2IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN7)
#define GPIO_TIM3_CH3OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_PORTC|GPIO_PIN8) #define GPIO_TIM3_CH2IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN5)
#define GPIO_TIM3_CH4OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_PORTB|GPIO_PIN1) #define GPIO_TIM3_CH2IN_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN7)
#define GPIO_TIM3_CH4OUT_3 (GPIO_ALT|GPIO_AF2|GPIO_PORTC|GPIO_PIN9) #define GPIO_TIM3_CH2OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN7)
#define GPIO_TIM3_ETR (GPIO_ALT|GPIO_AF2|GPIO_PORTD|GPIO_PIN2) #define GPIO_TIM3_CH2OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN5)
#define GPIO_TIM3_CH2OUT_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN7)
#define GPIO_TIM3_CH3IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN0)
#define GPIO_TIM3_CH3IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN8)
#define GPIO_TIM3_CH3OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN0)
#define GPIO_TIM3_CH3OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN8)
#define GPIO_TIM3_CH4IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN1)
#define GPIO_TIM3_CH4IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN9)
#define GPIO_TIM3_CH4OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN1)
#define GPIO_TIM3_CH4OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN9)
#define GPIO_TIM3_ETR (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN2)
#define GPIO_TIM4_CH1OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_PORTB|GPIO_PIN6) #define GPIO_TIM4_CH1IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN6)
#define GPIO_TIM4_CH1OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_PORTD|GPIO_PIN12) #define GPIO_TIM4_CH1IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN12)
#define GPIO_TIM4_CH2OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_PORTB|GPIO_PIN7) #define GPIO_TIM4_CH1OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN6)
#define GPIO_TIM4_CH2OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_PORTD|GPIO_PIN13) #define GPIO_TIM4_CH1OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN12)
#define GPIO_TIM4_CH3OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_PORTB|GPIO_PIN8) #define GPIO_TIM4_CH2IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN7)
#define GPIO_TIM4_CH3OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_PORTD|GPIO_PIN14) #define GPIO_TIM4_CH2IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN13)
#define GPIO_TIM4_CH4OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_PORTB|GPIO_PIN9) #define GPIO_TIM4_CH2OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN7)
#define GPIO_TIM4_CH4OUT_3 (GPIO_ALT|GPIO_AF2|GPIO_PORTD|GPIO_PIN15) #define GPIO_TIM4_CH2OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN13)
#define GPIO_TIM4_ETR (GPIO_ALT|GPIO_AF2|GPIO_PORTE|GPIO_PIN0) #define GPIO_TIM4_CH3IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN8)
#define GPIO_TIM4_CH3IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN14)
#define GPIO_TIM4_CH3OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN8)
#define GPIO_TIM4_CH3OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN14)
#define GPIO_TIM4_CH4IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN9)
#define GPIO_TIM4_CH4IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN15)
#define GPIO_TIM4_CH4OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN9)
#define GPIO_TIM4_CH4OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN15)
#define GPIO_TIM4_ETR (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN0)
#define GPIO_TIM5_CH1OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_PORTA|GPIO_PIN0) #define GPIO_TIM5_CH1IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN0)
#define GPIO_TIM5_CH1OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_PORTH|GPIO_PIN10) #define GPIO_TIM5_CH1IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTH|GPIO_PIN10)
#define GPIO_TIM5_CH2OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_PORTA|GPIO_PIN1) #define GPIO_TIM5_CH1OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN0)
#define GPIO_TIM5_CH2OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_PORTH|GPIO_PIN11) #define GPIO_TIM5_CH1OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN10)
#define GPIO_TIM5_CH3OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_PORTA|GPIO_PIN2) #define GPIO_TIM5_CH2IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN1)
#define GPIO_TIM5_CH3OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_PORTH|GPIO_PIN12) #define GPIO_TIM5_CH2IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTH|GPIO_PIN11)
#define GPIO_TIM5_CH4OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_PORTA|GPIO_PIN3) #define GPIO_TIM5_CH2OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN1)
#define GPIO_TIM5_CH4OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_PORTI|GPIO_PIN0) #define GPIO_TIM5_CH2OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN11)
#define GPIO_TIM5_ETR (GPIO_ALT|GPIO_AF2|GPIO_PORTH|GPIO_PIN10) #define GPIO_TIM5_CH3IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN2)
#define GPIO_TIM5_CH3IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTH|GPIO_PIN12)
#define GPIO_TIM5_CH3OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN2)
#define GPIO_TIM5_CH3OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN12)
#define GPIO_TIM5_CH4IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN3)
#define GPIO_TIM5_CH4IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTI|GPIO_PIN0)
#define GPIO_TIM5_CH4OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN3)
#define GPIO_TIM5_CH4OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN0)
#define GPIO_TIM5_ETR (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTH|GPIO_PIN10)
#define GPIO_TIM8_BKIN_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN6) #define GPIO_TIM8_BKIN_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN6)
#define GPIO_TIM8_BKIN_2 (GPIO_ALT|GPIO_AF3|GPIO_PORTI|GPIO_PIN4) #define GPIO_TIM8_BKIN_2 (GPIO_ALT|GPIO_AF3|GPIO_PORTI|GPIO_PIN4)
#define GPIO_TIM8_CH1N_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN5) #define GPIO_TIM8_CH1N_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN5)
#define GPIO_TIM8_CH1N_2 (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN7) #define GPIO_TIM8_CH1N_2 (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN7)
#define GPIO_TIM8_CH1N_3 (GPIO_ALT|GPIO_AF3|GPIO_PORTH|GPIO_PIN13) #define GPIO_TIM8_CH1N_3 (GPIO_ALT|GPIO_AF3|GPIO_PORTH|GPIO_PIN13)
#define GPIO_TIM8_CH1OUT_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTC|GPIO_PIN6) #define GPIO_TIM8_CH1IN_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN6)
#define GPIO_TIM8_CH1OUT_2 (GPIO_ALT|GPIO_AF3|GPIO_PORTI|GPIO_PIN5) #define GPIO_TIM8_CH1IN_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTI|GPIO_PIN5)
#define GPIO_TIM8_CH2OUT_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTC|GPIO_PIN7) #define GPIO_TIM8_CH1OUT_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN6)
#define GPIO_TIM8_CH2OUT_2 (GPIO_ALT|GPIO_AF3|GPIO_PORTI|GPIO_PIN6) #define GPIO_TIM8_CH1OUT_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN5)
#define GPIO_TIM8_CH2IN_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN7)
#define GPIO_TIM8_CH2IN_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTI|GPIO_PIN6)
#define GPIO_TIM8_CH2OUT_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN7)
#define GPIO_TIM8_CH2OUT_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN6)
#define GPIO_TIM8_CH2N_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN0) #define GPIO_TIM8_CH2N_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN0)
#define GPIO_TIM8_CH2N_2 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN14) #define GPIO_TIM8_CH2N_2 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN14)
#define GPIO_TIM8_CH2N_3 (GPIO_ALT|GPIO_AF3|GPIO_PORTH|GPIO_PIN14) #define GPIO_TIM8_CH2N_3 (GPIO_ALT|GPIO_AF3|GPIO_PORTH|GPIO_PIN14)
#define GPIO_TIM8_CH3N_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN1) #define GPIO_TIM8_CH3N_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN1)
#define GPIO_TIM8_CH3N_2 (GPIO_ALT|GPIO_AF3|GPIO_PORTC|GPIO_PIN15) #define GPIO_TIM8_CH3N_2 (GPIO_ALT|GPIO_AF3|GPIO_PORTC|GPIO_PIN15)
#define GPIO_TIM8_CH3N_3 (GPIO_ALT|GPIO_AF3|GPIO_PORTH|GPIO_PIN15) #define GPIO_TIM8_CH3N_3 (GPIO_ALT|GPIO_AF3|GPIO_PORTH|GPIO_PIN15)
#define GPIO_TIM8_CH3OUT_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTC|GPIO_PIN8) #define GPIO_TIM8_CH3IN_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN8)
#define GPIO_TIM8_CH3OUT_2 (GPIO_ALT|GPIO_AF3|GPIO_PORTI|GPIO_PIN7) #define GPIO_TIM8_CH3IN_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTI|GPIO_PIN7)
#define GPIO_TIM8_CH4OUT_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTC|GPIO_PIN9) #define GPIO_TIM8_CH3OUT_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN8)
#define GPIO_TIM8_CH4OUT_2 (GPIO_ALT|GPIO_AF3|GPIO_PORTI|GPIO_PIN2) #define GPIO_TIM8_CH3OUT_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN7)
#define GPIO_TIM8_ETR_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN0) #define GPIO_TIM8_CH4IN_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN9)
#define GPIO_TIM8_ETR_2 (GPIO_ALT|GPIO_AF3|GPIO_PORTI|GPIO_PIN3) #define GPIO_TIM8_CH4IN_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTI|GPIO_PIN2)
#define GPIO_TIM8_CH4OUT_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN9)
#define GPIO_TIM8_CH4OUT_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN2)
#define GPIO_TIM8_ETR_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN0)
#define GPIO_TIM8_ETR_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTI|GPIO_PIN3)
#define GPIO_TIM9_CH1OUT_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN2) #define GPIO_TIM9_CH1IN_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN2)
#define GPIO_TIM9_CH1OUT_2 (GPIO_ALT|GPIO_AF3|GPIO_PORTE|GPIO_PIN5) #define GPIO_TIM9_CH1IN_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN5)
#define GPIO_TIM9_CH2OUT_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN3) #define GPIO_TIM9_CH1OUT_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN2)
#define GPIO_TIM9_CH2OUT_2 (GPIO_ALT|GPIO_AF3|GPIO_PORTE|GPIO_PIN6) #define GPIO_TIM9_CH1OUT_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN5)
#define GPIO_TIM9_CH2IN_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN3)
#define GPIO_TIM9_CH2IN_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN6)
#define GPIO_TIM9_CH2OUT_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN3)
#define GPIO_TIM9_CH2OUT_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN6)
#define GPIO_TIM10_CH1OUT_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN8) #define GPIO_TIM10_CH1IN_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN8)
#define GPIO_TIM10_CH1OUT_2 (GPIO_ALT|GPIO_AF3|GPIO_PORTF|GPIO_PIN6) #define GPIO_TIM10_CH1IN_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN6)
#define GPIO_TIM10_CH1OUT_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN8)
#define GPIO_TIM10_CH1OUT_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN6)
#define GPIO_TIM11_CH1OUT_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN9) #define GPIO_TIM11_CH1IN_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN9)
#define GPIO_TIM11_CH1OUT_2 (GPIO_ALT|GPIO_AF3|GPIO_PORTF|GPIO_PIN7) #define GPIO_TIM11_CH1IN_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN7)
#define GPIO_TIM11_CH1OUT_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN9)
#define GPIO_TIM11_CH1OUT_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN7)
#define GPIO_TIM12_CH1OUT_1 (GPIO_ALT|GPIO_AF8|GPIO_PORTH|GPIO_PIN6) #define GPIO_TIM12_CH1IN_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTH|GPIO_PIN6)
#define GPIO_TIM12_CH1OUT_2 (GPIO_ALT|GPIO_AF9|GPIO_PORTB|GPIO_PIN14) #define GPIO_TIM12_CH1IN_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN14)
#define GPIO_TIM12_CH2OUT_1 (GPIO_ALT|GPIO_AF9|GPIO_PORTC|GPIO_PIN15) #define GPIO_TIM12_CH1OUT_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN6)
#define GPIO_TIM12_CH2OUT_2 (GPIO_ALT|GPIO_AF9|GPIO_PORTH|GPIO_PIN9) #define GPIO_TIM12_CH1OUT_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN14)
#define GPIO_TIM12_CH2IN_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN15)
#define GPIO_TIM12_CH2IN_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTH|GPIO_PIN9)
#define GPIO_TIM12_CH2OUT_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN15)
#define GPIO_TIM12_CH2OUT_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN9)
#define GPIO_TIM13_CH1OUT_1 (GPIO_ALT|GPIO_AF9|GPIO_PORTA|GPIO_PIN6) #define GPIO_TIM13_CH1IN_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN6)
#define GPIO_TIM13_CH1OUT_2 (GPIO_ALT|GPIO_AF9|GPIO_PORTF|GPIO_PIN8) #define GPIO_TIM13_CH1IN_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN8)
#define GPIO_TIM13_CH1OUT_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN6)
#define GPIO_TIM13_CH1OUT_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN8)
#define GPIO_TIM14_CH1OUT_1 (GPIO_ALT|GPIO_AF9|GPIO_PORTA|GPIO_PIN7) #define GPIO_TIM14_CH1IN_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN7)
#define GPIO_TIM14_CH1OUT_2 (GPIO_ALT|GPIO_AF9|GPIO_PORTF|GPIO_PIN9) #define GPIO_TIM14_CH1IN_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN9)
#define GPIO_TIM14_CH1OUT_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN7)
#define GPIO_TIM14_CH1OUT_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN9)
/* Trace */ /* Trace */
arch/arm/src/stm32/chip/stm32f20xxx_rcc.h
+2 -2
View File
@@ -1,7 +1,7 @@
/**************************************************************************************************** /****************************************************************************************************
* arch/arm/src/stm32/chip/stm32f20xxx_rcc.h * arch/arm/src/stm32/chip/stm32f20xxx_rcc.h
* *
* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. * Copyright (C) 2012 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org> * Author: Gregory Nutt <gnutt@nuttx.org>
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
@@ -240,7 +240,7 @@
#define RCC_AHB1RSTR_GPIOGRST (1 << 6) /* Bit 6: IO port G reset */ #define RCC_AHB1RSTR_GPIOGRST (1 << 6) /* Bit 6: IO port G reset */
#define RCC_AHB1RSTR_GPIOHRST (1 << 7) /* Bit 7: IO port H reset */ #define RCC_AHB1RSTR_GPIOHRST (1 << 7) /* Bit 7: IO port H reset */
#define RCC_AHB1RSTR_CRCRST (1 << 12) /* Bit 12 IO port I reset */ #define RCC_AHB1RSTR_CRCRST (1 << 12) /* Bit 12 IO port I reset */
#define RCC_AHB1RSTR_DMA1RST (1 << 21) /* Bit 21: DMA2 reset */ #define RCC_AHB1RSTR_DMA1RST (1 << 21) /* Bit 21: DMA1 reset */
#define RCC_AHB1RSTR_DMA2RST (1 << 22) /* Bit 22: DMA2 reset */ #define RCC_AHB1RSTR_DMA2RST (1 << 22) /* Bit 22: DMA2 reset */
#define RCC_AHB1RSTR_ETHMACRST (1 << 25) /* Bit 25: Ethernet MAC reset */ #define RCC_AHB1RSTR_ETHMACRST (1 << 25) /* Bit 25: Ethernet MAC reset */
#define RCC_AHB1RSTR_OTGHSRST (1 << 29) /* Bit 29: USB OTG HS module reset */ #define RCC_AHB1RSTR_OTGHSRST (1 << 29) /* Bit 29: USB OTG HS module reset */
arch/arm/src/stm32/chip/stm32f20xxx_rtc.h
+2 -2
View File
@@ -1,8 +1,8 @@
/************************************************************************************ /************************************************************************************
* arch/arm/src/stm32/chip/stm32f20xxx_rtc.h * arch/arm/src/stm32/chip/stm32f20xxx_rtc.h
* *
* Copyright (C) 2011 Gregory Nutt. All rights reserved. * Copyright (C) 2012 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr> * Author: Gregory Nutt <gnutt@nuttx.org>
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions * modification, are permitted provided that the following conditions
arch/arm/src/stm32/stm32f20xxx_dma.c
+299 -57
View File
@@ -1,7 +1,7 @@
/**************************************************************************** /****************************************************************************
* arch/arm/src/stm32/stm32f20xxx_dma.c * arch/arm/src/stm32/stm32f20xxx_dma.c
* *
* Copyright (C) 2011 Gregory Nutt. All rights reserved. * Copyright (C) 2012 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org> * Author: Gregory Nutt <gnutt@nuttx.org>
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
@@ -56,7 +56,8 @@
#include "stm32_dma.h" #include "stm32_dma.h"
#include "stm32_internal.h" #include "stm32_internal.h"
/* This file supports only the STM32 F2 family /* This file supports only the STM32 F2 family (although it is identical to
* the corresponding F4 file).
*/ */
#if defined(CONFIG_STM32_STM32F20XX) #if defined(CONFIG_STM32_STM32F20XX)
@@ -92,7 +93,8 @@ struct stm32_dma_s
uint8_t stream; /* DMA stream number (0-7) */ uint8_t stream; /* DMA stream number (0-7) */
uint8_t irq; /* DMA stream IRQ number */ uint8_t irq; /* DMA stream IRQ number */
uint8_t shift; /* ISR/IFCR bit shift value */ uint8_t shift; /* ISR/IFCR bit shift value */
uint8_t pad; /* Unused */ uint8_t channel; /* DMA channel number (0-7) */
bool nonstop; /* Stream is configured in a non-stopping mode. */
sem_t sem; /* Used to wait for DMA channel to become available */ sem_t sem; /* Used to wait for DMA channel to become available */
uint32_t base; /* DMA register channel base address */ uint32_t base; /* DMA register channel base address */
dma_callback_t callback; /* Callback invoked when the DMA completes */ dma_callback_t callback; /* Callback invoked when the DMA completes */
@@ -269,6 +271,59 @@ static inline void stm32_dmagive(FAR struct stm32_dma_s *dmast)
(void)sem_post(&dmast->sem); (void)sem_post(&dmast->sem);
} }
/************************************************************************************
* Name: stm32_dmastream
*
* Description:
* Get the g_dma table entry associated with a DMA controller and a stream number
*
************************************************************************************/
static inline FAR struct stm32_dma_s *stm32_dmastream(unsigned int stream,
unsigned int controller)
{
int index;
DEBUGASSERT(stream < DMA_NSTREAMS && controller < STM32_NDMA);
/* Convert the controller + stream based on the fact that there are 8 streams
* per controller.
*/
#if STM32_NDMA > 1
index = controller << 3 | stream;
#else
index = stream;
#endif
/* Then return the stream structure associated with the stream index */
return &g_dma[index];
}
/************************************************************************************
* Name: stm32_dmamap
*
* Description:
* Get the g_dma table entry associated with a bit-encoded DMA selection
*
************************************************************************************/
static inline FAR struct stm32_dma_s *stm32_dmamap(unsigned long dmamap)
{
/* Extract the DMA controller number from the bit encoded value */
unsigned int controller = STM32_DMA_CONTROLLER(dmamap);
/* Extact the stream number from the bit encoded value */
unsigned int stream = STM32_DMA_STREAM(dmamap);
/* Return the table entry associated with the controller + stream */
return stm32_dmastream(stream, controller);
}
/************************************************************************************ /************************************************************************************
* Name: stm32_dmastreamdisable * Name: stm32_dmastreamdisable
* *
@@ -319,44 +374,82 @@ static void stm32_dmastreamdisable(struct stm32_dma_s *dmast)
static int stm32_dmainterrupt(int irq, void *context) static int stm32_dmainterrupt(int irq, void *context)
{ {
struct stm32_dma_s *dmast; struct stm32_dma_s *dmast;
uint32_t isr; uint32_t status;
uint32_t regoffset = 0; uint32_t regoffset = 0;
int stndx = 0; unsigned int stream = 0;
unsigned int controller = 0;
/* Get the stream structure from the interrupt number */ /* Get the stream and the controller that generated the interrupt */
if (irq >= STM32_IRQ_DMA1S0 && irq <= STM32_IRQ_DMA1S7) if (irq >= STM32_IRQ_DMA1S0 && irq <= STM32_IRQ_DMA1S6)
{ {
stndx = irq - STM32_IRQ_DMA1S0; stream = irq - STM32_IRQ_DMA1S0;
regoffset = STM32_DMA_LISR_OFFSET; controller = DMA1;
}
else if (irq == STM32_IRQ_DMA1S7)
{
stream = 7;
controller = DMA1;
} }
else else
#if STM32_NDMA > 1 #if STM32_NDMA > 1
if (irq >= STM32_IRQ_DMA2S0 && irq <= STM32_IRQ_DMA2S7) if (irq >= STM32_IRQ_DMA2S0 && irq <= STM32_IRQ_DMA2S4)
{ {
stndx = irq - STM32_IRQ_DMA2S0 + DMA1_NSTREAMS; stream = irq - STM32_IRQ_DMA2S0;
regoffset = STM32_DMA_HISR_OFFSET; controller = DMA2;
}
else if (irq >= STM32_IRQ_DMA2S5 && irq <= STM32_IRQ_DMA2S7)
{
stream = irq - STM32_IRQ_DMA2S5 + 5;
controller = DMA2;
} }
else else
#endif #endif
{ {
PANIC(OSERR_INTERNAL); PANIC(OSERR_INTERNAL);
} }
dmast = &g_dma[stndx];
/* Get the stream structure from the stream and controller numbers */
dmast = stm32_dmastream(stream, controller);
/* Select the interrupt status register (either the LISR or HISR)
* based on the stream number that caused the interrupt.
*/
if (stream < 4)
{
regoffset = STM32_DMA_LISR_OFFSET;
}
else
{
regoffset = STM32_DMA_HISR_OFFSET;
}
/* Get the interrupt status for this stream */ /* Get the interrupt status for this stream */
isr = (dmabase_getreg(dmast, regoffset) >> dmast->shift) & DMA_STREAM_MASK; status = (dmabase_getreg(dmast, regoffset) >> dmast->shift) & DMA_STREAM_MASK;
/* Disable the DMA stream */ /* Clear fetched stream interrupts by setting bits in the upper or lower IFCR
* register
*/
stm32_dmastreamdisable(dmast); if (stream < 4)
{
regoffset = STM32_DMA_LIFCR_OFFSET;
}
else
{
regoffset = STM32_DMA_HIFCR_OFFSET;
}
dmabase_putreg(dmast, regoffset, (status << dmast->shift));
/* Invoke the callback */ /* Invoke the callback */
if (dmast->callback) if (dmast->callback)
{ {
dmast->callback(dmast, isr, dmast->arg); dmast->callback(dmast, status, dmast->arg);
} }
return OK; return OK;
} }
@@ -379,13 +472,13 @@ static int stm32_dmainterrupt(int irq, void *context)
void weak_function up_dmainitialize(void) void weak_function up_dmainitialize(void)
{ {
struct stm32_dma_s *dmast; struct stm32_dma_s *dmast;
int stndx; int stream;
/* Initialize each DMA stream */ /* Initialize each DMA stream */
for (stndx = 0; stndx < DMA_NSTREAMS; stndx++) for (stream = 0; stream < DMA_NSTREAMS; stream++)
{ {
dmast = &g_dma[stndx]; dmast = &g_dma[stream];
sem_init(&dmast->sem, 0, 1); sem_init(&dmast->sem, 0, 1);
/* Attach DMA interrupt vectors */ /* Attach DMA interrupt vectors */
@@ -411,7 +504,7 @@ void weak_function up_dmainitialize(void)
* *
* Description: * Description:
* Allocate a DMA channel. This function gives the caller mutually * Allocate a DMA channel. This function gives the caller mutually
* exclusive access to the DMA channel specified by the 'stndx' argument. * exclusive access to the DMA channel specified by the 'dmamap' argument.
* DMA channels are shared on the STM32: Devices sharing the same DMA * DMA channels are shared on the STM32: Devices sharing the same DMA
* channel cannot do DMA concurrently! See the DMACHAN_* definitions in * channel cannot do DMA concurrently! See the DMACHAN_* definitions in
* stm32_dma.h. * stm32_dma.h.
@@ -426,9 +519,14 @@ void weak_function up_dmainitialize(void)
* Hmm.. I suppose this interface could be extended to make a non-blocking * Hmm.. I suppose this interface could be extended to make a non-blocking
* version. Feel free to do that if that is what you need. * version. Feel free to do that if that is what you need.
* *
* Input parameter:
* dmamap - Identifies the stream/channel resource. For the STM32 F2, this
* is a bit-encoded value as provided by the the DMAMAP_* definitions
* in chip/stm32f20xxx_dma.h
*
* Returned Value: * Returned Value:
* Provided that 'stndx' is valid, this function ALWAYS returns a non-NULL, * Provided that 'dmamap' is valid, this function ALWAYS returns a non-NULL,
* void* DMA channel handle. (If 'stndx' is invalid, the function will * void* DMA channel handle. (If 'dmamap' is invalid, the function will
* assert if debug is enabled or do something ignorant otherwise). * assert if debug is enabled or do something ignorant otherwise).
* *
* Assumptions: * Assumptions:
@@ -438,11 +536,14 @@ void weak_function up_dmainitialize(void)
* *
****************************************************************************/ ****************************************************************************/
DMA_HANDLE stm32_dmachannel(int stndx) DMA_HANDLE stm32_dmachannel(unsigned int dmamap)
{ {
struct stm32_dma_s *dmast = &g_dma[stndx]; FAR struct stm32_dma_s *dmast;
DEBUGASSERT(stndx < DMA_NSTREAMS); /* Get the stream index from the bit-encoded channel value */
dmast = stm32_dmamap(dmamap);
DEBUGASSERT(dmast != NULL);
/* Get exclusive access to the DMA channel -- OR wait until the channel /* Get exclusive access to the DMA channel -- OR wait until the channel
* is available if it is currently being used by another driver * is available if it is currently being used by another driver
@@ -450,8 +551,12 @@ DMA_HANDLE stm32_dmachannel(int stndx)
stm32_dmatake(dmast); stm32_dmatake(dmast);
/* The caller now has exclusive use of the DMA channel */ /* The caller now has exclusive use of the DMA channel. Assign the
* channel to the stream and return an opaque reference to the stream
* structure.
*/
dmast->channel = STM32_DMA_CHANNEL(dmamap);
return (DMA_HANDLE)dmast; return (DMA_HANDLE)dmast;
} }
@@ -493,46 +598,137 @@ void stm32_dmafree(DMA_HANDLE handle)
* *
****************************************************************************/ ****************************************************************************/
void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, size_t ntransfers, uint32_t scr) void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr,
size_t ntransfers, uint32_t scr)
{ {
struct stm32_dma_s *dmast = (struct stm32_dma_s *)handle; struct stm32_dma_s *dmast = (struct stm32_dma_s *)handle;
uint32_t regoffset;
uint32_t regval; uint32_t regval;
/* Set the peripheral register address in the DMA_SPARx register. The data dmadbg("paddr: %08x maddr: %08x ntransfers: %d scr: %08x\n",
* will be moved from/to this address to/from the memory after the paddr, maddr, ntransfers, scr);
* peripheral event.
/* "If the stream is enabled, disable it by resetting the EN bit in the
* DMA_SxCR register, then read this bit in order to confirm that there is no
* ongoing stream operation. Writing this bit to 0 is not immediately
* effective since it is actually written to 0 once all the current transfers
* have finished. When the EN bit is read as 0, this means that the stream is
* ready to be configured. It is therefore necessary to wait for the EN bit
* to be cleared before starting any stream configuration. ..."
*/
while ((dmast_getreg(dmast, STM32_DMA_SCR_OFFSET) & DMA_SCR_EN) != 0);
/* "... All the stream dedicated bits set in the status register (DMA_LISR
* and DMA_HISR) from the previous data block DMA transfer should be cleared
* before the stream can be re-enabled."
*
* Clear pending stream interrupts by setting bits in the upper or lower IFCR
* register
*/
if (dmast->stream < 4)
{
regoffset = STM32_DMA_LIFCR_OFFSET;
}
else
{
regoffset = STM32_DMA_HIFCR_OFFSET;
}
dmabase_putreg(dmast, regoffset, (DMA_STREAM_MASK << dmast->shift));
/* "Set the peripheral register address in the DMA_SPARx register. The data
* will be moved from/to this address to/from the memory after the
* peripheral event.
*/ */
dmast_putreg(dmast, STM32_DMA_SPAR_OFFSET, paddr); dmast_putreg(dmast, STM32_DMA_SPAR_OFFSET, paddr);
/* Set the memory address in the DMA_SM0ARx register. The data will be /* "Set the memory address in the DMA_SM0ARx ... register. The data will be
* written to or read from this memory after the peripheral event. * written to or read from this memory after the peripheral event."
* Note that only single-buffer mode is currently supported so SM1ARx *
* is not used. * Note that in double-buffered mode it is explicitly assumed that the second
* buffer immediately follows the first.
*/ */
dmast_putreg(dmast, STM32_DMA_SM0AR_OFFSET, maddr); dmast_putreg(dmast, STM32_DMA_SM0AR_OFFSET, maddr);
if (scr & DMA_SCR_DBM)
{
dmast_putreg(dmast, STM32_DMA_SM1AR_OFFSET, maddr + ntransfers);
}
/* Configure the total number of data items to be transferred in the DMA_SNDTRx /* "Configure the total number of data items to be transferred in the
* register. After each peripheral event, this value will be decremented. * DMA_SNDTRx register. After each peripheral event, this value will be
* decremented."
*
* "When the peripheral flow controller is used for a given stream, the value
* written into the DMA_SxNDTR has no effect on the DMA transfer. Actually,
* whatever the value written, it will be forced by hardware to 0xFFFF as soon
* as the stream is enabled..."
*/ */
dmast_putreg(dmast, STM32_DMA_SNDTR_OFFSET, ntransfers); dmast_putreg(dmast, STM32_DMA_SNDTR_OFFSET, ntransfers);
/* Configure the stream priority using the PL[1:0] bits in the DMA_SCRx /* "Select the DMA channel (request) using CHSEL[2:0] in the DMA_SxCR register."
* register. Configure data transfer direction, circular mode, peripheral & memory *
* incremented mode, peripheral & memory data size, and interrupt after * "Configure the stream priority using the PL[1:0] bits in the DMA_SCRx"
* half and/or full transfer in the DMA_CCRx register. * register."
*/ */
regval = dmast_getreg(dmast, STM32_DMA_SCR_OFFSET); regval = dmast_getreg(dmast, STM32_DMA_SCR_OFFSET);
regval &= ~(DMA_SCR_DIR_MASK|DMA_SCR_PINC|DMA_SCR_MINC|DMA_SCR_PSIZE_MASK| regval &= ~(DMA_SCR_PL_MASK|DMA_SCR_CHSEL_MASK);
DMA_SCR_MSIZE_MASK|DMA_SCR_PINCOS|DMA_SCR_PL_MASK|DMA_SCR_PBURST_MASK| regval |= scr & DMA_SCR_PL_MASK;
DMA_SCR_MBURST_MASK); regval |= (uint32_t)dmast->channel << DMA_SCR_CHSEL_SHIFT;
scr &= (DMA_SCR_DIR_MASK|DMA_SCR_PINC|DMA_SCR_MINC|DMA_SCR_PSIZE_MASK| dmast_putreg(dmast, STM32_DMA_SCR_OFFSET, regval);
DMA_SCR_MSIZE_MASK|DMA_SCR_PINCOS|DMA_SCR_PL_MASK|DMA_SCR_PBURST_MASK|
DMA_SCR_MBURST_MASK); /* "Configure the FIFO usage (enable or disable, threshold in transmission and
* reception)"
*
* "Caution is required when choosing the FIFO threshold (bits FTH[1:0] of the
* DMA_SxFCR register) and the size of the memory burst (MBURST[1:0] of the
* DMA_SxCR register): The content pointed by the FIFO threshold must exactly
* match to an integer number of memory burst transfers. If this is not in the
* case, a FIFO error (flag FEIFx of the DMA_HISR or DMA_LISR register) will be
* generated when the stream is enabled, then the stream will be automatically
* disabled."
*
* The FIFO is disabled in circular mode when transferring data from a
* peripheral to memory, as in this case it is usually desirable to know that
* every byte from the peripheral is transferred immediately to memory. It is
* not practical to flush the DMA FIFO, as this requires disabling the channel
* which triggers the transfer-complete interrupt.
*
* NOTE: The FEIFx error interrupt is not enabled because the FEIFx seems to
* be reported spuriously causing good transfers to be marked as failures.
*/
regval = dmast_getreg(dmast, STM32_DMA_SFCR_OFFSET);
regval &= ~(DMA_SFCR_FTH_MASK | DMA_SFCR_FS_MASK | DMA_SFCR_FEIE);
if (!((scr & (DMA_SCR_CIRC | DMA_SCR_DIR_MASK)) == (DMA_SCR_CIRC | DMA_SCR_DIR_P2M)))
{
regval |= (DMA_SFCR_FTH_FULL | DMA_SFCR_DMDIS);
}
dmast_putreg(dmast, STM32_DMA_SFCR_OFFSET, regval);
/* "Configure data transfer direction, circular mode, peripheral & memory
* incremented mode, peripheral & memory data size, and interrupt after
* half and/or full transfer in the DMA_CCRx register."
*
* Note: The CT bit is always reset.
*/
regval = dmast_getreg(dmast, STM32_DMA_SCR_OFFSET);
regval &= ~(DMA_SCR_PFCTRL|DMA_SCR_DIR_MASK|DMA_SCR_PINC|DMA_SCR_MINC|
DMA_SCR_PSIZE_MASK|DMA_SCR_MSIZE_MASK|DMA_SCR_PINCOS|
DMA_SCR_CIRC|DMA_SCR_DBM|DMA_SCR_CT|
DMA_SCR_PBURST_MASK|DMA_SCR_MBURST_MASK);
scr &= (DMA_SCR_PFCTRL|DMA_SCR_DIR_MASK|DMA_SCR_PINC|DMA_SCR_MINC|
DMA_SCR_PSIZE_MASK|DMA_SCR_MSIZE_MASK|DMA_SCR_PINCOS|
DMA_SCR_DBM|DMA_SCR_CIRC|
DMA_SCR_PBURST_MASK|DMA_SCR_MBURST_MASK);
regval |= scr; regval |= scr;
dmast->nonstop = (scr & (DMA_SCR_DBM|DMA_SCR_CIRC)) != 0;
dmast_putreg(dmast, STM32_DMA_SCR_OFFSET, regval); dmast_putreg(dmast, STM32_DMA_SCR_OFFSET, regval);
} }
@@ -568,14 +764,28 @@ void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, bool
scr = dmast_getreg(dmast, STM32_DMA_SCR_OFFSET); scr = dmast_getreg(dmast, STM32_DMA_SCR_OFFSET);
scr |= DMA_SCR_EN; scr |= DMA_SCR_EN;
/* Once half of the bytes are transferred, the half-transfer flag (HTIF) is if (!dmast->nonstop)
* set and an interrupt is generated if the Half-Transfer Interrupt Enable {
* bit (HTIE) is set. At the end of the transfer, the Transfer Complete Flag /* Once half of the bytes are transferred, the half-transfer flag (HTIF) is
* (TCIF) is set and an interrupt is generated if the Transfer Complete * set and an interrupt is generated if the Half-Transfer Interrupt Enable
* Interrupt Enable bit (TCIE) is set. * bit (HTIE) is set. At the end of the transfer, the Transfer Complete Flag
*/ * (TCIF) is set and an interrupt is generated if the Transfer Complete
* Interrupt Enable bit (TCIE) is set.
*/
scr |= (half ? (DMA_SCR_HTIE|DMA_SCR_TEIE) : (DMA_SCR_TCIE|DMA_SCR_TEIE));
}
else
{
/* In nonstop mode, when the transfer completes it immediately resets
* and starts again. The transfer-complete interrupt is thus always
* enabled, and the half-complete interrupt can be used in circular
* mode to determine when the buffer is half-full, or in double-buffered
* mode to determine when one of the two buffers is full.
*/
scr |= (half ? DMA_SCR_HTIE : 0) | DMA_SCR_TCIE | DMA_SCR_TEIE;
}
scr |= (half ? (DMA_SCR_HTIE|DMA_SCR_TEIE) : (DMA_SCR_TCIE|DMA_SCR_TEIE));
dmast_putreg(dmast, STM32_DMA_SCR_OFFSET, scr); dmast_putreg(dmast, STM32_DMA_SCR_OFFSET, scr);
} }
@@ -598,6 +808,38 @@ void stm32_dmastop(DMA_HANDLE handle)
stm32_dmastreamdisable(dmast); stm32_dmastreamdisable(dmast);
} }
/****************************************************************************
* Name: stm32_dmaresidual
*
* Description:
* Read the DMA bytes-remaining register.
*
* Assumptions:
* - DMA handle allocated by stm32_dmachannel()
*
****************************************************************************/
size_t stm32_dmaresidual(DMA_HANDLE handle)
{
struct stm32_dma_s *dmast = (struct stm32_dma_s *)handle;
uint32_t residual;
/* Fetch the count of bytes remaining to be transferred.
*
* If the FIFO is enabled, this count may be inaccurate. ST don't
* appear to document whether this counts the peripheral or the memory
* side of the channel, and they don't make the memory pointer
* available either.
*
* For reception in circular mode the FIFO is disabled in order that
* this value can be useful.
*/
residual = dmast_getreg(dmast, STM32_DMA_SNDTR_OFFSET);
return (size_t)residual;
}
/**************************************************************************** /****************************************************************************
* Name: stm32_dmasample * Name: stm32_dmasample
* *
@@ -617,8 +859,8 @@ void stm32_dmasample(DMA_HANDLE handle, struct stm32_dmaregs_s *regs)
flags = irqsave(); flags = irqsave();
regs->lisr = dmabase_getreg(dmast, STM32_DMA_LISR_OFFSET); regs->lisr = dmabase_getreg(dmast, STM32_DMA_LISR_OFFSET);
regs->hisr = dmabase_getreg(dmast, STM32_DMA_LISR_OFFSET); regs->hisr = dmabase_getreg(dmast, STM32_DMA_HISR_OFFSET);
regs->scr = dmast_getreg(dmast, STM32_DMA_HISR_OFFSET); regs->scr = dmast_getreg(dmast, STM32_DMA_SCR_OFFSET);
regs->sndtr = dmast_getreg(dmast, STM32_DMA_SNDTR_OFFSET); regs->sndtr = dmast_getreg(dmast, STM32_DMA_SNDTR_OFFSET);
regs->spar = dmast_getreg(dmast, STM32_DMA_SPAR_OFFSET); regs->spar = dmast_getreg(dmast, STM32_DMA_SPAR_OFFSET);
regs->sm0ar = dmast_getreg(dmast, STM32_DMA_SM0AR_OFFSET); regs->sm0ar = dmast_getreg(dmast, STM32_DMA_SM0AR_OFFSET);
@@ -654,7 +896,7 @@ void stm32_dmadump(DMA_HANDLE handle, const struct stm32_dmaregs_s *regs,
dmadbg(" SPAR[%08x]: %08x\n", dmast->base + STM32_DMA_SPAR_OFFSET, regs->spar); dmadbg(" SPAR[%08x]: %08x\n", dmast->base + STM32_DMA_SPAR_OFFSET, regs->spar);
dmadbg(" SM0AR[%08x]: %08x\n", dmast->base + STM32_DMA_SM0AR_OFFSET, regs->sm0ar); dmadbg(" SM0AR[%08x]: %08x\n", dmast->base + STM32_DMA_SM0AR_OFFSET, regs->sm0ar);
dmadbg(" SM1AR[%08x]: %08x\n", dmast->base + STM32_DMA_SM1AR_OFFSET, regs->sm1ar); dmadbg(" SM1AR[%08x]: %08x\n", dmast->base + STM32_DMA_SM1AR_OFFSET, regs->sm1ar);
dmadbg(" SFCRF[%08x]: %08x\n", dmast->base + STM32_DMA_SFCR_OFFSET, regs->sfcr); dmadbg(" SFCR[%08x]: %08x\n", dmast->base + STM32_DMA_SFCR_OFFSET, regs->sfcr);
} }
#endif #endif
arch/arm/src/stm32/stm32f20xxx_rcc.c
+50 -46
View File
@@ -2,7 +2,7 @@
* arch/arm/src/stm32/stm32f20xxx_rcc.c * arch/arm/src/stm32/stm32f20xxx_rcc.c
* *
* Copyright (C) 2012 Gregory Nutt. All rights reserved. * Copyright (C) 2012 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr> * Author: Gregory Nutt <gnutt@nuttx.org>
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions * modification, are permitted provided that the following conditions
@@ -39,6 +39,10 @@
#include "stm32_pwr.h" #include "stm32_pwr.h"
/* This file supports only the STM32 F2 family (although it is identical to
* the corresponding F4 file).
*/
/**************************************************************************** /****************************************************************************
* Definitions * Definitions
****************************************************************************/ ****************************************************************************/
@@ -151,31 +155,31 @@ static inline void rcc_enableahb1(void)
); );
#endif #endif
#if CONFIG_STM32_CRC #ifdef CONFIG_STM32_CRC
/* CRC clock enable */ /* CRC clock enable */
regval |= RCC_AHB1ENR_CRCEN; regval |= RCC_AHB1ENR_CRCEN;
#endif #endif
#if CONFIG_STM32_BKPSRAM #ifdef CONFIG_STM32_BKPSRAM
/* Backup SRAM clock enable */ /* Backup SRAM clock enable */
regval |= RCC_AHB1ENR_BKPSRAMEN; regval |= RCC_AHB1ENR_BKPSRAMEN;
#endif #endif
#if CONFIG_STM32_CCMDATARAM #ifdef CONFIG_STM32_CCMDATARAM
/* CCM data RAM clock enable */ /* CCM data RAM clock enable */
regval |= RCC_AHB1ENR_CCMDATARAMEN; regval |= RCC_AHB1ENR_CCMDATARAMEN;
#endif #endif
#if CONFIG_STM32_DMA1 #ifdef CONFIG_STM32_DMA1
/* DMA 1 clock enable */ /* DMA 1 clock enable */
regval |= RCC_AHB1ENR_DMA1EN; regval |= RCC_AHB1ENR_DMA1EN;
#endif #endif
#if CONFIG_STM32_DMA2 #ifdef CONFIG_STM32_DMA2
/* DMA 2 clock enable */ /* DMA 2 clock enable */
regval |= RCC_AHB1ENR_DMA2EN; regval |= RCC_AHB1ENR_DMA2EN;
@@ -221,31 +225,31 @@ static inline void rcc_enableahb2(void)
regval = getreg32(STM32_RCC_AHB2ENR); regval = getreg32(STM32_RCC_AHB2ENR);
#if CONFIG_STM32_DCMI #ifdef CONFIG_STM32_DCMI
/* Camera interface enable */ /* Camera interface enable */
regval |= RCC_AHB2ENR_DCMIEN; regval |= RCC_AHB2ENR_DCMIEN;
#endif #endif
#if CONFIG_STM32_CRYP #ifdef CONFIG_STM32_CRYP
/* Cryptographic modules clock enable */ /* Cryptographic modules clock enable */
regval |= RCC_AHB2ENR_CRYPEN; regval |= RCC_AHB2ENR_CRYPEN;
#endif #endif
#if CONFIG_STM32_HASH #ifdef CONFIG_STM32_HASH
/* Hash modules clock enable */ /* Hash modules clock enable */
regval |= RCC_AHB2ENR_HASHEN; regval |= RCC_AHB2ENR_HASHEN;
#endif #endif
#if CONFIG_STM32_RNG #ifdef CONFIG_STM32_RNG
/* Random number generator clock enable */ /* Random number generator clock enable */
regval |= RCC_AHB2ENR_RNGEN; regval |= RCC_AHB2ENR_RNGEN;
#endif #endif
#if CONFIG_STM32_OTGFS #ifdef CONFIG_STM32_OTGFS
/* USB OTG FS clock enable */ /* USB OTG FS clock enable */
regval |= RCC_AHB2ENR_OTGFSEN; regval |= RCC_AHB2ENR_OTGFSEN;
@@ -264,7 +268,7 @@ static inline void rcc_enableahb2(void)
static inline void rcc_enableahb3(void) static inline void rcc_enableahb3(void)
{ {
#if CONFIG_STM32_FSMC #ifdef CONFIG_STM32_FSMC
uint32_t regval; uint32_t regval;
/* Set the appropriate bits in the AHB3ENR register to enabled the /* Set the appropriate bits in the AHB3ENR register to enabled the
@@ -299,127 +303,127 @@ static inline void rcc_enableapb1(void)
regval = getreg32(STM32_RCC_APB1ENR); regval = getreg32(STM32_RCC_APB1ENR);
#if CONFIG_STM32_TIM2 #ifdef CONFIG_STM32_TIM2
/* TIM2 clock enable */ /* TIM2 clock enable */
regval |= RCC_APB1ENR_TIM2EN; regval |= RCC_APB1ENR_TIM2EN;
#endif #endif
#if CONFIG_STM32_TIM3 #ifdef CONFIG_STM32_TIM3
/* TIM3 clock enable */ /* TIM3 clock enable */
regval |= RCC_APB1ENR_TIM3EN; regval |= RCC_APB1ENR_TIM3EN;
#endif #endif
#if CONFIG_STM32_TIM4 #ifdef CONFIG_STM32_TIM4
/* TIM4 clock enable */ /* TIM4 clock enable */
regval |= RCC_APB1ENR_TIM4EN; regval |= RCC_APB1ENR_TIM4EN;
#endif #endif
#if CONFIG_STM32_TIM5 #ifdef CONFIG_STM32_TIM5
/* TIM5 clock enable */ /* TIM5 clock enable */
regval |= RCC_APB1ENR_TIM5EN; regval |= RCC_APB1ENR_TIM5EN;
#endif #endif
#if CONFIG_STM32_TIM6 #ifdef CONFIG_STM32_TIM6
/* TIM6 clock enable */ /* TIM6 clock enable */
regval |= RCC_APB1ENR_TIM6EN; regval |= RCC_APB1ENR_TIM6EN;
#endif #endif
#if CONFIG_STM32_TIM7 #ifdef CONFIG_STM32_TIM7
/* TIM7 clock enable */ /* TIM7 clock enable */
regval |= RCC_APB1ENR_TIM7EN; regval |= RCC_APB1ENR_TIM7EN;
#endif #endif
#if CONFIG_STM32_TIM12 #ifdef CONFIG_STM32_TIM12
/* TIM12 clock enable */ /* TIM12 clock enable */
regval |= RCC_APB1ENR_TIM12EN; regval |= RCC_APB1ENR_TIM12EN;
#endif #endif
#if CONFIG_STM32_TIM13 #ifdef CONFIG_STM32_TIM13
/* TIM13 clock enable */ /* TIM13 clock enable */
regval |= RCC_APB1ENR_TIM13EN; regval |= RCC_APB1ENR_TIM13EN;
#endif #endif
#if CONFIG_STM32_TIM14 #ifdef CONFIG_STM32_TIM14
/* TIM14 clock enable */ /* TIM14 clock enable */
regval |= RCC_APB1ENR_TIM14EN; regval |= RCC_APB1ENR_TIM14EN;
#endif #endif
#if CONFIG_STM32_WWDG #ifdef CONFIG_STM32_WWDG
/* Window watchdog clock enable */ /* Window watchdog clock enable */
regval |= RCC_APB1ENR_WWDGEN; regval |= RCC_APB1ENR_WWDGEN;
#endif #endif
#if CONFIG_STM32_SPI2 #ifdef CONFIG_STM32_SPI2
/* SPI2 clock enable */ /* SPI2 clock enable */
regval |= RCC_APB1ENR_SPI2EN; regval |= RCC_APB1ENR_SPI2EN;
#endif #endif
#if CONFIG_STM32_SPI3 #ifdef CONFIG_STM32_SPI3
/* SPI3 clock enable */ /* SPI3 clock enable */
regval |= RCC_APB1ENR_SPI3EN; regval |= RCC_APB1ENR_SPI3EN;
#endif #endif
#if CONFIG_STM32_USART2 #ifdef CONFIG_STM32_USART2
/* USART 2 clock enable */ /* USART 2 clock enable */
regval |= RCC_APB1ENR_USART2EN; regval |= RCC_APB1ENR_USART2EN;
#endif #endif
#if CONFIG_STM32_USART3 #ifdef CONFIG_STM32_USART3
/* USART3 clock enable */ /* USART3 clock enable */
regval |= RCC_APB1ENR_USART3EN; regval |= RCC_APB1ENR_USART3EN;
#endif #endif
#if CONFIG_STM32_UART4 #ifdef CONFIG_STM32_UART4
/* UART4 clock enable */ /* UART4 clock enable */
regval |= RCC_APB1ENR_UART4EN; regval |= RCC_APB1ENR_UART4EN;
#endif #endif
#if CONFIG_STM32_UART5 #ifdef CONFIG_STM32_UART5
/* UART5 clock enable */ /* UART5 clock enable */
regval |= RCC_APB1ENR_UART5EN; regval |= RCC_APB1ENR_UART5EN;
#endif #endif
#if CONFIG_STM32_I2C1 #ifdef CONFIG_STM32_I2C1
/* I2C1 clock enable */ /* I2C1 clock enable */
regval |= RCC_APB1ENR_I2C1EN; regval |= RCC_APB1ENR_I2C1EN;
#endif #endif
#if CONFIG_STM32_I2C2 #ifdef CONFIG_STM32_I2C2
/* I2C2 clock enable */ /* I2C2 clock enable */
regval |= RCC_APB1ENR_I2C2EN; regval |= RCC_APB1ENR_I2C2EN;
#endif #endif
#if CONFIG_STM32_I2C3 #ifdef CONFIG_STM32_I2C3
/* I2C3 clock enable */ /* I2C3 clock enable */
regval |= RCC_APB1ENR_I2C3EN; regval |= RCC_APB1ENR_I2C3EN;
#endif #endif
#if CONFIG_STM32_CAN1 #ifdef CONFIG_STM32_CAN1
/* CAN 1 clock enable */ /* CAN 1 clock enable */
regval |= RCC_APB1ENR_CAN1EN; regval |= RCC_APB1ENR_CAN1EN;
#endif #endif
#if CONFIG_STM32_CAN2 #ifdef CONFIG_STM32_CAN2
/* CAN2 clock enable. NOTE: CAN2 needs CAN1 clock as well. */ /* CAN2 clock enable. NOTE: CAN2 needs CAN1 clock as well. */
regval |= (RCC_APB1ENR_CAN1EN | RCC_APB1ENR_CAN2EN); regval |= (RCC_APB1ENR_CAN1EN | RCC_APB1ENR_CAN2EN);
@@ -458,79 +462,79 @@ static inline void rcc_enableapb2(void)
regval = getreg32(STM32_RCC_APB2ENR); regval = getreg32(STM32_RCC_APB2ENR);
#if CONFIG_STM32_TIM1 #ifdef CONFIG_STM32_TIM1
/* TIM1 clock enable */ /* TIM1 clock enable */
regval |= RCC_APB2ENR_TIM1EN; regval |= RCC_APB2ENR_TIM1EN;
#endif #endif
#if CONFIG_STM32_TIM8 #ifdef CONFIG_STM32_TIM8
/* TIM8 clock enable */ /* TIM8 clock enable */
regval |= RCC_APB2ENR_TIM8EN; regval |= RCC_APB2ENR_TIM8EN;
#endif #endif
#if CONFIG_STM32_USART1 #ifdef CONFIG_STM32_USART1
/* USART1 clock enable */ /* USART1 clock enable */
regval |= RCC_APB2ENR_USART1EN; regval |= RCC_APB2ENR_USART1EN;
#endif #endif
#if CONFIG_STM32_USART6 #ifdef CONFIG_STM32_USART6
/* USART6 clock enable */ /* USART6 clock enable */
regval |= RCC_APB2ENR_USART6EN; regval |= RCC_APB2ENR_USART6EN;
#endif #endif
#if CONFIG_STM32_ADC1 #ifdef CONFIG_STM32_ADC1
/* ADC1 clock enable */ /* ADC1 clock enable */
regval |= RCC_APB2ENR_ADC1EN; regval |= RCC_APB2ENR_ADC1EN;
#endif #endif
#if CONFIG_STM32_ADC2 #ifdef CONFIG_STM32_ADC2
/* ADC2 clock enable */ /* ADC2 clock enable */
regval |= RCC_APB2ENR_ADC2EN; regval |= RCC_APB2ENR_ADC2EN;
#endif #endif
#if CONFIG_STM32_ADC3 #ifdef CONFIG_STM32_ADC3
/* ADC3 clock enable */ /* ADC3 clock enable */
regval |= RCC_APB2ENR_ADC3EN; regval |= RCC_APB2ENR_ADC3EN;
#endif #endif
#if CONFIG_STM32_SDIO #ifdef CONFIG_STM32_SDIO
/* SDIO clock enable */ /* SDIO clock enable */
regval |= RCC_APB2ENR_SDIOEN; regval |= RCC_APB2ENR_SDIOEN;
#endif #endif
#if CONFIG_STM32_SPI1 #ifdef CONFIG_STM32_SPI1
/* SPI1 clock enable */ /* SPI1 clock enable */
regval |= RCC_APB2ENR_SPI1EN; regval |= RCC_APB2ENR_SPI1EN;
#endif #endif
#if CONFIG_STM32_SYSCFG #ifdef CONFIG_STM32_SYSCFG
/* System configuration controller clock enable */ /* System configuration controller clock enable */
regval |= RCC_APB2ENR_SYSCFGEN; regval |= RCC_APB2ENR_SYSCFGEN;
#endif #endif
#if CONFIG_STM32_TIM9 #ifdef CONFIG_STM32_TIM9
/* TIM9 clock enable */ /* TIM9 clock enable */
regval |= RCC_APB2ENR_TIM9EN; regval |= RCC_APB2ENR_TIM9EN;
#endif #endif
#if CONFIG_STM32_TIM10 #ifdef CONFIG_STM32_TIM10
/* TIM10 clock enable */ /* TIM10 clock enable */
regval |= RCC_APB2ENR_TIM10EN; regval |= RCC_APB2ENR_TIM10EN;
#endif #endif
#if CONFIG_STM32_TIM11 #ifdef CONFIG_STM32_TIM11
/* TIM11 clock enable */ /* TIM11 clock enable */
regval |= RCC_APB2ENR_TIM11EN; regval |= RCC_APB2ENR_TIM11EN;
arch/arm/src/stm32/stm32f20xxx_rtc.c
+1 -1
View File
@@ -1,7 +1,7 @@
/************************************************************************************ /************************************************************************************
* arch/arm/src/stm32/stm32f20xxx_rtc.c * arch/arm/src/stm32/stm32f20xxx_rtc.c
* *
* Copyright (C) 2011 Gregory Nutt. All rights reserved. * Copyright (C) 2012 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org> * Author: Gregory Nutt <gnutt@nuttx.org>
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
arch/arm/src/stm32/stm32f40xxx_dma.c
+1 -1
View File
@@ -900,4 +900,4 @@ void stm32_dmadump(DMA_HANDLE handle, const struct stm32_dmaregs_s *regs,
} }
#endif #endif
#endif /* CONFIG_STM32_STM32F10XX */ #endif /* CONFIG_STM32_STM32F40XX */
configs/stm32f4discovery/README.txt
+1
View File
@@ -1011,6 +1011,7 @@ Where <subdir> is one of the following:
the USB console would be to change the .config file like this: the USB console would be to change the .config file like this:
CONFIG_STM32_OTGFS=y : STM32 OTG FS support CONFIG_STM32_OTGFS=y : STM32 OTG FS support
CONFIG_DEV_CONSOLE=n : Inhibit use of /dev/console by other logic
CONFIG_USBDEV=y : USB device support must be enabled CONFIG_USBDEV=y : USB device support must be enabled
CONFIG_CDCACM=y : The CDC/ACM driver must be built CONFIG_CDCACM=y : The CDC/ACM driver must be built
CONFIG_CDCACM_CONSOLE=y : Enable the CDC/ACM USB console. CONFIG_CDCACM_CONSOLE=y : Enable the CDC/ACM USB console.