diff --git a/arch/arm/src/imxrt/chip/imxrt_iomuxc.h b/arch/arm/src/imxrt/chip/imxrt_iomuxc.h index 718073b18c8..a5b2b14a47b 100644 --- a/arch/arm/src/imxrt/chip/imxrt_iomuxc.h +++ b/arch/arm/src/imxrt/chip/imxrt_iomuxc.h @@ -76,7 +76,7 @@ #define IMXRT_IOMUXC_GPR_GPR24_OFFSET 0x0060 /* GPR24 General Purpose Register*/ #define IMXRT_IOMUXC_GPR_GPR25_OFFSET 0x0064 /* GPR25 General Purpose Register*/ -#define IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEU_OFFSET 0x0000 /* SW_MUX_CTL_PAD_WAKEUP SW MUX Control Register */ +#define IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_OFFSET 0x0000 /* SW_MUX_CTL_PAD_WAKEUP SW MUX Control Register */ #define IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_OFFSET 0x0004 /* SW_MUX_CTL_PAD_PMIC_ON_REQ SW MUX Control Register */ #define IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_OFFSET 0x0008 /* SW_MUX_CTL_PAD_PMIC_STBY_REQ SW MUX Control Register */ #define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_OFFSET 0x000c /* SW_PAD_CTL_PAD_TEST_MODE SW PAD Control Register */ @@ -219,11 +219,17 @@ #define IMXRT_PADMUX_GPIO_SD_B1_10_INDEX 122 #define IMXRT_PADMUX_GPIO_SD_B1_11_INDEX 123 -#define IMXRT_PADMUX_NREGISTERS 124 +#define IMXRT_PADMUX_WAKEUP_INDEX 124 +#define IMXRT_PADMUX_PMIC_ON_REQ_INDEX 125 +#define IMXRT_PADMUX_PMIC_STBY_REQ_INDEX 126 + +#define IMXRT_PADMUX_NREGISTERS 127 /* Pad Mux Register Offsets */ #define IMXRT_PADMUX_OFFSET(n) (0x0014 + ((unsigned int)(n) << 2)) +#define IMXRT_PADMUX_OFFSET_SNVS(n) ((unsigned int)(n) << 2) + #define IMXRT_PADMUX_GPIO_EMC_00_OFFSET 0x0014 #define IMXRT_PADMUX_GPIO_EMC_01_OFFSET 0x0018 @@ -479,11 +485,16 @@ #define IMXRT_PADCTL_GPIO_SD_B1_10_INDEX 122 #define IMXRT_PADCTL_GPIO_SD_B1_11_INDEX 123 -#define IMXRT_PADCTL_NREGISTERS 124 +#define IMXRT_PADCTL_WAKEUP_INDEX 124 +#define IMXRT_PADCTL_PMIC_ON_REQ_INDEX 125 +#define IMXRT_PADCTL_PMIC_STBY_REQ_INDEX 126 + +#define IMXRT_PADCTL_NREGISTERS 127 /* Pad Mux Register Offsets */ #define IMXRT_PADCTL_OFFSET(n) (0x0204 + ((unsigned int)(n) << 2)) +#define IMXRT_PADCTL_OFFSET_SNVS(n) (0x18 + ((unsigned int)(n) << 2)) #define IMXRT_PADCTL_GPIO_EMC_00_OFFSET 0x0204 #define IMXRT_PADCTL_GPIO_EMC_01_OFFSET 0x0208 @@ -796,7 +807,7 @@ #define IMXRT_IOMUXC_GPR_GPR24 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR24_OFFSET) #define IMXRT_IOMUXC_GPR_GPR25 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR25_OFFSET) -#define IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEU (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEU_OFFSET) +#define IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_OFFSET) #define IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_OFFSET) #define IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_OFFSET) #define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_OFFSET) @@ -814,6 +825,7 @@ /* Pad Mux Registers */ #define IMXRT_PADMUX_ADDRESS(n) (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_OFFSET(n)) +#define IMXRT_PADMUX_ADDRESS_SNVS(n) (IMXRT_IOMUXCSNVS_BASE + IMXRT_PADMUX_OFFSET_SNVS(n)) #define IMXRT_PADMUX_GPIO_EMC_00 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_00_OFFSET) #define IMXRT_PADMUX_GPIO_EMC_01 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_01_OFFSET) @@ -943,6 +955,7 @@ /* Pad Control Registers */ #define IMXRT_PADCTL_ADDRESS(n) (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_OFFSET(n)) +#define IMXRT_PADCTL_ADDRESS_SNVS(n) (IMXRT_IOMUXCSNVS_BASE + IMXRT_PADCTL_OFFSET_SNVS(n)) #define IMXRT_PADCTL_GPIO_EMC_00 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_00_OFFSET) #define IMXRT_PADCTL_GPIO_EMC_01 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_01_OFFSET) diff --git a/arch/arm/src/imxrt/imxrt_gpio.c b/arch/arm/src/imxrt/imxrt_gpio.c index e0213a115a8..684e650a000 100644 --- a/arch/arm/src/imxrt/imxrt_gpio.c +++ b/arch/arm/src/imxrt/imxrt_gpio.c @@ -217,13 +217,52 @@ static const uint8_t g_gpio4_padmux[IMXRT_GPIO_NPINS] = IMXRT_PADMUX_GPIO_EMC_31_INDEX /* GPIO4 Pin 31 */ }; +static const uint8_t g_gpio5_padmux[IMXRT_GPIO_NPINS] = +{ + IMXRT_PADMUX_WAKEUP_INDEX, /* GPIO5 Pin 0 */ + IMXRT_PADMUX_PMIC_ON_REQ_INDEX, /* GPIO5 Pin 1 */ + IMXRT_PADMUX_PMIC_STBY_REQ_INDEX, /* GPIO5 Pin 2 */ + IMXRT_PADMUX_INVALID, /* GPIO5 Pin 3 */ + IMXRT_PADMUX_INVALID, /* GPIO5 Pin 4 */ + IMXRT_PADMUX_INVALID, /* GPIO5 Pin 5 */ + IMXRT_PADMUX_INVALID, /* GPIO5 Pin 6 */ + IMXRT_PADMUX_INVALID, /* GPIO5 Pin 7 */ + + IMXRT_PADMUX_INVALID, /* GPIO5 Pin 8 */ + IMXRT_PADMUX_INVALID, /* GPIO5 Pin 9 */ + IMXRT_PADMUX_INVALID, /* GPIO5 Pin 10 */ + IMXRT_PADMUX_INVALID, /* GPIO5 Pin 11 */ + IMXRT_PADMUX_INVALID, /* GPIO5 Pin 12 */ + IMXRT_PADMUX_INVALID, /* GPIO5 Pin 13 */ + IMXRT_PADMUX_INVALID, /* GPIO5 Pin 14 */ + IMXRT_PADMUX_INVALID, /* GPIO5 Pin 15 */ + + IMXRT_PADMUX_INVALID, /* GPIO5 Pin 16 */ + IMXRT_PADMUX_INVALID, /* GPIO5 Pin 17 */ + IMXRT_PADMUX_INVALID, /* GPIO5 Pin 18 */ + IMXRT_PADMUX_INVALID, /* GPIO5 Pin 19 */ + IMXRT_PADMUX_INVALID, /* GPIO5 Pin 20 */ + IMXRT_PADMUX_INVALID, /* GPIO5 Pin 21 */ + IMXRT_PADMUX_INVALID, /* GPIO5 Pin 22 */ + IMXRT_PADMUX_INVALID, /* GPIO5 Pin 23 */ + + IMXRT_PADMUX_INVALID, /* GPIO5 Pin 24 */ + IMXRT_PADMUX_INVALID, /* GPIO5 Pin 25 */ + IMXRT_PADMUX_INVALID, /* GPIO5 Pin 26 */ + IMXRT_PADMUX_INVALID, /* GPIO5 Pin 27 */ + IMXRT_PADMUX_INVALID, /* GPIO5 Pin 28 */ + IMXRT_PADMUX_INVALID, /* GPIO5 Pin 29 */ + IMXRT_PADMUX_INVALID, /* GPIO5 Pin 30 */ + IMXRT_PADMUX_INVALID /* GPIO5 Pin 31 */ +}; + static FAR const uint8_t *g_gpio_padmux[IMXRT_GPIO_NPORTS + 1] = { g_gpio1_padmux, /* GPIO1 */ g_gpio2_padmux, /* GPIO2 */ g_gpio3_padmux, /* GPIO3 */ g_gpio4_padmux, /* GPIO4 */ - NULL, /* GPIO5 REVISIT */ + g_gpio5_padmux, /* GPIO5 */ NULL /* End of list */ }; @@ -254,6 +293,34 @@ uintptr_t g_gpio_base[IMXRT_GPIO_NPORTS] = * Private Functions ****************************************************************************/ +/**************************************************************************** + * Name: imxrt_padmux_address + ****************************************************************************/ + +static uintptr_t imxrt_padmux_address(unsigned int index) +{ + if (index >= IMXRT_PADMUX_WAKEUP_INDEX) + { + return (IMXRT_PADMUX_ADDRESS_SNVS(index - IMXRT_PADMUX_WAKEUP_INDEX)); + } + + return (IMXRT_PADMUX_ADDRESS(index)); +} + +/**************************************************************************** + * Name: imxrt_padctl_address + ****************************************************************************/ + +static uintptr_t imxrt_padctl_address(unsigned int index) +{ + if (index >= IMXRT_PADCTL_WAKEUP_INDEX) + { + return (IMXRT_PADCTL_ADDRESS_SNVS(index - IMXRT_PADCTL_WAKEUP_INDEX)); + } + + return (IMXRT_PADCTL_ADDRESS(index)); +} + /**************************************************************************** * Name: imxrt_gpio_dirout ****************************************************************************/ @@ -344,7 +411,7 @@ static int imxrt_gpio_configinput(gpio_pinset_t pinset) return -EINVAL; } - regaddr = IMXRT_PADMUX_ADDRESS(index); + regaddr = imxrt_padmux_address(index); putreg32(PADMUX_MUXMODE_ALT5, regaddr); /* Configure pin pad settings */ @@ -355,7 +422,7 @@ static int imxrt_gpio_configinput(gpio_pinset_t pinset) return -EINVAL; } - regaddr = IMXRT_PADCTL_ADDRESS(index); + regaddr = imxrt_padctl_address(index); ioset = (iomux_pinset_t)((pinset & GPIO_IOMUX_MASK) >> GPIO_IOMUX_SHIFT); return imxrt_iomux_configure(regaddr, ioset); } @@ -397,7 +464,7 @@ static inline int imxrt_gpio_configperiph(gpio_pinset_t pinset) /* Configure pin as a peripheral */ index = ((pinset & GPIO_PADMUX_MASK) >> GPIO_PADMUX_SHIFT); - regaddr = IMXRT_PADMUX_ADDRESS(index); + regaddr = imxrt_padmux_address(index); value = ((pinset & GPIO_ALT_MASK) >> GPIO_ALT_SHIFT); regval = (value << PADMUX_MUXMODE_SHIFT); @@ -412,7 +479,7 @@ static inline int imxrt_gpio_configperiph(gpio_pinset_t pinset) return -EINVAL; } - regaddr = IMXRT_PADCTL_ADDRESS(index); + regaddr = imxrt_padctl_address(index); ioset = (iomux_pinset_t)((pinset & GPIO_IOMUX_MASK) >> GPIO_IOMUX_SHIFT); return imxrt_iomux_configure(regaddr, ioset); } diff --git a/arch/arm/src/imxrt/imxrt_iomuxc.c b/arch/arm/src/imxrt/imxrt_iomuxc.c index 2b4ec4cdf8e..e4c9998f338 100644 --- a/arch/arm/src/imxrt/imxrt_iomuxc.c +++ b/arch/arm/src/imxrt/imxrt_iomuxc.c @@ -192,7 +192,10 @@ static const uint8_t g_mux2ctl_map[IMXRT_PADMUX_NREGISTERS] = IMXRT_PADCTL_GPIO_SD_B1_08_INDEX, IMXRT_PADCTL_GPIO_SD_B1_09_INDEX, IMXRT_PADCTL_GPIO_SD_B1_10_INDEX, - IMXRT_PADCTL_GPIO_SD_B1_11_INDEX + IMXRT_PADCTL_GPIO_SD_B1_11_INDEX, + IMXRT_PADCTL_WAKEUP_INDEX, + IMXRT_PADCTL_PMIC_ON_REQ_INDEX, + IMXRT_PADCTL_PMIC_STBY_REQ_INDEX }; /****************************************************************************