diff --git a/arch/arm/src/stm32/chip/stm32f33xxx_hrtim.h b/arch/arm/src/stm32/chip/stm32f33xxx_hrtim.h index 65e84afab49..0bc6b93c5ef 100644 --- a/arch/arm/src/stm32/chip/stm32f33xxx_hrtim.h +++ b/arch/arm/src/stm32/chip/stm32f33xxx_hrtim.h @@ -1136,11 +1136,12 @@ /* Timer X Fault Register */ -#define HRTIM_TIMFLT_FLT1EN (1 << 0) /* Bit 0 */ -#define HRTIM_TIMFLT_FLT2EN (1 << 1) /* Bit 1 */ -#define HRTIM_TIMFLT_FLT3EN (1 << 2) /* Bit 2 */ -#define HRTIM_TIMFLT_FLT4EN (1 << 3) /* Bit 3 */ -#define HRTIM_TIMFLT_FLT5EN (1 << 4) /* Bit 4 */ +#define HRTIM_TIMFLT_FLT1EN (1 << 0) /* Bit 0: Fault1 enable */ +#define HRTIM_TIMFLT_FLT2EN (1 << 1) /* Bit 1: Fault 2 enable */ +#define HRTIM_TIMFLT_FLT3EN (1 << 2) /* Bit 2: Fault 3 enable*/ +#define HRTIM_TIMFLT_FLT4EN (1 << 3) /* Bit 3: Fault 4 enable */ +#define HRTIM_TIMFLT_FLT5EN (1 << 4) /* Bit 4: Fault 5 enable */ +#define HRTIM_TIMFLT_FLTLCK (1 << 31) /* Bit 31: Fault sources lock*/ /* Common Control Register 1 */ diff --git a/arch/arm/src/stm32/stm32_hrtim.c b/arch/arm/src/stm32/stm32_hrtim.c index d9f48d31ca1..cebfd9870fd 100644 --- a/arch/arm/src/stm32/stm32_hrtim.c +++ b/arch/arm/src/stm32/stm32_hrtim.c @@ -57,6 +57,8 @@ #if defined(CONFIG_STM32_STM32F33XX) +#warning "HRTIM UNDER DEVELOPMENT !" + #ifdef CONFIG_STM32_HRTIM_ADC # error HRTIM ADC Triggering not supported yet #endif @@ -65,14 +67,6 @@ # error HRTIM DAC Triggering not supported yet #endif -#ifdef CONFIG_STM32_HRTIM_FAULT -# error HRTIM Faults not supported yet -#endif - -#ifdef CONFIG_STM32_HRTIM_EEV -# error HRTIM External Events not supported yet -#endif - #ifdef CONFIG_STM32_HRTIM_BURST # error HRTIM Burst mode not supported yet #endif @@ -95,6 +89,42 @@ # define HRTIM_MASTER_PRESCALER HRTIM_PRESCALER_2 #endif +#ifndef HRTIM_TIMA_UPDATE +# define HRTIM_TIMA_UPDATE 0 +#endif +#ifndef HRTIM_TIMB_UPDATE +# define HRTIM_TIMB_UPDATE 0 +#endif +#ifndef HRTIM_TIMC_UPDATE +# define HRTIM_TIMC_UPDATE 0 +#endif +#ifndef HRTIM_TIMD_UPDATE +# define HRTIM_TIMD_UPDATE 0 +#endif +#ifndef HRTIM_TIME_UPDATE +# define HRTIM_TIME_UPDATE 0 +#endif + +#ifndef HRTIM_TIMA_RESET +# define HRTIM_TIMA_RESET 0 +#endif +#ifndef HRTIM_TIMB_RESET +# define HRTIM_TIMB_RESET 0 +#endif +#ifndef HRTIM_TIMC_RESET +# define HRTIM_TIMC_RESET 0 +#endif +#ifndef HRTIM_TIMD_RESET +# define HRTIM_TIMD_RESET 0 +#endif +#ifndef HRTIM_TIME_RESET +# define HRTIM_TIME_RESET 0 +#endif + +#ifndef HRTIM_IRQ_COMMON +# define HRTIM_IRQ_COMMON 0 +#endif + /* HRTIM clock source configuration */ #ifdef CONFIG_STM32_HRTIM_CLK_FROM_PLL @@ -166,6 +196,13 @@ # define HRTIM_HAVE_EEV 1 #endif +#if defined(CONFIG_STM32_HRTIM_MASTER_IRQ) || defined(CONFIG_STM32_HRTIM_TIMA_IRQ) || \ + defined(CONFIG_STM32_HRTIM_TIMB_IRQ) || defined(CONFIG_STM32_HRTIM_TIMC_IRQ) || \ + defined(CONFIG_STM32_HRTIM_TIMD_IRQ) || defined(CONFIG_STM32_HRTIM_TIME_IRQ) || \ + defined(CONFIG_STM32_HRTIM_CMN_IRQ) +# defined HRTIM_HAVE_INTERRUPTS +#endif + /**************************************************************************** * Private Types ****************************************************************************/ @@ -234,7 +271,11 @@ struct stm32_hrtim_timcmn_s { uint32_t base; /* The base adress of the timer */ uint32_t pclk; /* The frequency of the peripheral clock - * that drives the timer module */ + * that drives the timer module + */ +#ifdef HRTIM_HAVE_INTERRUPTS + uint16_t irq; /* interrupts configuration */ +#endif #ifdef CONFIG_STM32_HRTIM_DMA uint32_t dmaburst; #endif @@ -259,7 +300,13 @@ struct stm32_hrtim_master_priv_s struct stm32_hrtim_slave_priv_s { - uint16_t update; /* Update configuration */ +#ifdef HRTIM_HAVE_FAULTS + uint8_t flt; /* Faults configuration. + * First five bits are fault sources, + * last bit is lock configuration + */ +#endif + uint16_t update; /* Update configuration */ uint32_t reset; /* Timer reset events */ #ifdef HRTIM_HAVE_PWM struct stm32_hrtim_pwm_s pwm; /* PWM configuration */ @@ -275,10 +322,9 @@ struct stm32_hrtim_slave_priv_s struct stm32_hrtim_fault_cfg_s { - uint8_t pol:1; /* Fault poalrity */ + uint8_t pol:1; /* Fault polarity */ uint8_t src:1; /* Fault source */ uint8_t filter:4; /* Fault filter */ - uint8_t flts:1; /* Fault Sampling clock division */ uint8_t lock:1; /* Fault lock */ }; @@ -382,6 +428,9 @@ struct stm32_hrtim_s #ifdef HRTIM_HAVE_EEV struct stm32_hrtim_eev_s *eev; #endif +#ifdef CONFIG_STM32_HRTIM_CMN_IRQ + uint32_t irq; /* Common interrupts configuration */ +#endif }; /**************************************************************************** @@ -436,15 +485,21 @@ static int hrtim_synch_config(FAR struct stm32_hrtim_s *priv); #endif #if defined(HRTIM_HAVE_PWM) static int hrtim_outputs_config(FAR struct stm32_hrtim_s *priv); +static int hrtim_outputs_enable(FAR struct stm32_hrtim_s *priv, uint16_t outputs, + bool state); #endif #ifdef HRTIM_HAVE_ADC static int hrtim_adc_config(FAR struct stm32_hrtim_s *priv); #endif #ifdef HRTIM_HAVE_FAULTS static int hrtim_faults_config(FAR struct stm32_hrtim_s *priv); +static int hrtim_flt_cfg(FAR struct stm32_hrtim_s *priv, uint8_t index); +static int hrtim_tim_flts_cfg(FAR struct stm32_hrtim_s *priv, uint8_t timer); #endif #ifdef HRTIM_HAVE_EEV -static int hrtim_eev_config(FAR struct stm32_hrtim_s *priv); +static int hrtim_events_config(FAR struct stm32_hrtim_s *priv); +static int hrtim_eev_cfg(FAR struct stm32_hrtim_s *priv, uint8_t index); + #endif #ifdef HRTIM_HAVE_INTERRUPTS static int hrtim_irq_config(FAR struct stm32_hrtim_s *priv); @@ -456,6 +511,7 @@ static int hrtim_per_update(FAR struct stm32_hrtim_s *priv, uint8_t timer, static uint16_t hrtim_per_get(FAR struct stm32_hrtim_s *priv, uint8_t timer); static uint16_t hrtim_cmp_get(FAR struct stm32_hrtim_s *priv, uint8_t timer, uint8_t index); +static int hrtim_reset_set(FAR struct stm32_hrtim_s *priv, uint8_t timer, uint32_t reset); /* Initialization */ @@ -488,7 +544,10 @@ static struct stm32_hrtim_tim_s g_master = .tim = { .base = STM32_HRTIM1_MASTER_BASE, - .pclk = HRTIM_CLOCK/HRTIM_MASTER_PRESCALER + .pclk = HRTIM_CLOCK/HRTIM_MASTER_PRESCALER, +#ifdef CONFIG_STM32_HRTIM_MASTER_IRQ + .irq = HRTIM_IRQ_MASTER +#endif }, .priv = NULL, }; @@ -501,6 +560,8 @@ static struct stm32_hrtim_tim_s g_master = static struct stm32_hrtim_slave_priv_s g_tima_priv = { + .update = HRTIM_TIMA_UPDATE, + .reset = HRTIM_TIMA_RESET, #ifdef CONFIG_STM32_HRTIM_TIMA_PWM .pwm = { @@ -548,6 +609,9 @@ static struct stm32_hrtim_tim_s g_tima = { .base = STM32_HRTIM1_TIMERA_BASE, .pclk = HRTIM_CLOCK/HRTIM_TIMA_PRESCALER +#ifdef CONFIG_STM32_HRTIM_MASTER_IRQ + .irq = HRTIM_IRQ_TIMA, +#endif }, .priv = &g_tima_priv }; @@ -558,7 +622,51 @@ static struct stm32_hrtim_tim_s g_tima = #ifdef HRTIM_HAVE_FAULTS struct stm32_hrtim_faults_s g_flt = { -#warning "missing faults data" +#ifdef CONFIG_STM32_HRTIM_FAULT1 + .flt1 = + { + .pol = HRTIM_FAULT1_POL, + .src = HRTIM_FAULT1_SRC, + .filter = HRTIM_FAULT1_FILTER, + .lock = HRTIM_FAULT1_LOCK, + }, +#endif +#ifdef CONFIG_STM32_HRTIM_FAULT2 + .flt2 = + { + .pol = HRTIM_FAULT2_POL, + .src = HRTIM_FAULT2_SRC, + .filter = HRTIM_FAULT2_FILTER, + .lock = HRTIM_FAULT2_LOCK, + }, +#endif +#ifdef CONFIG_STM32_HRTIM_FAULT3 + .flt3 = + { + .pol = HRTIM_FAULT3_POL, + .src = HRTIM_FAULT3_SRC, + .filter = HRTIM_FAULT3_FILTER, + .lock = HRTIM_FAULT3_LOCK, + }, +#endif +#ifdef CONFIG_STM32_HRTIM_FAULT4 + .flt2 = + { + .pol = HRTIM_FAULT4_POL, + .src = HRTIM_FAULT4_SRC, + .filter = HRTIM_FAULT4_FILTER, + .lock = HRTIM_FAULT4_LOCK, + }, +#endif +#ifdef CONFIG_STM32_HRTIM_FAULT5 + .flt2 = + { + .pol = HRTIM_FAULT5_POL, + .src = HRTIM_FAULT5_SRC, + .filter = HRTIM_FAULT5_FILTER, + .lock = HRTIM_FAULT5_LOCK, + }, +#endif }; #endif @@ -567,7 +675,106 @@ struct stm32_hrtim_faults_s g_flt = #ifdef HRTIM_HAVE_EEV struct stm32_hrtim_eev_s g_eev = { -#warning "missing eev data" +#ifdef CONFIG_STM32_HRTIM_EEV1 + .eev1 = + { + .filter = HRTIM_EEV1_FILTER, + .src = HRTIM_EEV1_SRC, + .pol = HRTIM_EEV1_POL, + .sen = HRTIM_EEV1_SEN, + .mode = HRTIM_EEV1_MODE, + } +#endif +#ifdef CONFIG_STM32_HRTIM_EEV2 + .eev2 = + { + .filter = HRTIM_EEV2_FILTER, + .src = HRTIM_EEV2_SRC, + .pol = HRTIM_EEV2_POL, + .sen = HRTIM_EEV2_SEN, + .mode = HRTIM_EEV2_MODE, + } +#endif +#ifdef CONFIG_STM32_HRTIM_EEV3 + .eev3 = + { + .filter = HRTIM_EEV3_FILTER, + .src = HRTIM_EEV3_SRC, + .pol = HRTIM_EEV3_POL, + .sen = HRTIM_EEV3_SEN, + .mode = HRTIM_EEV3_MODE, + } +#endif +#ifdef CONFIG_STM32_HRTIM_EEV4 + .eev4 = + { + .filter = HRTIM_EEV4_FILTER, + .src = HRTIM_EEV4_SRC, + .pol = HRTIM_EEV4_POL, + .sen = HRTIM_EEV4_SEN, + .mode = HRTIM_EEV4_MODE, + } +#endif +#ifdef CONFIG_STM32_HRTIM_EEV5 + .eev5 = + { + .filter = HRTIM_EEV5_FILTER, + .src = HRTIM_EEV5_SRC, + .pol = HRTIM_EEV5_POL, + .sen = HRTIM_EEV5_SEN, + .mode = HRTIM_EEV5_MODE, + } +#endif +#ifdef CONFIG_STM32_HRTIM_EEV6 + .eev6 = + { + .filter = HRTIM_EEV6_FILTER, + .src = HRTIM_EEV6_SRC, + .pol = HRTIM_EEV6_POL, + .sen = HRTIM_EEV6_SEN, + .mode = HRTIM_EEV6_MODE, + } +#endif +#ifdef CONFIG_STM32_HRTIM_EEV7 + .eev7 = + { + .filter = HRTIM_EEV7_FILTER, + .src = HRTIM_EEV7_SRC, + .pol = HRTIM_EEV7_POL, + .sen = HRTIM_EEV7_SEN, + .mode = HRTIM_EEV7_MODE, + } +#endif +#ifdef CONFIG_STM32_HRTIM_EEV8 + .eev8 = + { + .filter = HRTIM_EEV8_FILTER, + .src = HRTIM_EEV8_SRC, + .pol = HRTIM_EEV8_POL, + .sen = HRTIM_EEV8_SEN, + .mode = HRTIM_EEV8_MODE, + } +#endif +#ifdef CONFIG_STM32_HRTIM_EEV9 + .eev9 = + { + .filter = HRTIM_EEV9_FILTER, + .src = HRTIM_EEV9_SRC, + .pol = HRTIM_EEV9_POL, + .sen = HRTIM_EEV9_SEN, + .mode = HRTIM_EEV9_MODE, + } +#endif +#ifdef CONFIG_STM32_HRTIM_EEV10 + .eev10 = + { + .filter = HRTIM_EEV10_FILTER, + .src = HRTIM_EEV10_SRC, + .pol = HRTIM_EEV10_POL, + .sen = HRTIM_EEV10_SEN, + .mode = HRTIM_EEV10_MODE, + } +#endif }; #endif @@ -593,10 +800,13 @@ static struct stm32_hrtim_s g_hrtim1priv = .time = &g_time, #endif #ifdef HRTIM_HAVE_FAULTS - .flt = &g_flt; + .flt = &g_flt, #endif #ifdef HRTIM_HAVE_EEV - .flt = &g_eev; + .eev = &g_eev, +#endif +#ifdef CONFIG_STM32_HRTIM_CMN_IRQ + .irq = HRTIM_IRQ_COMMON, #endif }; @@ -1249,35 +1459,35 @@ static int hrtim_gpios_config(FAR struct stm32_hrtim_s *priv) /* Configure Faults Inputs */ #ifdef CONFIG_STM32_HRTIM_FAULT1 - if (flt->flt1.src == HRTIM_FAULT_PIN) + if (flt->flt1.src == HRTIM_FAULT_SRC_PIN) { stm32_configgpio(GPIO_HRTIM1_FLT1); } #endif #ifdef CONFIG_STM32_HRTIM_FAULT2 - if (flt->flt2.src == HRTIM_FAULT_PIN) + if (flt->flt2.src == HRTIM_FAULT_SRC_PIN) { stm32_configgpio(GPIO_HRTIM1_FLT2); } #endif #ifdef CONFIG_STM32_HRTIM_FAULT3 - if (flt->flt3.src == HRTIM_FAULT_PIN) + if (flt->flt3.src == HRTIM_FAULT_SRC_PIN) { stm32_configgpio(GPIO_HRTIM1_FLT3); } #endif #ifdef CONFIG_STM32_HRTIM_FAULT4 - if (flt->flt4.src == HRTIM_FAULT_PIN) + if (flt->flt4.src == HRTIM_FAULT_SRC_PIN) { stm32_configgpio(GPIO_HRTIM1_FLT4); } #endif #ifdef CONFIG_STM32_HRTIM_FAULT5 - if (flt->flt5.src == HRTIM_FAULT_PIN) + if (flt->flt5.src == HRTIM_FAULT_SRC_PIN) { stm32_configgpio(GPIO_HRTIM1_FLT5); } @@ -1614,30 +1824,445 @@ static int hrtim_adc_config(FAR struct stm32_hrtim_s *priv) } #endif +#ifdef HRTIM_HAVE_FAULTS + /**************************************************************************** - * Name: hrtim_faults_config + * Name: hrtim_tim_flts_cfg * * Description: - * Configure HRTIM Faults + * Configure HRTIM Slave Timer faults sources. * * Input Parameters: * priv - A reference to the HRTIM structure + * timer - timer index + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +static int hrtim_tim_flts_cfg(FAR struct stm32_hrtim_s *priv, uint8_t timer) +{ + FAR struct stm32_hrtim_tim_s *tim; + FAR struct stm32_hrtim_slave_priv_s *slave_priv; + uint32_t regval = 0; + + tim = hrtim_tim_get(priv, timer); + + slave_priv = tim->priv; + + /* Get lock configuration */ + + regval = ((slave_priv->flt & HRTIM_TIM_FAULT_LOCK) ? HRTIM_TIMFLT_FLTLCK : 0); + + /* Get sources configuration */ + + regval |= slave_priv->flt & 0x1f; + + /* Write register */ + + hrtim_tim_putreg(priv, timer, STM32_HRTIM_TIM_FLTR_OFFSET, regval); + + return OK; +} + +/**************************************************************************** + * Name: hrtim_faults_config + * + * Description: + * Configure single HRTIM Fault + * + * Input Parameters: + * priv - A reference to the HRTIM structure + * index - Fault index + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +static int hrtim_flt_cfg(FAR struct stm32_hrtim_s *priv, uint8_t index) +{ + FAR struct stm32_hrtim_fault_cfg_s *flt; + int ret = OK; + uint32_t regval = 0; + + /* Get fault configuration */ + + switch (index) + { +#ifdef CONFIG_STM32_HRTIM_FAULT1 + case 1: + { + flt = &priv->flt->flt1; + break; + } +#endif +#ifdef CONFIG_STM32_HRTIM_FAULT2 + case 2: + { + flt = &priv->flt->flt2; + break; + } +#endif +#ifdef CONFIG_STM32_HRTIM_FAULT3 + case 3: + { + flt = &priv->flt->flt3; + break; + } +#endif +#ifdef CONFIG_STM32_HRTIM_FAULT4 + case 4: + { + flt = &priv->flt->flt4; + break; + } +#endif +#ifdef CONFIG_STM32_HRTIM_FAULT5 + case 5: + { + flt = &priv->flt->flt5; + break; + } +#endif + default: + { + ret = -EINVAL; + goto errout; + } + } + + /* Configure fault */ + + switch (index) + { + /* Fault 1-4 Configuration is located in first common fault register */ + + case 1: + case 2: + case 3: + case 4: + { + regval = hrtim_getreg(priv, STM32_HRTIM_CMN_FLTINR1_OFFSET); + + /* Configure polarity */ + + regval |= (((flt->pol & HRTIM_FAULT_POL_HIGH) ? HRTIM_FLTINR1_FLT1P : 0) << (index-1)*8); + + /* Config source */ + + regval |= (((flt->src & HRTIM_FAULT_SRC_PIN) ? HRTIM_FLTINR1_FLT1SRC : 0) << (index-1)*8); + + /* Config filter */ + + regval |= ((flt->filter << HRTIM_FLTINR1_FLT1F_SHIFT) << (index-1)*8); + + /* Fault enable */ + + regval |= (HRTIM_FLTINR1_FLT1E << (index-1)*8); + + /* Write register */ + + hrtim_putreg(priv, STM32_HRTIM_CMN_FLTINR1_OFFSET, regval); + + break; + } + + /* Fault 5 configuration is located in second common fault register */ + + case 5: + { + regval = hrtim_getreg(priv, STM32_HRTIM_CMN_FLTINR2_OFFSET); + + /* Configure polarity */ + + regval |= ((flt->pol & HRTIM_FAULT_POL_HIGH) ? HRTIM_FLTINR2_FLT5P : 0); + + /* Config source */ + + regval |= ((flt->src & HRTIM_FAULT_SRC_PIN) ? HRTIM_FLTINR2_FLT5SRC : 0); + + /* Config filter */ + + regval |= ((flt->filter << HRTIM_FLTINR2_FLT5F_SHIFT)); + + /* Fault enable */ + + regval |= HRTIM_FLTINR2_FLT5E; + + /* Write register */ + + hrtim_putreg(priv, STM32_HRTIM_CMN_FLTINR2_OFFSET, regval); + + break; + } + + default: + { + ret = -EINVAL; + goto errout; + } + } + +errout: + return ret; +} + +/**************************************************************************** + * Name: hrtim_faults_config + * + * Description: + * Configure HRTIM Faults + * + * Input Parameters: + * priv - A reference to the HRTIM structure * * Returned Value: * 0 on success, a negated errno value on failure * ****************************************************************************/ -#ifdef HRTIM_HAVE_FAULTS static int hrtim_faults_config(FAR struct stm32_hrtim_s *priv) { -#warning "hrtim_faults_config: missing logic" + uint32_t regval = 0; + + /* Configure faults */ + +#ifdef CONFIG_STM32_HRTIM_FAULT1 + hrtim_flt_cfg(priv, 1); +#endif + +#ifdef CONFIG_STM32_HRTIM_FAULT2 + hrtim_flt_cfg(priv, 2); +#endif + +#ifdef CONFIG_STM32_HRTIM_FAULT3 + hrtim_flt_cfg(priv, 3); +#endif + +#ifdef CONFIG_STM32_HRTIM_FAULT4 + hrtim_flt_cfg(priv, 4); +#endif + +#ifdef CONFIG_STM32_HRTIM_FAULT5 + hrtim_flt_cfg(priv, 5); +#endif + + /* Configure fault sources in Slave Timers */ + +#ifdef CONFIG_STM32_HRTIM_TIMA_FLT + hrtim_tim_flts_cfg(priv, HRTIM_TIMER_TIMA); +#endif + +#ifdef CONFIG_STM32_HRTIM_TIMB_FLT + hrtim_tim_flts_cfg(priv, HRTIM_TIMER_TIMA); +#endif + +#ifdef CONFIG_STM32_HRTIM_TIMC_FLT + hrtim_tim_flts_cfg(priv, HRTIM_TIMER_TIMA); +#endif + +#ifdef CONFIG_STM32_HRTIM_TIMD_FLT + hrtim_tim_flts_cfg(priv, HRTIM_TIMER_TIMA); +#endif + +#ifdef CONFIG_STM32_HRTIM_TIME_FLT + hrtim_tim_flts_cfg(priv, HRTIM_TIMER_TIMA); +#endif + + /* Configure fault sampling clock division */ + + regval = hrtim_getreg(priv, STM32_HRTIM_CMN_FLTINR2_OFFSET); + regval |= HRTIM_FAULT_SAMPLING << HRTIM_FLTINR1_FLT1F_SHIFT; + hrtim_putreg(priv, STM32_HRTIM_CMN_FLTINR2_OFFSET, regval); + return OK; } #endif +#ifdef HRTIM_HAVE_EEV + /**************************************************************************** - * Name: hrtim_eev_config + * Name: hrtim_eev_cfg + * + * Description: + * Configure single HRTIM External Event + * + * Input Parameters: + * priv - A reference to the HRTIM structure + * index - External Event index + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +static int hrtim_eev_cfg(FAR struct stm32_hrtim_s *priv, uint8_t index) +{ + struct stm32_hrtim_eev_cfg_s* eev; + int ret = OK; + uint32_t regval = 0; + + /* Get External Event configuration */ + + switch (index) + { +#ifdef CONFIG_STM32_HRTIM_EEV1 + case 1: + { + eev = &priv->eev->eev1; + break; + } +#endif +#ifdef CONFIG_STM32_HRTIM_EEV2 + case 2: + { + eev = &priv->eev->eev2; + break; + } +#endif +#ifdef CONFIG_STM32_HRTIM_EEV3 + case 3: + { + eev = &priv->eev->eev3; + break; + } +#endif +#ifdef CONFIG_STM32_HRTIM_EEV4 + case 4: + { + eev = &priv->eev->eev4; + break; + } +#endif +#ifdef CONFIG_STM32_HRTIM_EEV5 + case 5: + { + eev = &priv->eev->eev5; + break; + } +#endif +#ifdef CONFIG_STM32_HRTIM_EEV6 + case 6: + { + eev = &priv->eev->eev6; + break; + } +#endif +#ifdef CONFIG_STM32_HRTIM_EEV7 + case 7: + { + eev = &priv->eev->eev7; + break; + } +#endif +#ifdef CONFIG_STM32_HRTIM_EEV8 + case 8: + { + eev = &priv->eev->eev8; + break; + } +#endif +#ifdef CONFIG_STM32_HRTIM_EEV8 + case 9: + { + eev = &priv->eev->eev9; + break; + } +#endif +#ifdef CONFIG_STM32_HRTIM_EEV10 + case 10: + { + eev = &priv->eev->eev10; + break; + } +#endif + default: + { + ret = -EINVAL; + goto errout; + } + } + + switch (index) + { + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + { + regval = hrtim_getreg(priv, STM32_HRTIM_CMN_EECR1_OFFSET); + + /* Configure source */ + + regval |= ((eev->src << HRTIM_EECR1_EE1SRC_SHIFT) << (index-1)*6); + + /* Configure polarity */ + + regval |= ((eev->pol & HRTIM_FAULT_POL_HIGH ? HRTIM_EECR1_EE1POL : 0) << (index-1)*6); + + /* Configure sensitivity */ + + regval |= (((eev->sen) << HRTIM_EECR1_EE1SNS_SHIFT) << (index-1)*6); + + /* Configure mode */ + + regval |= (((eev->mode & HRTIM_EEV_MODE_FAST) ? HRTIM_EECR1_EE1FAST : 0) << (index-1)*6); + + /* Write register */ + + hrtim_putreg(priv, STM32_HRTIM_CMN_EECR1_OFFSET, regval); + + break; + } + case 7: + case 8: + case 9: + case 10: + { + regval = hrtim_getreg(priv, STM32_HRTIM_CMN_EECR2_OFFSET); + + /* Configure source */ + + regval |= ((eev->src << HRTIM_EECR2_EE6SRC_SHIFT) << (index-6)*6); + + /* Configure polarity */ + + regval |= ((eev->pol & HRTIM_FAULT_POL_HIGH ? HRTIM_EECR2_EE6POL : 0) << (index-6)*6); + + /* Configure sensitivity */ + + regval |= (((eev->sen) << HRTIM_EECR2_EE6SNS_SHIFT) << (index-6)*6); + + /* Configure External Event filter, only EEV6-10 */ + + regval |= (((eev->filter) << HRTIM_EECR2_EE6SNS_SHIFT) << (index-6)*6); + + /* Write register */ + + hrtim_putreg(priv, STM32_HRTIM_CMN_EECR2_OFFSET, regval); + + break; + } + + default: + { + ret = -EINVAL; + goto errout; + } + } + + + +errout: + return ret; +} + +/**************************************************************************** + * Name: hrtim_events_config * * Description: * Configure HRTIM External Events @@ -1650,10 +2275,58 @@ static int hrtim_faults_config(FAR struct stm32_hrtim_s *priv) * ****************************************************************************/ -#ifdef HRTIM_HAVE_EEV -static int hrtim_eev_config(FAR struct stm32_hrtim_s *priv) +static int hrtim_events_config(FAR struct stm32_hrtim_s *priv) { -#warning "hrtim_eev_confi: missing logic" + uint32_t regval = 0; + + /* Configure Events sources */ + +#ifdef CONFIG_STM32_HRTIM_EEV1 + hrtim_eev_cfg(priv, 1); +#endif + +#ifdef CONFIG_STM32_HRTIM_EEV2 + hrtim_eev_cfg(priv, 2); +#endif + +#ifdef CONFIG_STM32_HRTIM_EEV3 + hrtim_eev_cfg(priv, 3); +#endif + +#ifdef CONFIG_STM32_HRTIM_EEV4 + hrtim_eev_cfg(priv, 4); +#endif + +#ifdef CONFIG_STM32_HRTIM_EEV5 + hrtim_eev_cfg(priv, 5); +#endif + +#ifdef CONFIG_STM32_HRTIM_EEV6 + hrtim_eev_cfg(priv, 6); +#endif + +#ifdef CONFIG_STM32_HRTIM_EEV7 + hrtim_eev_cfg(priv, 7); +#endif + +#ifdef CONFIG_STM32_HRTIM_EEV8 + hrtim_eev_cfg(priv, 8); +#endif + +#ifdef CONFIG_STM32_HRTIM_EEV9 + hrtim_eev_cfg(priv, 9); +#endif + +#ifdef CONFIG_STM32_HRTIM_EEV10 + hrtim_eev_cfg(priv, 10); +#endif + + /* External Event Sampling clock */ + + regval = hrtim_getreg(priv, STM32_HRTIM_CMN_EECR3_OFFSET); + regval |= (HRTIM_EEV_SAMPLING << HRTIM_EECR3_EEVSD_SHIFT); + hrtim_putreg(priv, STM32_HRTIM_CMN_EECR3_OFFSET, regval); + return OK; } #endif @@ -1888,6 +2561,64 @@ errout: return cmpx; } +/**************************************************************************** + * Name: hrtim_reset_set + * + * Description: + * Set HRTIM Timer Reset events + * + * Input parameters: + * priv - A reference to the HRTIM block + * timer - HRTIM Timer index + * reset - Reset configuration + * + * Returned Value: + * Zero on success; a negated errno value on failure + * + ****************************************************************************/ + +static int hrtim_reset_set(FAR struct stm32_hrtim_s *priv, uint8_t timer, uint32_t reset) +{ + int ret = OK; + + if (timer == HRTIM_TIMER_MASTER) + { + ret = -EINVAL; + goto errout; + } + + hrtim_tim_putreg(priv, timer, STM32_HRTIM_TIM_RSTR_OFFSET, reset); + +errout: + return ret; +} + +static int hrtim_reset_config(FAR struct stm32_hrtim_s *priv) +{ + +#ifdef CONFIG_ST32_HRTIM_TIMA + hrtim_reset_set(priv, HRTIM_TIMER_TIMA, priv->tima->reset); +#endif + +#ifdef CONFIG_ST32_HRTIM_TIMB + hrtim_reset_set(priv, HRTIM_TIMER_TIMB, priv->timb->reset); +#endif + +#ifdef CONFIG_ST32_HRTIM_TIMC + hrtim_reset_set(priv, HRTIM_TIMER_TIMC, priv->timc->reset); +#endif + +#ifdef CONFIG_ST32_HRTIM_TIMD + hrtim_reset_set(priv, HRTIM_TIMER_TIMD, priv->timd->reset); +#endif + +#ifdef CONFIG_ST32_HRTIM_TIME + hrtim_reset_set(priv, HRTIM_TIMER_TIME, priv->time->reset); +#endif + + return OK; +} + /**************************************************************************** * Name: stm32_hrtimconfig * @@ -1931,6 +2662,10 @@ static int stm32_hrtimconfig(FAR struct stm32_hrtim_s *priv) goto errout; } + /* Configure reset events */ + + hrtim_reset_config(priv); + /* Configure HRTIM GPIOs */ #if defined(HRTIM_HAVE_CAPTURE) || defined(HRTIM_HAVE_PWM) || defined(HRTIM_HAVE_SYNC) @@ -1997,10 +2732,10 @@ static int stm32_hrtimconfig(FAR struct stm32_hrtim_s *priv) } #endif - /* Configure Events */ + /* Configure External Events */ #ifdef HRTIM_HAVE_EEV - ret = hrtim_eev_config(priv); + ret = hrtim_events_config(priv); if (ret != OK) { tmrerr("ERROR: HRTIM EEV configuration failed!\n"); diff --git a/arch/arm/src/stm32/stm32_hrtim.h b/arch/arm/src/stm32/stm32_hrtim.h index 7cd0620641c..a9c0af5c428 100644 --- a/arch/arm/src/stm32/stm32_hrtim.h +++ b/arch/arm/src/stm32/stm32_hrtim.h @@ -80,6 +80,7 @@ enum stm32_hrtim_tim_e #ifdef CONFIG_STM32_HRTIM_TIME HRTIM_TIMER_TIME = 5, #endif + HRTIM_TIMER_COMMON = 6 }; /* Source which can force the Tx1/Tx2 output to its inactive state */ @@ -222,12 +223,31 @@ enum stm32_hrtim_tim_prescaler_e HRTIM_PRESCALER_128, }; +/* HRTIM Slave Timer fault sources Lock */ + +enum stm32_hrtim_tim_fault_lock_e +{ + HRTIM_TIM_FAULT_RW = 0, /* Slave Timer fault source are read/write */ + HRTIM_TIM_FAULT_LOCK = (1 << 7), /* Slave Timer fault source are read only */ +}; + +/* HRTIM Slave Timer Fault configuration */ + +enum stm32_hrtim_tim_fault_src_e +{ + HRTIM_TIM_FAULT1 = (1 << 0), + HRTIM_TIM_FAULT2 = (1 << 2), + HRTIM_TIM_FAULT3 = (1 << 3), + HRTIM_TIM_FAULT4 = (1 << 4), + HRTIM_TIM_FAULT5 = (1 << 5), +}; + /* HRTIM Fault Source */ enum stm32_hrtim_fault_src_e { - HRTIM_FAULT_SRC_PIN, - HRTIM_FAULT_SRC_INTERNAL + HRTIM_FAULT_SRC_PIN = 0, + HRTIM_FAULT_SRC_INTERNAL = 1 }; /* HRTIM External Event Source @@ -236,10 +256,81 @@ enum stm32_hrtim_fault_src_e enum stm32_hrtim_eev_src_e { - HRTIM_EEV_SRC_PIN, - HRTIM_EEV_SRC_ANALOG, - HRTIM_EEV_SRC_TRGO, - HRTIM_EEV_SRC_ADC + HRTIM_EEV_SRC_PIN = 0, + HRTIM_EEV_SRC_ANALOG = 1, + HRTIM_EEV_SRC_TRGO = 2, + HRTIM_EEV_SRC_ADC = 3 +}; + +/* HRTIM Fault Polarity */ + +enum stm32_hrtim_fault_pol_e +{ + HRTIM_FAULT_POL_LOW = 0, + HRTIM_FAULT_POL_HIGH = 1 +}; + +/* HRTIM External Event Polarity */ + +enum stm32_hrtim_eev_pol_e +{ + HRTIM_EEV_POL_HIGH = 0, /* External Event is active high */ + HRTIM_EEV_POL_LOW = 1 /* External Event is active low */ +}; + +/* HRTIM External Event sensitivity */ + +enum stm32_hrtim_eev_sen_e +{ + HRTIM_EEV_SEN_LEVEL = 0, /* On active level defined by polarity */ + HRTIM_EEV_SEN_RISING = 1, /* Rising edgne */ + HRTIM_EEV_SEN_FALLING = 2, /* Falling edge */ + HRTIM_EEV_SEN_BOTH = 3 /* Both edges */ +}; + +/* External Event Sampling clock division */ + +enum stm32_hrtim_eev_sampling_e +{ + HRTIM_EEV_SAMPLING_d1 = 0, + HRTIM_EEV_SAMPLING_d2 = 1, + HRTIM_EEV_SAMPLING_d4 = 2, + HRTIM_EEV_SAMPLING_d8 = 3 +}; + +/* HRTIM External Event Mode. + * NOTE: supported only for EEV1-5 + */ + +enum stm32_hrtim_eev_mode_e +{ + HRTIM_EEV_MODE_NORMAL, + HRTIM_EEV_MODE_FAST /* low latency mode */ +}; + + +/* External Event filter. + * NOTE: supported only for EEV6-10 + */ + +enum stm32_hrtim_eev_filter_e +{ + HRTIM_EEV_DISABLE = 0, + HRTIM_EEV_HRT_N2 = 1, + HRTIM_EEV_HRT_N4 = 2, + HRTIM_EEV_HRT_N8 = 3, + HRTIM_EEV_EEVSd2_N6 = 4, + HRTIM_EEV_EEVSd2_N8 = 5, + HRTIM_EEV_EEVSd4_N6 = 6, + HRTIM_EEV_EEVSd4_N8 = 7, + HRTIM_EEV_EEVSd8_N6 = 8, + HRTIM_EEV_EEVSd8_N8 = 9, + HRTIM_EEV_EEVSd16_N5 = 10, + HRTIM_EEV_EEVSd16_N6 = 11, + HRTIM_EEV_EEVSd16_N8 = 12, + HRTIM_EEV_EEVSd32_N5 = 13, + HRTIM_EEV_EEVSd32_N6 = 14, + HRTIM_EEV_EEVSd32_N8 = 15, }; /* Compare register index */