diff --git a/arch/risc-v/src/common/riscv_exception_common.S b/arch/risc-v/src/common/riscv_exception_common.S
index a4dbdc0c239..a45441e4b90 100644
--- a/arch/risc-v/src/common/riscv_exception_common.S
+++ b/arch/risc-v/src/common/riscv_exception_common.S
@@ -31,14 +31,6 @@
  * Public Symbols
  ****************************************************************************/
 
-#ifdef CONFIG_ARCH_RV32
-#  define REGLOAD   lw
-#  define REGSTORE  sw
-#else
-#  define REGLOAD   ld
-#  define REGSTORE  sd
-#endif
-
 #ifdef CONFIG_IRQ_NSTACKS
 #  define IRQ_NSTACKS CONFIG_IRQ_NSTACKS
 #elif defined CONFIG_SMP
diff --git a/arch/risc-v/src/common/riscv_fpu.S b/arch/risc-v/src/common/riscv_fpu.S
index b5d11f8fde5..7b5fc583988 100644
--- a/arch/risc-v/src/common/riscv_fpu.S
+++ b/arch/risc-v/src/common/riscv_fpu.S
@@ -26,12 +26,20 @@
 
 #include <arch/irq.h>
 
+#include "riscv_internal.h"
+
 #ifdef CONFIG_ARCH_FPU
 
 /************************************************************************************
  * Pre-processor Definitions
  ************************************************************************************/
 
+#define FS_MASK     0x6000
+#define FS_OFF      0x0000
+#define FS_INITIAL  0x2000
+#define FS_CLEAN    0x4000
+#define FS_DIRTY    0x6000
+
 /************************************************************************************
  * Public Symbols
  ************************************************************************************/
@@ -42,31 +50,6 @@
 
     .file         "riscv_fpu.S"
 
-#define FS_MASK     0x6000
-#define FS_OFF      0x0000
-#define FS_INITIAL  0x2000
-#define FS_CLEAN    0x4000
-#define FS_DIRTY    0x6000
-
-#if defined(CONFIG_ARCH_QPFPU)
-#  define FLOAD     flq
-#  define FSTORE    fsq
-#elif defined(CONFIG_ARCH_DPFPU)
-#  define FLOAD     fld
-#  define FSTORE    fsd
-#else
-#  define FLOAD     flw
-#  define FSTORE    fsw
-#endif
-
-#ifdef CONFIG_ARCH_RV32
-#  define REGLOAD   lw
-#  define REGSTORE  sw
-#else
-#  define REGLOAD   ld
-#  define REGSTORE  sd
-#endif
-
 /************************************************************************************
  * Public Functions
  ************************************************************************************/
diff --git a/arch/risc-v/src/common/riscv_internal.h b/arch/risc-v/src/common/riscv_internal.h
index 66df3b70cd7..c25a07a6062 100644
--- a/arch/risc-v/src/common/riscv_internal.h
+++ b/arch/risc-v/src/common/riscv_internal.h
@@ -38,6 +38,32 @@
  * Pre-processor Definitions
  ****************************************************************************/
 
+#ifdef __ASSEMBLY__
+#  define __STR(s)  s
+#else
+#  define __STR(s)  #s
+#endif
+#define __XSTR(s)   __STR(s)
+
+#if defined(CONFIG_ARCH_QPFPU)
+#  define FLOAD     __STR(flq)
+#  define FSTORE    __STR(fsq)
+#elif defined(CONFIG_ARCH_DPFPU)
+#  define FLOAD     __STR(fld)
+#  define FSTORE    __STR(fsd)
+#else
+#  define FLOAD     __STR(flw)
+#  define FSTORE    __STR(fsw)
+#endif
+
+#ifdef CONFIG_ARCH_RV32
+#  define REGLOAD   __STR(lw)
+#  define REGSTORE  __STR(sw)
+#else
+#  define REGLOAD   __STR(ld)
+#  define REGSTORE  __STR(sd)
+#endif
+
 /* This is the value used to mark the stack for subsequent stack monitoring
  * logic.
  */
@@ -49,6 +75,7 @@
 /* RISC-V requires a 16-byte stack alignment. */
 
 #define STACK_ALIGNMENT     16
+#define STACK_FRAME_SIZE    __XSTR(STACK_ALIGNMENT)
 
 /* Stack alignment macros */
 
diff --git a/arch/risc-v/src/common/riscv_signal_handler.S b/arch/risc-v/src/common/riscv_signal_handler.S
index 52d47042f80..d7dcea06b88 100644
--- a/arch/risc-v/src/common/riscv_signal_handler.S
+++ b/arch/risc-v/src/common/riscv_signal_handler.S
@@ -26,6 +26,8 @@
 
 #include <arch/syscall.h>
 
+#include "riscv_internal.h"
+
 #if defined(CONFIG_BUILD_PROTECTED) && !defined(__KERNEL__)
 
 /****************************************************************************
@@ -69,8 +71,8 @@ up_signal_handler:
 
   /* Save ra on the stack */
 
-  addi sp, sp, -16
-  sd   ra, 8(sp)
+  addi sp, sp, -STACK_FRAME_SIZE
+  REGSTORE ra, 8(sp)
 
   /* Call the signal handler */
 
@@ -82,8 +84,8 @@ up_signal_handler:
 
   /* Restore the register */
 
-  ld   ra, 8(sp)  /* Restore ra in sp */
-  addi sp, sp, 16
+  REGLOAD ra, 8(sp)  /* Restore ra in sp */
+  addi sp, sp, STACK_FRAME_SIZE
 
   /* Execute the SYS_signal_handler_return SVCall (will not return) */
 
diff --git a/arch/risc-v/src/common/riscv_swint.c b/arch/risc-v/src/common/riscv_swint.c
index dcfa92ef1c6..3ea04661e62 100644
--- a/arch/risc-v/src/common/riscv_swint.c
+++ b/arch/risc-v/src/common/riscv_swint.c
@@ -109,45 +109,24 @@ static void riscv_registerdump(const uintptr_t *regs)
 
 #ifdef CONFIG_LIB_SYSCALL
 static void dispatch_syscall(void) naked_function;
-#ifdef CONFIG_ARCH_RV64
 static void dispatch_syscall(void)
 {
   asm volatile
     (
-     " addi sp, sp, -8\n"         /* Create a stack frame to hold ra */
-     " sd   ra, 0(sp)\n"          /* Save ra in the stack frame */
-     " la   t0, g_stublookup\n"   /* t0=The base of the stub lookup table */
-     " slli a0, a0, 3\n"          /* a0=Offset for the stub lookup table */
-     " add  t0, t0, a0\n"         /* t0=The address in the table */
-     " ld   t0, 0(t0)\n"          /* t0=The address of the stub for this syscall */
-     " jalr ra, t0\n"             /* Call the stub (modifies ra) */
-     " ld   ra, 0(sp)\n"          /* Restore ra */
-     " addi sp, sp, 8\n"          /* Destroy the stack frame */
-     " mv   a2, a0\n"             /* a2=Save return value in a0 */
-     " li   a0, 3\n"              /* a0=SYS_syscall_return (3) */
-     " ecall"                     /* Return from the syscall */
+     "addi sp, sp, -" STACK_FRAME_SIZE "\n" /* Create a stack frame to hold ra */
+     REGSTORE " ra, 0(sp)\n"                /* Save ra in the stack frame */
+     "la   t0, g_stublookup\n"              /* t0=The base of the stub lookup table */
+     "slli a0, a0, 3\n"                     /* a0=Offset for the stub lookup table */
+     "add  t0, t0, a0\n"                    /* t0=The address in the table */
+     REGLOAD "   t0, 0(t0)\n"               /* t0=The address of the stub for this syscall */
+     "jalr ra, t0\n"                        /* Call the stub (modifies ra) */
+     REGLOAD " ra, 0(sp)\n"                 /* Restore ra */
+     "addi sp, sp, " STACK_FRAME_SIZE "\n"  /* Destroy the stack frame */
+     "mv   a2, a0\n"                        /* a2=Save return value in a0 */
+     "li   a0, 3\n"                         /* a0=SYS_syscall_return (3) */
+     "ecall"                                /* Return from the syscall */
   );
 }
-#else
-static void dispatch_syscall(void)
-{
-  asm volatile
-    (
-     " addi sp, sp, -4\n"         /* Create a stack frame to hold ra */
-     " sw   ra, 0(sp)\n"          /* Save ra in the stack frame */
-     " la   t0, g_stublookup\n"   /* t0=The base of the stub lookup table */
-     " slli a0, a0, 3\n"          /* a0=Offset for the stub lookup table */
-     " add  t0, t0, a0\n"         /* t0=The address in the table */
-     " lw   t0, 0(t0)\n"          /* t0=The address of the stub for this syscall */
-     " jalr ra, t0\n"             /* Call the stub (modifies ra) */
-     " lw   ra, 0(sp)\n"          /* Restore ra */
-     " addi sp, sp, 4\n"          /* Destroy the stack frame */
-     " mv   a2, a0\n"             /* a2=Save return value in a0 */
-     " li   a0, 3\n"              /* a0=SYS_syscall_return (3) */
-     " ecall"                     /* Return from the syscall */
-  );
-}
-#endif
 #endif
 
 /****************************************************************************
diff --git a/arch/risc-v/src/qemu-rv/qemu_rv_head.S b/arch/risc-v/src/qemu-rv/qemu_rv_head.S
index 3f217f5084e..3dd82652c63 100644
--- a/arch/risc-v/src/qemu-rv/qemu_rv_head.S
+++ b/arch/risc-v/src/qemu-rv/qemu_rv_head.S
@@ -72,11 +72,7 @@ __start:
 
   /* Load idle stack base to sp */
 
-#ifdef CONFIG_ARCH_RV32
-  lw   sp, 0(t0)
-#else
-  ld   sp, 0(t0)
-#endif
+  REGLOAD sp, 0(t0)
 
   /*
    * sp (stack top) = sp + idle stack size - XCPTCONTEXT_SIZE