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Add missing NSH configuration settings. Correct some conditional logic for STM32 FALSH pre-fetch settings. From Lorenz Meier

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Gregory Nutt
2013-06-02 13:16:35 -06:00
parent cfd63d53ad
commit 5d7b246c8a
2 changed files with 2 additions and 2 deletions
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arch/arm/src/stm32/stm32f20xxx_rcc.c
+1 -1
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@@ -631,7 +631,7 @@ static void stm32_stdclockconfig(void)
/* Enable FLASH prefetch, instruction cache, data cache, and 5 wait states */ /* Enable FLASH prefetch, instruction cache, data cache, and 5 wait states */
#ifdef STM32_FLASH_PREFETCH #ifdef CONFIG_STM32_FLASH_PREFETCH
regval = (FLASH_ACR_LATENCY_5 | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_PRFTEN); regval = (FLASH_ACR_LATENCY_5 | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_PRFTEN);
#else #else
regval = (FLASH_ACR_LATENCY_5 | FLASH_ACR_ICEN | FLASH_ACR_DCEN); regval = (FLASH_ACR_LATENCY_5 | FLASH_ACR_ICEN | FLASH_ACR_DCEN);
arch/arm/src/stm32/stm32f40xxx_rcc.c
+1 -1
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@@ -669,7 +669,7 @@ static void stm32_stdclockconfig(void)
/* Enable FLASH prefetch, instruction cache, data cache, and 5 wait states */ /* Enable FLASH prefetch, instruction cache, data cache, and 5 wait states */
#ifdef STM32_FLASH_PREFETCH #ifdef CONFIG_STM32_FLASH_PREFETCH
regval = (FLASH_ACR_LATENCY_5 | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_PRFTEN); regval = (FLASH_ACR_LATENCY_5 | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_PRFTEN);
#else #else
regval = (FLASH_ACR_LATENCY_5 | FLASH_ACR_ICEN | FLASH_ACR_DCEN); regval = (FLASH_ACR_LATENCY_5 | FLASH_ACR_ICEN | FLASH_ACR_DCEN);