diff --git a/arch/arm/src/samd5e5/Make.defs b/arch/arm/src/samd5e5/Make.defs index 2069522f7c8..5653b9e4df2 100644 --- a/arch/arm/src/samd5e5/Make.defs +++ b/arch/arm/src/samd5e5/Make.defs @@ -87,7 +87,7 @@ endif # Required SAMD5x/E5x files CHIP_ASRCS = -CHIP_CSRCS = sam_clockconfig.c sam_cmcc.c sam_eic.c sam_gclk.c sam_irq.c +CHIP_CSRCS = sam_clockconfig.c sam_cmcc.c sam_gclk.c sam_irq.c CHIP_CSRCS += sam_lowputc.c sam_port.c sam_serial.c sam_start.c sam_usart.c # Configuration-dependent SAMD5x/E5x files diff --git a/arch/arm/src/samd5e5/chip/sam_gclk.h b/arch/arm/src/samd5e5/chip/sam_gclk.h index 1a37fc5da45..647ab8f7c68 100644 --- a/arch/arm/src/samd5e5/chip/sam_gclk.h +++ b/arch/arm/src/samd5e5/chip/sam_gclk.h @@ -139,11 +139,11 @@ /* PCHCTRL channel mapping ******************************************************************/ -#define GCLK_CHAN_OSCCTRL_DFLL48 0 /* DFLL48 input clock source */ -#define GCLK_CHAN_OSCCTRL_FDPLL0 1 /* Reference clock for FDPLL0 */ -#define GCLK_CHAN_OSCCTRL_FDPLL1 2 /* Reference clock for FDPLL1 */ -#define GCLK_CHAN_OSCCTRL_FDPLL0_32K 3 /* FDPLL0 32KHz clock for internal lock timer */ -#define GCLK_CHAN_OSCCTRL_FDPLL1_32K 3 /* FDPLL1 32KHz clock for internal lock timer */ +#define GCLK_CHAN_OSCCTRL_DFLL 0 /* DFLL input clock source */ +#define GCLK_CHAN_OSCCTRL_DPLL0 1 /* Reference clock for DPLL0 */ +#define GCLK_CHAN_OSCCTRL_DPLL1 2 /* Reference clock for DPLL1 */ +#define GCLK_CHAN_OSCCTRL_DPLL0_32K 3 /* DPLL0 32KHz clock for internal lock timer */ +#define GCLK_CHAN_OSCCTRL_DPLL1_32K 3 /* DPLL1 32KHz clock for internal lock timer */ #define GCLK_CHAN_SDHCn_SLOW 3 /* SDHC0-1 Slow */ #define GCLK_CHAN_SDHC0_SLOW 3 /* SDHC0 Slow */ #define GCLK_CHAN_SDHC1_SLOW 3 /* SDHC1 Slow */ diff --git a/arch/arm/src/samd5e5/chip/sam_oscctrl.h b/arch/arm/src/samd5e5/chip/sam_oscctrl.h index 18fdb60835b..c4ee79d288e 100644 --- a/arch/arm/src/samd5e5/chip/sam_oscctrl.h +++ b/arch/arm/src/samd5e5/chip/sam_oscctrl.h @@ -50,249 +50,267 @@ /* OSCCTRL register offsets *****************************************************************/ -#define SAM_OSCCTRL_EVCTRL_OFFSET 0x0000 /* Event Control */ -#define SAM_OSCCTRL_INTENCLR_OFFSET 0x0004 /* Interrupt enable clear */ -#define SAM_OSCCTRL_INTENSET_OFFSET 0x0008 /* Interrupt enable set */ -#define SAM_OSCCTRL_INTFLAG_OFFSET 0x000c /* Interrupt flag status and clear */ -#define SAM_OSCCTRL_STATUS_OFFSET 0x0010 /* Status */ -#define SAM_OSCCTRL_XOSCCTRL0_OFFSET 0x0014 /* External multi-purpose crystal oscillator control 0 */ -#define SAM_OSCCTRL_XOSCCTRL1_OFFSET 0x0018 /* External multi-purpose crystal oscillator control 1 */ -#define SAM_OSCCTRL_DFLLCTRLA_OFFSET 0x001c /* DFLL48M Control A */ -#define SAM_OSCCTRL_DFLLCTRLB_OFFSET 0x0020 /* DFLL48M Control B */ -#define SAM_OSCCTRL_DFLLVAL_OFFSET 0x0024 /* DFLL48M value */ -#define SAM_OSCCTRL_DFLLMUL_OFFSET 0x0028 /* DFLL48M multiplier */ -#define SAM_OSCCTRL_DFLLSYNC_OFFSET 0x002c /* DFLL48M synchronization */ -#define SAM_OSCCTRL_DPLL0CTRLA_OFFSET 0x0030 /* DPLL0 control A */ -#define SAM_OSCCTRL_DPLL0RATIO_OFFSET 0x0034 /* DPLL0 ratio control */ -#define SAM_OSCCTRL_DPLL0CTRLB_OFFSET 0x0038 /* DPLL0 control B */ -#define SAM_OSCCTRL_DPLL0SYNCBUSY_OFFSET 0x003c /* DPLL0 synchronization busy */ -#define SAM_OSCCTRL_DPLL0STATUS_OFFSET 0x0040 /* DPLL0 status */ -#define SAM_OSCCTRL_DPLL1CTRLA_OFFSET 0x0044 /* DPLL1 control A */ -#define SAM_OSCCTRL_DPLL1RATIO_OFFSET 0x0048 /* DPLL1 ratio control */ -#define SAM_OSCCTRL_DPLL1CTRLB_OFFSET 0x004c /* DPLL1 control B */ -#define SAM_OSCCTRL_DPLL1SYNCBUSY_OFFSET 0x0050 /* DPLL1 synchronization busy */ -#define SAM_OSCCTRL_DPLL1STATUS_OFFSET 0x0054 /* DPLL1 status */ +#define SAM_OSCCTRL_EVCTRL_OFFSET 0x0000 /* Event Control */ +#define SAM_OSCCTRL_INTENCLR_OFFSET 0x0004 /* Interrupt enable clear */ +#define SAM_OSCCTRL_INTENSET_OFFSET 0x0008 /* Interrupt enable set */ +#define SAM_OSCCTRL_INTFLAG_OFFSET 0x000c /* Interrupt flag status and clear */ +#define SAM_OSCCTRL_STATUS_OFFSET 0x0010 /* Status */ +#define SAM_OSCCTRL_XOSCCTRL0_OFFSET 0x0014 /* External multi-purpose crystal oscillator control 0 */ +#define SAM_OSCCTRL_XOSCCTRL1_OFFSET 0x0018 /* External multi-purpose crystal oscillator control 1 */ + +#define SAM_OSCCTRL_DFLLCTRLA_OFFSET 0x001c /* DFLL Control A */ +#define SAM_OSCCTRL_DFLLCTRLB_OFFSET 0x0020 /* DFLL Control B */ +#define SAM_OSCCTRL_DFLLVAL_OFFSET 0x0024 /* DFLL value */ +#define SAM_OSCCTRL_DFLLMUL_OFFSET 0x0028 /* DFLL multiplier */ +#define SAM_OSCCTRL_DFLLSYNC_OFFSET 0x002c /* DFLL synchronization */ + +#define SAM_OSCCTRL_DPLL0_OFFSET 0x0030 /* DPLL0 base offset */ +#define SAM_OSCCTRL_DPLL1_OFFSET 0x0044 /* DPLL1 base offset */ +# define SAM_OSCCTRL_DPLLCTRLA_OFFSET 0x0000 /* DPLLn control A */ +# define SAM_OSCCTRL_DPLLRATIO_OFFSET 0x0004 /* DPLLn ratio control */ +# define SAM_OSCCTRL_DPLLCTRLB_OFFSET 0x0008 /* DPLLn control B */ +# define SAM_OSCCTRL_DPLLSYNCBUSY_OFFSET 0x000c /* DPLLn synchronization busy */ +# define SAM_OSCCTRL_DPLLSTATUS_OFFSET 0x0010 /* DPLLn status */ + +#define SAM_OSCCTRL_DPLL0CTRLA_OFFSET 0x0030 /* DPLL0 control A */ +#define SAM_OSCCTRL_DPLL0RATIO_OFFSET 0x0034 /* DPLL0 ratio control */ +#define SAM_OSCCTRL_DPLL0CTRLB_OFFSET 0x0038 /* DPLL0 control B */ +#define SAM_OSCCTRL_DPLL0SYNCBUSY_OFFSET 0x003c /* DPLL0 synchronization busy */ +#define SAM_OSCCTRL_DPLL0STATUS_OFFSET 0x0040 /* DPLL0 status */ + +#define SAM_OSCCTRL_DPLL1CTRLA_OFFSET 0x0044 /* DPLL1 control A */ +#define SAM_OSCCTRL_DPLL1RATIO_OFFSET 0x0048 /* DPLL1 ratio control */ +#define SAM_OSCCTRL_DPLL1CTRLB_OFFSET 0x004c /* DPLL1 control B */ +#define SAM_OSCCTRL_DPLL1SYNCBUSY_OFFSET 0x0050 /* DPLL1 synchronization busy */ +#define SAM_OSCCTRL_DPLL1STATUS_OFFSET 0x0054 /* DPLL1 status */ /* OSCCTRL register addresses ***************************************************************/ -#define SAM_OSCCTRL_EVCTRL (SAM_OSCCTRL_BASE + SAM_OSCCTRL_EVCTRL_OFFSET) -#define SAM_OSCCTRL_INTENCLR (SAM_OSCCTRL_BASE + SAM_OSCCTRL_INTENCLR_OFFSET) -#define SAM_OSCCTRL_INTENSET (SAM_OSCCTRL_BASE + SAM_OSCCTRL_INTENSET_OFFSET) -#define SAM_OSCCTRL_INTFLAG (SAM_OSCCTRL_BASE + SAM_OSCCTRL_INTFLAG_OFFSET) -#define SAM_OSCCTRL_STATUS (SAM_OSCCTRL_BASE + SAM_OSCCTRL_STATUS_OFFSET) -#define SAM_OSCCTRL_XOSCCTRL0 (SAM_OSCCTRL_BASE + SAM_OSCCTRL_XOSCCTRL0_OFFSET) -#define SAM_OSCCTRL_XOSCCTRL1 (SAM_OSCCTRL_BASE + SAM_OSCCTRL_XOSCCTRL1_OFFSET) -#define SAM_OSCCTRL_DFLLCTRLA (SAM_OSCCTRL_BASE + SAM_OSCCTRL_DFLLCTRLA_OFFSET) -#define SAM_OSCCTRL_DFLLCTRLB (SAM_OSCCTRL_BASE + SAM_OSCCTRL_DFLLCTRLB_OFFSET) -#define SAM_OSCCTRL_DFLLVAL (SAM_OSCCTRL_BASE + SAM_OSCCTRL_DFLLVAL_OFFSET) -#define SAM_OSCCTRL_DFLLMUL (SAM_OSCCTRL_BASE + SAM_OSCCTRL_DFLLMUL_OFFSET) -#define SAM_OSCCTRL_DFLLSYNC (SAM_OSCCTRL_BASE + SAM_OSCCTRL_DFLLSYNC_OFFSET) -#define SAM_OSCCTRL_DPLL0CTRLA (SAM_OSCCTRL_BASE + SAM_OSCCTRL_DPLL0CTRLA_OFFSET) -#define SAM_OSCCTRL_DPLL0RATIO (SAM_OSCCTRL_BASE + SAM_OSCCTRL_DPLL0RATIO_OFFSET) -#define SAM_OSCCTRL_DPLL0CTRLB (SAM_OSCCTRL_BASE + SAM_OSCCTRL_DPLL0CTRLB_OFFSET) -#define SAM_OSCCTRL_DPLLPRESC (SAM_OSCCTRL_BASE + SAM_OSCCTRL_DPLLPRESC_OFFSET) -#define SAM_OSCCTRL_DPLL0SYNCBUSY (SAM_OSCCTRL_BASE + SAM_OSCCTRL_DPLL0SYNCBUSY_OFFSET) -#define SAM_OSCCTRL_DPLL0STATUS (SAM_OSCCTRL_BASE + SAM_OSCCTRL_DPLL0STATUS_OFFSET) -#define SAM_OSCCTRL_DPLL1CTRLA (SAM_OSCCTRL_BASE + SAM_OSCCTRL_DPLL1CTRLA_OFFSET) -#define SAM_OSCCTRL_DPLL1RATIO (SAM_OSCCTRL_BASE + SAM_OSCCTRL_DPLL1RATIO_OFFSET) -#define SAM_OSCCTRL_DPLL1CTRLB (SAM_OSCCTRL_BASE + SAM_OSCCTRL_DPLL1CTRLB_OFFSET) -#define SAM_OSCCTRL_DPLLPRESC (SAM_OSCCTRL_BASE + SAM_OSCCTRL_DPLLPRESC_OFFSET) -#define SAM_OSCCTRL_DPLL1SYNCBUSY (SAM_OSCCTRL_BASE + SAM_OSCCTRL_DPLL1SYNCBUSY_OFFSET) -#define SAM_OSCCTRL_DPLL1STATUS (SAM_OSCCTRL_BASE + SAM_OSCCTRL_DPLL1STATUS_OFFSET) +#define SAM_OSCCTRL_EVCTRL (SAM_OSCCTRL_BASE + SAM_OSCCTRL_EVCTRL_OFFSET) +#define SAM_OSCCTRL_INTENCLR (SAM_OSCCTRL_BASE + SAM_OSCCTRL_INTENCLR_OFFSET) +#define SAM_OSCCTRL_INTENSET (SAM_OSCCTRL_BASE + SAM_OSCCTRL_INTENSET_OFFSET) +#define SAM_OSCCTRL_INTFLAG (SAM_OSCCTRL_BASE + SAM_OSCCTRL_INTFLAG_OFFSET) +#define SAM_OSCCTRL_STATUS (SAM_OSCCTRL_BASE + SAM_OSCCTRL_STATUS_OFFSET) +#define SAM_OSCCTRL_XOSCCTRL0 (SAM_OSCCTRL_BASE + SAM_OSCCTRL_XOSCCTRL0_OFFSET) +#define SAM_OSCCTRL_XOSCCTRL1 (SAM_OSCCTRL_BASE + SAM_OSCCTRL_XOSCCTRL1_OFFSET) + +#define SAM_OSCCTRL_DFLLCTRLA (SAM_OSCCTRL_BASE + SAM_OSCCTRL_DFLLCTRLA_OFFSET) +#define SAM_OSCCTRL_DFLLCTRLB (SAM_OSCCTRL_BASE + SAM_OSCCTRL_DFLLCTRLB_OFFSET) +#define SAM_OSCCTRL_DFLLVAL (SAM_OSCCTRL_BASE + SAM_OSCCTRL_DFLLVAL_OFFSET) +#define SAM_OSCCTRL_DFLLMUL (SAM_OSCCTRL_BASE + SAM_OSCCTRL_DFLLMUL_OFFSET) +#define SAM_OSCCTRL_DFLLSYNC (SAM_OSCCTRL_BASE + SAM_OSCCTRL_DFLLSYNC_OFFSET) + +#define SAM_OSCCTRL_DPLL0_BASE (SAM_OSCCTRL_BASE + SAM_OSCCTRL_DPLL0_OFFSET) +#define SAM_OSCCTRL_DPLL0CTRLA (SAM_OSCCTRL_BASE + SAM_OSCCTRL_DPLL0CTRLA_OFFSET) +#define SAM_OSCCTRL_DPLL0RATIO (SAM_OSCCTRL_BASE + SAM_OSCCTRL_DPLL0RATIO_OFFSET) +#define SAM_OSCCTRL_DPLL0CTRLB (SAM_OSCCTRL_BASE + SAM_OSCCTRL_DPLL0CTRLB_OFFSET) +#define SAM_OSCCTRL_DPLLPRESC (SAM_OSCCTRL_BASE + SAM_OSCCTRL_DPLLPRESC_OFFSET) +#define SAM_OSCCTRL_DPLL0SYNCBUSY (SAM_OSCCTRL_BASE + SAM_OSCCTRL_DPLL0SYNCBUSY_OFFSET) +#define SAM_OSCCTRL_DPLL0STATUS (SAM_OSCCTRL_BASE + SAM_OSCCTRL_DPLL0STATUS_OFFSET) + +#define SAM_OSCCTRL_DPLL1_BASE (SAM_OSCCTRL_BASE + SAM_OSCCTRL_DPLL1_OFFSET) +#define SAM_OSCCTRL_DPLL1CTRLA (SAM_OSCCTRL_BASE + SAM_OSCCTRL_DPLL1CTRLA_OFFSET) +#define SAM_OSCCTRL_DPLL1RATIO (SAM_OSCCTRL_BASE + SAM_OSCCTRL_DPLL1RATIO_OFFSET) +#define SAM_OSCCTRL_DPLL1CTRLB (SAM_OSCCTRL_BASE + SAM_OSCCTRL_DPLL1CTRLB_OFFSET) +#define SAM_OSCCTRL_DPLLPRESC (SAM_OSCCTRL_BASE + SAM_OSCCTRL_DPLLPRESC_OFFSET) +#define SAM_OSCCTRL_DPLL1SYNCBUSY (SAM_OSCCTRL_BASE + SAM_OSCCTRL_DPLL1SYNCBUSY_OFFSET) +#define SAM_OSCCTRL_DPLL1STATUS (SAM_OSCCTRL_BASE + SAM_OSCCTRL_DPLL1STATUS_OFFSET) /* OSCCTRL register bit definitions *********************************************************/ /* Event Control */ -#define OSCCTRL_EVCTRL_CFDEO0 (1 << 0) /* Bit 0: Clock 0 failure detector event output enable */ -#define OSCCTRL_EVCTRL_CFDEO1 (1 << 1) /* Bit 1: Clock 1 failure detector event output enable */ +#define OSCCTRL_EVCTRL_CFDEO0 (1 << 0) /* Bit 0: Clock 0 failure detector event output enable */ +#define OSCCTRL_EVCTRL_CFDEO1 (1 << 1) /* Bit 1: Clock 1 failure detector event output enable */ /* Interrupt enable clear, Interrupt enable set, Interrupt flag status and clear, and * Status registers. */ -#define OSCCTRL_INT_XOSCRDY0 (1 << 0) /* Bit 0: XOSC 0 ready interrupt */ -#define OSCCTRL_INT_XOSCRDY1 (1 << 1) /* Bit 1: XOSC 1 ready interrupt */ -#define OSCCTRL_INT_XOSCFAIL0 (1 << 2) /* Bit 2: XOSC 0 clock failure interrupt */ -#define OSCCTRL_INT_XOSCFAIL1 (1 << 3) /* Bit 3: XOSC 1 clock failure interrupt */ -#define OSCCTRL_STATUS_XOSCCKSW0 (1 << 4) /* Bit 4: XOSC 1 clock failure interrupt (status) */ -#define OSCCTRL_STATUS_XOSCCKSW1 (1 << 5) /* Bit 5: XOSC 1 clock failure interrupt (status) */ -#define OSCCTRL_INT_DFLLRDY (1 << 8) /* Bit 8: DFLL ready interrupt */ -#define OSCCTRL_INT_DFLLOOB (1 << 9) /* Bit 9: DFLL out of bounds interrupt */ -#define OSCCTRL_INT_DFLLLCKF (1 << 10) /* Bit 10: DFLL lock fine interrupt */ -#define OSCCTRL_INT_DFLLLCKC (1 << 11) /* Bit 11: DFLL lock coarse interrupt */ -#define OSCCTRL_INT_DFLLRCS (1 << 12) /* Bit 12: DFLL reference clock stopped interrupt */ -#define OSCCTRL_INT_DPLL0LCKR (1 << 16) /* Bit 16: DPLL0 lock rise interrupt */ -#define OSCCTRL_INT_DPLL0LCKF (1 << 17) /* Bit 17: DPLL0 lock fall interrupt */ -#define OSCCTRL_INT_DPLL0LTO (1 << 18) /* Bit 18: DPLL0 lock timeout */ -#define OSCCTRL_INT_DPLL0DRTO (1 << 19) /* Bit 19: DPLL0 loop divider ratio update complete */ -#define OSCCTRL_INT_DPLL1LCKR (1 << 24) /* Bit 24: DPLL1 lock rise interrupt */ -#define OSCCTRL_INT_DPLL1LCKF (1 << 25) /* Bit 25: DPLL1 lock fall interrupt */ -#define OSCCTRL_INT_DPLL1LTO (1 << 26) /* Bit 26: DPLL1 lock timeout */ -#define OSCCTRL_INT_DPLL1DRTO (1 << 27) /* Bit 27: DPLL1 loop divider ratio update complete */ +#define OSCCTRL_INT_XOSCRDY0 (1 << 0) /* Bit 0: XOSC 0 ready interrupt */ +#define OSCCTRL_INT_XOSCRDY1 (1 << 1) /* Bit 1: XOSC 1 ready interrupt */ +#define OSCCTRL_INT_XOSCFAIL0 (1 << 2) /* Bit 2: XOSC 0 clock failure interrupt */ +#define OSCCTRL_INT_XOSCFAIL1 (1 << 3) /* Bit 3: XOSC 1 clock failure interrupt */ +#define OSCCTRL_STATUS_XOSCCKSW0 (1 << 4) /* Bit 4: XOSC 1 clock failure interrupt (status) */ +#define OSCCTRL_STATUS_XOSCCKSW1 (1 << 5) /* Bit 5: XOSC 1 clock failure interrupt (status) */ +#define OSCCTRL_INT_DFLLRDY (1 << 8) /* Bit 8: DFLL ready interrupt */ +#define OSCCTRL_INT_DFLLOOB (1 << 9) /* Bit 9: DFLL out of bounds interrupt */ +#define OSCCTRL_INT_DFLLLCKF (1 << 10) /* Bit 10: DFLL lock fine interrupt */ +#define OSCCTRL_INT_DFLLLCKC (1 << 11) /* Bit 11: DFLL lock coarse interrupt */ +#define OSCCTRL_INT_DFLLRCS (1 << 12) /* Bit 12: DFLL reference clock stopped interrupt */ +#define OSCCTRL_INT_DPLL0LCKR (1 << 16) /* Bit 16: DPLL0 lock rise interrupt */ +#define OSCCTRL_INT_DPLL0LCKF (1 << 17) /* Bit 17: DPLL0 lock fall interrupt */ +#define OSCCTRL_INT_DPLL0LTO (1 << 18) /* Bit 18: DPLL0 lock timeout */ +#define OSCCTRL_INT_DPLL0DRTO (1 << 19) /* Bit 19: DPLL0 loop divider ratio update complete */ +#define OSCCTRL_INT_DPLL1LCKR (1 << 24) /* Bit 24: DPLL1 lock rise interrupt */ +#define OSCCTRL_INT_DPLL1LCKF (1 << 25) /* Bit 25: DPLL1 lock fall interrupt */ +#define OSCCTRL_INT_DPLL1LTO (1 << 26) /* Bit 26: DPLL1 lock timeout */ +#define OSCCTRL_INT_DPLL1DRTO (1 << 27) /* Bit 27: DPLL1 loop divider ratio update complete */ -#define OSCCTRL_INT_ALL (0x0f0f1f0f) +#define OSCCTRL_INT_ALL (0x0f0f1f0f) /* External multi-purpose crystal oscillator control register 0/1 */ -#define OSCCTRL_XOSCCTRL_ENABLE (1 << 1) /* Bit 1: Oscillator enable */ -#define OSCCTRL_XOSCCTRL_XTALEN (1 << 2) /* Bit 2: Crystal oscillator enable */ -#define OSCCTRL_XOSCCTRL_RUNSTDBY (1 << 6) /* Bit 6: Run in standby */ -#define OSCCTRL_XOSCCTRL_ONDEMAND (1 << 7) /* Bit 7: On demand control */ -#define OSCCTRL_XOSCCTRL_LOWBUFGAIN (1 << 8) /* Bit 8: Low buffer gain enable */ -#define OSCCTRL_XOSCCTRL_IPTAT_SHIFT (9) /* Bits 9-10: Oscillator current reference */ -#define OSCCTRL_XOSCCTRL_IPTAT_MASK (3 << OSCCTRL_XOSCCTRL_IPTAT_SHIFT) -# define OSCCTRL_XOSCCTRL_IPTAT(n) ((uint32_t)(n) << OSCCTRL_XOSCCTRL_IPTAT_SHIFT) -#define OSCCTRL_XOSCCTRL_IMULT_SHIFT (11) /* Bits 11-14: Oscillator current reference */ -#define OSCCTRL_XOSCCTRL_IMULT_MASK (15 << OSCCTRL_XOSCCTRL_IMULT_SHIFT) -# define OSCCTRL_XOSCCTRL_IMULT(n) ((uint32_t)(n) << OSCCTRL_XOSCCTRL_IMULT_SHIFT) -#define OSCCTRL_XOSCCTRL_ENALC (1 << 15) /* Bit 15: Automatic loop control enable */ -#define OSCCTRL_XOSCCTRL_CFDEN (1 << 16) /* Bit 16: Clock failure detector enable */ -#define OSCCTRL_XOSCCTRL_SWBEN (1 << 17) /* Bit 17: XOSC clock switch enable */ -#define OSCCTRL_XOSCCTRL_STARTUP_SHIFT (20) /* Bits 20-23: Start-up time */ -#define OSCCTRL_XOSCCTRL_STARTUP_MASK (15 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) -# define OSCCTRL_XOSCCTRL_STARTUP(n) ((n) << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) -# define OSCCTRL_XOSCCTRL_STARTUP_31US (0 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 31µs */ -# define OSCCTRL_XOSCCTRL_STARTUP_61US (1 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 61µs */ -# define OSCCTRL_XOSCCTRL_STARTUP_122US (2 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 122µs */ -# define OSCCTRL_XOSCCTRL_STARTUP_244US (3 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 244µs */ -# define OSCCTRL_XOSCCTRL_STARTUP_488US (4 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 488µs */ -# define OSCCTRL_XOSCCTRL_STARTUP_977US (5 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 977µs */ -# define OSCCTRL_XOSCCTRL_STARTUP_2MS (6 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 1953µs */ -# define OSCCTRL_XOSCCTRL_STARTUP_4MS (7 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 3906µs */ -# define OSCCTRL_XOSCCTRL_STARTUP_8MS (8 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 7813µs */ -# define OSCCTRL_XOSCCTRL_STARTUP_16MS (9 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 15625µs */ -# define OSCCTRL_XOSCCTRL_STARTUP_31MS (10 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 31250µs */ -# define OSCCTRL_XOSCCTRL_STARTUP_63MS (11 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 62500µs */ -# define OSCCTRL_XOSCCTRL_STARTUP_125MS (12 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 125000µs */ -# define OSCCTRL_XOSCCTRL_STARTUP_250MS (13 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 250000µs */ -# define OSCCTRL_XOSCCTRL_STARTUP_500MS (14 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 500000µs */ -# define OSCCTRL_XOSCCTRL_STARTUP_1S (15 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 1000000µs */ -#define OSCCTRL_XOSCCTRL_CFDPRESC_SHIFT (24) /* Bits 24-27: Clock Failure Detector Prescaler */ -#define OSCCTRL_XOSCCTRL_CFDPRESC_MASK (15 << OSCCTRL_XOSCCTRL_CFDPRESC_SHIFT) -# define OSCCTRL_XOSCCTRL_CFDPRESC(n) ((uint32_t)(n) << OSCCTRL_XOSCCTRL_CFDPRESC_SHIFT) +#define OSCCTRL_XOSCCTRL_ENABLE (1 << 1) /* Bit 1: Oscillator enable */ +#define OSCCTRL_XOSCCTRL_XTALEN (1 << 2) /* Bit 2: Crystal oscillator enable */ +#define OSCCTRL_XOSCCTRL_RUNSTDBY (1 << 6) /* Bit 6: Run in standby */ +#define OSCCTRL_XOSCCTRL_ONDEMAND (1 << 7) /* Bit 7: On demand control */ +#define OSCCTRL_XOSCCTRL_LOWBUFGAIN (1 << 8) /* Bit 8: Low buffer gain enable */ +#define OSCCTRL_XOSCCTRL_IPTAT_SHIFT (9) /* Bits 9-10: Oscillator current reference */ +#define OSCCTRL_XOSCCTRL_IPTAT_MASK (3 << OSCCTRL_XOSCCTRL_IPTAT_SHIFT) +# define OSCCTRL_XOSCCTRL_IPTAT(n) ((uint32_t)(n) << OSCCTRL_XOSCCTRL_IPTAT_SHIFT) +#define OSCCTRL_XOSCCTRL_IMULT_SHIFT (11) /* Bits 11-14: Oscillator current reference */ +#define OSCCTRL_XOSCCTRL_IMULT_MASK (15 << OSCCTRL_XOSCCTRL_IMULT_SHIFT) +# define OSCCTRL_XOSCCTRL_IMULT(n) ((uint32_t)(n) << OSCCTRL_XOSCCTRL_IMULT_SHIFT) +#define OSCCTRL_XOSCCTRL_ENALC (1 << 15) /* Bit 15: Automatic loop control enable */ +#define OSCCTRL_XOSCCTRL_CFDEN (1 << 16) /* Bit 16: Clock failure detector enable */ +#define OSCCTRL_XOSCCTRL_SWBEN (1 << 17) /* Bit 17: XOSC clock switch enable */ +#define OSCCTRL_XOSCCTRL_STARTUP_SHIFT (20) /* Bits 20-23: Start-up time */ +#define OSCCTRL_XOSCCTRL_STARTUP_MASK (15 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) +# define OSCCTRL_XOSCCTRL_STARTUP(n) ((n) << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) +# define OSCCTRL_XOSCCTRL_STARTUP_31US (0 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 31µs */ +# define OSCCTRL_XOSCCTRL_STARTUP_61US (1 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 61µs */ +# define OSCCTRL_XOSCCTRL_STARTUP_122US (2 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 122µs */ +# define OSCCTRL_XOSCCTRL_STARTUP_244US (3 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 244µs */ +# define OSCCTRL_XOSCCTRL_STARTUP_488US (4 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 488µs */ +# define OSCCTRL_XOSCCTRL_STARTUP_977US (5 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 977µs */ +# define OSCCTRL_XOSCCTRL_STARTUP_2MS (6 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 1953µs */ +# define OSCCTRL_XOSCCTRL_STARTUP_4MS (7 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 3906µs */ +# define OSCCTRL_XOSCCTRL_STARTUP_8MS (8 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 7813µs */ +# define OSCCTRL_XOSCCTRL_STARTUP_16MS (9 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 15625µs */ +# define OSCCTRL_XOSCCTRL_STARTUP_31MS (10 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 31250µs */ +# define OSCCTRL_XOSCCTRL_STARTUP_63MS (11 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 62500µs */ +# define OSCCTRL_XOSCCTRL_STARTUP_125MS (12 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 125000µs */ +# define OSCCTRL_XOSCCTRL_STARTUP_250MS (13 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 250000µs */ +# define OSCCTRL_XOSCCTRL_STARTUP_500MS (14 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 500000µs */ +# define OSCCTRL_XOSCCTRL_STARTUP_1S (15 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 1000000µs */ +#define OSCCTRL_XOSCCTRL_CFDPRESC_SHIFT (24) /* Bits 24-27: Clock Failure Detector Prescaler */ +#define OSCCTRL_XOSCCTRL_CFDPRESC_MASK (15 << OSCCTRL_XOSCCTRL_CFDPRESC_SHIFT) +# define OSCCTRL_XOSCCTRL_CFDPRESC(n) ((uint32_t)(n) << OSCCTRL_XOSCCTRL_CFDPRESC_SHIFT) -/* DFLL48M control register A */ +/* DFLL control register A */ -#define OSCCTRL_DFLLCTRLA_ENABLE (1 << 1) /* Bit 1: DFLL enable */ -#define OSCCTRL_DFLLCTRLA_RUNSTDBY (1 << 6) /* Bit 6: Run in standby */ -#define OSCCTRL_DFLLCTRLA_ONDEMAND (1 << 7) /* Bit 7: On demand control */ +#define OSCCTRL_DFLLCTRLA_ENABLE (1 << 1) /* Bit 1: DFLL enable */ +#define OSCCTRL_DFLLCTRLA_RUNSTDBY (1 << 6) /* Bit 6: Run in standby */ +#define OSCCTRL_DFLLCTRLA_ONDEMAND (1 << 7) /* Bit 7: On demand control */ -/* DFLL48M control register B */ +/* DFLL control register B */ -#define OSCCTRL_DFLLCTRLB_MODE (1 << 0) /* Bit 0: Operating mode selection */ -#define OSCCTRL_DFLLCTRLB_STABLE (1 << 1) /* Bit 1: Stable DFLL frequency */ -#define OSCCTRL_DFLLCTRLB_LLAW (1 << 2) /* Bit 2: Lose lock after wake */ -#define OSCCTRL_DFLLCTRLB_USBCRM (1 << 3) /* Bit 3: USB clock recovery mode */ -#define OSCCTRL_DFLLCTRLB_CCDIS (1 << 4) /* Bit 4: Chill cycle disable */ -#define OSCCTRL_DFLLCTRLB_QLDIS (1 << 5) /* Bit 5: Quick Lock Disable */ -#define OSCCTRL_DFLLCTRLB_BPLCKC (1 << 6) /* Bit 6: Bypass coarse clock */ -#define OSCCTRL_DFLLCTRLB_WAITLOCK (1 << 7) /* Bit 7: Wait lock */ +#define OSCCTRL_DFLLCTRLB_MODE (1 << 0) /* Bit 0: Operating mode selection */ +#define OSCCTRL_DFLLCTRLB_STABLE (1 << 1) /* Bit 1: Stable DFLL frequency */ +#define OSCCTRL_DFLLCTRLB_LLAW (1 << 2) /* Bit 2: Lose lock after wake */ +#define OSCCTRL_DFLLCTRLB_USBCRM (1 << 3) /* Bit 3: USB clock recovery mode */ +#define OSCCTRL_DFLLCTRLB_CCDIS (1 << 4) /* Bit 4: Chill cycle disable */ +#define OSCCTRL_DFLLCTRLB_QLDIS (1 << 5) /* Bit 5: Quick Lock Disable */ +#define OSCCTRL_DFLLCTRLB_BPLCKC (1 << 6) /* Bit 6: Bypass coarse clock */ +#define OSCCTRL_DFLLCTRLB_WAITLOCK (1 << 7) /* Bit 7: Wait lock */ -/* DFLL48M value register */ +/* DFLL value register */ -#define OSCCTRL_DFLLVAL_FINE_SHIFT (0) /* Bits 0-7: Fine value */ -#define OSCCTRL_DFLLVAL_FINE_MASK (0xff << OSCCTRL_DFLLVAL_FINE_SHIFT) -# define OSCCTRL_DFLLVAL_FINE(n) ((uint32_t)(n) << OSCCTRL_DFLLVAL_FINE_SHIFT) -#define OSCCTRL_DFLLVAL_COARSE_SHIFT (10) /* Bits 10-15: Coarse value */ -#define OSCCTRL_DFLLVAL_COARSE_MASK (0x3f << OSCCTRL_DFLLVAL_COARSE_SHIFT) -# define OSCCTRL_DFLLVAL_COARSE(n) ((uint32_t)(n) << OSCCTRL_DFLLVAL_COARSE_SHIFT) -#define OSCCTRL_DFLLVAL_DIFF_SHIFT (16) /* Bits 16-31: Multiplication ratio difference */ -#define OSCCTRL_DFLLVAL_DIFF_MASK (0xffff << OSCCTRL_DFLLVAL_DIFF_SHIFT) -# define OSCCTRL_DFLLVAL_DIFF(n) ((n) << OSCCTRL_DFLLVAL_DIFF_SHIFT) +#define OSCCTRL_DFLLVAL_FINE_SHIFT (0) /* Bits 0-7: Fine value */ +#define OSCCTRL_DFLLVAL_FINE_MASK (0xff << OSCCTRL_DFLLVAL_FINE_SHIFT) +# define OSCCTRL_DFLLVAL_FINE(n) ((uint32_t)(n) << OSCCTRL_DFLLVAL_FINE_SHIFT) +#define OSCCTRL_DFLLVAL_COARSE_SHIFT (10) /* Bits 10-15: Coarse value */ +#define OSCCTRL_DFLLVAL_COARSE_MASK (0x3f << OSCCTRL_DFLLVAL_COARSE_SHIFT) +# define OSCCTRL_DFLLVAL_COARSE(n) ((uint32_t)(n) << OSCCTRL_DFLLVAL_COARSE_SHIFT) +#define OSCCTRL_DFLLVAL_DIFF_SHIFT (16) /* Bits 16-31: Multiplication ratio difference */ +#define OSCCTRL_DFLLVAL_DIFF_MASK (0xffff << OSCCTRL_DFLLVAL_DIFF_SHIFT) +# define OSCCTRL_DFLLVAL_DIFF(n) ((n) << OSCCTRL_DFLLVAL_DIFF_SHIFT) -/* DFLL48M multiplier register */ +/* DFLL multiplier register */ -#define OSCCTRL_DFLLMUL_MUL_SHIFT (0) /* Bits 0-15: DFLL multiply factor */ -#define OSCCTRL_DFLLMUL_MUL_MASK (0xffff << OSCCTRL_DFLLMUL_MUL_SHIFT) -# define OSCCTRL_DFLLMUL_MUL(n) ((uint32_t)(n) << OSCCTRL_DFLLMUL_MUL_SHIFT) -#define OSCCTRL_DFLLMUL_FSTEP_SHIFT (16) /* Bits 16-23: Fine maximum step */ -#define OSCCTRL_DFLLMUL_FSTEP_MASK (0xff << OSCCTRL_DFLLMUL_FSTEP_SHIFT) -# define OSCCTRL_DFLLMUL_FSTEP(n) ((uint32_t)(n) << OSCCTRL_DFLLMUL_FSTEP_SHIFT) -#define OSCCTRL_DFLLMUL_CSTEP_SHIFT (26) /* Bits 26-31: Coarse maximum step */ -#define OSCCTRL_DFLLMUL_CSTEP_MASK (0x3f << OSCCTRL_DFLLMUL_CSTEP_SHIFT) -# define OSCCTRL_DFLLMUL_CSTEP(n) ((uint32_t)(n) << OSCCTRL_DFLLMUL_CSTEP_SHIFT) +#define OSCCTRL_DFLLMUL_MUL_SHIFT (0) /* Bits 0-15: DFLL multiply factor */ +#define OSCCTRL_DFLLMUL_MUL_MASK (0xffff << OSCCTRL_DFLLMUL_MUL_SHIFT) +# define OSCCTRL_DFLLMUL_MUL(n) ((uint32_t)(n) << OSCCTRL_DFLLMUL_MUL_SHIFT) +#define OSCCTRL_DFLLMUL_FSTEP_SHIFT (16) /* Bits 16-23: Fine maximum step */ +#define OSCCTRL_DFLLMUL_FSTEP_MASK (0xff << OSCCTRL_DFLLMUL_FSTEP_SHIFT) +# define OSCCTRL_DFLLMUL_FSTEP(n) ((uint32_t)(n) << OSCCTRL_DFLLMUL_FSTEP_SHIFT) +#define OSCCTRL_DFLLMUL_CSTEP_SHIFT (26) /* Bits 26-31: Coarse maximum step */ +#define OSCCTRL_DFLLMUL_CSTEP_MASK (0x3f << OSCCTRL_DFLLMUL_CSTEP_SHIFT) +# define OSCCTRL_DFLLMUL_CSTEP(n) ((uint32_t)(n) << OSCCTRL_DFLLMUL_CSTEP_SHIFT) -/* DFLL48M synchronization register */ +/* DFLL synchronization register */ -#define OSCCTRL_DFLLSYNC_ENABLE (1 << 1) /* Bit 1: ENABLE Synchronization Busy */ -#define OSCCTRL_DFLLSYNC_DFLLCTRLB (1 << 2) /* Bit 2: DFLLCTRLB Synchronization Busy */ -#define OSCCTRL_DFLLSYNC_DFLLVAL (1 << 3) /* Bit 3: DFLLVAL Synchronization Busy */ -#define OSCCTRL_DFLLSYNC_REDFLLMULADREQ (1 << 4) /* Bit 4: DFLLMUL Synchronization Busy */ +#define OSCCTRL_DFLLSYNC_ENABLE (1 << 1) /* Bit 1: ENABLE Synchronization Busy */ +#define OSCCTRL_DFLLSYNC_DFLLCTRLB (1 << 2) /* Bit 2: DFLLCTRLB Synchronization Busy */ +#define OSCCTRL_DFLLSYNC_DFLLVAL (1 << 3) /* Bit 3: DFLLVAL Synchronization Busy */ +#define OSCCTRL_DFLLSYNC_DFLLMUL (1 << 4) /* Bit 4: DFLLMUL Synchronization Busy */ /* DPLL0/1 control A */ -#define OSCCTRL_DPLLCTRLA_ENABLE (1 << 1) /* Bit 1: DPLL enable */ -#define OSCCTRL_DPLLCTRLA_RUNSTDBY (1 << 6) /* Bit 6: Run in standby */ -#define OSCCTRL_DPLLCTRLA_ONDEMAND (1 << 7) /* Bit 7: On demand clock activation */ +#define OSCCTRL_DPLLCTRLA_ENABLE (1 << 1) /* Bit 1: DPLL enable */ +#define OSCCTRL_DPLLCTRLA_RUNSTDBY (1 << 6) /* Bit 6: Run in standby */ +#define OSCCTRL_DPLLCTRLA_ONDEMAND (1 << 7) /* Bit 7: On demand clock activation */ /* DPLL0/1 ratio control */ -#define OSCCTRL_DPLLRATIO_LDR_SHIFT (0) /* Bits 0-11: Loop divider ratio */ -#define OSCCTRL_DPLLRATIO_LDR_MASK (0x1fff << OSCCTRL_DPLLRATIO_LDR_SHIFT) -# define OSCCTRL_DPLLRATIO_LDR(n) ((uint32_t)(n) << OSCCTRL_DPLLRATIO_LDR_SHIFT) -#define OSCCTRL_DPLLRATIO_LDRFRAC_SHIFT (16) /* Bits 16-20: Loop divider fractional part */ -#define OSCCTRL_DPLLRATIO_LDRFRAC_MASK (31 << OSCCTRL_DPLLRATIO_LDRFRAC_SHIFT) -# define OSCCTRL_DPLLRATIO_LDRFRAC(n) ((uint32_t)(n) << OSCCTRL_DPLLRATIO_LDRFRAC_SHIFT) +#define OSCCTRL_DPLLRATIO_LDR_SHIFT (0) /* Bits 0-11: Loop divider ratio */ +#define OSCCTRL_DPLLRATIO_LDR_MASK (0x1fff << OSCCTRL_DPLLRATIO_LDR_SHIFT) +# define OSCCTRL_DPLLRATIO_LDR(n) ((uint32_t)(n) << OSCCTRL_DPLLRATIO_LDR_SHIFT) +#define OSCCTRL_DPLLRATIO_LDRFRAC_SHIFT (16) /* Bits 16-20: Loop divider fractional part */ +#define OSCCTRL_DPLLRATIO_LDRFRAC_MASK (31 << OSCCTRL_DPLLRATIO_LDRFRAC_SHIFT) +# define OSCCTRL_DPLLRATIO_LDRFRAC(n) ((uint32_t)(n) << OSCCTRL_DPLLRATIO_LDRFRAC_SHIFT) /* DPLL0/1 control B */ -#define OSCCTRL_DPLLCTRLB_FILTER_SHIFT (0) /* Bits 0-3: Proportional integer filter selection */ -#define OSCCTRL_DPLLCTRLB_FILTER_MASK (15 << OSCCTRL_DPLLCTRLB_FILTER_SHIFT) -# define OSCCTRL_DPLLCTRLB_FILTER(n) ((uint32_t)(n) << OSCCTRL_DPLLCTRLB_FILTER_SHIFT) +#define OSCCTRL_DPLLCTRLB_FILTER_SHIFT (0) /* Bits 0-3: Proportional integer filter selection */ +#define OSCCTRL_DPLLCTRLB_FILTER_MASK (15 << OSCCTRL_DPLLCTRLB_FILTER_SHIFT) +# define OSCCTRL_DPLLCTRLB_FILTER(n) ((uint32_t)(n) << OSCCTRL_DPLLCTRLB_FILTER_SHIFT) /* PLL BW Damping */ -# define OSCCTRL_DPLLCTRLB_FILTER0 (0 << OSCCTRL_DPLLCTRLB_FILTER_SHIFT) /* 92.7 kHz 0.76 */ -# define OSCCTRL_DPLLCTRLB_FILTER1 (1 << OSCCTRL_DPLLCTRLB_FILTER_SHIFT) /* 131 kHz 1.08 */ -# define OSCCTRL_DPLLCTRLB_FILTER2 (2 << OSCCTRL_DPLLCTRLB_FILTER_SHIFT) /* 46.4 kHz 0.38 */ -# define OSCCTRL_DPLLCTRLB_FILTER3 (3 << OSCCTRL_DPLLCTRLB_FILTER_SHIFT) /* 65.6 kHz 0.54 */ -# define OSCCTRL_DPLLCTRLB_FILTER4 (4 << OSCCTRL_DPLLCTRLB_FILTER_SHIFT) /* 131 kHz 0.56 */ -# define OSCCTRL_DPLLCTRLB_FILTER5 (5 << OSCCTRL_DPLLCTRLB_FILTER_SHIFT) /* 185 kHz 0.79 */ -# define OSCCTRL_DPLLCTRLB_FILTER6 (6 << OSCCTRL_DPLLCTRLB_FILTER_SHIFT) /* 65.6 kHz 0.28 */ -# define OSCCTRL_DPLLCTRLB_FILTER7 (7 << OSCCTRL_DPLLCTRLB_FILTER_SHIFT) /* 92.7 kHz 0.39 */ -# define OSCCTRL_DPLLCTRLB_FILTER8 (8 << OSCCTRL_DPLLCTRLB_FILTER_SHIFT) /* 46.4 kHz 1.49 */ -# define OSCCTRL_DPLLCTRLB_FILTER9 (9 << OSCCTRL_DPLLCTRLB_FILTER_SHIFT) /* 65.6 kHz 2.11 */ -# define OSCCTRL_DPLLCTRLB_FILTER10 (10 << OSCCTRL_DPLLCTRLB_FILTER_SHIFT) /* 23.2 kHz 0.75 */ -# define OSCCTRL_DPLLCTRLB_FILTER11 (11 << OSCCTRL_DPLLCTRLB_FILTER_SHIFT) /* 32.8 kHz 1.06 */ -# define OSCCTRL_DPLLCTRLB_FILTER12 (12 << OSCCTRL_DPLLCTRLB_FILTER_SHIFT) /* 65.6 kHz 1.07 */ -# define OSCCTRL_DPLLCTRLB_FILTER13 (13 << OSCCTRL_DPLLCTRLB_FILTER_SHIFT) /* 92.7 kHz 1.51 */ -# define OSCCTRL_DPLLCTRLB_FILTER14 (14 << OSCCTRL_DPLLCTRLB_FILTER_SHIFT) /* 32.8 kHz 0.53 */ -# define OSCCTRL_DPLLCTRLB_FILTER15 (15 << OSCCTRL_DPLLCTRLB_FILTER_SHIFT) /* 46.4 kHz 0.75 */ -#define OSCCTRL_DPLLCTRLB_WUF (1 << 4) /* Bit 4: Wake up fast */ -#define OSCCTRL_DPLLCTRLB_REFLCK_SHIFT (5) /* Bits 5-7: Reference clock selection */ -#define OSCCTRL_DPLLCTRLB_REFLCK_MASK (3 << OSCCTRL_DPLLCTRLB_REFLCK_SHIFT) -# define OSCCTRL_DPLLCTRLB_REFLCK_GLCK (0 << OSCCTRL_DPLLCTRLB_REFLCK_SHIFT) /* Dedicated GCLK clock reference */ -# define OSCCTRL_DPLLCTRLB_REFLCK_XOSC32 (1 << OSCCTRL_DPLLCTRLB_REFLCK_SHIFT) /* XOSC32K clock reference (default) */ -# define OSCCTRL_DPLLCTRLB_REFLCK_XOSC0 (2 << OSCCTRL_DPLLCTRLB_REFLCK_SHIFT) /* XOSC0 clock reference */ -# define OSCCTRL_DPLLCTRLB_REFLCK_XOSC1 (3 << OSCCTRL_DPLLCTRLB_REFLCK_SHIFT) /* XOSC2 clock reference */ -#define OSCCTRL_DPLLCTRLB_LTIME_SHIFT (8) /* Bits 8-10: Lock time */ -#define OSCCTRL_DPLLCTRLB_LTIME_MASK (7 << OSCCTRL_DPLLCTRLB_LTIME_SHIFT) -# define OSCCTRL_DPLLCTRLB_LTIME_NONE (0 << OSCCTRL_DPLLCTRLB_LTIME_SHIFT) /* No time-out. Automatic lock */ -# define OSCCTRL_DPLLCTRLB_LTIME_800US (4 << OSCCTRL_DPLLCTRLB_LTIME_SHIFT) /* Time-out if no locka within 800 us */ -# define OSCCTRL_DPLLCTRLB_LTIME_900US (5 << OSCCTRL_DPLLCTRLB_LTIME_SHIFT) /* Time-out if no locka within 900 us */ -# define OSCCTRL_DPLLCTRLB_LTIME_1MS (6 << OSCCTRL_DPLLCTRLB_LTIME_SHIFT) /* Time-out if no locka within 1MS */ -# define OSCCTRL_DPLLCTRLB_LTIME_1p1MS (7 << OSCCTRL_DPLLCTRLB_LTIME_SHIFT) /* Time-out if no locka within 1.1MS */ -#define OSCCTRL_DPLLCTRLB_LBYPASS (1 << 11) /* Bit 11: Lock bypass */ -#define OSCCTRL_DPLLCTRLB_DCOFILTER_SHIFT (12) /* Bits 12-14: Sigma-Delta DCO Filter Selection */ -#define OSCCTRL_DPLLCTRLB_DCOFILTER_MASK (7 << OSCCTRL_DPLLCTRLB_DCOFILTER_SHIFT) -# define OSCCTRL_DPLLCTRLB_DCOFILTER(n) ((uint32_t)(n) << OSCCTRL_DPLLCTRLB_DCOFILTER_SHIFT) +# define OSCCTRL_DPLLCTRLB_FILTER0 (0 << OSCCTRL_DPLLCTRLB_FILTER_SHIFT) /* 92.7 kHz 0.76 */ +# define OSCCTRL_DPLLCTRLB_FILTER1 (1 << OSCCTRL_DPLLCTRLB_FILTER_SHIFT) /* 131 kHz 1.08 */ +# define OSCCTRL_DPLLCTRLB_FILTER2 (2 << OSCCTRL_DPLLCTRLB_FILTER_SHIFT) /* 46.4 kHz 0.38 */ +# define OSCCTRL_DPLLCTRLB_FILTER3 (3 << OSCCTRL_DPLLCTRLB_FILTER_SHIFT) /* 65.6 kHz 0.54 */ +# define OSCCTRL_DPLLCTRLB_FILTER4 (4 << OSCCTRL_DPLLCTRLB_FILTER_SHIFT) /* 131 kHz 0.56 */ +# define OSCCTRL_DPLLCTRLB_FILTER5 (5 << OSCCTRL_DPLLCTRLB_FILTER_SHIFT) /* 185 kHz 0.79 */ +# define OSCCTRL_DPLLCTRLB_FILTER6 (6 << OSCCTRL_DPLLCTRLB_FILTER_SHIFT) /* 65.6 kHz 0.28 */ +# define OSCCTRL_DPLLCTRLB_FILTER7 (7 << OSCCTRL_DPLLCTRLB_FILTER_SHIFT) /* 92.7 kHz 0.39 */ +# define OSCCTRL_DPLLCTRLB_FILTER8 (8 << OSCCTRL_DPLLCTRLB_FILTER_SHIFT) /* 46.4 kHz 1.49 */ +# define OSCCTRL_DPLLCTRLB_FILTER9 (9 << OSCCTRL_DPLLCTRLB_FILTER_SHIFT) /* 65.6 kHz 2.11 */ +# define OSCCTRL_DPLLCTRLB_FILTER10 (10 << OSCCTRL_DPLLCTRLB_FILTER_SHIFT) /* 23.2 kHz 0.75 */ +# define OSCCTRL_DPLLCTRLB_FILTER11 (11 << OSCCTRL_DPLLCTRLB_FILTER_SHIFT) /* 32.8 kHz 1.06 */ +# define OSCCTRL_DPLLCTRLB_FILTER12 (12 << OSCCTRL_DPLLCTRLB_FILTER_SHIFT) /* 65.6 kHz 1.07 */ +# define OSCCTRL_DPLLCTRLB_FILTER13 (13 << OSCCTRL_DPLLCTRLB_FILTER_SHIFT) /* 92.7 kHz 1.51 */ +# define OSCCTRL_DPLLCTRLB_FILTER14 (14 << OSCCTRL_DPLLCTRLB_FILTER_SHIFT) /* 32.8 kHz 0.53 */ +# define OSCCTRL_DPLLCTRLB_FILTER15 (15 << OSCCTRL_DPLLCTRLB_FILTER_SHIFT) /* 46.4 kHz 0.75 */ +#define OSCCTRL_DPLLCTRLB_WUF (1 << 4) /* Bit 4: Wake up fast */ +#define OSCCTRL_DPLLCTRLB_REFLCK_SHIFT (5) /* Bits 5-7: Reference clock selection */ +#define OSCCTRL_DPLLCTRLB_REFLCK_MASK (3 << OSCCTRL_DPLLCTRLB_REFLCK_SHIFT) +# define OSCCTRL_DPLLCTRLB_REFLCK(n) ((uint32_t)(n) << OSCCTRL_DPLLCTRLB_REFLCK_SHIFT) +# define OSCCTRL_DPLLCTRLB_REFLCK_GLCK (0 << OSCCTRL_DPLLCTRLB_REFLCK_SHIFT) /* Dedicated GCLK clock reference */ +# define OSCCTRL_DPLLCTRLB_REFLCK_XOSC32 (1 << OSCCTRL_DPLLCTRLB_REFLCK_SHIFT) /* XOSC32K clock reference (default) */ +# define OSCCTRL_DPLLCTRLB_REFLCK_XOSC0 (2 << OSCCTRL_DPLLCTRLB_REFLCK_SHIFT) /* XOSC0 clock reference */ +# define OSCCTRL_DPLLCTRLB_REFLCK_XOSC1 (3 << OSCCTRL_DPLLCTRLB_REFLCK_SHIFT) /* XOSC2 clock reference */ +#define OSCCTRL_DPLLCTRLB_LTIME_SHIFT (8) /* Bits 8-10: Lock time */ +#define OSCCTRL_DPLLCTRLB_LTIME_MASK (7 << OSCCTRL_DPLLCTRLB_LTIME_SHIFT) +# define OSCCTRL_DPLLCTRLB_LTIME(n) ((uint32_t)(n) << OSCCTRL_DPLLCTRLB_LTIME_SHIFT) +# define OSCCTRL_DPLLCTRLB_LTIME_NONE (0 << OSCCTRL_DPLLCTRLB_LTIME_SHIFT) /* No time-out. Automatic lock */ +# define OSCCTRL_DPLLCTRLB_LTIME_800US (4 << OSCCTRL_DPLLCTRLB_LTIME_SHIFT) /* Time-out if no locka within 800 us */ +# define OSCCTRL_DPLLCTRLB_LTIME_900US (5 << OSCCTRL_DPLLCTRLB_LTIME_SHIFT) /* Time-out if no locka within 900 us */ +# define OSCCTRL_DPLLCTRLB_LTIME_1MS (6 << OSCCTRL_DPLLCTRLB_LTIME_SHIFT) /* Time-out if no locka within 1MS */ +# define OSCCTRL_DPLLCTRLB_LTIME_1p1MS (7 << OSCCTRL_DPLLCTRLB_LTIME_SHIFT) /* Time-out if no locka within 1.1MS */ +#define OSCCTRL_DPLLCTRLB_LBYPASS (1 << 11) /* Bit 11: Lock bypass */ +#define OSCCTRL_DPLLCTRLB_DCOFILTER_SHIFT (12) /* Bits 12-14: Sigma-Delta DCO Filter Selection */ +#define OSCCTRL_DPLLCTRLB_DCOFILTER_MASK (7 << OSCCTRL_DPLLCTRLB_DCOFILTER_SHIFT) +# define OSCCTRL_DPLLCTRLB_DCOFILTER(n) ((uint32_t)(n) << OSCCTRL_DPLLCTRLB_DCOFILTER_SHIFT) /* Capa pF BW MHz */ -# define OSCCTRL_DPLLCTRLB_DCOFILTER0 (0 << OSCCTRL_DPLLCTRLB_DCOFILTER_SHIFT) /* 0.5 3.21 */ -# define OSCCTRL_DPLLCTRLB_DCOFILTER1 (1 << OSCCTRL_DPLLCTRLB_DCOFILTER_SHIFT) /* 1 1.6 */ -# define OSCCTRL_DPLLCTRLB_DCOFILTER2 (2 << OSCCTRL_DPLLCTRLB_DCOFILTER_SHIFT) /* 1.5 1.1 */ -# define OSCCTRL_DPLLCTRLB_DCOFILTER3 (3 << OSCCTRL_DPLLCTRLB_DCOFILTER_SHIFT) /* 2 0.8 */ -# define OSCCTRL_DPLLCTRLB_DCOFILTER4 (4 << OSCCTRL_DPLLCTRLB_DCOFILTER_SHIFT) /* 2.5 0.64 */ -# define OSCCTRL_DPLLCTRLB_DCOFILTER5 (5 << OSCCTRL_DPLLCTRLB_DCOFILTER_SHIFT) /* 3 0.55 */ -# define OSCCTRL_DPLLCTRLB_DCOFILTER6 (6 << OSCCTRL_DPLLCTRLB_DCOFILTER_SHIFT) /* 3.5 0.45 */ -# define OSCCTRL_DPLLCTRLB_DCOFILTER7 (7 << OSCCTRL_DPLLCTRLB_DCOFILTER_SHIFT) /* 4 0.4 */ -#define OSCCTRL_DPLLCTRLB_DCOEN (1 << 15) /* Bit 15: DCO Filter Enable */ -#define OSCCTRL_DPLLCTRLB_DIV_SHIFT (16) /* Bits 16-26: Clock divider */ -#define OSCCTRL_DPLLCTRLB_DIV_MASK (0x7ff << OSCCTRL_DPLLCTRLB_DIV_SHIFT) -# define OSCCTRL_DPLLCTRLB_DIV(n) ((uint32_t)(n) << OSCCTRL_DPLLCTRLB_DIV_SHIFT) +# define OSCCTRL_DPLLCTRLB_DCOFILTER0 (0 << OSCCTRL_DPLLCTRLB_DCOFILTER_SHIFT) /* 0.5 3.21 */ +# define OSCCTRL_DPLLCTRLB_DCOFILTER1 (1 << OSCCTRL_DPLLCTRLB_DCOFILTER_SHIFT) /* 1 1.6 */ +# define OSCCTRL_DPLLCTRLB_DCOFILTER2 (2 << OSCCTRL_DPLLCTRLB_DCOFILTER_SHIFT) /* 1.5 1.1 */ +# define OSCCTRL_DPLLCTRLB_DCOFILTER3 (3 << OSCCTRL_DPLLCTRLB_DCOFILTER_SHIFT) /* 2 0.8 */ +# define OSCCTRL_DPLLCTRLB_DCOFILTER4 (4 << OSCCTRL_DPLLCTRLB_DCOFILTER_SHIFT) /* 2.5 0.64 */ +# define OSCCTRL_DPLLCTRLB_DCOFILTER5 (5 << OSCCTRL_DPLLCTRLB_DCOFILTER_SHIFT) /* 3 0.55 */ +# define OSCCTRL_DPLLCTRLB_DCOFILTER6 (6 << OSCCTRL_DPLLCTRLB_DCOFILTER_SHIFT) /* 3.5 0.45 */ +# define OSCCTRL_DPLLCTRLB_DCOFILTER7 (7 << OSCCTRL_DPLLCTRLB_DCOFILTER_SHIFT) /* 4 0.4 */ +#define OSCCTRL_DPLLCTRLB_DCOEN (1 << 15) /* Bit 15: DCO Filter Enable */ +#define OSCCTRL_DPLLCTRLB_DIV_SHIFT (16) /* Bits 16-26: Clock divider */ +#define OSCCTRL_DPLLCTRLB_DIV_MASK (0x7ff << OSCCTRL_DPLLCTRLB_DIV_SHIFT) +# define OSCCTRL_DPLLCTRLB_DIV(n) ((uint32_t)(n) << OSCCTRL_DPLLCTRLB_DIV_SHIFT) /* DPLL0 synchronization busy */ -#define OSCCTRL_DPLL0STATUS_ENABLE (1 << 1) /* Bit 1: DPLL enable synchronization status */ -#define OSCCTRL_DPLL0STATUS_DPLLRATIO (1 << 2) /* Bit 2: DPLL loop divider ratio synchronization status */ +#define OSCCTRL_DPLL0STATUS_ENABLE (1 << 1) /* Bit 1: DPLL enable synchronization status */ +#define OSCCTRL_DPLL0STATUS_DPLLRATIO (1 << 2) /* Bit 2: DPLL loop divider ratio synchronization status */ /* DPLL0 status */ diff --git a/arch/arm/src/samd5e5/sam_clockconfig.c b/arch/arm/src/samd5e5/sam_clockconfig.c index ea2d2ae94c2..e5364e6a4ed 100644 --- a/arch/arm/src/samd5e5/sam_clockconfig.c +++ b/arch/arm/src/samd5e5/sam_clockconfig.c @@ -70,10 +70,6 @@ * Private Data ****************************************************************************/ -/* This is the currently configured CPU frequency */ - -static uint32_t g_cpu_frequency; - /* This describes the power-up clock configuration using data provided in the * board.h header file. */ @@ -131,6 +127,62 @@ static const struct sam_clockconfig_s g_initial_clocking = .xosc_frequency = BOARD_XOSC1_FREQUENCY, }, #endif + .dfll = + { + .enable = BOARD_DFLL_ENABLE, + .runstdby = BOARD_DFLL_RUNSTDBY, + .ondemand = BOARD_DFLL_ONDEMAND, + .mode = BOARD_DFLL_MODE, + .stable = BOARD_DFLL_STABLE, + .llaw = BOARD_DFLL_LLAW, + .usbcrm = BOARD_DFLL_USBCRM, + .ccdis = BOARD_DFLL_CCDIS, + .qldis = BOARD_DFLL_QLDIS, + .bplckc = BOARD_DFLL_BPLCKC, + .waitlock = BOARD_DFLL_WAITLOCK, + .caliben = BOARD_DFLL_CALIBEN, + .fcalib = BOARD_DFLL_FCALIB, + .ccalib = BOARD_DFLL_CCALIB, + .fstep = BOARD_DFLL_FSTEP, + .cstep = BOARD_DFLL_CSTEP, + .gclk = BOARD_DFLL_GCLK, + .mul = BOARD_DFLL_MUL + }, + .dpll = + { + { + .enable = BOARD_DPLL0_ENABLE, + .dcoen = BOARD_DPLL0_DCOEN, + .lbypass = BOARD_DPLL0_LBYPASS, + .wuf = BOARD_DPLL0_WUF, + .runstdby = BOARD_DPLL0_RUNSTDBY, + .ondemand = BOARD_DPLL0_ONDEMAND, + .refclk = BOARD_DPLL0_REFCLK, + .ltime = BOARD_DPLL0_LTIME, + .filter = BOARD_DPLL0_FILTER, + .dcofilter = BOARD_DPLL0_DCOFILTER, + .gclk = BOARD_DPLL0_GCLK, + .ldrfrac = BOARD_DPLL0_LDRFRAC, + .ldrint = BOARD_DPLL0_LDRINT, + .div = BOARD_DPLL0_DIV + }, + { + .enable = BOARD_DPLL1_ENABLE, + .dcoen = BOARD_DPLL1_DCOEN, + .lbypass = BOARD_DPLL1_LBYPASS, + .wuf = BOARD_DPLL1_WUF, + .runstdby = BOARD_DPLL1_RUNSTDBY, + .ondemand = BOARD_DPLL1_ONDEMAND, + .refclk = BOARD_DPLL1_REFCLK, + .ltime = BOARD_DPLL1_LTIME, + .filter = BOARD_DPLL1_FILTER, + .dcofilter = BOARD_DPLL1_DCOFILTER, + .gclk = BOARD_DPLL1_GCLK, + .ldrfrac = BOARD_DPLL1_LDRFRAC, + .ldrint = BOARD_DPLL1_LDRINT, + .div = BOARD_DPLL1_DIV + } + }, .gclk = { { @@ -261,14 +313,28 @@ static const struct sam_clockconfig_s g_initial_clocking = ****************************************************************************/ /**************************************************************************** - * Name: sam_set_waitsates + * Name: sam_get_waitstates * * Description: * Set the number of FLASH wait states. * ****************************************************************************/ -static void sam_set_waitsates(const struct sam_clockconfig_s *config) +static uint16_t sam_get_waitstates(void) +{ + uint16_t regval = getreg16(SAM_NVMCTRL_CTRLA); + return (regval & NVMCTRL_CTRLA_RWS_MASK) >> NVMCTRL_CTRLA_RWS_SHIFT; +} + +/**************************************************************************** + * Name: sam_set_waitstates + * + * Description: + * Set the number of FLASH wait states. + * + ****************************************************************************/ + +static void sam_set_waitstates(const struct sam_clockconfig_s *config) { DEBUGASSERT(config->waitstates < 16); modifyreg16(SAM_NVMCTRL_CTRLA, NVMCTRL_CTRLA_RWS_MASK, @@ -543,19 +609,6 @@ static inline void sam_mclk_configure(uint8_t cpudiv) putreg8(cpudiv, SAM_MCLK_CPUDIV); } -/**************************************************************************** - * Name: sam_fdpll_configure - * - * Description: - * Configure FDPLL0 and FDPLL1 - * - ****************************************************************************/ - -static void sam_fdpll_configure(const struct sam_fdpll_config_s config[2]) -{ -#warning Missing logic -} - /**************************************************************************** * Name: sam_gclk_configure * @@ -647,6 +700,356 @@ static void sam_gclkset_configure(uint16_t gclkset, } } +/**************************************************************************** + * Name: sam_dfll_configure, sam_dfll_ready, and sam_dfll_gclkready + * + * Description: + * Configure the DFLL + * + ****************************************************************************/ + +static void sam_dfll_configure(const struct sam_dfll_config_s *config) +{ + uint32_t regval32; + uint8_t regval8; + + /* Set GCLK0 source to OSCULP32K (temporarily) */ + + regval32 = getreg32(SAM_GCLK_GENCTRL_OFFSET(0)); + regval32 &= GCLK_GENCTRL_SRC_MASK; + regval32 |= GCLK_GENCTRL_SRC_OSCULP32K; + putreg32(regval32, SAM_GCLK_GENCTRL_OFFSET(0)); + + /* Disable the DFLL */ + + putreg8(0, SAM_OSCCTRL_DFLLCTRLA); + + /* If we are running in closed loop mode and we are in USB clock recover + * mode, then set up the input source GCLK channel. + */ + + if (config->usbcrm && config->mode) + { + /* Configure the GCLK channel */ + + sam_gclk_chan_enable(GCLK_CHAN_OSCCTRL_DFLL, config->gclk); + } + + /* Setup the DFLLMUL register */ + + regval32 = OSCCTRL_DFLLMUL_MUL(config->mul) | + OSCCTRL_DFLLMUL_FSTEP(config->fstep) | + OSCCTRL_DFLLMUL_CSTEP(config->cstep); + putreg32(regval32, SAM_OSCCTRL_DFLLMUL); + + /* Wait until the multiplier is synchronized */ + + do + { + regval8 = getreg32(SAM_OSCCTRL_DFLLSYNC); + regval8 &= OSCCTRL_DFLLSYNC_DFLLMUL; + } + while (regval8 != 0); + + /* Reset the DFLLCTRLB register */ + + putreg32(0, SAM_OSCCTRL_DFLLCTRLB); + + do + { + regval8 = getreg8(SAM_OSCCTRL_DFLLSYNC); + regval8 &= OSCCTRL_DFLLSYNC_DFLLCTRLB; + } + while (regval8 != 0); + + /* Set up the DFLLCTRLA register */ + + regval8 = OSCCTRL_DPLLCTRLA_ENABLE; + + if (config->runstdby) + { + regval8 |= OSCCTRL_DPLLCTRLA_RUNSTDBY; + } + + putreg8(regval8, SAM_OSCCTRL_DFLLCTRLA); + + do + { + regval8 = getreg8(SAM_OSCCTRL_DFLLSYNC); + regval8 &= OSCCTRL_DPLLCTRLA_ENABLE; + } + while (regval8 != 0); + + /* Overwrite factory calibration values is so requested */ + + if (config->caliben) + { + regval32 = OSCCTRL_DFLLVAL_FINE(config->fcalib) | + OSCCTRL_DFLLVAL_COARSE(config->ccalib); + putreg32(regval32, SAM_OSCCTRL_DFLLVAL); + } + else + { + regval32 = getreg32(SAM_OSCCTRL_DFLLVAL); + } + + /* Writing to the DFLLVAL will force it to re-syncrhonize */ + + putreg32(regval32, SAM_OSCCTRL_DFLLVAL); + + do + { + regval8 = getreg8(SAM_OSCCTRL_DFLLSYNC); + regval8 &= OSCCTRL_DFLLSYNC_DFLLVAL; + } + while (regval8 != 0); + + /* Setup the DFLLCTRLB register */ + + regval8 = 0; + + if (config->mode) + { + regval8 |= OSCCTRL_DFLLCTRLB_MODE; + } + + if (config->stable) + { + regval8 |= OSCCTRL_DFLLCTRLB_STABLE; + } + + if (config->llaw) + { + regval8 |= OSCCTRL_DFLLCTRLB_LLAW; + } + + if (config->usbcrm) + { + regval8 |= OSCCTRL_DFLLCTRLB_USBCRM; + } + + if (config->ccdis) + { + regval8 |= OSCCTRL_DFLLCTRLB_CCDIS; + } + + if (config->qldis) + { + regval8 |= OSCCTRL_DFLLCTRLB_QLDIS; + } + + if (config->bplckc) + { + regval8 |= OSCCTRL_DFLLCTRLB_BPLCKC; + } + + if (config->waitlock) + { + regval8 |= OSCCTRL_DFLLCTRLB_WAITLOCK; + } + + putreg8(regval8, SAM_OSCCTRL_DPLL0CTRLB); + + do + { + regval8 = getreg8(SAM_OSCCTRL_DFLLSYNC); + regval8 &= OSCCTRL_DFLLSYNC_DFLLCTRLB; + } + while (regval8 != 0); +} + +static void sam_dfll_ready(const struct sam_dfll_config_s *config) +{ + uint32_t ready; + uint32_t regval32; + uint8_t regval8; + + /* Check if the mode bit was set, i.e., we are in closed-loop mode. If so + * wait for the DFLL to be ready for and for the coarse lock to be obtained. + */ + + regval8 = getreg8(SAM_OSCCTRL_DPLL0CTRLB); + if ((regval8 & OSCCTRL_DFLLCTRLB_MODE) != 0) + { + ready = OSCCTRL_INT_DFLLRDY | OSCCTRL_INT_DFLLLCKC; + + } + + /* In open-loop mode, wait only for DFLL ready */ + + else + { + ready = OSCCTRL_INT_DFLLRDY; + } + + /* Wait for whichever ready condition */ + + do + { + regval32 = getreg32(SAM_OSCCTRL_STATUS); + regval32 &= ready; + } + while (regval32 != ready); + + /* Now, we can set the OnDemand bit in the DFLLCTRLA */ + + if (config->ondemand) + { + regval8 = getreg8(SAM_OSCCTRL_DFLLCTRLA); + regval8 |= OSCCTRL_DFLLCTRLA_ONDEMAND; + putreg8(regval8, SAM_OSCCTRL_DFLLCTRLA); + } +} + +static void sam_dfll_gclkready(const struct sam_dfll_config_s *config) +{ + uint32_t regval32; + + /* Wait until all GCLKs are synchronized */ + + while (getreg32(SAM_GCLK_SYNCHBUSY) != 0) + { + } + + /* Set the source of GLCK0 to to the configured source. */ + + regval32 = getreg32(SAM_GCLK_GENCTRL_OFFSET(0)); + regval32 &= GCLK_GENCTRL_SRC_MASK; + regval32 |= GCLK_GENCTRL_SRC(config->gclk); + putreg32(regval32, SAM_GCLK_GENCTRL_OFFSET(0)); +} + +/**************************************************************************** + * Name: sam_dpll_configure and sam_dpll_ready + * + * Description: + * Configure a DPLL, DPLL0 or DPLL1 + * + ****************************************************************************/ + +static void sam_dpll_gclkchannel(uint8_t chan, + const struct sam_dpll_config_s *config) +{ + /* Check if we are using a dedicated GCLK as the reference clock */ + + if (config->refclk == 0) + { + /* Yes.. configure the GCLK channel */ + + sam_gclk_chan_enable(chan, config->gclk); + } +} + +static void sam_dpll_configure(uintptr_t base, + const struct sam_dpll_config_s *config) +{ + uint32_t regval; + + /* Set up the DPLL ratio control register */ + + regval = OSCCTRL_DPLLRATIO_LDR(config->ldrint) | + OSCCTRL_DPLLRATIO_LDRFRAC(config->ldrfrac); + putreg32(regval, base + SAM_OSCCTRL_DPLLRATIO_OFFSET); + + /* Set up the DPLL control B register */ + + regval = OSCCTRL_DPLLCTRLB_FILTER(config->filter) | + OSCCTRL_DPLLCTRLB_REFLCK(config->refclk) | + OSCCTRL_DPLLCTRLB_LTIME(config->ltime) | + OSCCTRL_DPLLCTRLB_DCOFILTER(config->dcofilter) | + OSCCTRL_DPLLCTRLB_DIV(config->div); + + if (config->wuf) + { + regval |= OSCCTRL_DPLLCTRLB_WUF; + } + + if (config->lbypass) + { + regval |= OSCCTRL_DPLLCTRLB_LBYPASS; + } + + if (config->dcoen) + { + regval |= OSCCTRL_DPLLCTRLB_DCOEN; + } + + putreg32(regval, base + SAM_OSCCTRL_DPLLCTRLB_OFFSET); + + /* Set up the DPLL control A register */ + + regval = 0; + + if (config->enable) + { + regval |= OSCCTRL_DFLLCTRLA_ENABLE; + } + + if (config->runstdby) + { + regval |= OSCCTRL_DFLLCTRLA_RUNSTDBY; + } + + putreg32(regval, base + SAM_OSCCTRL_DPLLCTRLA_OFFSET); +} + +static void sam_dpll_ready(uintptr_t base, + const struct sam_dpll_config_s *config) +{ + uint32_t regval; + + /* If the DPLL was enabled, then wait for it to lock and for the clock to + * be ready. + */ + + if (config->enable) + { + uint32_t lockready = (OSCCTRL_DPLL0STATUS_LOCK | + OSCCTRL_DPLL0STATUS_CLKRDY); + do + { + regval = getreg32(base + SAM_OSCCTRL_DPLLSTATUS_OFFSET); + regval &= lockready; + } + while (regval != lockready); + } + + /* Finally, set the OnDemand bit if selected */ + + if (config->ondemand) + { + regval = getreg32(base + SAM_OSCCTRL_DPLLCTRLA_OFFSET); + regval |= OSCCTRL_DFLLCTRLA_ONDEMAND; + putreg32(regval, base + SAM_OSCCTRL_DPLLCTRLA_OFFSET); + } +} + +/**************************************************************************** + * Name: sam_loop_configure + * + * Description: + * Configure all loops: DFLL, DPLL0, and DPLL1 + * + ****************************************************************************/ + +static void sam_loop_configure(const struct sam_clockconfig_s *config) +{ + /* Configure and enable all loops */ + + sam_dfll_configure(&config->dfll); + sam_dpll_gclkchannel(GCLK_CHAN_OSCCTRL_DPLL0, &config->dpll[0]); + sam_dpll_configure(SAM_OSCCTRL_DPLL0_BASE, &config->dpll[0]); + sam_dpll_gclkchannel(GCLK_CHAN_OSCCTRL_DPLL1, &config->dpll[1]); + sam_dpll_configure(SAM_OSCCTRL_DPLL1_BASE, &config->dpll[1]); + + /* Wait for them to become ready */ + + sam_dfll_ready(&config->dfll); + sam_dpll_ready(SAM_OSCCTRL_DPLL0_BASE, &config->dpll[0]); + sam_dpll_ready(SAM_OSCCTRL_DPLL1_BASE, &config->dpll[1]); + sam_dfll_gclkready(&config->dfll); +} + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -664,17 +1067,28 @@ static void sam_gclkset_configure(uint16_t gclkset, void sam_clock_configure(const struct sam_clockconfig_s *config) { - /* Check if the clock frequency is increasing or decreasing */ + uint16_t waitstates; - if (config->cpu_frequency > g_cpu_frequency) + /* Check if the number of wait states is increasing or decreasing */ + + waitstates = sam_get_waitstates(); + if (config->waitstates > waitstates) { - /* Increasing. The number of waits states should be larger. Set the - * new number of wait states before configuring the clocking. + /* Increasing. Set the new number of wait states before configuring + * the clocking. */ - sam_set_waitsates(config); + sam_set_waitstates(config); } + /* REVISIT: This function is intended to support both the power-up reset + * clock configuration as well as the subsequent re-configuration of the + * clocking. Logic is here dependent upon the initial clock state. In + * order to successfully reconfigure the clocks, I suspect that it will be + * necessary to always restore the power-up clock configuration here before + * setting the new clock configuration. + */ + #if BOARD_HAVE_XOSC32K != 0 /* Configure XOSC32 */ @@ -697,27 +1111,27 @@ void sam_clock_configure(const struct sam_clockconfig_s *config) sam_mclk_configure(config->cpudiv); - /* Pre-configure some GCLKs before configuring the FDPLLs */ + /* Pre-configure some GCLKs before configuring the DPLLs */ sam_gclkset_configure(config->glckset1, config->gclk); - /* Configure the FDPLLs */ + /* Configure loops: DFLL, DPLL0, and DPLL1. */ - sam_fdpll_configure(config->fdpll); + sam_loop_configure(config); - /* Configure the renaming GCLKs before configuring the FDPLLs */ + /* Configure the renaming GCLKs before configuring the DPLLs */ sam_gclkset_configure(config->glckset2, config->gclk); - /* Check if the clock frequency is increasing or decreasing */ + /* Check if the number of wait states is increasing or decreasing */ - if (config->cpu_frequency < g_cpu_frequency) + if (config->waitstates < waitstates) { - /* Decreasing. The number of waits states should be smaller. Set the - * new number of wait states after configuring the clocking. + /* Decreasing. Set the new number of wait states after configuring + * the clocking. */ - sam_set_waitsates(config); + sam_set_waitstates(config); } } @@ -732,10 +1146,5 @@ void sam_clock_configure(const struct sam_clockconfig_s *config) void sam_clock_initialize(void) { - /* Clear .bss used by this file in case it is called before .bss is - * initialized. - */ - - g_cpu_frequency = 0; sam_clock_configure(&g_initial_clocking); } diff --git a/arch/arm/src/samd5e5/sam_clockconfig.h b/arch/arm/src/samd5e5/sam_clockconfig.h index 6a0a83ebe52..c6ba7fe8d13 100644 --- a/arch/arm/src/samd5e5/sam_clockconfig.h +++ b/arch/arm/src/samd5e5/sam_clockconfig.h @@ -110,10 +110,75 @@ struct sam_xosc_config_s uint32_t xosc_frequency; /* XOSC frequency */ }; -/* This structure defines the configuration of the FDPLL0/1 */ +/* This structure defines the configuration of the DFLL0 */ -struct sam_fdpll_config_s +struct sam_dfll_config_s { + uint8_t enable : 1; /* DFLL enable */ + uint8_t runstdby : 1; /* Run in standby */ + uint8_t ondemand : 1; /* On-demand control */ + uint8_t mode : 1; /* Operating mode selection + * 0 Open-loop operation + * 1 Closed-loop operation */ + uint8_t stable : 1; /* Stable DFLL frequency */ + uint8_t llaw : 1; /* Lose lock after wake */ + uint8_t usbcrm : 1; /* USB clock recovery mode */ + uint8_t ccdis : 1; /* Chill cycle disable */ + uint8_t qldis : 1; /* Quick Lock Disable */ + uint8_t bplckc : 1; /* Bypass coarse clock */ + uint8_t waitlock : 1; /* Wait lock */ + uint8_t caliben : 1; /* Overwrite factory calibration */ + uint8_t fcalib; /* Fine calibration value (if caliben != 0) */ + uint8_t ccalib; /* Coarse calibration value (if caliben != 0) */ + uint8_t fstep; /* Fine maximum step */ + uint8_t cstep; /* Coarse maximum step */ + uint8_t gclk; /* GCLK source (if usbcrm != 1 && mode != 0) */ + uint16_t mul; /* DFLL multiply factor */ +}; + +/* This structure defines the configuration of the DPLL0/1 */ + +struct sam_dpll_config_s +{ + uint8_t enable : 1; /* DPLL enable */ + uint8_t dcoen : 1; /* DCO filter enable */ + uint8_t lbypass : 1; /* Lock bypass */ + uint8_t wuf : 1; /* Wake up fast */ + uint8_t runstdby : 1; /* Run in standby */ + uint8_t ondemand : 1; /* On demand clock activation */ + uint8_t refclk; /* Reference clock selection + * 0 Dedicated GCLK clock reference + * 1 XOSC32K clock reference + * 2 XOSC0 clock reference + * 3 XOSC2 clock reference */ + uint8_t ltime; /* Lock time + * 0 No time-out. Automatic lock + * 4 Time-out if no locka within 800 us + * 5 Time-out if no locka within 900 us + * 6 Time-out if no locka within 1MS + * 7 Time-out if no locka within 1.1MS */ + uint8_t filter; /* Proportional integer filter selection + * PLL BW Damping PLL BW Damping + * 0 92.7 kHz 0.76 8 46.4 kHz 1.49 + * 1 131 kHz 1.08 9 65.6 kHz 2.11 + * 2 46.4 kHz 0.38 10 23.2 kHz 0.75 + * 3 65.6 kHz 0.54 11 32.8 kHz 1.06 + * 4 131 kHz 0.56 12 65.6 kHz 1.07 + * 5 185 kHz 0.79 13 92.7 kHz 1.51 + * 6 65.6 kHz 0.28 14 32.8 kHz 0.53 + * 7 92.7 kHz 0.39 15 46.4 kHz 0.75 */ + uint8_t dcofilter; /* Sigma-delta DCO filter selection + * + * Capa pF BW MHz Capa pF BW MHz + * 0 0.5 3.21 4 2.5 0.64 + * 1 1 1.6 5 3 0.55 + * 2 1.5 1.1 6 3.5 0.45 + * 3 2 0.8 7 4 0.4 */ + + uint8_t gclk; /* GCLK source (if refclock == 0) */ + uint8_t ldrfrac; /* Loop divider fractional part */ + uint16_t ldrint; /* Loop divider ratio */ + uint16_t div; /* Clock divider */ }; /* This structure defines the configuration of a GCLK */ @@ -145,8 +210,8 @@ struct sam_clockconfig_s { uint8_t waitstates; /* NVM read wait states 9-15 */ uint8_t cpudiv; /* MCLK divider to get CPU frequency */ - uint16_t glckset1; /* GLCKs to initialize prior to FDPLL init */ - uint16_t glckset2; /* GLCKs to initialize after to FDPLL init */ + uint16_t glckset1; /* GLCKs to initialize prior to DPLL init */ + uint16_t glckset2; /* GLCKs to initialize after to DPLL init */ uint32_t cpu_frequency; /* Resulting CPU frequency */ #if BOARD_HAVE_XOSC32K != 0 struct sam_xosc32_config_s xosc32k; /* XOSC32 configuration */ @@ -157,7 +222,8 @@ struct sam_clockconfig_s #if BOARD_HAVE_XOSC1 != 0 struct sam_xosc_config_s xosc1; /* XOSC1 configuration */ #endif - struct sam_fdpll_config_s fdpll[2]; /* FDPLL0/1 configurations */ + struct sam_dfll_config_s dfll; /* DFLL configuration */ + struct sam_dpll_config_s dpll[2]; /* DPLL0/1 configurations */ struct sam_gclk_config_s gclk[12]; /* GLCK configurations */ }; #endif /* BOARD_HAVE_CLKDEFS */ diff --git a/arch/arm/src/samd5e5/sam_sercom.c b/arch/arm/src/samd5e5/sam_sercom.c index a7eccf5a3f1..83f0ecb12a9 100644 --- a/arch/arm/src/samd5e5/sam_sercom.c +++ b/arch/arm/src/samd5e5/sam_sercom.c @@ -242,7 +242,7 @@ void sercom_slowclk_configure(int sercom, int gclkgen) * of SERCOM modules and, hence, only need to configured once. */ - sam_apb_gclk_chan_enable(GCLK_CHAN_SERCOMn_SLOW, gclkgen); + sam_gclk_chan_enable(GCLK_CHAN_SERCOMn_SLOW, gclkgen); /* The slow clock is now configured and should not be re=configured * again. diff --git a/configs/metro-m4/include/board.h b/configs/metro-m4/include/board.h index 094537bf47e..d08fb0437f4 100644 --- a/configs/metro-m4/include/board.h +++ b/configs/metro-m4/include/board.h @@ -106,15 +106,6 @@ #define BOARD_MCLK_CPUDIV 1 /* MCLK divder to get CPU frequency */ #define BOARD_CPU_FREQUENCY 120000000 /* CPU frequency 120MHz */ -/* FDPLL0/1 -- To be provided */ - -#define BOARD_FDPLL0_FREQUENCY 0 -#define BOARD_FDPLL1_FREQUENCY 0 - -/* FDLL -- To be provided */ - -#define BOARD_DFLL_FREQUENCY 0 - /* GCLK */ #define BOARD_GCLK_SET1 0x0000 /* The empty set */ @@ -178,7 +169,7 @@ #define BOARD_GCLK5_RUNSTDBY false /* Don't run in standby */ #define BOARD_GCLK5_SOURCE 6 /* Select DFLL output as GLCK5 source */ #define BOARD_GCLK5_DIV 24 /* Division factor */ -#define BOARD_GCLK5_FREQUENCY BOARD_DFLL_FREQUENCY +#define BOARD_GCLK5_FREQUENCY (BOARD_DFLL_FREQUENCY / 24) #define BOARD_GCLK6_ENABLE false /* Don't enable GCLK6 */ #define BOARD_GCLK6_IDC false /* Don't improve duty cycle */ @@ -238,7 +229,85 @@ #define BOARD_GCLK11_RUNSTDBY false /* Don't run in standby */ #define BOARD_GCLK11_SOURCE 1 /* Select XOSC1 as GLCK5 source */ #define BOARD_GCLK11_DIV 1 /* Division factor */ -#define BOARD_GCLK0_FREQUENCY BOARD_XOSC1_FREQUENCY +#define BOARD_GCLK11_FREQUENCY BOARD_XOSC1_FREQUENCY + +/* FDLL */ + +#define BOARD_DFLL_ENABLE true /* DFLL enable */ +#define BOARD_DFLL_RUNSTDBY false /* Run in standby */ +#define BOARD_DFLL_ONDEMAND false /* On-demand control */ +#define BOARD_DFLL_MODE false /* Operating mode selection */ +#define BOARD_DFLL_STABLE false /* Stable DFLL frequency */ +#define BOARD_DFLL_LLAW false /* Lose lock after wake */ +#define BOARD_DFLL_USBCRM true /* USB clock recovery mode */ +#define BOARD_DFLL_CCDIS true /* Chill cycle disable */ +#define BOARD_DFLL_QLDIS false /* Quick Lock Disable */ +#define BOARD_DFLL_BPLCKC false /* Bypass coarse clock */ +#define BOARD_DFLL_WAITLOCK true /* Wait lock */ +#define BOARD_DFLL_CALIBEN false /* Overwrite factory calibration */ +#define BOARD_DFLL_FCALIB 128 /* Coarse calibration value (if caliben) */ +#define BOARD_DFLL_CCALIB (31 / 4) /* Fine calibration value (if caliben) */ +#define BOARD_DFLL_FSTEP 1 /* Fine maximum step */ +#define BOARD_DFLL_CSTEP 1 /* Coarse maximum step */ +#define BOARD_DFLL_GCLK 3 /* GCLK source (if !usbcrm && !mode) */ +#define BOARD_DFLL_MUL 0 /* DFLL multiply factor */ + +#define BOARD_DFLL_FREQUENCY 0 /* To be provided */ + +/* DPLL0/1 + * + * Fckr is the frequency of the selected reference clock reference: + * + * BOARD_XOSC32K_FREQENCY, + * BOARD_XOSCn_FREQUENCY / DIV, or + * BOARD_GCLKn_FREQUENCY + * + * The DPLL output frequency is then given by: + * + * Fdpll = Fckr * (LDR + 1 + LDRFRAC / 32) + * + * DPLL0: + * Fckr = BOARD_GCLK5_FREQUENCY = BOARD_DFLL_FREQUENCY / 24 + * + * DPLL1: + * Fckr = BOARD_XOSCK32_FREQUENCY = 32.768KHz + * Fdpll = 32768 * (1463 + 1 + 13/32) = 47.986 MHz + */ + +#define BOARD_DPLL0_ENABLE true /* DPLL enable */ +#define BOARD_DPLL0_DCOEN false /* DCO filter enable */ +#define BOARD_DPLL0_LBYPASS false /* Lock bypass */ +#define BOARD_DPLL0_WUF false /* Wake up fast */ +#define BOARD_DPLL0_RUNSTDBY false /* Run in standby */ +#define BOARD_DPLL0_ONDEMAND false /* On demand clock activation */ +#define BOARD_DPLL0_REFCLK 0 /* Reference clock selection */ +#define BOARD_DPLL0_LTIME 0 /* Lock time */ +#define BOARD_DPLL0_FILTER 0 /* Proportional integer filter selection */ +#define BOARD_DPLL0_DCOFILTER 0 /* Sigma-delta DCO filter selection */ +#define BOARD_DPLL0_GCLK 5 /* GCLK5 source (if refclock == 0) */ +#define BOARD_DPLL0_LDRFRAC 0 /* Loop divider fractional part */ +#define BOARD_DPLL0_LDRINT 59 /* Loop divider ratio */ +#define BOARD_DPLL0_DIV 0 /* Clock divider */ + +#define BOARD_DPLL0_FCLKR BOARD_GCLK5_FREQUENCY +#define BOARD_DPLL0_FREQUENCY 0 /* To be provided */ + +#define BOARD_DPLL1_ENABLE false /* DPLL enable */ +#define BOARD_DPLL1_DCOEN false /* DCO filter enable */ +#define BOARD_DPLL1_LBYPASS false /* Lock bypass */ +#define BOARD_DPLL1_WUF false /* Wake up fast */ +#define BOARD_DPLL1_RUNSTDBY false /* Run in standby */ +#define BOARD_DPLL1_ONDEMAND false /* On demand clock activation */ +#define BOARD_DPLL1_REFCLK 1 /* Reference clock = XOSCK32 */ +#define BOARD_DPLL1_LTIME 0 /* Lock time */ +#define BOARD_DPLL1_FILTER 0 /* Sigma-delta DCO filter selection */ +#define BOARD_DPLL1_DCOFILTER 0 /* Sigma-delta DCO filter selection */ +#define BOARD_DPLL1_GCLK 0 /* GCLK source (if refclock == 0) */ +#define BOARD_DPLL1_LDRFRAC 13 /* Loop divider fractional part */ +#define BOARD_DPLL1_LDRINT 1463 /* Loop divider ratio */ +#define BOARD_DPLL1_DIV 0 /* Clock divider */ + +#define BOARD_DPLL1_FREQUENCY 47985664 /* Peripheral clocking */