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Finish port of GPIO driver for STM3240

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4122 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
2011-11-23 15:08:05 +00:00
parent 67eb344218
commit 5bcaa4dfb8
4 changed files with 428 additions and 241 deletions
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arch/arm/src/stm32/chip/stm32_syscfg.h
+46 -36
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@@ -53,20 +53,26 @@
#define STM32_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */ #define STM32_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */
#define STM32_SYSCFG_PMC_OFFSET 0x0004 /* SYSCFG peripheral mode configuration register */ #define STM32_SYSCFG_PMC_OFFSET 0x0004 /* SYSCFG peripheral mode configuration register */
#define STM32_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */
#define STM32_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */ #define STM32_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */
#define STM32_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */ #define STM32_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */
#define STM32_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */ #define STM32_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */
#define STM32_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */ #define STM32_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */
#define STM32_SYSCFG_CMPCR_OFFSET 0x0020 /* Compensation cell control register */ #define STM32_SYSCFG_CMPCR_OFFSET 0x0020 /* Compensation cell control register */
/* Register Addresses *******************************************************************************/ /* Register Addresses *******************************************************************************/
#define STM32_SYSCFG_MEMRMP (STM32_SYSCFG_BASE+STM32_SYSCFG_MEMRMP_OFFSET) #define STM32_SYSCFG_MEMRMP (STM32_SYSCFG_BASE+STM32_SYSCFG_MEMRMP_OFFSET)
#define STM32_SYSCFG_PMC (STM32_SYSCFG_BASE+STM32_SYSCFG_PMC_OFFSET) #define STM32_SYSCFG_PMC (STM32_SYSCFG_BASE+STM32_SYSCFG_PMC_OFFSET)
#define STM32_SYSCFG_EXTICR(p) (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR_OFFSET(p))
#define STM32_SYSCFG_EXTICR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR1_OFFSET) #define STM32_SYSCFG_EXTICR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR1_OFFSET)
#define STM32_SYSCFG_EXTICR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR2_OFFSET) #define STM32_SYSCFG_EXTICR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR2_OFFSET)
#define STM32_SYSCFG_EXTICR3 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR3_OFFSET) #define STM32_SYSCFG_EXTICR3 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR3_OFFSET)
#define STM32_SYSCFG_EXTICR4 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR4_OFFSET) #define STM32_SYSCFG_EXTICR4 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR4_OFFSET)
#define STM32_SYSCFG_CMPCR (STM32_SYSCFG_BASE+STM32_SYSCFG_CMPCR_OFFSET) #define STM32_SYSCFG_CMPCR (STM32_SYSCFG_BASE+STM32_SYSCFG_CMPCR_OFFSET)
/* Register Bitfield Definitions ********************************************************************/ /* Register Bitfield Definitions ********************************************************************/
@@ -75,10 +81,10 @@
#define SYSCFG_MEMRMP_SHIFT (0) /* Bits 1:0 MEM_MODE: Memory mapping selection */ #define SYSCFG_MEMRMP_SHIFT (0) /* Bits 1:0 MEM_MODE: Memory mapping selection */
#define SYSCFG_MEMRMP_MASK (3 << SYSCFG_MEMRMP_SHIFT) #define SYSCFG_MEMRMP_MASK (3 << SYSCFG_MEMRMP_SHIFT)
# define SYSCFG_MEMRMP _MASK (0 << SYSCFG_MEMRMP_SHIFT) /* 00: Main Flash memory mapped at 0x0000 0000 */ # define SYSCFG_MEMRMP_FLASH (0 << SYSCFG_MEMRMP_SHIFT) /* 00: Main Flash memory mapped at 0x0000 0000 */
# define SYSCFG_MEMRMP _MASK (1 << SYSCFG_MEMRMP_SHIFT) /* 01: System Flash memory mapped at 0x0000 0000 */ # define SYSCFG_MEMRMP_SYSTEM (1 << SYSCFG_MEMRMP_SHIFT) /* 01: System Flash memory mapped at 0x0000 0000 */
# define SYSCFG_MEMRMP _MASK (2 << SYSCFG_MEMRMP_SHIFT) /* 10: FSMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x0000 0000 */ # define SYSCFG_MEMRMP_FSMC (2 << SYSCFG_MEMRMP_SHIFT) /* 10: FSMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x0000 0000 */
# define SYSCFG_MEMRMP _MASK (3 << SYSCFG_MEMRMP_SHIFT) /* 11: Embedded SRAM (112kB) mapped at 0x0000 0000 */ # define SYSCFG_MEMRMP_SRAM (3 << SYSCFG_MEMRMP_SHIFT) /* 11: Embedded SRAM (112kB) mapped at 0x0000 0000 */
/* SYSCFG peripheral mode configuration register */ /* SYSCFG peripheral mode configuration register */
@@ -96,41 +102,45 @@
#define SYSCFG_EXTICR_PORTH (7) /* 0111: PH[x] pin */ #define SYSCFG_EXTICR_PORTH (7) /* 0111: PH[x] pin */
#define SYSCFG_EXTICR_PORTI (8) /* 1000: PI[x] pin */ #define SYSCFG_EXTICR_PORTI (8) /* 1000: PI[x] pin */
#define SYSCFG_EXTICR1_EXTI0_SHIFT (0) /* Bits 0-3: EXIT 0 coinfiguration */ #define SYSCFG_EXTICR_PORT_MASK (15)
#define SYSCFG_EXTICR1_EXTI0_MASK (15 << SYSCFG_EXTICR1_EXTI0_SHIFT) #define SYSCFG_EXTICR_EXTI_SHIFT(g) (((g) & 3) << 2)
#define SYSCFG_EXTICR1_EXTI1_SHIFT (0) /* Bits 4-7: EXIT 1 coinfiguration */ #define SYSCFG_EXTICR_EXTI_MASK(g) (SYSCFG_EXTICR_PORT_MASK << (SYSCFG_EXTICR_EXTI_SHIFT(g)))
#define SYSCFG_EXTICR1_EXTI1_MASK (15 << SYSCFG_EXTICR1_EXTI1_SHIFT)
#define SYSCFG_EXTICR1_EXTI2_SHIFT (0) /* Bits 8-11: EXIT 2 coinfiguration */
#define SYSCFG_EXTICR1_EXTI2_MASK (15 << SYSCFG_EXTICR1_EXTI2_SHIFT)
#define SYSCFG_EXTICR1_EXTI3_SHIFT (0) /* Bits 12-15: EXIT 3 coinfiguration */
#define SYSCFG_EXTICR1_EXTI3_MASK (15 << SYSCFG_EXTICR1_EXTI3_SHIFT)
#define SYSCFG_EXTICR2_EXTI4_SHIFT (0) /* Bits 0-3: EXIT 4 coinfiguration */ #define SYSCFG_EXTICR1_EXTI0_SHIFT (0) /* Bits 0-3: EXTI 0 coinfiguration */
#define SYSCFG_EXTICR2_EXTI4_MASK (15 << SYSCFG_EXTICR2_EXTI4_SHIFT) #define SYSCFG_EXTICR1_EXTI0_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI0_SHIFT)
#define SYSCFG_EXTICR2_EXTI5_SHIFT (0) /* Bits 4-7: EXIT 5 coinfiguration */ #define SYSCFG_EXTICR1_EXTI1_SHIFT (4) /* Bits 4-7: EXTI 1 coinfiguration */
#define SYSCFG_EXTICR2_EXTI5_MASK (15 << SYSCFG_EXTICR2_EXTI5_SHIFT) #define SYSCFG_EXTICR1_EXTI1_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI1_SHIFT)
#define SYSCFG_EXTICR2_EXTI6_SHIFT (0) /* Bits 8-11: EXIT 6 coinfiguration */ #define SYSCFG_EXTICR1_EXTI2_SHIFT (8) /* Bits 8-11: EXTI 2 coinfiguration */
#define SYSCFG_EXTICR2_EXTI6_MASK (15 << SYSCFG_EXTICR2_EXTI6_SHIFT) #define SYSCFG_EXTICR1_EXTI2_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI2_SHIFT)
#define SYSCFG_EXTICR2_EXTI7_SHIFT (0) /* Bits 12-15: EXIT 7 coinfiguration */ #define SYSCFG_EXTICR1_EXTI3_SHIFT (12) /* Bits 12-15: EXTI 3 coinfiguration */
#define SYSCFG_EXTICR2_EXTI7_MASK (15 << SYSCFG_EXTICR2_EXTI7_SHIFT) #define SYSCFG_EXTICR1_EXTI3_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI3_SHIFT)
#define SYSCFG_EXTICR3_EXTI8_SHIFT (0) /* Bits 0-3: EXIT 8 coinfiguration */ #define SYSCFG_EXTICR2_EXTI4_SHIFT (0) /* Bits 0-3: EXTI 4 coinfiguration */
#define SYSCFG_EXTICR3_EXTI8_MASK (15 << SYSCFG_EXTICR3_EXTI8_SHIFT) #define SYSCFG_EXTICR2_EXTI4_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI4_SHIFT)
#define SYSCFG_EXTICR3_EXTI9_SHIFT (0) /* Bits 4-7: EXIT 9 coinfiguration */ #define SYSCFG_EXTICR2_EXTI5_SHIFT (4) /* Bits 4-7: EXTI 5 coinfiguration */
#define SYSCFG_EXTICR3_EXTI9_MASK (15 << SYSCFG_EXTICR3_EXTI9_SHIFT) #define SYSCFG_EXTICR2_EXTI5_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI5_SHIFT)
#define SYSCFG_EXTICR3_EXTI10_SHIFT (0) /* Bits 8-11: EXIT 10 coinfiguration */ #define SYSCFG_EXTICR2_EXTI6_SHIFT (8) /* Bits 8-11: EXTI 6 coinfiguration */
#define SYSCFG_EXTICR3_EXTI10_MASK (15 << SYSCFG_EXTICR3_EXTI10_SHIFT) #define SYSCFG_EXTICR2_EXTI6_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI6_SHIFT)
#define SYSCFG_EXTICR3_EXTI11_SHIFT (0) /* Bits 12-15: EXIT 11 coinfiguration */ #define SYSCFG_EXTICR2_EXTI7_SHIFT (12) /* Bits 12-15: EXTI 7 coinfiguration */
#define SYSCFG_EXTICR3_EXTI11_MASK (15 << SYSCFG_EXTICR3_EXTI11_SHIFT) #define SYSCFG_EXTICR2_EXTI7_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI7_SHIFT)
#define SYSCFG_EXTICR4_EXTI12_SHIFT (0) /* Bits 0-3: EXIT 12 coinfiguration */ #define SYSCFG_EXTICR3_EXTI8_SHIFT (0) /* Bits 0-3: EXTI 8 coinfiguration */
#define SYSCFG_EXTICR4_EXTI12_MASK (15 << SYSCFG_EXTICR4_EXTI12_SHIFT) #define SYSCFG_EXTICR3_EXTI8_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI8_SHIFT)
#define SYSCFG_EXTICR4_EXTI13_SHIFT (0) /* Bits 4-7: EXIT 13 coinfiguration */ #define SYSCFG_EXTICR3_EXTI9_SHIFT (4) /* Bits 4-7: EXTI 9 coinfiguration */
#define SYSCFG_EXTICR4_EXTI13_MASK (15 << SYSCFG_EXTICR4_EXTI13_SHIFT) #define SYSCFG_EXTICR3_EXTI9_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI9_SHIFT)
#define SYSCFG_EXTICR4_EXTI14_SHIFT (0) /* Bits 8-11: EXIT 14 coinfiguration */ #define SYSCFG_EXTICR3_EXTI10_SHIFT (8) /* Bits 8-11: EXTI 10 coinfiguration */
#define SYSCFG_EXTICR4_EXTI14_MASK (15 << SYSCFG_EXTICR4_EXTI14_SHIFT) #define SYSCFG_EXTICR3_EXTI10_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI10_SHIFT)
#define SYSCFG_EXTICR4_EXTI15_SHIFT (0) /* Bits 12-15: EXIT 15 coinfiguration */ #define SYSCFG_EXTICR3_EXTI11_SHIFT (12) /* Bits 12-15: EXTI 11 coinfiguration */
#define SYSCFG_EXTICR4_EXTI15_MASK (15 << SYSCFG_EXTICR4_EXTI15_SHIFT) #define SYSCFG_EXTICR3_EXTI11_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI11_SHIFT)
#define SYSCFG_EXTICR4_EXTI12_SHIFT (0) /* Bits 0-3: EXTI 12 coinfiguration */
#define SYSCFG_EXTICR4_EXTI12_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI12_SHIFT)
#define SYSCFG_EXTICR4_EXTI13_SHIFT (4) /* Bits 4-7: EXTI 13 coinfiguration */
#define SYSCFG_EXTICR4_EXTI13_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI13_SHIFT)
#define SYSCFG_EXTICR4_EXTI14_SHIFT (8) /* Bits 8-11: EXTI 14 coinfiguration */
#define SYSCFG_EXTICR4_EXTI14_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI14_SHIFT)
#define SYSCFG_EXTICR4_EXTI15_SHIFT (12) /* Bits 12-15: EXTI 15 coinfiguration */
#define SYSCFG_EXTICR4_EXTI15_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI15_SHIFT)
/* Compensation cell control register */ /* Compensation cell control register */
arch/arm/src/stm32/chip/stm32f10xxx_gpio.h
+1 -1
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@@ -54,7 +54,7 @@
#define STM32_AFIO_EVCR_OFFSET 0x0000 /* Event control register */ #define STM32_AFIO_EVCR_OFFSET 0x0000 /* Event control register */
#define STM32_AFIO_MAPR_OFFSET 0x0004 /* AF remap and debug I/O configuration register */ #define STM32_AFIO_MAPR_OFFSET 0x0004 /* AF remap and debug I/O configuration register */
#define STM32_AFIO_EXTICR_OFFSET(p) (0x0008 + ((p) & 0xC)) /* Registers are displaced by 4! */ #define STM32_AFIO_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */
#define STM32_AFIO_EXTICR1_OFFSET 0x0008 /* External interrupt configuration register 1 */ #define STM32_AFIO_EXTICR1_OFFSET 0x0008 /* External interrupt configuration register 1 */
#define STM32_AFIO_EXTICR2_OFFSET 0x000c /* External interrupt configuration register 2 */ #define STM32_AFIO_EXTICR2_OFFSET 0x000c /* External interrupt configuration register 2 */
#define STM32_AFIO_EXTICR3_OFFSET 0x0010 /* External interrupt configuration register 3 */ #define STM32_AFIO_EXTICR3_OFFSET 0x0010 /* External interrupt configuration register 3 */
arch/arm/src/stm32/stm32_gpio.c
+352 -175
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File diff suppressed because it is too large Load Diff
arch/arm/src/stm32/stm32_gpio.h
+1 -1
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@@ -307,7 +307,7 @@ extern "C" {
* .... .... ..O. .... .... * .... .... ..O. .... ....
*/ */
#define GPIO_OPENDRAM (1 << 9) /* Bit9: 1=Open-drain output */ #define GPIO_OPENDRAIN (1 << 9) /* Bit9: 1=Open-drain output */
#define GPIO_PUSHPULL (0) /* Bit9: 0=Push-pull output */ #define GPIO_PUSHPULL (0) /* Bit9: 0=Push-pull output */
/* If the pin is a GPIO digital output, then this identifies the initial output value. /* If the pin is a GPIO digital output, then this identifies the initial output value.