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Fix nxstyle warnings

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This commit is contained in:
Yoshinori Sugino
2020-09-28 12:43:13 +09:00
committed by Xiang Xiao
parent 698008d1e5
commit 5bb4eb39f2
10 changed files with 59 additions and 39 deletions
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arch/misoc/src/lm32/lm32_schedulesigaction.c
-1
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@@ -155,7 +155,6 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
g_current_regs[REG_EPC] = (uint32_t)lm32_sigdeliver;
g_current_regs[REG_INT_CTX] = 0;
/* And make sure that the saved context in the TCB
* is the same as the interrupt return context.
*/
arch/misoc/src/minerva/minerva_schedulesigaction.c
+11 -8
View File
@@ -133,16 +133,16 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
*
* Hmmm... there looks like a latent bug here: The following logic
* would fail in the strange case where we are in an interrupt
* handler, the thread is signalling itself, but a context switch to
* another task has occurred so that g_current_regs does not refer
* to the thread of this_task()!
* handler, the thread is signalling itself, but a context switch
* to another task has occurred so that g_current_regs does not
* refer to the thread of this_task()!
*/
else
{
/* Save the return EPC and STATUS registers. These will be
* restored by the signal trampoline after the signals have been
* delivered.
* restored by the signal trampoline after the signals have
* been delivered.
*/
tcb->xcp.sigdeliver = sigdeliver;
@@ -175,15 +175,18 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
else
{
/* Save the return EPC and STATUS registers. These will be restored
* by the signal trampoline after the signals have been delivered.
/* Save the return EPC and STATUS registers. These will be
* restored by the signal trampoline after the signals have been
* delivered.
*/
tcb->xcp.sigdeliver = sigdeliver;
tcb->xcp.saved_epc = tcb->xcp.regs[REG_CSR_MEPC];
tcb->xcp.saved_int_ctx = tcb->xcp.regs[REG_CSR_MSTATUS];
/* Then set up to vector to the trampoline with interrupts disabled */
/* Then set up to vector to the trampoline with interrupts
* disabled
*/
tcb->xcp.regs[REG_CSR_MEPC] = (uint32_t) minerva_sigdeliver;
g_current_regs[REG_CSR_MSTATUS] &= ~CSR_MSTATUS_MIE;