diff --git a/ChangeLog b/ChangeLog
index d4085fd5db2..10c9ed34b60 100755
--- a/ChangeLog
+++ b/ChangeLog
@@ -12045,3 +12045,75 @@
 	    - escape LASTXFER: this suppresses the LASTXFER bit at the end of the
 	      next transfer. The "escape"-Flag is reset automatically.
 	  From Frank Benkert (2016-06-14)
+	* Many CONFIG_DEBUG_* options did not have matching macros defined in
+	  include/debug.h.  Rather, there were various definitions scattered
+	  throughout the sourse tree.  These were collected together and
+	  centralized with single macro definitions in include/debug.h
+	  (2016-06-15)
+	* STM32F7: Add SPI, I2C, and ADC drivers.  From Lok Tep (2016-06-15).
+	* err(), warn(), info(), and alert() renamed to include leading '_'.
+	  This was done to avoid some naming collisions (2-06-16
+	* STM32: Move backup domain reset to to earlier in the initialization
+	  sequence (stm32_rcc.c() in order to avoid disabling LSE during RTC
+	  initialiation.  From Alan Carvalho de Assis (2016-06-16).
+	* SYSLOG: syslog() will now automatically redirect output to lowsyslog()
+	  if called from an interrupt handler (2016-06-16).
+	* STM32: When configuring a GPIO via stm32_configgpio() the function
+	  will first set the mode to output and then set the initial state of
+	  the gpio later on.  If you have an application with an externaly
+	  pulled-up pin, this would lead to a glitch on the line that may be
+	  dangerous in some applications (e.G. Reset Line for other chips,
+	  etc).  This changes sets the output state before configuring the pin
+	  as an output.  From Pascal Speck  (2016-06-17).
+	* STM32 F7: Apply Pascal Speck's GPIO STM32 change to STM32 L4
+	  (2016-06-17).
+	* STM32 L4: Apply Pascal Speck's GPIO STM32 change to STM32 L4.
+	  From Sebastien Lorquet (2016-06-17).
+	* Review all uses of *err().  These macro family should indicate only
+	  error conditions.  Convert *err() to either *info() or add ERROR:,
+	  depending on if an error is reported (2016-06-17).
+	* STM32F7: Review, correct, and update I2C, SPI, and ADC drivers.  From
+	  David Sidrane (2016-06-17).
+	* LPC17 Ethernet:  Needs to correctly ignore PHYID2 revision number
+	  when comparing PHY IDs (2016-06-18).
+	* SYSLOG: Consolidate all SYSLOG logic in drivers/syslog.  Add an
+	  abstraction layer that supports:  (1) redirection of SYSLOG outpout.
+	  This is usually so that you can boot with one SYSLOG output but
+	  transition to another SYSLOG output when the OS has initialialized,
+	  (2) adds common serialization of interrupt output as a configuration
+	  option.  Without this configuration setting, interrupt level output
+	  will be asynchronous.  And (3) vsyslog is now a system call and is
+	  usable with other-than-FLAT builds (2016-06-19).
+	* TCP Networking: While working with version 7.10 I discovered a
+	  problem in TCP stack that could be observed on high network load.
+	  Generally speaking, the problem is that RST flag is set in
+	  unnecessary case, in which between loss of some TCP packet and its
+	  proper retransmission, another packets had been successfully sent.
+	  The scenario is as follows:  NuttX did not receive ACK for some
+	  sent packet, so it has been probably lost somewhere. But before
+	  its retransmission starts, NuttX is correctly issuing next TCP
+	  packets, with sequence numbers increasing properly. When the
+	  retransmission of previously lost packet finally succeeds, tcp_input
+	  receives the accumulated ACK value, which acknowledges also the
+	  packets sent in the meantime (i.e. between unsuccessful sending of
+	  lost packet and its proper retransmission). However, variable unackseq
+	  is still set to conn->isn + conn->sent, which is truth only if no
+	  further packets transmission occurred in the meantime.  Because of
+	  incorrect (in such specific case) unackseq value, few lines further
+	  condition if (ackseq <= unackseq)is not met, and, as a result, we
+	  are going to reset label.  From  Jakub Łągwa (2016-06-20).
+	* SYSLOG: Remove lowsyslog(), vlowsyslog(), and associated macros
+	  *llinfo(), *llwarn(), and llerr().  In the redesigned syslog() logic,
+	  these serve no purpose (2016-06-20).
+	* Make system: Need to build the drivers/ directory even it file
+	  descriptors are not supported.  There are things in the drivers/
+	  directory that are still needed (like SYSLOG logic) (2016-06-20).
+	* assert.h: Define static assert for C++ usage.  From Paul Alexander
+	  Patience (2016-06-21).
+	* arch/arm/src/stm32l4:  Add ioctls to set/get bit timing in stm32l4.
+	  Add ioctl hooks to allow future management of can id filters. From
+	  Sebastien Lorquet (2016-06-21).
+	* drivers/can.c:  Add support for poll. From Paul Alexander Patience
+	  (2016-06-21).
+	* drivers/syslog: Extend SYSLOG logic so that we can send SYSLOG output
+	  to a file.  Not verified on initial commit  (2016-06-21).
diff --git a/Directories.mk b/Directories.mk
index 6eeedc79e8a..2e42a8a435f 100644
--- a/Directories.mk
+++ b/Directories.mk
@@ -59,7 +59,10 @@ endif
 #
 # FSDIRS depend on file descriptor support; NONFSDIRS do not (except for parts
 #   of FSDIRS).  We will exclude FSDIRS from the build if file descriptor
-#   support is disabled
+#   support is disabled.  NOTE that drivers, in general, depends on file
+#   descriptor support but is always built because there are other components
+#   in the drivers directory that are needed even if file descriptors are not
+#   supported.
 # CONTEXTDIRS include directories that have special, one-time pre-build
 #   requirements.  Normally this includes things like auto-generation of
 #   configuration specific files or creation of configurable symbolic links
@@ -69,8 +72,8 @@ endif
 #   be cleaned to prevent garbage from collecting in them when changing
 #   configurations.
 
-NONFSDIRS = sched configs $(ARCH_SRC) $(NUTTX_ADDONS)
-FSDIRS = fs drivers binfmt
+NONFSDIRS = sched drivers configs $(ARCH_SRC) $(NUTTX_ADDONS)
+FSDIRS = fs binfmt
 CONTEXTDIRS = $(APPDIR)
 USERDIRS =
 OTHERDIRS = lib
diff --git a/FlatLibs.mk b/FlatLibs.mk
index 13dcc6c3400..69fe6a9fa06 100644
--- a/FlatLibs.mk
+++ b/FlatLibs.mk
@@ -45,6 +45,12 @@
 NUTTXLIBS = lib$(DELIM)libsched$(LIBEXT)
 USERLIBS =
 
+# Driver support.  Generally depends on file descriptor support but there
+# are some components in the drivers directory that are needed even if file
+# descriptors are not supported.
+
+NUTTXLIBS += lib$(DELIM)libdrivers$(LIBEXT)
+
 # Add libraries for board support
 
 NUTTXLIBS += lib$(DELIM)libconfigs$(LIBEXT)
@@ -89,11 +95,8 @@ ifeq ($(CONFIG_NFILE_DESCRIPTORS),0)
 ifneq ($(CONFIG_NSOCKET_DESCRIPTORS),0)
 NUTTXLIBS += lib$(DELIM)libfs$(LIBEXT)
 endif
-ifeq ($(CONFIG_NET),y)
-NUTTXLIBS += lib$(DELIM)libdrivers$(LIBEXT)
-endif
 else
-NUTTXLIBS += lib$(DELIM)libfs$(LIBEXT) lib$(DELIM)libdrivers$(LIBEXT) lib$(DELIM)libbinfmt$(LIBEXT)
+NUTTXLIBS += lib$(DELIM)libfs$(LIBEXT) lib$(DELIM)libbinfmt$(LIBEXT)
 endif
 
 # Add libraries for the NX graphics sub-system
diff --git a/Kconfig b/Kconfig
index 7e9ae4eed3c..c174c16e4cb 100644
--- a/Kconfig
+++ b/Kconfig
@@ -395,9 +395,14 @@ endmenu # Customize Header Files
 
 menu "Debug Options"
 
+config DEBUG_ALERT
+	bool
+	default n
+
 config DEBUG_FEATURES
 	bool "Enable Debug Features"
 	default n
+	select DEBUG_ALERT
 	---help---
 		Enables built-in debug features.  Selecting this option will (1) Enable
 		debug assertions in the code, (2) enable extended parameter testing in
diff --git a/KernelLibs.mk b/KernelLibs.mk
index a7888d714dc..719430b6c9b 100644
--- a/KernelLibs.mk
+++ b/KernelLibs.mk
@@ -45,6 +45,12 @@
 NUTTXLIBS = lib$(DELIM)libsched$(LIBEXT)
 USERLIBS =
 
+# Driver support.  Generally depends on file descriptor support but there
+# are some components in the drivers directory that are needed even if file
+# descriptors are not supported.
+
+NUTTXLIBS += lib$(DELIM)libdrivers$(LIBEXT)
+
 # Add libraries for board support
 
 NUTTXLIBS += lib$(DELIM)libconfigs$(LIBEXT)
@@ -83,11 +89,8 @@ ifeq ($(CONFIG_NFILE_DESCRIPTORS),0)
 ifneq ($(CONFIG_NSOCKET_DESCRIPTORS),0)
 NUTTXLIBS += lib$(DELIM)libfs$(LIBEXT)
 endif
-ifeq ($(CONFIG_NET),y)
-NUTTXLIBS += lib$(DELIM)libdrivers$(LIBEXT)
-endif
 else
-NUTTXLIBS += lib$(DELIM)libfs$(LIBEXT) lib$(DELIM)libdrivers$(LIBEXT) lib$(DELIM)libbinfmt$(LIBEXT)
+NUTTXLIBS += lib$(DELIM)libfs$(LIBEXT) lib$(DELIM)libbinfmt$(LIBEXT)
 endif
 
 # Add libraries for the NX graphics sub-system
diff --git a/ProtectedLibs.mk b/ProtectedLibs.mk
index 70185eacf47..4f2e2c6072d 100644
--- a/ProtectedLibs.mk
+++ b/ProtectedLibs.mk
@@ -45,6 +45,12 @@
 NUTTXLIBS = lib$(DELIM)libsched$(LIBEXT)
 USERLIBS =
 
+# Driver support.  Generally depends on file descriptor support but there
+# are some components in the drivers directory that are needed even if file
+# descriptors are not supported.
+
+NUTTXLIBS += lib$(DELIM)libdrivers$(LIBEXT)
+
 # Add libraries for board support
 
 NUTTXLIBS += lib$(DELIM)libconfigs$(LIBEXT)
@@ -89,11 +95,8 @@ ifeq ($(CONFIG_NFILE_DESCRIPTORS),0)
 ifneq ($(CONFIG_NSOCKET_DESCRIPTORS),0)
 NUTTXLIBS += lib$(DELIM)libfs$(LIBEXT)
 endif
-ifeq ($(CONFIG_NET),y)
-NUTTXLIBS += lib$(DELIM)libdrivers$(LIBEXT)
-endif
 else
-NUTTXLIBS += lib$(DELIM)libfs$(LIBEXT) lib$(DELIM)libdrivers$(LIBEXT) lib$(DELIM)libbinfmt$(LIBEXT)
+NUTTXLIBS += lib$(DELIM)libfs$(LIBEXT) lib$(DELIM)libbinfmt$(LIBEXT)
 endif
 
 # Add libraries for the NX graphics sub-system
diff --git a/arch/Kconfig b/arch/Kconfig
index fd61f2fbf55..fa5bf48edaa 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -58,6 +58,7 @@ config ARCH_SIM
 	select ARCH_HAVE_TLS
 	select ARCH_HAVE_TICKLESS
 	select ARCH_HAVE_POWEROFF
+	select SERIAL_CONSOLE
 	---help---
 		Linux/Cywgin user-mode simulation.
 
@@ -525,6 +526,7 @@ config ARCH_IRQPRIO
 config ARCH_STACKDUMP
 	bool "Dump stack on assertions"
 	default n
+	select DEBUG_ALERT
 	---help---
 		Enable to do stack dumps after assertions
 
diff --git a/arch/arm/include/stm32f7/chip.h b/arch/arm/include/stm32f7/chip.h
index d30937541e8..b3beb4e09e8 100644
--- a/arch/arm/include/stm32f7/chip.h
+++ b/arch/arm/include/stm32f7/chip.h
@@ -2,7 +2,8 @@
  * arch/arm/include/stm32f7/chip.h
  *
  *   Copyright (C) 2015-2016 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *   Authors: Gregory Nutt <gnutt@nuttx.org>
+ *            David Sidrane <david_s5@nscdg.com>
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
diff --git a/arch/arm/src/a1x/a1x_serial.c b/arch/arm/src/a1x/a1x_serial.c
index 8c28eabb37c..7dae40aa997 100644
--- a/arch/arm/src/a1x/a1x_serial.c
+++ b/arch/arm/src/a1x/a1x_serial.c
@@ -1192,7 +1192,7 @@ static int uart_interrupt(struct uart_dev_s *dev)
 
           default:
             {
-              _llerr("Unexpected IIR: %02x\n", status);
+              _err("ERROR: Unexpected IIR: %02x\n", status);
               break;
             }
         }
diff --git a/arch/arm/src/arm/up_assert.c b/arch/arm/src/arm/up_assert.c
index 27788451daf..3d188174b3d 100644
--- a/arch/arm/src/arm/up_assert.c
+++ b/arch/arm/src/arm/up_assert.c
@@ -151,7 +151,7 @@ static int usbtrace_syslog(FAR const char *fmt, ...)
   /* Let vsyslog do the real work */
 
   va_start(ap, fmt);
-  ret = lowvsyslog(LOG_INFO, fmt, ap);
+  ret = vsyslog(LOG_EMERG, fmt, ap);
   va_end(ap);
   return ret;
 }
@@ -311,7 +311,7 @@ static void _up_assert(int errorcode)
 
 void up_assert(const uint8_t *filename, int lineno)
 {
-#if CONFIG_TASK_NAME_SIZE > 0
+#if CONFIG_TASK_NAME_SIZE > 0 && defined(CONFIG_DEBUG_ALERT)
   struct tcb_s *rtcb = this_task();
 #endif
 
diff --git a/arch/arm/src/arm/up_dataabort.c b/arch/arm/src/arm/up_dataabort.c
index 926352fac4e..318c59232c4 100644
--- a/arch/arm/src/arm/up_dataabort.c
+++ b/arch/arm/src/arm/up_dataabort.c
@@ -107,7 +107,7 @@ void up_dataabort(uint32_t *regs, uint32_t far, uint32_t fsr)
    * fatal error.
    */
 
-  pgllerr("FSR: %08x FAR: %08x\n", fsr, far);
+  pginfo("FSR: %08x FAR: %08x\n", fsr, far);
   if ((fsr & FSR_MASK) != FSR_PAGE)
     {
       goto segfault;
@@ -118,7 +118,7 @@ void up_dataabort(uint32_t *regs, uint32_t far, uint32_t fsr)
    * (It has not yet been saved in the register context save area).
    */
 
-  pgllinfo("VBASE: %08x VEND: %08x\n", PG_PAGED_VBASE, PG_PAGED_VEND);
+  pginfo("VBASE: %08x VEND: %08x\n", PG_PAGED_VBASE, PG_PAGED_VEND);
   if (far < PG_PAGED_VBASE || far >= PG_PAGED_VEND)
     {
       goto segfault;
diff --git a/arch/arm/src/arm/up_elf.c b/arch/arm/src/arm/up_elf.c
index 06c0c5157c1..c6d88bdc325 100644
--- a/arch/arm/src/arm/up_elf.c
+++ b/arch/arm/src/arm/up_elf.c
@@ -86,7 +86,7 @@ bool up_checkarch(FAR const Elf32_Ehdr *ehdr)
 
   if (ehdr->e_machine != EM_ARM)
     {
-      berr("Not for ARM: e_machine=%04x\n", ehdr->e_machine);
+      berr("ERROR: Not for ARM: e_machine=%04x\n", ehdr->e_machine);
       return -ENOEXEC;
     }
 
@@ -94,7 +94,7 @@ bool up_checkarch(FAR const Elf32_Ehdr *ehdr)
 
   if (ehdr->e_ident[EI_CLASS] != ELFCLASS32)
     {
-      berr("Need 32-bit objects: e_ident[EI_CLASS]=%02x\n", ehdr->e_ident[EI_CLASS]);
+      berr("ERROR: Need 32-bit objects: e_ident[EI_CLASS]=%02x\n", ehdr->e_ident[EI_CLASS]);
       return -ENOEXEC;
     }
 
@@ -106,7 +106,7 @@ bool up_checkarch(FAR const Elf32_Ehdr *ehdr)
   if (ehdr->e_ident[EI_DATA] != ELFDATA2LSB)
 #endif
     {
-      berr("Wrong endian-ness: e_ident[EI_DATA]=%02x\n", ehdr->e_ident[EI_DATA]);
+      berr("ERROR: Wrong endian-ness: e_ident[EI_DATA]=%02x\n", ehdr->e_ident[EI_DATA]);
       return -ENOEXEC;
     }
 
@@ -114,7 +114,7 @@ bool up_checkarch(FAR const Elf32_Ehdr *ehdr)
 
   if ((ehdr->e_entry & 3) != 0)
     {
-      berr("Entry point is not properly aligned: %08x\n", ehdr->e_entry);
+      berr("ERROR: Entry point is not properly aligned: %08x\n", ehdr->e_entry);
       return -ENOEXEC
     }
 
@@ -185,7 +185,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
         offset += sym->st_value - addr;
         if (offset & 3 || offset <= (int32_t) 0xfe000000 || offset >= (int32_t) 0x02000000)
           {
-            berr("  ERROR: PC24 [%d] relocation out of range, offset=%08lx\n",
+            berr("ERROR: PC24 [%d] relocation out of range, offset=%08lx\n",
                  ELF32_R_TYPE(rel->r_info), offset);
 
             return -EINVAL;
@@ -256,7 +256,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
       break;
 
     default:
-      berr("Unsupported relocation: %d\n", ELF32_R_TYPE(rel->r_info));
+      berr("ERROR: Unsupported relocation: %d\n", ELF32_R_TYPE(rel->r_info));
       return -EINVAL;
     }
 
@@ -266,6 +266,6 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
 int up_relocateadd(FAR const Elf32_Rela *rel, FAR const Elf32_Sym *sym,
                    uintptr_t addr)
 {
-  berr("RELA relocation not supported\n");
+  berr("ERROR: RELA relocation not supported\n");
   return -ENOSYS;
 }
diff --git a/arch/arm/src/arm/up_prefetchabort.c b/arch/arm/src/arm/up_prefetchabort.c
index 070c1ce5d2e..ab97efd5737 100644
--- a/arch/arm/src/arm/up_prefetchabort.c
+++ b/arch/arm/src/arm/up_prefetchabort.c
@@ -99,8 +99,8 @@ void up_prefetchabort(uint32_t *regs)
    * virtual addresses.
    */
 
-  pgllerr("VADDR: %08x VBASE: %08x VEND: %08x\n",
-          regs[REG_PC], PG_PAGED_VBASE, PG_PAGED_VEND);
+  pginfo("VADDR: %08x VBASE: %08x VEND: %08x\n",
+         regs[REG_PC], PG_PAGED_VBASE, PG_PAGED_VEND);
 
   if (regs[REG_R15] >= PG_PAGED_VBASE && regs[REG_R15] < PG_PAGED_VEND)
     {
diff --git a/arch/arm/src/arm/up_releasepending.c b/arch/arm/src/arm/up_releasepending.c
index 99bf93f6f7f..c0ee7e6e727 100644
--- a/arch/arm/src/arm/up_releasepending.c
+++ b/arch/arm/src/arm/up_releasepending.c
@@ -67,7 +67,7 @@ void up_release_pending(void)
 {
   struct tcb_s *rtcb = this_task();
 
-  sllerr("From TCB=%p\n", rtcb);
+  sinfo("From TCB=%p\n", rtcb);
 
   /* Merge the g_pendingtasks list into the ready-to-run task list */
 
diff --git a/arch/arm/src/arm/up_reprioritizertr.c b/arch/arm/src/arm/up_reprioritizertr.c
index 7d6015cccb9..95679e31dd7 100644
--- a/arch/arm/src/arm/up_reprioritizertr.c
+++ b/arch/arm/src/arm/up_reprioritizertr.c
@@ -95,7 +95,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority)
       struct tcb_s *rtcb = this_task();
       bool switch_needed;
 
-      sllerr("TCB=%p PRI=%d\n", tcb, priority);
+      sinfo("TCB=%p PRI=%d\n", tcb, priority);
 
       /* Remove the tcb task from the ready-to-run list.
        * sched_removereadytorun will return true if we just
diff --git a/arch/arm/src/arm/up_schedulesigaction.c b/arch/arm/src/arm/up_schedulesigaction.c
index 5b99b2059a0..f6f0c655e8f 100644
--- a/arch/arm/src/arm/up_schedulesigaction.c
+++ b/arch/arm/src/arm/up_schedulesigaction.c
@@ -94,7 +94,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
 {
   irqstate_t flags;
 
-  serr("tcb=0x%p sigdeliver=0x%p\n", tcb, sigdeliver);
+  sinfo("tcb=0x%p sigdeliver=0x%p\n", tcb, sigdeliver);
 
   /* Make sure that interrupts are disabled */
 
@@ -108,7 +108,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
        * being delivered to the currently executing task.
        */
 
-      serr("rtcb=0x%p CURRENT_REGS=0x%p\n", this_task(), CURRENT_REGS);
+      sinfo("rtcb=0x%p CURRENT_REGS=0x%p\n", this_task(), CURRENT_REGS);
 
       if (tcb == this_task())
         {
diff --git a/arch/arm/src/arm/up_sigdeliver.c b/arch/arm/src/arm/up_sigdeliver.c
index 0b3b6ea266f..29176429f3c 100644
--- a/arch/arm/src/arm/up_sigdeliver.c
+++ b/arch/arm/src/arm/up_sigdeliver.c
@@ -95,7 +95,7 @@ void up_sigdeliver(void)
 
   board_autoled_on(LED_SIGNAL);
 
-  serr("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n",
+  sinfo("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n",
         rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head);
   ASSERT(rtcb->xcp.sigdeliver != NULL);
 
@@ -126,7 +126,7 @@ void up_sigdeliver(void)
    * errno that is needed by the user logic (it is probably EINTR).
    */
 
-  serr("Resuming\n");
+  sinfo("Resuming\n");
   (void)up_irq_save();
   rtcb->pterrno = saved_errno;
 
diff --git a/arch/arm/src/armv6-m/up_assert.c b/arch/arm/src/armv6-m/up_assert.c
index 93ff4a9f6fb..f218cd477b0 100644
--- a/arch/arm/src/armv6-m/up_assert.c
+++ b/arch/arm/src/armv6-m/up_assert.c
@@ -193,7 +193,7 @@ static int usbtrace_syslog(FAR const char *fmt, ...)
   /* Let vsyslog do the real work */
 
   va_start(ap, fmt);
-  ret = lowvsyslog(LOG_INFO, fmt, ap);
+  ret = vsyslog(LOG_EMERG, fmt, ap);
   va_end(ap);
   return ret;
 }
@@ -366,7 +366,7 @@ static void _up_assert(int errorcode)
 
 void up_assert(const uint8_t *filename, int lineno)
 {
-#if CONFIG_TASK_NAME_SIZE > 0
+#if CONFIG_TASK_NAME_SIZE > 0 && defined(CONFIG_DEBUG_ALERT)
   struct tcb_s *rtcb = this_task();
 #endif
 
diff --git a/arch/arm/src/armv6-m/up_dumpnvic.c b/arch/arm/src/armv6-m/up_dumpnvic.c
index ba4974a0ac0..8439ac6a2a9 100644
--- a/arch/arm/src/armv6-m/up_dumpnvic.c
+++ b/arch/arm/src/armv6-m/up_dumpnvic.c
@@ -72,27 +72,27 @@ void up_dumpnvic(FAR const char *msg)
 
   flags = enter_critical_section();
 
-  _llinfo("NVIC: %s\n", msg);
-  _llinfo("   ISER: %08x  ICER: %08x  ISPR: %08x  ICPR: %08x\n",
-         getreg32(ARMV6M_NVIC_ISER), getreg32(ARMV6M_NVIC_ICER),
-         getreg32(ARMV6M_NVIC_ISPR), getreg32(ARMV6M_NVIC_ICPR));
+  _info("NVIC: %s\n", msg);
+  _info("   ISER: %08x  ICER: %08x  ISPR: %08x  ICPR: %08x\n",
+       getreg32(ARMV6M_NVIC_ISER), getreg32(ARMV6M_NVIC_ICER),
+       getreg32(ARMV6M_NVIC_ISPR), getreg32(ARMV6M_NVIC_ICPR));
 
   for (i = 0 ; i < 8; i += 4)
     {
-      _llinfo("   IPR%d: %08x  IPR%d: %08x  IPR%d: %08x  IPR%d: %08x\n",
-             i,   getreg32(ARMV6M_NVIC_IPR(i)),
-             i+1, getreg32(ARMV6M_NVIC_IPR(i+1)),
-             i+2, getreg32(ARMV6M_NVIC_IPR(i+2)),
-             i+3, getreg32(ARMV6M_NVIC_IPR(i+3)));
+      _info("   IPR%d: %08x  IPR%d: %08x  IPR%d: %08x  IPR%d: %08x\n",
+           i,   getreg32(ARMV6M_NVIC_IPR(i)),
+           i+1, getreg32(ARMV6M_NVIC_IPR(i+1)),
+           i+2, getreg32(ARMV6M_NVIC_IPR(i+2)),
+           i+3, getreg32(ARMV6M_NVIC_IPR(i+3)));
     }
 
-  _llinfo("SYSCON:\n");
-  _llinfo("  CPUID: %08x  ICSR: %08x AIRCR: %08x   SCR: %08x\n",
-         getreg32(ARMV6M_SYSCON_CPUID), getreg32(ARMV6M_SYSCON_ICSR),
-         getreg32(ARMV6M_SYSCON_AIRCR), getreg32(ARMV6M_SYSCON_SCR));
-  _llinfo("    CCR: %08x SHPR2: %08x SHPR3: %08x\n",
-         getreg32(ARMV6M_SYSCON_CCR),   getreg32(ARMV6M_SYSCON_SHPR2),
-         getreg32(ARMV6M_SYSCON_SHPR3));
+  _info("SYSCON:\n");
+  _info("  CPUID: %08x  ICSR: %08x AIRCR: %08x   SCR: %08x\n",
+       getreg32(ARMV6M_SYSCON_CPUID), getreg32(ARMV6M_SYSCON_ICSR),
+       getreg32(ARMV6M_SYSCON_AIRCR), getreg32(ARMV6M_SYSCON_SCR));
+  _info("    CCR: %08x SHPR2: %08x SHPR3: %08x\n",
+       getreg32(ARMV6M_SYSCON_CCR),   getreg32(ARMV6M_SYSCON_SHPR2),
+       getreg32(ARMV6M_SYSCON_SHPR3));
 
   leave_critical_section(flags);
 #endif
diff --git a/arch/arm/src/armv6-m/up_elf.c b/arch/arm/src/armv6-m/up_elf.c
index ad0b4d8dad3..7bde5d01106 100644
--- a/arch/arm/src/armv6-m/up_elf.c
+++ b/arch/arm/src/armv6-m/up_elf.c
@@ -86,7 +86,7 @@ bool up_checkarch(FAR const Elf32_Ehdr *ehdr)
 
   if (ehdr->e_machine != EM_ARM)
     {
-      berr("Not for ARM: e_machine=%04x\n", ehdr->e_machine);
+      berr("ERROR: Not for ARM: e_machine=%04x\n", ehdr->e_machine);
       return -ENOEXEC;
     }
 
@@ -94,7 +94,7 @@ bool up_checkarch(FAR const Elf32_Ehdr *ehdr)
 
   if (ehdr->e_ident[EI_CLASS] != ELFCLASS32)
     {
-      berr("Need 32-bit objects: e_ident[EI_CLASS]=%02x\n", ehdr->e_ident[EI_CLASS]);
+      berr("ERROR: Need 32-bit objects: e_ident[EI_CLASS]=%02x\n", ehdr->e_ident[EI_CLASS]);
       return -ENOEXEC;
     }
 
@@ -106,7 +106,7 @@ bool up_checkarch(FAR const Elf32_Ehdr *ehdr)
   if (ehdr->e_ident[EI_DATA] != ELFDATA2LSB)
 #endif
     {
-      berr("Wrong endian-ness: e_ident[EI_DATA]=%02x\n", ehdr->e_ident[EI_DATA]);
+      berr("ERROR: Wrong endian-ness: e_ident[EI_DATA]=%02x\n", ehdr->e_ident[EI_DATA]);
       return -ENOEXEC;
     }
 
@@ -181,7 +181,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
         offset += sym->st_value - addr;
         if (offset & 3 || offset <= (int32_t) 0xfe000000 || offset >= (int32_t) 0x02000000)
           {
-            berr("  ERROR: PC24 [%d] relocation out of range, offset=%08lx\n",
+            berr("ERROR:   ERROR: PC24 [%d] relocation out of range, offset=%08lx\n",
                  ELF32_R_TYPE(rel->r_info), offset);
 
             return -EINVAL;
@@ -290,7 +290,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
 
         if (ELF32_ST_TYPE(sym->st_info) == STT_FUNC && (offset & 1) == 0)
           {
-            berr("  ERROR: JUMP24 [%d] requires odd offset, offset=%08lx\n",
+            berr("ERROR:   ERROR: JUMP24 [%d] requires odd offset, offset=%08lx\n",
                  ELF32_R_TYPE(rel->r_info), offset);
 
             return -EINVAL;
@@ -300,7 +300,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
 
         if (offset <= (int32_t)0xff000000 || offset >= (int32_t)0x01000000)
           {
-            berr("  ERROR: JUMP24 [%d] relocation out of range, branch taget=%08lx\n",
+            berr("ERROR:   ERROR: JUMP24 [%d] relocation out of range, branch taget=%08lx\n",
                  ELF32_R_TYPE(rel->r_info), offset);
 
             return -EINVAL;
@@ -451,7 +451,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
       break;
 
     default:
-      berr("Unsupported relocation: %d\n", ELF32_R_TYPE(rel->r_info));
+      berr("ERROR: Unsupported relocation: %d\n", ELF32_R_TYPE(rel->r_info));
       return -EINVAL;
     }
 
@@ -461,6 +461,6 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
 int up_relocateadd(FAR const Elf32_Rela *rel, FAR const Elf32_Sym *sym,
                    uintptr_t addr)
 {
-  berr("RELA relocation not supported\n");
+  berr("ERROR: RELA relocation not supported\n");
   return -ENOSYS;
 }
diff --git a/arch/arm/src/armv6-m/up_hardfault.c b/arch/arm/src/armv6-m/up_hardfault.c
index ef5c59ba2ed..b3c24d88515 100644
--- a/arch/arm/src/armv6-m/up_hardfault.c
+++ b/arch/arm/src/armv6-m/up_hardfault.c
@@ -55,9 +55,9 @@
  ****************************************************************************/
 
 #ifdef CONFIG_DEBUG_HARDFAULT
-# define hferr(format, ...)  _llerr(format, ##__VA_ARGS__)
+# define hfinfo(format, ...)  _alert(format, ##__VA_ARGS__)
 #else
-# define hferr(x...)
+# define hfinfo(x...)
 #endif
 
 #define INSN_SVC0        0xdf00 /* insn: svc 0 */
@@ -106,7 +106,7 @@ int up_hardfault(int irq, FAR void *context)
       /* Fetch the instruction that caused the Hard fault */
 
       uint16_t insn = *pc;
-      hferr("  PC: %p INSN: %04x\n", pc, insn);
+      hfinfo("  PC: %p INSN: %04x\n", pc, insn);
 
       /* If this was the instruction 'svc 0', then forward processing
        * to the SVCall handler
@@ -114,7 +114,7 @@ int up_hardfault(int irq, FAR void *context)
 
       if (insn == INSN_SVC0)
         {
-          hferr("Forward SVCall\n");
+          hfinfo("Forward SVCall\n");
           return up_svcall(irq, context);
         }
     }
@@ -122,22 +122,22 @@ int up_hardfault(int irq, FAR void *context)
 #if defined(CONFIG_DEBUG_HARDFAULT)
   /* Dump some hard fault info */
 
-  hferr("\nHard Fault:\n");
-  hferr("  IRQ: %d regs: %p\n", irq, regs);
-  hferr("  PRIMASK: %08x IPSR: %08x\n",
-        getprimask(), getipsr());
-  hferr("  R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
-        regs[REG_R0],  regs[REG_R1],  regs[REG_R2],  regs[REG_R3],
-        regs[REG_R4],  regs[REG_R5],  regs[REG_R6],  regs[REG_R7]);
-  hferr("  R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
-        regs[REG_R8],  regs[REG_R9],  regs[REG_R10], regs[REG_R11],
-        regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
-  hferr("  xPSR: %08x PRIMASK: %08x (saved)\n",
-        CURRENT_REGS[REG_XPSR],  CURRENT_REGS[REG_PRIMASK]);
+  _alert("\nHard Fault:\n");
+  _alert("  IRQ: %d regs: %p\n", irq, regs);
+  _alert("  PRIMASK: %08x IPSR: %08x\n",
+         getprimask(), getipsr());
+  _alert("  R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+         regs[REG_R0],  regs[REG_R1],  regs[REG_R2],  regs[REG_R3],
+         regs[REG_R4],  regs[REG_R5],  regs[REG_R6],  regs[REG_R7]);
+  _alert("  R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+         regs[REG_R8],  regs[REG_R9],  regs[REG_R10], regs[REG_R11],
+         regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
+  _alert("  xPSR: %08x PRIMASK: %08x (saved)\n",
+         CURRENT_REGS[REG_XPSR],  CURRENT_REGS[REG_PRIMASK]);
 #endif
 
   (void)up_irq_save();
-  _llerr("PANIC!!! Hard fault\n");
+  _alert("PANIC!!! Hard fault\n");
   PANIC();
   return OK; /* Won't get here */
 }
diff --git a/arch/arm/src/armv6-m/up_releasepending.c b/arch/arm/src/armv6-m/up_releasepending.c
index 6ac07736b5b..3c925a02b81 100644
--- a/arch/arm/src/armv6-m/up_releasepending.c
+++ b/arch/arm/src/armv6-m/up_releasepending.c
@@ -66,7 +66,7 @@ void up_release_pending(void)
 {
   struct tcb_s *rtcb = this_task();
 
-  sllerr("From TCB=%p\n", rtcb);
+  sinfo("From TCB=%p\n", rtcb);
 
   /* Merge the g_pendingtasks list into the ready-to-run task list */
 
diff --git a/arch/arm/src/armv6-m/up_reprioritizertr.c b/arch/arm/src/armv6-m/up_reprioritizertr.c
index ff30d6b590b..41f0c8700d3 100644
--- a/arch/arm/src/armv6-m/up_reprioritizertr.c
+++ b/arch/arm/src/armv6-m/up_reprioritizertr.c
@@ -94,7 +94,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority)
       struct tcb_s *rtcb = this_task();
       bool switch_needed;
 
-      sllerr("TCB=%p PRI=%d\n", tcb, priority);
+      sinfo("TCB=%p PRI=%d\n", tcb, priority);
 
       /* Remove the tcb task from the ready-to-run list.
        * sched_removereadytorun will return true if we just removed the head
diff --git a/arch/arm/src/armv6-m/up_schedulesigaction.c b/arch/arm/src/armv6-m/up_schedulesigaction.c
index bf9fdf1c494..5040582bacf 100644
--- a/arch/arm/src/armv6-m/up_schedulesigaction.c
+++ b/arch/arm/src/armv6-m/up_schedulesigaction.c
@@ -107,7 +107,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
 {
   irqstate_t flags;
 
-  serr("tcb=0x%p sigdeliver=0x%p\n", tcb, sigdeliver);
+  sinfo("tcb=0x%p sigdeliver=0x%p\n", tcb, sigdeliver);
 
   /* Make sure that interrupts are disabled */
 
@@ -121,7 +121,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
        * to the currently executing task.
        */
 
-      serr("rtcb=0x%p CURRENT_REGS=0x%p\n", this_task(), CURRENT_REGS);
+      sinfo("rtcb=0x%p CURRENT_REGS=0x%p\n", this_task(), CURRENT_REGS);
 
       if (tcb == this_task())
         {
diff --git a/arch/arm/src/armv6-m/up_sigdeliver.c b/arch/arm/src/armv6-m/up_sigdeliver.c
index 4f40b976659..c2b3e8675e0 100644
--- a/arch/arm/src/armv6-m/up_sigdeliver.c
+++ b/arch/arm/src/armv6-m/up_sigdeliver.c
@@ -100,7 +100,7 @@ void up_sigdeliver(void)
 
   board_autoled_on(LED_SIGNAL);
 
-  serr("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n",
+  sinfo("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n",
         rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head);
   ASSERT(rtcb->xcp.sigdeliver != NULL);
 
@@ -135,7 +135,7 @@ void up_sigdeliver(void)
    * errno that is needed by the user logic (it is probably EINTR).
    */
 
-  serr("Resuming\n");
+  sinfo("Resuming\n");
   (void)up_irq_save();
   rtcb->pterrno = saved_errno;
 
diff --git a/arch/arm/src/armv6-m/up_svcall.c b/arch/arm/src/armv6-m/up_svcall.c
index 971b6d2c1e7..1cd7e3a33b0 100644
--- a/arch/arm/src/armv6-m/up_svcall.c
+++ b/arch/arm/src/armv6-m/up_svcall.c
@@ -147,19 +147,19 @@ int up_svcall(int irq, FAR void *context)
   if (cmd > SYS_switch_context)
 # endif
     {
-      svcllinfo("SVCALL Entry: regs: %p cmd: %d\n", regs, cmd);
-      svcllinfo("  R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
-                regs[REG_R0],  regs[REG_R1],  regs[REG_R2],  regs[REG_R3],
-                regs[REG_R4],  regs[REG_R5],  regs[REG_R6],  regs[REG_R7]);
-      svcllinfo("  R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
-                regs[REG_R8],  regs[REG_R9],  regs[REG_R10], regs[REG_R11],
-                regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
+      svcinfo("SVCALL Entry: regs: %p cmd: %d\n", regs, cmd);
+      svcinfo("  R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+              regs[REG_R0],  regs[REG_R1],  regs[REG_R2],  regs[REG_R3],
+              regs[REG_R4],  regs[REG_R5],  regs[REG_R6],  regs[REG_R7]);
+      svcinfo("  R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+              regs[REG_R8],  regs[REG_R9],  regs[REG_R10], regs[REG_R11],
+              regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
 # ifdef CONFIG_BUILD_PROTECTED
-      svcllinfo(" PSR: %08x PRIMASK: %08x EXC_RETURN: %08x\n",
-                regs[REG_XPSR], regs[REG_PRIMASK], regs[REG_EXC_RETURN]);
+      svcinfo(" PSR: %08x PRIMASK: %08x EXC_RETURN: %08x\n",
+              regs[REG_XPSR], regs[REG_PRIMASK], regs[REG_EXC_RETURN]);
 # else
-      svcllinfo(" PSR: %08x PRIMASK: %08x\n",
-                regs[REG_XPSR], regs[REG_PRIMASK]);
+      svcinfo(" PSR: %08x PRIMASK: %08x\n",
+              regs[REG_XPSR], regs[REG_PRIMASK]);
 # endif
     }
 #endif
@@ -444,7 +444,7 @@ int up_svcall(int irq, FAR void *context)
 
           regs[REG_R0] -= CONFIG_SYS_RESERVED;
 #else
-          svcllerr("ERROR: Bad SYS call: %d\n", regs[REG_R0]);
+          svcerr("ERROR: Bad SYS call: %d\n", regs[REG_R0]);
 #endif
         }
         break;
@@ -459,30 +459,30 @@ int up_svcall(int irq, FAR void *context)
   if (regs != CURRENT_REGS)
 # endif
     {
-      svcllinfo("SVCall Return:\n");
-      svcllinfo("  R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
-                CURRENT_REGS[REG_R0],  CURRENT_REGS[REG_R1],
-                CURRENT_REGS[REG_R2],  CURRENT_REGS[REG_R3],
-                CURRENT_REGS[REG_R4],  CURRENT_REGS[REG_R5],
-                CURRENT_REGS[REG_R6],  CURRENT_REGS[REG_R7]);
-      svcllinfo("  R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
-                CURRENT_REGS[REG_R8],  CURRENT_REGS[REG_R9],
-                CURRENT_REGS[REG_R10], CURRENT_REGS[REG_R11],
-                CURRENT_REGS[REG_R12], CURRENT_REGS[REG_R13],
-                CURRENT_REGS[REG_R14], CURRENT_REGS[REG_R15]);
+      svcinfo("SVCall Return:\n");
+      svcinfo("  R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+              CURRENT_REGS[REG_R0],  CURRENT_REGS[REG_R1],
+              CURRENT_REGS[REG_R2],  CURRENT_REGS[REG_R3],
+              CURRENT_REGS[REG_R4],  CURRENT_REGS[REG_R5],
+              CURRENT_REGS[REG_R6],  CURRENT_REGS[REG_R7]);
+      svcinfo("  R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+              CURRENT_REGS[REG_R8],  CURRENT_REGS[REG_R9],
+              CURRENT_REGS[REG_R10], CURRENT_REGS[REG_R11],
+              CURRENT_REGS[REG_R12], CURRENT_REGS[REG_R13],
+              CURRENT_REGS[REG_R14], CURRENT_REGS[REG_R15]);
 #ifdef CONFIG_BUILD_PROTECTED
-      svcllinfo(" PSR: %08x PRIMASK: %08x EXC_RETURN: %08x\n",
-                CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_PRIMASK],
-                CURRENT_REGS[REG_EXC_RETURN]);
+      svcinfo(" PSR: %08x PRIMASK: %08x EXC_RETURN: %08x\n",
+              CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_PRIMASK],
+              CURRENT_REGS[REG_EXC_RETURN]);
 #else
-      svcllinfo(" PSR: %08x PRIMASK: %08x\n",
-                CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_PRIMASK]);
+      svcinfo(" PSR: %08x PRIMASK: %08x\n",
+              CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_PRIMASK]);
 #endif
     }
 # ifdef CONFIG_DEBUG_SVCALL
   else
     {
-      svcllinfo("SVCall Return: %d\n", regs[REG_R0]);
+      svcinfo("SVCall Return: %d\n", regs[REG_R0]);
     }
 # endif
 #endif
diff --git a/arch/arm/src/armv7-a/arm_assert.c b/arch/arm/src/armv7-a/arm_assert.c
index bdeffa763cf..3c798d33a0d 100644
--- a/arch/arm/src/armv7-a/arm_assert.c
+++ b/arch/arm/src/armv7-a/arm_assert.c
@@ -185,7 +185,7 @@ static int usbtrace_syslog(FAR const char *fmt, ...)
   /* Let vsyslog do the real work */
 
   va_start(ap, fmt);
-  ret = lowvsyslog(LOG_INFO, fmt, ap);
+  ret = vsyslog(LOG_EMERG, fmt, ap);
   va_end(ap);
   return ret;
 }
@@ -372,7 +372,7 @@ static void _up_assert(int errorcode)
 
 void up_assert(const uint8_t *filename, int lineno)
 {
-#if CONFIG_TASK_NAME_SIZE > 0
+#if CONFIG_TASK_NAME_SIZE > 0 && defined(CONFIG_DEBUG_ALERT)
   struct tcb_s *rtcb = this_task();
 #endif
   board_autoled_on(LED_ASSERTION);
diff --git a/arch/arm/src/armv7-a/arm_cpustart.c b/arch/arm/src/armv7-a/arm_cpustart.c
index 98aee251ab1..88906a717de 100644
--- a/arch/arm/src/armv7-a/arm_cpustart.c
+++ b/arch/arm/src/armv7-a/arm_cpustart.c
@@ -64,19 +64,19 @@ static inline void arm_registerdump(FAR struct tcb_s *tcb)
 {
   int regndx;
 
-  _llerr("CPU%d:\n", up_cpu_index());
+  _info("CPU%d:\n", up_cpu_index());
 
   /* Dump the startup registers */
 
   for (regndx = REG_R0; regndx <= REG_R15; regndx += 8)
     {
       uint32_t *ptr = (uint32_t *)&tcb->xcp.regs[regndx];
-      _llerr("R%d: %08x %08x %08x %08x %08x %08x %08x %08x\n",
-             regndx, ptr[0], ptr[1], ptr[2], ptr[3],
-             ptr[4], ptr[5], ptr[6], ptr[7]);
+      _info("R%d: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+            regndx, ptr[0], ptr[1], ptr[2], ptr[3],
+            ptr[4], ptr[5], ptr[6], ptr[7]);
     }
 
-  _llerr("CPSR: %08x\n", tcb->xcp.regs[REG_CPSR]);
+  _info("CPSR: %08x\n", tcb->xcp.regs[REG_CPSR]);
 }
 #else
 # define arm_registerdump(tcb)
@@ -106,7 +106,7 @@ int arm_start_handler(int irq, FAR void *context)
 {
   FAR struct tcb_s *tcb;
 
-  sllinfo("CPU%d Started\n", up_cpu_index());
+  sinfo("CPU%d Started\n", up_cpu_index());
 
   /* Reset scheduler parameters */
 
@@ -155,7 +155,7 @@ int arm_start_handler(int irq, FAR void *context)
 
 int up_cpu_start(int cpu)
 {
-  sllinfo("Starting CPU%d\n", cpu);
+  sinfo("Starting CPU%d\n", cpu);
 
   DEBUGASSERT(cpu >= 0 && cpu < CONFIG_SMP_NCPUS && cpu != this_cpu());
 
diff --git a/arch/arm/src/armv7-a/arm_dataabort.c b/arch/arm/src/armv7-a/arm_dataabort.c
index dae3b926e06..50c95a20188 100644
--- a/arch/arm/src/armv7-a/arm_dataabort.c
+++ b/arch/arm/src/armv7-a/arm_dataabort.c
@@ -104,7 +104,7 @@ uint32_t *arm_dataabort(uint32_t *regs, uint32_t dfar, uint32_t dfsr)
    * fatal error.
    */
 
-  pgllerr("DFSR: %08x DFAR: %08x\n", dfsr, dfar);
+  pginfo("DFSR: %08x DFAR: %08x\n", dfsr, dfar);
   if ((dfsr & FSR_MASK) != FSR_PAGE)
     {
       goto segfault;
@@ -115,7 +115,7 @@ uint32_t *arm_dataabort(uint32_t *regs, uint32_t dfar, uint32_t dfsr)
    * (It has not yet been saved in the register context save area).
    */
 
-  pgllinfo("VBASE: %08x VEND: %08x\n", PG_PAGED_VBASE, PG_PAGED_VEND);
+  pginfo("VBASE: %08x VEND: %08x\n", PG_PAGED_VBASE, PG_PAGED_VEND);
   if (dfar < PG_PAGED_VBASE || dfar >= PG_PAGED_VEND)
     {
       goto segfault;
diff --git a/arch/arm/src/armv7-a/arm_elf.c b/arch/arm/src/armv7-a/arm_elf.c
index e262095e5c0..8b9528159ce 100644
--- a/arch/arm/src/armv7-a/arm_elf.c
+++ b/arch/arm/src/armv7-a/arm_elf.c
@@ -74,7 +74,7 @@ bool up_checkarch(FAR const Elf32_Ehdr *ehdr)
 
   if (ehdr->e_machine != EM_ARM)
     {
-      berr("Not for ARM: e_machine=%04x\n", ehdr->e_machine);
+      berr("ERROR: Not for ARM: e_machine=%04x\n", ehdr->e_machine);
       return -ENOEXEC;
     }
 
@@ -82,7 +82,7 @@ bool up_checkarch(FAR const Elf32_Ehdr *ehdr)
 
   if (ehdr->e_ident[EI_CLASS] != ELFCLASS32)
     {
-      berr("Need 32-bit objects: e_ident[EI_CLASS]=%02x\n", ehdr->e_ident[EI_CLASS]);
+      berr("ERROR: Need 32-bit objects: e_ident[EI_CLASS]=%02x\n", ehdr->e_ident[EI_CLASS]);
       return -ENOEXEC;
     }
 
@@ -94,7 +94,7 @@ bool up_checkarch(FAR const Elf32_Ehdr *ehdr)
   if (ehdr->e_ident[EI_DATA] != ELFDATA2LSB)
 #endif
     {
-      berr("Wrong endian-ness: e_ident[EI_DATA]=%02x\n", ehdr->e_ident[EI_DATA]);
+      berr("ERROR: Wrong endian-ness: e_ident[EI_DATA]=%02x\n", ehdr->e_ident[EI_DATA]);
       return -ENOEXEC;
     }
 
@@ -102,7 +102,7 @@ bool up_checkarch(FAR const Elf32_Ehdr *ehdr)
 
   if ((ehdr->e_entry & 3) != 0)
     {
-      berr("Entry point is not properly aligned: %08x\n", ehdr->e_entry);
+      berr("ERROR: Entry point is not properly aligned: %08x\n", ehdr->e_entry);
       return -ENOEXEC;
     }
 
@@ -175,7 +175,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
         offset += sym->st_value - addr;
         if (offset & 3 || offset <= (int32_t) 0xfe000000 || offset >= (int32_t) 0x02000000)
           {
-            berr("  ERROR: PC24 [%d] relocation out of range, offset=%08lx\n",
+            berr("ERROR: PC24 [%d] relocation out of range, offset=%08lx\n",
                  ELF32_R_TYPE(rel->r_info), offset);
 
             return -EINVAL;
@@ -246,7 +246,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
       break;
 
     default:
-      berr("Unsupported relocation: %d\n", ELF32_R_TYPE(rel->r_info));
+      berr("ERROR: Unsupported relocation: %d\n", ELF32_R_TYPE(rel->r_info));
       return -EINVAL;
     }
 
@@ -256,6 +256,6 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
 int up_relocateadd(FAR const Elf32_Rela *rel, FAR const Elf32_Sym *sym,
                    uintptr_t addr)
 {
-  berr("RELA relocation not supported\n");
+  berr("ERROR: RELA relocation not supported\n");
   return -ENOSYS;
 }
diff --git a/arch/arm/src/armv7-a/arm_gicv2.c b/arch/arm/src/armv7-a/arm_gicv2.c
index b342c2fe822..e99eb540fde 100644
--- a/arch/arm/src/armv7-a/arm_gicv2.c
+++ b/arch/arm/src/armv7-a/arm_gicv2.c
@@ -387,7 +387,7 @@ uint32_t *arm_decodeirq(uint32_t *regs)
   regval = getreg32(GIC_ICCIAR);
   irq    = (regval & GIC_ICCIAR_INTID_MASK) >> GIC_ICCIAR_INTID_SHIFT;
 
-  irqllinfo("irq=%d\n", irq);
+  irqinfo("irq=%d\n", irq);
 
   /* Ignore spurions IRQs.  ICCIAR will report 1023 if there is no pending
    * interrupt.
diff --git a/arch/arm/src/armv7-a/arm_gicv2_dump.c b/arch/arm/src/armv7-a/arm_gicv2_dump.c
index c71ef444a32..23e43738da2 100644
--- a/arch/arm/src/armv7-a/arm_gicv2_dump.c
+++ b/arch/arm/src/armv7-a/arm_gicv2_dump.c
@@ -69,22 +69,22 @@
 
 static inline void arm_gic_dump_cpu(bool all, int irq, int nlines)
 {
-  irqllinfo("  CPU Interface Registers:\n");
-  irqllinfo("       ICR: %08x    PMR: %08x    BPR: %08x    IAR: %08x\n",
-            getreg32(GIC_ICCICR), getreg32(GIC_ICCPMR),
-            getreg32(GIC_ICCBPR), getreg32(GIC_ICCIAR));
-  irqllinfo("       RPR: %08x   HPIR: %08x   ABPR: %08x\n",
-            getreg32(GIC_ICCRPR), getreg32(GIC_ICCHPIR),
-            getreg32(GIC_ICCABPR));
-  irqllinfo("      AIAR: %08x  AHPIR: %08x    IDR: %08x\n",
-            getreg32(GIC_ICCAIAR), getreg32(GIC_ICCAHPIR),
-            getreg32(GIC_ICCIDR));
-  irqllinfo("      APR1: %08x   APR2: %08x   APR3: %08x   APR4: %08x\n",
-            getreg32(GIC_ICCAPR1), getreg32(GIC_ICCAPR2),
-            getreg32(GIC_ICCAPR3), getreg32(GIC_ICCAPR4));
-  irqllinfo("    NSAPR1: %08x NSAPR2: %08x NSAPR3: %08x NSAPR4: %08x\n",
-            getreg32(GIC_ICCNSAPR1), getreg32(GIC_ICCNSAPR2),
-            getreg32(GIC_ICCNSAPR3), getreg32(GIC_ICCNSAPR4));
+  irqinfo("  CPU Interface Registers:\n");
+  irqinfo("       ICR: %08x    PMR: %08x    BPR: %08x    IAR: %08x\n",
+          getreg32(GIC_ICCICR), getreg32(GIC_ICCPMR),
+          getreg32(GIC_ICCBPR), getreg32(GIC_ICCIAR));
+  irqinfo("       RPR: %08x   HPIR: %08x   ABPR: %08x\n",
+          getreg32(GIC_ICCRPR), getreg32(GIC_ICCHPIR),
+          getreg32(GIC_ICCABPR));
+  irqinfo("      AIAR: %08x  AHPIR: %08x    IDR: %08x\n",
+          getreg32(GIC_ICCAIAR), getreg32(GIC_ICCAHPIR),
+          getreg32(GIC_ICCIDR));
+  irqinfo("      APR1: %08x   APR2: %08x   APR3: %08x   APR4: %08x\n",
+          getreg32(GIC_ICCAPR1), getreg32(GIC_ICCAPR2),
+          getreg32(GIC_ICCAPR3), getreg32(GIC_ICCAPR4));
+  irqinfo("    NSAPR1: %08x NSAPR2: %08x NSAPR3: %08x NSAPR4: %08x\n",
+          getreg32(GIC_ICCNSAPR1), getreg32(GIC_ICCNSAPR2),
+          getreg32(GIC_ICCNSAPR3), getreg32(GIC_ICCNSAPR4));
 }
 
 /****************************************************************************
@@ -110,9 +110,9 @@ static void arm_gic_dumpregs(uintptr_t regaddr, int nlines, int incr)
   incr <<= 2;
   for (i = 0; i < nlines; i += incr, regaddr += 16)
     {
-      irqllinfo("         %08x %08x %08x %08x\n",
-                getreg32(regaddr), getreg32(regaddr + 4),
-                getreg32(regaddr + 8), getreg32(regaddr + 12));
+      irqinfo("         %08x %08x %08x %08x\n",
+              getreg32(regaddr), getreg32(regaddr + 4),
+              getreg32(regaddr + 8), getreg32(regaddr + 12));
     }
 }
 
@@ -135,7 +135,7 @@ static void arm_gic_dumpregs(uintptr_t regaddr, int nlines, int incr)
 static inline void arm_gic_dump4(const char *name, uintptr_t regaddr,
                                  int nlines)
 {
-  irqllinfo("       %s[%08lx]\n", name, (unsigned long)regaddr);
+  irqinfo("       %s[%08lx]\n", name, (unsigned long)regaddr);
   arm_gic_dumpregs(regaddr, nlines, 4);
 }
 
@@ -158,7 +158,7 @@ static inline void arm_gic_dump4(const char *name, uintptr_t regaddr,
 static inline void arm_gic_dump8(const char *name, uintptr_t regaddr,
                                  int nlines)
 {
-  irqllinfo("       %s[%08lx]\n", name, (unsigned long)regaddr);
+  irqinfo("       %s[%08lx]\n", name, (unsigned long)regaddr);
   arm_gic_dumpregs(regaddr, nlines, 8);
 }
 
@@ -181,7 +181,7 @@ static inline void arm_gic_dump8(const char *name, uintptr_t regaddr,
 static inline void arm_gic_dump16(const char *name, uintptr_t regaddr,
                                   int nlines)
 {
-  irqllinfo("       %s[%08lx]\n", name, (unsigned long)regaddr);
+  irqinfo("       %s[%08lx]\n", name, (unsigned long)regaddr);
   arm_gic_dumpregs(regaddr, nlines, 16);
 }
 
@@ -204,7 +204,7 @@ static inline void arm_gic_dump16(const char *name, uintptr_t regaddr,
 static inline void arm_gic_dump32(const char *name, uintptr_t regaddr,
                                   int nlines)
 {
-  irqllinfo("       %s[%08lx]\n", name, (unsigned long)regaddr);
+  irqinfo("       %s[%08lx]\n", name, (unsigned long)regaddr);
   arm_gic_dumpregs(regaddr, nlines, 32);
 }
 
@@ -226,10 +226,10 @@ static inline void arm_gic_dump32(const char *name, uintptr_t regaddr,
 
 static inline void arm_gic_dump_distributor(bool all, int irq, int nlines)
 {
-  irqllinfo("  Distributor Registers:\n");
-  irqllinfo("       DCR: %08x   ICTR: %08x   IIDR: %08x\n",
-        getreg32(GIC_ICDDCR), getreg32(GIC_ICDICTR),
-        getreg32(GIC_ICDIIDR));
+  irqinfo("  Distributor Registers:\n");
+  irqinfo("       DCR: %08x   ICTR: %08x   IIDR: %08x\n",
+          getreg32(GIC_ICDDCR), getreg32(GIC_ICDICTR),
+          getreg32(GIC_ICDIIDR));
 
   if (all)
     {
@@ -246,27 +246,27 @@ static inline void arm_gic_dump_distributor(bool all, int irq, int nlines)
     }
   else
     {
-      irqllinfo("       ISR: %08x   ISER: %08x   ISPR: %08x    SAR: %08x\n",
-                getreg32(GIC_ICDISR(irq)), getreg32(GIC_ICDISER(irq)),
-                getreg32(GIC_ICDISPR(irq)), getreg32(GIC_ICDSAR(irq)));
-      irqllinfo("       IPR: %08x   IPTR: %08x   ICFR: %08x  SPISR: %08x\n",
-                getreg32(GIC_ICDIPR(irq)), getreg32(GIC_ICDIPTR(irq)),
-                getreg32(GIC_ICDICFR(irq)), getreg32(GIC_ICDSPISR(irq)));
-      irqllinfo("     NSACR: %08x   SCPR: %08x\n",
-                getreg32(GIC_ICDNSACR(irq)), getreg32(GIC_ICDSCPR(irq)));
+      irqinfo("       ISR: %08x   ISER: %08x   ISPR: %08x    SAR: %08x\n",
+              getreg32(GIC_ICDISR(irq)), getreg32(GIC_ICDISER(irq)),
+              getreg32(GIC_ICDISPR(irq)), getreg32(GIC_ICDSAR(irq)));
+      irqinfo("       IPR: %08x   IPTR: %08x   ICFR: %08x  SPISR: %08x\n",
+              getreg32(GIC_ICDIPR(irq)), getreg32(GIC_ICDIPTR(irq)),
+              getreg32(GIC_ICDICFR(irq)), getreg32(GIC_ICDSPISR(irq)));
+      irqinfo("     NSACR: %08x   SCPR: %08x\n",
+              getreg32(GIC_ICDNSACR(irq)), getreg32(GIC_ICDSCPR(irq)));
     }
 
-  irqllinfo("       PIDR[%08lx]:\n", (unsigned long)GIC_ICDPIDR(0));
-  irqllinfo("         %08x %08x %08x %08x\n",
-            getreg32(GIC_ICDPIDR(0)), getreg32(GIC_ICDPIDR(1)),
-            getreg32(GIC_ICDPIDR(2)), getreg32(GIC_ICDPIDR(3)));
-  irqllinfo("         %08x %08x %08x %08x\n",
-            getreg32(GIC_ICDPIDR(4)), getreg32(GIC_ICDPIDR(5)),
-            getreg32(GIC_ICDPIDR(6)));
-  irqllinfo("       CIDR[%08lx]:\n", (unsigned long)GIC_ICDCIDR(0));
-  irqllinfo("         %08x %08x %08x %08x\n",
-            getreg32(GIC_ICDCIDR(0)), getreg32(GIC_ICDCIDR(1)),
-            getreg32(GIC_ICDCIDR(2)), getreg32(GIC_ICDCIDR(3)));
+  irqinfo("       PIDR[%08lx]:\n", (unsigned long)GIC_ICDPIDR(0));
+  irqinfo("         %08x %08x %08x %08x\n",
+          getreg32(GIC_ICDPIDR(0)), getreg32(GIC_ICDPIDR(1)),
+          getreg32(GIC_ICDPIDR(2)), getreg32(GIC_ICDPIDR(3)));
+  irqinfo("         %08x %08x %08x %08x\n",
+          getreg32(GIC_ICDPIDR(4)), getreg32(GIC_ICDPIDR(5)),
+          getreg32(GIC_ICDPIDR(6)));
+  irqinfo("       CIDR[%08lx]:\n", (unsigned long)GIC_ICDCIDR(0));
+  irqinfo("         %08x %08x %08x %08x\n",
+          getreg32(GIC_ICDCIDR(0)), getreg32(GIC_ICDCIDR(1)),
+          getreg32(GIC_ICDCIDR(2)), getreg32(GIC_ICDCIDR(3)));
 }
 
 /****************************************************************************
@@ -295,11 +295,11 @@ void arm_gic_dump(const char *msg, bool all, int irq)
 
   if (all)
     {
-      irqllinfo("GIC: %s NLINES=%u\n", msg, nlines);
+      irqinfo("GIC: %s NLINES=%u\n", msg, nlines);
     }
   else
     {
-      irqllinfo("GIC: %s IRQ=%d\n", msg, irq);
+      irqinfo("GIC: %s IRQ=%d\n", msg, irq);
     }
 
   arm_gic_dump_cpu(all, irq, nlines);
diff --git a/arch/arm/src/armv7-a/arm_l2cc_pl310.c b/arch/arm/src/armv7-a/arm_l2cc_pl310.c
index 94a1a343dca..9d455e40d27 100644
--- a/arch/arm/src/armv7-a/arm_l2cc_pl310.c
+++ b/arch/arm/src/armv7-a/arm_l2cc_pl310.c
@@ -411,7 +411,7 @@ void up_l2ccinitialize(void)
       putreg32(L2CC_CR_L2CEN, L2CC_CR);
     }
 
-  _llerr("(%d ways) * (%d bytes/way) = %d bytes\n",
+  sinfo("(%d ways) * (%d bytes/way) = %d bytes\n",
         PL310_NWAYS, PL310_WAYSIZE, PL310_CACHE_SIZE);
 }
 
diff --git a/arch/arm/src/armv7-a/arm_prefetchabort.c b/arch/arm/src/armv7-a/arm_prefetchabort.c
index 4e211436425..0bb8cd37932 100644
--- a/arch/arm/src/armv7-a/arm_prefetchabort.c
+++ b/arch/arm/src/armv7-a/arm_prefetchabort.c
@@ -86,8 +86,8 @@ uint32_t *arm_prefetchabort(uint32_t *regs, uint32_t ifar, uint32_t ifsr)
    * virtual addresses.
    */
 
-  pgllerr("VADDR: %08x VBASE: %08x VEND: %08x\n",
-          regs[REG_PC], PG_PAGED_VBASE, PG_PAGED_VEND);
+  pginfo("VADDR: %08x VBASE: %08x VEND: %08x\n",
+         regs[REG_PC], PG_PAGED_VBASE, PG_PAGED_VEND);
 
   if (regs[REG_R15] >= PG_PAGED_VBASE && regs[REG_R15] < PG_PAGED_VEND)
     {
diff --git a/arch/arm/src/armv7-a/arm_releasepending.c b/arch/arm/src/armv7-a/arm_releasepending.c
index b2e36821b11..7afc6989a75 100644
--- a/arch/arm/src/armv7-a/arm_releasepending.c
+++ b/arch/arm/src/armv7-a/arm_releasepending.c
@@ -67,7 +67,7 @@ void up_release_pending(void)
 {
   struct tcb_s *rtcb = this_task();
 
-  sllerr("From TCB=%p\n", rtcb);
+  sinfo("From TCB=%p\n", rtcb);
 
   /* Merge the g_pendingtasks list into the ready-to-run task list */
 
diff --git a/arch/arm/src/armv7-a/arm_reprioritizertr.c b/arch/arm/src/armv7-a/arm_reprioritizertr.c
index 468e382779f..4381178e05b 100644
--- a/arch/arm/src/armv7-a/arm_reprioritizertr.c
+++ b/arch/arm/src/armv7-a/arm_reprioritizertr.c
@@ -95,7 +95,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority)
       struct tcb_s *rtcb = this_task();
       bool switch_needed;
 
-      sllerr("TCB=%p PRI=%d\n", tcb, priority);
+      sinfo("TCB=%p PRI=%d\n", tcb, priority);
 
       /* Remove the tcb task from the ready-to-run list.
        * sched_removereadytorun will return true if we just
diff --git a/arch/arm/src/armv7-a/arm_schedulesigaction.c b/arch/arm/src/armv7-a/arm_schedulesigaction.c
index 74648c8fa5d..89df348ba03 100644
--- a/arch/arm/src/armv7-a/arm_schedulesigaction.c
+++ b/arch/arm/src/armv7-a/arm_schedulesigaction.c
@@ -94,7 +94,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
 {
   irqstate_t flags;
 
-  serr("tcb=0x%p sigdeliver=0x%p\n", tcb, sigdeliver);
+  sinfo("tcb=0x%p sigdeliver=0x%p\n", tcb, sigdeliver);
 
   /* Make sure that interrupts are disabled */
 
@@ -108,7 +108,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
        * to the currently executing task.
        */
 
-      serr("rtcb=0x%p CURRENT_REGS=0x%p\n", this_task(), CURRENT_REGS);
+      sinfo("rtcb=0x%p CURRENT_REGS=0x%p\n", this_task(), CURRENT_REGS);
 
       if (tcb == this_task())
         {
diff --git a/arch/arm/src/armv7-a/arm_sigdeliver.c b/arch/arm/src/armv7-a/arm_sigdeliver.c
index 8009386492d..be720a464c3 100644
--- a/arch/arm/src/armv7-a/arm_sigdeliver.c
+++ b/arch/arm/src/armv7-a/arm_sigdeliver.c
@@ -83,7 +83,7 @@ void up_sigdeliver(void)
 
   board_autoled_on(LED_SIGNAL);
 
-  serr("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n",
+  sinfo("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n",
         rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head);
   ASSERT(rtcb->xcp.sigdeliver != NULL);
 
@@ -114,7 +114,7 @@ void up_sigdeliver(void)
    * errno that is needed by the user logic (it is probably EINTR).
    */
 
-  serr("Resuming\n");
+  sinfo("Resuming\n");
   (void)up_irq_save();
   rtcb->pterrno = saved_errno;
 
diff --git a/arch/arm/src/armv7-a/arm_syscall.c b/arch/arm/src/armv7-a/arm_syscall.c
index 0259acb5c6f..77b33b45f4b 100644
--- a/arch/arm/src/armv7-a/arm_syscall.c
+++ b/arch/arm/src/armv7-a/arm_syscall.c
@@ -156,14 +156,14 @@ uint32_t *arm_syscall(uint32_t *regs)
    * and R1..R7 =  variable number of arguments depending on the system call.
    */
 
-  svcllinfo("SYSCALL Entry: regs: %p cmd: %d\n", regs, cmd);
-  svcllinfo("  R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
-            regs[REG_R0],  regs[REG_R1],  regs[REG_R2],  regs[REG_R3],
-            regs[REG_R4],  regs[REG_R5],  regs[REG_R6],  regs[REG_R7]);
-  svcllinfo("  R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
-            regs[REG_R8],  regs[REG_R9],  regs[REG_R10], regs[REG_R11],
-            regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
-  svcllinfo("CPSR: %08x\n", regs[REG_CPSR]);
+  svcinfo("SYSCALL Entry: regs: %p cmd: %d\n", regs, cmd);
+  svcinfo("  R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+          regs[REG_R0],  regs[REG_R1],  regs[REG_R2],  regs[REG_R3],
+          regs[REG_R4],  regs[REG_R5],  regs[REG_R6],  regs[REG_R7]);
+  svcinfo("  R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+          regs[REG_R8],  regs[REG_R9],  regs[REG_R10], regs[REG_R11],
+          regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
+  svcinfo("CPSR: %08x\n", regs[REG_CPSR]);
 
   /* Handle the SVCall according to the command in R0 */
 
@@ -456,7 +456,7 @@ uint32_t *arm_syscall(uint32_t *regs)
 
           regs[REG_R0] -= CONFIG_SYS_RESERVED;
 #else
-          svcllerr("ERROR: Bad SYS call: %d\n", regs[REG_R0]);
+          svcerr("ERROR: Bad SYS call: %d\n", regs[REG_R0]);
 #endif
 
 #ifdef CONFIG_ARCH_KERNEL_STACK
@@ -479,14 +479,14 @@ uint32_t *arm_syscall(uint32_t *regs)
 
   /* Report what happened */
 
-  svcllinfo("SYSCALL Exit: regs: %p\n", regs);
-  svcllinfo("  R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
-            regs[REG_R0],  regs[REG_R1],  regs[REG_R2],  regs[REG_R3],
-            regs[REG_R4],  regs[REG_R5],  regs[REG_R6],  regs[REG_R7]);
-  svcllinfo("  R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
-            regs[REG_R8],  regs[REG_R9],  regs[REG_R10], regs[REG_R11],
-           regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
-  svcllinfo("CPSR: %08x\n", regs[REG_CPSR]);
+  svcinfo("SYSCALL Exit: regs: %p\n", regs);
+  svcinfo("  R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+          regs[REG_R0],  regs[REG_R1],  regs[REG_R2],  regs[REG_R3],
+          regs[REG_R4],  regs[REG_R5],  regs[REG_R6],  regs[REG_R7]);
+  svcinfo("  R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+          regs[REG_R8],  regs[REG_R9],  regs[REG_R10], regs[REG_R11],
+         regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
+  svcinfo("CPSR: %08x\n", regs[REG_CPSR]);
 
   /* Return the last value of curent_regs.  This supports context switches
    * on return from the exception.  That capability is only used with the
diff --git a/arch/arm/src/armv7-m/Kconfig b/arch/arm/src/armv7-m/Kconfig
index 406e2e46624..404dce07538 100644
--- a/arch/arm/src/armv7-m/Kconfig
+++ b/arch/arm/src/armv7-m/Kconfig
@@ -160,6 +160,7 @@ config ARMV7M_STACKCHECK
 config ARMV7M_ITMSYSLOG
 	bool "ITM SYSLOG support"
 	default n
+	select ARCH_SYSLOG
 	select SYSLOG
 	---help---
 		Enable hooks to support ITM syslog output.  This requires additional
diff --git a/arch/arm/src/armv7-m/itm_syslog.h b/arch/arm/src/armv7-m/itm_syslog.h
index 1b42be2ea8e..40f71624f57 100644
--- a/arch/arm/src/armv7-m/itm_syslog.h
+++ b/arch/arm/src/armv7-m/itm_syslog.h
@@ -57,7 +57,7 @@
  *
  ****************************************************************************/
 
-#if defined(CONFIG_SYSLOG) || defined(CONFIG_ARMV7M_ITMSYSLOG)
+#ifdef CONFIG_ARMV7M_ITMSYSLOG
 void itm_syslog_initialize(void);
 #else
 #  define itm_syslog_initialize()
diff --git a/arch/arm/src/armv7-m/mpu.h b/arch/arm/src/armv7-m/mpu.h
index 3ff96371cb1..22348a23a68 100644
--- a/arch/arm/src/armv7-m/mpu.h
+++ b/arch/arm/src/armv7-m/mpu.h
@@ -219,13 +219,13 @@ uint32_t mpu_subregion(uintptr_t base, size_t size, uint8_t l2size);
 
 static inline void mpu_showtype(void)
 {
-#ifdef CONFIG_DEBUG_ERROR
+#ifdef CONFIG_DEBUG_SCHED_INFO
   uint32_t regval = getreg32(MPU_TYPE);
 
-  _err("%s MPU Regions: data=%d instr=%d\n",
-      (regval & MPU_TYPE_SEPARATE) != 0 ? "Separate" : "Unified",
-      (regval & MPU_TYPE_DREGION_MASK) >> MPU_TYPE_DREGION_SHIFT,
-      (regval & MPU_TYPE_IREGION_MASK) >> MPU_TYPE_IREGION_SHIFT);
+  sinfo("%s MPU Regions: data=%d instr=%d\n",
+        (regval & MPU_TYPE_SEPARATE) != 0 ? "Separate" : "Unified",
+        (regval & MPU_TYPE_DREGION_MASK) >> MPU_TYPE_DREGION_SHIFT,
+        (regval & MPU_TYPE_IREGION_MASK) >> MPU_TYPE_IREGION_SHIFT);
 #endif
 }
 
diff --git a/arch/arm/src/armv7-m/up_assert.c b/arch/arm/src/armv7-m/up_assert.c
index eedfa522d81..b34cfc73950 100644
--- a/arch/arm/src/armv7-m/up_assert.c
+++ b/arch/arm/src/armv7-m/up_assert.c
@@ -198,7 +198,7 @@ static int usbtrace_syslog(FAR const char *fmt, ...)
   /* Let vsyslog do the real work */
 
   va_start(ap, fmt);
-  ret = lowvsyslog(LOG_INFO, fmt, ap);
+  ret = vsyslog(LOG_EMERG, fmt, ap);
   va_end(ap);
   return ret;
 }
@@ -375,7 +375,7 @@ static void _up_assert(int errorcode)
 
 void up_assert(const uint8_t *filename, int lineno)
 {
-#if CONFIG_TASK_NAME_SIZE > 0
+#if CONFIG_TASK_NAME_SIZE > 0 && defined(CONFIG_DEBUG_ALERT)
   struct tcb_s *rtcb = this_task();
 #endif
 
diff --git a/arch/arm/src/armv7-m/up_elf.c b/arch/arm/src/armv7-m/up_elf.c
index e45e2dbe242..f2e0cdd9792 100644
--- a/arch/arm/src/armv7-m/up_elf.c
+++ b/arch/arm/src/armv7-m/up_elf.c
@@ -82,7 +82,7 @@ bool up_checkarch(FAR const Elf32_Ehdr *ehdr)
 
   if (ehdr->e_machine != EM_ARM)
     {
-      berr("Not for ARM: e_machine=%04x\n", ehdr->e_machine);
+      berr("ERROR: Not for ARM: e_machine=%04x\n", ehdr->e_machine);
       return -ENOEXEC;
     }
 
@@ -90,7 +90,7 @@ bool up_checkarch(FAR const Elf32_Ehdr *ehdr)
 
   if (ehdr->e_ident[EI_CLASS] != ELFCLASS32)
     {
-      berr("Need 32-bit objects: e_ident[EI_CLASS]=%02x\n", ehdr->e_ident[EI_CLASS]);
+      berr("ERROR: Need 32-bit objects: e_ident[EI_CLASS]=%02x\n", ehdr->e_ident[EI_CLASS]);
       return -ENOEXEC;
     }
 
@@ -102,7 +102,7 @@ bool up_checkarch(FAR const Elf32_Ehdr *ehdr)
   if (ehdr->e_ident[EI_DATA] != ELFDATA2LSB)
 #endif
     {
-      berr("Wrong endian-ness: e_ident[EI_DATA]=%02x\n", ehdr->e_ident[EI_DATA]);
+      berr("ERROR: Wrong endian-ness: e_ident[EI_DATA]=%02x\n", ehdr->e_ident[EI_DATA]);
       return -ENOEXEC;
     }
 
@@ -177,7 +177,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
         offset += sym->st_value - addr;
         if (offset & 3 || offset <= (int32_t) 0xfe000000 || offset >= (int32_t) 0x02000000)
           {
-            berr("  ERROR: PC24 [%d] relocation out of range, offset=%08lx\n",
+            berr("ERROR:   ERROR: PC24 [%d] relocation out of range, offset=%08lx\n",
                  ELF32_R_TYPE(rel->r_info), offset);
 
             return -EINVAL;
@@ -298,7 +298,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
 
         if (ELF32_ST_TYPE(sym->st_info) == STT_FUNC && (offset & 1) == 0)
           {
-            berr("  ERROR: JUMP24 [%d] requires odd offset, offset=%08lx\n",
+            berr("ERROR:   ERROR: JUMP24 [%d] requires odd offset, offset=%08lx\n",
                  ELF32_R_TYPE(rel->r_info), offset);
 
             return -EINVAL;
@@ -308,7 +308,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
 
         if (offset <= (int32_t)0xff000000 || offset >= (int32_t)0x01000000)
           {
-            berr("  ERROR: JUMP24 [%d] relocation out of range, branch taget=%08lx\n",
+            berr("ERROR:   ERROR: JUMP24 [%d] relocation out of range, branch taget=%08lx\n",
                  ELF32_R_TYPE(rel->r_info), offset);
 
             return -EINVAL;
@@ -461,7 +461,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
       break;
 
     default:
-      berr("Unsupported relocation: %d\n", ELF32_R_TYPE(rel->r_info));
+      berr("ERROR: Unsupported relocation: %d\n", ELF32_R_TYPE(rel->r_info));
       return -EINVAL;
     }
 
@@ -471,7 +471,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
 int up_relocateadd(FAR const Elf32_Rela *rel, FAR const Elf32_Sym *sym,
                    uintptr_t addr)
 {
-  berr("RELA relocation not supported\n");
+  berr("ERROR: RELA relocation not supported\n");
   return -ENOSYS;
 }
 
diff --git a/arch/arm/src/armv7-m/up_hardfault.c b/arch/arm/src/armv7-m/up_hardfault.c
index 225ca8337e1..fe133cc4f37 100644
--- a/arch/arm/src/armv7-m/up_hardfault.c
+++ b/arch/arm/src/armv7-m/up_hardfault.c
@@ -60,25 +60,13 @@
  */
 
 #ifdef CONFIG_DEBUG_HARDFAULT
-# define hferr(format, ...)  _llerr(format, ##__VA_ARGS__)
+# define hfalert(format, ...)  _alert(format, ##__VA_ARGS__)
 #else
-# define hferr(x...)
+# define hfalert(x...)
 #endif
 
 #define INSN_SVC0        0xdf00 /* insn: svc 0 */
 
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Public Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
@@ -127,7 +115,7 @@ int up_hardfault(int irq, FAR void *context)
       /* Fetch the instruction that caused the Hard fault */
 
       uint16_t insn = *pc;
-      hferr("  PC: %p INSN: %04x\n", pc, insn);
+      hfalert("  PC: %p INSN: %04x\n", pc, insn);
 
       /* If this was the instruction 'svc 0', then forward processing
        * to the SVCall handler
@@ -135,7 +123,7 @@ int up_hardfault(int irq, FAR void *context)
 
       if (insn == INSN_SVC0)
         {
-          hferr("Forward SVCall\n");
+          hfalert("Forward SVCall\n");
           return up_svcall(irq, context);
         }
     }
@@ -143,43 +131,43 @@ int up_hardfault(int irq, FAR void *context)
 
   /* Dump some hard fault info */
 
-  hferr("Hard Fault:\n");
-  hferr("  IRQ: %d regs: %p\n", irq, regs);
-  hferr("  BASEPRI: %08x PRIMASK: %08x IPSR: %08x CONTROL: %08x\n",
-        getbasepri(), getprimask(), getipsr(), getcontrol());
-  hferr("  CFAULTS: %08x HFAULTS: %08x DFAULTS: %08x BFAULTADDR: %08x AFAULTS: %08x\n",
-        getreg32(NVIC_CFAULTS), getreg32(NVIC_HFAULTS),
-        getreg32(NVIC_DFAULTS), getreg32(NVIC_BFAULT_ADDR),
-        getreg32(NVIC_AFAULTS));
-  hferr("  R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
-        regs[REG_R0],  regs[REG_R1],  regs[REG_R2],  regs[REG_R3],
-        regs[REG_R4],  regs[REG_R5],  regs[REG_R6],  regs[REG_R7]);
-  hferr("  R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
-        regs[REG_R8],  regs[REG_R9],  regs[REG_R10], regs[REG_R11],
-        regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
+  hfalert("Hard Fault:\n");
+  hfalert("  IRQ: %d regs: %p\n", irq, regs);
+  hfalert("  BASEPRI: %08x PRIMASK: %08x IPSR: %08x CONTROL: %08x\n",
+          getbasepri(), getprimask(), getipsr(), getcontrol());
+  hfalert("  CFAULTS: %08x HFAULTS: %08x DFAULTS: %08x BFAULTADDR: %08x AFAULTS: %08x\n",
+          getreg32(NVIC_CFAULTS), getreg32(NVIC_HFAULTS),
+          getreg32(NVIC_DFAULTS), getreg32(NVIC_BFAULT_ADDR),
+          getreg32(NVIC_AFAULTS));
+  hfalert("  R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+          regs[REG_R0],  regs[REG_R1],  regs[REG_R2],  regs[REG_R3],
+          regs[REG_R4],  regs[REG_R5],  regs[REG_R6],  regs[REG_R7]);
+  hfalert("  R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+          regs[REG_R8],  regs[REG_R9],  regs[REG_R10], regs[REG_R11],
+          regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
 
 #ifdef CONFIG_ARMV7M_USEBASEPRI
 #  ifdef REG_EXC_RETURN
-  hferr("  xPSR: %08x BASEPRI: %08x EXC_RETURN: %08x (saved)\n",
-        CURRENT_REGS[REG_XPSR],  CURRENT_REGS[REG_BASEPRI],
-        CURRENT_REGS[REG_EXC_RETURN]);
+  hfalert("  xPSR: %08x BASEPRI: %08x EXC_RETURN: %08x (saved)\n",
+          CURRENT_REGS[REG_XPSR],  CURRENT_REGS[REG_BASEPRI],
+          CURRENT_REGS[REG_EXC_RETURN]);
 #  else
-  hferr("  xPSR: %08x BASEPRI: %08x (saved)\n",
-        CURRENT_REGS[REG_XPSR],  CURRENT_REGS[REG_BASEPRI]);
+  hfalert("  xPSR: %08x BASEPRI: %08x (saved)\n",
+          CURRENT_REGS[REG_XPSR],  CURRENT_REGS[REG_BASEPRI]);
 #  endif
 #else
 #  ifdef REG_EXC_RETURN
-  hferr("  xPSR: %08x PRIMASK: %08x EXC_RETURN: %08x (saved)\n",
-        CURRENT_REGS[REG_XPSR],  CURRENT_REGS[REG_PRIMASK],
-        CURRENT_REGS[REG_EXC_RETURN]);
+  hfalert("  xPSR: %08x PRIMASK: %08x EXC_RETURN: %08x (saved)\n",
+          CURRENT_REGS[REG_XPSR],  CURRENT_REGS[REG_PRIMASK],
+          CURRENT_REGS[REG_EXC_RETURN]);
 #  else
-  hferr("  xPSR: %08x PRIMASK: %08x (saved)\n",
-        CURRENT_REGS[REG_XPSR],  CURRENT_REGS[REG_PRIMASK]);
+  hfalert("  xPSR: %08x PRIMASK: %08x (saved)\n",
+          CURRENT_REGS[REG_XPSR],  CURRENT_REGS[REG_PRIMASK]);
 #  endif
 #endif
 
   (void)up_irq_save();
-  _llerr("PANIC!!! Hard fault: %08x\n", getreg32(NVIC_HFAULTS));
+  _alert("PANIC!!! Hard fault: %08x\n", getreg32(NVIC_HFAULTS));
   PANIC();
   return OK;
 }
diff --git a/arch/arm/src/armv7-m/up_itm_syslog.c b/arch/arm/src/armv7-m/up_itm_syslog.c
index 94b499879a7..d63fed09adb 100644
--- a/arch/arm/src/armv7-m/up_itm_syslog.c
+++ b/arch/arm/src/armv7-m/up_itm_syslog.c
@@ -2,7 +2,7 @@
  * arch/arm/src/armv7-m/up_itm_syslog.c
  *
  *   Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved.
- *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2014, 2016 Gregory Nutt. All rights reserved.
  *   Authors: Pierre-noel Bouteville <pnb990@gmail.com>
  *            Gregory Nutt <gnutt@nuttx.org>
  *
@@ -52,7 +52,7 @@
 #include "up_arch.h"
 #include "itm_syslog.h"
 
-#if defined(CONFIG_SYSLOG) || defined(CONFIG_ARMV7M_ITMSYSLOG)
+#ifdef CONFIG_ARMV7M_ITMSYSLOG
 
 /****************************************************************************
  * Pre-processor Definitions
@@ -72,6 +72,73 @@
 #  define CONFIG_ARMV7M_ITMSYSLOG_PORT 0
 #endif
 
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/* SYSLOG channel methods */
+
+static int itm_putc(int ch);
+static int itm_flush(void);
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/* This structure describes the ITM SYSLOG channel */
+
+static const struct syslog_channel_s g_itm_channel =
+{
+  .sc_putc  = itm_putc,
+  .sc_force = itm_putc,
+  .sc_flush = itm_flush,
+};
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: itm_putc
+ *
+ * Description:
+ *   This is the low-level system logging interface.
+ *
+ ****************************************************************************/
+
+static int itm_putc(int ch)
+{
+  /* ITM enabled */
+
+  if ((getreg32(ITM_TCR) & ITM_TCR_ITMENA_Msk) == 0)
+    {
+      return EOF;
+    }
+
+  /* ITM Port "CONFIG_ARMV7M_ITMSYSLOG_PORT" enabled */
+
+  if (getreg32(ITM_TER) & (1 << CONFIG_ARMV7M_ITMSYSLOG_PORT))
+    {
+      while (getreg32(ITM_PORT(CONFIG_ARMV7M_ITMSYSLOG_PORT)) == 0);
+      putreg8((uint8_t)ch, ITM_PORT(CONFIG_ARMV7M_ITMSYSLOG_PORT));
+    }
+
+  return ch;
+}
+
+/****************************************************************************
+ * Name: itm_flush
+ *
+ * Description:
+ *   A dummy FLUSH method
+ *
+ ****************************************************************************/
+
+static int itm_flush(void)
+{
+  return OK;
+}
+
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
@@ -116,38 +183,10 @@ void itm_syslog_initialize(void)
   putreg32(0x0001000d, ITM_TCR);
   putreg32(0x00000100, TPI_FFCR);
   putreg32(0xffffffff, ITM_TER); /* Enable 32 Ports */
+
+  /* Setup the SYSLOG channel */
+
+  (void)syslog_channel(&g_itm_channel);
 }
 
-/****************************************************************************
- * Name: syslog_putc
- *
- * Description:
- *   This is the low-level system logging interface.  The debugging/syslogging
- *   interfaces are syslog() and lowsyslog().  The difference is that
- *   the syslog() internface writes to fd=1 (stdout) whereas lowsyslog() uses
- *   a lower level interface that works from interrupt handlers.  This
- *   function is the low-level interface used to implement lowsyslog().
- *
- ****************************************************************************/
-
-int syslog_putc(int ch)
-{
-  /* ITM enabled */
-
-  if ((getreg32(ITM_TCR) & ITM_TCR_ITMENA_Msk) == 0)
-    {
-      return EOF;
-    }
-
-  /* ITM Port "CONFIG_ARMV7M_ITMSYSLOG_PORT" enabled */
-
-  if (getreg32(ITM_TER) & (1 << CONFIG_ARMV7M_ITMSYSLOG_PORT))
-    {
-      while (getreg32(ITM_PORT(CONFIG_ARMV7M_ITMSYSLOG_PORT)) == 0);
-      putreg8((uint8_t)ch, ITM_PORT(CONFIG_ARMV7M_ITMSYSLOG_PORT));
-    }
-
-  return ch;
-}
-
-#endif /* CONFIG_SYSLOG && CONFIG_ARMV7M_ITMSYSLOG */
+#endif /* CONFIG_ARMV7M_ITMSYSLOG */
diff --git a/arch/arm/src/armv7-m/up_memfault.c b/arch/arm/src/armv7-m/up_memfault.c
index 4359072e65e..f883209b769 100644
--- a/arch/arm/src/armv7-m/up_memfault.c
+++ b/arch/arm/src/armv7-m/up_memfault.c
@@ -55,23 +55,13 @@
 #undef DEBUG_MEMFAULTS         /* Define to debug memory management faults */
 
 #ifdef DEBUG_MEMFAULTS
-# define mferr(format, ...)  _llerr(format, ##__VA_ARGS__)
+# define mferr(format, ...)  _alert(format, ##__VA_ARGS__)
+# define mfinfo(format, ...) _alert(format, ##__VA_ARGS__)
 #else
 # define mferr(x...)
+# define mfinfo(x...)
 #endif
 
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Public Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
@@ -92,36 +82,36 @@ int up_memfault(int irq, FAR void *context)
   /* Dump some memory management fault info */
 
   (void)up_irq_save();
-  _llerr("PANIC!!! Memory Management Fault:\n");
-  mferr("  IRQ: %d context: %p\n", irq, regs);
-  _llerr("  CFAULTS: %08x MMFAR: %08x\n",
+  _alert("PANIC!!! Memory Management Fault:\n");
+  mfinfo("  IRQ: %d context: %p\n", irq, regs);
+  _alert("  CFAULTS: %08x MMFAR: %08x\n",
         getreg32(NVIC_CFAULTS), getreg32(NVIC_MEMMANAGE_ADDR));
-  mferr("  BASEPRI: %08x PRIMASK: %08x IPSR: %08x CONTROL: %08x\n",
-        getbasepri(), getprimask(), getipsr(), getcontrol());
-  mferr("  R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
-        regs[REG_R0],  regs[REG_R1],  regs[REG_R2],  regs[REG_R3],
-        regs[REG_R4],  regs[REG_R5],  regs[REG_R6],  regs[REG_R7]);
-  mferr("  R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
-        regs[REG_R8],  regs[REG_R9],  regs[REG_R10], regs[REG_R11],
-        regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
+  mfinfo("  BASEPRI: %08x PRIMASK: %08x IPSR: %08x CONTROL: %08x\n",
+         getbasepri(), getprimask(), getipsr(), getcontrol());
+  mfinfo("  R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+         regs[REG_R0],  regs[REG_R1],  regs[REG_R2],  regs[REG_R3],
+         regs[REG_R4],  regs[REG_R5],  regs[REG_R6],  regs[REG_R7]);
+  mfinfo("  R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+         regs[REG_R8],  regs[REG_R9],  regs[REG_R10], regs[REG_R11],
+         regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
 
 #ifdef CONFIG_ARMV7M_USEBASEPRI
 #  ifdef REG_EXC_RETURN
-  mferr("  xPSR: %08x BASEPRI: %08x EXC_RETURN: %08x (saved)\n",
-        CURRENT_REGS[REG_XPSR],  CURRENT_REGS[REG_BASEPRI],
-        CURRENT_REGS[REG_EXC_RETURN]);
+  mfinfo("  xPSR: %08x BASEPRI: %08x EXC_RETURN: %08x (saved)\n",
+         CURRENT_REGS[REG_XPSR],  CURRENT_REGS[REG_BASEPRI],
+         CURRENT_REGS[REG_EXC_RETURN]);
 #  else
-  mferr("  xPSR: %08x BASEPRI: %08x (saved)\n",
-        CURRENT_REGS[REG_XPSR],  CURRENT_REGS[REG_BASEPRI]);
+  mfinfo("  xPSR: %08x BASEPRI: %08x (saved)\n",
+         CURRENT_REGS[REG_XPSR],  CURRENT_REGS[REG_BASEPRI]);
 #  endif
 #else
 #  ifdef REG_EXC_RETURN
-  mferr("  xPSR: %08x PRIMASK: %08x EXC_RETURN: %08x (saved)\n",
-        CURRENT_REGS[REG_XPSR],  CURRENT_REGS[REG_PRIMASK],
-        CURRENT_REGS[REG_EXC_RETURN]);
+  mfinfo("  xPSR: %08x PRIMASK: %08x EXC_RETURN: %08x (saved)\n",
+         CURRENT_REGS[REG_XPSR],  CURRENT_REGS[REG_PRIMASK],
+         CURRENT_REGS[REG_EXC_RETURN]);
 #  else
-  mferr("  xPSR: %08x PRIMASK: %08x (saved)\n",
-        CURRENT_REGS[REG_XPSR],  CURRENT_REGS[REG_PRIMASK]);
+  mfinfo("  xPSR: %08x PRIMASK: %08x (saved)\n",
+         CURRENT_REGS[REG_XPSR],  CURRENT_REGS[REG_PRIMASK]);
 #  endif
 #endif
 
diff --git a/arch/arm/src/armv7-m/up_releasepending.c b/arch/arm/src/armv7-m/up_releasepending.c
index 489e3537e11..83be88094e7 100644
--- a/arch/arm/src/armv7-m/up_releasepending.c
+++ b/arch/arm/src/armv7-m/up_releasepending.c
@@ -66,7 +66,7 @@ void up_release_pending(void)
 {
   struct tcb_s *rtcb = this_task();
 
-  sllerr("From TCB=%p\n", rtcb);
+  sinfo("From TCB=%p\n", rtcb);
 
   /* Merge the g_pendingtasks list into the ready-to-run task list */
 
diff --git a/arch/arm/src/armv7-m/up_reprioritizertr.c b/arch/arm/src/armv7-m/up_reprioritizertr.c
index 61b592be05b..5e65a3d3383 100644
--- a/arch/arm/src/armv7-m/up_reprioritizertr.c
+++ b/arch/arm/src/armv7-m/up_reprioritizertr.c
@@ -94,7 +94,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority)
       struct tcb_s *rtcb = this_task();
       bool switch_needed;
 
-      sllerr("TCB=%p PRI=%d\n", tcb, priority);
+      sinfo("TCB=%p PRI=%d\n", tcb, priority);
 
       /* Remove the tcb task from the ready-to-run list.
        * sched_removereadytorun will return true if we just removed the head
diff --git a/arch/arm/src/armv7-m/up_schedulesigaction.c b/arch/arm/src/armv7-m/up_schedulesigaction.c
index d24906dd3be..cf70662510c 100644
--- a/arch/arm/src/armv7-m/up_schedulesigaction.c
+++ b/arch/arm/src/armv7-m/up_schedulesigaction.c
@@ -95,7 +95,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
 {
   irqstate_t flags;
 
-  serr("tcb=0x%p sigdeliver=0x%p\n", tcb, sigdeliver);
+  sinfo("tcb=0x%p sigdeliver=0x%p\n", tcb, sigdeliver);
   DEBUGASSERT(tcb != NULL && sigdeliver != NULL);
 
   /* Make sure that interrupts are disabled */
@@ -110,7 +110,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
        * to the currently executing task.
        */
 
-      serr("rtcb=0x%p CURRENT_REGS=0x%p\n", this_task(), CURRENT_REGS);
+      sinfo("rtcb=0x%p CURRENT_REGS=0x%p\n", this_task(), CURRENT_REGS);
 
       if (tcb == this_task())
         {
diff --git a/arch/arm/src/armv7-m/up_sigdeliver.c b/arch/arm/src/armv7-m/up_sigdeliver.c
index 16f05b5adcb..6169b512796 100644
--- a/arch/arm/src/armv7-m/up_sigdeliver.c
+++ b/arch/arm/src/armv7-m/up_sigdeliver.c
@@ -95,7 +95,7 @@ void up_sigdeliver(void)
 
   board_autoled_on(LED_SIGNAL);
 
-  serr("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n",
+  sinfo("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n",
         rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head);
   ASSERT(rtcb->xcp.sigdeliver != NULL);
 
@@ -138,7 +138,7 @@ void up_sigdeliver(void)
    * errno that is needed by the user logic (it is probably EINTR).
    */
 
-  serr("Resuming\n");
+  sinfo("Resuming\n");
   (void)up_irq_save();
   rtcb->pterrno = saved_errno;
 
diff --git a/arch/arm/src/armv7-m/up_svcall.c b/arch/arm/src/armv7-m/up_svcall.c
index 63f229a0481..8e78de3a432 100644
--- a/arch/arm/src/armv7-m/up_svcall.c
+++ b/arch/arm/src/armv7-m/up_svcall.c
@@ -142,18 +142,18 @@ int up_svcall(int irq, FAR void *context)
   if (cmd > SYS_switch_context)
 # endif
     {
-      svcllinfo("SVCALL Entry: regs: %p cmd: %d\n", regs, cmd);
-      svcllinfo("  R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
-                regs[REG_R0],  regs[REG_R1],  regs[REG_R2],  regs[REG_R3],
-                regs[REG_R4],  regs[REG_R5],  regs[REG_R6],  regs[REG_R7]);
-      svcllinfo("  R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
-                regs[REG_R8],  regs[REG_R9],  regs[REG_R10], regs[REG_R11],
-                regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
+      svcinfo("SVCALL Entry: regs: %p cmd: %d\n", regs, cmd);
+      svcinfo("  R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+              regs[REG_R0],  regs[REG_R1],  regs[REG_R2],  regs[REG_R3],
+              regs[REG_R4],  regs[REG_R5],  regs[REG_R6],  regs[REG_R7]);
+      svcinfo("  R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+              regs[REG_R8],  regs[REG_R9],  regs[REG_R10], regs[REG_R11],
+              regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
 # ifdef REG_EXC_RETURN
-      svcllinfo(" PSR: %08x EXC_RETURN: %08x\n",
-                regs[REG_XPSR], regs[REG_EXC_RETURN]);
+      svcinfo(" PSR: %08x EXC_RETURN: %08x\n",
+              regs[REG_XPSR], regs[REG_EXC_RETURN]);
 # else
-      svcllinfo(" PSR: %08x\n", regs[REG_XPSR]);
+      svcinfo(" PSR: %08x\n", regs[REG_XPSR]);
 # endif
     }
 #endif
@@ -446,7 +446,7 @@ int up_svcall(int irq, FAR void *context)
 
           regs[REG_R0] -= CONFIG_SYS_RESERVED;
 #else
-          svcllerr("ERROR: Bad SYS call: %d\n", regs[REG_R0]);
+          svcerr("ERROR: Bad SYS call: %d\n", regs[REG_R0]);
 #endif
         }
         break;
@@ -461,28 +461,28 @@ int up_svcall(int irq, FAR void *context)
   if (regs != CURRENT_REGS)
 # endif
     {
-      svcllinfo("SVCall Return:\n");
-      svcllinfo("  R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
-                CURRENT_REGS[REG_R0],  CURRENT_REGS[REG_R1],
-                CURRENT_REGS[REG_R2],  CURRENT_REGS[REG_R3],
-                CURRENT_REGS[REG_R4],  CURRENT_REGS[REG_R5],
-                CURRENT_REGS[REG_R6],  CURRENT_REGS[REG_R7]);
-      svcllinfo("  R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
-                CURRENT_REGS[REG_R8],  CURRENT_REGS[REG_R9],
-                CURRENT_REGS[REG_R10], CURRENT_REGS[REG_R11],
-                CURRENT_REGS[REG_R12], CURRENT_REGS[REG_R13],
-                CURRENT_REGS[REG_R14], CURRENT_REGS[REG_R15]);
+      svcinfo("SVCall Return:\n");
+      svcinfo("  R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+              CURRENT_REGS[REG_R0],  CURRENT_REGS[REG_R1],
+              CURRENT_REGS[REG_R2],  CURRENT_REGS[REG_R3],
+              CURRENT_REGS[REG_R4],  CURRENT_REGS[REG_R5],
+              CURRENT_REGS[REG_R6],  CURRENT_REGS[REG_R7]);
+      svcinfo("  R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+              CURRENT_REGS[REG_R8],  CURRENT_REGS[REG_R9],
+              CURRENT_REGS[REG_R10], CURRENT_REGS[REG_R11],
+              CURRENT_REGS[REG_R12], CURRENT_REGS[REG_R13],
+              CURRENT_REGS[REG_R14], CURRENT_REGS[REG_R15]);
 # ifdef REG_EXC_RETURN
-      svcllinfo(" PSR: %08x EXC_RETURN: %08x\n",
-                CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_EXC_RETURN]);
+      svcinfo(" PSR: %08x EXC_RETURN: %08x\n",
+              CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_EXC_RETURN]);
 # else
-      svcllinfo(" PSR: %08x\n", CURRENT_REGS[REG_XPSR]);
+      svcinfo(" PSR: %08x\n", CURRENT_REGS[REG_XPSR]);
 # endif
     }
 # ifdef CONFIG_DEBUG_SVCALL
   else
     {
-      svcllinfo("SVCall Return: %d\n", regs[REG_R0]);
+      svcinfo("SVCall Return: %d\n", regs[REG_R0]);
     }
 # endif
 #endif
diff --git a/arch/arm/src/armv7-r/arm_assert.c b/arch/arm/src/armv7-r/arm_assert.c
index b6f6b23546d..b841416450b 100644
--- a/arch/arm/src/armv7-r/arm_assert.c
+++ b/arch/arm/src/armv7-r/arm_assert.c
@@ -98,7 +98,7 @@ static void up_stackdump(uint32_t sp, uint32_t stack_base)
   for (stack = sp & ~0x1f; stack < stack_base; stack += 32)
     {
       uint32_t *ptr = (uint32_t *)stack;
-      _llerr("%08x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+      _alert("%08x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
              stack, ptr[0], ptr[1], ptr[2], ptr[3],
              ptr[4], ptr[5], ptr[6], ptr[7]);
     }
@@ -117,11 +117,11 @@ static void up_taskdump(FAR struct tcb_s *tcb, FAR void *arg)
   /* Dump interesting properties of this task */
 
 #if CONFIG_TASK_NAME_SIZE > 0
-  _llerr("%s: PID=%d Stack Used=%lu of %lu\n",
+  _alert("%s: PID=%d Stack Used=%lu of %lu\n",
         tcb->name, tcb->pid, (unsigned long)up_check_tcbstack(tcb),
         (unsigned long)tcb->adj_stack_size);
 #else
-  _llerr("PID: %d Stack Used=%lu of %lu\n",
+  _alert("PID: %d Stack Used=%lu of %lu\n",
         tcb->pid, (unsigned long)up_check_tcbstack(tcb),
         (unsigned long)tcb->adj_stack_size);
 #endif
@@ -161,12 +161,12 @@ static inline void up_registerdump(void)
       for (regs = REG_R0; regs <= REG_R15; regs += 8)
         {
           uint32_t *ptr = (uint32_t *)&CURRENT_REGS[regs];
-          _llerr("R%d: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+          _alert("R%d: %08x %08x %08x %08x %08x %08x %08x %08x\n",
                  regs, ptr[0], ptr[1], ptr[2], ptr[3],
                  ptr[4], ptr[5], ptr[6], ptr[7]);
         }
 
-      _llerr("CPSR: %08x\n", CURRENT_REGS[REG_CPSR]);
+      _alert("CPSR: %08x\n", CURRENT_REGS[REG_CPSR]);
     }
 }
 #else
@@ -186,7 +186,7 @@ static int usbtrace_syslog(FAR const char *fmt, ...)
   /* Let vsyslog do the real work */
 
   va_start(ap, fmt);
-  ret = lowvsyslog(LOG_INFO, fmt, ap);
+  ret = vsyslog(LOG_EMERG, fmt, ap);
   va_end(ap);
   return ret;
 }
@@ -230,7 +230,7 @@ static void up_dumpstate(void)
       ustacksize = (uint32_t)rtcb->adj_stack_size;
     }
 
-  _llerr("Current sp: %08x\n", sp);
+  _alert("Current sp: %08x\n", sp);
 
 #if CONFIG_ARCH_INTERRUPTSTACK > 3
   /* Get the limits on the interrupt stack memory */
@@ -240,21 +240,21 @@ static void up_dumpstate(void)
 
   /* Show interrupt stack info */
 
-  _llerr("Interrupt stack:\n");
-  _llerr("  base: %08x\n", istackbase);
-  _llerr("  size: %08x\n", istacksize);
+  _alert("Interrupt stack:\n");
+  _alert("  base: %08x\n", istackbase);
+  _alert("  size: %08x\n", istacksize);
 #ifdef CONFIG_STACK_COLORATION
-  _llerr("  used: %08x\n", up_check_intstack());
+  _alert("  used: %08x\n", up_check_intstack());
 #endif
 #endif
 
   /* Show user stack info */
 
-  _llerr("User stack:\n");
-  _llerr("  base: %08x\n", ustackbase);
-  _llerr("  size: %08x\n", ustacksize);
+  _alert("User stack:\n");
+  _alert("  base: %08x\n", ustackbase);
+  _alert("  size: %08x\n", ustacksize);
 #ifdef CONFIG_STACK_COLORATION
-  _llerr("  used: %08x\n", up_check_tcbstack(rtcb));
+  _alert("  used: %08x\n", up_check_tcbstack(rtcb));
 #endif
 
 #ifdef CONFIG_ARCH_KERNEL_STACK
@@ -264,9 +264,9 @@ static void up_dumpstate(void)
     {
       kstackbase = (uint32_t)rtcb->xcp.kstack + CONFIG_ARCH_KERNEL_STACKSIZE - 4;
 
-      _llerr("Kernel stack:\n");
-      _llerr("  base: %08x\n", kstackbase);
-      _llerr("  size: %08x\n", CONFIG_ARCH_KERNEL_STACKSIZE);
+      _alert("Kernel stack:\n");
+      _alert("  base: %08x\n", kstackbase);
+      _alert("  size: %08x\n", CONFIG_ARCH_KERNEL_STACKSIZE);
     }
 #endif
 
@@ -277,7 +277,7 @@ static void up_dumpstate(void)
     {
       /* Yes.. dump the interrupt stack */
 
-      _llerr("Interrupt Stack\n", sp);
+      _alert("Interrupt Stack\n", sp);
       up_stackdump(sp, istackbase);
 
       /* Extract the user stack pointer which should lie
@@ -285,7 +285,7 @@ static void up_dumpstate(void)
        */
 
       sp = g_intstackbase;
-      _llerr("User sp: %08x\n", sp);
+      _alert("User sp: %08x\n", sp);
     }
 #endif
 
@@ -295,7 +295,7 @@ static void up_dumpstate(void)
 
   if (sp > ustackbase - ustacksize && sp < ustackbase)
     {
-      _llerr("User Stack\n", sp);
+      _alert("User Stack\n", sp);
       up_stackdump(sp, ustackbase);
     }
 
@@ -306,7 +306,7 @@ static void up_dumpstate(void)
 
   if (sp >= (uint32_t)rtcb->xcp.kstack && sp < kstackbase)
     {
-      _llerr("Kernel Stack\n", sp);
+      _alert("Kernel Stack\n", sp);
       up_stackdump(sp, kstackbase);
     }
 #endif
@@ -367,16 +367,16 @@ static void _up_assert(int errorcode)
 
 void up_assert(const uint8_t *filename, int lineno)
 {
-#if CONFIG_TASK_NAME_SIZE > 0
+#if CONFIG_TASK_NAME_SIZE > 0 && defined(CONFIG_DEBUG_ALERT)
   struct tcb_s *rtcb = this_task();
 #endif
   board_autoled_on(LED_ASSERTION);
 
 #if CONFIG_TASK_NAME_SIZE > 0
-  _llerr("Assertion failed at file:%s line: %d task: %s\n",
+  _alert("Assertion failed at file:%s line: %d task: %s\n",
         filename, lineno, rtcb->name);
 #else
-  _llerr("Assertion failed at file:%s line: %d\n",
+  _alert("Assertion failed at file:%s line: %d\n",
         filename, lineno);
 #endif
   up_dumpstate();
diff --git a/arch/arm/src/armv7-r/arm_elf.c b/arch/arm/src/armv7-r/arm_elf.c
index 0d7b40cd491..4ab4713b62e 100644
--- a/arch/arm/src/armv7-r/arm_elf.c
+++ b/arch/arm/src/armv7-r/arm_elf.c
@@ -86,7 +86,7 @@ bool up_checkarch(FAR const Elf32_Ehdr *ehdr)
 
   if (ehdr->e_machine != EM_ARM)
     {
-      berr("Not for ARM: e_machine=%04x\n", ehdr->e_machine);
+      berr("ERROR: Not for ARM: e_machine=%04x\n", ehdr->e_machine);
       return -ENOEXEC;
     }
 
@@ -94,7 +94,7 @@ bool up_checkarch(FAR const Elf32_Ehdr *ehdr)
 
   if (ehdr->e_ident[EI_CLASS] != ELFCLASS32)
     {
-      berr("Need 32-bit objects: e_ident[EI_CLASS]=%02x\n", ehdr->e_ident[EI_CLASS]);
+      berr("ERROR: Need 32-bit objects: e_ident[EI_CLASS]=%02x\n", ehdr->e_ident[EI_CLASS]);
       return -ENOEXEC;
     }
 
@@ -106,7 +106,7 @@ bool up_checkarch(FAR const Elf32_Ehdr *ehdr)
   if (ehdr->e_ident[EI_DATA] != ELFDATA2LSB)
 #endif
     {
-      berr("Wrong endian-ness: e_ident[EI_DATA]=%02x\n", ehdr->e_ident[EI_DATA]);
+      berr("ERROR: Wrong endian-ness: e_ident[EI_DATA]=%02x\n", ehdr->e_ident[EI_DATA]);
       return -ENOEXEC;
     }
 
@@ -114,7 +114,7 @@ bool up_checkarch(FAR const Elf32_Ehdr *ehdr)
 
   if ((ehdr->e_entry & 3) != 0)
     {
-      berr("Entry point is not properly aligned: %08x\n", ehdr->e_entry);
+      berr("ERROR: Entry point is not properly aligned: %08x\n", ehdr->e_entry);
       return -ENOEXEC;
     }
 
@@ -187,8 +187,8 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
         offset += sym->st_value - addr;
         if (offset & 3 || offset <= (int32_t) 0xfe000000 || offset >= (int32_t) 0x02000000)
           {
-            berr("  ERROR: PC24 [%d] relocation out of range, offset=%08lx\n",
-                 ELF32_R_TYPE(rel->r_info), offset);
+            berr("ERROR:   ERROR: PC24 [%d] relocation out of range, offset=%08lx\n",
+                  ELF32_R_TYPE(rel->r_info), offset);
 
             return -EINVAL;
           }
@@ -258,7 +258,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
       break;
 
     default:
-      berr("Unsupported relocation: %d\n", ELF32_R_TYPE(rel->r_info));
+      berr("ERROR: Unsupported relocation: %d\n", ELF32_R_TYPE(rel->r_info));
       return -EINVAL;
     }
 
@@ -268,6 +268,6 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
 int up_relocateadd(FAR const Elf32_Rela *rel, FAR const Elf32_Sym *sym,
                    uintptr_t addr)
 {
-  berr("RELA relocation not supported\n");
+  berr("ERROR: RELA relocation not supported\n");
   return -ENOSYS;
 }
diff --git a/arch/arm/src/armv7-r/arm_l2cc_pl310.c b/arch/arm/src/armv7-r/arm_l2cc_pl310.c
index f606dadc8af..18c3d224a2c 100644
--- a/arch/arm/src/armv7-r/arm_l2cc_pl310.c
+++ b/arch/arm/src/armv7-r/arm_l2cc_pl310.c
@@ -411,8 +411,8 @@ void up_l2ccinitialize(void)
       putreg32(L2CC_CR_L2CEN, L2CC_CR);
     }
 
-  _llerr("(%d ways) * (%d bytes/way) = %d bytes\n",
-        PL310_NWAYS, PL310_WAYSIZE, PL310_CACHE_SIZE);
+  sinfo("(%d ways) * (%d bytes/way) = %d bytes\n",
+          PL310_NWAYS, PL310_WAYSIZE, PL310_CACHE_SIZE);
 }
 
 /****************************************************************************
diff --git a/arch/arm/src/armv7-r/arm_releasepending.c b/arch/arm/src/armv7-r/arm_releasepending.c
index d65bc75be21..a66de941356 100644
--- a/arch/arm/src/armv7-r/arm_releasepending.c
+++ b/arch/arm/src/armv7-r/arm_releasepending.c
@@ -67,7 +67,7 @@ void up_release_pending(void)
 {
   struct tcb_s *rtcb = this_task();
 
-  sllerr("From TCB=%p\n", rtcb);
+  sinfo("From TCB=%p\n", rtcb);
 
   /* Merge the g_pendingtasks list into the ready-to-run task list */
 
diff --git a/arch/arm/src/armv7-r/arm_reprioritizertr.c b/arch/arm/src/armv7-r/arm_reprioritizertr.c
index 192bff007d9..db96424eb2f 100644
--- a/arch/arm/src/armv7-r/arm_reprioritizertr.c
+++ b/arch/arm/src/armv7-r/arm_reprioritizertr.c
@@ -95,7 +95,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority)
       struct tcb_s *rtcb = this_task();
       bool switch_needed;
 
-      sllerr("TCB=%p PRI=%d\n", tcb, priority);
+      sinfo("TCB=%p PRI=%d\n", tcb, priority);
 
       /* Remove the tcb task from the ready-to-run list.
        * sched_removereadytorun will return true if we just
diff --git a/arch/arm/src/armv7-r/arm_schedulesigaction.c b/arch/arm/src/armv7-r/arm_schedulesigaction.c
index 3ece5d8acfa..a51d660cb4c 100644
--- a/arch/arm/src/armv7-r/arm_schedulesigaction.c
+++ b/arch/arm/src/armv7-r/arm_schedulesigaction.c
@@ -94,7 +94,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
 {
   irqstate_t flags;
 
-  serr("tcb=0x%p sigdeliver=0x%p\n", tcb, sigdeliver);
+  sinfo("tcb=0x%p sigdeliver=0x%p\n", tcb, sigdeliver);
 
   /* Make sure that interrupts are disabled */
 
@@ -108,7 +108,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
        * to the currently executing task.
        */
 
-      serr("rtcb=0x%p CURRENT_REGS=0x%p\n", this_task(), CURRENT_REGS);
+      sinfo("rtcb=0x%p CURRENT_REGS=0x%p\n", this_task(), CURRENT_REGS);
 
       if (tcb == this_task())
         {
diff --git a/arch/arm/src/armv7-r/arm_sigdeliver.c b/arch/arm/src/armv7-r/arm_sigdeliver.c
index 1a4f9b966d7..280a5ef9c71 100644
--- a/arch/arm/src/armv7-r/arm_sigdeliver.c
+++ b/arch/arm/src/armv7-r/arm_sigdeliver.c
@@ -83,7 +83,7 @@ void up_sigdeliver(void)
 
   board_autoled_on(LED_SIGNAL);
 
-  serr("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n",
+  sinfo("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n",
         rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head);
   ASSERT(rtcb->xcp.sigdeliver != NULL);
 
@@ -114,7 +114,7 @@ void up_sigdeliver(void)
    * errno that is needed by the user logic (it is probably EINTR).
    */
 
-  serr("Resuming\n");
+  sinfo("Resuming\n");
   (void)up_irq_save();
   rtcb->pterrno = saved_errno;
 
diff --git a/arch/arm/src/armv7-r/arm_syscall.c b/arch/arm/src/armv7-r/arm_syscall.c
index 7d36ccb0d9c..49290d5509e 100644
--- a/arch/arm/src/armv7-r/arm_syscall.c
+++ b/arch/arm/src/armv7-r/arm_syscall.c
@@ -154,14 +154,14 @@ uint32_t *arm_syscall(uint32_t *regs)
    * and R1..R7 =  variable number of arguments depending on the system call.
    */
 
-  svcllinfo("SYSCALL Entry: regs: %p cmd: %d\n", regs, cmd);
-  svcllinfo("  R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
-            regs[REG_R0],  regs[REG_R1],  regs[REG_R2],  regs[REG_R3],
-            regs[REG_R4],  regs[REG_R5],  regs[REG_R6],  regs[REG_R7]);
-  svcllinfo("  R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
-            regs[REG_R8],  regs[REG_R9],  regs[REG_R10], regs[REG_R11],
-            regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
-  svcllinfo("CPSR: %08x\n", regs[REG_CPSR]);
+  svcinfo("SYSCALL Entry: regs: %p cmd: %d\n", regs, cmd);
+  svcinfo("  R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+          regs[REG_R0],  regs[REG_R1],  regs[REG_R2],  regs[REG_R3],
+          regs[REG_R4],  regs[REG_R5],  regs[REG_R6],  regs[REG_R7]);
+  svcinfo("  R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+          regs[REG_R8],  regs[REG_R9],  regs[REG_R10], regs[REG_R11],
+          regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
+  svcinfo("CPSR: %08x\n", regs[REG_CPSR]);
 
   /* Handle the SVCall according to the command in R0 */
 
@@ -454,7 +454,7 @@ uint32_t *arm_syscall(uint32_t *regs)
 
           regs[REG_R0] -= CONFIG_SYS_RESERVED;
 #else
-          svcllerr("ERROR: Bad SYS call: %d\n", regs[REG_R0]);
+          svcerr("ERROR: Bad SYS call: %d\n", regs[REG_R0]);
 #endif
 
 #ifdef CONFIG_ARCH_KERNEL_STACK
@@ -477,14 +477,14 @@ uint32_t *arm_syscall(uint32_t *regs)
 
   /* Report what happened */
 
-  svcllinfo("SYSCALL Exit: regs: %p\n", regs);
-  svcllinfo("  R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
-            regs[REG_R0],  regs[REG_R1],  regs[REG_R2],  regs[REG_R3],
-            regs[REG_R4],  regs[REG_R5],  regs[REG_R6],  regs[REG_R7]);
-  svcllinfo("  R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
-            regs[REG_R8],  regs[REG_R9],  regs[REG_R10], regs[REG_R11],
-            regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
-  svcllinfo("CPSR: %08x\n", regs[REG_CPSR]);
+  svcinfo("SYSCALL Exit: regs: %p\n", regs);
+  svcinfo("  R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+          regs[REG_R0],  regs[REG_R1],  regs[REG_R2],  regs[REG_R3],
+          regs[REG_R4],  regs[REG_R5],  regs[REG_R6],  regs[REG_R7]);
+  svcinfo("  R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+          regs[REG_R8],  regs[REG_R9],  regs[REG_R10], regs[REG_R11],
+          regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
+  svcinfo("CPSR: %08x\n", regs[REG_CPSR]);
 
   /* Return the last value of curent_regs.  This supports context switches
    * on return from the exception.  That capability is only used with the
diff --git a/arch/arm/src/armv7-r/mpu.h b/arch/arm/src/armv7-r/mpu.h
index 07b19697601..e9e29cf13f8 100644
--- a/arch/arm/src/armv7-r/mpu.h
+++ b/arch/arm/src/armv7-r/mpu.h
@@ -359,12 +359,12 @@ static inline void mpu_set_rgnr(unsigned int rgnr)
 
 static inline void mpu_showtype(void)
 {
-#ifdef CONFIG_DEBUG_FEATURES
+#ifdef CONFIG_DEBUG_SCHED_INFO
   uint32_t regval = mpu_get_mpuir();
-  _err("%s MPU Regions: data=%d instr=%d\n",
-      (regval & MPUIR_SEPARATE) != 0 ? "Separate" : "Unified",
-      (regval & MPUIR_DREGION_MASK) >> MPUIR_DREGION_SHIFT,
-      (regval & MPUIR_IREGION_MASK) >> MPUIR_IREGION_SHIFT);
+  sinfo("%s MPU Regions: data=%d instr=%d\n",
+        (regval & MPUIR_SEPARATE) != 0 ? "Separate" : "Unified",
+        (regval & MPUIR_DREGION_MASK) >> MPUIR_DREGION_SHIFT,
+        (regval & MPUIR_IREGION_MASK) >> MPUIR_IREGION_SHIFT);
 #endif
 }
 
diff --git a/arch/arm/src/c5471/c5471_ethernet.c b/arch/arm/src/c5471/c5471_ethernet.c
index 38d894e74e5..b7563aa0545 100644
--- a/arch/arm/src/c5471/c5471_ethernet.c
+++ b/arch/arm/src/c5471/c5471_ethernet.c
@@ -737,22 +737,22 @@ static int c5471_phyinit (void)
   phyid = (c5471_mdread(0, MD_PHY_MSB_REG) << 16) | c5471_mdread(0, MD_PHY_LSB_REG);
   if (phyid != LU3X31_T64_PHYID)
     {
-      nerr("Unrecognized PHY ID: %08x\n", phyid);
+      nerr("ERROR: Unrecognized PHY ID: %08x\n", phyid);
       return ERROR;
     }
 
   /* Next, Set desired network rate, 10BaseT, 100BaseT, or auto. */
 
 #ifdef CONFIG_C5471_AUTONEGOTIATION
-  nerr("Setting PHY Transceiver for Autonegotiation\n");
+  ninfo("Setting PHY Transceiver for Autonegotiation\n");
   c5471_mdwrite(0, MD_PHY_CONTROL_REG, MODE_AUTONEG);
 #endif
 #ifdef CONFIG_C5471_BASET100
-  nerr("Setting PHY Transceiver for 100BaseT FullDuplex\n");
+  ninfo("Setting PHY Transceiver for 100BaseT FullDuplex\n");
   c5471_mdwrite(0, MD_PHY_CONTROL_REG, MODE_100MBIT_FULLDUP);
 #endif
 #ifdef CONFIG_C5471_BASET10
-  nerr("Setting PHY Transceiver for 10BaseT FullDuplex\n");
+  ninfo("Setting PHY Transceiver for 10BaseT FullDuplex\n");
   c5471_mdwrite(0, MD_PHY_CONTROL_REG, MODE_10MBIT_FULLDUP);
 #endif
 
@@ -1267,7 +1267,7 @@ static void c5471_receive(struct c5471_driver_s *c5471)
 #ifdef CONFIG_NET_IPv4
       if (BUF->type == HTONS(ETHTYPE_IP))
         {
-          nllinfo("IPv4 frame\n");
+          ninfo("IPv4 frame\n");
 
           /* Handle ARP on input then give the IPv4 packet to the network
            * layer
@@ -1310,7 +1310,7 @@ static void c5471_receive(struct c5471_driver_s *c5471)
 #ifdef CONFIG_NET_IPv6
       if (BUF->type == HTONS(ETHTYPE_IP6))
         {
-          nllinfo("Iv6 frame\n");
+          ninfo("Iv6 frame\n");
 
           /* Give the IPv6 packet to the network layer */
 
@@ -1371,7 +1371,7 @@ static void c5471_receive(struct c5471_driver_s *c5471)
     {
       /* Increment the count of dropped packets */
 
-      nerr("Too big! packetlen: %d\n", packetlen);
+      nwarn("WARNING: Too big! packetlen: %d\n", packetlen);
       c5471->c_rxdropped++;
     }
 #endif
@@ -1680,9 +1680,9 @@ static int c5471_ifup(struct net_driver_s *dev)
   struct c5471_driver_s *c5471 = (struct c5471_driver_s *)dev->d_private;
   volatile uint32_t clearbits;
 
-  nerr("Bringing up: %d.%d.%d.%d\n",
-       dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff,
-       (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24);
+  ninfo("Bringing up: %d.%d.%d.%d\n",
+        dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff,
+        (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24);
 
   /* Initilize Ethernet interface */
 
@@ -1742,7 +1742,7 @@ static int c5471_ifdown(struct net_driver_s *dev)
   struct c5471_driver_s *c5471 = (struct c5471_driver_s *)dev->d_private;
   irqstate_t flags;
 
-  nerr("Stopping\n");
+  ninfo("Stopping\n");
 
   /* Disable the Ethernet interrupt */
 
@@ -1798,7 +1798,7 @@ static int c5471_txavail(struct net_driver_s *dev)
   struct c5471_driver_s *c5471 = (struct c5471_driver_s *)dev->d_private;
   irqstate_t flags;
 
-  nerr("Polling\n");
+  ninfo("Polling\n");
   flags = enter_critical_section();
 
   /* Ignore the notification if the interface is not yet up */
@@ -1951,7 +1951,7 @@ static void c5471_eimconfig(struct c5471_driver_s *c5471)
 
   /* TX ENET 0 */
 
-  nerr("TX ENET0 desc: %08x pbuf: %08x\n", desc, pbuf);
+  ninfo("TX ENET0 desc: %08x pbuf: %08x\n", desc, pbuf);
   putreg32((desc & 0x0000ffff), ENET0_TDBA); /* 16-bit offset address */
   for (i = NUM_DESC_TX-1; i >= 0; i--)
     {
@@ -1978,7 +1978,7 @@ static void c5471_eimconfig(struct c5471_driver_s *c5471)
 
   /* RX ENET 0 */
 
-  nerr("RX ENET0 desc: %08x pbuf: %08x\n", desc, pbuf);
+  ninfo("RX ENET0 desc: %08x pbuf: %08x\n", desc, pbuf);
   putreg32((desc & 0x0000ffff), ENET0_RDBA); /* 16-bit offset address */
   for (i = NUM_DESC_RX-1; i >= 0; i--)
     {
@@ -2005,7 +2005,7 @@ static void c5471_eimconfig(struct c5471_driver_s *c5471)
 
   /* TX CPU */
 
-  nerr("TX CPU desc: %08x pbuf: %08x\n", desc, pbuf);
+  ninfo("TX CPU desc: %08x pbuf: %08x\n", desc, pbuf);
   c5471->c_txcpudesc = desc;
   putreg32((desc & 0x0000ffff), EIM_CPU_TXBA); /* 16-bit offset address */
   for (i = NUM_DESC_TX-1; i >= 0; i--)
@@ -2035,7 +2035,7 @@ static void c5471_eimconfig(struct c5471_driver_s *c5471)
 
   /* RX CPU */
 
-  nerr("RX CPU desc: %08x pbuf: %08x\n", desc, pbuf);
+  ninfo("RX CPU desc: %08x pbuf: %08x\n", desc, pbuf);
   c5471->c_rxcpudesc = desc;
   putreg32((desc & 0x0000ffff), EIM_CPU_RXBA); /* 16-bit offset address */
   for (i = NUM_DESC_RX-1; i >= 0; i--)
@@ -2063,7 +2063,7 @@ static void c5471_eimconfig(struct c5471_driver_s *c5471)
       pbuf += sizeof(uint32_t); /* Ether Module's "Buffer Usage Word" */
     }
 
-  nerr("END desc: %08x pbuf: %08x\n", desc, pbuf);
+  ninfo("END desc: %08x pbuf: %08x\n", desc, pbuf);
 
   /* Save the descriptor packet size */
 
@@ -2150,13 +2150,13 @@ static void c5471_eimconfig(struct c5471_driver_s *c5471)
 static void c5471_reset(struct c5471_driver_s *c5471)
 {
 #if defined(CONFIG_C5471_PHY_LU3X31T_T64)
-  nerr("EIM reset\n");
+  ninfo("EIM reset\n");
   c5471_eimreset(c5471);
 #endif
-  nerr("PHY init\n");
+  ninfo("PHY init\n");
   c5471_phyinit();
 
-  nerr("EIM config\n");
+  ninfo("EIM config\n");
   c5471_eimconfig(c5471);
 }
 
@@ -2178,7 +2178,7 @@ static void c5471_macassign(struct c5471_driver_s *c5471)
   uint8_t *mptr = dev->d_mac.ether_addr_octet;
   register uint32_t tmp;
 
-  nerr("MAC: %0x:%0x:%0x:%0x:%0x:%0x\n",
+  ninfo("MAC: %0x:%0x:%0x:%0x:%0x:%0x\n",
         mptr[0], mptr[1], mptr[2], mptr[3], mptr[4], mptr[5]);
 
   /* Set CPU port MAC address. S/W will only see incoming packets that match
@@ -2241,7 +2241,7 @@ void up_netinitialize(void)
     {
       /* We could not attach the ISR to the ISR */
 
-      nllerr("irq_attach() failed\n");
+      nerr("ERROR: irq_attach() failed\n");
       return;
     }
 
diff --git a/arch/arm/src/c5471/c5471_watchdog.c b/arch/arm/src/c5471/c5471_watchdog.c
index 51363ec8df1..d1381f45d46 100644
--- a/arch/arm/src/c5471/c5471_watchdog.c
+++ b/arch/arm/src/c5471/c5471_watchdog.c
@@ -155,7 +155,7 @@ static inline unsigned int wdt_prescaletoptv(unsigned int prescale)
         }
     }
 
-  _err("prescale=%d -> ptv=%d\n", prescale, ptv);
+  wdinfo("prescale=%d -> ptv=%d\n", prescale, ptv);
   return ptv;
 }
 
@@ -173,7 +173,7 @@ static int wdt_setusec(uint32_t usec)
   uint32_t divisor   = 1;
   uint32_t mode;
 
-  _err("usec=%d\n", usec);
+  wdinfo("usec=%d\n", usec);
 
   /* Calculate a value of prescaler and divisor that will be able
    * to count to the usec.  It may not be exact or the best
@@ -186,7 +186,7 @@ static int wdt_setusec(uint32_t usec)
   do
     {
       divisor = (CLOCK_MHZx2 * usec) / (prescaler * 2);
-      _err("divisor=0x%x prescaler=0x%x\n", divisor, prescaler);
+      wdinfo("divisor=0x%x prescaler=0x%x\n", divisor, prescaler);
 
       if (divisor >= 0x10000)
         {
@@ -194,7 +194,7 @@ static int wdt_setusec(uint32_t usec)
             {
               /* This is the max possible ~2.5 seconds. */
 
-              _err("prescaler=0x%x too big!\n", prescaler);
+              wderr("ERROR: prescaler=0x%x too big!\n", prescaler);
               return ERROR;
             }
 
@@ -207,19 +207,19 @@ static int wdt_setusec(uint32_t usec)
     }
   while (divisor >= 0x10000);
 
-  _err("prescaler=0x%x divisor=0x%x\n", prescaler, divisor);
+  wdinfo("prescaler=0x%x divisor=0x%x\n", prescaler, divisor);
 
   mode  = wdt_prescaletoptv(prescaler);
   mode &= ~C5471_TIMER_AUTORELOAD; /* One shot mode. */
   mode |= divisor << 5;
-  _err("mode=0x%x\n", mode);
+  wdinfo("mode=0x%x\n", mode);
 
   c5471_wdt_cntl = mode;
 
   /* Now start the watchdog */
 
   c5471_wdt_cntl |= C5471_TIMER_STARTBIT;
-  _err("cntl_timer=0x%x\n", c5471_wdt_cntl);
+  wdinfo("cntl_timer=0x%x\n", c5471_wdt_cntl);
 
   return 0;
 }
@@ -234,17 +234,17 @@ static int wdt_setusec(uint32_t usec)
 
 static int wdt_interrupt(int irq, void *context)
 {
-  _err("expired\n");
+  wdinfo("expired\n");
 
 #if defined(CONFIG_SOFTWARE_REBOOT)
 #  if defined(CONFIG_SOFTWARE_TEST)
-  _err("  Test only\n");
+  wdinfo("  Test only\n");
 #  else
-  _err("  Re-booting\n");
+  wdinfo("  Re-booting\n");
 #    warning "Add logic to reset CPU here"
 #  endif
 #else
-  _err("  No reboot\n");
+  wdinfo("  No reboot\n");
 #endif
   return OK;
 }
@@ -259,7 +259,7 @@ static ssize_t wdt_read(struct file *filep, char *buffer, size_t buflen)
    * not work if the user provides a buffer smaller than 18 bytes.
    */
 
-  _err("buflen=%d\n", buflen);
+  wdinfo("buflen=%d\n", buflen);
   if (buflen >= 18)
     {
       sprintf(buffer, "%08x %08x\n", c5471_wdt_cntl, c5471_wdt_count);
@@ -274,7 +274,7 @@ static ssize_t wdt_read(struct file *filep, char *buffer, size_t buflen)
 
 static ssize_t wdt_write(struct file *filep, const char *buffer, size_t buflen)
 {
-  _err("buflen=%d\n", buflen);
+  wdinfo("buflen=%d\n", buflen);
   if (buflen)
     {
       /* Reset the timer to the maximum delay */
@@ -292,7 +292,7 @@ static ssize_t wdt_write(struct file *filep, const char *buffer, size_t buflen)
 
 static int wdt_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
 {
-  _err("ioctl Call: cmd=0x%x arg=0x%x", cmd, arg);
+  wdinfo("ioctl Call: cmd=0x%x arg=0x%x", cmd, arg);
 
   /* Process the IOCTL command (see arch/watchdog.h) */
 
@@ -315,8 +315,6 @@ static int wdt_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
 
 static int wdt_open(struct file *filep)
 {
-  _err("");
-
   if (g_wdtopen)
     {
       return -EBUSY;
@@ -339,11 +337,8 @@ static int wdt_open(struct file *filep)
 
 static int wdt_close(struct file *filep)
 {
-  _err("");
-
   /* The task controlling the watchdog has terminated.  Take the timer
-   *  the
-   * watchdog in interrupt mode -- we are going to reset unless the
+   * the watchdog in interrupt mode -- we are going to reset unless the
    * reopened again soon.
    */
 
@@ -367,7 +362,7 @@ int up_wdtinit(void)
 {
   int ret;
 
-  _err("C547x Watchdog Driver\n");
+  wdinfo("C547x Watchdog Driver\n");
 
   /* Register as /dev/wdt */
 
@@ -379,7 +374,7 @@ int up_wdtinit(void)
 
   /* Register for an interrupt level callback through wdt_interrupt */
 
-  _err("Attach to IRQ=%d\n", C5471_IRQ_WATCHDOG);
+  wdinfo("Attach to IRQ=%d\n", C5471_IRQ_WATCHDOG);
 
   /* Make sure that the timer is stopped */
 
diff --git a/arch/arm/src/calypso/calypso_spi.c b/arch/arm/src/calypso/calypso_spi.c
index 6278c32707b..36727927c43 100644
--- a/arch/arm/src/calypso/calypso_spi.c
+++ b/arch/arm/src/calypso/calypso_spi.c
@@ -216,8 +216,8 @@ int spi_xfer(uint8_t dev_idx, uint8_t bitlen, const void *dout, void *din)
       tmp <<= (32-bitlen);    /* align to MSB */
     }
 
-  _err("spi_xfer(dev_idx=%u, bitlen=%u, data_out=0x%08x): ",
-      dev_idx, bitlen, tmp);
+  spiinfo("spi_xfer(dev_idx=%u, bitlen=%u, data_out=0x%08x): ",
+          dev_idx, bitlen, tmp);
 
   /* fill transmit registers */
 
@@ -236,14 +236,14 @@ int spi_xfer(uint8_t dev_idx, uint8_t bitlen, const void *dout, void *din)
     }
 
   putreg16(reg_ctrl, SPI_REG(REG_CTRL));
-  _err("reg_ctrl=0x%04x ", reg_ctrl);
+  spiinfo("reg_ctrl=0x%04x ", reg_ctrl);
 
   /* wait until the transfer is complete */
 
   while (1)
     {
       reg_status = getreg16(SPI_REG(REG_STATUS));
-      _err("status=0x%04x ", reg_status);
+      spiinfo("status=0x%04x ", reg_status);
       if (din && (reg_status & SPI_STATUS_RE))
         {
           break;
@@ -262,7 +262,7 @@ int spi_xfer(uint8_t dev_idx, uint8_t bitlen, const void *dout, void *din)
     {
       tmp = getreg16(SPI_REG(REG_RX_MSB)) << 16;
       tmp |= getreg16(SPI_REG(REG_RX_LSB));
-      _err("data_in=0x%08x ", tmp);
+      spiinfo("data_in=0x%08x ", tmp);
 
       if (bitlen <= 8)
         {
@@ -278,7 +278,7 @@ int spi_xfer(uint8_t dev_idx, uint8_t bitlen, const void *dout, void *din)
         }
     }
 
-  _err("\n");
+  spiinfo("\n");
 
   return 0;
 }
diff --git a/arch/arm/src/calypso/calypso_uwire.c b/arch/arm/src/calypso/calypso_uwire.c
index 7ad9075b1e4..fe2c33b7cc1 100644
--- a/arch/arm/src/calypso/calypso_uwire.c
+++ b/arch/arm/src/calypso/calypso_uwire.c
@@ -112,7 +112,7 @@ int uwire_xfer(int cs, int bitlen, const void *dout, void *din)
 
   /* FIXME uwire_init always selects CS0 for now */
 
-  _err("uwire_xfer(dev_idx=%u, bitlen=%u\n", cs, bitlen);
+  _info("uwire_xfer(dev_idx=%u, bitlen=%u\n", cs, bitlen);
 
   /* select the chip */
 
@@ -128,7 +128,7 @@ int uwire_xfer(int cs, int bitlen, const void *dout, void *din)
 
       tmp <<= 16 - bitlen; /* align to MSB */
       putreg16(tmp, UWIRE_REG(REG_DATA));
-      _err(", data_out=0x%04hx", tmp);
+      _info(", data_out=0x%04hx", tmp);
     }
 
   tmp = (dout ? UWIRE_CSR_BITS_WR(bitlen) : 0) |
@@ -142,7 +142,7 @@ int uwire_xfer(int cs, int bitlen, const void *dout, void *din)
       _uwire_wait(UWIRE_CSR_RDRB, UWIRE_CSR_RDRB);
 
       tmp = getreg16(UWIRE_REG(REG_DATA));
-      _err(", data_in=0x%08x", tmp);
+      _info(", data_in=0x%08x", tmp);
 
       if (bitlen <= 8)
           *(uint8_t *)din = tmp & 0xff;
@@ -155,7 +155,7 @@ int uwire_xfer(int cs, int bitlen, const void *dout, void *din)
   putreg16(UWIRE_CSR_IDX(0) | 0, UWIRE_REG(REG_CSR));
   _uwire_wait(UWIRE_CSR_CSRB, 0);
 
-  _err(")\n");
+  _info(")\n");
 
   return 0;
 }
diff --git a/arch/arm/src/common/up_exit.c b/arch/arm/src/common/up_exit.c
index be084481fd9..4d16f2a8a55 100644
--- a/arch/arm/src/common/up_exit.c
+++ b/arch/arm/src/common/up_exit.c
@@ -52,6 +52,14 @@
 #include "group/group.h"
 #include "up_internal.h"
 
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#ifndef CONFIG_DEBUG_SCHED_INFO
+#  undef CONFIG_DUMP_ON_EXIT
+#endif
+
 /****************************************************************************
  * Private Functions
  ****************************************************************************/
@@ -66,7 +74,7 @@
  *
  ****************************************************************************/
 
-#if defined(CONFIG_DUMP_ON_EXIT) && defined(CONFIG_DEBUG_FEATURES)
+#ifdef CONFIG_DUMP_ON_EXIT
 static void _up_dumponexit(FAR struct tcb_s *tcb, FAR void *arg)
 {
 #if CONFIG_NFILE_DESCRIPTORS > 0
@@ -77,8 +85,8 @@ static void _up_dumponexit(FAR struct tcb_s *tcb, FAR void *arg)
   int i;
 #endif
 
-  serr("  TCB=%p name=%s pid=%d\n", tcb, tcb->argv[0], tcb->pid);
-  serr("    priority=%d state=%d\n", tcb->sched_priority, tcb->task_state);
+  sinfo("  TCB=%p name=%s pid=%d\n", tcb, tcb->argv[0], tcb->pid);
+  sinfo("    priority=%d state=%d\n", tcb->sched_priority, tcb->task_state);
 
 #if CONFIG_NFILE_DESCRIPTORS > 0
   filelist = tcb->group->tg_filelist;
@@ -87,8 +95,8 @@ static void _up_dumponexit(FAR struct tcb_s *tcb, FAR void *arg)
       struct inode *inode = filelist->fl_files[i].f_inode;
       if (inode)
         {
-          serr("      fd=%d refcount=%d\n",
-               i, inode->i_crefs);
+          sinfo("      fd=%d refcount=%d\n",
+                i, inode->i_crefssinfo);
         }
     }
 #endif
@@ -101,11 +109,11 @@ static void _up_dumponexit(FAR struct tcb_s *tcb, FAR void *arg)
       if (filep->fs_fd >= 0)
         {
 #if CONFIG_STDIO_BUFFER_SIZE > 0
-          serr("      fd=%d nbytes=%d\n",
-               filep->fs_fd,
-               filep->fs_bufpos - filep->fs_bufstart);
+          sinfo("      fd=%d nbytes=%d\n",
+                filep->fs_fd,
+                filep->fs_bufpos - filep->fs_bufstart);
 #else
-          serr("      fd=%d\n", filep->fs_fd);
+          sinfo("      fd=%d\n", filep->fs_fd);
 #endif
         }
     }
@@ -138,10 +146,10 @@ void _exit(int status)
 
   (void)up_irq_save();
 
-  sllerr("TCB=%p exiting\n", this_task());
+  sinfo("TCB=%p exiting\n", this_task());
 
-#if defined(CONFIG_DUMP_ON_EXIT) && defined(CONFIG_DEBUG_FEATURES)
-  sllerr("Other tasks:\n");
+#ifdef CONFIG_DUMP_ON_EXIT
+  sinfo("Other tasks:\n");
   sched_foreach(_up_dumponexit, NULL);
 #endif
 
diff --git a/arch/arm/src/common/up_initialize.c b/arch/arm/src/common/up_initialize.c
index 5316eacbb68..6b5117adf1b 100644
--- a/arch/arm/src/common/up_initialize.c
+++ b/arch/arm/src/common/up_initialize.c
@@ -49,7 +49,7 @@
 #include <nuttx/net/loopback.h>
 #include <nuttx/net/tun.h>
 #include <nuttx/net/telnet.h>
-#include <nuttx/syslog/ramlog.h>
+#include <nuttx/syslog/syslog.h>
 #include <nuttx/syslog/syslog_console.h>
 #include <nuttx/crypto/crypto.h>
 
@@ -77,13 +77,13 @@ static void up_calibratedelay(void)
 {
   int i;
 
-  _llerr("Beginning 100s delay\n");
+  _warn("Beginning 100s delay\n");
   for (i = 0; i < 100; i++)
     {
       up_mdelay(1000);
     }
 
-  _llerr("End 100s delay\n");
+  _warn("End 100s delay\n");
 }
 #else
 # define up_calibratedelay()
@@ -222,7 +222,7 @@ void up_initialize(void)
 
 #if defined(CONFIG_DEV_LOWCONSOLE)
   lowconsole_init();
-#elif defined(CONFIG_SYSLOG_CONSOLE)
+#elif defined(CONFIG_CONSOLE_SYSLOG)
   syslog_console_init();
 #elif defined(CONFIG_RAMLOG_CONSOLE)
   ramlog_consoleinit();
@@ -246,14 +246,12 @@ void up_initialize(void)
   up_rnginitialize();
 #endif
 
-  /* Initialize the system logging device */
+  /* Early initialization of the system logging device.  Some SYSLOG channel
+   * can be initialized early in the initialization sequence because they
+   * depend on only minimal OS initialization.
+   */
 
-#ifdef CONFIG_SYSLOG_CHAR
-  syslog_initialize();
-#endif
-#ifdef CONFIG_RAMLOG_SYSLOG
-  ramlog_sysloginit();
-#endif
+  syslog_initialize(SYSLOG_INIT_EARLY);
 
 #ifndef CONFIG_NETDEV_LATEINIT
   /* Initialize the network */
diff --git a/arch/arm/src/common/up_internal.h b/arch/arm/src/common/up_internal.h
index 8dccf8a1ef0..feec4333558 100644
--- a/arch/arm/src/common/up_internal.h
+++ b/arch/arm/src/common/up_internal.h
@@ -63,6 +63,10 @@
 #undef  CONFIG_SUPPRESS_UART_CONFIG   /* DEFINED: Do not reconfig UART */
 #undef  CONFIG_DUMP_ON_EXIT           /* DEFINED: Dump task state on exit */
 
+#ifndef CONFIG_DEBUG_SCHED_INFO
+#  undef CONFIG_DUMP_ON_EXIT          /* Needs CONFIG_DEBUG_SCHED_INFO */
+#endif
+
 /* Determine which (if any) console driver to use.  If a console is enabled
  * and no other console device is specified, then a serial console is
  * assumed.
@@ -97,13 +101,6 @@
 #  define USE_SERIALDRIVER 1
 #endif
 
-/* Determine which device to use as the system logging device */
-
-#ifndef CONFIG_SYSLOG
-#  undef CONFIG_SYSLOG_CHAR
-#  undef CONFIG_RAMLOG_SYSLOG
-#endif
-
 /* Check if an interrupt stack size is configured */
 
 #ifndef CONFIG_ARCH_INTERRUPTSTACK
diff --git a/arch/arm/src/dm320/dm320_decodeirq.c b/arch/arm/src/dm320/dm320_decodeirq.c
index 5d36a6bdc65..5d7e7095881 100644
--- a/arch/arm/src/dm320/dm320_decodeirq.c
+++ b/arch/arm/src/dm320/dm320_decodeirq.c
@@ -51,22 +51,6 @@
 
 #include "group/group.h"
 
-/********************************************************************************
- * Pre-processor Definitions
- ********************************************************************************/
-
-/********************************************************************************
- * Public Data
- ********************************************************************************/
-
-/********************************************************************************
- * Private Data
- ********************************************************************************/
-
-/********************************************************************************
- * Private Functions
- ********************************************************************************/
-
 /********************************************************************************
  * Public Functions
  ********************************************************************************/
@@ -74,8 +58,8 @@
 void up_decodeirq(uint32_t *regs)
 {
 #ifdef CONFIG_SUPPRESS_INTERRUPTS
-  lowsyslog(LOG_ERR, "Unexpected IRQ\n");
   CURRENT_REGS = regs;
+  err("ERROR: Unexpected IRQ\n");
   PANIC();
 #else
   /* Decode the interrupt.  First, fetch the interrupt id register. */
diff --git a/arch/arm/src/dm320/dm320_framebuffer.c b/arch/arm/src/dm320/dm320_framebuffer.c
index ca81e8a8486..dcedcb62e5d 100644
--- a/arch/arm/src/dm320/dm320_framebuffer.c
+++ b/arch/arm/src/dm320/dm320_framebuffer.c
@@ -928,7 +928,7 @@ static void dm320_hwinitialize(void)
   /* Set up the rectangular cursor with defaults */
 
 #ifdef CONFIG_FB_HWCURSOR
-  gerr("Initialize rectangular cursor\n");
+  lcdinfo("Initialize rectangular cursor\n");
 
   putreg16(0, DM320_OSD_CURXP);
   putreg16(0, DM320_OSD_CURYP);
@@ -1385,7 +1385,7 @@ int up_fbinitialize(int display)
   ret = dm320_allocvideomemory();
   if (ret != 0)
     {
-      gerr("Failed to allocate video buffers\n");
+      lcderr("ERROR: Failed to allocate video buffers\n");
       return ret;
     }
 
diff --git a/arch/arm/src/dm320/dm320_usbdev.c b/arch/arm/src/dm320/dm320_usbdev.c
index ad1641db1f8..df25123b09e 100644
--- a/arch/arm/src/dm320/dm320_usbdev.c
+++ b/arch/arm/src/dm320/dm320_usbdev.c
@@ -268,7 +268,7 @@ struct dm320_epinfo_s
 
 /* Register operations */
 
-#if defined(CONFIG_DM320_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES)
+#ifdef CONFIG_DM320_USBDEV_REGDEBUG
 static uint32_t dm320_getreg8(uint32_t addr);
 static uint32_t dm320_getreg16(uint32_t addr);
 static uint32_t dm320_getreg32(uint32_t addr);
@@ -422,7 +422,7 @@ static const struct dm320_epinfo_s g_epinfo[DM320_NENDPOINTS] =
  *
  ****************************************************************************/
 
-#if defined(CONFIG_DM320_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES)
+#ifdef CONFIG_DM320_USBDEV_REGDEBUG
 static uint8_t dm320_getreg8(uint32_t addr)
 {
   static uint32_t prevaddr = 0;
@@ -443,7 +443,7 @@ static uint8_t dm320_getreg8(uint32_t addr)
         {
           if (count == 4)
             {
-              _llerr("...\n");
+              uinfo("...\n");
             }
 
           return val;
@@ -460,7 +460,7 @@ static uint8_t dm320_getreg8(uint32_t addr)
         {
           /* Yes.. then show how many times the value repeated */
 
-          _llerr("[repeats %d more times]\n", count-3);
+          uinfo("[repeats %d more times]\n", count-3);
         }
 
       /* Save the new address, value, and count */
@@ -472,7 +472,7 @@ static uint8_t dm320_getreg8(uint32_t addr)
 
   /* Show the register value read */
 
-  _llerr("%08x->%02x\n", addr, val);
+  uinfo("%08x->%02x\n", addr, val);
   return val;
 }
 #endif
@@ -485,7 +485,7 @@ static uint8_t dm320_getreg8(uint32_t addr)
  *
  ****************************************************************************/
 
-#if defined(CONFIG_DM320_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES)
+#ifdef CONFIG_DM320_USBDEV_REGDEBUG
 static uint32_t dm320_getreg16(uint32_t addr)
 {
   static uint32_t prevaddr = 0;
@@ -506,7 +506,7 @@ static uint32_t dm320_getreg16(uint32_t addr)
         {
           if (count == 4)
             {
-              _llerr("...\n");
+              uinfo("...\n");
             }
 
           return val;
@@ -523,7 +523,7 @@ static uint32_t dm320_getreg16(uint32_t addr)
         {
           /* Yes.. then show how many times the value repeated */
 
-          _llerr("[repeats %d more times]\n", count-3);
+          uinfo("[repeats %d more times]\n", count-3);
         }
 
       /* Save the new address, value, and count */
@@ -535,7 +535,7 @@ static uint32_t dm320_getreg16(uint32_t addr)
 
   /* Show the register value read */
 
-  _llerr("%08x->%04x\n", addr, val);
+  uinfo("%08x->%04x\n", addr, val);
   return val;
 }
 #endif
@@ -548,7 +548,7 @@ static uint32_t dm320_getreg16(uint32_t addr)
  *
  ****************************************************************************/
 
-#if defined(CONFIG_DM320_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES)
+#ifdef CONFIG_DM320_USBDEV_REGDEBUG
 static uint32_t dm320_getreg32(uint32_t addr)
 {
   static uint32_t prevaddr = 0;
@@ -569,7 +569,7 @@ static uint32_t dm320_getreg32(uint32_t addr)
         {
           if (count == 4)
             {
-              _llerr("...\n");
+              uinfo("...\n");
             }
 
           return val;
@@ -586,7 +586,7 @@ static uint32_t dm320_getreg32(uint32_t addr)
         {
           /* Yes.. then show how many times the value repeated */
 
-          _llerr("[repeats %d more times]\n", count-3);
+          uinfo("[repeats %d more times]\n", count-3);
         }
 
       /* Save the new address, value, and count */
@@ -598,7 +598,7 @@ static uint32_t dm320_getreg32(uint32_t addr)
 
   /* Show the register value read */
 
-  _llerr("%08x->%08x\n", addr, val);
+  uinfo("%08x->%08x\n", addr, val);
   return val;
 }
 #endif
@@ -611,12 +611,12 @@ static uint32_t dm320_getreg32(uint32_t addr)
  *
  ****************************************************************************/
 
-#if defined(CONFIG_DM320_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES)
+#ifdef CONFIG_DM320_USBDEV_REGDEBUG
 static void dm320_putreg8(uint8_t val, uint32_t addr)
 {
   /* Show the register value being written */
 
-  _llerr("%08x<-%02x\n", addr, val);
+  uinfo("%08x<-%02x\n", addr, val);
 
   /* Write the value */
 
@@ -632,12 +632,12 @@ static void dm320_putreg8(uint8_t val, uint32_t addr)
  *
  ****************************************************************************/
 
-#if defined(CONFIG_DM320_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES)
+#ifdef CONFIG_DM320_USBDEV_REGDEBUG
 static void dm320_putreg16(uint16_t val, uint32_t addr)
 {
   /* Show the register value being written */
 
-  _llerr("%08x<-%04x\n", addr, val);
+  uinfo("%08x<-%04x\n", addr, val);
 
   /* Write the value */
 
@@ -653,12 +653,12 @@ static void dm320_putreg16(uint16_t val, uint32_t addr)
  *
  ****************************************************************************/
 
-#if defined(CONFIG_DM320_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES)
+#ifdef CONFIG_DM320_USBDEV_REGDEBUG
 static void dm320_putreg32(uint32_t val, uint32_t addr)
 {
   /* Show the register value being written */
 
-  _llerr("%08x<-%08x\n", addr, val);
+  uinfo("%08x<-%08x\n", addr, val);
 
   /* Write the value */
 
@@ -1216,8 +1216,8 @@ static inline void dm320_ep0setup(struct dm320_usbdev_s *priv)
   value = GETUINT16(ctrl.value);
   len   = GETUINT16(ctrl.len);
 
-  ullinfo("type=%02x req=%02x value=%04x index=%04x len=%04x\n",
-          ctrl.type, ctrl.req, value, index, len);
+  uinfo("type=%02x req=%02x value=%04x index=%04x len=%04x\n",
+        ctrl.type, ctrl.req, value, index, len);
 
   /* Dispatch any non-standard requests */
 
@@ -1618,7 +1618,7 @@ static int dm320_ctlrinterrupt(int irq, FAR void *context)
               }
             else
               {
-                ullinfo("Pending data on OUT endpoint\n");
+                uinfo("Pending data on OUT endpoint\n");
                 priv->rxpending = 1;
               }
           }
@@ -2415,9 +2415,9 @@ void up_usbinitialize(void)
   memset(priv, 0, sizeof(struct dm320_usbdev_s));
   priv->usbdev.ops = &g_devops;
 
-#ifdef CONFIG_DEBUG_USB
+#ifdef CONFIG_DEBUG_USB_INFO
   chiprev = dm320_getreg16(DM320_BUSC_REVR);
-  ullerr("DM320 revision : %d.%d\n", chiprev >> 4, chiprev & 0x0f);
+  uinfo("DM320 revision : %d.%d\n", chiprev >> 4, chiprev & 0x0f);
 #endif
 
   /* Enable USB clock & GIO clock  */
diff --git a/arch/arm/src/efm32/efm32_adc.c b/arch/arm/src/efm32/efm32_adc.c
index bc652fc59e9..c9e339e6ea2 100644
--- a/arch/arm/src/efm32/efm32_adc.c
+++ b/arch/arm/src/efm32/efm32_adc.c
@@ -1191,7 +1191,7 @@ static int adc_interrupt(FAR struct adc_dev_s *dev)
   adcsr = adc_getreg(priv, EFM32_ADC_SR_OFFSET);
   if ((adcsr & ADC_SR_AWD) != 0)
     {
-      allerr("WARNING: Analog Watchdog, Value converted out of range!\n");
+      awarn("WARNING: Analog Watchdog, Value converted out of range!\n");
     }
 
   /* EOC: End of conversion */
@@ -1298,7 +1298,7 @@ struct adc_dev_s *efm32_adcinitialize(int intf, const uint8_t *chanlist, int nch
   else
 #endif
     {
-      aerr("No ADC interface defined\n");
+      aerr("ERROR: No ADC interface defined\n");
       return NULL;
     }
 
diff --git a/arch/arm/src/efm32/efm32_clockconfig.c b/arch/arm/src/efm32/efm32_clockconfig.c
index d5974078118..5ecdf03c12f 100644
--- a/arch/arm/src/efm32/efm32_clockconfig.c
+++ b/arch/arm/src/efm32/efm32_clockconfig.c
@@ -884,7 +884,7 @@ static inline void efm32_gpioclock(void)
  *
  ****************************************************************************/
 
-#if defined(CONFIG_SYSLOG) || defined(CONFIG_ARMV7M_ITMSYSLOG)
+#ifdef CONFIG_ARMV7M_ITMSYSLOG
 static inline void efm32_itm_syslog(void)
 {
   int regval;
diff --git a/arch/arm/src/efm32/efm32_config.h b/arch/arm/src/efm32/efm32_config.h
index b60c3a60e4d..f0bf6335d96 100644
--- a/arch/arm/src/efm32/efm32_config.h
+++ b/arch/arm/src/efm32/efm32_config.h
@@ -127,7 +127,7 @@
 #undef HAVE_UART_CONSOLE
 #undef HAVE_LEUART_CONSOLE
 
-#if defined(CONFIG_SYSLOG_CONSOLE)
+#if defined(CONFIG_CONSOLE_SYSLOG)
 #  undef CONFIG_USART1_SERIAL_CONSOLE
 #  undef CONFIG_USART2_SERIAL_CONSOLE
 #  undef CONFIG_UART0_SERIAL_CONSOLE
diff --git a/arch/arm/src/efm32/efm32_dma.c b/arch/arm/src/efm32/efm32_dma.c
index de260de00d2..4bf901500b6 100644
--- a/arch/arm/src/efm32/efm32_dma.c
+++ b/arch/arm/src/efm32/efm32_dma.c
@@ -270,7 +270,7 @@ void weak_function up_dmainitialize(void)
   uint32_t regval;
   int i;
 
-  dmallinfo("Initialize XDMAC0\n");
+  dmainfo("Initialize XDMAC0\n");
 
   /* Initialize the channel list  */
 
@@ -745,7 +745,7 @@ void efm32_dmastop(DMA_HANDLE handle)
  *
  ****************************************************************************/
 
-#ifdef CONFIG_DEBUG_DMA
+#ifdef CONFIG_DEBUG_DMA_INFO
 void efm32_dmasample(DMA_HANDLE handle, struct efm32_dmaregs_s *regs)
 {
   struct dma_channel_s *dmach = (struct dma_channel_s *)handle;
@@ -798,35 +798,35 @@ void efm32_dmasample(DMA_HANDLE handle, struct efm32_dmaregs_s *regs)
  *
  ****************************************************************************/
 
-#ifdef CONFIG_DEBUG_DMA
+#ifdef CONFIG_DEBUG_DMA_INFO
 void efm32_dmadump(DMA_HANDLE handle, const struct efm32_dmaregs_s *regs,
                    const char *msg)
 {
   struct dma_channel_s *dmach = (struct dma_channel_s *)handle;
 
-  dmaerr("%s\n", msg);
-  dmaerr("  DMA Registers:\n");
-  dmaerr("        STATUS: %08x\n", regs->status);
-  dmaerr("      CTRLBASE: %08x\n", regs->ctrlbase);
-  dmaerr("   ALTCTRLBASE: %08x\n", regs->altctrlbase);
-  dmaerr("  CHWAITSTATUS: %08x\n", regs->chwaitstatus);
-  dmaerr("   CHUSEBURSTS: %08x\n", regs->chusebursts);
-  dmaerr("    CHREQMASKS: %08x\n", regs->chreqmasks);
-  dmaerr("         CHENS: %08x\n", regs->chens);
-  dmaerr("        CHALTS: %08x\n", regs->chalts);
-  dmaerr("        CHPRIS: %08x\n", regs->chpris);
-  dmaerr("        ERRORC: %08x\n", regs->errorc);
-  dmaerr("   CHREQSTATUS: %08x\n", regs->chreqstatus);
-  dmaerr("  CHSREQSTATUS: %08x\n", regs->chsreqstatus);
-  dmaerr("           IEN: %08x\n", regs->ien);
+  dmainfo("%s\n", msg);
+  dmainfo("  DMA Registers:\n");
+  dmainfo("        STATUS: %08x\n", regs->status);
+  dmainfo("      CTRLBASE: %08x\n", regs->ctrlbase);
+  dmainfo("   ALTCTRLBASE: %08x\n", regs->altctrlbase);
+  dmainfo("  CHWAITSTATUS: %08x\n", regs->chwaitstatus);
+  dmainfo("   CHUSEBURSTS: %08x\n", regs->chusebursts);
+  dmainfo("    CHREQMASKS: %08x\n", regs->chreqmasks);
+  dmainfo("         CHENS: %08x\n", regs->chens);
+  dmainfo("        CHALTS: %08x\n", regs->chalts);
+  dmainfo("        CHPRIS: %08x\n", regs->chpris);
+  dmainfo("        ERRORC: %08x\n", regs->errorc);
+  dmainfo("   CHREQSTATUS: %08x\n", regs->chreqstatus);
+  dmainfo("  CHSREQSTATUS: %08x\n", regs->chsreqstatus);
+  dmainfo("           IEN: %08x\n", regs->ien);
 #if defined(CONFIG_EFM32_EFM32GG)
-  dmaerr("          CTRL: %08x\n", regs->ctrl);
-  dmaerr("           RDS: %08x\n", regs->rds);
-  dmaerr("         LOOP0: %08x\n", regs->loop0);
-  dmaerr("         LOOP1: %08x\n", regs->loop1);
-  dmaerr("         RECT0: %08x\n", regs->rect0);
+  dmainfo("          CTRL: %08x\n", regs->ctrl);
+  dmainfo("           RDS: %08x\n", regs->rds);
+  dmainfo("         LOOP0: %08x\n", regs->loop0);
+  dmainfo("         LOOP1: %08x\n", regs->loop1);
+  dmainfo("         RECT0: %08x\n", regs->rect0);
 #endif
-  dmaerr("  DMA Channel %d Registers:\n", dmach->chan);
-  dmaerr("        CHCTRL: %08x\n", regs->chnctrl);
+  dmainfo("  DMA Channel %d Registers:\n", dmach->chan);
+  dmainfo("        CHCTRL: %08x\n", regs->chnctrl);
 }
 #endif
diff --git a/arch/arm/src/efm32/efm32_dma.h b/arch/arm/src/efm32/efm32_dma.h
index 2cedb881f38..011a7d98742 100644
--- a/arch/arm/src/efm32/efm32_dma.h
+++ b/arch/arm/src/efm32/efm32_dma.h
@@ -109,7 +109,7 @@ typedef FAR void *DMA_HANDLE;
 
 typedef void (*dma_callback_t)(DMA_HANDLE handle, uint8_t status, void *arg);
 
-#ifdef CONFIG_DEBUG_DMA
+#ifdef CONFIG_DEBUG_DMA_INFO
 struct efm32_dmaregs_s
 {
   uint32_t status;            /* DMA Status Register */
@@ -282,7 +282,7 @@ void efm32_dmastop(DMA_HANDLE handle);
  *
  ************************************************************************************/
 
-#ifdef CONFIG_DEBUG_DMA
+#ifdef CONFIG_DEBUG_DMA_INFO
 void efm32_dmasample(DMA_HANDLE handle, struct efm32_dmaregs_s *regs);
 #else
 #  define efm32_dmasample(handle,regs)
@@ -299,7 +299,7 @@ void efm32_dmasample(DMA_HANDLE handle, struct efm32_dmaregs_s *regs);
  *
  ************************************************************************************/
 
-#ifdef CONFIG_DEBUG_DMA
+#ifdef CONFIG_DEBUG_DMA_INFO
 void efm32_dmadump(DMA_HANDLE handle, const struct efm32_dmaregs_s *regs,
                    const char *msg);
 #else
diff --git a/arch/arm/src/efm32/efm32_i2c.c b/arch/arm/src/efm32/efm32_i2c.c
index c139ea012a0..d05f9ae22a6 100644
--- a/arch/arm/src/efm32/efm32_i2c.c
+++ b/arch/arm/src/efm32/efm32_i2c.c
@@ -751,7 +751,7 @@ static void efm32_i2c_tracenew(FAR struct efm32_i2c_priv_s *priv)
 
           if (priv->tndx >= (CONFIG_I2C_NTRACE - 1))
             {
-              i2cerr("Trace table overflow\n");
+              i2cerr("ERROR: Trace table overflow\n");
               return;
             }
 
@@ -1526,9 +1526,9 @@ static int efm32_i2c_transfer(FAR struct i2c_master_s *dev,
     {
       ret = -ETIMEDOUT;
 
-      i2cerr("Timed out: I2Cx_STATE: 0x%04x I2Cx_STATUS: 0x%08x\n",
-             efm32_i2c_getreg(priv, EFM32_I2C_STATE_OFFSET),
-             efm32_i2c_getreg(priv, EFM32_I2C_STATUS_OFFSET));
+      i2cerr("ERROR: Timed out: I2Cx_STATE: 0x%04x I2Cx_STATUS: 0x%08x\n",
+              efm32_i2c_getreg(priv, EFM32_I2C_STATE_OFFSET),
+              efm32_i2c_getreg(priv, EFM32_I2C_STATUS_OFFSET));
 
       /* Abort */
 
diff --git a/arch/arm/src/efm32/efm32_idle.c b/arch/arm/src/efm32/efm32_idle.c
index b5a2278a1a2..9a6d9f7e155 100644
--- a/arch/arm/src/efm32/efm32_idle.c
+++ b/arch/arm/src/efm32/efm32_idle.c
@@ -110,7 +110,7 @@ static void up_idlepm(void)
 
       /* Perform board-specific, state-dependent logic here */
 
-      _llinfo("newstate= %d oldstate=%d\n", newstate, oldstate);
+      _info("newstate= %d oldstate=%d\n", newstate, oldstate);
 
       /* Then force the global state change */
 
diff --git a/arch/arm/src/efm32/efm32_irq.c b/arch/arm/src/efm32/efm32_irq.c
index 05d28c74a4c..63fa4b18ec7 100644
--- a/arch/arm/src/efm32/efm32_irq.c
+++ b/arch/arm/src/efm32/efm32_irq.c
@@ -157,7 +157,7 @@ static void efm32_dumpnvic(const char *msg, int irq)
 
 /****************************************************************************
  * Name: efm32_nmi, efm32_busfault, efm32_usagefault, efm32_pendsv,
- *       efm32_errmonitor, efm32_pendsv, efm32_reserved
+ *       efm32_dbgmonitor, efm32_pendsv, efm32_reserved
  *
  * Description:
  *   Handlers for various exceptions.  None are handled and all are fatal
@@ -199,7 +199,7 @@ static int efm32_pendsv(int irq, FAR void *context)
   return 0;
 }
 
-static int efm32_errmonitor(int irq, FAR void *context)
+static int efm32_dbgmonitor(int irq, FAR void *context)
 {
   (void)up_irq_save();
   _err("PANIC!!! Debug Monitor received\n");
@@ -458,7 +458,7 @@ void up_irqinitialize(void)
   irq_attach(EFM32_IRQ_BUSFAULT, efm32_busfault);
   irq_attach(EFM32_IRQ_USAGEFAULT, efm32_usagefault);
   irq_attach(EFM32_IRQ_PENDSV, efm32_pendsv);
-  irq_attach(EFM32_IRQ_DBGMONITOR, efm32_errmonitor);
+  irq_attach(EFM32_IRQ_DBGMONITOR, efm32_dbgmonitor);
   irq_attach(EFM32_IRQ_RESERVED, efm32_reserved);
 #endif
 
diff --git a/arch/arm/src/efm32/efm32_leserial.c b/arch/arm/src/efm32/efm32_leserial.c
index 02126a92f3d..8a5de937888 100644
--- a/arch/arm/src/efm32/efm32_leserial.c
+++ b/arch/arm/src/efm32/efm32_leserial.c
@@ -518,7 +518,7 @@ static int  efm32_interrupt(struct uart_dev_s *dev)
        * FERR - Framing Error Interrupt Enable
        */
 
-      _llerr("RX ERROR: %08x\n", intflags);
+      _err("RX ERROR: %08x\n", intflags);
     }
 
   /* Check for transmit errors */
@@ -527,7 +527,7 @@ static int  efm32_interrupt(struct uart_dev_s *dev)
     {
       /* TXOF - TX Overflow Interrupt Enable */
 
-      _llerr("RX ERROR: %08x\n", intflags);
+      _err("RX ERROR: %08x\n", intflags);
     }
 #endif
 
diff --git a/arch/arm/src/efm32/efm32_pwm.c b/arch/arm/src/efm32/efm32_pwm.c
index 0f149f8dc4f..b34d8aeb2ff 100644
--- a/arch/arm/src/efm32/efm32_pwm.c
+++ b/arch/arm/src/efm32/efm32_pwm.c
@@ -395,7 +395,7 @@ static int pwm_timer(FAR struct efm32_pwmtimer_s *priv,
 
   if (efm32_timer_set_freq(priv->base, priv->pclk, info->frequency) < 0)
     {
-      pwmerr("Cannot set TIMER frequency %dHz from clock %dHz\n",
+      pwmerr("ERROR: Cannot set TIMER frequency %dHz from clock %dHz\n",
              info->frequency, priv->pclk);
       return -EINVAL;
     }
@@ -522,8 +522,8 @@ static int pwm_interrupt(struct efm32_pwmtimer_s *priv)
 
   /* Now all of the time critical stuff is done so we can do some debug output */
 
-  pwmllinfo("Update interrupt SR: %04x prev: %d curr: %d count: %d\n",
-            regval, priv->prev, priv->curr, priv->count);
+  pwminfo("Update interrupt SR: %04x prev: %d curr: %d count: %d\n",
+          regval, priv->prev, priv->curr, priv->count);
 
   return OK;
 #else
@@ -914,7 +914,7 @@ FAR struct pwm_lowerhalf_s *efm32_pwminitialize(int timer)
 #endif
 
       default:
-        pwmerr("No such timer configured\n");
+        pwmerr("ERROR: No such timer configured\n");
         return NULL;
     }
 
diff --git a/arch/arm/src/efm32/efm32_rmu.c b/arch/arm/src/efm32/efm32_rmu.c
index 1d30cb2b409..57d7b0e02b7 100644
--- a/arch/arm/src/efm32/efm32_rmu.c
+++ b/arch/arm/src/efm32/efm32_rmu.c
@@ -63,7 +63,7 @@
  * Private Types
  ************************************************************************************/
 
-#ifdef CONFIG_EFM32_RMU_DEBUG
+#if defined(CONFIG_EFM32_RMU_DEBUG) && defined(CONFIG_DEBUG_WARN)
 typedef struct
 {
   const uint32_t val;
@@ -76,7 +76,7 @@ typedef struct
  * Private Data
  ************************************************************************************/
 
-#ifdef CONFIG_EFM32_RMU_DEBUG
+#if defined(CONFIG_EFM32_RMU_DEBUG) && defined(CONFIG_DEBUG_WARN)
 static efm32_reset_cause_list_t efm32_reset_cause_list[] =
 {
   {
@@ -191,7 +191,7 @@ uint32_t g_efm32_rstcause;
  *
  ************************************************************************************/
 
-#ifdef CONFIG_EFM32_RMU_DEBUG
+#if defined(CONFIG_EFM32_RMU_DEBUG) && defined(CONFIG_DEBUG_WARN)
 const char *efm32_reset_cause_list_str(uint32_t reg, unsigned int *idx)
 {
   int len = sizeof(efm32_reset_cause_list)/sizeof(efm32_reset_cause_list[0]);
@@ -261,8 +261,8 @@ void efm32_rmu_initialize(void)
       putreg32(EMU_LOCK_LOCKKEY_LOCK, EMU_LOCK_LOCKKEY_LOCK);
     }
 
-#ifdef CONFIG_EFM32_RMU_DEBUG
-  rmuerr("RMU => reg = 0x%08X\n", g_efm32_rstcause);
+#if defined(CONFIG_EFM32_RMU_DEBUG) && defined(CONFIG_DEBUG_WARN)
+  rmuwarn("RMU => reg = 0x%08X\n", g_efm32_rstcause);
   for (; ; )
     {
       const char *str;
@@ -273,7 +273,7 @@ void efm32_rmu_initialize(void)
           break;
         }
 
-      rmuerr("RMU => %s\n", str);
+      rmuwarn("RMU => %s\n", str);
     }
 #endif
 }
diff --git a/arch/arm/src/efm32/efm32_rmu.h b/arch/arm/src/efm32/efm32_rmu.h
index 215f0c85e85..1bcfec2d33f 100644
--- a/arch/arm/src/efm32/efm32_rmu.h
+++ b/arch/arm/src/efm32/efm32_rmu.h
@@ -50,20 +50,17 @@
  ****************************************************************************/
 /* Configuration ************************************************************/
 
-#ifndef CONFIG_DEBUG_FEATURES
-#  undef CONFIG_DEBUG_INFO
+#ifndef CONFIG_DEBUG_ERROR
 #  undef CONFIG_EFM32_RMU_DEBUG
 #endif
 
 #ifdef CONFIG_EFM32_RMU_DEBUG
-#  define rmuerr  _llerr
-#  ifdef CONFIG_DEBUG_INFO
-#    define rmuinfo  _llerr
-#  else
-#    define rmuinfo(x...)
-#  endif
+#  define rmuerr   _err
+#  define rmuwarn  _warn
+#  define rmuinfo  _info
 #else
 #  define rmuerr(x...)
+#  define rmuwarn(x...)
 #  define rmuinfo(x...)
 #endif
 
diff --git a/arch/arm/src/efm32/efm32_serial.c b/arch/arm/src/efm32/efm32_serial.c
index ff8c0f7dac6..52848fcd03d 100644
--- a/arch/arm/src/efm32/efm32_serial.c
+++ b/arch/arm/src/efm32/efm32_serial.c
@@ -780,7 +780,7 @@ static int  efm32_rxinterrupt(struct uart_dev_s *dev)
        * FERR - Framing Error Interrupt Enable
        */
 
-      _llerr("RX ERROR: %08x\n", intflags);
+      _err("RX ERROR: %08x\n", intflags);
     }
 #endif
 
@@ -863,7 +863,7 @@ static int  efm32_txinterrupt(struct uart_dev_s *dev)
     {
       /* TXOF - TX Overflow Interrupt Enable */
 
-      _llerr("RX ERROR: %08x\n", intflags);
+      _err("RX ERROR: %08x\n", intflags);
     }
 #endif
 
diff --git a/arch/arm/src/efm32/efm32_usbdev.c b/arch/arm/src/efm32/efm32_usbdev.c
index 207cce2e94f..26753dd3ff4 100644
--- a/arch/arm/src/efm32/efm32_usbdev.c
+++ b/arch/arm/src/efm32/efm32_usbdev.c
@@ -114,6 +114,10 @@
 #  error "FIFO allocations exceed FIFO memory size"
 #endif
 
+#ifndef CONFIG_DEBUG_USB_INFO
+#  undef CONFIG_EFM32_USBDEV_REGDEBUG
+#endif
+
 /* The actual FIFO addresses that we use must be aligned to 4-byte boundaries;
  * FIFO sizes must be provided in units of 32-bit words.
  */
@@ -474,7 +478,7 @@ struct efm32_usbdev_s
 
 /* Register operations ********************************************************/
 
-#if defined(CONFIG_EFM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES)
+#ifdef CONFIG_EFM32_USBDEV_REGDEBUG
 static uint32_t    efm32_getreg(uint32_t addr);
 static void        efm32_putreg(uint32_t val, uint32_t addr);
 #else
@@ -794,7 +798,7 @@ const struct trace_msg_t g_usb_trace_strings_intdecode[] =
  *
  ****************************************************************************/
 
-#if defined(CONFIG_EFM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES)
+#ifdef CONFIG_EFM32_USBDEV_REGDEBUG
 static uint32_t efm32_getreg(uint32_t addr)
 {
   static uint32_t prevaddr = 0;
@@ -815,7 +819,7 @@ static uint32_t efm32_getreg(uint32_t addr)
         {
           if (count == 4)
             {
-              _llerr("...\n");
+              uinfo("...\n");
             }
 
           return val;
@@ -832,7 +836,7 @@ static uint32_t efm32_getreg(uint32_t addr)
         {
           /* Yes.. then show how many times the value repeated */
 
-          _llerr("[repeats %d more times]\n", count-3);
+          uinfo("[repeats %d more times]\n", count-3);
         }
 
       /* Save the new address, value, and count */
@@ -844,7 +848,7 @@ static uint32_t efm32_getreg(uint32_t addr)
 
   /* Show the register value read */
 
-  _llerr("%08x->%08x\n", addr, val);
+  uinfo("%08x->%08x\n", addr, val);
   return val;
 }
 #endif
@@ -857,12 +861,12 @@ static uint32_t efm32_getreg(uint32_t addr)
  *
  ****************************************************************************/
 
-#if defined(CONFIG_EFM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES)
+#ifdef CONFIG_EFM32_USBDEV_REGDEBUG
 static void efm32_putreg(uint32_t val, uint32_t addr)
 {
   /* Show the register value being written */
 
-  _llerr("%08x<-%08x\n", addr, val);
+  uinfo("%08x<-%08x\n", addr, val);
 
   /* Write the value */
 
@@ -1220,9 +1224,9 @@ static void efm32_epin_request(FAR struct efm32_usbdev_s *priv,
       return;
     }
 
-  ullinfo("EP%d req=%p: len=%d xfrd=%d zlp=%d\n",
-          privep->epphy, privreq, privreq->req.len,
-          privreq->req.xfrd, privep->zlp);
+  uinfo("EP%d req=%p: len=%d xfrd=%d zlp=%d\n",
+        privep->epphy, privreq, privreq->req.len,
+        privreq->req.xfrd, privep->zlp);
 
   /* Check for a special case:  If we are just starting a request (xfrd==0) and
    * the class driver is trying to send a zero-length packet (len==0).  Then set
@@ -1486,8 +1490,8 @@ static void efm32_epout_complete(FAR struct efm32_usbdev_s *priv,
       return;
     }
 
-  ullinfo("EP%d: len=%d xfrd=%d\n",
-          privep->epphy, privreq->req.len, privreq->req.xfrd);
+  uinfo("EP%d: len=%d xfrd=%d\n",
+        privep->epphy, privreq->req.len, privreq->req.xfrd);
 
   /* Return the completed read request to the class driver and mark the state
    * IDLE.
@@ -1521,7 +1525,7 @@ static inline void efm32_ep0out_receive(FAR struct efm32_ep_s *privep, int bcnt)
   DEBUGASSERT(privep && privep->ep.priv);
   priv = (FAR struct efm32_usbdev_s *)privep->ep.priv;
 
-  ullinfo("EP0: bcnt=%d\n", bcnt);
+  uinfo("EP0: bcnt=%d\n", bcnt);
   usbtrace(TRACE_READ(EP0), bcnt);
 
   /* Verify that an OUT SETUP request as received before this data was
@@ -1614,7 +1618,8 @@ static inline void efm32_epout_receive(FAR struct efm32_ep_s *privep, int bcnt)
       return;
     }
 
-  ullinfo("EP%d: len=%d xfrd=%d\n", privep->epphy, privreq->req.len, privreq->req.xfrd);
+  uinfo("EP%d: len=%d xfrd=%d\n",
+        privep->epphy, privreq->req.len, privreq->req.xfrd);
   usbtrace(TRACE_READ(privep->epphy), bcnt);
 
   /* Get the number of bytes to transfer from the RxFIFO */
@@ -1698,7 +1703,7 @@ static void efm32_epout_request(FAR struct efm32_usbdev_s *priv,
               return;
             }
 
-          ullinfo("EP%d: len=%d\n", privep->epphy, privreq->req.len);
+          uinfo("EP%d: len=%d\n", privep->epphy, privreq->req.len);
 
           /* Ignore any attempt to receive a zero length packet (this really
            * should not happen.
@@ -2494,8 +2499,8 @@ static inline void efm32_ep0out_setup(struct efm32_usbdev_s *priv)
   ctrlreq.index = GETUINT16(priv->ctrlreq.index);
   ctrlreq.len   = GETUINT16(priv->ctrlreq.len);
 
-  ullinfo("type=%02x req=%02x value=%04x index=%04x len=%04x\n",
-          ctrlreq.type, ctrlreq.req, ctrlreq.value, ctrlreq.index, ctrlreq.len);
+  uinfo("type=%02x req=%02x value=%04x index=%04x len=%04x\n",
+        ctrlreq.type, ctrlreq.req, ctrlreq.value, ctrlreq.index, ctrlreq.len);
 
   /* Check for a standard request */
 
@@ -2629,7 +2634,7 @@ static inline void efm32_epout_interrupt(FAR struct efm32_usbdev_s *priv)
           if ((daint & 1) != 0)
             {
               regval = efm32_getreg(EFM32_USB_DOEPINT(epno));
-              ullerr("DOEPINT(%d) = %08x\n", epno, regval);
+              uinfo("DOEPINT(%d) = %08x\n", epno, regval);
               efm32_putreg(0xFF, EFM32_USB_DOEPINT(epno));
             }
 
@@ -2859,8 +2864,8 @@ static inline void efm32_epin_interrupt(FAR struct efm32_usbdev_s *priv)
         {
           if ((daint & 1) != 0)
             {
-              ullerr("DIEPINT(%d) = %08x\n",
-                     epno, efm32_getreg(EFM32_USB_DIEPINT(epno)));
+              uinfo("DIEPINT(%d) = %08x\n",
+                    epno, efm32_getreg(EFM32_USB_DIEPINT(epno)));
               efm32_putreg(0xFF, EFM32_USB_DIEPINT(epno));
             }
 
@@ -3799,7 +3804,7 @@ static int efm32_epout_configure(FAR struct efm32_ep_s *privep, uint8_t eptype,
             break;
 
           default:
-            uerr("Unsupported maxpacket: %d\n", maxpacket);
+            uerr("ERROR: Unsupported maxpacket: %d\n", maxpacket);
             return -EINVAL;
         }
     }
@@ -3894,7 +3899,7 @@ static int efm32_epin_configure(FAR struct efm32_ep_s *privep, uint8_t eptype,
             break;
 
           default:
-            uerr("Unsupported maxpacket: %d\n", maxpacket);
+            uerr("ERROR: Unsupported maxpacket: %d\n", maxpacket);
             return -EINVAL;
         }
     }
@@ -4333,7 +4338,8 @@ static int efm32_ep_submit(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s *
   if (!req || !req->callback || !req->buf || !ep)
     {
       usbtrace(TRACE_DEVERROR(EFM32_TRACEERR_INVALIDPARMS), 0);
-      ullinfo("req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, ep);
+      uinfo("req=%p callback=%p buf=%p ep=%p\n",
+            req, req->callback, req->buf, ep);
       return -EINVAL;
     }
 #endif
@@ -5482,7 +5488,7 @@ void up_usbinitialize(void)
   ret = irq_attach(EFM32_IRQ_USB, efm32_usbinterrupt);
   if (ret < 0)
     {
-      uerr("irq_attach failed\n", ret);
+      uerr("ERROR: irq_attach failed\n", ret);
       goto errout;
     }
 
diff --git a/arch/arm/src/efm32/efm32_usbhost.c b/arch/arm/src/efm32/efm32_usbhost.c
index ccfd96e34b7..19f80bc43d4 100644
--- a/arch/arm/src/efm32/efm32_usbhost.c
+++ b/arch/arm/src/efm32/efm32_usbhost.c
@@ -123,7 +123,7 @@
 
 /* Register/packet debug depends on CONFIG_DEBUG_FEATURES */
 
-#ifndef CONFIG_DEBUG_FEATURES
+#ifndef CONFIG_DEBUG_USB_INFO
 #  undef CONFIG_EFM32_USBHOST_REGDEBUG
 #  undef CONFIG_EFM32_USBHOST_PKTDUMP
 #endif
@@ -582,7 +582,7 @@ static const struct efm32_usbhost_trace_s g_trace2[TRACE2_NSTRINGS] =
 #ifdef CONFIG_EFM32_USBHOST_REGDEBUG
 static void efm32_printreg(uint32_t addr, uint32_t val, bool iswrite)
 {
-  _llerr("%08x%s%08x\n", addr, iswrite ? "<-" : "->", val);
+  uinfo("%08x%s%08x\n", addr, iswrite ? "<-" : "->", val);
 }
 #endif
 
@@ -632,7 +632,7 @@ static void efm32_checkreg(uint32_t addr, uint32_t val, bool iswrite)
             {
               /* No.. More than one. */
 
-              _llerr("[repeats %d more times]\n", count);
+              uinfo("[repeats %d more times]\n", count);
             }
         }
 
@@ -2448,7 +2448,7 @@ static inline void efm32_gint_hcinisr(FAR struct efm32_usbhost_s *priv,
   /* AND the two to get the set of enabled, pending HC interrupts */
 
   pending &= regval;
-  ullinfo("HCINTMSK%d: %08x pending: %08x\n", chidx, regval, pending);
+  uinfo("HCINTMSK%d: %08x pending: %08x\n", chidx, regval, pending);
 
   /* Check for a pending ACK response received/transmitted (ACK) interrupt */
 
@@ -2709,7 +2709,7 @@ static inline void efm32_gint_hcoutisr(FAR struct efm32_usbhost_s *priv,
   /* AND the two to get the set of enabled, pending HC interrupts */
 
   pending &= regval;
-  ullinfo("HCINTMSK%d: %08x pending: %08x\n", chidx, regval, pending);
+  uinfo("HCINTMSK%d: %08x pending: %08x\n", chidx, regval, pending);
 
   /* Check for a pending ACK response received/transmitted (ACK) interrupt */
 
@@ -3012,7 +3012,7 @@ static inline void efm32_gint_rxflvlisr(FAR struct efm32_usbhost_s *priv)
   /* Read and pop the next status from the Rx FIFO */
 
   grxsts = efm32_getreg(EFM32_USB_GRXSTSP);
-  ullinfo("GRXSTS: %08x\n", grxsts);
+  uinfo("GRXSTS: %08x\n", grxsts);
 
   /* Isolate the channel number/index in the status word */
 
@@ -3166,8 +3166,8 @@ static inline void efm32_gint_nptxfeisr(FAR struct efm32_usbhost_s *priv)
 
   /* Write the next group of packets into the Tx FIFO */
 
-  ullinfo("HNPTXSTS: %08x chidx: %d avail: %d buflen: %d xfrd: %d wrsize: %d\n",
-           regval, chidx, avail, chan->buflen, chan->xfrd, wrsize);
+  uinfo("HNPTXSTS: %08x chidx: %d avail: %d buflen: %d xfrd: %d wrsize: %d\n",
+         regval, chidx, avail, chan->buflen, chan->xfrd, wrsize);
 
   efm32_gint_wrpacket(priv, chan->buffer, chidx, wrsize);
 }
@@ -3254,8 +3254,8 @@ static inline void efm32_gint_ptxfeisr(FAR struct efm32_usbhost_s *priv)
 
   /* Write the next group of packets into the Tx FIFO */
 
-  ullinfo("HPTXSTS: %08x chidx: %d avail: %d buflen: %d xfrd: %d wrsize: %d\n",
-           regval, chidx, avail, chan->buflen, chan->xfrd, wrsize);
+  uinfo("HPTXSTS: %08x chidx: %d avail: %d buflen: %d xfrd: %d wrsize: %d\n",
+        regval, chidx, avail, chan->buflen, chan->xfrd, wrsize);
 
   efm32_gint_wrpacket(priv, chan->buffer, chidx, wrsize);
 }
@@ -4795,7 +4795,8 @@ static int efm32_connect(FAR struct usbhost_driver_s *drvr,
   /* Set the connected/disconnected flag */
 
   hport->connected = connected;
-  ullinfo("Hub port %d connected: %s\n", hport->port, connected ? "YES" : "NO");
+  uinfo("Hub port %d connected: %s\n",
+        hport->port, connected ? "YES" : "NO");
 
   /* Report the connection event */
 
diff --git a/arch/arm/src/imx1/imx_decodeirq.c b/arch/arm/src/imx1/imx_decodeirq.c
index 5c35e68fab2..48164d9099c 100644
--- a/arch/arm/src/imx1/imx_decodeirq.c
+++ b/arch/arm/src/imx1/imx_decodeirq.c
@@ -74,8 +74,8 @@
 void up_decodeirq(uint32_t *regs)
 {
 #ifdef CONFIG_SUPPRESS_INTERRUPTS
-  lowsyslog(LOG_ERR, "Unexpected IRQ\n");
   CURRENT_REGS = regs;
+  err("ERROR: Unexpected IRQ\n");
   PANIC();
 #else
   uint32_t regval;
diff --git a/arch/arm/src/kinetis/kinetis_enet.c b/arch/arm/src/kinetis/kinetis_enet.c
index b8e0ed627eb..aa4b3cf1016 100644
--- a/arch/arm/src/kinetis/kinetis_enet.c
+++ b/arch/arm/src/kinetis/kinetis_enet.c
@@ -557,7 +557,7 @@ static void kinetis_receive(FAR struct kinetis_driver_s *priv)
 #ifdef CONFIG_NET_IPv4
       if (BUF->type == HTONS(ETHTYPE_IP))
         {
-          nllinfo("IPv4 frame\n");
+          ninfo("IPv4 frame\n");
           NETDEV_RXIPV4(&priv->dev);
 
           /* Handle ARP on input then give the IPv4 packet to the network
@@ -598,7 +598,7 @@ static void kinetis_receive(FAR struct kinetis_driver_s *priv)
 #ifdef CONFIG_NET_IPv6
       if (BUF->type == HTONS(ETHTYPE_IP6))
         {
-          nllinfo("Iv6 frame\n");
+          ninfo("Iv6 frame\n");
           NETDEV_RXIPV6(&priv->dev);
 
           /* Give the IPv6 packet to the network layer */
@@ -918,9 +918,9 @@ static int kinetis_ifup(struct net_driver_s *dev)
   uint8_t *mac = dev->d_mac.ether_addr_octet;
   uint32_t regval;
 
-  nerr("Bringing up: %d.%d.%d.%d\n",
-       dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff,
-       (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24);
+  ninfo("Bringing up: %d.%d.%d.%d\n",
+        dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff,
+        (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24);
 
   /* Initialize ENET buffers */
 
@@ -1695,7 +1695,7 @@ int kinetis_netinitialize(int intf)
     {
       /* We could not attach the ISR to the interrupt */
 
-      nerr("Failed to attach EMACTMR IRQ\n");
+      nerr("ERROR: Failed to attach EMACTMR IRQ\n");
       return -EAGAIN;
     }
 #endif
@@ -1706,7 +1706,7 @@ int kinetis_netinitialize(int intf)
     {
       /* We could not attach the ISR to the interrupt */
 
-      nerr("Failed to attach EMACTX IRQ\n");
+      nerr("ERROR: Failed to attach EMACTX IRQ\n");
       return -EAGAIN;
     }
 
@@ -1716,7 +1716,7 @@ int kinetis_netinitialize(int intf)
     {
       /* We could not attach the ISR to the interrupt */
 
-      nerr("Failed to attach EMACRX IRQ\n");
+      nerr("ERROR: Failed to attach EMACRX IRQ\n");
       return -EAGAIN;
     }
 
@@ -1726,7 +1726,7 @@ int kinetis_netinitialize(int intf)
     {
       /* We could not attach the ISR to the interrupt */
 
-      nerr("Failed to attach EMACMISC IRQ\n");
+      nerr("ERROR: Failed to attach EMACMISC IRQ\n");
       return -EAGAIN;
     }
 
diff --git a/arch/arm/src/kinetis/kinetis_irq.c b/arch/arm/src/kinetis/kinetis_irq.c
index 2ce3d373a9c..d2a04de3ae6 100644
--- a/arch/arm/src/kinetis/kinetis_irq.c
+++ b/arch/arm/src/kinetis/kinetis_irq.c
@@ -160,7 +160,7 @@ static void kinetis_dumpnvic(const char *msg, int irq)
 
 /****************************************************************************
  * Name: kinetis_nmi, kinetis_busfault, kinetis_usagefault, kinetis_pendsv,
- *       kinetis_errmonitor, kinetis_pendsv, kinetis_reserved
+ *       kinetis_dbgmonitor, kinetis_pendsv, kinetis_reserved
  *
  * Description:
  *   Handlers for various execptions.  None are handled and all are fatal
@@ -202,7 +202,7 @@ static int kinetis_pendsv(int irq, FAR void *context)
   return 0;
 }
 
-static int kinetis_errmonitor(int irq, FAR void *context)
+static int kinetis_dbgmonitor(int irq, FAR void *context)
 {
   (void)up_irq_save();
   _err("PANIC!!! Debug Monitor received\n");
@@ -429,7 +429,7 @@ void up_irqinitialize(void)
   irq_attach(KINETIS_IRQ_BUSFAULT, kinetis_busfault);
   irq_attach(KINETIS_IRQ_USAGEFAULT, kinetis_usagefault);
   irq_attach(KINETIS_IRQ_PENDSV, kinetis_pendsv);
-  irq_attach(KINETIS_IRQ_DBGMONITOR, kinetis_errmonitor);
+  irq_attach(KINETIS_IRQ_DBGMONITOR, kinetis_dbgmonitor);
   irq_attach(KINETIS_IRQ_RESERVED, kinetis_reserved);
 #endif
 
diff --git a/arch/arm/src/kinetis/kinetis_pwm.c b/arch/arm/src/kinetis/kinetis_pwm.c
index 9ac5afbd953..0730bf8dd83 100644
--- a/arch/arm/src/kinetis/kinetis_pwm.c
+++ b/arch/arm/src/kinetis/kinetis_pwm.c
@@ -500,7 +500,7 @@ static int pwm_timer(FAR struct kinetis_pwmtimer_s *priv,
         break;
 
       default:
-        pwmerr("No such channel: %d\n", priv->channel);
+        pwmerr("ERROR: No such channel: %d\n", priv->channel);
         return -EINVAL;
     }
 
@@ -692,7 +692,7 @@ static int pwm_stop(FAR struct pwm_lowerhalf_s *dev)
         break;
 
       default:
-        pwmerr("No such channel: %d\n", priv->channel);
+        pwmerr("ERROR: No such channel: %d\n", priv->channel);
         return -EINVAL;
     }
 
@@ -779,7 +779,7 @@ FAR struct pwm_lowerhalf_s *kinetis_pwminitialize(int timer)
 #endif
 
       default:
-        pwmerr("No such timer configured\n");
+        pwmerr("ERROR: No such timer configured\n");
         return NULL;
     }
 
diff --git a/arch/arm/src/kinetis/kinetis_sdhc.c b/arch/arm/src/kinetis/kinetis_sdhc.c
index 0b2214cb2b0..aff35be9b4d 100644
--- a/arch/arm/src/kinetis/kinetis_sdhc.c
+++ b/arch/arm/src/kinetis/kinetis_sdhc.c
@@ -89,7 +89,7 @@
 #  define CONFIG_KINETIS_SDHC_DMAPRIO DMA_CCR_PRIMED
 #endif
 
-#if !defined(CONFIG_DEBUG_FS) || !defined(CONFIG_DEBUG_INFO)
+#ifndef CONFIG_DEBUG_MEMCARD_INFO
 #  undef CONFIG_SDIO_XFRDEBUG
 #endif
 
@@ -574,29 +574,29 @@ static void kinetis_sample(struct kinetis_dev_s *priv, int index)
 static void kinetis_dumpsample(struct kinetis_dev_s *priv,
                                struct kinetis_sdhcregs_s *regs, const char *msg)
 {
-  ferr("SDHC Registers: %s\n", msg);
-  ferr("   DSADDR[%08x]: %08x\n", KINETIS_SDHC_DSADDR,    regs->dsaddr);
-  ferr("  BLKATTR[%08x]: %08x\n", KINETIS_SDHC_BLKATTR,   regs->blkattr);
-  ferr("   CMDARG[%08x]: %08x\n", KINETIS_SDHC_CMDARG,    regs->cmdarg);
-  ferr("   XFERTY[%08x]: %08x\n", KINETIS_SDHC_XFERTYP,   regs->xferty);
-  ferr("  CMDRSP0[%08x]: %08x\n", KINETIS_SDHC_CMDRSP0,   regs->cmdrsp0);
-  ferr("  CMDRSP1[%08x]: %08x\n", KINETIS_SDHC_CMDRSP1,   regs->cmdrsp1);
-  ferr("  CMDRSP2[%08x]: %08x\n", KINETIS_SDHC_CMDRSP2,   regs->cmdrsp2);
-  ferr("  CMDRSP3[%08x]: %08x\n", KINETIS_SDHC_CMDRSP3,   regs->cmdrsp3);
-  ferr("  PRSSTAT[%08x]: %08x\n", KINETIS_SDHC_PRSSTAT,   regs->prsstat);
-  ferr("   PROCTL[%08x]: %08x\n", KINETIS_SDHC_PROCTL,    regs->proctl);
-  ferr("   SYSCTL[%08x]: %08x\n", KINETIS_SDHC_SYSCTL,    regs->sysctl);
-  ferr("  IRQSTAT[%08x]: %08x\n", KINETIS_SDHC_IRQSTAT,   regs->irqstat);
-  ferr("IRQSTATEN[%08x]: %08x\n", KINETIS_SDHC_IRQSTATEN, regs->irqstaten);
-  ferr(" IRQSIGEN[%08x]: %08x\n", KINETIS_SDHC_IRQSIGEN,  regs->irqsigen);
-  ferr("  AC12ERR[%08x]: %08x\n", KINETIS_SDHC_AC12ERR,   regs->ac12err);
-  ferr(" HTCAPBLT[%08x]: %08x\n", KINETIS_SDHC_HTCAPBLT,  regs->htcapblt);
-  ferr("      WML[%08x]: %08x\n", KINETIS_SDHC_WML,       regs->wml);
-  ferr("   ADMAES[%08x]: %08x\n", KINETIS_SDHC_ADMAES,    regs->admaes);
-  ferr("  ADSADDR[%08x]: %08x\n", KINETIS_SDHC_ADSADDR,   regs->adsaddr);
-  ferr("   VENDOR[%08x]: %08x\n", KINETIS_SDHC_VENDOR,    regs->vendor);
-  ferr("  MMCBOOT[%08x]: %08x\n", KINETIS_SDHC_MMCBOOT,   regs->mmcboot);
-  ferr("  HOSTVER[%08x]: %08x\n", KINETIS_SDHC_HOSTVER,   regs->hostver);
+  mcinfo("SDHC Registers: %s\n", msg);
+  mcinfo("   DSADDR[%08x]: %08x\n", KINETIS_SDHC_DSADDR,    regs->dsaddr);
+  mcinfo("  BLKATTR[%08x]: %08x\n", KINETIS_SDHC_BLKATTR,   regs->blkattr);
+  mcinfo("   CMDARG[%08x]: %08x\n", KINETIS_SDHC_CMDARG,    regs->cmdarg);
+  mcinfo("   XFERTY[%08x]: %08x\n", KINETIS_SDHC_XFERTYP,   regs->xferty);
+  mcinfo("  CMDRSP0[%08x]: %08x\n", KINETIS_SDHC_CMDRSP0,   regs->cmdrsp0);
+  mcinfo("  CMDRSP1[%08x]: %08x\n", KINETIS_SDHC_CMDRSP1,   regs->cmdrsp1);
+  mcinfo("  CMDRSP2[%08x]: %08x\n", KINETIS_SDHC_CMDRSP2,   regs->cmdrsp2);
+  mcinfo("  CMDRSP3[%08x]: %08x\n", KINETIS_SDHC_CMDRSP3,   regs->cmdrsp3);
+  mcinfo("  PRSSTAT[%08x]: %08x\n", KINETIS_SDHC_PRSSTAT,   regs->prsstat);
+  mcinfo("   PROCTL[%08x]: %08x\n", KINETIS_SDHC_PROCTL,    regs->proctl);
+  mcinfo("   SYSCTL[%08x]: %08x\n", KINETIS_SDHC_SYSCTL,    regs->sysctl);
+  mcinfo("  IRQSTAT[%08x]: %08x\n", KINETIS_SDHC_IRQSTAT,   regs->irqstat);
+  mcinfo("IRQSTATEN[%08x]: %08x\n", KINETIS_SDHC_IRQSTATEN, regs->irqstaten);
+  mcinfo(" IRQSIGEN[%08x]: %08x\n", KINETIS_SDHC_IRQSIGEN,  regs->irqsigen);
+  mcinfo("  AC12ERR[%08x]: %08x\n", KINETIS_SDHC_AC12ERR,   regs->ac12err);
+  mcinfo(" HTCAPBLT[%08x]: %08x\n", KINETIS_SDHC_HTCAPBLT,  regs->htcapblt);
+  mcinfo("      WML[%08x]: %08x\n", KINETIS_SDHC_WML,       regs->wml);
+  mcinfo("   ADMAES[%08x]: %08x\n", KINETIS_SDHC_ADMAES,    regs->admaes);
+  mcinfo("  ADSADDR[%08x]: %08x\n", KINETIS_SDHC_ADSADDR,   regs->adsaddr);
+  mcinfo("   VENDOR[%08x]: %08x\n", KINETIS_SDHC_VENDOR,    regs->vendor);
+  mcinfo("  MMCBOOT[%08x]: %08x\n", KINETIS_SDHC_MMCBOOT,   regs->mmcboot);
+  mcinfo("  HOSTVER[%08x]: %08x\n", KINETIS_SDHC_HOSTVER,   regs->hostver);
 }
 #endif
 
@@ -791,8 +791,8 @@ static void kinetis_transmit(struct kinetis_dev_s *priv)
    * ready (BWR)
    */
 
-  fllinfo("Entry: remaining: %d IRQSTAT: %08x\n",
-          priv->remaining, getreg32(KINETIS_SDHC_IRQSTAT));
+  mcinfo("Entry: remaining: %d IRQSTAT: %08x\n",
+         priv->remaining, getreg32(KINETIS_SDHC_IRQSTAT));
 
   while (priv->remaining > 0 &&
          (getreg32(KINETIS_SDHC_IRQSTAT) & SDHC_INT_BWR) != 0)
@@ -837,9 +837,8 @@ static void kinetis_transmit(struct kinetis_dev_s *priv)
       putreg32(data.w, KINETIS_SDHC_DATPORT);
     }
 
-  fllinfo("Exit: remaining: %d IRQSTAT: %08x\n",
-          priv->remaining, getreg32(KINETIS_SDHC_IRQSTAT));
-
+  mcinfo("Exit: remaining: %d IRQSTAT: %08x\n",
+         priv->remaining, getreg32(KINETIS_SDHC_IRQSTAT));
 }
 #endif
 
@@ -877,8 +876,8 @@ static void kinetis_receive(struct kinetis_dev_s *priv)
    * ready (BRR)
    */
 
-  fllinfo("Entry: remaining: %d IRQSTAT: %08x\n",
-          priv->remaining, getreg32(KINETIS_SDHC_IRQSTAT));
+  mcinfo("Entry: remaining: %d IRQSTAT: %08x\n",
+         priv->remaining, getreg32(KINETIS_SDHC_IRQSTAT));
 
   while (priv->remaining > 0 &&
          (getreg32(KINETIS_SDHC_IRQSTAT) & SDHC_INT_BRR) != 0)
@@ -929,10 +928,9 @@ static void kinetis_receive(struct kinetis_dev_s *priv)
 
   putreg32(watermark << SDHC_WML_RD_SHIFT, KINETIS_SDHC_WML);
 
-  fllinfo("Exit: remaining: %d IRQSTAT: %08x WML: %08x\n",
-          priv->remaining, getreg32(KINETIS_SDHC_IRQSTAT),
-          getreg32(KINETIS_SDHC_WML));
-
+  mcinfo("Exit: remaining: %d IRQSTAT: %08x WML: %08x\n",
+         priv->remaining, getreg32(KINETIS_SDHC_IRQSTAT),
+         getreg32(KINETIS_SDHC_WML));
 }
 #endif
 
@@ -973,7 +971,7 @@ static void kinetis_eventtimeout(int argc, uint32_t arg)
       /* Wake up any waiting threads */
 
       kinetis_endwait(priv, SDIOWAIT_TIMEOUT);
-      fllerr("Timeout: remaining: %d\n", priv->remaining);
+      mcerr("ERROR: Timeout: remaining: %d\n", priv->remaining);
     }
 }
 
@@ -1105,8 +1103,8 @@ static int kinetis_interrupt(int irq, void *context)
 
   regval  = getreg32(KINETIS_SDHC_IRQSIGEN);
   enabled = getreg32(KINETIS_SDHC_IRQSTAT) & regval;
-  fllinfo("IRQSTAT: %08x IRQSIGEN %08x enabled: %08x\n",
-          getreg32(KINETIS_SDHC_IRQSTAT), regval, enabled);
+  mcinfo("IRQSTAT: %08x IRQSIGEN %08x enabled: %08x\n",
+         getreg32(KINETIS_SDHC_IRQSTAT), regval, enabled);
 
   /* Disable card interrupts to clear the card interrupt to the host system. */
 
@@ -1162,7 +1160,7 @@ static int kinetis_interrupt(int irq, void *context)
         {
           /* Terminate the transfer with an error */
 
-          fllerr("ERROR: Data block CRC failure, remaining: %d\n", priv->remaining);
+          mcerr("ERROR: Data block CRC failure, remaining: %d\n", priv->remaining);
           kinetis_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR);
         }
 
@@ -1172,7 +1170,7 @@ static int kinetis_interrupt(int irq, void *context)
         {
           /* Terminate the transfer with an error */
 
-          fllerr("ERROR: Data timeout, remaining: %d\n", priv->remaining);
+          mcerr("ERROR: Data timeout, remaining: %d\n", priv->remaining);
           kinetis_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_TIMEOUT);
         }
     }
@@ -1289,9 +1287,9 @@ static void kinetis_reset(FAR struct sdio_dev_s *dev)
 
   putreg32(SDHC_INT_ALL, KINETIS_SDHC_IRQSTATEN);
 
-  finfo("SYSCTL: %08x PRSSTAT: %08x IRQSTATEN: %08x\n",
-        getreg32(KINETIS_SDHC_SYSCTL), getreg32(KINETIS_SDHC_PRSSTAT),
-        getreg32(KINETIS_SDHC_IRQSTATEN));
+  mcinfo("SYSCTL: %08x PRSSTAT: %08x IRQSTATEN: %08x\n",
+         getreg32(KINETIS_SDHC_SYSCTL), getreg32(KINETIS_SDHC_PRSSTAT),
+         getreg32(KINETIS_SDHC_IRQSTATEN));
 
   /* The next phase of the hardware reset would be to set the SYSCTRL INITA
    * bit to send 80 clock ticks for card to power up and then reset the card
@@ -1504,7 +1502,7 @@ static void kinetis_frequency(FAR struct sdio_dev_s *dev, uint32_t frequency)
   regval |= (SDHC_SYSCTL_SDCLKEN | SDHC_SYSCTL_PEREN | SDHC_SYSCTL_HCKEN |
              SDHC_SYSCTL_IPGEN);
   putreg32(regval, KINETIS_SDHC_SYSCTL);
-  finfo("SYSCTRL: %08x\n", getreg32(KINETIS_SDHC_SYSCTL));
+  mcinfo("SYSCTRL: %08x\n", getreg32(KINETIS_SDHC_SYSCTL));
 }
 #endif
 
@@ -1538,7 +1536,7 @@ static void kinetis_clock(FAR struct sdio_dev_s *dev, enum sdio_clock_e rate)
   regval  = getreg32(KINETIS_SDHC_SYSCTL);
   regval &= ~SDHC_SYSCTL_SDCLKEN;
   putreg32(regval, KINETIS_SDHC_SYSCTL);
-  finfo("SYSCTRL: %08x\n", getreg32(KINETIS_SDHC_SYSCTL));
+  mcinfo("SYSCTRL: %08x\n", getreg32(KINETIS_SDHC_SYSCTL));
 
   switch (rate)
     {
@@ -1552,7 +1550,7 @@ static void kinetis_clock(FAR struct sdio_dev_s *dev, enum sdio_clock_e rate)
           regval &= ~(SDHC_SYSCTL_IPGEN | SDHC_SYSCTL_HCKEN | SDHC_SYSCTL_PEREN |
                       SDHC_SYSCTL_SDCLKFS_MASK | SDHC_SYSCTL_DVS_MASK);
           putreg32(regval, KINETIS_SDHC_SYSCTL);
-          finfo("SYSCTRL: %08x\n", getreg32(KINETIS_SDHC_SYSCTL));
+          mcinfo("SYSCTRL: %08x\n", getreg32(KINETIS_SDHC_SYSCTL));
           return;
         }
 
@@ -1593,7 +1591,7 @@ static void kinetis_clock(FAR struct sdio_dev_s *dev, enum sdio_clock_e rate)
   regval  = getreg32(KINETIS_SDHC_SYSCTL);
   regval &= ~SDHC_SYSCTL_SDCLKEN;
   putreg32(regval, KINETIS_SDHC_SYSCTL);
-  finfo("SYSCTRL: %08x\n", getreg32(KINETIS_SDHC_SYSCTL));
+  mcinfo("SYSCTRL: %08x\n", getreg32(KINETIS_SDHC_SYSCTL));
 
   /* Clear the old prescaler and divisor values so that new ones can be ORed
    * in.
@@ -1619,7 +1617,7 @@ static void kinetis_clock(FAR struct sdio_dev_s *dev, enum sdio_clock_e rate)
 
           regval &= ~(SDHC_SYSCTL_IPGEN | SDHC_SYSCTL_HCKEN | SDHC_SYSCTL_PEREN);
           putreg32(regval, KINETIS_SDHC_SYSCTL);
-          finfo("SYSCTRL: %08x\n", getreg32(KINETIS_SDHC_SYSCTL));
+          mcinfo("SYSCTRL: %08x\n", getreg32(KINETIS_SDHC_SYSCTL));
           return;
         }
 
@@ -1653,7 +1651,7 @@ static void kinetis_clock(FAR struct sdio_dev_s *dev, enum sdio_clock_e rate)
     }
 
   putreg32(regval, KINETIS_SDHC_SYSCTL);
-  finfo("SYSCTRL: %08x\n", getreg32(KINETIS_SDHC_SYSCTL));
+  mcinfo("SYSCTRL: %08x\n", getreg32(KINETIS_SDHC_SYSCTL));
 }
 #endif
 
@@ -1824,7 +1822,7 @@ static int kinetis_sendcmd(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t ar
 
   /* Other bits? What about CMDTYP? */
 
-  finfo("cmd: %08x arg: %08x regval: %08x\n", cmd, arg, regval);
+  mcinfo("cmd: %08x arg: %08x regval: %08x\n", cmd, arg, regval);
 
   /* The Command Inhibit (CIHB) bit is set in the PRSSTAT bit immediately
    * after the transfer type register is written.  This bit is cleared when
@@ -1840,8 +1838,8 @@ static int kinetis_sendcmd(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t ar
     {
       if (--timeout <= 0)
         {
-          ferr("ERROR: Timeout cmd: %08x PRSSTAT: %08x\n",
-               cmd, getreg32(KINETIS_SDHC_PRSSTAT));
+          mcerr("ERROR: Timeout cmd: %08x PRSSTAT: %08x\n",
+                cmd, getreg32(KINETIS_SDHC_PRSSTAT));
 
           return -EBUSY;
         }
@@ -2079,8 +2077,8 @@ static int kinetis_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd)
     {
       if (--timeout <= 0)
         {
-          ferr("ERROR: Timeout cmd: %08x IRQSTAT: %08x\n",
-               cmd, getreg32(KINETIS_SDHC_IRQSTAT));
+          mcerr("ERROR: Timeout cmd: %08x IRQSTAT: %08x\n",
+                cmd, getreg32(KINETIS_SDHC_IRQSTAT));
 
           return -ETIMEDOUT;
         }
@@ -2090,8 +2088,8 @@ static int kinetis_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd)
 
   if ((getreg32(KINETIS_SDHC_IRQSTAT) & errors) != 0)
     {
-      ferr("ERROR: cmd: %08x errors: %08x IRQSTAT: %08x\n",
-           cmd, errors, getreg32(KINETIS_SDHC_IRQSTAT));
+      mcerr("ERROR: cmd: %08x errors: %08x IRQSTAT: %08x\n",
+            cmd, errors, getreg32(KINETIS_SDHC_IRQSTAT));
       ret = -EIO;
     }
 
@@ -2155,7 +2153,7 @@ static int kinetis_recvshortcrc(FAR struct sdio_dev_s *dev, uint32_t cmd,
 #ifdef CONFIG_DEBUG_FEATURES
   if (!rshort)
     {
-      ferr("ERROR: rshort=NULL\n");
+      mcerr("ERROR: rshort=NULL\n");
       ret = -EINVAL;
     }
 
@@ -2165,7 +2163,7 @@ static int kinetis_recvshortcrc(FAR struct sdio_dev_s *dev, uint32_t cmd,
            (cmd & MMCSD_RESPONSE_MASK) != MMCSD_R1B_RESPONSE &&
            (cmd & MMCSD_RESPONSE_MASK) != MMCSD_R6_RESPONSE)
     {
-      ferr("ERROR: Wrong response CMD=%08x\n", cmd);
+      mcerr("ERROR: Wrong response CMD=%08x\n", cmd);
       ret = -EINVAL;
     }
   else
@@ -2176,12 +2174,12 @@ static int kinetis_recvshortcrc(FAR struct sdio_dev_s *dev, uint32_t cmd,
       regval = getreg32(KINETIS_SDHC_IRQSTAT);
       if ((regval & SDHC_INT_CTOE) != 0)
         {
-          ferr("ERROR: Command timeout: %08x\n", regval);
+          mcerr("ERROR: Command timeout: %08x\n", regval);
           ret = -ETIMEDOUT;
         }
       else if ((regval & SDHC_INT_CCE) != 0)
         {
-          ferr("ERROR: CRC failure: %08x\n", regval);
+          mcerr("ERROR: CRC failure: %08x\n", regval);
           ret = -EIO;
         }
     }
@@ -2214,7 +2212,7 @@ static int kinetis_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t r
 
   if ((cmd & MMCSD_RESPONSE_MASK) != MMCSD_R2_RESPONSE)
     {
-      ferr("ERROR: Wrong response CMD=%08x\n", cmd);
+      mcerr("ERROR: Wrong response CMD=%08x\n", cmd);
       ret = -EINVAL;
     }
   else
@@ -2225,12 +2223,12 @@ static int kinetis_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t r
       regval = getreg32(KINETIS_SDHC_IRQSTAT);
       if (regval & SDHC_INT_CTOE)
         {
-          ferr("ERROR: Timeout IRQSTAT: %08x\n", regval);
+          mcerr("ERROR: Timeout IRQSTAT: %08x\n", regval);
           ret = -ETIMEDOUT;
         }
       else if (regval & SDHC_INT_CCE)
         {
-          ferr("ERROR: CRC fail IRQSTAT: %08x\n", regval);
+          mcerr("ERROR: CRC fail IRQSTAT: %08x\n", regval);
           ret = -EIO;
         }
     }
@@ -2267,7 +2265,7 @@ static int kinetis_recvshort(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t
   if ((cmd & MMCSD_RESPONSE_MASK) != MMCSD_R3_RESPONSE &&
       (cmd & MMCSD_RESPONSE_MASK) != MMCSD_R7_RESPONSE)
     {
-      ferr("ERROR: Wrong response CMD=%08x\n", cmd);
+      mcerr("ERROR: Wrong response CMD=%08x\n", cmd);
       ret = -EINVAL;
     }
   else
@@ -2280,7 +2278,7 @@ static int kinetis_recvshort(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t
       regval = getreg32(KINETIS_SDHC_IRQSTAT);
       if (regval & SDHC_INT_CTOE)
         {
-          ferr("ERROR: Timeout IRQSTAT: %08x\n", regval);
+          mcerr("ERROR: Timeout IRQSTAT: %08x\n", regval);
           ret = -ETIMEDOUT;
         }
     }
@@ -2416,7 +2414,7 @@ static sdio_eventset_t kinetis_eventwait(FAR struct sdio_dev_s *dev,
                        1, (uint32_t)priv);
       if (ret != OK)
         {
-          ferr("ERROR: wd_start failed: %d\n", ret);
+          mcerr("ERROR: wd_start failed: %d\n", ret);
         }
     }
 
@@ -2486,7 +2484,7 @@ static void kinetis_callbackenable(FAR struct sdio_dev_s *dev,
 {
   struct kinetis_dev_s *priv = (struct kinetis_dev_s *)dev;
 
-  finfo("eventset: %02x\n", eventset);
+  mcinfo("eventset: %02x\n", eventset);
   DEBUGASSERT(priv != NULL);
 
   priv->cbevents = eventset;
@@ -2522,7 +2520,7 @@ static int kinetis_registercallback(FAR struct sdio_dev_s *dev,
 
   /* Disable callbacks and register this callback and is argument */
 
-  finfo("Register %p(%p)\n", callback, arg);
+  mcinfo("Register %p(%p)\n", callback, arg);
   DEBUGASSERT(priv != NULL);
 
   priv->cbevents = 0;
@@ -2694,8 +2692,8 @@ static void kinetis_callback(void *arg)
   /* Is a callback registered? */
 
   DEBUGASSERT(priv != NULL);
-  finfo("Callback %p(%p) cbevents: %02x cdstatus: %02x\n",
-        priv->callback, priv->cbarg, priv->cbevents, priv->cdstatus);
+  mcinfo("Callback %p(%p) cbevents: %02x cdstatus: %02x\n",
+         priv->callback, priv->cbarg, priv->cbevents, priv->cdstatus);
 
   if (priv->callback)
     {
@@ -2739,14 +2737,14 @@ static void kinetis_callback(void *arg)
         {
           /* Yes.. queue it */
 
-           finfo("Queuing callback to %p(%p)\n", priv->callback, priv->cbarg);
+           mcinfo("Queuing callback to %p(%p)\n", priv->callback, priv->cbarg);
           (void)work_queue(HPWORK, &priv->cbwork, (worker_t)priv->callback, priv->cbarg, 0);
         }
       else
         {
           /* No.. then just call the callback here */
 
-          finfo("Callback to %p(%p)\n", priv->callback, priv->cbarg);
+          mcinfo("Callback to %p(%p)\n", priv->callback, priv->cbarg);
           priv->callback(priv->cbarg);
         }
     }
@@ -2792,7 +2790,7 @@ FAR struct sdio_dev_s *sdhc_initialize(int slotno)
   regval = getreg32(KINETIS_SIM_SCGC3);
   regval |= SIM_SCGC3_SDHC;
   putreg32(regval, KINETIS_SIM_SCGC3);
-  finfo("SIM_SCGC3: %08x\n", regval);
+  mcinfo("SIM_SCGC3: %08x\n", regval);
 
   /* In addition to the system clock, the SDHC module needs a clock for the
    * base for the external card clock.  There are four possible sources for
@@ -2808,7 +2806,7 @@ FAR struct sdio_dev_s *sdhc_initialize(int slotno)
   regval &= ~SIM_SOPT2_SDHCSRC_MASK;
   regval |= SIM_SOPT2_SDHCSRC_CORE;
   putreg32(regval, KINETIS_SIM_SOPT2);
-  finfo("SIM_SOPT2: %08x\n", regval);
+  mcinfo("SIM_SOPT2: %08x\n", regval);
 
   /* Configure pins for 1 or 4-bit, wide-bus operation (the chip is capable
    * of 8-bit wide bus operation but D4-D7 are not configured).
@@ -2892,7 +2890,7 @@ void sdhc_mediachange(FAR struct sdio_dev_s *dev, bool cardinslot)
       priv->cdstatus &= ~SDIO_STATUS_PRESENT;
     }
 
-  finfo("cdstatus OLD: %02x NEW: %02x\n", cdstatus, priv->cdstatus);
+  mcinfo("cdstatus OLD: %02x NEW: %02x\n", cdstatus, priv->cdstatus);
 
   /* Perform any requested callback if the status has changed */
 
@@ -2937,7 +2935,7 @@ void sdhc_wrprotect(FAR struct sdio_dev_s *dev, bool wrprotect)
       priv->cdstatus &= ~SDIO_STATUS_WRPROTECTED;
     }
 
-  finfo("cdstatus: %02x\n", priv->cdstatus);
+  mcinfo("cdstatus: %02x\n", priv->cdstatus);
   leave_critical_section(flags);
 }
 #endif /* CONFIG_KINETIS_SDHC */
diff --git a/arch/arm/src/kinetis/kinetis_serial.c b/arch/arm/src/kinetis/kinetis_serial.c
index 084204daa91..d47235ba90b 100644
--- a/arch/arm/src/kinetis/kinetis_serial.c
+++ b/arch/arm/src/kinetis/kinetis_serial.c
@@ -805,7 +805,7 @@ static int up_interrupt(int irq, void *context)
    */
 
   regval = up_serialin(priv, KINETIS_UART_S1_OFFSET);
-  _llerr("S1: %02x\n", regval);
+  _info("S1: %02x\n", regval);
   UNUSED(regval);
 
   regval = up_serialin(priv, KINETIS_UART_D_OFFSET);
diff --git a/arch/arm/src/kinetis/kinetis_start.c b/arch/arm/src/kinetis/kinetis_start.c
index 6744012f070..8de2524ef56 100644
--- a/arch/arm/src/kinetis/kinetis_start.c
+++ b/arch/arm/src/kinetis/kinetis_start.c
@@ -156,8 +156,8 @@ void __start(void)
 
   /* Show reset status */
 
-  _err("Reset status: %02x:%02x\n",
-      getreg8(KINETIS_SMC_SRSH), getreg8(KINETIS_SMC_SRSL));
+  _warn("Reset status: %02x:%02x\n",
+        getreg8(KINETIS_SMC_SRSH), getreg8(KINETIS_SMC_SRSL));
 
   /* Then start NuttX */
 
diff --git a/arch/arm/src/kinetis/kinetis_usbdev.c b/arch/arm/src/kinetis/kinetis_usbdev.c
index 406880cb2ae..8deedb7603c 100644
--- a/arch/arm/src/kinetis/kinetis_usbdev.c
+++ b/arch/arm/src/kinetis/kinetis_usbdev.c
@@ -86,7 +86,7 @@
  * enabled.
  */
 
-#ifndef CONFIG_DEBUG_FEATURES
+#ifndef CONFIG_DEBUG_USB_INFO
 #  undef CONFIG_KHCI_USBDEV_REGDEBUG
 #  undef CONFIG_KHCI_USBDEV_BDTDEBUG
 #endif
@@ -365,42 +365,21 @@ const struct trace_msg_t g_usb_trace_strings_deverror[] =
  */
 
 #ifdef CONFIG_KHCI_USBDEV_REGDEBUG
-
 #  undef CONFIG_KHCI_USBDEV_BDTDEBUG
 #  define CONFIG_KHCI_USBDEV_BDTDEBUG 1
-
-#  define regerr  _llerr
-#  ifdef CONFIG_DEBUG_INFO
-#    define reginfo  _llerr
-#  else
-#    define reginfo(x...)
-#  endif
-
 #else
-
 #  define khci_getreg(addr)      getreg8(addr)
 #  define khci_putreg(val,addr)  putreg8(val,addr)
-#  define regerr(x...)
-#  define reginfo(x...)
-
 #endif
 
 /* CONFIG_KHCI_USBDEV_BDTDEBUG dumps most BDT settings */
 
 #ifdef CONFIG_KHCI_USBDEV_BDTDEBUG
-
-#  define bdterr  _llerr
-#  ifdef CONFIG_DEBUG_INFO
-#    define bdtinfo  _llerr
-#  else
-#    define bdtinfo(x...)
-#  endif
-
+#  define bdterr  uerr
+#  define bdtinfo uinfo
 #else
-
 #  define bdterr(x...)
 #  define bdtinfo(x...)
-
 #endif
 
 /****************************************************************************
@@ -714,7 +693,7 @@ static uint16_t khci_getreg(uint32_t addr)
         {
            if (count == 4)
              {
-               _llerr("...\n");
+               uinfo("...\n");
              }
           return val;
         }
@@ -730,7 +709,7 @@ static uint16_t khci_getreg(uint32_t addr)
          {
            /* Yes.. then show how many times the value repeated */
 
-           _llerr("[repeats %d more times]\n", count-3);
+           uinfo("[repeats %d more times]\n", count-3);
          }
 
        /* Save the new address, value, and count */
@@ -742,7 +721,7 @@ static uint16_t khci_getreg(uint32_t addr)
 
   /* Show the register value read */
 
-  _llerr("%08x->%04x\n", addr, val);
+  uinfo("%08x->%04x\n", addr, val);
   return val;
 }
 #endif
@@ -756,7 +735,7 @@ static void khci_putreg(uint32_t val, uint32_t addr)
 {
   /* Show the register value being written */
 
-  _llerr("%08x<-%04x\n", addr, val);
+  uinfo("%08x<-%04x\n", addr, val);
 
   /* Write the value */
 
@@ -953,8 +932,8 @@ static void khci_epwrite(struct khci_ep_s *privep,
 
   /* And, finally, give the BDT to the USB */
 
-  bdterr("EP%d BDT IN [%p] {%08x, %08x}\n",
-         USB_EPNO(privep->ep.eplog), bdt, status, bdt->addr);
+  bdtinfo("EP%d BDT IN [%p] {%08x, %08x}\n",
+          USB_EPNO(privep->ep.eplog), bdt, status, bdt->addr);
 
   bdt->status = status;
 }
@@ -987,15 +966,15 @@ static void khci_wrcomplete(struct khci_usbdev_s *priv,
   epno   = USB_EPNO(privep->ep.eplog);
 
 #ifdef CONFIG_USBDEV_NOWRITEAHEAD
-  ullinfo("EP%d: len=%d xfrd=%d inflight=%d\n",
-          epno, privreq->req.len, privreq->req.xfrd, privreq->inflight[0]);
+  uinfo("EP%d: len=%d xfrd=%d inflight=%d\n",
+        epno, privreq->req.len, privreq->req.xfrd, privreq->inflight[0]);
 #else
-  ullinfo("EP%d: len=%d xfrd=%d inflight={%d, %d}\n",
-          epno, privreq->req.len, privreq->req.xfrd,
-          privreq->inflight[0], privreq->inflight[1]);
+  uinfo("EP%d: len=%d xfrd=%d inflight={%d, %d}\n",
+        epno, privreq->req.len, privreq->req.xfrd,
+        privreq->inflight[0], privreq->inflight[1]);
 #endif
-  bdterr("EP%d BDT IN [%p] {%08x, %08x}\n",
-         epno, bdtin, bdtin->status, bdtin->addr);
+  bdtinfo("EP%d BDT IN [%p] {%08x, %08x}\n",
+        epno, bdtin, bdtin->status, bdtin->addr);
 
   /* We should own the BDT that just completed. But NULLify the entire BDT IN.
    * Why?  So that we can tell later that the BDT available.  No, it is not
@@ -1303,8 +1282,8 @@ static int khci_wrstart(struct khci_usbdev_s *priv,
       bytesleft = privreq->req.len;
     }
 
-  ullinfo("epno=%d req=%p: len=%d xfrd=%d index=%d nullpkt=%d\n",
-          epno, privreq, privreq->req.len, xfrd, index, privep->txnullpkt);
+  uinfo("epno=%d req=%p: len=%d xfrd=%d index=%d nullpkt=%d\n",
+        epno, privreq, privreq->req.len, xfrd, index, privep->txnullpkt);
 
   /* Get the number of bytes left to be sent in the packet */
 
@@ -1417,10 +1396,10 @@ static int khci_rdcomplete(struct khci_usbdev_s *priv,
   bdtout = privep->bdtout;
   epno   = USB_EPNO(privep->ep.eplog);
 
-  ullinfo("EP%d: len=%d xfrd=%d\n",
-          epno, privreq->req.len, privreq->req.xfrd);
-  bdterr("EP%d BDT OUT [%p] {%08x, %08x}\n",
-         epno, bdtout, bdtout->status, bdtout->addr);
+  uinfo("EP%d: len=%d xfrd=%d\n",
+        epno, privreq->req.len, privreq->req.xfrd);
+  bdtinfo("EP%d BDT OUT [%p] {%08x, %08x}\n",
+        epno, bdtout, bdtout->status, bdtout->addr);
 
   /* We should own the BDT that just completed */
 
@@ -1563,7 +1542,7 @@ static int khci_ep0rdsetup(struct khci_usbdev_s *priv, uint8_t *dest,
 
   /* Then give the BDT to the USB */
 
-  bdterr("EP0 BDT OUT [%p] {%08x, %08x}\n", bdtout, status, bdtout->addr);
+  bdtinfo("EP0 BDT OUT [%p] {%08x, %08x}\n", bdtout, status, bdtout->addr);
   bdtout->status = status;
 
   priv->ctrlstate = CTRLSTATE_RDREQUEST;
@@ -1664,7 +1643,8 @@ static int khci_rdsetup(struct khci_ep_s *privep, uint8_t *dest, int readlen)
 
   /* Then give the BDT to the USB */
 
-  bdterr("EP%d BDT OUT [%p] {%08x, %08x}\n",  epno, bdtout, status, bdtout->addr);
+  bdtinfo("EP%d BDT OUT [%p] {%08x, %08x}\n", 
+          epno, bdtout, status, bdtout->addr);
 
   bdtout->status = status;
   return OK;
@@ -1705,7 +1685,7 @@ static int khci_rdrequest(struct khci_usbdev_s *priv,
       return OK;
     }
 
-  ullinfo("EP%d: len=%d\n", USB_EPNO(privep->ep.eplog), privreq->req.len);
+  uinfo("EP%d: len=%d\n", USB_EPNO(privep->ep.eplog), privreq->req.len);
 
   /* Ignore any attempt to receive a zero length packet */
 
@@ -1995,8 +1975,8 @@ static void khci_ep0setup(struct khci_usbdev_s *priv)
   index.w = GETUINT16(priv->ctrl.index);
   len.w   = GETUINT16(priv->ctrl.len);
 
-  ullinfo("SETUP: type=%02x req=%02x value=%04x index=%04x len=%04x\n",
-          priv->ctrl.type, priv->ctrl.req, value.w, index.w, len.w);
+  uinfo("SETUP: type=%02x req=%02x value=%04x index=%04x len=%04x\n",
+        priv->ctrl.type, priv->ctrl.req, value.w, index.w, len.w);
 
   /* Dispatch any non-standard requests */
 
@@ -2239,7 +2219,7 @@ static void khci_ep0setup(struct khci_usbdev_s *priv)
               {
                 /* Special case recipient=device test mode */
 
-                ullinfo("test mode: %d\n", index.w);
+                uinfo("test mode: %d\n", index.w);
               }
             else
               {
@@ -2676,7 +2656,7 @@ static void khci_ep0transfer(struct khci_usbdev_s *priv, uint16_t ustat)
       bdt   = &g_bdt[index];
       priv->eplist[0].bdtout = bdt;
 
-      bdterr("EP0 BDT OUT [%p] {%08x, %08x}\n", bdt, bdt->status, bdt->addr);
+      bdtinfo("EP0 BDT OUT [%p] {%08x, %08x}\n", bdt, bdt->status, bdt->addr);
 
       /* Check the current EP0 OUT buffer contains a SETUP packet */
 
@@ -2913,7 +2893,7 @@ x
   if ((usbir & USB_INT_ERROR) != 0)
     {
       usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_UERR), usbir);
-      ullerr("Error: EIR=%04x\n", khci_getreg(KINETIS_USB0_ERRSTAT));
+      uerr("ERROR: EIR=%04x\n", khci_getreg(KINETIS_USB0_ERRSTAT));
 
       /* Clear all pending USB error interrupts */
 
@@ -3241,7 +3221,7 @@ static int khci_epconfigure(struct usbdev_ep_s *ep,
   if (!ep || !desc)
     {
       usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_INVALIDPARMS), 0);
-      ullerr("ERROR: ep=%p desc=%p\n");
+      uerr("ERROR: ep=%p desc=%p\n");
       return -EINVAL;
     }
 #endif
@@ -3299,7 +3279,8 @@ static int khci_epconfigure(struct usbdev_ep_s *ep,
       bdt->status = 0;
       bdt->addr   = 0;
 
-      bdterr("EP%d BDT IN [%p] {%08x, %08x}\n", epno, bdt, bdt->status, bdt->addr);
+      bdtinfo("EP%d BDT IN [%p] {%08x, %08x}\n",
+              epno, bdt, bdt->status, bdt->addr);
 
       /* Now do the same for the other buffer. */
 
@@ -3307,7 +3288,8 @@ static int khci_epconfigure(struct usbdev_ep_s *ep,
       bdt->status = 0;
       bdt->addr   = 0;
 
-      bdterr("EP%d BDT IN [%p] {%08x, %08x}\n", epno, bdt, bdt->status, bdt->addr);
+      bdtinfo("EP%d BDT IN [%p] {%08x, %08x}\n",
+              epno, bdt, bdt->status, bdt->addr);
     }
 
   if (!epin || bidi)
@@ -3321,7 +3303,8 @@ static int khci_epconfigure(struct usbdev_ep_s *ep,
       bdt->status = 0;
       bdt->addr   = 0;
 
-      bdterr("EP%d BDT OUT [%p] {%08x, %08x}\n", epno, bdt, bdt->status, bdt->addr);
+      bdtinfo("EP%d BDT OUT [%p] {%08x, %08x}\n",
+              epno, bdt, bdt->status, bdt->addr);
 
       /* Now do the same for the other buffer. */
 
@@ -3329,7 +3312,8 @@ static int khci_epconfigure(struct usbdev_ep_s *ep,
       bdt->status = 0;
       bdt->addr   = 0;
 
-      bdterr("EP%d BDT OUT [%p] {%08x, %08x}\n", epno, bdt, bdt->status, bdt->addr);
+      bdtinfo("EP%d BDT OUT [%p] {%08x, %08x}\n",
+              epno, bdt, bdt->status, bdt->addr);
     }
 
   /* Get the maxpacket size of the endpoint. */
@@ -3368,7 +3352,7 @@ static int khci_epdisable(struct usbdev_ep_s *ep)
   if (!ep)
     {
       usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_INVALIDPARMS), 0);
-      ullerr("ERROR: ep=%p\n", ep);
+      uerr("ERROR: ep=%p\n", ep);
       return -EINVAL;
     }
 #endif
@@ -3467,7 +3451,8 @@ static int khci_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req)
   if (!req || !req->callback || !req->buf || !ep)
     {
       usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_INVALIDPARMS), 0);
-      ullerr("ERROR: req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, ep);
+      uerr("ERROR: req=%p callback=%p buf=%p ep=%p\n",
+           req, req->callback, req->buf, ep);
       return -EINVAL;
     }
 #endif
@@ -3479,7 +3464,7 @@ static int khci_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req)
   if (!priv->driver)
     {
       usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_NOTCONFIGURED), priv->usbdev.speed);
-      ullerr("ERROR: driver=%p\n", priv->driver);
+      uerr("ERROR: driver=%p\n", priv->driver);
       return -ESHUTDOWN;
     }
 #endif
@@ -3666,10 +3651,10 @@ static int khci_epbdtstall(struct usbdev_ep_s *ep, bool resume, bool epin)
           bdt->addr          = (uint8_t *)physaddr;
           bdt->status        = (USB_BDT_UOWN | bytecount);
 
-          bdterr("EP0 BDT IN [%p] {%08x, %08x}\n",
-                 bdt, bdt->status, bdt->addr);
-          bdterr("EP0 BDT IN [%p] {%08x, %08x}\n",
-                 otherbdt, otherbdt->status, otherbdt->addr);
+          bdtinfo("EP0 BDT IN [%p] {%08x, %08x}\n",
+                  bdt, bdt->status, bdt->addr);
+          bdtinfo("EP0 BDT IN [%p] {%08x, %08x}\n",
+                  otherbdt, otherbdt->status, otherbdt->addr);
         }
       else
         {
@@ -3683,10 +3668,10 @@ static int khci_epbdtstall(struct usbdev_ep_s *ep, bool resume, bool epin)
           bdt->addr        = 0;
           bdt->status      = 0;
 
-          bdterr("EP%d BDT %s [%p] {%08x, %08x}\n",
-                 epno, epin ? "IN" : "OUT", bdt, bdt->status, bdt->addr);
-          bdterr("EP%d BDT %s [%p] {%08x, %08x}\n",
-                 epno, epin ? "IN" : "OUT", otherbdt, otherbdt->status, otherbdt->addr);
+          bdtinfo("EP%d BDT %s [%p] {%08x, %08x}\n",
+                  epno, epin ? "IN" : "OUT", bdt, bdt->status, bdt->addr);
+          bdtinfo("EP%d BDT %s [%p] {%08x, %08x}\n",
+                  epno, epin ? "IN" : "OUT", otherbdt, otherbdt->status, otherbdt->addr);
 
           /* Restart any queued requests (after a delay so that we can be assured
            * that the hardware has recovered from the stall -- I don't know of any
@@ -3718,10 +3703,10 @@ static int khci_epbdtstall(struct usbdev_ep_s *ep, bool resume, bool epin)
 
       khci_rqstop(privep);
 
-      bdterr("EP%d BDT %s [%p] {%08x, %08x}\n",
-             epno, epin ? "IN" : "OUT", bdt, bdt->status, bdt->addr);
-      bdterr("EP%d BDT %s [%p] {%08x, %08x}\n",
-             epno, epin ? "IN" : "OUT", otherbdt, otherbdt->status, otherbdt->addr);
+      bdtinfo("EP%d BDT %s [%p] {%08x, %08x}\n",
+              epno, epin ? "IN" : "OUT", bdt, bdt->status, bdt->addr);
+      bdtinfo("EP%d BDT %s [%p] {%08x, %08x}\n",
+              epno, epin ? "IN" : "OUT", otherbdt, otherbdt->status, otherbdt->addr);
     }
 
   return OK;
@@ -4248,10 +4233,10 @@ static void khci_hwreset(struct khci_usbdev_s *priv)
   khci_putreg((uint8_t)((uint32_t)g_bdt >> 16), KINETIS_USB0_BDTPAGE2);
   khci_putreg((uint8_t)(((uint32_t)g_bdt >>  8) & USB_BDTPAGE1_MASK), KINETIS_USB0_BDTPAGE1);
 
-  ullerr("BDT Address %hhx \n" ,&g_bdt);
-  ullerr("BDTPAGE3 %hhx\n",khci_getreg(KINETIS_USB0_BDTPAGE3));
-  ullerr("BDTPAGE2 %hhx\n",khci_getreg(KINETIS_USB0_BDTPAGE2));
-  ullerr("BDTPAGE1 %hhx\n",khci_getreg(KINETIS_USB0_BDTPAGE1));
+  uinfo("BDT Address %hhx \n" ,&g_bdt);
+  uinfo("BDTPAGE3 %hhx\n",khci_getreg(KINETIS_USB0_BDTPAGE3));
+  uinfo("BDTPAGE2 %hhx\n",khci_getreg(KINETIS_USB0_BDTPAGE2));
+  uinfo("BDTPAGE1 %hhx\n",khci_getreg(KINETIS_USB0_BDTPAGE1));
 
   /* Clear any pending interrupts */
 
diff --git a/arch/arm/src/kl/kl_dumpgpio.c b/arch/arm/src/kl/kl_dumpgpio.c
index 8ca8e150023..0e6dadfd8ef 100644
--- a/arch/arm/src/kl/kl_dumpgpio.c
+++ b/arch/arm/src/kl/kl_dumpgpio.c
@@ -118,12 +118,12 @@ void kl_dumpgpio(gpio_cfgset_t pinset, const char *msg)
 
   flags = enter_critical_section();
 
-  _llinfo("GPIO%c pinset: %08x base: %08x -- %s\n",
-         g_portchar[port], pinset, base, msg);
-  _llinfo("  PDOR: %08x  PDIR: %08x  PDDR: %08x\n",
-         getreg32(base + KL_GPIO_PDOR_OFFSET),
-         getreg32(base + KL_GPIO_PDIR_OFFSET),
-         getreg32(base + KL_GPIO_PDDR_OFFSET));
+  _info("GPIO%c pinset: %08x base: %08x -- %s\n",
+       g_portchar[port], pinset, base, msg);
+  _info("  PDOR: %08x  PDIR: %08x  PDDR: %08x\n",
+       getreg32(base + KL_GPIO_PDOR_OFFSET),
+       getreg32(base + KL_GPIO_PDIR_OFFSET),
+       getreg32(base + KL_GPIO_PDDR_OFFSET));
 
   leave_critical_section(flags);
 }
diff --git a/arch/arm/src/kl/kl_idle.c b/arch/arm/src/kl/kl_idle.c
index 1122cf43917..f7db42f276c 100644
--- a/arch/arm/src/kl/kl_idle.c
+++ b/arch/arm/src/kl/kl_idle.c
@@ -103,7 +103,7 @@ static void up_idlepm(void)
 
       /* Perform board-specific, state-dependent logic here */
 
-      _llinfo("newstate= %d oldstate=%d\n", newstate, oldstate);
+      _info("newstate= %d oldstate=%d\n", newstate, oldstate);
 
       /* Then force the global state change */
 
diff --git a/arch/arm/src/kl/kl_irq.c b/arch/arm/src/kl/kl_irq.c
index c76a07ed25c..b37f7afe1c9 100644
--- a/arch/arm/src/kl/kl_irq.c
+++ b/arch/arm/src/kl/kl_irq.c
@@ -128,7 +128,7 @@ static void kl_dumpnvic(const char *msg, int irq)
 
 /****************************************************************************
  * Name: kl_nmi, kl_busfault, kl_usagefault, kl_pendsv,
- *       kl_errmonitor, kl_pendsv, kl_reserved
+ *       kl_dbgmonitor, kl_pendsv, kl_reserved
  *
  * Description:
  *   Handlers for various execptions.  None are handled and all are fatal
diff --git a/arch/arm/src/kl/kl_pwm.c b/arch/arm/src/kl/kl_pwm.c
index 3da236c34cc..6f3f6e40503 100644
--- a/arch/arm/src/kl/kl_pwm.c
+++ b/arch/arm/src/kl/kl_pwm.c
@@ -464,7 +464,7 @@ static int pwm_timer(FAR struct kl_pwmtimer_s *priv,
         break;
 
       default:
-        pwmerr("No such channel: %d\n", priv->channel);
+        pwmerr("ERROR: No such channel: %d\n", priv->channel);
         return -EINVAL;
     }
 
@@ -644,7 +644,7 @@ static int pwm_stop(FAR struct pwm_lowerhalf_s *dev)
         break;
 
       default:
-        pwmerr("No such channel: %d\n", priv->channel);
+        pwmerr("ERROR: No such channel: %d\n", priv->channel);
         return -EINVAL;
     }
 
@@ -731,7 +731,7 @@ FAR struct pwm_lowerhalf_s *kl_pwminitialize(int timer)
 #endif
 
       default:
-        pwmerr("No such timer configured\n");
+        pwmerr("ERROR: No such timer configured\n");
         return NULL;
     }
 
diff --git a/arch/arm/src/kl/kl_spi.c b/arch/arm/src/kl/kl_spi.c
index abc587caff9..e9fb9947cd4 100644
--- a/arch/arm/src/kl/kl_spi.c
+++ b/arch/arm/src/kl/kl_spi.c
@@ -341,7 +341,7 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency)
   priv->frequency = frequency;
   priv->actual    = actual;
 
-  spierr("Frequency %d->%d\n", frequency, actual);
+  spiinfo("Frequency %d->%d\n", frequency, actual);
   return actual;
 }
 
diff --git a/arch/arm/src/lpc11xx/lpc11_i2c.c b/arch/arm/src/lpc11xx/lpc11_i2c.c
index 46011f75082..184290a602f 100644
--- a/arch/arm/src/lpc11xx/lpc11_i2c.c
+++ b/arch/arm/src/lpc11xx/lpc11_i2c.c
@@ -485,7 +485,7 @@ struct i2c_master_s *lpc11_i2cbus_initialize(int port)
 
   if (port > 1)
     {
-      _err("lpc I2C Only support 0,1\n");
+      i2cerr("ERROR: LPC I2C only supports ports 0 and 1\n");
       return NULL;
     }
 
diff --git a/arch/arm/src/lpc11xx/lpc11_irq.c b/arch/arm/src/lpc11xx/lpc11_irq.c
index d907b7d4aec..f861943bc0a 100644
--- a/arch/arm/src/lpc11xx/lpc11_irq.c
+++ b/arch/arm/src/lpc11xx/lpc11_irq.c
@@ -124,7 +124,7 @@ static void lpc11_dumpnvic(const char *msg, int irq)
 
 /****************************************************************************
  * Name: lpc11_nmi, lpc11_busfault, lpc11_usagefault, lpc11_pendsv,
- *       lpc11_errmonitor, lpc11_pendsv, lpc11_reserved
+ *       lpc11_dbgmonitor, lpc11_pendsv, lpc11_reserved
  *
  * Description:
  *   Handlers for various execptions.  None are handled and all are fatal
diff --git a/arch/arm/src/lpc11xx/lpc11_serial.c b/arch/arm/src/lpc11xx/lpc11_serial.c
index b9365615dac..55c05ac5172 100644
--- a/arch/arm/src/lpc11xx/lpc11_serial.c
+++ b/arch/arm/src/lpc11xx/lpc11_serial.c
@@ -638,7 +638,7 @@ static int up_interrupt(int irq, void *context)
 
           default:
             {
-              _err("Unexpected IIR: %02x\n", status);
+              _err("ERROR: Unexpected IIR: %02x\n", status);
               break;
             }
         }
diff --git a/arch/arm/src/lpc11xx/lpc11_spi.c b/arch/arm/src/lpc11xx/lpc11_spi.c
index db01c47acec..c3f9157fe52 100644
--- a/arch/arm/src/lpc11xx/lpc11_spi.c
+++ b/arch/arm/src/lpc11xx/lpc11_spi.c
@@ -272,7 +272,7 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev,
   priv->frequency = frequency;
   priv->actual    = actual;
 
-  spierr("Frequency %d->%d\n", frequency, actual);
+  spiinfo("Frequency %d->%d\n", frequency, actual);
   return actual;
 }
 
@@ -436,7 +436,7 @@ static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer,
   FAR uint8_t *ptr = (FAR uint8_t *)buffer;
   uint8_t data;
 
-  spierr("nwords: %d\n", nwords);
+  spiinfo("nwords: %d\n", nwords);
   while (nwords)
     {
       /* Write the data to transmitted to the SPI Data Register */
@@ -483,7 +483,7 @@ static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer,
 {
   FAR uint8_t *ptr = (FAR uint8_t *)buffer;
 
-  spierr("nwords: %d\n", nwords);
+  spiinfo("nwords: %d\n", nwords);
   while (nwords)
     {
       /* Write some dummy data to the SPI Data Register in order to clock the
diff --git a/arch/arm/src/lpc17xx/Kconfig b/arch/arm/src/lpc17xx/Kconfig
index 7aea897ba08..abfd205fedc 100644
--- a/arch/arm/src/lpc17xx/Kconfig
+++ b/arch/arm/src/lpc17xx/Kconfig
@@ -704,12 +704,12 @@ config NET_WOL
 	---help---
 		Enable Wake-up on Lan (not fully implemented).
 
-config NET_REGDEBUG
+config LPC17_NET_REGDEBUG
 	bool "Ethernet register-level debug"
-	depends on DEBUG_FEATURES
+	depends on DEBUG_NET_INFO
 	default n
 	---help---
-		Enable low level register debug.  Also needs CONFIG_DEBUG_FEATURES.
+		Enable low level register debug.  Also needs CONFIG_DEBUG_NET_INFO.
 
 config NET_HASH
 	bool "Hashing"
@@ -901,11 +901,11 @@ config LPC17_USBDEV_NOLED
 
 config LPC17_USBDEV_REGDEBUG
 	bool "Register level debug"
-	depends on DEBUG_FEATURES
+	depends on DEBUG_USB_INFO
 	default n
 	---help---
 		Output detailed register-level USB device debug information.  Requires
-		also CONFIG_DEBUG_FEATURES.
+		also CONFIG_DEBUG_USB_INFO.
 
 endmenu
 
@@ -978,10 +978,10 @@ config USBHOST_ISOC_DISABLE
 
 config LPC17_USBHOST_REGDEBUG
 	bool "Register level debug"
-	depends on DEBUG_FEATURES
+	depends on DEBUG_USB_INFO
 	default n
 	---help---
 		Output detailed register-level USB host debug information.  Requires
-		also CONFIG_DEBUG_FEATURES.
+		also CONFIG_DEBUG_USB_INFO.
 
 endmenu
diff --git a/arch/arm/src/lpc17xx/lpc17_can.c b/arch/arm/src/lpc17xx/lpc17_can.c
index 802fe89ae96..f25de325b9f 100644
--- a/arch/arm/src/lpc17xx/lpc17_can.c
+++ b/arch/arm/src/lpc17xx/lpc17_can.c
@@ -308,7 +308,7 @@ static void can_printreg(uint32_t addr, uint32_t value)
         {
           if (count == 4)
             {
-              _llerr("...\n");
+              caninfo("...\n");
             }
 
           return;
@@ -325,7 +325,7 @@ static void can_printreg(uint32_t addr, uint32_t value)
         {
           /* Yes.. then show how many times the value repeated */
 
-          _llerr("[repeats %d more times]\n", count-3);
+          caninfo("[repeats %d more times]\n", count-3);
         }
 
       /* Save the new address, value, and count */
@@ -337,7 +337,7 @@ static void can_printreg(uint32_t addr, uint32_t value)
 
   /* Show the register value read */
 
-  _llerr("%08x->%08x\n", addr, value);
+  caninfo("%08x->%08x\n", addr, value);
 }
 #endif
 
@@ -398,7 +398,7 @@ static void can_putreg(struct up_dev_s *priv, int offset, uint32_t value)
 
   /* Show the register value being written */
 
-  _llerr("%08x<-%08x\n", addr, value);
+  caninfo("%08x<-%08x\n", addr, value);
 
   /* Write the value */
 
@@ -458,7 +458,7 @@ static void can_putcommon(uint32_t addr, uint32_t value)
 {
   /* Show the register value being written */
 
-  _llerr("%08x<-%08x\n", addr, value);
+  caninfo("%08x<-%08x\n", addr, value);
 
   /* Write the value */
 
@@ -681,7 +681,7 @@ static void can_txint(FAR struct can_dev_s *dev, bool enable)
 
 static int can_ioctl(FAR struct can_dev_s *dev, int cmd, unsigned long arg)
 {
-  _err("Fix me:Not Implemented\n");
+  canerr("ERROR: Fix me -- Not Implemented\n");
   return 0;
 }
 
@@ -701,7 +701,7 @@ static int can_ioctl(FAR struct can_dev_s *dev, int cmd, unsigned long arg)
 
 static int can_remoterequest(FAR struct can_dev_s *dev, uint16_t id)
 {
-  _err("Fix me:Not Implemented\n");
+  canerr("ERROR: Fix me -- Not Implemented\n");
   return 0;
 }
 
@@ -862,7 +862,7 @@ static int can_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg)
     }
   else
     {
-      canerr("No available transmission buffer, SR: %08x\n", regval);
+      canerr("ERROR: No available transmission buffer, SR: %08x\n", regval);
       ret = -EBUSY;
     }
 
@@ -942,7 +942,7 @@ static void can_interrupt(FAR struct can_dev_s *dev)
   /* Read the interrupt and capture register (also clearing most status bits) */
 
   regval = can_getreg(priv, LPC17_CAN_ICR_OFFSET);
-  canllinfo("CAN%d ICR: %08x\n",  priv->port, regval);
+  caninfo("CAN%d ICR: %08x\n",  priv->port, regval);
 
   /* Check for a receive interrupt */
 
@@ -972,7 +972,7 @@ static void can_interrupt(FAR struct can_dev_s *dev)
 
       if ((rfs & CAN_RFS_FF) != 0)
         {
-          canllerr("ERROR: Received message with extended identifier.  Dropped\n");
+          canerr("ERROR: Received message with extended identifier.  Dropped\n");
         }
       else
 #endif
@@ -1049,7 +1049,7 @@ static int can12_interrupt(int irq, void *context)
 {
   /* Handle CAN1/2 interrupts */
 
-  canllinfo("irq: %d\n",  irq);
+  caninfo("irq: %d\n",  irq);
 
 #ifdef CONFIG_LPC17_CAN1
   can_interrupt(&g_can1dev);
@@ -1126,8 +1126,8 @@ static int can_bittiming(struct up_dev_s *priv)
   uint32_t ts2;
   uint32_t sjw;
 
-  canllinfo("CAN%d PCLK: %d baud: %d\n", priv->port,
-            CAN_CLOCK_FREQUENCY(priv->divisor), priv->baud);
+  caninfo("CAN%d PCLK: %d baud: %d\n", priv->port,
+          CAN_CLOCK_FREQUENCY(priv->divisor), priv->baud);
 
   /* Try to get CAN_BIT_QUANTA quanta in one bit_time.
    *
@@ -1179,7 +1179,7 @@ static int can_bittiming(struct up_dev_s *priv)
 
   sjw = 1;
 
-  canllinfo("TS1: %d TS2: %d BRP: %d SJW= %d\n", ts1, ts2, brp, sjw);
+  caninfo("TS1: %d TS2: %d BRP: %d SJW= %d\n", ts1, ts2, brp, sjw);
 
   /* Configure bit timing */
 
@@ -1196,7 +1196,7 @@ static int can_bittiming(struct up_dev_s *priv)
   btr |= CAN_BTR_SAM;
 #endif
 
-  canllinfo("Setting CANxBTR= 0x%08x\n", btr);
+  caninfo("Setting CANxBTR= 0x%08x\n", btr);
   can_putreg(priv, LPC17_CAN_BTR_OFFSET, btr);        /* Set bit timing */
   return OK;
 }
@@ -1224,7 +1224,7 @@ FAR struct can_dev_s *lpc17_caninitialize(int port)
   irqstate_t flags;
   uint32_t regval;
 
-  canllinfo("CAN%d\n",  port);
+  caninfo("CAN%d\n",  port);
 
   flags = enter_critical_section();
 
@@ -1283,7 +1283,7 @@ FAR struct can_dev_s *lpc17_caninitialize(int port)
   else
 #endif
     {
-      canerr("Unsupported port: %d\n", port);
+      canerr("ERROR: Unsupported port: %d\n", port);
       leave_critical_section(flags);
       return NULL;
     }
diff --git a/arch/arm/src/lpc17xx/lpc17_dac.c b/arch/arm/src/lpc17xx/lpc17_dac.c
index d936aa0fc57..003d6092664 100644
--- a/arch/arm/src/lpc17xx/lpc17_dac.c
+++ b/arch/arm/src/lpc17xx/lpc17_dac.c
@@ -170,9 +170,9 @@ static int  dac_send(FAR struct dac_dev_s *dev, FAR struct dac_msg_s *msg)
 
 /* All ioctl calls will be routed through this method */
 
-static int  dac_ioctl(FAR struct dac_dev_s *dev, int cmd, unsigned long arg)
+static int dac_ioctl(FAR struct dac_dev_s *dev, int cmd, unsigned long arg)
 {
-  _err("Fix me:Not Implemented\n");
+  aerr("ERROR: Fix me -- Not Implemented\n");
   return 0;
 }
 
diff --git a/arch/arm/src/lpc17xx/lpc17_ethernet.c b/arch/arm/src/lpc17xx/lpc17_ethernet.c
index a7a28a26162..13730506821 100644
--- a/arch/arm/src/lpc17xx/lpc17_ethernet.c
+++ b/arch/arm/src/lpc17xx/lpc17_ethernet.c
@@ -127,17 +127,17 @@
 #endif
 
 /* Debug Configuration *****************************************************/
-/* Register debug -- can only happen of CONFIG_DEBUG_FEATURES is selected */
+/* Register debug -- can only happen of CONFIG_DEBUG_NET_INFO is selected */
 
-#ifndef CONFIG_DEBUG_FEATURES
-#  undef  CONFIG_NET_REGDEBUG
+#ifndef CONFIG_DEBUG_NET_INFO
+#  undef  CONFIG_LPC17_NET_REGDEBUG
 #endif
 
 /* CONFIG_NET_DUMPPACKET will dump the contents of each packet to the
  * console.
  */
 
-#ifndef CONFIG_DEBUG_FEATURES
+#ifndef CONFIG_DEBUG_NET_INFO
 #  undef  CONFIG_NET_DUMPPACKET
 #endif
 
@@ -301,7 +301,7 @@ static const uint16_t g_enetpins[GPIO_NENET_PINS] =
 
 /* Register operations */
 
-#ifdef CONFIG_NET_REGDEBUG
+#ifdef CONFIG_LPC17_NET_REGDEBUG
 static void lpc17_printreg(uint32_t addr, uint32_t val, bool iswrite);
 static void lpc17_checkreg(uint32_t addr, uint32_t val, bool iswrite);
 static uint32_t lpc17_getreg(uint32_t addr);
@@ -365,7 +365,7 @@ static int lpc17_rmmac(struct net_driver_s *dev, const uint8_t *mac);
 
 /* Initialization functions */
 
-#if defined(CONFIG_NET_REGDEBUG) && defined(CONFIG_DEBUG_GPIO_INFO)
+#if defined(CONFIG_LPC17_NET_REGDEBUG) && defined(CONFIG_DEBUG_GPIO_INFO)
 static void lpc17_showpins(void);
 #else
 #  define lpc17_showpins()
@@ -374,7 +374,7 @@ static void lpc17_showpins(void);
 /* PHY initialization functions */
 
 #ifdef LPC17_HAVE_PHY
-#  ifdef CONFIG_NET_REGDEBUG
+#  ifdef CONFIG_LPC17_NET_REGDEBUG
 static void lpc17_showmii(uint8_t phyaddr, const char *msg);
 #  else
 #    define lpc17_showmii(phyaddr,msg)
@@ -412,10 +412,10 @@ static void lpc17_ethreset(struct lpc17_driver_s *priv);
  *
  ****************************************************************************/
 
-#ifdef CONFIG_NET_REGDEBUG
+#ifdef CONFIG_LPC17_NET_REGDEBUG
 static void lpc17_printreg(uint32_t addr, uint32_t val, bool iswrite)
 {
-  _err("%08x%s%08x\n", addr, iswrite ? "<-" : "->", val);
+  ninfo("%08x%s%08x\n", addr, iswrite ? "<-" : "->", val);
 }
 #endif
 
@@ -427,7 +427,7 @@ static void lpc17_printreg(uint32_t addr, uint32_t val, bool iswrite)
  *
  ****************************************************************************/
 
-#ifdef CONFIG_NET_REGDEBUG
+#ifdef CONFIG_LPC17_NET_REGDEBUG
 static void lpc17_checkreg(uint32_t addr, uint32_t val, bool iswrite)
 {
   static uint32_t prevaddr = 0;
@@ -465,7 +465,7 @@ static void lpc17_checkreg(uint32_t addr, uint32_t val, bool iswrite)
             {
               /* No.. More than one. */
 
-              _err("[repeats %d more times]\n", count);
+              ninfo("[repeats %d more times]\n", count);
             }
         }
 
@@ -491,7 +491,7 @@ static void lpc17_checkreg(uint32_t addr, uint32_t val, bool iswrite)
  *
  ****************************************************************************/
 
-#ifdef CONFIG_NET_REGDEBUG
+#ifdef CONFIG_LPC17_NET_REGDEBUG
 static uint32_t lpc17_getreg(uint32_t addr)
 {
   /* Read the value from the register */
@@ -513,7 +513,7 @@ static uint32_t lpc17_getreg(uint32_t addr)
  *
  ****************************************************************************/
 
-#ifdef CONFIG_NET_REGDEBUG
+#ifdef CONFIG_LPC17_NET_REGDEBUG
 static void lpc17_putreg(uint32_t val, uint32_t addr)
 {
   /* Check if we need to print this value */
@@ -837,8 +837,8 @@ static void lpc17_rxdone_process(struct lpc17_driver_s *priv)
 
       if ((*rxstat & RXSTAT_INFO_ERROR) != 0)
         {
-          nllerr("Error. considx: %08x prodidx: %08x rxstat: %08x\n",
-                 considx, prodidx, *rxstat);
+          nerr("ERROR: considx: %08x prodidx: %08x rxstat: %08x\n",
+               considx, prodidx, *rxstat);
           NETDEV_RXERRORS(&priv->lp_dev);
         }
 
@@ -850,21 +850,21 @@ static void lpc17_rxdone_process(struct lpc17_driver_s *priv)
 
       /* else */ if (pktlen > CONFIG_NET_ETH_MTU + CONFIG_NET_GUARDSIZE)
         {
-          nllerr("Too big. considx: %08x prodidx: %08x pktlen: %d rxstat: %08x\n",
-                 considx, prodidx, pktlen, *rxstat);
+          nwarn("WARNING: Too big. considx: %08x prodidx: %08x pktlen: %d rxstat: %08x\n",
+                considx, prodidx, pktlen, *rxstat);
           NETDEV_RXERRORS(&priv->lp_dev);
         }
       else if ((*rxstat & RXSTAT_INFO_LASTFLAG) == 0)
         {
-          nllerr("Fragment. considx: %08x prodidx: %08x pktlen: %d rxstat: %08x\n",
-                 considx, prodidx, pktlen, *rxstat);
+          ninfo("Fragment. considx: %08x prodidx: %08x pktlen: %d rxstat: %08x\n",
+                considx, prodidx, pktlen, *rxstat);
           NETDEV_RXFRAGMENTS(&priv->lp_dev);
           fragment = true;
         }
       else if (fragment)
         {
-          nllerr("Last fragment. considx: %08x prodidx: %08x pktlen: %d rxstat: %08x\n",
-                 considx, prodidx, pktlen, *rxstat);
+          ninfo("Last fragment. considx: %08x prodidx: %08x pktlen: %d rxstat: %08x\n",
+                considx, prodidx, pktlen, *rxstat);
           NETDEV_RXFRAGMENTS(&priv->lp_dev);
           fragment = false;
         }
@@ -906,7 +906,7 @@ static void lpc17_rxdone_process(struct lpc17_driver_s *priv)
 #ifdef CONFIG_NET_IPv4
           if (BUF->type == HTONS(ETHTYPE_IP))
             {
-              nllinfo("IPv4 frame\n");
+              ninfo("IPv4 frame\n");
               NETDEV_RXIPV4(&priv->lp_dev);
 
               /* Handle ARP on input then give the IPv4 packet to the
@@ -948,7 +948,7 @@ static void lpc17_rxdone_process(struct lpc17_driver_s *priv)
 #ifdef CONFIG_NET_IPv6
           if (BUF->type == HTONS(ETHTYPE_IP6))
             {
-              nllinfo("Iv6 frame\n");
+              ninfo("Iv6 frame\n");
               NETDEV_RXIPV6(&priv->lp_dev);
 
               /* Give the IPv6 packet to the network layer */
@@ -1202,13 +1202,13 @@ static int lpc17_interrupt(int irq, void *context)
         {
           if ((status & ETH_INT_RXOVR) != 0)
             {
-              nllerr("RX Overrun. status: %08x\n", status);
+              nerr("ERROR: RX Overrun. status: %08x\n", status);
               NETDEV_RXERRORS(&priv->lp_dev);
             }
 
           if ((status & ETH_INT_TXUNR) != 0)
             {
-              nllerr("TX Underrun. status: %08x\n", status);
+              nerr("ERROR: TX Underrun. status: %08x\n", status);
               NETDEV_TXERRORS(&priv->lp_dev);
             }
 
@@ -1229,7 +1229,7 @@ static int lpc17_interrupt(int irq, void *context)
 
           if ((status & ETH_INT_RXERR) != 0)
             {
-              nllerr("RX Error. status: %08x\n", status);
+              nerr("ERROR: RX ERROR: status: %08x\n", status);
               NETDEV_RXERRORS(&priv->lp_dev);
             }
 
@@ -1281,7 +1281,7 @@ static int lpc17_interrupt(int irq, void *context)
 
           if ((status & ETH_INT_TXERR) != 0)
             {
-              nllerr("TX Error. status: %08x\n", status);
+              nerr("ERROR: TX ERROR: status: %08x\n", status);
               NETDEV_TXERRORS(&priv->lp_dev);
             }
 
@@ -1720,9 +1720,9 @@ static int lpc17_ifup(struct net_driver_s *dev)
   uint32_t regval;
   int ret;
 
-  nerr("Bringing up: %d.%d.%d.%d\n",
-       dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff,
-       (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24);
+  ninfo("Bringing up: %d.%d.%d.%d\n",
+        dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff,
+        (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24);
 
   /* Reset the Ethernet controller (again) */
 
@@ -1733,7 +1733,7 @@ static int lpc17_ifup(struct net_driver_s *dev)
   ret = lpc17_phyinit(priv);
   if (ret != 0)
     {
-      nerr("lpc17_phyinit failed: %d\n", ret);
+      nerr("ERROR: lpc17_phyinit failed: %d\n", ret);
       return ret;
     }
 
@@ -2145,8 +2145,8 @@ static int lpc17_addmac(struct net_driver_s *dev, const uint8_t *mac)
   uint32_t crc;
   unsigned int ndx;
 
-  nllinfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
-          mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+  ninfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
+        mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
 
   /* Hash function:
    *
@@ -2221,8 +2221,8 @@ static int lpc17_rmmac(struct net_driver_s *dev, const uint8_t *mac)
   uint32_t crc;
   unsigned int ndx;
 
-  nllinfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
-          mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+  ninfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
+        mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
 
   /* Hash function:
    *
@@ -2292,7 +2292,7 @@ static int lpc17_rmmac(struct net_driver_s *dev, const uint8_t *mac)
  *
  ****************************************************************************/
 
-#if defined(CONFIG_NET_REGDEBUG) && defined(CONFIG_DEBUG_GPIO_INFO)
+#if defined(CONFIG_LPC17_NET_REGDEBUG) && defined(CONFIG_DEBUG_GPIO_INFO)
 static void lpc17_showpins(void)
 {
   lpc17_dumpgpio(GPIO_PORT1 | GPIO_PIN0, "P1[1-15]");
@@ -2316,17 +2316,17 @@ static void lpc17_showpins(void)
  *
  ****************************************************************************/
 
-#if defined(CONFIG_NET_REGDEBUG) && defined(LPC17_HAVE_PHY)
+#if defined(CONFIG_LPC17_NET_REGDEBUG) && defined(LPC17_HAVE_PHY)
 static void lpc17_showmii(uint8_t phyaddr, const char *msg)
 {
-  _err("PHY " LPC17_PHYNAME ": %s\n", msg);
-  _err("  MCR:       %04x\n", lpc17_phyread(phyaddr, MII_MCR));
-  _err("  MSR:       %04x\n", lpc17_phyread(phyaddr, MII_MSR));
-  _err("  ADVERTISE: %04x\n", lpc17_phyread(phyaddr, MII_ADVERTISE));
-  _err("  LPA:       %04x\n", lpc17_phyread(phyaddr, MII_LPA));
-  _err("  EXPANSION: %04x\n", lpc17_phyread(phyaddr, MII_EXPANSION));
+  ninfo("PHY " LPC17_PHYNAME ": %s\n", msg);
+  ninfo("  MCR:       %04x\n", lpc17_phyread(phyaddr, MII_MCR));
+  ninfo("  MSR:       %04x\n", lpc17_phyread(phyaddr, MII_MSR));
+  ninfo("  ADVERTISE: %04x\n", lpc17_phyread(phyaddr, MII_ADVERTISE));
+  ninfo("  LPA:       %04x\n", lpc17_phyread(phyaddr, MII_LPA));
+  ninfo("  EXPANSION: %04x\n", lpc17_phyread(phyaddr, MII_EXPANSION));
 #ifdef CONFIG_ETH0_PHY_KS8721
-  _err("  10BTCR:    %04x\n", lpc17_phyread(phyaddr, MII_KS8721_10BTCR));
+  ninfo("  10BTCR:    %04x\n", lpc17_phyread(phyaddr, MII_KS8721_10BTCR));
 #endif
 }
 #endif
@@ -2462,7 +2462,7 @@ static inline int lpc17_phyreset(uint8_t phyaddr)
         }
     }
 
-  nerr("Reset failed. MCR: %04x\n", phyreg);
+  nerr("ERROR: Reset failed. MCR: %04x\n", phyreg);
   return -ETIMEDOUT;
 }
 #endif
@@ -2509,7 +2509,7 @@ static inline int lpc17_phyautoneg(uint8_t phyaddr)
         }
     }
 
-  nerr("Auto-negotiation failed. MSR: %04x\n", phyreg);
+  nerr("ERROR: Auto-negotiation failed. MSR: %04x\n", phyreg);
   return -ETIMEDOUT;
 }
 #endif
@@ -2593,7 +2593,7 @@ static int lpc17_phymode(uint8_t phyaddr, uint8_t mode)
 #endif
     }
 
-  nerr("Link failed. MSR: %04x\n", phyreg);
+  nerr("ERROR: Link failed. MSR: %04x\n", phyreg);
   return -ETIMEDOUT;
 }
 #endif
@@ -2660,7 +2660,7 @@ static inline int lpc17_phyinit(struct lpc17_driver_s *priv)
            * 4-bit revision number).
            */
 
-          if ((phyreg & 0xfff0) == LPC17_PHYID2)
+          if ((phyreg & 0xfff0) == (LPC17_PHYID2 & 0xfff0))
             {
               break;
             }
@@ -2673,7 +2673,7 @@ static inline int lpc17_phyinit(struct lpc17_driver_s *priv)
     {
       /* Failed to find PHY at any location */
 
-      nerr("No PHY detected\n");
+      nerr("ERROR: No PHY detected\n");
       return -ENODEV;
     }
   ninfo("phyaddr: %d\n", phyaddr);
@@ -2760,7 +2760,7 @@ static inline int lpc17_phyinit(struct lpc17_driver_s *priv)
         break;
 
       default:
-        nerr("Unrecognized mode: %04x\n", phyreg);
+        nerr("ERROR: Unrecognized mode: %04x\n", phyreg);
         return -ENODEV;
     }
 
@@ -2788,7 +2788,7 @@ static inline int lpc17_phyinit(struct lpc17_driver_s *priv)
         break;
 
       default:
-        nerr("Unrecognized mode: %04x\n", phyreg);
+        nerr("ERROR: Unrecognized mode: %04x\n", phyreg);
         return -ENODEV;
     }
 
@@ -2816,7 +2816,7 @@ static inline int lpc17_phyinit(struct lpc17_driver_s *priv)
         break;
 
       default:
-        nerr("Unrecognized mode: %04x\n", phyreg);
+        nerr("ERROR: Unrecognized mode: %04x\n", phyreg);
         return -ENODEV;
     }
 
@@ -2862,7 +2862,7 @@ static inline int lpc17_phyinit(struct lpc17_driver_s *priv)
       }
     else
       {
-        nerr("Unrecognized mode: %04x\n", phyreg);
+        nerr("ERROR: Unrecognized mode: %04x\n", phyreg);
         return -ENODEV;
       }
   }
@@ -2871,9 +2871,9 @@ static inline int lpc17_phyinit(struct lpc17_driver_s *priv)
 #  warning "PHY Unknown: speed and duplex are bogus"
 #endif
 
-  nerr("%dBase-T %s duplex\n",
-       (priv->lp_mode & LPC17_SPEED_MASK) ==  LPC17_SPEED_100 ? 100 : 10,
-       (priv->lp_mode & LPC17_DUPLEX_MASK) == LPC17_DUPLEX_FULL ?"full" : "half");
+  ninfo("%dBase-T %s duplex\n",
+        (priv->lp_mode & LPC17_SPEED_MASK) ==  LPC17_SPEED_100 ? 100 : 10,
+        (priv->lp_mode & LPC17_DUPLEX_MASK) == LPC17_DUPLEX_FULL ?"full" : "half");
 
   /* Disable auto-configuration.  Set the fixed speed/duplex mode.
    * (probably more than little redundant).
diff --git a/arch/arm/src/lpc17xx/lpc17_gpdma.c b/arch/arm/src/lpc17xx/lpc17_gpdma.c
index 7b692c2535a..2eb2edf16ab 100644
--- a/arch/arm/src/lpc17xx/lpc17_gpdma.c
+++ b/arch/arm/src/lpc17xx/lpc17_gpdma.c
@@ -654,7 +654,7 @@ void lpc17_dmastop(DMA_HANDLE handle)
  *
  ****************************************************************************/
 
-#ifdef CONFIG_DEBUG_DMA
+#ifdef CONFIG__DEBUG_DMA_INFO
 void lpc17_dmasample(DMA_HANDLE handle, struct lpc17_dmaregs_s *regs)
 {
   struct lpc17_dmach_s *dmach = (DMA_HANDLE)handle;
@@ -686,7 +686,7 @@ void lpc17_dmasample(DMA_HANDLE handle, struct lpc17_dmaregs_s *regs)
   regs->ch.control      = getreg32(base + LPC17_DMACH_CONTROL_OFFSET);
   regs->ch.config       = getreg32(base + LPC17_DMACH_CONFIG_OFFSET);
 }
-#endif /* CONFIG_DEBUG_DMA */
+#endif /* CONFIG__DEBUG_DMA_INFO */
 
 /****************************************************************************
  * Name: lpc17_dmadump
@@ -696,7 +696,7 @@ void lpc17_dmasample(DMA_HANDLE handle, struct lpc17_dmaregs_s *regs)
  *
  ****************************************************************************/
 
-#ifdef CONFIG_DEBUG_DMA
+#ifdef CONFIG__DEBUG_DMA_INFO
 void lpc17_dmadump(DMA_HANDLE handle, const struct lpc17_dmaregs_s *regs,
                    const char *msg)
 {
@@ -707,49 +707,49 @@ void lpc17_dmadump(DMA_HANDLE handle, const struct lpc17_dmaregs_s *regs,
 
   /* Dump the sampled global DMA registers */
 
-  dmaerr("Global GPDMA Registers: %s\n", msg);
-  dmaerr("       INTST[%08x]: %08x\n",
-         LPC17_DMA_INTST, regs->gbl.intst);
-  dmaerr("     INTTCST[%08x]: %08x\n",
-         LPC17_DMA_INTTCST, regs->gbl.inttcst);
-  dmaerr("    INTERRST[%08x]: %08x\n",
-         LPC17_DMA_INTERRST, regs->gbl.interrst);
-  dmaerr("  RAWINTTCST[%08x]: %08x\n",
-         LPC17_DMA_RAWINTTCST, regs->gbl.rawinttcst);
-  dmaerr(" RAWINTERRST[%08x]: %08x\n",
-         LPC17_DMA_RAWINTERRST, regs->gbl.rawinterrst);
-  dmaerr("   ENBLDCHNS[%08x]: %08x\n",
-         LPC17_DMA_ENBLDCHNS, regs->gbl.enbldchns);
-  dmaerr("    SOFTBREQ[%08x]: %08x\n",
-         LPC17_DMA_SOFTBREQ, regs->gbl.softbreq);
-  dmaerr("    SOFTSREQ[%08x]: %08x\n",
-         LPC17_DMA_SOFTSREQ, regs->gbl.softsreq);
-  dmaerr("   SOFTLBREQ[%08x]: %08x\n",
-         LPC17_DMA_SOFTLBREQ, regs->gbl.softlbreq);
-  dmaerr("   SOFTLSREQ[%08x]: %08x\n",
-         LPC17_DMA_SOFTLSREQ, regs->gbl.softlsreq);
-  dmaerr("      CONFIG[%08x]: %08x\n",
-         LPC17_DMA_CONFIG, regs->gbl.config);
-  dmaerr("        SYNC[%08x]: %08x\n",
-         LPC17_DMA_SYNC, regs->gbl.sync);
+  dmainfo("Global GPDMA Registers: %s\n", msg);
+  dmainfo("       INTST[%08x]: %08x\n",
+          LPC17_DMA_INTST, regs->gbl.intst);
+  dmainfo("     INTTCST[%08x]: %08x\n",
+          LPC17_DMA_INTTCST, regs->gbl.inttcst);
+  dmainfo("    INTERRST[%08x]: %08x\n",
+          LPC17_DMA_INTERRST, regs->gbl.interrst);
+  dmainfo("  RAWINTTCST[%08x]: %08x\n",
+          LPC17_DMA_RAWINTTCST, regs->gbl.rawinttcst);
+  dmainfo(" RAWINTERRST[%08x]: %08x\n",
+          LPC17_DMA_RAWINTERRST, regs->gbl.rawinterrst);
+  dmainfo("   ENBLDCHNS[%08x]: %08x\n",
+          LPC17_DMA_ENBLDCHNS, regs->gbl.enbldchns);
+  dmainfo("    SOFTBREQ[%08x]: %08x\n",
+          LPC17_DMA_SOFTBREQ, regs->gbl.softbreq);
+  dmainfo("    SOFTSREQ[%08x]: %08x\n",
+          LPC17_DMA_SOFTSREQ, regs->gbl.softsreq);
+  dmainfo("   SOFTLBREQ[%08x]: %08x\n",
+          LPC17_DMA_SOFTLBREQ, regs->gbl.softlbreq);
+  dmainfo("   SOFTLSREQ[%08x]: %08x\n",
+          LPC17_DMA_SOFTLSREQ, regs->gbl.softlsreq);
+  dmainfo("      CONFIG[%08x]: %08x\n",
+          LPC17_DMA_CONFIG, regs->gbl.config);
+  dmainfo("        SYNC[%08x]: %08x\n",
+          LPC17_DMA_SYNC, regs->gbl.sync);
 
   /* Dump the DMA channel registers */
 
   base = LPC17_DMACH_BASE((uint32_t)dmach->chn);
 
-  dmaerr("Channel GPDMA Registers: %d\n", dmach->chn);
+  dmainfo("Channel GPDMA Registers: %d\n", dmach->chn);
 
-  dmaerr("     SRCADDR[%08x]: %08x\n",
-         base + LPC17_DMACH_SRCADDR_OFFSET, regs->ch.srcaddr);
-  dmaerr("    DESTADDR[%08x]: %08x\n",
-         base + LPC17_DMACH_DESTADDR_OFFSET, regs->ch.destaddr);
-  dmaerr("         LLI[%08x]: %08x\n",
-         base + LPC17_DMACH_LLI_OFFSET, regs->ch.lli);
-  dmaerr("     CONTROL[%08x]: %08x\n",
-         base + LPC17_DMACH_CONTROL_OFFSET, regs->ch.control);
-  dmaerr("      CONFIG[%08x]: %08x\n",
-         base + LPC17_DMACH_CONFIG_OFFSET, regs->ch.config);
+  dmainfo("     SRCADDR[%08x]: %08x\n",
+          base + LPC17_DMACH_SRCADDR_OFFSET, regs->ch.srcaddr);
+  dmainfo("    DESTADDR[%08x]: %08x\n",
+          base + LPC17_DMACH_DESTADDR_OFFSET, regs->ch.destaddr);
+  dmainfo("         LLI[%08x]: %08x\n",
+          base + LPC17_DMACH_LLI_OFFSET, regs->ch.lli);
+  dmainfo("     CONTROL[%08x]: %08x\n",
+          base + LPC17_DMACH_CONTROL_OFFSET, regs->ch.control);
+  dmainfo("      CONFIG[%08x]: %08x\n",
+          base + LPC17_DMACH_CONFIG_OFFSET, regs->ch.config);
 }
-#endif /* CONFIG_DEBUG_DMA */
+#endif /* CONFIG__DEBUG_DMA_INFO */
 
 #endif /* CONFIG_LPC17_GPDMA */
diff --git a/arch/arm/src/lpc17xx/lpc17_gpdma.h b/arch/arm/src/lpc17xx/lpc17_gpdma.h
index 4e1e499eb1c..a7c0d7009cc 100644
--- a/arch/arm/src/lpc17xx/lpc17_gpdma.h
+++ b/arch/arm/src/lpc17xx/lpc17_gpdma.h
@@ -68,7 +68,7 @@ typedef void (*dma_callback_t)(DMA_HANDLE handle, void *arg, int result);
 
 /* The following is used for sampling DMA registers when CONFIG DEBUG_DMA is selected */
 
-#ifdef CONFIG_DEBUG_DMA
+#ifdef CONFIG__DEBUG_DMA_INFO
 struct lpc17_dmaglobalregs_s
 {
   /* Global Registers */
@@ -109,7 +109,7 @@ struct lpc17_dmaregs_s
   struct lpc17_dmachanregs_s   ch;
 };
 
-#endif /* CONFIG_DEBUG_DMA */
+#endif /* CONFIG__DEBUG_DMA_INFO */
 
 /****************************************************************************
  * Public Data
@@ -239,7 +239,7 @@ void lpc17_dmastop(DMA_HANDLE handle);
  *
  ****************************************************************************/
 
-#ifdef CONFIG_DEBUG_DMA
+#ifdef CONFIG__DEBUG_DMA_INFO
 void lpc17_dmasample(DMA_HANDLE handle, struct lpc17_dmaregs_s *regs);
 #else
 #  define lpc17_dmasample(handle,regs)
@@ -253,7 +253,7 @@ void lpc17_dmasample(DMA_HANDLE handle, struct lpc17_dmaregs_s *regs);
  *
  ****************************************************************************/
 
-#ifdef CONFIG_DEBUG_DMA
+#ifdef CONFIG__DEBUG_DMA_INFO
 void lpc17_dmadump(DMA_HANDLE handle, const struct lpc17_dmaregs_s *regs,
                    const char *msg);
 #else
diff --git a/arch/arm/src/lpc17xx/lpc17_i2c.c b/arch/arm/src/lpc17xx/lpc17_i2c.c
index a4f817be33d..58bb2de8987 100644
--- a/arch/arm/src/lpc17xx/lpc17_i2c.c
+++ b/arch/arm/src/lpc17xx/lpc17_i2c.c
@@ -485,7 +485,7 @@ struct i2c_master_s *lpc17_i2cbus_initialize(int port)
 
   if (port > 1)
     {
-      _err("lpc I2C Only support 0,1\n");
+      i2cerr("ERROR: LPC I2C Only supports ports 0 and 1\n");
       return NULL;
     }
 
diff --git a/arch/arm/src/lpc17xx/lpc17_irq.c b/arch/arm/src/lpc17xx/lpc17_irq.c
index a3ada9cbe8e..44d149c7342 100644
--- a/arch/arm/src/lpc17xx/lpc17_irq.c
+++ b/arch/arm/src/lpc17xx/lpc17_irq.c
@@ -139,7 +139,7 @@ static void lpc17_dumpnvic(const char *msg, int irq)
 
 /****************************************************************************
  * Name: lpc17_nmi, lpc17_busfault, lpc17_usagefault, lpc17_pendsv,
- *       lpc17_errmonitor, lpc17_pendsv, lpc17_reserved
+ *       lpc17_dbgmonitor, lpc17_pendsv, lpc17_reserved
  *
  * Description:
  *   Handlers for various execptions.  None are handled and all are fatal
@@ -181,7 +181,7 @@ static int lpc17_pendsv(int irq, FAR void *context)
   return 0;
 }
 
-static int lpc17_errmonitor(int irq, FAR void *context)
+static int lpc17_dbgmonitor(int irq, FAR void *context)
 {
   (void)up_irq_save();
   _err("PANIC!!! Debug Monitor received\n");
@@ -402,7 +402,7 @@ void up_irqinitialize(void)
   irq_attach(LPC17_IRQ_BUSFAULT, lpc17_busfault);
   irq_attach(LPC17_IRQ_USAGEFAULT, lpc17_usagefault);
   irq_attach(LPC17_IRQ_PENDSV, lpc17_pendsv);
-  irq_attach(LPC17_IRQ_DBGMONITOR, lpc17_errmonitor);
+  irq_attach(LPC17_IRQ_DBGMONITOR, lpc17_dbgmonitor);
   irq_attach(LPC17_IRQ_RESERVED, lpc17_reserved);
 #endif
 
diff --git a/arch/arm/src/lpc17xx/lpc17_lcd.c b/arch/arm/src/lpc17xx/lpc17_lcd.c
index 5abf5d319ed..f8a6c6db6c9 100644
--- a/arch/arm/src/lpc17xx/lpc17_lcd.c
+++ b/arch/arm/src/lpc17xx/lpc17_lcd.c
@@ -202,14 +202,14 @@ struct fb_vtable_s g_fbobject =
 static int lpc17_getvideoinfo(FAR struct fb_vtable_s *vtable,
                               FAR struct fb_videoinfo_s *vinfo)
 {
-  ginfo("vtable=%p vinfo=%p\n", vtable, vinfo);
+  lcdinfo("vtable=%p vinfo=%p\n", vtable, vinfo);
   if (vtable && vinfo)
     {
       memcpy(vinfo, &g_videoinfo, sizeof(struct fb_videoinfo_s));
       return OK;
     }
 
-  gerr("Returning EINVAL\n");
+  lcderr("ERROR: Returning EINVAL\n");
   return -EINVAL;
 }
 
@@ -220,14 +220,14 @@ static int lpc17_getvideoinfo(FAR struct fb_vtable_s *vtable,
 static int lpc17_getplaneinfo(FAR struct fb_vtable_s *vtable, int planeno,
                               FAR struct fb_planeinfo_s *pinfo)
 {
-  ginfo("vtable=%p planeno=%d pinfo=%p\n", vtable, planeno, pinfo);
+  lcdinfo("vtable=%p planeno=%d pinfo=%p\n", vtable, planeno, pinfo);
   if (vtable && planeno == 0 && pinfo)
     {
       memcpy(pinfo, &g_planeinfo, sizeof(struct fb_planeinfo_s));
       return OK;
     }
 
-  gerr("Returning EINVAL\n");
+  lcderr("ERROR: Returning EINVAL\n");
   return -EINVAL;
 }
 
@@ -244,8 +244,8 @@ static int lpc17_getcmap(FAR struct fb_vtable_s *vtable,
   int last;
   int i;
 
-  ginfo("vtable=%p cmap=%p first=%d len=%d\n",
-        vtable, cmap, cmap->first, cmap->len);
+  lcdinfo("vtable=%p cmap=%p first=%d len=%d\n",
+          vtable, cmap, cmap->first, cmap->len);
 
   DEBUGASSERT(vtable && cmap &&
               cmap->first < 256 && (cmap->first + cmap->len) < 256);
@@ -319,8 +319,8 @@ static int lpc17_putcmap(FAR struct fb_vtable_s *vtable,
   int last;
   int i;
 
-  ginfo("vtable=%p cmap=%p first=%d len=%d\n",
-        vtable, cmap, cmap->first, cmap->len);
+  lcdinfo("vtable=%p cmap=%p first=%d len=%d\n",
+          vtable, cmap, cmap->first, cmap->len);
 
   DEBUGASSERT(vtable && cmap);
 
@@ -383,27 +383,27 @@ static int lpc17_putcmap(FAR struct fb_vtable_s *vtable,
 static int lpc17_getcursor(FAR struct fb_vtable_s *vtable,
                         FAR struct fb_cursorattrib_s *attrib)
 {
-  ginfo("vtable=%p attrib=%p\n", vtable, attrib);
+  lcdinfo("vtable=%p attrib=%p\n", vtable, attrib);
   if (vtable && attrib)
     {
 #ifdef CONFIG_FB_HWCURSORIMAGE
       attrib->fmt = LPC17_COLOR_FMT;
 #endif
 
-      ginfo("pos: (x=%d, y=%d)\n", g_cpos.x, g_cpos.y);
+      lcdinfo("pos: (x=%d, y=%d)\n", g_cpos.x, g_cpos.y);
       attrib->pos = g_cpos;
 
 #ifdef CONFIG_FB_HWCURSORSIZE
       attrib->mxsize.h = CONFIG_LPC17_LCD_VHEIGHT;
       attrib->mxsize.w = CONFIG_LPC17_LCD_HWIDTH;
 
-      ginfo("size: (h=%d, w=%d)\n", g_csize.h, g_csize.w);
+      lcdinfo("size: (h=%d, w=%d)\n", g_csize.h, g_csize.w);
       attrib->size = g_csize;
 #endif
       return OK;
     }
 
-  gerr("Returning EINVAL\n");
+  lcderr("ERROR: Returning EINVAL\n");
   return -EINVAL;
 }
 #endif
@@ -416,34 +416,34 @@ static int lpc17_getcursor(FAR struct fb_vtable_s *vtable,
 static int lpc17_setcursor(FAR struct fb_vtable_s *vtable,
                        FAR struct fb_setcursor_s *setttings)
 {
-  ginfo("vtable=%p setttings=%p\n", vtable, setttings);
+  lcdinfo("vtable=%p setttings=%p\n", vtable, setttings);
   if (vtable && setttings)
     {
-      ginfo("flags: %02x\n", settings->flags);
+      lcdinfo("flags: %02x\n", settings->flags);
       if ((flags & FB_CUR_SETPOSITION) != 0)
         {
           g_cpos = settings->pos;
-          ginfo("pos: (h:%d, w:%d)\n", g_cpos.x, g_cpos.y);
+          lcdinfo("pos: (h:%d, w:%d)\n", g_cpos.x, g_cpos.y);
         }
 #ifdef CONFIG_FB_HWCURSORSIZE
       if ((flags & FB_CUR_SETSIZE) != 0)
         {
           g_csize = settings->size;
-          ginfo("size: (h:%d, w:%d)\n", g_csize.h, g_csize.w);
+          lcdinfo("size: (h:%d, w:%d)\n", g_csize.h, g_csize.w);
         }
 #endif
 #ifdef CONFIG_FB_HWCURSORIMAGE
       if ((flags & FB_CUR_SETIMAGE) != 0)
         {
-          ginfo("image: (h:%d, w:%d) @ %p\n",
-                settings->img.height, settings->img.width,
-                settings->img.image);
+          lcdinfo("image: (h:%d, w:%d) @ %p\n",
+                  settings->img.height, settings->img.width,
+                  settings->img.image);
         }
 #endif
       return OK;
     }
 
-  gerr("Returning EINVAL\n");
+  lcderr("ERROR: Returning EINVAL\n");
   return -EINVAL;
 }
 #endif
@@ -473,7 +473,7 @@ int up_fbinitialize(int display)
   uint32_t regval;
   int i;
 
-  ginfo("Entry\n");
+  lcdinfo("Entry\n");
 
   /* Give LCD bus priority */
 
@@ -485,7 +485,7 @@ int up_fbinitialize(int display)
   /* Configure pins */
   /* Video data */
 
-  ginfo("Configuring pins\n");
+  lcdinfo("Configuring pins\n");
 
   lpc17_configgpio(GPIO_LCD_VD0);
   lpc17_configgpio(GPIO_LCD_VD1);
@@ -528,7 +528,7 @@ int up_fbinitialize(int display)
 
   modifyreg32(LPC17_SYSCON_PCONP, 0, SYSCON_PCONP_PCLCD);
 
-  ginfo("Configuring the LCD controller\n");
+  lcdinfo("Configuring the LCD controller\n");
 
   /* Disable the cursor */
 
@@ -686,7 +686,7 @@ int up_fbinitialize(int display)
 #endif
 
   putreg32(0, LPC17_LCD_INTMSK);
-  ginfo("Enabling the display\n");
+  lcdinfo("Enabling the display\n");
 
   for (i = LPC17_LCD_PWREN_DELAY; i; i--);
 
@@ -727,7 +727,7 @@ int up_fbinitialize(int display)
 
 FAR struct fb_vtable_s *up_fbgetvplane(int display, int vplane)
 {
-  ginfo("vplane: %d\n", vplane);
+  lcdinfo("vplane: %d\n", vplane);
   if (vplane == 0)
     {
       return &g_fbobject;
@@ -801,16 +801,16 @@ void lpc17_lcdclear(nxgl_mxpixel_t color)
 #if LPC17_BPP > 16
   uint32_t *dest = (uint32_t *)CONFIG_LPC17_LCD_VRAMBASE;
 
-  ginfo("Clearing display: color=%08x VRAM=%08x size=%d\n",
-        color, CONFIG_LPC17_LCD_VRAMBASE,
-        CONFIG_LPC17_LCD_HWIDTH * CONFIG_LPC17_LCD_VHEIGHT * sizeof(uint32_t));
+  lcdinfo("Clearing display: color=%08x VRAM=%08x size=%d\n",
+          color, CONFIG_LPC17_LCD_VRAMBASE,
+          CONFIG_LPC17_LCD_HWIDTH * CONFIG_LPC17_LCD_VHEIGHT * sizeof(uint32_t));
 
 #else
   uint16_t *dest = (uint16_t *)CONFIG_LPC17_LCD_VRAMBASE;
 
-  ginfo("Clearing display: color=%08x VRAM=%08x size=%d\n",
-        color, CONFIG_LPC17_LCD_VRAMBASE,
-        CONFIG_LPC17_LCD_HWIDTH * CONFIG_LPC17_LCD_VHEIGHT * sizeof(uint16_t));
+  lcdinfo("Clearing display: color=%08x VRAM=%08x size=%d\n",
+          color, CONFIG_LPC17_LCD_VRAMBASE,
+          CONFIG_LPC17_LCD_HWIDTH * CONFIG_LPC17_LCD_VHEIGHT * sizeof(uint16_t));
 #endif
 
   for (i = 0; i < (CONFIG_LPC17_LCD_HWIDTH * CONFIG_LPC17_LCD_VHEIGHT); i++)
diff --git a/arch/arm/src/lpc17xx/lpc17_mcpwm.c b/arch/arm/src/lpc17xx/lpc17_mcpwm.c
index d7d70daeaa9..be526964c4a 100644
--- a/arch/arm/src/lpc17xx/lpc17_mcpwm.c
+++ b/arch/arm/src/lpc17xx/lpc17_mcpwm.c
@@ -655,7 +655,7 @@ FAR struct pwm_lowerhalf_s *lpc17_mcpwminitialize(int timer)
 #endif
 
       default:
-        pwmerr("No such timer configured\n");
+        pwmerr("ERROR: No such timer configured\n");
         return NULL;
     }
 
diff --git a/arch/arm/src/lpc17xx/lpc17_pwm.c b/arch/arm/src/lpc17xx/lpc17_pwm.c
index 5bcbeab20b2..dc073fc1a73 100644
--- a/arch/arm/src/lpc17xx/lpc17_pwm.c
+++ b/arch/arm/src/lpc17xx/lpc17_pwm.c
@@ -626,7 +626,7 @@ FAR struct pwm_lowerhalf_s *lpc17_pwminitialize(int timer)
 #endif
 
       default:
-        pwmerr("No such timer configured\n");
+        pwmerr("ERROR: No such timer configured\n");
         return NULL;
     }
 
diff --git a/arch/arm/src/lpc17xx/lpc17_sdcard.c b/arch/arm/src/lpc17xx/lpc17_sdcard.c
index 6fb077c10b7..2ea6c17c45c 100644
--- a/arch/arm/src/lpc17xx/lpc17_sdcard.c
+++ b/arch/arm/src/lpc17xx/lpc17_sdcard.c
@@ -810,7 +810,7 @@ static void lpc17_dmacallback(DMA_HANDLE handle, void *arg, int status)
 
   if (status < 0)
     {
-      fllerr("DMA error %d, remaining: %d\n", status, priv->remaining);
+      dmaerr("ERROR: DMA error %d, remaining: %d\n", status, priv->remaining);
       result = SDIOWAIT_ERROR;
     }
   else
@@ -1077,7 +1077,7 @@ static void lpc17_eventtimeout(int argc, uint32_t arg)
       /* Yes.. wake up any waiting threads */
 
       lpc17_endwait(priv, SDIOWAIT_TIMEOUT);
-      fllerr("Timeout: remaining: %d\n", priv->remaining);
+      mcerr("ERROR: Timeout: remaining: %d\n", priv->remaining);
     }
 }
 
@@ -1294,7 +1294,7 @@ static int lpc17_interrupt(int irq, void *context)
             {
               /* Terminate the transfer with an error */
 
-              fllerr("ERROR: Data block CRC failure, remaining: %d\n", priv->remaining);
+              mcerr("ERROR: Data block CRC failure, remaining: %d\n", priv->remaining);
               lpc17_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR);
             }
 
@@ -1304,7 +1304,7 @@ static int lpc17_interrupt(int irq, void *context)
             {
               /* Terminate the transfer with an error */
 
-              fllerr("ERROR: Data timeout, remaining: %d\n", priv->remaining);
+              mcerr("ERROR: Data timeout, remaining: %d\n", priv->remaining);
               lpc17_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_TIMEOUT);
             }
 
@@ -1314,7 +1314,7 @@ static int lpc17_interrupt(int irq, void *context)
             {
               /* Terminate the transfer with an error */
 
-              fllerr("ERROR: RX FIFO overrun, remaining: %d\n", priv->remaining);
+              mcerr("ERROR: RX FIFO overrun, remaining: %d\n", priv->remaining);
               lpc17_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR);
             }
 
@@ -1324,7 +1324,7 @@ static int lpc17_interrupt(int irq, void *context)
             {
               /* Terminate the transfer with an error */
 
-              fllerr("ERROR: TX FIFO underrun, remaining: %d\n", priv->remaining);
+              mcerr("ERROR: TX FIFO underrun, remaining: %d\n", priv->remaining);
               lpc17_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR);
             }
 
@@ -1334,7 +1334,7 @@ static int lpc17_interrupt(int irq, void *context)
             {
               /* Terminate the transfer with an error */
 
-              fllerr("ERROR: Start bit, remaining: %d\n", priv->remaining);
+              mcerr("ERROR: Start bit, remaining: %d\n", priv->remaining);
               lpc17_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR);
             }
         }
diff --git a/arch/arm/src/lpc17xx/lpc17_serial.c b/arch/arm/src/lpc17xx/lpc17_serial.c
index 0ec62236a65..7062c521f48 100644
--- a/arch/arm/src/lpc17xx/lpc17_serial.c
+++ b/arch/arm/src/lpc17xx/lpc17_serial.c
@@ -1153,7 +1153,7 @@ static int up_interrupt(int irq, void *context)
 
           default:
             {
-              _err("Unexpected IIR: %02x\n", status);
+              _err("ERROR: Unexpected IIR: %02x\n", status);
               break;
             }
         }
diff --git a/arch/arm/src/lpc17xx/lpc17_spi.c b/arch/arm/src/lpc17xx/lpc17_spi.c
index 7a53a040228..6ddef3951fc 100644
--- a/arch/arm/src/lpc17xx/lpc17_spi.c
+++ b/arch/arm/src/lpc17xx/lpc17_spi.c
@@ -267,7 +267,7 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency)
   priv->frequency = frequency;
   priv->actual    = actual;
 
-  spierr("Frequency %d->%d\n", frequency, actual);
+  spiinfo("Frequency %d->%d\n", frequency, actual);
   return actual;
 }
 
@@ -429,7 +429,7 @@ static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size
   FAR uint8_t *ptr = (FAR uint8_t *)buffer;
   uint8_t data;
 
-  spierr("nwords: %d\n", nwords);
+  spiinfo("nwords: %d\n", nwords);
   while (nwords)
     {
       /* Write the data to transmitted to the SPI Data Register */
@@ -474,7 +474,7 @@ static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nw
 {
   FAR uint8_t *ptr = (FAR uint8_t *)buffer;
 
-  spierr("nwords: %d\n", nwords);
+  spiinfo("nwords: %d\n", nwords);
   while (nwords)
     {
       /* Write some dummy data to the SPI Data Register in order to clock the
diff --git a/arch/arm/src/lpc17xx/lpc17_usbdev.c b/arch/arm/src/lpc17xx/lpc17_usbdev.c
index d2c4606283e..ca4d5f90d80 100644
--- a/arch/arm/src/lpc17xx/lpc17_usbdev.c
+++ b/arch/arm/src/lpc17xx/lpc17_usbdev.c
@@ -102,10 +102,13 @@
 #ifdef CONFIG_DEBUG_USB
 #  define USB_ERROR_INT USBDEV_INT_ERRINT
 #else
-#  undef  CONFIG_LPC17_USBDEV_REGDEBUG
 #  define USB_ERROR_INT 0
 #endif
 
+#ifndef CONFIG_DEBUG_USB_INFO
+#  undef  CONFIG_LPC17_USBDEV_REGDEBUG
+#endif
+
 /* CLKCTRL enable bits */
 
 #define LPC17_CLKCTRL_ENABLES (USBDEV_CLK_DEVCLK|USBDEV_CLK_AHBCLK)
@@ -531,7 +534,7 @@ static struct lpc17_dmadesc_s  g_usbddesc[CONFIG_LPC17_USBDEV_NDMADESCRIPTORS];
 #ifdef CONFIG_LPC17_USBDEV_REGDEBUG
 static void lpc17_printreg(uint32_t addr, uint32_t val, bool iswrite)
 {
-  _llerr("%08x%s%08x\n", addr, iswrite ? "<-" : "->", val);
+  uinfo("%08x%s%08x\n", addr, iswrite ? "<-" : "->", val);
 }
 #endif
 
@@ -581,7 +584,7 @@ static void lpc17_checkreg(uint32_t addr, uint32_t val, bool iswrite)
             {
               /* No.. More than one. */
 
-              _llerr("[repeats %d more times]\n", count);
+              uinfo("[repeats %d more times]\n", count);
             }
         }
 
@@ -1076,8 +1079,9 @@ static int lpc17_wrrequest(struct lpc17_ep_s *privep)
       return OK;
     }
 
-  ullinfo("epphy=%d req=%p: len=%d xfrd=%d nullpkt=%d\n",
-          privep->epphy, privreq, privreq->req.len, privreq->req.xfrd, privep->txnullpkt);
+  uinfo("epphy=%d req=%p: len=%d xfrd=%d nullpkt=%d\n",
+        privep->epphy, privreq, privreq->req.len, privreq->req.xfrd,
+        privep->txnullpkt);
 
   /* Ignore any attempt to send a zero length packet on anything but EP0IN */
 
@@ -1185,8 +1189,8 @@ static int lpc17_rdrequest(struct lpc17_ep_s *privep)
       return OK;
     }
 
-  ullinfo("len=%d xfrd=%d nullpkt=%d\n",
-          privreq->req.len, privreq->req.xfrd, privep->txnullpkt);
+  uinfo("len=%d xfrd=%d nullpkt=%d\n",
+        privreq->req.len, privreq->req.xfrd, privep->txnullpkt);
 
   /* Ignore any attempt to receive a zero length packet */
 
@@ -1593,8 +1597,8 @@ static inline void lpc17_ep0setup(struct lpc17_usbdev_s *priv)
   index = GETUINT16(ctrl.index);
   len   = GETUINT16(ctrl.len);
 
-  ullinfo("type=%02x req=%02x value=%04x index=%04x len=%04x\n",
-          ctrl.type, ctrl.req, value, index, len);
+  uinfo("type=%02x req=%02x value=%04x index=%04x len=%04x\n",
+        ctrl.type, ctrl.req, value, index, len);
 
   /* Dispatch any non-standard requests */
 
@@ -1739,7 +1743,7 @@ static inline void lpc17_ep0setup(struct lpc17_usbdev_s *priv)
         if (((ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE) &&
             value == USB_FEATURE_TESTMODE)
           {
-            ullinfo("test mode: %d\n", index);
+            uinfo("test mode: %d\n", index);
           }
         else if ((ctrl.type & USB_REQ_RECIPIENT_MASK) != USB_REQ_RECIPIENT_ENDPOINT)
           {
@@ -2321,7 +2325,7 @@ static int lpc17_usbinterrupt(int irq, FAR void *context)
                                 }
                               else
                                 {
-                                  ullinfo("Pending data on OUT endpoint\n");
+                                  uinfo("Pending data on OUT endpoint\n");
                                   priv->rxpending = 1;
                                 }
                             }
@@ -2800,7 +2804,8 @@ static int lpc17_epsubmit(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s *r
   if (!req || !req->callback || !req->buf || !ep)
     {
       usbtrace(TRACE_DEVERROR(LPC17_TRACEERR_INVALIDPARMS), 0);
-      ullinfo("req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, ep);
+      uinfo("req=%p callback=%p buf=%p ep=%p\n",
+            req, req->callback, req->buf, ep);
       return -EINVAL;
     }
 #endif
diff --git a/arch/arm/src/lpc17xx/lpc17_usbhost.c b/arch/arm/src/lpc17xx/lpc17_usbhost.c
index 7d707daf797..d8d02f629c0 100644
--- a/arch/arm/src/lpc17xx/lpc17_usbhost.c
+++ b/arch/arm/src/lpc17xx/lpc17_usbhost.c
@@ -88,6 +88,10 @@
 #  define CONFIG_LPC17_USBHOST_NPREALLOC 8
 #endif
 
+#ifndef CONFIG_DEBUG_USB_INFO
+#  undef CONFIG_LPC17_USBHOST_REGDEBUG
+#endif
+
 /* OHCI Setup ******************************************************************/
 /* Frame Interval / Periodic Start */
 
@@ -114,7 +118,7 @@
 
 /* Dump GPIO registers */
 
-#if defined(CONFIG_LPC17_USBHOST_REGDEBUG) && defined(CONFIG_DEBUG_GPIO_INFO)
+#ifdef CONFIG_LPC17_USBHOST_REGDEBUG
 #  define usbhost_dumpgpio() \
    do { \
      lpc17_dumpgpio(GPIO_USB_DP, "D+ P0.29; D- P0.30"); \
@@ -456,7 +460,7 @@ static struct lpc17_xfrinfo_s g_xfrbuffers[CONFIG_LPC17_USBHOST_NPREALLOC];
 #ifdef CONFIG_LPC17_USBHOST_REGDEBUG
 static void lpc17_printreg(uint32_t addr, uint32_t val, bool iswrite)
 {
-  _llerr("%08x%s%08x\n", addr, iswrite ? "<-" : "->", val);
+  uinfo("%08x%s%08x\n", addr, iswrite ? "<-" : "->", val);
 }
 #endif
 
@@ -506,7 +510,7 @@ static void lpc17_checkreg(uint32_t addr, uint32_t val, bool iswrite)
             {
               /* No.. More than one. */
 
-              _llerr("[repeats %d more times]\n", count);
+              uinfo("[repeats %d more times]\n", count);
             }
         }
 
@@ -1642,7 +1646,7 @@ static int lpc17_usbinterrupt(int irq, void *context)
 
   intst  = lpc17_getreg(LPC17_USBHOST_INTST);
   regval = lpc17_getreg(LPC17_USBHOST_INTEN);
-  ullinfo("INST: %08x INTEN: %08x\n", intst, regval);
+  uinfo("INST: %08x INTEN: %08x\n", intst, regval);
 
   pending = intst & regval;
   if (pending != 0)
@@ -1652,18 +1656,18 @@ static int lpc17_usbinterrupt(int irq, void *context)
       if ((pending & OHCI_INT_RHSC) != 0)
         {
           uint32_t rhportst1 = lpc17_getreg(LPC17_USBHOST_RHPORTST1);
-          ullinfo("Root Hub Status Change, RHPORTST1: %08x\n", rhportst1);
+          uinfo("Root Hub Status Change, RHPORTST1: %08x\n", rhportst1);
 
           if ((rhportst1 & OHCI_RHPORTST_CSC) != 0)
             {
               uint32_t rhstatus = lpc17_getreg(LPC17_USBHOST_RHSTATUS);
-              ullinfo("Connect Status Change, RHSTATUS: %08x\n", rhstatus);
+              uinfo("Connect Status Change, RHSTATUS: %08x\n", rhstatus);
 
               /* If DRWE is set, Connect Status Change indicates a remote wake-up event */
 
               if (rhstatus & OHCI_RHSTATUS_DRWE)
                 {
-                  ullinfo("DRWE: Remote wake-up\n");
+                  uinfo("DRWE: Remote wake-up\n");
                 }
 
               /* Otherwise... Not a remote wake-up event */
@@ -1680,7 +1684,7 @@ static int lpc17_usbinterrupt(int irq, void *context)
                         {
                           /* Yes.. connected. */
 
-                          ullinfo("Connected\n");
+                          uinfo("Connected\n");
                           priv->connected = true;
                           priv->change    = true;
 
@@ -1694,7 +1698,7 @@ static int lpc17_usbinterrupt(int irq, void *context)
                         }
                       else
                         {
-                          ullerr("Spurious status change (connected)\n");
+                          uwarn("WARNING: Spurious status change (connected)\n");
                         }
 
                       /* The LSDA (Low speed device attached) bit is valid
@@ -1710,7 +1714,7 @@ static int lpc17_usbinterrupt(int irq, void *context)
                           priv->rhport.hport.speed = USB_SPEED_FULL;
                         }
 
-                      ullinfo("Speed:%d\n", priv->rhport.hport.speed);
+                      uinfo("Speed:%d\n", priv->rhport.hport.speed);
                     }
 
                   /* Check if we are now disconnected */
@@ -1719,7 +1723,7 @@ static int lpc17_usbinterrupt(int irq, void *context)
                     {
                       /* Yes.. disconnect the device */
 
-                      ullinfo("Disconnected\n");
+                      uinfo("Disconnected\n");
                       priv->connected = false;
                       priv->change    = true;
 
@@ -1750,7 +1754,7 @@ static int lpc17_usbinterrupt(int irq, void *context)
                     }
                   else
                     {
-                       ullerr("Spurious status change (disconnected)\n");
+                       uwarn("WARNING: Spurious status change (disconnected)\n");
                     }
                 }
 
@@ -1830,9 +1834,9 @@ static int lpc17_usbinterrupt(int irq, void *context)
                     {
                       /* The transfer failed for some reason... dump some diagnostic info. */
 
-                      ullerr("ERROR: ED xfrtype:%d TD CTRL:%08x/CC:%d RHPORTST1:%08x\n",
-                             ed->xfrtype, td->hw.ctrl, xfrinfo->tdstatus,
-                             lpc17_getreg(LPC17_USBHOST_RHPORTST1));
+                      uerr("ERROR: ED xfrtype:%d TD CTRL:%08x/CC:%d RHPORTST1:%08x\n",
+                           ed->xfrtype, td->hw.ctrl, xfrinfo->tdstatus,
+                           lpc17_getreg(LPC17_USBHOST_RHPORTST1));
                     }
 #endif
 
@@ -1894,7 +1898,7 @@ static int lpc17_usbinterrupt(int irq, void *context)
 #ifdef CONFIG_DEBUG_USB
       if ((pending & LPC17_DEBUG_INTS) != 0)
         {
-          ullerr("ERROR: Unhandled interrupts INTST:%08x\n", intst);
+          uerr("ERROR: Unhandled interrupts INTST:%08x\n", intst);
         }
 #endif
 
@@ -1967,8 +1971,8 @@ static int lpc17_wait(struct usbhost_connection_s *conn,
               *hport = connport;
               leave_critical_section(flags);
 
-              uerr("RHport Connected: %s\n",
-                   connport->connected ? "YES" : "NO");
+              uinfo("RHport Connected: %s\n",
+                    connport->connected ? "YES" : "NO");
 
               return OK;
             }
@@ -1987,7 +1991,7 @@ static int lpc17_wait(struct usbhost_connection_s *conn,
           *hport = connport;
           leave_critical_section(flags);
 
-          uerr("Hub port Connected: %s\n", connport->connected ? "YES" : "NO");
+          uinfo("Hub port Connected: %s\n", connport->connected ? "YES" : "NO");
           return OK;
         }
 #endif
@@ -2041,7 +2045,7 @@ static int lpc17_rh_enumerate(struct usbhost_connection_s *conn,
     {
       /* No, return an error */
 
-      uerr("Not connected\n");
+      uwarn("WARNING: Not connected\n");
       return -ENODEV;
     }
 
@@ -3454,7 +3458,7 @@ static int lpc17_connect(FAR struct usbhost_driver_s *drvr,
   /* Set the connected/disconnected flag */
 
   hport->connected = connected;
-  ullinfo("Hub port %d connected: %s\n", hport->port, connected ? "YES" : "NO");
+  uinfo("Hub port %d connected: %s\n", hport->port, connected ? "YES" : "NO");
 
   /* Report the connection event */
 
@@ -3695,7 +3699,7 @@ struct usbhost_connection_s *lpc17_usbhost_initialize(int controller)
   lpc17_configgpio(GPIO_USB_OVRCR);   /* USB port Over-Current status */
   usbhost_dumpgpio();
 
-  uerr("Initializing Host Stack\n");
+  uinfo("Initializing Host Stack\n");
 
   /* Show AHB SRAM memory map */
 
@@ -3825,7 +3829,7 @@ struct usbhost_connection_s *lpc17_usbhost_initialize(int controller)
 
   if (irq_attach(LPC17_IRQ_USB, lpc17_usbinterrupt) != 0)
     {
-      uerr("Failed to attach IRQ\n");
+      uerr("ERROR: Failed to attach IRQ\n");
       return NULL;
     }
 
@@ -3850,8 +3854,8 @@ struct usbhost_connection_s *lpc17_usbhost_initialize(int controller)
   /* Enable interrupts at the interrupt controller */
 
   up_enable_irq(LPC17_IRQ_USB); /* enable USB interrupt */
-  uerr("USB host Initialized, Device connected:%s\n",
-       priv->connected ? "YES" : "NO");
+  uinfo("USB host Initialized, Device connected:%s\n",
+        priv->connected ? "YES" : "NO");
 
   return &g_usbconn;
 }
diff --git a/arch/arm/src/lpc214x/lpc214x_decodeirq.c b/arch/arm/src/lpc214x/lpc214x_decodeirq.c
index 382c0bba022..331fea560eb 100644
--- a/arch/arm/src/lpc214x/lpc214x_decodeirq.c
+++ b/arch/arm/src/lpc214x/lpc214x_decodeirq.c
@@ -111,8 +111,8 @@ static void lpc214x_decodeirq(uint32_t *regs)
 #endif
 {
 #ifdef CONFIG_SUPPRESS_INTERRUPTS
-  lowsyslog(LOG_ERR, "Unexpected IRQ\n");
   CURRENT_REGS = regs;
+  err("ERROR: Unexpected IRQ\n");
   PANIC();
 #else
 
diff --git a/arch/arm/src/lpc214x/lpc214x_serial.c b/arch/arm/src/lpc214x/lpc214x_serial.c
index 1f699f51295..e1b3511f9ca 100644
--- a/arch/arm/src/lpc214x/lpc214x_serial.c
+++ b/arch/arm/src/lpc214x/lpc214x_serial.c
@@ -549,7 +549,7 @@ static int up_interrupt(int irq, void *context)
 
           default:
             {
-              _err("Unexpected IIR: %02x\n", status);
+              _err("ERROR: Unexpected IIR: %02x\n", status);
               break;
             }
         }
diff --git a/arch/arm/src/lpc214x/lpc214x_usbdev.c b/arch/arm/src/lpc214x/lpc214x_usbdev.c
index e9ea74f088a..636c7391251 100644
--- a/arch/arm/src/lpc214x/lpc214x_usbdev.c
+++ b/arch/arm/src/lpc214x/lpc214x_usbdev.c
@@ -382,7 +382,7 @@ struct lpc214x_usbdev_s
 
 /* Register operations ********************************************************/
 
-#if defined(CONFIG_LPC214X_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES)
+#ifdef CONFIG_LPC214X_USBDEV_REGDEBUG
 static uint32_t lpc214x_getreg(uint32_t addr);
 static void lpc214x_putreg(uint32_t val, uint32_t addr);
 #else
@@ -518,7 +518,7 @@ static const struct usbdev_ops_s g_devops =
  *
  ****************************************************************************/
 
-#if defined(CONFIG_LPC214X_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES)
+#ifdef CONFIG_LPC214X_USBDEV_REGDEBUG
 static uint32_t lpc214x_getreg(uint32_t addr)
 {
   static uint32_t prevaddr = 0;
@@ -539,7 +539,7 @@ static uint32_t lpc214x_getreg(uint32_t addr)
         {
           if (count == 4)
             {
-              _llerr("...\n");
+              uinfo("...\n");
             }
 
           return val;
@@ -556,7 +556,7 @@ static uint32_t lpc214x_getreg(uint32_t addr)
         {
           /* Yes.. then show how many times the value repeated */
 
-          _llerr("[repeats %d more times]\n", count-3);
+          uinfo("[repeats %d more times]\n", count-3);
         }
 
       /* Save the new address, value, and count */
@@ -568,7 +568,7 @@ static uint32_t lpc214x_getreg(uint32_t addr)
 
   /* Show the register value read */
 
-  _llerr("%08x->%08x\n", addr, val);
+  uinfo("%08x->%08x\n", addr, val);
   return val;
 }
 #endif
@@ -581,12 +581,12 @@ static uint32_t lpc214x_getreg(uint32_t addr)
  *
  ****************************************************************************/
 
-#if defined(CONFIG_LPC214X_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES)
+#ifdef CONFIG_LPC214X_USBDEV_REGDEBUG
 static void lpc214x_putreg(uint32_t val, uint32_t addr)
 {
   /* Show the register value being written */
 
-  _llerr("%08x<-%08x\n", addr, val);
+  uinfo("%08x<-%08x\n", addr, val);
 
   /* Write the value */
 
@@ -1021,8 +1021,9 @@ static int lpc214x_wrrequest(struct lpc214x_ep_s *privep)
       return OK;
     }
 
-  ullinfo("epphy=%d req=%p: len=%d xfrd=%d nullpkt=%d\n",
-          privep->epphy, privreq, privreq->req.len, privreq->req.xfrd, privep->txnullpkt);
+  uinfo("epphy=%d req=%p: len=%d xfrd=%d nullpkt=%d\n",
+        privep->epphy, privreq, privreq->req.len, privreq->req.xfrd,
+        privep->txnullpkt);
 
   /* Ignore any attempt to send a zero length packet on anything but EP0IN */
 
@@ -1130,8 +1131,8 @@ static int lpc214x_rdrequest(struct lpc214x_ep_s *privep)
       return OK;
     }
 
-  ullinfo("len=%d xfrd=%d nullpkt=%d\n",
-          privreq->req.len, privreq->req.xfrd, privep->txnullpkt);
+  uinfo("len=%d xfrd=%d nullpkt=%d\n",
+        privreq->req.len, privreq->req.xfrd, privep->txnullpkt);
 
   /* Ignore any attempt to receive a zero length packet */
 
@@ -1552,8 +1553,8 @@ static inline void lpc214x_ep0setup(struct lpc214x_usbdev_s *priv)
   index = GETUINT16(ctrl.index);
   len   = GETUINT16(ctrl.len);
 
-  ullinfo("type=%02x req=%02x value=%04x index=%04x len=%04x\n",
-          ctrl.type, ctrl.req, value, index, len);
+  uinfo("type=%02x req=%02x value=%04x index=%04x len=%04x\n",
+        ctrl.type, ctrl.req, value, index, len);
 
   /* Dispatch any non-standard requests */
 
@@ -1697,7 +1698,7 @@ static inline void lpc214x_ep0setup(struct lpc214x_usbdev_s *priv)
         if (((ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE) &&
             value == USB_FEATURE_TESTMODE)
           {
-            ullinfo("test mode: %d\n", index);
+            uinfo("test mode: %d\n", index);
           }
         else if ((ctrl.type & USB_REQ_RECIPIENT_MASK) != USB_REQ_RECIPIENT_ENDPOINT)
           {
@@ -2287,7 +2288,7 @@ static int lpc214x_usbinterrupt(int irq, FAR void *context)
                                 }
                               else
                                 {
-                                  ullinfo("Pending data on OUT endpoint\n");
+                                  uinfo("Pending data on OUT endpoint\n");
                                   priv->rxpending = 1;
                                 }
                             }
@@ -2763,7 +2764,8 @@ static int lpc214x_epsubmit(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s
   if (!req || !req->callback || !req->buf || !ep)
     {
       usbtrace(TRACE_DEVERROR(LPC214X_TRACEERR_INVALIDPARMS), 0);
-      ullinfo("req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, ep);
+      uinfo("req=%p callback=%p buf=%p ep=%p\n",
+            req, req->callback, req->buf, ep);
       return -EINVAL;
     }
 #endif
diff --git a/arch/arm/src/lpc2378/lpc23xx_decodeirq.c b/arch/arm/src/lpc2378/lpc23xx_decodeirq.c
index aca536e6651..9c0e0b5b764 100644
--- a/arch/arm/src/lpc2378/lpc23xx_decodeirq.c
+++ b/arch/arm/src/lpc2378/lpc23xx_decodeirq.c
@@ -110,9 +110,9 @@ static void lpc23xx_decodeirq(uint32_t *regs)
 #endif
 {
 #ifdef CONFIG_SUPPRESS_INTERRUPTS
-  lowsyslog(LOG_ERR, "Unexpected IRQ\n");
-  CURRENT_REGS = regs;
   PANIC();
+  err("ERROR: Unexpected IRQ\n");
+  CURRENT_REGS = regs;
 #else
 
   /* Check which IRQ fires */
diff --git a/arch/arm/src/lpc2378/lpc23xx_i2c.c b/arch/arm/src/lpc2378/lpc23xx_i2c.c
index 6932e932102..1c281e88574 100644
--- a/arch/arm/src/lpc2378/lpc23xx_i2c.c
+++ b/arch/arm/src/lpc2378/lpc23xx_i2c.c
@@ -490,7 +490,7 @@ struct i2c_master_s *lpc2378_i2cbus_initialize(int port)
 
   if (port > 1)
     {
-      _err("lpc I2C Only support 0,1\n");
+      l2cerr("ERROR: lpc I2C Only support 0,1\n");
       return NULL;
     }
 
diff --git a/arch/arm/src/lpc2378/lpc23xx_serial.c b/arch/arm/src/lpc2378/lpc23xx_serial.c
index 50aaa662a6b..48e322ec15a 100644
--- a/arch/arm/src/lpc2378/lpc23xx_serial.c
+++ b/arch/arm/src/lpc2378/lpc23xx_serial.c
@@ -667,7 +667,7 @@ static int up_interrupt(int irq, void *context)
 
         default:
           {
-            _err("Unexpected IIR: %02x\n", status);
+            _err("ERROR: Unexpected IIR: %02x\n", status);
             break;
           }
         }
diff --git a/arch/arm/src/lpc2378/lpc23xx_spi.c b/arch/arm/src/lpc2378/lpc23xx_spi.c
index 95b0cdcd1d7..cf95f63a8bc 100644
--- a/arch/arm/src/lpc2378/lpc23xx_spi.c
+++ b/arch/arm/src/lpc2378/lpc23xx_spi.c
@@ -274,7 +274,7 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency)
   priv->frequency = frequency;
   priv->actual    = actual;
 
-  spierr("Frequency %d->%d\n", frequency, actual);
+  spiinfo("Frequency %d->%d\n", frequency, actual);
   return actual;
 }
 
@@ -438,7 +438,7 @@ static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size
   FAR uint8_t *ptr = (FAR uint8_t *)buffer;
   uint8_t data;
 
-  spierr("nwords: %d\n", nwords);
+  spiinfo("nwords: %d\n", nwords);
   while (nwords)
     {
       /* Write the data to transmitted to the SPI Data Register */
@@ -483,7 +483,7 @@ static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nw
 {
   FAR uint8_t *ptr = (FAR uint8_t *)buffer;
 
-  spierr("nwords: %d\n", nwords);
+  spiinfo("nwords: %d\n", nwords);
   while (nwords)
     {
       /* Write some dummy data to the SPI Data Register in order to clock the
diff --git a/arch/arm/src/lpc31xx/Kconfig b/arch/arm/src/lpc31xx/Kconfig
index e89430ec9b0..addeaf16e42 100644
--- a/arch/arm/src/lpc31xx/Kconfig
+++ b/arch/arm/src/lpc31xx/Kconfig
@@ -243,11 +243,11 @@ config LPC31_USBDEV_DMA
 
 config LPC31_USBDEV_REGDEBUG
 	bool "Register level debug"
-	depends on DEBUG_FEATURES
+	depends on DEBUG_USB_INFO
 	default n
 	---help---
 		Output detailed register-level USB device debug information.  Requires
-		also CONFIG_DEBUG_FEATURES.
+		also CONFIG_DEBUG_USB_INFO.
 
 endmenu # USB device driver controller (DCD) options
 endif # LPC31_USBOTG && USBDEV
@@ -301,7 +301,7 @@ config LPC31_EHCI_PREALLOCATE
 config LPC31_EHCI_REGDEBUG
 	bool "Enable low-level EHCI register debug"
 	default n
-	depends on DEBUG_FEATURES
+	depends on DEBUG_USB_INFO
 
 endmenu # USB host controller driver (HCD) options
 endif # LPC31_USBOTG && USBHOST
@@ -310,9 +310,9 @@ menu "SPI device driver options"
 
 config LPC31_SPI_REGDEBUG
 	bool "SPI Register level debug"
-	depends on LPC31_SPI && DEBUG_FEATURES
+	depends on LPC31_SPI && DEBUG_SPI_INFO
 	default n
 	---help---
-		Output detailed register-level SPI device debug information.  Requires also CONFIG_DEBUG_FEATURES.
+		Output detailed register-level SPI device debug information.  Requires also CONFIG_DEBUG_SPI_INFO.
 
 endmenu # SPI device driver options
diff --git a/arch/arm/src/lpc31xx/lpc31_decodeirq.c b/arch/arm/src/lpc31xx/lpc31_decodeirq.c
index 9cfcd3f4435..a4f7a11628f 100644
--- a/arch/arm/src/lpc31xx/lpc31_decodeirq.c
+++ b/arch/arm/src/lpc31xx/lpc31_decodeirq.c
@@ -76,8 +76,8 @@
 void up_decodeirq(uint32_t *regs)
 {
 #ifdef CONFIG_SUPPRESS_INTERRUPTS
-  lowsyslog(LOG_ERR, "Unexpected IRQ\n");
   CURRENT_REGS = regs;
+  err("ERROR: Unexpected IRQ\n");
   PANIC();
 #else
   int index;
diff --git a/arch/arm/src/lpc31xx/lpc31_ehci.c b/arch/arm/src/lpc31xx/lpc31_ehci.c
index 1532feddbdf..e37abe4997f 100644
--- a/arch/arm/src/lpc31xx/lpc31_ehci.c
+++ b/arch/arm/src/lpc31xx/lpc31_ehci.c
@@ -113,7 +113,7 @@
 
 /* Debug options */
 
-#ifndef CONFIG_DEBUG_FEATURES
+#ifndef CONFIG_DEBUG_USB_INFO
 #  undef CONFIG_LPC31_EHCI_REGDEBUG
 #endif
 
@@ -826,7 +826,7 @@ static uint32_t lpc31_swap32(uint32_t value)
 static void lpc31_printreg(volatile uint32_t *regaddr, uint32_t regval,
                           bool iswrite)
 {
-  _llerr("%08x%s%08x\n", (uintptr_t)regaddr, iswrite ? "<-" : "->", regval);
+  uinfo("%08x%s%08x\n", (uintptr_t)regaddr, iswrite ? "<-" : "->", regval);
 }
 #endif
 
@@ -877,7 +877,7 @@ static void lpc31_checkreg(volatile uint32_t *regaddr, uint32_t regval, bool isw
             {
               /* No.. More than one. */
 
-              _llerr("[repeats %d more times]\n", count);
+              uinfo("[repeats %d more times]\n", count);
             }
         }
 
@@ -1456,13 +1456,13 @@ static int lpc31_qh_flush(struct lpc31_qh_s *qh)
 #ifdef CONFIG_LPC31_EHCI_REGDEBUG
 static void lpc31_qtd_print(struct lpc31_qtd_s *qtd)
 {
-  uerr("  QTD[%p]:\n", qtd);
-  uerr("    hw:\n");
-  uerr("      nqp: %08x alt: %08x token: %08x\n",
-       qtd->hw.nqp, qtd->hw.alt, qtd->hw.token);
-  uerr("      bpl: %08x %08x %08x %08x %08x\n",
-       qtd->hw.bpl[0], qtd->hw.bpl[1], qtd->hw.bpl[2],
-       qtd->hw.bpl[3], qtd->hw.bpl[4]);
+  uinfo("  QTD[%p]:\n", qtd);
+  uinfo("    hw:\n");
+  uinfo("      nqp: %08x alt: %08x token: %08x\n",
+        qtd->hw.nqp, qtd->hw.alt, qtd->hw.token);
+  uinfo("      bpl: %08x %08x %08x %08x %08x\n",
+        qtd->hw.bpl[0], qtd->hw.bpl[1], qtd->hw.bpl[2],
+        qtd->hw.bpl[3], qtd->hw.bpl[4]);
 }
 #endif
 
@@ -1480,30 +1480,30 @@ static void lpc31_qh_print(struct lpc31_qh_s *qh)
   struct lpc31_epinfo_s *epinfo;
   struct ehci_overlay_s *overlay;
 
-  uerr("QH[%p]:\n", qh);
-  uerr("  hw:\n");
-  uerr("    hlp: %08x epchar: %08x epcaps: %08x cqp: %08x\n",
-       qh->hw.hlp, qh->hw.epchar, qh->hw.epcaps, qh->hw.cqp);
+  uinfo("QH[%p]:\n", qh);
+  uinfo("  hw:\n");
+  uinfo("    hlp: %08x epchar: %08x epcaps: %08x cqp: %08x\n",
+        qh->hw.hlp, qh->hw.epchar, qh->hw.epcaps, qh->hw.cqp);
 
   overlay = &qh->hw.overlay;
-  uerr("  overlay:\n");
-  uerr("    nqp: %08x alt: %08x token: %08x\n",
-       overlay->nqp, overlay->alt, overlay->token);
-  uerr("    bpl: %08x %08x %08x %08x %08x\n",
-       overlay->bpl[0], overlay->bpl[1], overlay->bpl[2],
-       overlay->bpl[3], overlay->bpl[4]);
+  uinfo("  overlay:\n");
+  uinfo("    nqp: %08x alt: %08x token: %08x\n",
+        overlay->nqp, overlay->alt, overlay->token);
+  uinfo("    bpl: %08x %08x %08x %08x %08x\n",
+        overlay->bpl[0], overlay->bpl[1], overlay->bpl[2],
+        overlay->bpl[3], overlay->bpl[4]);
 
-  uerr("  fqp:\n", qh->fqp);
+  uinfo("  fqp:\n", qh->fqp);
 
   epinfo = qh->epinfo;
-  uerr("  epinfo[%p]:\n", epinfo);
+  uinfo("  epinfo[%p]:\n", epinfo);
   if (epinfo)
     {
-      uerr("    EP%d DIR=%s FA=%08x TYPE=%d MaxPacket=%d\n",
-           epinfo->epno, epinfo->dirin ? "IN" : "OUT", epinfo->devaddr,
-           epinfo->xfrtype, epinfo->maxpacket);
-      uerr("    Toggle=%d iocwait=%d speed=%d result=%d\n",
-           epinfo->toggle, epinfo->iocwait, epinfo->speed, epinfo->result);
+      uinfo("    EP%d DIR=%s FA=%08x TYPE=%d MaxPacket=%d\n",
+            epinfo->epno, epinfo->dirin ? "IN" : "OUT", epinfo->devaddr,
+            epinfo->xfrtype, epinfo->maxpacket);
+      uinfo("    Toggle=%d iocwait=%d speed=%d result=%d\n",
+            epinfo->toggle, epinfo->iocwait, epinfo->speed, epinfo->result);
     }
 }
 #endif
@@ -3370,7 +3370,7 @@ static int lpc31_ehci_interrupt(int irq, FAR void *context)
 #ifdef CONFIG_USBHOST_TRACE
   usbhost_vtrace1(EHCI_VTRACE1_TOPHALF, usbsts & regval);
 #else
-  ullinfo("USBSTS: %08x USBINTR: %08x\n", usbsts, regval);
+  uinfo("USBSTS: %08x USBINTR: %08x\n", usbsts, regval);
 #endif
 
   /* Handle all unmasked interrupt sources */
@@ -4680,7 +4680,7 @@ static int lpc31_connect(FAR struct usbhost_driver_s *drvr,
   /* Set the connected/disconnected flag */
 
   hport->connected = connected;
-  ullinfo("Hub port %d connected: %s\n", hport->port, connected ? "YES" : "NO");
+  uinfo("Hub port %d connected: %s\n", hport->port, connected ? "YES" : "NO");
 
   /* Report the connection event */
 
diff --git a/arch/arm/src/lpc31xx/lpc31_serial.c b/arch/arm/src/lpc31xx/lpc31_serial.c
index b46c0598fc0..bf5ac8cd586 100644
--- a/arch/arm/src/lpc31xx/lpc31_serial.c
+++ b/arch/arm/src/lpc31xx/lpc31_serial.c
@@ -560,7 +560,7 @@ static int up_interrupt(int irq, void *context)
 
           default:
             {
-              _err("Unexpected IIR: %02x\n", status);
+              _err("ERROR: Unexpected IIR: %02x\n", status);
               break;
             }
         }
diff --git a/arch/arm/src/lpc31xx/lpc31_spi.c b/arch/arm/src/lpc31xx/lpc31_spi.c
index 074bbe2b7d4..ca2544bc265 100644
--- a/arch/arm/src/lpc31xx/lpc31_spi.c
+++ b/arch/arm/src/lpc31xx/lpc31_spi.c
@@ -66,7 +66,7 @@
  * CONFIG_DEBUG_FEATURES must also be defined
  */
 
-#ifndef CONFIG_DEBUG_FEATURES
+#ifndef CONFIG_DEBUG_SPI_INFO
 #  undef CONFIG_LPC31_SPI_REGDEBUG
 #endif
 
@@ -207,7 +207,7 @@ static bool spi_checkreg(bool wr, uint32_t value, uint32_t address)
     {
       if (g_ntimes > 0)
         {
-          _llerr("...[Repeats %d times]...\n", g_ntimes);
+          spiinfo("...[Repeats %d times]...\n", g_ntimes);
         }
 
       g_wrlast      = wr;
@@ -239,7 +239,7 @@ static void spi_putreg(uint32_t value, uint32_t address)
 {
   if (spi_checkreg(true, value, address))
     {
-      _llerr("%08x<-%08x\n", address, value);
+      spiinfo("%08x<-%08x\n", address, value);
     }
   putreg32(value, address);
 }
@@ -265,7 +265,7 @@ static uint32_t spi_getreg(uint32_t address)
   uint32_t value = getreg32(address);
   if (spi_checkreg(false, value, address))
     {
-      _llerr("%08x->%08x\n", address, value);
+      spiinfo("%08x->%08x\n", address, value);
     }
   return value;
 }
@@ -921,10 +921,10 @@ FAR struct spi_dev_s *lpc31_spibus_initialize(int port)
    */
 
 #ifdef CONFIG_LPC31_SPI_REGDEBUG
-  _llerr("PINS: %08x MODE0: %08x MODE1: %08x\n",
-        spi_getreg(LPC31_IOCONFIG_SPI_PINS),
-        spi_getreg(LPC31_IOCONFIG_SPI_MODE0),
-        spi_getreg(LPC31_IOCONFIG_SPI_MODE1));
+  spiinfo("PINS: %08x MODE0: %08x MODE1: %08x\n",
+          spi_getreg(LPC31_IOCONFIG_SPI_PINS),
+          spi_getreg(LPC31_IOCONFIG_SPI_MODE0),
+          spi_getreg(LPC31_IOCONFIG_SPI_MODE1));
 #endif
 
   /* Enable SPI clocks */
diff --git a/arch/arm/src/lpc31xx/lpc31_usbdev.c b/arch/arm/src/lpc31xx/lpc31_usbdev.c
index f75eb1aa529..1cc9ec0d38b 100644
--- a/arch/arm/src/lpc31xx/lpc31_usbdev.c
+++ b/arch/arm/src/lpc31xx/lpc31_usbdev.c
@@ -343,7 +343,7 @@ struct lpc31_usbdev_s
 
 /* Register operations ********************************************************/
 
-#if defined(CONFIG_LPC31_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES)
+#ifdef CONFIG_LPC31_USBDEV_REGDEBUG
 static uint32_t lpc31_getreg(uint32_t addr);
 static void lpc31_putreg(uint32_t val, uint32_t addr);
 #else
@@ -480,7 +480,7 @@ static const struct usbdev_ops_s g_devops =
  *
  ****************************************************************************/
 
-#if defined(CONFIG_LPC31_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES)
+#ifdef CONFIG_LPC31_USBDEV_REGDEBUG
 static uint32_t lpc31_getreg(uint32_t addr)
 {
   static uint32_t prevaddr = 0;
@@ -501,7 +501,7 @@ static uint32_t lpc31_getreg(uint32_t addr)
         {
           if (count == 4)
             {
-              _llerr("...\n");
+              uinfo("...\n");
             }
 
           return val;
@@ -518,7 +518,7 @@ static uint32_t lpc31_getreg(uint32_t addr)
         {
           /* Yes.. then show how many times the value repeated */
 
-          _llerr("[repeats %d more times]\n", count-3);
+          uinfo("[repeats %d more times]\n", count-3);
         }
 
       /* Save the new address, value, and count */
@@ -530,7 +530,7 @@ static uint32_t lpc31_getreg(uint32_t addr)
 
   /* Show the register value read */
 
-  _llerr("%08x->%08x\n", addr, val);
+  uinfo("%08x->%08x\n", addr, val);
   return val;
 }
 #endif
@@ -543,12 +543,12 @@ static uint32_t lpc31_getreg(uint32_t addr)
  *
  ****************************************************************************/
 
-#if defined(CONFIG_LPC31_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES)
+#ifdef CONFIG_LPC31_USBDEV_REGDEBUG
 static void lpc31_putreg(uint32_t val, uint32_t addr)
 {
   /* Show the register value being written */
 
-  _llerr("%08x<-%08x\n", addr, val);
+  uinfo("%08x<-%08x\n", addr, val);
 
   /* Write the value */
 
@@ -1183,8 +1183,8 @@ static inline void lpc31_ep0setup(struct lpc31_usbdev_s *priv)
   index = GETUINT16(ctrl.index);
   len   = GETUINT16(ctrl.len);
 
-  ullinfo("type=%02x req=%02x value=%04x index=%04x len=%04x\n",
-          ctrl.type, ctrl.req, value, index, len);
+  uinfo("type=%02x req=%02x value=%04x index=%04x len=%04x\n",
+        ctrl.type, ctrl.req, value, index, len);
 
   /* Dispatch any non-standard requests */
   if ((ctrl.type & USB_REQ_TYPE_MASK) != USB_REQ_TYPE_STANDARD)
@@ -1323,7 +1323,7 @@ static inline void lpc31_ep0setup(struct lpc31_usbdev_s *priv)
           if (((ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE) &&
               value == USB_FEATURE_TESTMODE)
             {
-              ullinfo("test mode: %d\n", index);
+              uinfo("test mode: %d\n", index);
             }
           else if ((ctrl.type & USB_REQ_RECIPIENT_MASK) != USB_REQ_RECIPIENT_ENDPOINT)
             {
@@ -2083,7 +2083,7 @@ static int lpc31_epsubmit(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s *r
   if (!req || !req->callback || !req->buf || !ep)
     {
       usbtrace(TRACE_DEVERROR(LPC31_TRACEERR_INVALIDPARMS), 0);
-      ullinfo("req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, ep);
+      uinfo("req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, ep);
       return -EINVAL;
     }
 #endif
diff --git a/arch/arm/src/lpc43xx/Kconfig b/arch/arm/src/lpc43xx/Kconfig
index 84868ab13fa..e7f830ed2ba 100644
--- a/arch/arm/src/lpc43xx/Kconfig
+++ b/arch/arm/src/lpc43xx/Kconfig
@@ -457,9 +457,9 @@ config LPC43_RMII
 config LPC43_ETHERNET_REGDEBUG
 	bool "Register-Level Debug"
 	default n
-	depends on DEBUG_FEATURES
+	depends on DEBUG_NET_INFO
 	---help---
-		Enable very low-level register access debug.  Depends on CONFIG_DEBUG_FEATURES.
+		Enable very low-level register access debug.  Depends on CONFIG_DEBUG_NET_INFO.
 
 endmenu # Ethernet MAC configuration
 endif # LPC43_ETHERNET
diff --git a/arch/arm/src/lpc43xx/lpc43_dac.c b/arch/arm/src/lpc43xx/lpc43_dac.c
index f14186f7d1d..51b7000def9 100644
--- a/arch/arm/src/lpc43xx/lpc43_dac.c
+++ b/arch/arm/src/lpc43xx/lpc43_dac.c
@@ -173,7 +173,7 @@ static int  dac_send(FAR struct dac_dev_s *dev, FAR struct dac_msg_s *msg)
 
 static int  dac_ioctl(FAR struct dac_dev_s *dev, int cmd, unsigned long arg)
 {
-  _err("Fix me:Not Implemented\n");
+  aerr("ERROR: Fix me:Not Implemented\n");
   return 0;
 }
 
diff --git a/arch/arm/src/lpc43xx/lpc43_ehci.c b/arch/arm/src/lpc43xx/lpc43_ehci.c
index a0483accd42..ae462f80b46 100644
--- a/arch/arm/src/lpc43xx/lpc43_ehci.c
+++ b/arch/arm/src/lpc43xx/lpc43_ehci.c
@@ -105,7 +105,7 @@
 
 /* Debug options */
 
-#ifndef CONFIG_DEBUG_FEATURES
+#ifndef CONFIG_DEBUG_USB_INFO
 #  undef CONFIG_LPC43_EHCI_REGDEBUG
 #endif
 
@@ -817,7 +817,7 @@ static uint32_t lpc43_swap32(uint32_t value)
 static void lpc43_printreg(volatile uint32_t *regaddr, uint32_t regval,
                           bool iswrite)
 {
-  _llerr("%08x%s%08x\n", (uintptr_t)regaddr, iswrite ? "<-" : "->", regval);
+  uinfo("%08x%s%08x\n", (uintptr_t)regaddr, iswrite ? "<-" : "->", regval);
 }
 #endif
 
@@ -868,7 +868,7 @@ static void lpc43_checkreg(volatile uint32_t *regaddr, uint32_t regval, bool isw
             {
               /* No.. More than one. */
 
-              _llerr("[repeats %d more times]\n", count);
+              uinfo("[repeats %d more times]\n", count);
             }
         }
 
@@ -1350,13 +1350,13 @@ static int lpc43_qh_discard(struct lpc43_qh_s *qh)
 #ifdef CONFIG_LPC43_EHCI_REGDEBUG
 static void lpc43_qtd_print(struct lpc43_qtd_s *qtd)
 {
-  uerr("  QTD[%p]:\n", qtd);
-  uerr("    hw:\n");
-  uerr("      nqp: %08x alt: %08x token: %08x\n",
-       qtd->hw.nqp, qtd->hw.alt, qtd->hw.token);
-  uerr("      bpl: %08x %08x %08x %08x %08x\n",
-       qtd->hw.bpl[0], qtd->hw.bpl[1], qtd->hw.bpl[2],
-       qtd->hw.bpl[3], qtd->hw.bpl[4]);
+  uinfo("  QTD[%p]:\n", qtd);
+  uinfo("    hw:\n");
+  uinfo("      nqp: %08x alt: %08x token: %08x\n",
+        qtd->hw.nqp, qtd->hw.alt, qtd->hw.token);
+  uinfo("      bpl: %08x %08x %08x %08x %08x\n",
+        qtd->hw.bpl[0], qtd->hw.bpl[1], qtd->hw.bpl[2],
+        qtd->hw.bpl[3], qtd->hw.bpl[4]);
 }
 #endif
 
@@ -1374,30 +1374,30 @@ static void lpc43_qh_print(struct lpc43_qh_s *qh)
   struct lpc43_epinfo_s *epinfo;
   struct ehci_overlay_s *overlay;
 
-  uerr("QH[%p]:\n", qh);
-  uerr("  hw:\n");
-  uerr("    hlp: %08x epchar: %08x epcaps: %08x cqp: %08x\n",
-       qh->hw.hlp, qh->hw.epchar, qh->hw.epcaps, qh->hw.cqp);
+  uinfo("QH[%p]:\n", qh);
+  uinfo("  hw:\n");
+  uinfo("    hlp: %08x epchar: %08x epcaps: %08x cqp: %08x\n",
+        qh->hw.hlp, qh->hw.epchar, qh->hw.epcaps, qh->hw.cqp);
 
   overlay = &qh->hw.overlay;
-  uerr("  overlay:\n");
-  uerr("    nqp: %08x alt: %08x token: %08x\n",
-       overlay->nqp, overlay->alt, overlay->token);
-  uerr("    bpl: %08x %08x %08x %08x %08x\n",
-       overlay->bpl[0], overlay->bpl[1], overlay->bpl[2],
-       overlay->bpl[3], overlay->bpl[4]);
+  uinfo("  overlay:\n");
+  uinfo("    nqp: %08x alt: %08x token: %08x\n",
+        overlay->nqp, overlay->alt, overlay->token);
+  uinfo("    bpl: %08x %08x %08x %08x %08x\n",
+        overlay->bpl[0], overlay->bpl[1], overlay->bpl[2],
+        overlay->bpl[3], overlay->bpl[4]);
 
-  uerr("  fqp:\n", qh->fqp);
+  uinfo("  fqp:\n", qh->fqp);
 
   epinfo = qh->epinfo;
-  uerr("  epinfo[%p]:\n", epinfo);
+  uinfo("  epinfo[%p]:\n", epinfo);
   if (epinfo)
     {
-      uerr("    EP%d DIR=%s FA=%08x TYPE=%d MaxPacket=%d\n",
-           epinfo->epno, epinfo->dirin ? "IN" : "OUT", epinfo->devaddr,
-           epinfo->xfrtype, epinfo->maxpacket);
-      uerr("    Toggle=%d iocwait=%d speed=%d result=%d\n",
-           epinfo->toggle, epinfo->iocwait, epinfo->speed, epinfo->result);
+      uinfo("    EP%d DIR=%s FA=%08x TYPE=%d MaxPacket=%d\n",
+            epinfo->epno, epinfo->dirin ? "IN" : "OUT", epinfo->devaddr,
+            epinfo->xfrtype, epinfo->maxpacket);
+      uinfo("    Toggle=%d iocwait=%d speed=%d result=%d\n",
+            epinfo->toggle, epinfo->iocwait, epinfo->speed, epinfo->result);
     }
 }
 #endif
@@ -3207,7 +3207,7 @@ static int lpc43_ehci_interrupt(int irq, FAR void *context)
 #ifdef CONFIG_USBHOST_TRACE
   usbhost_vtrace1(EHCI_VTRACE1_TOPHALF, usbsts & regval);
 #else
-  ullinfo("USBSTS: %08x USBINTR: %08x\n", usbsts, regval);
+  uinfo("USBSTS: %08x USBINTR: %08x\n", usbsts, regval);
 #endif
 
   /* Handle all unmasked interrupt sources */
@@ -4511,7 +4511,7 @@ static int lpc43_connect(FAR struct usbhost_driver_s *drvr,
   /* Set the connected/disconnected flag */
 
   hport->connected = connected;
-  ullinfo("Hub port %d connected: %s\n", hport->port, connected ? "YES" : "NO");
+  uinfo("Hub port %d connected: %s\n", hport->port, connected ? "YES" : "NO");
 
   /* Report the connection event */
 
diff --git a/arch/arm/src/lpc43xx/lpc43_ethernet.c b/arch/arm/src/lpc43xx/lpc43_ethernet.c
index 13b2983aafe..db05295ec07 100644
--- a/arch/arm/src/lpc43xx/lpc43_ethernet.c
+++ b/arch/arm/src/lpc43xx/lpc43_ethernet.c
@@ -197,7 +197,7 @@
  * enabled.
  */
 
-#ifndef CONFIG_DEBUG_FEATURES
+#ifndef CONFIG_DEBUG_NET_INFO
 #  undef CONFIG_LPC43_ETHMAC_REGDEBUG
 #endif
 
@@ -559,7 +559,7 @@ static struct lpc43_ethmac_s g_lpc43ethmac;
  ****************************************************************************/
 /* Register operations ******************************************************/
 
-#if defined(CONFIG_LPC43_ETHMAC_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES)
+#ifdef CONFIG_LPC43_ETHMAC_REGDEBUG
 static uint32_t lpc43_getreg(uint32_t addr);
 static void lpc43_putreg(uint32_t val, uint32_t addr);
 static void lpc43_checksetup(void);
@@ -683,7 +683,7 @@ static int  lpc43_ethconfig(FAR struct lpc43_ethmac_s *priv);
  *
  ****************************************************************************/
 
-#if defined(CONFIG_LPC43_ETHMAC_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES)
+#ifdef CONFIG_LPC43_ETHMAC_REGDEBUG
 static uint32_t lpc43_getreg(uint32_t addr)
 {
   static uint32_t prevaddr = 0;
@@ -704,7 +704,7 @@ static uint32_t lpc43_getreg(uint32_t addr)
         {
           if (count == 4)
             {
-              _llerr("...\n");
+              ninfo("...\n");
             }
 
           return val;
@@ -721,7 +721,7 @@ static uint32_t lpc43_getreg(uint32_t addr)
         {
           /* Yes.. then show how many times the value repeated */
 
-          _llerr("[repeats %d more times]\n", count-3);
+          ninfo("[repeats %d more times]\n", count-3);
         }
 
       /* Save the new address, value, and count */
@@ -733,7 +733,7 @@ static uint32_t lpc43_getreg(uint32_t addr)
 
   /* Show the register value read */
 
-  _llerr("%08x->%08x\n", addr, val);
+  ninfo("%08x->%08x\n", addr, val);
   return val;
 }
 #endif
@@ -755,12 +755,12 @@ static uint32_t lpc43_getreg(uint32_t addr)
  *
  ****************************************************************************/
 
-#if defined(CONFIG_LPC43_ETHMAC_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES)
+#ifdef CONFIG_LPC43_ETHMAC_REGDEBUG
 static void lpc43_putreg(uint32_t val, uint32_t addr)
 {
   /* Show the register value being written */
 
-  _llerr("%08x<-%08x\n", addr, val);
+  ninfo("%08x<-%08x\n", addr, val);
 
   /* Write the value */
 
@@ -782,7 +782,7 @@ static void lpc43_putreg(uint32_t val, uint32_t addr)
  *
  ****************************************************************************/
 
-#if defined(CONFIG_LPC43_ETHMAC_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES)
+#ifdef CONFIG_LPC43_ETHMAC_REGDEBUG
 static void lpc43_checksetup(void)
 {
 }
@@ -947,8 +947,8 @@ static int lpc43_transmit(FAR struct lpc43_ethmac_s *priv)
   txdesc  = priv->txhead;
   txfirst = txdesc;
 
-  nllinfo("d_len: %d d_buf: %p txhead: %p tdes0: %08x\n",
-          priv->dev.d_len, priv->dev.d_buf, txdesc, txdesc->tdes0);
+  ninfo("d_len: %d d_buf: %p txhead: %p tdes0: %08x\n",
+        priv->dev.d_len, priv->dev.d_buf, txdesc, txdesc->tdes0);
 
   DEBUGASSERT(txdesc && (txdesc->tdes0 & ETH_TDES0_OWN) == 0);
 
@@ -964,7 +964,7 @@ static int lpc43_transmit(FAR struct lpc43_ethmac_s *priv)
       bufcount = (priv->dev.d_len + (CONFIG_LPC43_ETH_BUFSIZE-1)) / CONFIG_LPC43_ETH_BUFSIZE;
       lastsize = priv->dev.d_len - (bufcount - 1) * CONFIG_LPC43_ETH_BUFSIZE;
 
-      nllinfo("bufcount: %d lastsize: %d\n", bufcount, lastsize);
+      ninfo("bufcount: %d lastsize: %d\n", bufcount, lastsize);
 
       /* Set the first segment bit in the first TX descriptor */
 
@@ -1074,8 +1074,8 @@ static int lpc43_transmit(FAR struct lpc43_ethmac_s *priv)
 
   priv->inflight++;
 
-  nllinfo("txhead: %p txtail: %p inflight: %d\n",
-          priv->txhead, priv->txtail, priv->inflight);
+  ninfo("txhead: %p txtail: %p inflight: %d\n",
+        priv->txhead, priv->txtail, priv->inflight);
 
   /* If all TX descriptors are in-flight, then we have to disable receive interrupts
    * too.  This is because receive events can trigger more un-stoppable transmit
@@ -1373,7 +1373,7 @@ static void lpc43_freesegment(FAR struct lpc43_ethmac_s *priv,
   struct eth_rxdesc_s *rxdesc;
   int i;
 
-  nllinfo("rxfirst: %p segments: %d\n", rxfirst, segments);
+  ninfo("rxfirst: %p segments: %d\n", rxfirst, segments);
 
   /* Set OWN bit in RX descriptors.  This gives the buffers back to DMA */
 
@@ -1431,8 +1431,8 @@ static int lpc43_recvframe(FAR struct lpc43_ethmac_s *priv)
   uint8_t *buffer;
   int i;
 
-  nllinfo("rxhead: %p rxcurr: %p segments: %d\n",
-          priv->rxhead, priv->rxcurr, priv->segments);
+  ninfo("rxhead: %p rxcurr: %p segments: %d\n",
+        priv->rxhead, priv->rxcurr, priv->segments);
 
   /* Check if there are free buffers.  We cannot receive new frames in this
    * design unless there is at least one free buffer.
@@ -1440,7 +1440,7 @@ static int lpc43_recvframe(FAR struct lpc43_ethmac_s *priv)
 
   if (!lpc43_isfreebuffer(priv))
     {
-      nllerr("No free buffers\n");
+      nerr("ERROR: No free buffers\n");
       return -ENOMEM;
     }
 
@@ -1497,7 +1497,7 @@ static int lpc43_recvframe(FAR struct lpc43_ethmac_s *priv)
               rxcurr = priv->rxcurr;
             }
 
-          nllinfo("rxhead: %p rxcurr: %p segments: %d\n",
+          ninfo("rxhead: %p rxcurr: %p segments: %d\n",
               priv->rxhead, priv->rxcurr, priv->segments);
 
           /* Check if any errors are reported in the frame */
@@ -1536,8 +1536,8 @@ static int lpc43_recvframe(FAR struct lpc43_ethmac_s *priv)
               priv->rxhead   = (struct eth_rxdesc_s *)rxdesc->rdes3;
               lpc43_freesegment(priv, rxcurr, priv->segments);
 
-              nllinfo("rxhead: %p d_buf: %p d_len: %d\n",
-                      priv->rxhead, dev->d_buf, dev->d_len);
+              ninfo("rxhead: %p d_buf: %p d_len: %d\n",
+                    priv->rxhead, dev->d_buf, dev->d_len);
 
               return OK;
             }
@@ -1547,7 +1547,7 @@ static int lpc43_recvframe(FAR struct lpc43_ethmac_s *priv)
                * scanning logic, and continue scanning with the next frame.
                */
 
-              nllerr("DROPPED: RX descriptor errors: %08x\n", rxdesc->rdes0);
+              nwarn("WARNING: Dropped, RX descriptor errors: %08x\n", rxdesc->rdes0);
               lpc43_freesegment(priv, rxcurr, priv->segments);
             }
         }
@@ -1563,8 +1563,8 @@ static int lpc43_recvframe(FAR struct lpc43_ethmac_s *priv)
 
   priv->rxhead = rxdesc;
 
-  nllinfo("rxhead: %p rxcurr: %p segments: %d\n",
-          priv->rxhead, priv->rxcurr, priv->segments);
+  ninfo("rxhead: %p rxcurr: %p segments: %d\n",
+        priv->rxhead, priv->rxcurr, priv->segments);
 
   return -EAGAIN;
 }
@@ -1608,7 +1608,7 @@ static void lpc43_receive(FAR struct lpc43_ethmac_s *priv)
 
       if (dev->d_len > CONFIG_NET_ETH_MTU)
         {
-          nllerr("DROPPED: Too big: %d\n", dev->d_len);
+          nwarn("WARNING: Dropped, Too big: %d\n", dev->d_len);
           /* Free dropped packet buffer */
 
           if (dev->d_buf)
@@ -1632,7 +1632,7 @@ static void lpc43_receive(FAR struct lpc43_ethmac_s *priv)
 #ifdef CONFIG_NET_IPv4
       if (BUF->type == HTONS(ETHTYPE_IP))
         {
-          nllinfo("IPv4 frame\n");
+          ninfo("IPv4 frame\n");
 
           /* Handle ARP on input then give the IPv4 packet to the network
            * layer
@@ -1672,7 +1672,7 @@ static void lpc43_receive(FAR struct lpc43_ethmac_s *priv)
 #ifdef CONFIG_NET_IPv6
       if (BUF->type == HTONS(ETHTYPE_IP6))
         {
-          nllinfo("Iv6 frame\n");
+          ninfo("Iv6 frame\n");
 
           /* Give the IPv6 packet to the network layer */
 
@@ -1709,7 +1709,7 @@ static void lpc43_receive(FAR struct lpc43_ethmac_s *priv)
 #ifdef CONFIG_NET_ARP
       if (BUF->type == htons(ETHTYPE_ARP))
         {
-          nllinfo("ARP frame\n");
+          ninfo("ARP frame\n");
 
           /* Handle ARP packet */
 
@@ -1727,7 +1727,7 @@ static void lpc43_receive(FAR struct lpc43_ethmac_s *priv)
       else
 #endif
         {
-          nllerr("DROPPED: Unknown type: %04x\n", BUF->type);
+          nwarn("WARNING: Dropped, Unknown type: %04x\n", BUF->type);
         }
 
       /* We are finished with the RX buffer.  NOTE:  If the buffer is
@@ -1768,8 +1768,8 @@ static void lpc43_freeframe(FAR struct lpc43_ethmac_s *priv)
   struct eth_txdesc_s *txdesc;
   int i;
 
-  nllinfo("txhead: %p txtail: %p inflight: %d\n",
-          priv->txhead, priv->txtail, priv->inflight);
+  ninfo("txhead: %p txtail: %p inflight: %d\n",
+        priv->txhead, priv->txtail, priv->inflight);
 
   /* Scan for "in-flight" descriptors owned by the CPU */
 
@@ -1784,8 +1784,8 @@ static void lpc43_freeframe(FAR struct lpc43_ethmac_s *priv)
            * TX descriptors.
            */
 
-          nllinfo("txtail: %p tdes0: %08x tdes2: %08x tdes3: %08x\n",
-                  txdesc, txdesc->tdes0, txdesc->tdes2, txdesc->tdes3);
+          ninfo("txtail: %p tdes0: %08x tdes2: %08x tdes3: %08x\n",
+                txdesc, txdesc->tdes0, txdesc->tdes2, txdesc->tdes3);
 
           DEBUGASSERT(txdesc->tdes2 != 0);
 
@@ -1837,8 +1837,8 @@ static void lpc43_freeframe(FAR struct lpc43_ethmac_s *priv)
 
       priv->txtail = txdesc;
 
-      nllinfo("txhead: %p txtail: %p inflight: %d\n",
-              priv->txhead, priv->txtail, priv->inflight);
+      ninfo("txhead: %p txtail: %p inflight: %d\n",
+            priv->txhead, priv->txtail, priv->inflight);
     }
 }
 
@@ -1975,7 +1975,7 @@ static inline void lpc43_interrupt_process(FAR struct lpc43_ethmac_s *priv)
     {
       /* Just let the user know what happened */
 
-      nllerr("Abnormal event(s): %08x\n", dmasr);
+      nerr("ERROR: Abnormal event(s): %08x\n", dmasr);
 
       /* Clear all pending abnormal events */
 
@@ -2179,7 +2179,7 @@ static void lpc43_txtimeout_expiry(int argc, uint32_t arg, ...)
 {
   FAR struct lpc43_ethmac_s *priv = (FAR struct lpc43_ethmac_s *)arg;
 
-  nllerr("Timeout!\n");
+  ninfo("Timeout!\n");
 
 #ifdef CONFIG_NET_NOINTS
   /* Disable further Ethernet interrupts.  This will prevent some race
@@ -2381,15 +2381,15 @@ static int lpc43_ifup(struct net_driver_s *dev)
   int ret;
 
 #ifdef CONFIG_NET_IPv4
-  nerr("Bringing up: %d.%d.%d.%d\n",
-       dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff,
-       (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24);
+  ninfo("Bringing up: %d.%d.%d.%d\n",
+        dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff,
+        (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24);
 #endif
 #ifdef CONFIG_NET_IPv6
-  nerr("Bringing up: %04x:%04x:%04x:%04x:%04x:%04x:%04x:%04x\n",
-       dev->d_ipv6addr[0], dev->d_ipv6addr[1], dev->d_ipv6addr[2],
-       dev->d_ipv6addr[3], dev->d_ipv6addr[4], dev->d_ipv6addr[5],
-       dev->d_ipv6addr[6], dev->d_ipv6addr[7]);
+  ninfo("Bringing up: %04x:%04x:%04x:%04x:%04x:%04x:%04x:%04x\n",
+        dev->d_ipv6addr[0], dev->d_ipv6addr[1], dev->d_ipv6addr[2],
+        dev->d_ipv6addr[3], dev->d_ipv6addr[4], dev->d_ipv6addr[5],
+        dev->d_ipv6addr[6], dev->d_ipv6addr[7]);
 #endif
 
   /* Configure the Ethernet interface for DMA operation. */
@@ -2435,7 +2435,7 @@ static int lpc43_ifdown(struct net_driver_s *dev)
   FAR struct lpc43_ethmac_s *priv = (FAR struct lpc43_ethmac_s *)dev->d_private;
   irqstate_t flags;
 
-  nerr("Taking the network down\n");
+  ninfo("Taking the network down\n");
 
   /* Disable the Ethernet interrupt */
 
@@ -2647,8 +2647,8 @@ static int lpc43_addmac(struct net_driver_s *dev, FAR const uint8_t *mac)
   uint32_t temp;
   uint32_t registeraddress;
 
-  nllinfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
-          mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+  ninfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
+        mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
 
   /* Add the MAC address to the hardware multicast hash table */
 
@@ -2704,8 +2704,8 @@ static int lpc43_rmmac(struct net_driver_s *dev, FAR const uint8_t *mac)
   uint32_t temp;
   uint32_t registeraddress;
 
-  nllinfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
-          mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+  ninfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
+        mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
 
   /* Remove the MAC address to the hardware multicast hash table */
 
@@ -3065,7 +3065,7 @@ static int lpc43_phyread(uint16_t phydevaddr, uint16_t phyregaddr, uint16_t *val
         }
     }
 
-  nerr("MII transfer timed out: phydevaddr: %04x phyregaddr: %04x\n",
+  nerr("ERROR: MII transfer timed out: phydevaddr: %04x phyregaddr: %04x\n",
        phydevaddr, phyregaddr);
 
   return -ETIMEDOUT;
@@ -3124,7 +3124,7 @@ static int lpc43_phywrite(uint16_t phydevaddr, uint16_t phyregaddr, uint16_t val
         }
     }
 
-  nerr("MII transfer timed out: phydevaddr: %04x phyregaddr: %04x value: %04x\n",
+  nerr("ERROR: MII transfer timed out: phydevaddr: %04x phyregaddr: %04x value: %04x\n",
        phydevaddr, phyregaddr, value);
 
   return -ETIMEDOUT;
@@ -3161,7 +3161,7 @@ static inline int lpc43_dm9161(FAR struct lpc43_ethmac_s *priv)
   ret = lpc43_phyread(CONFIG_LPC43_PHYADDR, MII_PHYID1, &phyval);
   if (ret < 0)
     {
-      nerr("Failed to read the PHY ID1: %d\n", ret);
+      nerr("ERROR: Failed to read the PHY ID1: %d\n", ret);
       return ret;
     }
 
@@ -3179,7 +3179,7 @@ static inline int lpc43_dm9161(FAR struct lpc43_ethmac_s *priv)
   ret = lpc43_phyread(CONFIG_LPC43_PHYADDR, 16, &phyval);
   if (ret < 0)
     {
-      nerr("Failed to read the PHY Register 0x10: %d\n", ret);
+      nerr("ERROR: Failed to read the PHY Register 0x10: %d\n", ret);
       return ret;
     }
 
@@ -3236,7 +3236,7 @@ static int lpc43_phyinit(FAR struct lpc43_ethmac_s *priv)
   ret = lpc43_phywrite(CONFIG_LPC43_PHYADDR, MII_MCR, MII_MCR_RESET);
   if (ret < 0)
     {
-      nerr("Failed to reset the PHY: %d\n", ret);
+      nerr("ERROR: Failed to reset the PHY: %d\n", ret);
       return ret;
     }
 
@@ -3248,7 +3248,7 @@ static int lpc43_phyinit(FAR struct lpc43_ethmac_s *priv)
   ret = lpc43_phy_boardinitialize(0);
   if (ret < 0)
     {
-      nerr("Failed to initialize the PHY: %d\n", ret);
+      nerr("ERROR: Failed to initialize the PHY: %d\n", ret);
       return ret;
     }
 #endif
@@ -3273,7 +3273,7 @@ static int lpc43_phyinit(FAR struct lpc43_ethmac_s *priv)
       ret = lpc43_phyread(CONFIG_LPC43_PHYADDR, MII_MSR, &phyval);
       if (ret < 0)
         {
-          nerr("Failed to read the PHY MSR: %d\n", ret);
+          nerr("ERROR: Failed to read the PHY MSR: %d\n", ret);
           return ret;
         }
       else if ((phyval & MII_MSR_LINKSTATUS) != 0)
@@ -3284,7 +3284,7 @@ static int lpc43_phyinit(FAR struct lpc43_ethmac_s *priv)
 
   if (timeout >= PHY_RETRY_TIMEOUT)
     {
-      nerr("Timed out waiting for link status: %04x\n", phyval);
+      nerr("ERROR: Timed out waiting for link status: %04x\n", phyval);
       return -ETIMEDOUT;
     }
 
@@ -3293,7 +3293,7 @@ static int lpc43_phyinit(FAR struct lpc43_ethmac_s *priv)
   ret = lpc43_phywrite(CONFIG_LPC43_PHYADDR, MII_MCR, MII_MCR_ANENABLE);
   if (ret < 0)
     {
-      nerr("Failed to enable auto-negotiation: %d\n", ret);
+      nerr("ERROR: Failed to enable auto-negotiation: %d\n", ret);
       return ret;
     }
 
@@ -3304,7 +3304,7 @@ static int lpc43_phyinit(FAR struct lpc43_ethmac_s *priv)
       ret = lpc43_phyread(CONFIG_LPC43_PHYADDR, MII_MSR, &phyval);
       if (ret < 0)
         {
-          nerr("Failed to read the PHY MSR: %d\n", ret);
+          nerr("ERROR: Failed to read the PHY MSR: %d\n", ret);
           return ret;
         }
       else if ((phyval & MII_MSR_ANEGCOMPLETE) != 0)
@@ -3315,7 +3315,7 @@ static int lpc43_phyinit(FAR struct lpc43_ethmac_s *priv)
 
   if (timeout >= PHY_RETRY_TIMEOUT)
     {
-      nerr("Timed out waiting for auto-negotiation\n");
+      nerr("ERROR: Timed out waiting for auto-negotiation\n");
       return -ETIMEDOUT;
     }
 
@@ -3324,7 +3324,7 @@ static int lpc43_phyinit(FAR struct lpc43_ethmac_s *priv)
   ret = lpc43_phyread(CONFIG_LPC43_PHYADDR, CONFIG_LPC43_PHYSR, &phyval);
   if (ret < 0)
     {
-      nerr("Failed to read PHY status register\n");
+      nerr("ERROR: Failed to read PHY status register\n");
       return ret;
     }
 
@@ -3418,7 +3418,7 @@ static int lpc43_phyinit(FAR struct lpc43_ethmac_s *priv)
   ret = lpc43_phywrite(CONFIG_LPC43_PHYADDR, MII_MCR, phyval);
   if (ret < 0)
     {
-     nerr("Failed to write the PHY MCR: %d\n", ret);
+     nerr("ERROR: Failed to write the PHY MCR: %d\n", ret);
       return ret;
     }
 
@@ -3434,9 +3434,9 @@ static int lpc43_phyinit(FAR struct lpc43_ethmac_s *priv)
 #endif
 #endif
 
-  nerr("Duplex: %s Speed: %d MBps\n",
-       priv->fduplex ? "FULL" : "HALF",
-       priv->mbps100 ? 100 : 10);
+  ninfo("Duplex: %s Speed: %d MBps\n",
+        priv->fduplex ? "FULL" : "HALF",
+        priv->mbps100 ? 100 : 10);
 
   return OK;
 }
@@ -3718,11 +3718,11 @@ static void lpc43_macaddress(FAR struct lpc43_ethmac_s *priv)
   FAR struct net_driver_s *dev = &priv->dev;
   uint32_t regval;
 
-  nllinfo("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
-          dev->d_ifname,
-          dev->d_mac.ether_addr_octet[0], dev->d_mac.ether_addr_octet[1],
-          dev->d_mac.ether_addr_octet[2], dev->d_mac.ether_addr_octet[3],
-          dev->d_mac.ether_addr_octet[4], dev->d_mac.ether_addr_octet[5]);
+  ninfo("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
+        dev->d_ifname,
+        dev->d_mac.ether_addr_octet[0], dev->d_mac.ether_addr_octet[1],
+        dev->d_mac.ether_addr_octet[2], dev->d_mac.ether_addr_octet[3],
+        dev->d_mac.ether_addr_octet[4], dev->d_mac.ether_addr_octet[5]);
 
   /* Set the MAC address high register */
 
@@ -3925,12 +3925,12 @@ static int lpc43_ethconfig(FAR struct lpc43_ethmac_s *priv)
 
   /* Reset the Ethernet block */
 
-  nllinfo("Reset the Ethernet block\n");
+  ninfo("Reset the Ethernet block\n");
   lpc43_ethreset(priv);
 
   /* Initialize the PHY */
 
-  nllinfo("Initialize the PHY\n");
+  ninfo("Initialize the PHY\n");
   ret = lpc43_phyinit(priv);
   if (ret < 0)
     {
@@ -3945,7 +3945,7 @@ static int lpc43_ethconfig(FAR struct lpc43_ethmac_s *priv)
 
   /* Initialize the MAC and DMA */
 
-  nllinfo("Initialize the MAC and DMA\n");
+  ninfo("Initialize the MAC and DMA\n");
   ret = lpc43_macconfig(priv);
   if (ret < 0)
     {
@@ -3966,7 +3966,7 @@ static int lpc43_ethconfig(FAR struct lpc43_ethmac_s *priv)
 
   /* Enable normal MAC operation */
 
-  nllinfo("Enable normal operation\n");
+  ninfo("Enable normal operation\n");
   return lpc43_macenable(priv);
 }
 
diff --git a/arch/arm/src/lpc43xx/lpc43_i2c.c b/arch/arm/src/lpc43xx/lpc43_i2c.c
index 4ec260760b7..fed79db2073 100644
--- a/arch/arm/src/lpc43xx/lpc43_i2c.c
+++ b/arch/arm/src/lpc43xx/lpc43_i2c.c
@@ -464,7 +464,7 @@ struct i2c_master_s *lpc43_i2cbus_initialize(int port)
 
   if (port > 1)
     {
-      _err("lpc I2C Only support 0,1\n");
+      i2cerr("ERROR: lpc I2C Only suppors ports 0 and 1\n");
       return NULL;
     }
 
diff --git a/arch/arm/src/lpc43xx/lpc43_idle.c b/arch/arm/src/lpc43xx/lpc43_idle.c
index 89c9d98e833..5cc38b16f5f 100644
--- a/arch/arm/src/lpc43xx/lpc43_idle.c
+++ b/arch/arm/src/lpc43xx/lpc43_idle.c
@@ -98,7 +98,7 @@ static void up_idlepm(void)
 
       /* Perform board-specific, state-dependent logic here */
 
-      _llinfo("newstate= %d oldstate=%d\n", newstate, oldstate);
+      _info("newstate= %d oldstate=%d\n", newstate, oldstate);
 
       /* Then force the global state change */
 
diff --git a/arch/arm/src/lpc43xx/lpc43_irq.c b/arch/arm/src/lpc43xx/lpc43_irq.c
index ea87cec8fe0..345f63b5c24 100644
--- a/arch/arm/src/lpc43xx/lpc43_irq.c
+++ b/arch/arm/src/lpc43xx/lpc43_irq.c
@@ -148,7 +148,7 @@ static void lpc43_dumpnvic(const char *msg, int irq)
 
 /****************************************************************************
  * Name: lpc43_nmi, lpc43_busfault, lpc43_usagefault, lpc43_pendsv,
- *       lpc43_errmonitor, lpc43_pendsv, lpc43_reserved
+ *       lpc43_dbgmonitor, lpc43_pendsv, lpc43_reserved
  *
  * Description:
  *   Handlers for various exceptions.  None are handled and all are fatal
@@ -190,7 +190,7 @@ static int lpc43_pendsv(int irq, FAR void *context)
   return 0;
 }
 
-static int lpc43_errmonitor(int irq, FAR void *context)
+static int lpc43_dbgmonitor(int irq, FAR void *context)
 {
   (void)up_irq_save();
   _err("PANIC!!! Debug Monitor received\n");
@@ -437,7 +437,7 @@ void up_irqinitialize(void)
   irq_attach(LPC43_IRQ_BUSFAULT, lpc43_busfault);
   irq_attach(LPC43_IRQ_USAGEFAULT, lpc43_usagefault);
   irq_attach(LPC43_IRQ_PENDSV, lpc43_pendsv);
-  irq_attach(LPC43_IRQ_DBGMONITOR, lpc43_errmonitor);
+  irq_attach(LPC43_IRQ_DBGMONITOR, lpc43_dbgmonitor);
   irq_attach(LPC43_IRQ_RESERVED, lpc43_reserved);
 #endif
 
diff --git a/arch/arm/src/lpc43xx/lpc43_rit.c b/arch/arm/src/lpc43xx/lpc43_rit.c
index 7d68c8f58ba..e42fc7db438 100644
--- a/arch/arm/src/lpc43xx/lpc43_rit.c
+++ b/arch/arm/src/lpc43xx/lpc43_rit.c
@@ -201,8 +201,8 @@ void up_timer_initialize(void)
       mask_bits++;
     }
 
-  _llerr("mask_bits = %d, mask = %X, ticks_per_int = %d\r\n",
-        mask_bits, (0xffffffff << (32 - mask_bits)), ticks_per_int);
+  tmrinfo("mask_bits = %d, mask = %X, ticks_per_int = %d\r\n",
+          mask_bits, (0xffffffff << (32 - mask_bits)), ticks_per_int);
 
   /* Set the mask and compare value so we get interrupts every
    * RIT_TIMER_RESOLUTION cycles.
diff --git a/arch/arm/src/lpc43xx/lpc43_serial.c b/arch/arm/src/lpc43xx/lpc43_serial.c
index e423e2c0da3..56e03bbea03 100644
--- a/arch/arm/src/lpc43xx/lpc43_serial.c
+++ b/arch/arm/src/lpc43xx/lpc43_serial.c
@@ -873,7 +873,7 @@ static int up_interrupt(int irq, void *context)
 
           default:
             {
-              _err("Unexpected IIR: %02x\n", status);
+              _err("ERROR: Unexpected IIR: %02x\n", status);
               break;
             }
         }
diff --git a/arch/arm/src/lpc43xx/lpc43_spi.c b/arch/arm/src/lpc43xx/lpc43_spi.c
index e686fb50543..e30b39bf259 100644
--- a/arch/arm/src/lpc43xx/lpc43_spi.c
+++ b/arch/arm/src/lpc43xx/lpc43_spi.c
@@ -259,7 +259,7 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency)
   priv->frequency = frequency;
   priv->actual    = actual;
 
-  spierr("Frequency %d->%d\n", frequency, actual);
+  spiinfo("Frequency %d->%d\n", frequency, actual);
   return actual;
 }
 
@@ -421,7 +421,7 @@ static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size
   FAR uint8_t *ptr = (FAR uint8_t *)buffer;
   uint8_t data;
 
-  spierr("nwords: %d\n", nwords);
+  spiinfo("nwords: %d\n", nwords);
   while (nwords)
     {
       /* Write the data to transmitted to the SPI Data Register */
@@ -466,7 +466,7 @@ static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nw
 {
   FAR uint8_t *ptr = (FAR uint8_t *)buffer;
 
-  spierr("nwords: %d\n", nwords);
+  spiinfo("nwords: %d\n", nwords);
   while (nwords)
     {
       /* Write some dummy data to the SPI Data Register in order to clock the
diff --git a/arch/arm/src/lpc43xx/lpc43_ssp.c b/arch/arm/src/lpc43xx/lpc43_ssp.c
index 3deb90d5030..49f7c5781f9 100644
--- a/arch/arm/src/lpc43xx/lpc43_ssp.c
+++ b/arch/arm/src/lpc43xx/lpc43_ssp.c
@@ -352,7 +352,7 @@ static uint32_t ssp_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency)
   priv->frequency = frequency;
   priv->actual    = actual;
 
-  spierr("Frequency %d->%d\n", frequency, actual);
+  spiinfo("Frequency %d->%d\n", frequency, actual);
   return actual;
 }
 
@@ -403,7 +403,7 @@ static void ssp_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
           break;
 
         default:
-          spierr("Bad mode: %d\n", mode);
+          spierr("ERROR: Bad mode: %d\n", mode);
           DEBUGASSERT(FALSE);
           return;
         }
@@ -491,7 +491,7 @@ static uint16_t ssp_send(FAR struct spi_dev_s *dev, uint16_t wd)
   /* Get the value from the RX FIFO and return it */
 
   regval = ssp_getreg(priv, LPC43_SSP_DR_OFFSET);
-  spierr("%04x->%04x\n", wd, regval);
+  spiinfo("%04x->%04x\n", wd, regval);
   return (uint16_t)regval;
 }
 
@@ -538,7 +538,7 @@ static void ssp_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer,
 
   /* While there is remaining to be sent (and no synchronization error has occurred) */
 
-  spierr("nwords: %d\n", nwords);
+  spiinfo("nwords: %d\n", nwords);
 
   tx.pv = txbuffer;
   rx.pv = rxbuffer;
diff --git a/arch/arm/src/lpc43xx/lpc43_usb0dev.c b/arch/arm/src/lpc43xx/lpc43_usb0dev.c
index af5337bda2d..c583dd30a18 100644
--- a/arch/arm/src/lpc43xx/lpc43_usb0dev.c
+++ b/arch/arm/src/lpc43xx/lpc43_usb0dev.c
@@ -361,7 +361,7 @@ struct lpc43_usbdev_s
 
 /* Register operations ********************************************************/
 
-#if defined(CONFIG_LPC43_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES)
+#ifdef CONFIG_LPC43_USBDEV_REGDEBUG
 static uint32_t lpc43_getreg(uint32_t addr);
 static void lpc43_putreg(uint32_t val, uint32_t addr);
 #else
@@ -501,7 +501,7 @@ static const struct usbdev_ops_s g_devops =
  *
  ****************************************************************************/
 
-#if defined(CONFIG_LPC43_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES)
+#ifdef CONFIG_LPC43_USBDEV_REGDEBUG
 static uint32_t lpc43_getreg(uint32_t addr)
 {
   static uint32_t prevaddr = 0;
@@ -522,7 +522,7 @@ static uint32_t lpc43_getreg(uint32_t addr)
         {
           if (count == 4)
             {
-              _llerr("...\n");
+              usbinfo("...\n");
             }
 
           return val;
@@ -539,7 +539,7 @@ static uint32_t lpc43_getreg(uint32_t addr)
         {
           /* Yes.. then show how many times the value repeated */
 
-          _llerr("[repeats %d more times]\n", count-3);
+          usbinfo("[repeats %d more times]\n", count-3);
         }
 
       /* Save the new address, value, and count */
@@ -551,7 +551,7 @@ static uint32_t lpc43_getreg(uint32_t addr)
 
   /* Show the register value read */
 
-  _llerr("%08x->%08x\n", addr, val);
+  usbinfo("%08x->%08x\n", addr, val);
   return val;
 }
 #endif
@@ -564,12 +564,12 @@ static uint32_t lpc43_getreg(uint32_t addr)
  *
  ****************************************************************************/
 
-#if defined(CONFIG_LPC43_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES)
+#ifdef CONFIG_LPC43_USBDEV_REGDEBUG
 static void lpc43_putreg(uint32_t val, uint32_t addr)
 {
   /* Show the register value being written */
 
-  _llerr("%08x<-%08x\n", addr, val);
+  usbinfo("%08x<-%08x\n", addr, val);
 
   /* Write the value */
 
@@ -1228,8 +1228,8 @@ static inline void lpc43_ep0setup(struct lpc43_usbdev_s *priv)
 
   priv->ep0buf_len = len;
 
-  ullinfo("type=%02x req=%02x value=%04x index=%04x len=%04x\n",
-          ctrl->type, ctrl->req, value, index, len);
+  uinfo("type=%02x req=%02x value=%04x index=%04x len=%04x\n",
+        ctrl->type, ctrl->req, value, index, len);
 
   /* Starting a control request - update state */
 
@@ -1393,7 +1393,7 @@ static inline void lpc43_ep0setup(struct lpc43_usbdev_s *priv)
           if (((ctrl->type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE) &&
               value == USB_FEATURE_TESTMODE)
             {
-              ullinfo("test mode: %d\n", index);
+              uinfo("test mode: %d\n", index);
             }
           else if ((ctrl->type & USB_REQ_RECIPIENT_MASK) != USB_REQ_RECIPIENT_ENDPOINT)
             {
@@ -2206,7 +2206,7 @@ static int lpc43_epsubmit(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s *r
   if (!req || !req->callback || !req->buf || !ep)
     {
       usbtrace(TRACE_DEVERROR(LPC43_TRACEERR_INVALIDPARMS), 0);
-      ullinfo("req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, ep);
+      uinfo("req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, ep);
       return -EINVAL;
     }
 #endif
diff --git a/arch/arm/src/nuc1xx/nuc_idle.c b/arch/arm/src/nuc1xx/nuc_idle.c
index 7462aa24aa2..791ce2f0918 100644
--- a/arch/arm/src/nuc1xx/nuc_idle.c
+++ b/arch/arm/src/nuc1xx/nuc_idle.c
@@ -99,7 +99,7 @@ static void up_idlepm(void)
 
       /* Perform board-specific, state-dependent logic here */
 
-      _llinfo("newstate= %d oldstate=%d\n", newstate, oldstate);
+      _info("newstate= %d oldstate=%d\n", newstate, oldstate);
 
       /* Then force the global state change */
 
diff --git a/arch/arm/src/nuc1xx/nuc_irq.c b/arch/arm/src/nuc1xx/nuc_irq.c
index ec045c3734e..66f6d78044d 100644
--- a/arch/arm/src/nuc1xx/nuc_irq.c
+++ b/arch/arm/src/nuc1xx/nuc_irq.c
@@ -128,7 +128,7 @@ static void nuc_dumpnvic(const char *msg, int irq)
 
 /****************************************************************************
  * Name: nuc_nmi, nuc_busfault, nuc_usagefault, nuc_pendsv,
- *       nuc_errmonitor, nuc_pendsv, nuc_reserved
+ *       nuc_dbgmonitor, nuc_pendsv, nuc_reserved
  *
  * Description:
  *   Handlers for various execptions.  None are handled and all are fatal
diff --git a/arch/arm/src/sam34/Kconfig b/arch/arm/src/sam34/Kconfig
index bc191c88df9..8e764dff40e 100644
--- a/arch/arm/src/sam34/Kconfig
+++ b/arch/arm/src/sam34/Kconfig
@@ -1369,7 +1369,7 @@ config SAM34_HSMCI_WRPROOF
 
 config SAM34_HSMCI_XFRDEBUG
 	bool "HSMCI transfer debug"
-	depends on DEBUG_FS && CONFIG_DEBUG_INFO
+	depends on DEBUG_FS_INFO
 	default n
 	---help---
 		Enable special debug instrumentation analyze HSMCI data transfers.
@@ -1381,7 +1381,7 @@ config SAM34_HSMCI_XFRDEBUG
 
 config SAM34_HSMCI_CMDDEBUG
 	bool "HSMCI command debug"
-	depends on DEBUG_FS && CONFIG_DEBUG_INFO
+	depends on DEBUG_FS_INFO
 	default n
 	---help---
 		Enable special debug instrumentation analyze HSMCI commands. This
diff --git a/arch/arm/src/sam34/sam4cm_oneshot.c b/arch/arm/src/sam34/sam4cm_oneshot.c
index 402166b2f7a..a7505b5a72e 100644
--- a/arch/arm/src/sam34/sam4cm_oneshot.c
+++ b/arch/arm/src/sam34/sam4cm_oneshot.c
@@ -91,7 +91,7 @@ static void sam_oneshot_handler(TC_HANDLE tch, void *arg, uint32_t sr)
   oneshot_handler_t oneshot_handler;
   void *oneshot_arg;
 
-  tmrllinfo("Expired...\n");
+  tmrinfo("Expired...\n");
   DEBUGASSERT(oneshot && oneshot->handler);
 
   /* The clock was stopped, but not disabled when the RC match occurred.
diff --git a/arch/arm/src/sam34/sam4cm_tickless.c b/arch/arm/src/sam34/sam4cm_tickless.c
index ed6b56dccd0..54b6c943af9 100644
--- a/arch/arm/src/sam34/sam4cm_tickless.c
+++ b/arch/arm/src/sam34/sam4cm_tickless.c
@@ -197,7 +197,7 @@ static struct sam_tickless_s g_tickless;
 
 static void sam_oneshot_handler(void *arg)
 {
-  tmrllinfo("Expired...\n");
+  tmrinfo("Expired...\n");
   sched_timer_expiration();
 }
 
@@ -244,7 +244,7 @@ void up_timer_initialize(void)
                                CONFIG_USEC_PER_TICK);
   if (ret < 0)
     {
-      tmrllerr("ERROR: sam_oneshot_initialize failed\n");
+      tmrerr("ERROR: sam_oneshot_initialize failed\n");
       PANIC();
     }
 
@@ -256,7 +256,7 @@ void up_timer_initialize(void)
   ret = sam_oneshot_max_delay(&g_tickless.oneshot, &max_delay);
   if (ret < 0)
     {
-      tmrllerr("ERROR: sam_oneshot_max_delay failed\n");
+      tmrerr("ERROR: sam_oneshot_max_delay failed\n");
       PANIC();
     }
 
@@ -280,7 +280,7 @@ void up_timer_initialize(void)
                                CONFIG_USEC_PER_TICK);
   if (ret < 0)
     {
-      tmrllerr("ERROR: sam_freerun_initialize failed\n");
+      tmrerr("ERROR: sam_freerun_initialize failed\n");
       PANIC();
     }
 
diff --git a/arch/arm/src/sam34/sam_dmac.c b/arch/arm/src/sam34/sam_dmac.c
index 01b7f65656a..7cf1cff3499 100644
--- a/arch/arm/src/sam34/sam_dmac.c
+++ b/arch/arm/src/sam34/sam_dmac.c
@@ -1354,7 +1354,7 @@ static int sam_dmainterrupt(int irq, void *context)
 
 void weak_function up_dmainitialize(void)
 {
-  dmallinfo("Initialize DMAC0\n");
+  dmainfo("Initialize DMAC0\n");
 
   /* Enable peripheral clock */
 
diff --git a/arch/arm/src/sam34/sam_emac.c b/arch/arm/src/sam34/sam_emac.c
index b1a665dd9ac..5e4e348f6c0 100644
--- a/arch/arm/src/sam34/sam_emac.c
+++ b/arch/arm/src/sam34/sam_emac.c
@@ -753,14 +753,14 @@ static int sam_transmit(struct sam_emac_s *priv)
   uint32_t regval;
   uint32_t status;
 
-  nllinfo("d_len: %d txhead: %d\n",  dev->d_len, priv->txhead);
+  ninfo("d_len: %d txhead: %d\n",  dev->d_len, priv->txhead);
   sam_dumppacket("Transmit packet", dev->d_buf, dev->d_len);
 
   /* Check parameter */
 
   if (dev->d_len > EMAC_TX_UNITSIZE)
     {
-      nllerr("ERROR: Packet too big: %d\n", dev->d_len);
+      nerr("ERROR: Packet too big: %d\n", dev->d_len);
       return -EINVAL;
     }
 
@@ -772,7 +772,7 @@ static int sam_transmit(struct sam_emac_s *priv)
 
   if (sam_txfree(priv) < 1)
     {
-      nllerr("ERROR: No free TX descriptors\n");
+      nerr("ERROR: No free TX descriptors\n");
       return -EBUSY;
     }
 
@@ -830,7 +830,7 @@ static int sam_transmit(struct sam_emac_s *priv)
 
   if (sam_txfree(priv) < 1)
     {
-      nllinfo("Disabling RX interrupts\n");
+      ninfo("Disabling RX interrupts\n");
       sam_putreg(priv, SAM_EMAC_IDR, EMAC_INT_RCOMP);
     }
 
@@ -1010,7 +1010,7 @@ static int sam_recvframe(struct sam_emac_s *priv)
   sam_cmcc_invalidate((uintptr_t)rxdesc,
                       (uintptr_t)rxdesc + sizeof(struct emac_rxdesc_s));
 
-  nllinfo("rxndx: %d\n", rxndx);
+  ninfo("rxndx: %d\n", rxndx);
 
   while ((rxdesc->addr & EMACRXD_ADDR_OWNER) != 0)
     {
@@ -1060,7 +1060,7 @@ static int sam_recvframe(struct sam_emac_s *priv)
         {
           if (rxndx == priv->rxndx)
             {
-              nllinfo("ERROR: No EOF (Invalid of buffers too small)\n");
+              nerr("ERROR: No EOF (Invalid of buffers too small)\n");
               do
                 {
                   /* Give ownership back to the EMAC */
@@ -1107,7 +1107,7 @@ static int sam_recvframe(struct sam_emac_s *priv)
               /* Frame size from the EMAC */
 
               dev->d_len = (rxdesc->status & EMACRXD_STA_FRLEN_MASK);
-              nllinfo("packet %d-%d (%d)\n", priv->rxndx, rxndx, dev->d_len);
+              ninfo("packet %d-%d (%d)\n", priv->rxndx, rxndx, dev->d_len);
 
               /* All data have been copied in the application frame buffer,
                * release the RX descriptor
@@ -1132,11 +1132,11 @@ static int sam_recvframe(struct sam_emac_s *priv)
                * all of the data.
                */
 
-              nllinfo("rxndx: %d d_len: %d\n", priv->rxndx, dev->d_len);
+              ninfo("rxndx: %d d_len: %d\n", priv->rxndx, dev->d_len);
 
               if (pktlen < dev->d_len)
                 {
-                  nllerr("ERROR: Buffer size %d; frame size %d\n", dev->d_len, pktlen);
+                  nerr("ERROR: Buffer size %d; frame size %d\n", dev->d_len, pktlen);
                   return -E2BIG;
                 }
 
@@ -1167,7 +1167,7 @@ static int sam_recvframe(struct sam_emac_s *priv)
   /* No packet was found */
 
   priv->rxndx = rxndx;
-  nllinfo("rxndx: %d\n", priv->rxndx);
+  ninfo("rxndx: %d\n", priv->rxndx);
   return -EAGAIN;
 }
 
@@ -1207,7 +1207,7 @@ static void sam_receive(struct sam_emac_s *priv)
 
       if (dev->d_len > CONFIG_NET_ETH_MTU)
         {
-          nllwarn("WARNING: Dropped, Too big: %d\n", dev->d_len);
+          nwarn("WARNING: Dropped, Too big: %d\n", dev->d_len);
           continue;
         }
 
@@ -1222,7 +1222,7 @@ static void sam_receive(struct sam_emac_s *priv)
 #ifdef CONFIG_NET_IPv4
       if (BUF->type == HTONS(ETHTYPE_IP))
         {
-          nllinfo("IPv4 frame\n");
+          ninfo("IPv4 frame\n");
 
           /* Handle ARP on input then give the IPv4 packet to the network
            * layer
@@ -1262,7 +1262,7 @@ static void sam_receive(struct sam_emac_s *priv)
 #ifdef CONFIG_NET_IPv6
       if (BUF->type == HTONS(ETHTYPE_IP6))
         {
-          nllinfo("Iv6 frame\n");
+          ninfo("Iv6 frame\n");
 
           /* Give the IPv6 packet to the network layer */
 
@@ -1299,7 +1299,7 @@ static void sam_receive(struct sam_emac_s *priv)
 #ifdef CONFIG_NET_ARP
       if (BUF->type == htons(ETHTYPE_ARP))
         {
-          nllinfo("ARP frame\n");
+          ninfo("ARP frame\n");
 
           /* Handle ARP packet */
 
@@ -1317,7 +1317,7 @@ static void sam_receive(struct sam_emac_s *priv)
       else
 #endif
         {
-          nllwarn("WARNING: Dropped, Unknown type: %04x\n", BUF->type);
+          nwarn("WARNING: Dropped, Unknown type: %04x\n", BUF->type);
         }
     }
 }
@@ -1442,7 +1442,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv)
   imr = sam_getreg(priv, SAM_EMAC_IMR);
 
   pending = isr & ~(imr | EMAC_INT_UNUSED);
-  nllinfo("isr: %08x pending: %08x\n", isr, pending);
+  ninfo("isr: %08x pending: %08x\n", isr, pending);
 
   /* Check for the completion of a transmission.  This should be done before
    * checking for received data (because receiving can cause another transmission
@@ -1468,7 +1468,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv)
           clrbits = EMAC_TSR_RLE | sam_txinuse(priv);
           sam_txreset(priv);
 
-          nllerr("ERROR: Retry Limit Exceeded TSR: %08x\n", tsr);
+          nerr("ERROR: Retry Limit Exceeded TSR: %08x\n", tsr);
 
           regval = sam_getreg(priv, SAM_EMAC_NCR);
           regval |= EMAC_NCR_TXEN;
@@ -1479,7 +1479,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv)
 
       if ((tsr & EMAC_TSR_COL) != 0)
         {
-          nllerr("ERROR: Collision occurred TSR: %08x\n", tsr);
+          nerr("ERROR: Collision occurred TSR: %08x\n", tsr);
           clrbits |= EMAC_TSR_COL;
         }
 
@@ -1487,7 +1487,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv)
 
       if ((tsr & EMAC_TSR_TFC) != 0)
         {
-          nllerr("ERROR: Transmit Frame Corruption due to AHB error: %08x\n", tsr);
+          nerr("ERROR: Transmit Frame Corruption due to AHB error: %08x\n", tsr);
           clrbits |= EMAC_TSR_TFC;
         }
 
@@ -1502,7 +1502,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv)
 
       if ((tsr & EMAC_TSR_UND) != 0)
         {
-          nllerr("ERROR: Transmit Underrun TSR: %08x\n", tsr);
+          nerr("ERROR: Transmit Underrun TSR: %08x\n", tsr);
           clrbits |= EMAC_TSR_UND;
         }
 
@@ -1539,7 +1539,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv)
 
       if ((rsr & EMAC_RSR_RXOVR) != 0)
         {
-          nllerr("ERROR: Receiver overrun RSR: %08x\n", rsr);
+          nerr("ERROR: Receiver overrun RSR: %08x\n", rsr);
           clrbits |= EMAC_RSR_RXOVR;
         }
 
@@ -1556,7 +1556,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv)
 
       if ((rsr & EMAC_RSR_BNA) != 0)
         {
-          nllerr("ERROR: Buffer not available RSR: %08x\n", rsr);
+          nerr("ERROR: Buffer not available RSR: %08x\n", rsr);
           clrbits |= EMAC_RSR_BNA;
         }
 
@@ -1578,7 +1578,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv)
 
   if ((pending & EMAC_INT_PFNZ) != 0)
     {
-      nllwarn("WARNING: Pause frame received\n");
+      nwarn("WARNING: Pause frame received\n");
     }
 
   /* Check for Pause Time Zero (PTZ)
@@ -1588,7 +1588,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv)
 
   if ((pending & EMAC_INT_PTZ) != 0)
     {
-      nllwarn("WARNING: Pause TO!\n");
+      nwarn("WARNING: Pause TO!\n");
     }
 #endif
 }
@@ -1725,7 +1725,7 @@ static int sam_emac_interrupt(int irq, void *context)
 
 static inline void sam_txtimeout_process(FAR struct sam_emac_s *priv)
 {
-  nllerr("ERROR: Timeout!\n");
+  nerr("ERROR: Timeout!\n");
 
   /* Then reset the hardware.  Just take the interface down, then back
    * up again.
diff --git a/arch/arm/src/sam34/sam_hsmci.c b/arch/arm/src/sam34/sam_hsmci.c
index e46ee1c3706..fa4073d6a27 100644
--- a/arch/arm/src/sam34/sam_hsmci.c
+++ b/arch/arm/src/sam34/sam_hsmci.c
@@ -1083,7 +1083,7 @@ static void sam_eventtimeout(int argc, uint32_t arg)
       /* Yes.. wake up any waiting threads */
 
       sam_endwait(priv, SDIOWAIT_TIMEOUT);
-      mcllerr("ERROR: Timeout\n");
+      mcerr("ERROR: Timeout\n");
     }
 }
 
@@ -1278,7 +1278,7 @@ static int sam_interrupt(int irq, void *context)
             {
               /* Yes.. Was it some kind of timeout error? */
 
-              mcllerr("ERROR: enabled: %08x pending: %08x\n", enabled, pending);
+              mcerr("ERROR: enabled: %08x pending: %08x\n", enabled, pending);
               if ((pending & HSMCI_DATA_TIMEOUT_ERRORS) != 0)
                 {
                   /* Yes.. Terminate with a timeout. */
@@ -1320,8 +1320,8 @@ static int sam_interrupt(int irq, void *context)
                 {
                   /* Yes.. Was the error some kind of timeout? */
 
-                  mcllinfo("ERROR: events: %08x SR: %08x\n",
-                          priv->cmdrmask, enabled);
+                  mcerr("ERROR: events: %08x SR: %08x\n",
+                        priv->cmdrmask, enabled);
 
                   if ((pending & HSMCI_RESPONSE_TIMEOUT_ERRORS) != 0)
                     {
@@ -2628,7 +2628,7 @@ static void sam_callback(void *arg)
         {
           /* Yes.. queue it */
 
-           mcllinfo("Queuing callback to %p(%p)\n", priv->callback, priv->cbarg);
+           mcinfo("Queuing callback to %p(%p)\n", priv->callback, priv->cbarg);
           (void)work_queue(LPWORK, &priv->cbwork, (worker_t)priv->callback, priv->cbarg, 0);
         }
       else
@@ -2743,7 +2743,7 @@ void sdio_mediachange(FAR struct sdio_dev_s *dev, bool cardinslot)
       priv->cdstatus &= ~SDIO_STATUS_PRESENT;
     }
 
-  mcllinfo("cdstatus OLD: %02x NEW: %02x\n", cdstatus, priv->cdstatus);
+  mcinfo("cdstatus OLD: %02x NEW: %02x\n", cdstatus, priv->cdstatus);
 
   /* Perform any requested callback if the status has changed */
 
diff --git a/arch/arm/src/sam34/sam_irq.c b/arch/arm/src/sam34/sam_irq.c
index 7e002224fb3..68f17774347 100644
--- a/arch/arm/src/sam34/sam_irq.c
+++ b/arch/arm/src/sam34/sam_irq.c
@@ -163,7 +163,7 @@ static void sam_dumpnvic(const char *msg, int irq)
 #endif
 
 /****************************************************************************
- * Name: sam_nmi, sam_busfault, sam_usagefault, sam_pendsv, sam_errmonitor,
+ * Name: sam_nmi, sam_busfault, sam_usagefault, sam_pendsv, sam_dbgmonitor,
  *       sam_pendsv, sam_reserved
  *
  * Description:
@@ -206,7 +206,7 @@ static int sam_pendsv(int irq, FAR void *context)
   return 0;
 }
 
-static int sam_errmonitor(int irq, FAR void *context)
+static int sam_dbgmonitor(int irq, FAR void *context)
 {
   (void)up_irq_save();
   _err("PANIC!!! Debug Monitor received\n");
@@ -466,7 +466,7 @@ void up_irqinitialize(void)
   irq_attach(SAM_IRQ_BUSFAULT, sam_busfault);
   irq_attach(SAM_IRQ_USAGEFAULT, sam_usagefault);
   irq_attach(SAM_IRQ_PENDSV, sam_pendsv);
-  irq_attach(SAM_IRQ_DBGMONITOR, sam_errmonitor);
+  irq_attach(SAM_IRQ_DBGMONITOR, sam_dbgmonitor);
   irq_attach(SAM_IRQ_RESERVED, sam_reserved);
 #endif
 
diff --git a/arch/arm/src/sam34/sam_rtc.c b/arch/arm/src/sam34/sam_rtc.c
index e6e5d0b6990..c4c548cc9f9 100644
--- a/arch/arm/src/sam34/sam_rtc.c
+++ b/arch/arm/src/sam34/sam_rtc.c
@@ -274,7 +274,7 @@ static int rtc_interrupt(int irq, void *context)
   ret = work_queue(LPWORK, &g_alarmwork, rtc_worker, NULL, 0);
   if (ret < 0)
     {
-      rtcllerr("ERROR: work_queue failed: %d\n", ret);
+      rtcerr("ERROR: work_queue failed: %d\n", ret);
     }
 
   /* Disable any further alarm interrupts */
diff --git a/arch/arm/src/sam34/sam_twi.c b/arch/arm/src/sam34/sam_twi.c
index af90936b1b9..6e4aae14271 100644
--- a/arch/arm/src/sam34/sam_twi.c
+++ b/arch/arm/src/sam34/sam_twi.c
@@ -390,9 +390,9 @@ static int twi_wait(struct twi_dev_s *priv)
 
   do
     {
-      i2cllinfo("TWI%d Waiting...\n", priv->twi);
+      i2cinfo("TWI%d Waiting...\n", priv->twi);
       twi_takesem(&priv->waitsem);
-      i2cllinfo("TWI%d Awakened with result: %d\n", priv->twi, priv->result);
+      i2cinfo("TWI%d Awakened with result: %d\n", priv->twi, priv->result);
     }
   while (priv->result == -EBUSY);
 
@@ -449,7 +449,7 @@ static int twi_interrupt(struct twi_dev_s *priv)
   imr     = twi_getrel(priv, SAM_TWI_IMR_OFFSET);
   pending = sr & imr;
 
-  i2cllinfo("TWI%d pending: %08x\n", priv->twi, pending);
+  i2cinfo("TWI%d pending: %08x\n", priv->twi, pending);
 
   msg = priv->msg;
 
@@ -459,7 +459,7 @@ static int twi_interrupt(struct twi_dev_s *priv)
     {
       /* Wake up the thread with an I/O error indication */
 
-      i2cllerr("ERROR: TWI%d pending: %08x\n", priv->twi, pending);
+      i2cerr("ERROR: TWI%d pending: %08x\n", priv->twi, pending);
       twi_wakeup(priv, -EIO);
     }
 
@@ -582,7 +582,7 @@ static void twi_timeout(int argc, uint32_t arg, ...)
 {
   struct twi_dev_s *priv = (struct twi_dev_s *)arg;
 
-  i2cllerr("ERROR: TWI%d Timeout!\n", priv->twi);
+  i2cerr("ERROR: TWI%d Timeout!\n", priv->twi);
   twi_wakeup(priv, -ETIMEDOUT);
 }
 
diff --git a/arch/arm/src/sam34/sam_udp.c b/arch/arm/src/sam34/sam_udp.c
index 8c84fce2f88..6fe76f4f57b 100644
--- a/arch/arm/src/sam34/sam_udp.c
+++ b/arch/arm/src/sam34/sam_udp.c
@@ -606,7 +606,7 @@ const struct trace_msg_t g_usb_trace_strings_intdecode[] =
 #ifdef CONFIG_SAM34_UDP_REGDEBUG
 static void sam_printreg(uintptr_t regaddr, uint32_t regval, bool iswrite)
 {
-  _llinfo("%p%s%08x\n", regaddr, iswrite ? "<-" : "->", regval);
+  _info("%p%s%08x\n", regaddr, iswrite ? "<-" : "->", regval);
 }
 #endif
 
@@ -657,7 +657,7 @@ static void sam_checkreg(uintptr_t regaddr, uint32_t regval, bool iswrite)
             {
               /* No.. More than one. */
 
-              _llinfo("[repeats %d more times]\n", count);
+              _info("[repeats %d more times]\n", count);
             }
         }
 
@@ -737,15 +737,15 @@ static void sam_dumpep(struct sam_usbdev_s *priv, uint8_t epno)
 {
   /* Global Registers */
 
-  _llinfo("Global Registers:\n");
-  _llinfo(" FRMNUM:    %08x\n", sam_getreg(SAM_UDP_FRMNUM));
-  _llinfo("GLBSTAT:    %08x\n", sam_getreg(SAM_UDP_GLBSTAT));
-  _llinfo("  FADDR:    %08x\n", sam_getreg(SAM_UDP_FADDR));
-  _llinfo("    IMR:    %08x\n", sam_getreg(SAM_UDP_IMR));
-  _llinfo("    ISR:    %08x\n", sam_getreg(SAM_UDP_ISR));
-  _llinfo("  RSTEP:    %08x\n", sam_getreg(SAM_UDP_RSTEP));
-  _llinfo("   TXVC:    %08x\n", sam_getreg(SAM_UDP_TXVC));
-  _llinfo(" CSR[%d]:    %08x\n", epno, sam_getreg(SAM_UDPEP_CSR(epno)));
+  _info("Global Registers:\n");
+  _info(" FRMNUM:    %08x\n", sam_getreg(SAM_UDP_FRMNUM));
+  _info("GLBSTAT:    %08x\n", sam_getreg(SAM_UDP_GLBSTAT));
+  _info("  FADDR:    %08x\n", sam_getreg(SAM_UDP_FADDR));
+  _info("    IMR:    %08x\n", sam_getreg(SAM_UDP_IMR));
+  _info("    ISR:    %08x\n", sam_getreg(SAM_UDP_ISR));
+  _info("  RSTEP:    %08x\n", sam_getreg(SAM_UDP_RSTEP));
+  _info("   TXVC:    %08x\n", sam_getreg(SAM_UDP_TXVC));
+  _info(" CSR[%d]:    %08x\n", epno, sam_getreg(SAM_UDPEP_CSR(epno)));
 }
 #endif
 
@@ -968,9 +968,9 @@ static int sam_req_write(struct sam_usbdev_s *priv, struct sam_ep_s *privep)
           return -ENOENT;
         }
 
-      ullinfo("epno=%d req=%p: len=%d xfrd=%d inflight=%d zlpneeded=%d\n",
-              epno, privreq, privreq->req.len, privreq->req.xfrd,
-              privreq->inflight, privep->zlpneeded);
+      uinfo("epno=%d req=%p: len=%d xfrd=%d inflight=%d zlpneeded=%d\n",
+            epno, privreq, privreq->req.len, privreq->req.xfrd,
+            privreq->inflight, privep->zlpneeded);
 
       /* Handle any bytes in flight. */
 
@@ -1139,8 +1139,8 @@ static int sam_req_read(struct sam_usbdev_s *priv, struct sam_ep_s *privep,
           return -ENOENT;
         }
 
-      ullinfo("EP%d: len=%d xfrd=%d\n",
-              epno, privreq->req.len, privreq->req.xfrd);
+      uinfo("EP%d: len=%d xfrd=%d\n",
+            epno, privreq->req.len, privreq->req.xfrd);
 
       /* Ignore any attempt to receive a zero length packet */
 
@@ -1408,8 +1408,8 @@ static void sam_ep0_setup(struct sam_usbdev_s *priv)
   index.w = GETUINT16(priv->ctrl.index);
   len.w   = GETUINT16(priv->ctrl.len);
 
-  ullinfo("SETUP: type=%02x req=%02x value=%04x index=%04x len=%04x\n",
-          priv->ctrl.type, priv->ctrl.req, value.w, index.w, len.w);
+  uinfo("SETUP: type=%02x req=%02x value=%04x index=%04x len=%04x\n",
+        priv->ctrl.type, priv->ctrl.req, value.w, index.w, len.w);
 
   /* Dispatch any non-standard requests */
 
@@ -1572,7 +1572,7 @@ static void sam_ep0_setup(struct sam_usbdev_s *priv)
           {
             /* Special case recipient=device test mode */
 
-            ullinfo("test mode: %d\n", index.w);
+            uinfo("test mode: %d\n", index.w);
           }
         else if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) != USB_REQ_RECIPIENT_ENDPOINT)
           {
@@ -2946,7 +2946,7 @@ static int sam_ep_disable(struct usbdev_ep_s *ep)
   if (!ep)
     {
       usbtrace(TRACE_DEVERROR(SAM_TRACEERR_INVALIDPARMS), 0);
-      ullerr("ERROR: ep=%p\n", ep);
+      uerr("ERROR: ep=%p\n", ep);
       return -EINVAL;
     }
 #endif
@@ -3079,7 +3079,8 @@ static int sam_ep_submit(struct usbdev_ep_s *ep, struct usbdev_req_s *req)
   if (!req || !req->callback || !req->buf || !ep)
     {
       usbtrace(TRACE_DEVERROR(SAM_TRACEERR_INVALIDPARMS), 0);
-      ullerr("ERROR: req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, ep);
+      uerr("ERROR: req=%p callback=%p buf=%p ep=%p\n",
+           req, req->callback, req->buf, ep);
       return -EINVAL;
     }
 #endif
@@ -3091,7 +3092,7 @@ static int sam_ep_submit(struct usbdev_ep_s *ep, struct usbdev_req_s *req)
   if (!priv->driver)
     {
       usbtrace(TRACE_DEVERROR(SAM_TRACEERR_NOTCONFIGURED), priv->usbdev.speed);
-      ullerr("ERROR: driver=%p\n", priv->driver);
+      uerr("ERROR: driver=%p\n", priv->driver);
       return -ESHUTDOWN;
     }
 #endif
@@ -3119,7 +3120,7 @@ static int sam_ep_submit(struct usbdev_ep_s *ep, struct usbdev_req_s *req)
            * queue. They will stay queuee until the stall is cleared.
            */
 
-          ullinfo("Pending stall clear\n");
+          uinfo("Pending stall clear\n");
           sam_req_enqueue(&privep->pendq, privreq);
           usbtrace(TRACE_INREQQUEUED(epno), req->len);
           ret = OK;
diff --git a/arch/arm/src/sama5/Kconfig b/arch/arm/src/sama5/Kconfig
index 4f7b2371dbb..11aa7179f1f 100644
--- a/arch/arm/src/sama5/Kconfig
+++ b/arch/arm/src/sama5/Kconfig
@@ -2857,7 +2857,7 @@ config SAMA5_HSMCI_WRPROOF
 
 config SAMA5_HSMCI_XFRDEBUG
 	bool "HSMCI transfer debug"
-	depends on DEBUG_FS && CONFIG_DEBUG_INFO
+	depends on DEBUG_FS_INFO
 	default n
 	---help---
 		Enable special debug instrumentation analyze HSMCI data transfers.
@@ -2869,7 +2869,7 @@ config SAMA5_HSMCI_XFRDEBUG
 
 config SAMA5_HSMCI_CMDDEBUG
 	bool "HSMCI command debug"
-	depends on DEBUG_FS && CONFIG_DEBUG_INFO
+	depends on DEBUG_FS_INFO
 	default n
 	---help---
 		Enable special debug instrumentation analyze HSMCI commands. This
diff --git a/arch/arm/src/sama5/sam_adc.c b/arch/arm/src/sama5/sam_adc.c
index ad276ff947a..dcf82b1f6d9 100644
--- a/arch/arm/src/sama5/sam_adc.c
+++ b/arch/arm/src/sama5/sam_adc.c
@@ -729,7 +729,7 @@ static void sam_adc_dmacallback(DMA_HANDLE handle, void *arg, int result)
   struct sam_adc_s *priv = (struct sam_adc_s *)arg;
   int ret;
 
-  allinfo("ready=%d enabled=%d\n", priv->enabled, priv->ready);
+  ainfo("ready=%d enabled=%d\n", priv->enabled, priv->ready);
   DEBUGASSERT(priv->ready);
 
   /* Check of the bottom half is keeping up with us.
@@ -755,7 +755,7 @@ static void sam_adc_dmacallback(DMA_HANDLE handle, void *arg, int result)
       ret = work_queue(HPWORK, &priv->work, sam_adc_dmadone, priv, 0);
       if (ret != 0)
         {
-          allerr("ERROR: Failed to queue work: %d\n", ret);
+          aerr("ERROR: Failed to queue work: %d\n", ret);
         }
     }
 
@@ -961,7 +961,7 @@ static int sam_adc_interrupt(int irq, void *context)
       ret = work_queue(HPWORK, &priv->work, sam_adc_endconversion, priv, 0);
       if (ret != 0)
         {
-          allerr("ERROR: Failed to queue work: %d\n", ret);
+          aerr("ERROR: Failed to queue work: %d\n", ret);
         }
 
       pending &= ~ADC_INT_EOCALL;
diff --git a/arch/arm/src/sama5/sam_can.c b/arch/arm/src/sama5/sam_can.c
index 10bb9a4d330..3e1b3d116a1 100644
--- a/arch/arm/src/sama5/sam_can.c
+++ b/arch/arm/src/sama5/sam_can.c
@@ -783,7 +783,7 @@ static void can_reset(FAR struct can_dev_s *dev)
   config = priv->config;
   DEBUGASSERT(config);
 
-  canllinfo("CAN%d\n", config->port);
+  caninfo("CAN%d\n", config->port);
   UNUSED(config);
 
   /* Get exclusive access to the CAN peripheral */
@@ -840,7 +840,7 @@ static int can_setup(FAR struct can_dev_s *dev)
   config = priv->config;
   DEBUGASSERT(config);
 
-  canllinfo("CAN%d pid: %d\n", config->port, config->pid);
+  caninfo("CAN%d pid: %d\n", config->port, config->pid);
 
   /* Get exclusive access to the CAN peripheral */
 
@@ -851,7 +851,7 @@ static int can_setup(FAR struct can_dev_s *dev)
   ret = can_hwinitialize(priv);
   if (ret < 0)
     {
-      canllerr("ERROR: CAN%d H/W initialization failed: %d\n", config->port, ret);
+      canerr("ERROR: CAN%d H/W initialization failed: %d\n", config->port, ret);
       return ret;
     }
 
@@ -863,7 +863,7 @@ static int can_setup(FAR struct can_dev_s *dev)
   ret = irq_attach(config->pid, config->handler);
   if (ret < 0)
     {
-      canllerr("ERROR: Failed to attach CAN%d IRQ (%d)", config->port, config->pid);
+      canerr("ERROR: Failed to attach CAN%d IRQ (%d)", config->port, config->pid);
       return ret;
     }
 
@@ -872,7 +872,7 @@ static int can_setup(FAR struct can_dev_s *dev)
   ret = can_recvsetup(priv);
   if (ret < 0)
     {
-      canllerr("ERROR: CAN%d H/W initialization failed: %d\n", config->port, ret);
+      canerr("ERROR: CAN%d H/W initialization failed: %d\n", config->port, ret);
       return ret;
     }
 
@@ -918,7 +918,7 @@ static void can_shutdown(FAR struct can_dev_s *dev)
   config = priv->config;
   DEBUGASSERT(config);
 
-  canllinfo("CAN%d\n", config->port);
+  caninfo("CAN%d\n", config->port);
 
   /* Get exclusive access to the CAN peripheral */
 
@@ -957,7 +957,7 @@ static void can_rxint(FAR struct can_dev_s *dev, bool enable)
   FAR struct sam_can_s *priv = dev->cd_priv;
   DEBUGASSERT(priv && priv->config);
 
-  canllinfo("CAN%d enable: %d\n", priv->config->port, enable);
+  caninfo("CAN%d enable: %d\n", priv->config->port, enable);
 
   /* Enable/disable the mailbox interrupts from all receive mailboxes */
 
@@ -990,7 +990,7 @@ static void can_txint(FAR struct can_dev_s *dev, bool enable)
   FAR struct sam_can_s *priv = dev->cd_priv;
   DEBUGASSERT(priv && priv->config);
 
-  canllinfo("CAN%d enable: %d\n", priv->config->port, enable);
+  caninfo("CAN%d enable: %d\n", priv->config->port, enable);
 
   /* Get exclusive access to the CAN peripheral */
 
@@ -1091,9 +1091,9 @@ static int can_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg)
   priv = dev->cd_priv;
   DEBUGASSERT(priv && priv->config);
 
-  canllinfo("CAN%d\n", priv->config->port);
-  canllinfo("CAN%d ID: %d DLC: %d\n",
-            priv->config->port, msg->cm_hdr.ch_id, msg->cm_hdr.ch_dlc);
+  caninfo("CAN%d\n", priv->config->port);
+  caninfo("CAN%d ID: %d DLC: %d\n",
+          priv->config->port, msg->cm_hdr.ch_id, msg->cm_hdr.ch_dlc);
 
   /* Get exclusive access to the CAN peripheral */
 
@@ -1327,7 +1327,7 @@ static inline void can_rxinterrupt(FAR struct can_dev_s *dev, int mbndx,
   ret = can_receive(dev, &hdr, (FAR uint8_t *)md);
   if (ret < 0)
     {
-      canllerr("ERROR: can_receive failed: %d\n", ret);
+      canerr("ERROR: can_receive failed: %d\n", ret);
     }
 
   /* Set the MTCR flag in the CAN_MCRx register.  This clears the
@@ -1422,9 +1422,9 @@ static inline void can_mbinterrupt(FAR struct can_dev_s *dev, int mbndx)
           case CAN_MMR_MOT_CONSUMER: /* Consumer Mailbox */
           case CAN_MMR_MOT_PRODUCER: /* Producer Mailbox */
           case CAN_MMR_MOT_DISABLED: /* Mailbox is disabled */
-            canllerr("ERROR: CAN%d MB%d: Unsupported or invalid mailbox type\n",
-                     priv->config->port, mbndx);
-            canllerr("       MSR: %08x MMR: %08x\n", msr, mmr);
+            canerr("ERROR: CAN%d MB%d: Unsupported or invalid mailbox type\n",
+                   priv->config->port, mbndx);
+            canerr("       MSR: %08x MMR: %08x\n", msr, mmr);
             break;
         }
     }
@@ -1515,8 +1515,8 @@ static void can_interrupt(FAR struct can_dev_s *dev)
 
   if ((pending & ~CAN_INT_MBALL) != 0)
     {
-      canllerr("ERROR: CAN%d system interrupt, SR=%08x IMR=%08x\n",
-               priv->config->port, sr, imr);
+      canerr("ERROR: CAN%d system interrupt, SR=%08x IMR=%08x\n",
+             priv->config->port, sr, imr);
     }
 }
 
@@ -1773,7 +1773,7 @@ static int can_autobaud(struct sam_can_s *priv)
   uint32_t regval;
   int ret;
 
-  canllinfo("CAN%d\n", config->port);
+  caninfo("CAN%d\n", config->port);
 
   /* The CAN controller can start listening to the network in Autobaud Mode.
    * In this case, the error counters are locked and a mailbox may be
@@ -1843,7 +1843,7 @@ static int can_hwinitialize(struct sam_can_s *priv)
   uint32_t mck;
   int ret;
 
-  canllinfo("CAN%d\n", config->port);
+  caninfo("CAN%d\n", config->port);
 
   /* Configure CAN pins */
 
diff --git a/arch/arm/src/sama5/sam_dmac.c b/arch/arm/src/sama5/sam_dmac.c
index 74bbd3f533e..e3a813c1b21 100644
--- a/arch/arm/src/sama5/sam_dmac.c
+++ b/arch/arm/src/sama5/sam_dmac.c
@@ -1818,7 +1818,7 @@ static int sam_dmac_interrupt(struct sam_dmac_s *dmac)
                 {
                    /* Yes... Terminate the transfer with an error? */
 
-                   dmallerr("ERROR: DMA failed: %08x\n", regval);
+                   dmaerr("ERROR: DMA failed: %08x\n", regval);
                    sam_dmaterminate(dmach, -EIO);
                 }
 
@@ -1920,7 +1920,7 @@ void sam_dmainitialize(struct sam_dmac_s *dmac)
 void weak_function up_dmainitialize(void)
 {
 #ifdef CONFIG_SAMA5_DMAC0
-  dmallinfo("Initialize DMAC0\n");
+  dmainfo("Initialize DMAC0\n");
 
   /* Enable peripheral clock */
 
@@ -1940,7 +1940,7 @@ void weak_function up_dmainitialize(void)
 #endif
 
 #ifdef CONFIG_SAMA5_DMAC1
-  dmallinfo("Initialize DMAC1\n");
+  dmainfo("Initialize DMAC1\n");
 
   /* Enable peripheral clock */
 
diff --git a/arch/arm/src/sama5/sam_ehci.c b/arch/arm/src/sama5/sam_ehci.c
index cdd86c208b7..78135e3e8da 100644
--- a/arch/arm/src/sama5/sam_ehci.c
+++ b/arch/arm/src/sama5/sam_ehci.c
@@ -3180,7 +3180,7 @@ static int sam_ehci_tophalf(int irq, FAR void *context)
 #ifdef CONFIG_USBHOST_TRACE
   usbhost_vtrace1(EHCI_VTRACE1_TOPHALF, usbsts & regval);
 #else
-  ullinfo("USBSTS: %08x USBINTR: %08x\n", usbsts, regval);
+  uinfo("USBSTS: %08x USBINTR: %08x\n", usbsts, regval);
 #endif
 
   /* Handle all unmasked interrupt sources */
@@ -4493,7 +4493,7 @@ static int sam_connect(FAR struct usbhost_driver_s *drvr,
   /* Set the connected/disconnected flag */
 
   hport->connected = connected;
-  ullinfo("Hub port %d connected: %s\n", hport->port, connected ? "YES" : "NO");
+  uinfo("Hub port %d connected: %s\n", hport->port, connected ? "YES" : "NO");
 
   /* Report the connection event */
 
diff --git a/arch/arm/src/sama5/sam_emaca.c b/arch/arm/src/sama5/sam_emaca.c
index 553d15f51b9..3972f2324ac 100644
--- a/arch/arm/src/sama5/sam_emaca.c
+++ b/arch/arm/src/sama5/sam_emaca.c
@@ -607,7 +607,7 @@ static int sam_buffer_initialize(struct sam_emac_s *priv)
   priv->txdesc = (struct emac_txdesc_s *)kmm_memalign(8, allocsize);
   if (!priv->txdesc)
     {
-      nllerr("ERROR: Failed to allocate TX descriptors\n");
+      nerr("ERROR: Failed to allocate TX descriptors\n");
       return -ENOMEM;
     }
 
@@ -617,7 +617,7 @@ static int sam_buffer_initialize(struct sam_emac_s *priv)
   priv->rxdesc = (struct emac_rxdesc_s *)kmm_memalign(8, allocsize);
   if (!priv->rxdesc)
     {
-      nllerr("ERROR: Failed to allocate RX descriptors\n");
+      nerr("ERROR: Failed to allocate RX descriptors\n");
       sam_buffer_free(priv);
       return -ENOMEM;
     }
@@ -628,7 +628,7 @@ static int sam_buffer_initialize(struct sam_emac_s *priv)
   priv->txbuffer = (uint8_t *)kmm_memalign(8, allocsize);
   if (!priv->txbuffer)
     {
-      nllerr("ERROR: Failed to allocate TX buffer\n");
+      nerr("ERROR: Failed to allocate TX buffer\n");
       sam_buffer_free(priv);
       return -ENOMEM;
     }
@@ -637,7 +637,7 @@ static int sam_buffer_initialize(struct sam_emac_s *priv)
   priv->rxbuffer = (uint8_t *)kmm_memalign(8, allocsize);
   if (!priv->rxbuffer)
     {
-      nllerr("ERROR: Failed to allocate RX buffer\n");
+      nerr("ERROR: Failed to allocate RX buffer\n");
       sam_buffer_free(priv);
       return -ENOMEM;
     }
@@ -725,14 +725,14 @@ static int sam_transmit(struct sam_emac_s *priv)
   uint32_t regval;
   uint32_t status;
 
-  nllinfo("d_len: %d txhead: %d\n",  dev->d_len, priv->txhead);
+  ninfo("d_len: %d txhead: %d\n",  dev->d_len, priv->txhead);
   sam_dumppacket("Transmit packet", dev->d_buf, dev->d_len);
 
   /* Check parameter */
 
   if (dev->d_len > EMAC_TX_UNITSIZE)
     {
-      nllerr("ERROR: Packet too big: %d\n", dev->d_len);
+      nerr("ERROR: Packet too big: %d\n", dev->d_len);
       return -EINVAL;
     }
 
@@ -744,7 +744,7 @@ static int sam_transmit(struct sam_emac_s *priv)
 
   if (sam_txfree(priv) < 1)
     {
-      nllerr("ERROR: No free TX descriptors\n");
+      nerr("ERROR: No free TX descriptors\n");
       return -EBUSY;
     }
 
@@ -806,7 +806,7 @@ static int sam_transmit(struct sam_emac_s *priv)
 
   if (sam_txfree(priv) < 1)
     {
-      nllinfo("Disabling RX interrupts\n");
+      ninfo("Disabling RX interrupts\n");
       sam_putreg(priv, SAM_EMAC_IDR, EMAC_INT_RCOMP);
     }
 
@@ -986,7 +986,7 @@ static int sam_recvframe(struct sam_emac_s *priv)
   arch_invalidate_dcache((uintptr_t)rxdesc,
                          (uintptr_t)rxdesc + sizeof(struct emac_rxdesc_s));
 
-  nllinfo("rxndx: %d\n", rxndx);
+  ninfo("rxndx: %d\n", rxndx);
 
   while ((rxdesc->addr & EMACRXD_ADDR_OWNER) != 0)
     {
@@ -1042,7 +1042,7 @@ static int sam_recvframe(struct sam_emac_s *priv)
         {
           if (rxndx == priv->rxndx)
             {
-              nllinfo("ERROR: No EOF (Invalid of buffers too small)\n");
+              nerr("ERROR: No EOF (Invalid of buffers too small)\n");
               do
                 {
                   /* Give ownership back to the EMAC */
@@ -1097,7 +1097,7 @@ static int sam_recvframe(struct sam_emac_s *priv)
               /* Frame size from the EMAC */
 
               dev->d_len = (rxdesc->status & EMACRXD_STA_FRLEN_MASK);
-              nllinfo("packet %d-%d (%d)\n", priv->rxndx, rxndx, dev->d_len);
+              ninfo("packet %d-%d (%d)\n", priv->rxndx, rxndx, dev->d_len);
 
               /* All data have been copied in the application frame buffer,
                * release the RX descriptor
@@ -1128,11 +1128,11 @@ static int sam_recvframe(struct sam_emac_s *priv)
                * all of the data.
                */
 
-              nllinfo("rxndx: %d d_len: %d\n", priv->rxndx, dev->d_len);
+              ninfo("rxndx: %d d_len: %d\n", priv->rxndx, dev->d_len);
 
               if (pktlen < dev->d_len)
                 {
-                  nllerr("ERROR: Buffer size %d; frame size %d\n", dev->d_len, pktlen);
+                  nerr("ERROR: Buffer size %d; frame size %d\n", dev->d_len, pktlen);
                   return -E2BIG;
                 }
 
@@ -1172,7 +1172,7 @@ static int sam_recvframe(struct sam_emac_s *priv)
   /* No packet was found */
 
   priv->rxndx = rxndx;
-  nllinfo("rxndx: %d\n", priv->rxndx);
+  ninfo("rxndx: %d\n", priv->rxndx);
   return -EAGAIN;
 }
 
@@ -1212,7 +1212,7 @@ static void sam_receive(struct sam_emac_s *priv)
 
       if (dev->d_len > CONFIG_NET_ETH_MTU)
         {
-          nllwarn("WARNING: Dropped, Too big: %d\n", dev->d_len);
+          nwarn("WARNING: Dropped, Too big: %d\n", dev->d_len);
           continue;
         }
 
@@ -1227,7 +1227,7 @@ static void sam_receive(struct sam_emac_s *priv)
 #ifdef CONFIG_NET_IPv4
       if (BUF->type == HTONS(ETHTYPE_IP))
         {
-          nllinfo("IPv4 frame\n");
+          ninfo("IPv4 frame\n");
 
           /* Handle ARP on input then give the IPv4 packet to the network
            * layer
@@ -1267,7 +1267,7 @@ static void sam_receive(struct sam_emac_s *priv)
 #ifdef CONFIG_NET_IPv6
       if (BUF->type == HTONS(ETHTYPE_IP6))
         {
-          nllinfo("Iv6 frame\n");
+          ninfo("Iv6 frame\n");
 
           /* Give the IPv6 packet to the network layer */
 
@@ -1304,7 +1304,7 @@ static void sam_receive(struct sam_emac_s *priv)
 #ifdef CONFIG_NET_ARP
       if (BUF->type == htons(ETHTYPE_ARP))
         {
-          nllinfo("ARP frame\n");
+          ninfo("ARP frame\n");
 
           /* Handle ARP packet */
 
@@ -1322,7 +1322,7 @@ static void sam_receive(struct sam_emac_s *priv)
       else
 #endif
         {
-          nllwarn("WARNING: Dropped, Unknown type: %04x\n", BUF->type);
+          nwarn("WARNING: Dropped, Unknown type: %04x\n", BUF->type);
         }
     }
 }
@@ -1449,7 +1449,7 @@ static int sam_emac_interrupt(int irq, void *context)
   imr = sam_getreg(priv, SAM_EMAC_IMR);
 
   pending = isr & ~(imr | EMAC_INT_UNUSED);
-  nllinfo("isr: %08x pending: %08x\n", isr, pending);
+  ninfo("isr: %08x pending: %08x\n", isr, pending);
 
   /* Check for the completion of a transmission.  This should be done before
    * checking for received data (because receiving can cause another transmission
@@ -1475,7 +1475,7 @@ static int sam_emac_interrupt(int irq, void *context)
           clrbits = EMAC_TSR_RLES | sam_txinuse(priv);
           sam_txreset(priv);
 
-          nllerr("ERROR: Retry Limit Exceeded TSR: %08x\n", tsr);
+          nerr("ERROR: Retry Limit Exceeded TSR: %08x\n", tsr);
 
           regval = sam_getreg(priv, SAM_EMAC_NCR);
           regval |= EMAC_NCR_TE;
@@ -1486,7 +1486,7 @@ static int sam_emac_interrupt(int irq, void *context)
 
       if ((tsr & EMAC_TSR_COL) != 0)
         {
-          nllerr("ERROR: Collision occurred TSR: %08x\n", tsr);
+          nerr("ERROR: Collision occurred TSR: %08x\n", tsr);
           clrbits |= EMAC_TSR_COL;
         }
 
@@ -1494,7 +1494,7 @@ static int sam_emac_interrupt(int irq, void *context)
 
       if ((tsr & EMAC_TSR_BEX) != 0)
         {
-          nllerr("ERROR: Buffers exhausted mid-frame TSR: %08x\n", tsr);
+          nerr("ERROR: Buffers exhausted mid-frame TSR: %08x\n", tsr);
           clrbits |= EMAC_TSR_BEX;
         }
 
@@ -1509,7 +1509,7 @@ static int sam_emac_interrupt(int irq, void *context)
 
       if ((tsr & EMAC_TSR_UND) != 0)
         {
-          nllerr("ERROR: Transmit Underrun TSR: %08x\n", tsr);
+          nerr("ERROR: Transmit Underrun TSR: %08x\n", tsr);
           clrbits |= EMAC_TSR_UND;
         }
 
@@ -1546,7 +1546,7 @@ static int sam_emac_interrupt(int irq, void *context)
 
       if ((rsr & EMAC_RSR_OVR) != 0)
         {
-          nllerr("ERROR: Receiver overrun RSR: %08x\n", rsr);
+          nerr("ERROR: Receiver overrun RSR: %08x\n", rsr);
           clrbits |= EMAC_RSR_OVR;
         }
 
@@ -1563,7 +1563,7 @@ static int sam_emac_interrupt(int irq, void *context)
 
       if ((rsr & EMAC_RSR_BNA) != 0)
         {
-          nllerr("ERROR: Buffer not available RSR: %08x\n", rsr);
+          nerr("ERROR: Buffer not available RSR: %08x\n", rsr);
           clrbits |= EMAC_RSR_BNA;
         }
 
@@ -1584,7 +1584,7 @@ static int sam_emac_interrupt(int irq, void *context)
 
   if ((pending & EMAC_INT_PFR) != 0)
     {
-      nllwarn("WARNING: Pause frame received\n");
+      nwarn("WARNING: Pause frame received\n");
     }
 
   /* Check for Pause Time Zero (PTZ)
@@ -1594,7 +1594,7 @@ static int sam_emac_interrupt(int irq, void *context)
 
   if ((pending & EMAC_INT_PTZ) != 0)
     {
-      nllwarn("WARNING: Pause TO!\n");
+      nwarn("WARNING: Pause TO!\n");
     }
 #endif
 
@@ -1624,7 +1624,7 @@ static void sam_txtimeout(int argc, uint32_t arg, ...)
 {
   struct sam_emac_s *priv = (struct sam_emac_s *)arg;
 
-  nllerr("ERROR: Timeout!\n");
+  nerr("ERROR: Timeout!\n");
 
   /* Then reset the hardware.  Just take the interface down, then back
    * up again.
@@ -1705,7 +1705,7 @@ static int sam_ifup(struct net_driver_s *dev)
 
   /* Configure the EMAC interface for normal operation. */
 
-  nllinfo("Initialize the EMAC\n");
+  ninfo("Initialize the EMAC\n");
   sam_emac_configure(priv);
 
   /* Set the MAC address (should have been configured while we were down) */
@@ -1723,7 +1723,7 @@ static int sam_ifup(struct net_driver_s *dev)
   ret = sam_phyinit(priv);
   if (ret < 0)
     {
-      nllerr("ERROR: sam_phyinit failed: %d\n", ret);
+      nerr("ERROR: sam_phyinit failed: %d\n", ret);
       return ret;
     }
 
@@ -1732,16 +1732,16 @@ static int sam_ifup(struct net_driver_s *dev)
   ret = sam_autonegotiate(priv);
   if (ret < 0)
     {
-      nllerr("ERROR: sam_autonegotiate failed: %d\n", ret);
+      nerr("ERROR: sam_autonegotiate failed: %d\n", ret);
       return ret;
     }
 
   while (sam_linkup(priv) == 0);
-  nllinfo("Link detected \n");
+  ninfo("Link detected \n");
 
   /* Enable normal MAC operation */
 
-  nllinfo("Enable normal operation\n");
+  ninfo("Enable normal operation\n");
 
   /* Set and activate a timer process */
 
@@ -1825,7 +1825,7 @@ static int sam_txavail(struct net_driver_s *dev)
   struct sam_emac_s *priv = (struct sam_emac_s *)dev->d_private;
   irqstate_t flags;
 
-  nllinfo("ifup: %d\n", priv->ifup);
+  ninfo("ifup: %d\n", priv->ifup);
 
   /* Disable interrupts because this function may be called from interrupt
    * level processing.
@@ -2003,8 +2003,8 @@ static int sam_addmac(struct net_driver_s *dev, const uint8_t *mac)
   unsigned int bit;
   UNUSED(priv);
 
-  nllinfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
-          mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+  ninfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
+        mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
 
   /* Calculate the 6-bit has table index */
 
@@ -2077,8 +2077,8 @@ static int sam_rmmac(struct net_driver_s *dev, const uint8_t *mac)
   unsigned int bit;
   UNUSED(priv);
 
-  nllinfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
-          mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+  ninfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
+        mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
 
   /* Calculate the 6-bit has table index */
 
@@ -2273,21 +2273,21 @@ static void sam_phydump(struct sam_emac_s *priv)
   sam_putreg(priv, SAM_EMAC_NCR, regval);
 
 #ifdef CONFIG_SAMA5_EMAC_RMII
-  nllinfo("RMII Registers (Address %02x)\n", priv->phyaddr);
+  ninfo("RMII Registers (Address %02x)\n", priv->phyaddr);
 #else /* defined(CONFIG_SAMA5_EMAC_MII) */
-  nllinfo("MII Registers (Address %02x)\n", priv->phyaddr);
+  ninfo("MII Registers (Address %02x)\n", priv->phyaddr);
 #endif
 
   sam_phyread(priv, priv->phyaddr, MII_MCR, &phyval);
-  nllinfo("  MCR:       %04x\n", phyval);
+  ninfo("  MCR:       %04x\n", phyval);
   sam_phyread(priv, priv->phyaddr, MII_MSR, &phyval);
-  nllinfo("  MSR:       %04x\n", phyval);
+  ninfo("  MSR:       %04x\n", phyval);
   sam_phyread(priv, priv->phyaddr, MII_ADVERTISE, &phyval);
-  nllinfo("  ADVERTISE: %04x\n", phyval);
+  ninfo("  ADVERTISE: %04x\n", phyval);
   sam_phyread(priv, priv->phyaddr, MII_LPA, &phyval);
-  nllinfo("  LPR:       %04x\n", phyval);
+  ninfo("  LPR:       %04x\n", phyval);
   sam_phyread(priv, priv->phyaddr, CONFIG_SAMA5_EMAC_PHYSR, &phyval);
-  nllinfo("  PHYSR:     %04x\n", phyval);
+  ninfo("  PHYSR:     %04x\n", phyval);
 
   /* Disable management port */
 
@@ -2410,7 +2410,7 @@ static int sam_phyreset(struct sam_emac_s *priv)
   int timeout;
   int ret;
 
-  nllinfo(" sam_phyreset\n");
+  ninfo(" sam_phyreset\n");
 
   /* Enable management port */
 
@@ -2423,7 +2423,7 @@ static int sam_phyreset(struct sam_emac_s *priv)
   ret = sam_phywrite(priv, priv->phyaddr, MII_MCR, MII_MCR_RESET);
   if (ret < 0)
     {
-      nllerr("ERROR: sam_phywrite failed: %d\n", ret);
+      nerr("ERROR: sam_phywrite failed: %d\n", ret);
     }
 
   /* Wait for the PHY reset to complete */
@@ -2435,7 +2435,7 @@ static int sam_phyreset(struct sam_emac_s *priv)
       int result = sam_phyread(priv, priv->phyaddr, MII_MCR, &mcr);
       if (result < 0)
         {
-          nllerr("ERROR: Failed to read the MCR register: %d\n", ret);
+          nerr("ERROR: Failed to read the MCR register: %d\n", ret);
           ret = result;
         }
       else if ((mcr & MII_MCR_RESET) == 0)
@@ -2477,7 +2477,7 @@ static int sam_phyfind(struct sam_emac_s *priv, uint8_t *phyaddr)
   unsigned int offset;
   int ret = -ESRCH;
 
-  nllinfo("Find a valid PHY address\n");
+  ninfo("Find a valid PHY address\n");
 
   /* Enable management port */
 
@@ -2500,8 +2500,8 @@ static int sam_phyfind(struct sam_emac_s *priv, uint8_t *phyaddr)
 
   else
     {
-      nllerr("ERROR: sam_phyread failed for PHY address %02x: %d\n",
-             candidate, ret);
+      nerr("ERROR: sam_phyread failed for PHY address %02x: %d\n",
+           candidate, ret);
 
       for (offset = 0; offset < 32; offset++)
         {
@@ -2522,10 +2522,10 @@ static int sam_phyfind(struct sam_emac_s *priv, uint8_t *phyaddr)
 
   if (ret == OK)
     {
-      nllinfo("  PHYID1: %04x PHY addr: %d\n", phyval, candidate);
+      ninfo("  PHYID1: %04x PHY addr: %d\n", phyval, candidate);
       *phyaddr = candidate;
       sam_phyread(priv, candidate, CONFIG_SAMA5_EMAC_PHYSR, &phyval);
-      nllinfo("  PHYSR:  %04x PHY addr: %d\n", phyval, candidate);
+      ninfo("  PHYSR:  %04x PHY addr: %d\n", phyval, candidate);
     }
 
   /* Disable management port */
@@ -2566,7 +2566,7 @@ static int sam_phyread(struct sam_emac_s *priv, uint8_t phyaddr,
   ret = sam_phywait(priv);
   if (ret < 0)
     {
-      nllerr("ERROR: sam_phywait failed: %d\n", ret);
+      nerr("ERROR: sam_phywait failed: %d\n", ret);
       return ret;
     }
 
@@ -2581,7 +2581,7 @@ static int sam_phyread(struct sam_emac_s *priv, uint8_t phyaddr,
   ret = sam_phywait(priv);
   if (ret < 0)
     {
-      nllerr("ERROR: sam_phywait failed: %d\n", ret);
+      nerr("ERROR: sam_phywait failed: %d\n", ret);
       return ret;
     }
 
@@ -2621,7 +2621,7 @@ static int sam_phywrite(struct sam_emac_s *priv, uint8_t phyaddr,
   ret = sam_phywait(priv);
   if (ret < 0)
     {
-      nllerr("ERROR: sam_phywait failed: %d\n", ret);
+      nerr("ERROR: sam_phywait failed: %d\n", ret);
       return ret;
     }
 
@@ -2636,7 +2636,7 @@ static int sam_phywrite(struct sam_emac_s *priv, uint8_t phyaddr,
   ret = sam_phywait(priv);
   if (ret < 0)
     {
-      nllerr("ERROR: sam_phywait failed: %d\n", ret);
+      nerr("ERROR: sam_phywait failed: %d\n", ret);
       return ret;
     }
 
@@ -2680,32 +2680,32 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
   ret = sam_phyread(priv, priv->phyaddr, MII_PHYID1, &phyid1);
   if (ret < 0)
     {
-      nllerr("ERROR: Failed to read PHYID1\n");
+      nerr("ERROR: Failed to read PHYID1\n");
       goto errout;
     }
 
-  nllinfo("PHYID1: %04x PHY address: %02x\n", phyid1, priv->phyaddr);
+  ninfo("PHYID1: %04x PHY address: %02x\n", phyid1, priv->phyaddr);
 
   ret = sam_phyread(priv, priv->phyaddr, MII_PHYID2, &phyid2);
   if (ret < 0)
     {
-      nllerr("ERROR: Failed to read PHYID2\n");
+      nerr("ERROR: Failed to read PHYID2\n");
       goto errout;
     }
 
-  nllinfo("PHYID2: %04x PHY address: %02x\n", phyid2, priv->phyaddr);
+  ninfo("PHYID2: %04x PHY address: %02x\n", phyid2, priv->phyaddr);
 
   if (phyid1 == MII_OUI_MSB &&
      ((phyid2 & MII_PHYID2_OUI_MASK) >> MII_PHYID2_OUI_SHIFT) == MII_OUI_LSB)
     {
-      nllinfo("  Vendor Model Number:   %04x\n",
-             (phyid2 & MII_PHYID2_MODEL_MASK) >> MII_PHYID2_MODEL_SHIFT);
-      nllinfo("  Model Revision Number: %04x\n",
-             (phyid2 & MII_PHYID2_REV_MASK) >> MII_PHYID2_REV_SHIFT);
+      ninfo("  Vendor Model Number:   %04x\n",
+           (phyid2 & MII_PHYID2_MODEL_MASK) >> MII_PHYID2_MODEL_SHIFT);
+      ninfo("  Model Revision Number: %04x\n",
+           (phyid2 & MII_PHYID2_REV_MASK) >> MII_PHYID2_REV_SHIFT);
     }
   else
     {
-      nllerr("ERROR: PHY not recognized\n");
+      nerr("ERROR: PHY not recognized\n");
     }
 
   /* Setup control register */
@@ -2713,7 +2713,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
   ret = sam_phyread(priv, priv->phyaddr, MII_MCR, &mcr);
   if (ret < 0)
     {
-      nllerr("ERROR: Failed to read MCR\n");
+      nerr("ERROR: Failed to read MCR\n");
       goto errout;
     }
 
@@ -2724,7 +2724,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
   ret = sam_phywrite(priv, priv->phyaddr, MII_MCR, mcr);
   if (ret < 0)
     {
-      nllerr("ERROR: Failed to write MCR\n");
+      nerr("ERROR: Failed to write MCR\n");
       goto errout;
     }
 
@@ -2739,7 +2739,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
   ret = sam_phywrite(priv, priv->phyaddr, MII_ADVERTISE, advertise);
   if (ret < 0)
     {
-      nllerr("ERROR: Failed to write ANAR\n");
+      nerr("ERROR: Failed to write ANAR\n");
       goto errout;
     }
 
@@ -2748,7 +2748,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
   ret = sam_phyread(priv, priv->phyaddr, MII_MCR, &mcr);
   if (ret < 0)
     {
-      nllerr("ERROR: Failed to read MCR\n");
+      nerr("ERROR: Failed to read MCR\n");
       goto errout;
     }
 
@@ -2756,7 +2756,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
   ret = sam_phywrite(priv, priv->phyaddr, MII_MCR, mcr);
   if (ret < 0)
     {
-      nllerr("ERROR: Failed to write MCR\n");
+      nerr("ERROR: Failed to write MCR\n");
       goto errout;
     }
 
@@ -2768,11 +2768,11 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
   ret = sam_phywrite(priv, priv->phyaddr, MII_MCR, mcr);
   if (ret < 0)
     {
-      nllerr("ERROR: Failed to write MCR\n");
+      nerr("ERROR: Failed to write MCR\n");
       goto errout;
     }
 
-  nllinfo("  MCR: %04x\n", mcr);
+  ninfo("  MCR: %04x\n", mcr);
 
   /* Check AutoNegotiate complete */
 
@@ -2782,7 +2782,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
       ret = sam_phyread(priv, priv->phyaddr, MII_MSR, &msr);
       if (ret < 0)
         {
-          nllerr("ERROR: Failed to read MSR\n");
+          nerr("ERROR: Failed to read MSR\n");
           goto errout;
         }
 
@@ -2792,7 +2792,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
         {
           /* Yes.. break out of the loop */
 
-          nllinfo("AutoNegotiate complete\n");
+          ninfo("AutoNegotiate complete\n");
           break;
         }
 
@@ -2800,7 +2800,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
 
       if (++timeout >= PHY_RETRY_MAX)
         {
-          nllerr("ERROR: TimeOut\n");
+          nerr("ERROR: TimeOut\n");
           sam_phydump(priv);
           ret = -ETIMEDOUT;
           goto errout;
@@ -2812,7 +2812,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
   ret = sam_phyread(priv, priv->phyaddr, MII_LPA, &lpa);
   if (ret < 0)
     {
-      nllerr("ERROR: Failed to read ANLPAR\n");
+      nerr("ERROR: Failed to read ANLPAR\n");
       goto errout;
     }
 
@@ -2902,13 +2902,13 @@ static bool sam_linkup(struct sam_emac_s *priv)
   ret = sam_phyread(priv, priv->phyaddr, MII_MSR, &msr);
   if (ret < 0)
     {
-      nllerr("ERROR: Failed to read MSR: %d\n", ret);
+      nerr("ERROR: Failed to read MSR: %d\n", ret);
       goto errout;
     }
 
   if ((msr & MII_MSR_LINKSTATUS) == 0)
     {
-      nllerr("ERROR: MSR LinkStatus: %04x\n", msr);
+      nerr("ERROR: MSR LinkStatus: %04x\n", msr);
       goto errout;
     }
 
@@ -2917,7 +2917,7 @@ static bool sam_linkup(struct sam_emac_s *priv)
   ret = sam_phyread(priv, priv->phyaddr, CONFIG_SAMA5_EMAC_PHYSR, &physr);
   if (ret < 0)
     {
-      nllerr("ERROR: Failed to read PHYSR: %d\n", ret);
+      nerr("ERROR: Failed to read PHYSR: %d\n", ret);
       goto errout;
     }
 
@@ -2955,7 +2955,7 @@ static bool sam_linkup(struct sam_emac_s *priv)
 
   /* Start the EMAC transfers */
 
-  nllinfo("Link is up\n");
+  ninfo("Link is up\n");
   linkup = true;
 
 errout:
@@ -3024,7 +3024,7 @@ static int sam_phyinit(struct sam_emac_s *priv)
   ret = sam_phyfind(priv, &priv->phyaddr);
   if (ret < 0)
     {
-      nllerr("ERROR: sam_phyfind failed: %d\n", ret);
+      nerr("ERROR: sam_phyfind failed: %d\n", ret);
       return ret;
     }
 
@@ -3276,11 +3276,11 @@ static void sam_macaddress(struct sam_emac_s *priv)
   struct net_driver_s *dev = &priv->dev;
   uint32_t regval;
 
-  nllinfo("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
-          dev->d_ifname,
-          dev->d_mac.ether_addr_octet[0], dev->d_mac.ether_addr_octet[1],
-          dev->d_mac.ether_addr_octet[2], dev->d_mac.ether_addr_octet[3],
-          dev->d_mac.ether_addr_octet[4], dev->d_mac.ether_addr_octet[5]);
+  ninfo("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
+        dev->d_ifname,
+        dev->d_mac.ether_addr_octet[0], dev->d_mac.ether_addr_octet[1],
+        dev->d_mac.ether_addr_octet[2], dev->d_mac.ether_addr_octet[3],
+        dev->d_mac.ether_addr_octet[4], dev->d_mac.ether_addr_octet[5]);
 
   /* Set the MAC address */
 
@@ -3388,7 +3388,7 @@ static int sam_emac_configure(struct sam_emac_s *priv)
 {
   uint32_t regval;
 
-  nllinfo("Entry\n");
+  ninfo("Entry\n");
 
   /* Enable clocking to the EMAC peripheral */
 
diff --git a/arch/arm/src/sama5/sam_emacb.c b/arch/arm/src/sama5/sam_emacb.c
index 6dab62599f4..9b64fbc5ab9 100644
--- a/arch/arm/src/sama5/sam_emacb.c
+++ b/arch/arm/src/sama5/sam_emacb.c
@@ -970,7 +970,7 @@ static int sam_buffer_initialize(struct sam_emac_s *priv)
   priv->txdesc = (struct emac_txdesc_s *)kmm_memalign(8, allocsize);
   if (!priv->txdesc)
     {
-      nllerr("ERROR: Failed to allocate TX descriptors\n");
+      nerr("ERROR: Failed to allocate TX descriptors\n");
       return -ENOMEM;
     }
 
@@ -980,7 +980,7 @@ static int sam_buffer_initialize(struct sam_emac_s *priv)
   priv->rxdesc = (struct emac_rxdesc_s *)kmm_memalign(8, allocsize);
   if (!priv->rxdesc)
     {
-      nllerr("ERROR: Failed to allocate RX descriptors\n");
+      nerr("ERROR: Failed to allocate RX descriptors\n");
       sam_buffer_free(priv);
       return -ENOMEM;
     }
@@ -991,7 +991,7 @@ static int sam_buffer_initialize(struct sam_emac_s *priv)
   priv->txbuffer = (uint8_t *)kmm_memalign(8, allocsize);
   if (!priv->txbuffer)
     {
-      nllerr("ERROR: Failed to allocate TX buffer\n");
+      nerr("ERROR: Failed to allocate TX buffer\n");
       sam_buffer_free(priv);
       return -ENOMEM;
     }
@@ -1000,7 +1000,7 @@ static int sam_buffer_initialize(struct sam_emac_s *priv)
   priv->rxbuffer = (uint8_t *)kmm_memalign(8, allocsize);
   if (!priv->rxbuffer)
     {
-      nllerr("ERROR: Failed to allocate RX buffer\n");
+      nerr("ERROR: Failed to allocate RX buffer\n");
       sam_buffer_free(priv);
       return -ENOMEM;
     }
@@ -1088,14 +1088,14 @@ static int sam_transmit(struct sam_emac_s *priv)
   uint32_t regval;
   uint32_t status;
 
-  nllinfo("d_len: %d txhead: %d\n",  dev->d_len, priv->txhead);
+  ninfo("d_len: %d txhead: %d\n",  dev->d_len, priv->txhead);
   sam_dumppacket("Transmit packet", dev->d_buf, dev->d_len);
 
   /* Check parameter */
 
   if (dev->d_len > EMAC_TX_UNITSIZE)
     {
-      nllerr("ERROR: Packet too big: %d\n", dev->d_len);
+      nerr("ERROR: Packet too big: %d\n", dev->d_len);
       return -EINVAL;
     }
 
@@ -1107,7 +1107,7 @@ static int sam_transmit(struct sam_emac_s *priv)
 
   if (sam_txfree(priv) < 1)
     {
-      nllerr("ERROR: No free TX descriptors\n");
+      nerr("ERROR: No free TX descriptors\n");
       return -EBUSY;
     }
 
@@ -1169,7 +1169,7 @@ static int sam_transmit(struct sam_emac_s *priv)
 
   if (sam_txfree(priv) < 1)
     {
-      nllinfo("Disabling RX interrupts\n");
+      ninfo("Disabling RX interrupts\n");
       sam_putreg(priv, SAM_EMAC_IDR_OFFSET, EMAC_INT_RCOMP);
     }
 
@@ -1349,7 +1349,7 @@ static int sam_recvframe(struct sam_emac_s *priv)
 
   arch_invalidate_dcache((uintptr_t)rxdesc,
                          (uintptr_t)rxdesc + sizeof(struct emac_rxdesc_s));
-  nllinfo("rxndx: %d\n", rxndx);
+  ninfo("rxndx: %d\n", rxndx);
 
   while ((rxdesc->addr & EMACRXD_ADDR_OWNER) != 0)
     {
@@ -1405,7 +1405,7 @@ static int sam_recvframe(struct sam_emac_s *priv)
         {
           if (rxndx == priv->rxndx)
             {
-              nllinfo("ERROR: No EOF (Invalid of buffers too small)\n");
+              nerr("ERROR: No EOF (Invalid of buffers too small)\n");
               do
                 {
                   /* Give ownership back to the EMAC */
@@ -1460,7 +1460,7 @@ static int sam_recvframe(struct sam_emac_s *priv)
               /* Frame size from the EMAC */
 
               dev->d_len = (rxdesc->status & EMACRXD_STA_FRLEN_MASK);
-              nllinfo("packet %d-%d (%d)\n", priv->rxndx, rxndx, dev->d_len);
+              ninfo("packet %d-%d (%d)\n", priv->rxndx, rxndx, dev->d_len);
 
               /* All data have been copied in the application frame buffer,
                * release the RX descriptor
@@ -1491,11 +1491,11 @@ static int sam_recvframe(struct sam_emac_s *priv)
                * all of the data.
                */
 
-              nllinfo("rxndx: %d d_len: %d\n", priv->rxndx, dev->d_len);
+              ninfo("rxndx: %d d_len: %d\n", priv->rxndx, dev->d_len);
               if (pktlen < dev->d_len)
                 {
-                  nllerr("ERROR: Buffer size %d; frame size %d\n",
-                         dev->d_len, pktlen);
+                  nerr("ERROR: Buffer size %d; frame size %d\n",
+                       dev->d_len, pktlen);
                   return -E2BIG;
                 }
 
@@ -1535,7 +1535,7 @@ static int sam_recvframe(struct sam_emac_s *priv)
   /* No packet was found */
 
   priv->rxndx = rxndx;
-  nllinfo("rxndx: %d\n", priv->rxndx);
+  ninfo("rxndx: %d\n", priv->rxndx);
   return -EAGAIN;
 }
 
@@ -1575,7 +1575,7 @@ static void sam_receive(struct sam_emac_s *priv)
 
       if (dev->d_len > CONFIG_NET_ETH_MTU)
         {
-          nllwarn("WARNING: Dropped, Too big: %d\n", dev->d_len);
+          nwarn("WARNING: Dropped, Too big: %d\n", dev->d_len);
           continue;
         }
 
@@ -1590,7 +1590,7 @@ static void sam_receive(struct sam_emac_s *priv)
 #ifdef CONFIG_NET_IPv4
       if (BUF->type == HTONS(ETHTYPE_IP))
         {
-          nllinfo("IPv4 frame\n");
+          ninfo("IPv4 frame\n");
 
           /* Handle ARP on input then give the IPv4 packet to the network
            * layer
@@ -1630,7 +1630,7 @@ static void sam_receive(struct sam_emac_s *priv)
 #ifdef CONFIG_NET_IPv6
       if (BUF->type == HTONS(ETHTYPE_IP6))
         {
-          nllinfo("Iv6 frame\n");
+          ninfo("Iv6 frame\n");
 
           /* Give the IPv6 packet to the network layer */
 
@@ -1667,7 +1667,7 @@ static void sam_receive(struct sam_emac_s *priv)
 #ifdef CONFIG_NET_ARP
       if (BUF->type == htons(ETHTYPE_ARP))
         {
-          nllinfo("ARP frame\n");
+          ninfo("ARP frame\n");
 
           /* Handle ARP packet */
 
@@ -1685,7 +1685,7 @@ static void sam_receive(struct sam_emac_s *priv)
       else
 #endif
         {
-          nllwarn("WARNING: Dropped, Unknown type: %04x\n", BUF->type);
+          nwarn("WARNING: Dropped, Unknown type: %04x\n", BUF->type);
         }
     }
 }
@@ -1836,7 +1836,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv)
   imr = sam_getreg(priv, SAM_EMAC_IMR_OFFSET);
 
   pending = isr & ~(imr | EMAC_INT_UNUSED);
-  nllinfo("isr: %08x pending: %08x\n", isr, pending);
+  ninfo("isr: %08x pending: %08x\n", isr, pending);
 
   /* Check for the completion of a transmission.  This should be done before
    * checking for received data (because receiving can cause another transmission
@@ -1862,7 +1862,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv)
           clrbits = EMAC_TSR_RLE | sam_txinuse(priv);
           sam_txreset(priv);
 
-          nllerr("ERROR: Retry Limit Exceeded TSR: %08x\n", tsr);
+          nerr("ERROR: Retry Limit Exceeded TSR: %08x\n", tsr);
 
           regval = sam_getreg(priv, SAM_EMAC_NCR_OFFSET);
           regval |= EMAC_NCR_TXEN;
@@ -1873,7 +1873,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv)
 
       if ((tsr & EMAC_TSR_COL) != 0)
         {
-          nllerr("ERROR: Collision occurred TSR: %08x\n", tsr);
+          nerr("ERROR: Collision occurred TSR: %08x\n", tsr);
           clrbits |= EMAC_TSR_COL;
         }
 
@@ -1881,7 +1881,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv)
 
       if ((tsr & EMAC_TSR_TFC) != 0)
         {
-          nllerr("ERROR: Transmit Frame Corruption due to AHB error: %08x\n", tsr);
+          nerr("ERROR: Transmit Frame Corruption due to AHB error: %08x\n", tsr);
           clrbits |= EMAC_TSR_TFC;
         }
 
@@ -1896,7 +1896,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv)
 
       if ((tsr & EMAC_TSR_UND) != 0)
         {
-          nllerr("ERROR: Transmit Underrun TSR: %08x\n", tsr);
+          nerr("ERROR: Transmit Underrun TSR: %08x\n", tsr);
           clrbits |= EMAC_TSR_UND;
         }
 
@@ -1933,7 +1933,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv)
 
       if ((rsr & EMAC_RSR_RXOVR) != 0)
         {
-          nllerr("ERROR: Receiver overrun RSR: %08x\n", rsr);
+          nerr("ERROR: Receiver overrun RSR: %08x\n", rsr);
           clrbits |= EMAC_RSR_RXOVR;
         }
 
@@ -1950,7 +1950,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv)
 
       if ((rsr & EMAC_RSR_BNA) != 0)
         {
-          nllerr("ERROR: Buffer not available RSR: %08x\n", rsr);
+          nerr("ERROR: Buffer not available RSR: %08x\n", rsr);
           clrbits |= EMAC_RSR_BNA;
         }
 
@@ -1972,7 +1972,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv)
 
   if ((pending & EMAC_INT_PFNZ) != 0)
     {
-      nllwarn("WARNING: Pause frame received\n");
+      nwarn("WARNING: Pause frame received\n");
     }
 
   /* Check for Pause Time Zero (PTZ)
@@ -1982,7 +1982,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv)
 
   if ((pending & EMAC_INT_PTZ) != 0)
     {
-      nllwarn("WARNING: Pause TO!\n");
+      nwarn("WARNING: Pause TO!\n");
     }
 #endif
 }
@@ -2147,7 +2147,7 @@ static int sam_emac1_interrupt(int irq, void *context)
 
 static inline void sam_txtimeout_process(FAR struct sam_emac_s *priv)
 {
-  nllerr("ERROR: Timeout!\n");
+  nerr("ERROR: Timeout!\n");
 
   /* Reset the hardware.  Just take the interface down, then back up again. */
 
@@ -2390,7 +2390,7 @@ static int sam_ifup(struct net_driver_s *dev)
 
   /* Configure the EMAC interface for normal operation. */
 
-  nllinfo("Initialize the EMAC\n");
+  ninfo("Initialize the EMAC\n");
   sam_emac_configure(priv);
 
   /* Set the MAC address (should have been configured while we were down) */
@@ -2408,7 +2408,7 @@ static int sam_ifup(struct net_driver_s *dev)
   ret = sam_phyinit(priv);
   if (ret < 0)
     {
-      nllerr("ERROR: sam_phyinit failed: %d\n", ret);
+      nerr("ERROR: sam_phyinit failed: %d\n", ret);
       return ret;
     }
 
@@ -2417,16 +2417,16 @@ static int sam_ifup(struct net_driver_s *dev)
   ret = sam_autonegotiate(priv);
   if (ret < 0)
     {
-      nllerr("ERROR: sam_autonegotiate failed: %d\n", ret);
+      nerr("ERROR: sam_autonegotiate failed: %d\n", ret);
       return ret;
     }
 
   while (sam_linkup(priv) == 0);
-  nllinfo("Link detected \n");
+  ninfo("Link detected \n");
 
   /* Enable normal MAC operation */
 
-  nllinfo("Enable normal operation\n");
+  ninfo("Enable normal operation\n");
 
   /* Set and activate a timer process */
 
@@ -2460,7 +2460,7 @@ static int sam_ifdown(struct net_driver_s *dev)
   struct sam_emac_s *priv = (struct sam_emac_s *)dev->d_private;
   irqstate_t flags;
 
-  nllinfo("Taking the network down\n");
+  ninfo("Taking the network down\n");
 
   /* Disable the EMAC interrupt */
 
@@ -2505,7 +2505,7 @@ static int sam_ifdown(struct net_driver_s *dev)
 
 static inline void sam_txavail_process(FAR struct sam_emac_s *priv)
 {
-  nllinfo("ifup: %d\n", priv->ifup);
+  ninfo("ifup: %d\n", priv->ifup);
 
   /* Ignore the notification if the interface is not yet up */
 
@@ -2758,8 +2758,8 @@ static int sam_addmac(struct net_driver_s *dev, const uint8_t *mac)
   unsigned int ndx;
   unsigned int bit;
 
-  nllinfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
-          mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+  ninfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
+        mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
 
   /* Calculate the 6-bit has table index */
 
@@ -2831,8 +2831,8 @@ static int sam_rmmac(struct net_driver_s *dev, const uint8_t *mac)
   unsigned int ndx;
   unsigned int bit;
 
-  nllinfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
-          mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+  ninfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
+        mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
 
   /* Calculate the 6-bit has table index */
 
@@ -3026,19 +3026,19 @@ static void sam_phydump(struct sam_emac_s *priv)
   regval |= EMAC_NCR_MPE;
   sam_putreg(priv, SAM_EMAC_NCR_OFFSET, regval);
 
-  nllinfo("%s Registers (Address %02x)\n",
-          priv->attr->rmii ? "RMII" : "MII", priv->phyaddr);
+  ninfo("%s Registers (Address %02x)\n",
+        priv->attr->rmii ? "RMII" : "MII", priv->phyaddr);
 
   sam_phyread(priv, priv->phyaddr, MII_MCR, &phyval);
-  nllinfo("  MCR:       %04x\n", phyval);
+  ninfo("  MCR:       %04x\n", phyval);
   sam_phyread(priv, priv->phyaddr, MII_MSR, &phyval);
-  nllinfo("  MSR:       %04x\n", phyval);
+  ninfo("  MSR:       %04x\n", phyval);
   sam_phyread(priv, priv->phyaddr, MII_ADVERTISE, &phyval);
-  nllinfo("  ADVERTISE: %04x\n", phyval);
+  ninfo("  ADVERTISE: %04x\n", phyval);
   sam_phyread(priv, priv->phyaddr, MII_LPA, &phyval);
-  nllinfo("  LPR:       %04x\n", phyval);
+  ninfo("  LPR:       %04x\n", phyval);
   sam_phyread(priv, priv->phyaddr, priv->attr->physr, &phyval);
-  nllinfo("  PHYSR:     %04x\n", phyval);
+  ninfo("  PHYSR:     %04x\n", phyval);
 
   /* Disable management port */
 
@@ -3262,7 +3262,7 @@ static int sam_phyreset(struct sam_emac_s *priv)
   int timeout;
   int ret;
 
-  nllinfo(" sam_phyreset\n");
+  ninfo(" sam_phyreset\n");
 
   /* Enable management port */
 
@@ -3275,7 +3275,7 @@ static int sam_phyreset(struct sam_emac_s *priv)
   ret = sam_phywrite(priv, priv->phyaddr, MII_MCR, MII_MCR_RESET);
   if (ret < 0)
     {
-      nllerr("ERROR: sam_phywrite failed: %d\n", ret);
+      nerr("ERROR: sam_phywrite failed: %d\n", ret);
     }
 
   /* Wait for the PHY reset to complete */
@@ -3287,7 +3287,7 @@ static int sam_phyreset(struct sam_emac_s *priv)
       int result = sam_phyread(priv, priv->phyaddr, MII_MCR, &mcr);
       if (result < 0)
         {
-          nllerr("ERROR: Failed to read the MCR register: %d\n", ret);
+          nerr("ERROR: Failed to read the MCR register: %d\n", ret);
           ret = result;
         }
       else if ((mcr & MII_MCR_RESET) == 0)
@@ -3329,7 +3329,7 @@ static int sam_phyfind(struct sam_emac_s *priv, uint8_t *phyaddr)
   unsigned int offset;
   int ret = -ESRCH;
 
-  nllinfo("Find a valid PHY address\n");
+  ninfo("Find a valid PHY address\n");
 
   /* Enable management port */
 
@@ -3352,8 +3352,8 @@ static int sam_phyfind(struct sam_emac_s *priv, uint8_t *phyaddr)
 
   else
     {
-      nllerr("ERROR: sam_phyread failed for PHY address %02x: %d\n",
-             candidate, ret);
+      nerr("ERROR: sam_phyread failed for PHY address %02x: %d\n",
+           candidate, ret);
 
       for (offset = 0; offset < 32; offset++)
         {
@@ -3374,10 +3374,10 @@ static int sam_phyfind(struct sam_emac_s *priv, uint8_t *phyaddr)
 
   if (ret == OK)
     {
-      nllinfo("  PHYID1: %04x PHY addr: %d\n", phyval, candidate);
+      ninfo("  PHYID1: %04x PHY addr: %d\n", phyval, candidate);
       *phyaddr = candidate;
       sam_phyread(priv, candidate, priv->attr->physr, &phyval);
-      nllinfo("  PHYSR:  %04x PHY addr: %d\n", phyval, candidate);
+      ninfo("  PHYSR:  %04x PHY addr: %d\n", phyval, candidate);
     }
 
   /* Disable management port */
@@ -3418,7 +3418,7 @@ static int sam_phyread(struct sam_emac_s *priv, uint8_t phyaddr,
   ret = sam_phywait(priv);
   if (ret < 0)
     {
-      nllerr("ERROR: sam_phywait failed: %d\n", ret);
+      nerr("ERROR: sam_phywait failed: %d\n", ret);
       return ret;
     }
 
@@ -3443,7 +3443,7 @@ static int sam_phyread(struct sam_emac_s *priv, uint8_t phyaddr,
   ret = sam_phywait(priv);
   if (ret < 0)
     {
-      nllerr("ERROR: sam_phywait failed: %d\n", ret);
+      nerr("ERROR: sam_phywait failed: %d\n", ret);
       return ret;
     }
 
@@ -3483,7 +3483,7 @@ static int sam_phywrite(struct sam_emac_s *priv, uint8_t phyaddr,
   ret = sam_phywait(priv);
   if (ret < 0)
     {
-      nllerr("ERROR: sam_phywait failed: %d\n", ret);
+      nerr("ERROR: sam_phywait failed: %d\n", ret);
       return ret;
     }
 
@@ -3508,7 +3508,7 @@ static int sam_phywrite(struct sam_emac_s *priv, uint8_t phyaddr,
   ret = sam_phywait(priv);
   if (ret < 0)
     {
-      nllerr("ERROR: sam_phywait failed: %d\n", ret);
+      nerr("ERROR: sam_phywait failed: %d\n", ret);
       return ret;
     }
 
@@ -3552,33 +3552,33 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
   ret = sam_phyread(priv, priv->phyaddr, MII_PHYID1, &phyid1);
   if (ret < 0)
     {
-      nllerr("ERROR: Failed to read PHYID1\n");
+      nerr("ERROR: Failed to read PHYID1\n");
       goto errout;
     }
 
-  nllinfo("PHYID1: %04x PHY address: %02x\n", phyid1, priv->phyaddr);
+  ninfo("PHYID1: %04x PHY address: %02x\n", phyid1, priv->phyaddr);
 
   ret = sam_phyread(priv, priv->phyaddr, MII_PHYID2, &phyid2);
   if (ret < 0)
     {
-      nllerr("ERROR: Failed to read PHYID2\n");
+      nerr("ERROR: Failed to read PHYID2\n");
       goto errout;
     }
 
-  nllinfo("PHYID2: %04x PHY address: %02x\n", phyid2, priv->phyaddr);
+  ninfo("PHYID2: %04x PHY address: %02x\n", phyid2, priv->phyaddr);
 
   if (phyid1 == priv->attr->msoui &&
      ((phyid2 & MII_PHYID2_OUI_MASK) >> MII_PHYID2_OUI_SHIFT) ==
       (uint16_t)priv->attr->lsoui)
     {
-      nllinfo("  Vendor Model Number:   %04x\n",
-             (phyid2 & MII_PHYID2_MODEL_MASK) >> MII_PHYID2_MODEL_SHIFT);
-      nllinfo("  Model Revision Number: %04x\n",
-             (phyid2 & MII_PHYID2_REV_MASK) >> MII_PHYID2_REV_SHIFT);
+      ninfo("  Vendor Model Number:   %04x\n",
+           (phyid2 & MII_PHYID2_MODEL_MASK) >> MII_PHYID2_MODEL_SHIFT);
+      ninfo("  Model Revision Number: %04x\n",
+           (phyid2 & MII_PHYID2_REV_MASK) >> MII_PHYID2_REV_SHIFT);
     }
   else
     {
-      nllerr("ERROR: PHY not recognized\n");
+      nerr("ERROR: PHY not recognized\n");
     }
 
   /* Setup control register */
@@ -3586,7 +3586,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
   ret = sam_phyread(priv, priv->phyaddr, MII_MCR, &mcr);
   if (ret < 0)
     {
-      nllerr("ERROR: Failed to read MCR\n");
+      nerr("ERROR: Failed to read MCR\n");
       goto errout;
     }
 
@@ -3597,7 +3597,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
   ret = sam_phywrite(priv, priv->phyaddr, MII_MCR, mcr);
   if (ret < 0)
     {
-      nllerr("ERROR: Failed to write MCR\n");
+      nerr("ERROR: Failed to write MCR\n");
       goto errout;
     }
 
@@ -3612,7 +3612,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
   ret = sam_phywrite(priv, priv->phyaddr, MII_ADVERTISE, advertise);
   if (ret < 0)
     {
-      nllerr("ERROR: Failed to write ANAR\n");
+      nerr("ERROR: Failed to write ANAR\n");
       goto errout;
     }
 
@@ -3621,7 +3621,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
   ret = sam_phyread(priv, priv->phyaddr, MII_MCR, &mcr);
   if (ret < 0)
     {
-      nllerr("ERROR: Failed to read MCR\n");
+      nerr("ERROR: Failed to read MCR\n");
       goto errout;
     }
 
@@ -3629,7 +3629,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
   ret = sam_phywrite(priv, priv->phyaddr, MII_MCR, mcr);
   if (ret < 0)
     {
-      nllerr("ERROR: Failed to write MCR\n");
+      nerr("ERROR: Failed to write MCR\n");
       goto errout;
     }
 
@@ -3641,11 +3641,11 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
   ret = sam_phywrite(priv, priv->phyaddr, MII_MCR, mcr);
   if (ret < 0)
     {
-      nllerr("ERROR: Failed to write MCR\n");
+      nerr("ERROR: Failed to write MCR\n");
       goto errout;
     }
 
-  nllinfo("  MCR: %04x\n", mcr);
+  ninfo("  MCR: %04x\n", mcr);
 
   /* Check AutoNegotiate complete */
 
@@ -3655,7 +3655,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
       ret = sam_phyread(priv, priv->phyaddr, MII_MSR, &msr);
       if (ret < 0)
         {
-          nllerr("ERROR: Failed to read MSR\n");
+          nerr("ERROR: Failed to read MSR\n");
           goto errout;
         }
 
@@ -3665,7 +3665,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
         {
           /* Yes.. break out of the loop */
 
-          nllinfo("AutoNegotiate complete\n");
+          ninfo("AutoNegotiate complete\n");
           break;
         }
 
@@ -3673,7 +3673,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
 
       if (++timeout >= PHY_RETRY_MAX)
         {
-          nllerr("ERROR: TimeOut\n");
+          nerr("ERROR: TimeOut\n");
           sam_phydump(priv);
           ret = -ETIMEDOUT;
           goto errout;
@@ -3685,7 +3685,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
   ret = sam_phyread(priv, priv->phyaddr, MII_LPA, &lpa);
   if (ret < 0)
     {
-      nllerr("ERROR: Failed to read ANLPAR\n");
+      nerr("ERROR: Failed to read ANLPAR\n");
       goto errout;
     }
 
@@ -3775,13 +3775,13 @@ static bool sam_linkup(struct sam_emac_s *priv)
   ret = sam_phyread(priv, priv->phyaddr, MII_MSR, &msr);
   if (ret < 0)
     {
-      nllerr("ERROR: Failed to read MSR: %d\n", ret);
+      nerr("ERROR: Failed to read MSR: %d\n", ret);
       goto errout;
     }
 
   if ((msr & MII_MSR_LINKSTATUS) == 0)
     {
-      nllerr("ERROR: MSR LinkStatus: %04x\n", msr);
+      nerr("ERROR: MSR LinkStatus: %04x\n", msr);
       goto errout;
     }
 
@@ -3790,7 +3790,7 @@ static bool sam_linkup(struct sam_emac_s *priv)
   ret = sam_phyread(priv, priv->phyaddr, priv->attr->physr, &physr);
   if (ret < 0)
     {
-      nllerr("ERROR: Failed to read PHYSR: %d\n", ret);
+      nerr("ERROR: Failed to read PHYSR: %d\n", ret);
       goto errout;
     }
 
@@ -3828,7 +3828,7 @@ static bool sam_linkup(struct sam_emac_s *priv)
 
   /* Start the EMAC transfers */
 
-  nllinfo("Link is up\n");
+  ninfo("Link is up\n");
   linkup = true;
 
 errout:
@@ -3897,7 +3897,7 @@ static int sam_phyinit(struct sam_emac_s *priv)
   ret = sam_phyfind(priv, &priv->phyaddr);
   if (ret < 0)
     {
-      nllerr("ERROR: sam_phyfind failed: %d\n", ret);
+      nerr("ERROR: sam_phyfind failed: %d\n", ret);
       return ret;
     }
 
@@ -4012,7 +4012,7 @@ static inline void sam_ethgpioconfig(struct sam_emac_s *priv)
   else
 #endif
     {
-      ninfo("ERROR: emac=%d\n", priv->attr->emac);
+      nerr("ERROR: emac=%d\n", priv->attr->emac);
     }
 }
 
@@ -4311,11 +4311,11 @@ static void sam_macaddress(struct sam_emac_s *priv)
   struct net_driver_s *dev = &priv->dev;
   uint32_t regval;
 
-  nllinfo("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
-          dev->d_ifname,
-          dev->d_mac.ether_addr_octet[0], dev->d_mac.ether_addr_octet[1],
-          dev->d_mac.ether_addr_octet[2], dev->d_mac.ether_addr_octet[3],
-          dev->d_mac.ether_addr_octet[4], dev->d_mac.ether_addr_octet[5]);
+  ninfo("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
+        dev->d_ifname,
+        dev->d_mac.ether_addr_octet[0], dev->d_mac.ether_addr_octet[1],
+        dev->d_mac.ether_addr_octet[2], dev->d_mac.ether_addr_octet[3],
+        dev->d_mac.ether_addr_octet[4], dev->d_mac.ether_addr_octet[5]);
 
   /* Set the MAC address */
 
@@ -4423,7 +4423,7 @@ static int sam_emac_configure(struct sam_emac_s *priv)
 {
   uint32_t regval;
 
-  nllinfo("Entry\n");
+  ninfo("Entry\n");
 
   /* Enable clocking to the EMAC peripheral */
 
diff --git a/arch/arm/src/sama5/sam_ethernet.c b/arch/arm/src/sama5/sam_ethernet.c
index d10f096d294..206af9fc672 100644
--- a/arch/arm/src/sama5/sam_ethernet.c
+++ b/arch/arm/src/sama5/sam_ethernet.c
@@ -88,7 +88,7 @@ static inline void up_gmac_initialize(void)
   ret = sam_gmac_initialize();
   if (ret < 0)
     {
-      nllerr("ERROR: sam_gmac_initialize failed: %d\n", ret);
+      nerr("ERROR: sam_gmac_initialize failed: %d\n", ret);
     }
 }
 #else
@@ -119,7 +119,7 @@ static inline void up_emac_initialize(void)
   ret = sam_emac_initialize();
   if (ret < 0)
     {
-      nllerr("ERROR: up_emac_initialize failed: %d\n", ret);
+      nerr("ERROR: up_emac_initialize failed: %d\n", ret);
     }
 }
 #elif defined(CONFIG_SAMA5_EMACB)
@@ -133,7 +133,7 @@ static inline void up_emac_initialize(void)
   ret = sam_emac_initialize(EMAC0_INTF);
   if (ret < 0)
     {
-      nllerr("ERROR: up_emac_initialize(EMAC0) failed: %d\n", ret);
+      nerr("ERROR: up_emac_initialize(EMAC0) failed: %d\n", ret);
     }
 #endif
 
@@ -143,7 +143,7 @@ static inline void up_emac_initialize(void)
   ret = sam_emac_initialize(EMAC1_INTF);
   if (ret < 0)
     {
-      nllerr("ERROR: up_emac_initialize(EMAC1) failed: %d\n", ret);
+      nerr("ERROR: up_emac_initialize(EMAC1) failed: %d\n", ret);
     }
 #endif
 }
diff --git a/arch/arm/src/sama5/sam_gmac.c b/arch/arm/src/sama5/sam_gmac.c
index 66472d36835..75a38365540 100644
--- a/arch/arm/src/sama5/sam_gmac.c
+++ b/arch/arm/src/sama5/sam_gmac.c
@@ -538,7 +538,7 @@ static int sam_buffer_initialize(struct sam_gmac_s *priv)
   priv->txdesc = (struct gmac_txdesc_s *)kmm_memalign(8, allocsize);
   if (!priv->txdesc)
     {
-      nllerr("ERROR: Failed to allocate TX descriptors\n");
+      nerr("ERROR: Failed to allocate TX descriptors\n");
       return -ENOMEM;
     }
 
@@ -548,7 +548,7 @@ static int sam_buffer_initialize(struct sam_gmac_s *priv)
   priv->rxdesc = (struct gmac_rxdesc_s *)kmm_memalign(8, allocsize);
   if (!priv->rxdesc)
     {
-      nllerr("ERROR: Failed to allocate RX descriptors\n");
+      nerr("ERROR: Failed to allocate RX descriptors\n");
       sam_buffer_free(priv);
       return -ENOMEM;
     }
@@ -559,7 +559,7 @@ static int sam_buffer_initialize(struct sam_gmac_s *priv)
   priv->txbuffer = (uint8_t *)kmm_memalign(8, allocsize);
   if (!priv->txbuffer)
     {
-      nllerr("ERROR: Failed to allocate TX buffer\n");
+      nerr("ERROR: Failed to allocate TX buffer\n");
       sam_buffer_free(priv);
       return -ENOMEM;
     }
@@ -568,7 +568,7 @@ static int sam_buffer_initialize(struct sam_gmac_s *priv)
   priv->rxbuffer = (uint8_t *)kmm_memalign(8, allocsize);
   if (!priv->rxbuffer)
     {
-      nllerr("ERROR: Failed to allocate RX buffer\n");
+      nerr("ERROR: Failed to allocate RX buffer\n");
       sam_buffer_free(priv);
       return -ENOMEM;
     }
@@ -656,15 +656,15 @@ static int sam_transmit(struct sam_gmac_s *priv)
   uint32_t regval;
   uint32_t status;
 
-  nllinfo("d_len: %d txhead: %d txtail: %d\n",
-          dev->d_len, priv->txhead, priv->txtail);
+  ninfo("d_len: %d txhead: %d txtail: %d\n",
+        dev->d_len, priv->txhead, priv->txtail);
   sam_dumppacket("Transmit packet", dev->d_buf, dev->d_len);
 
   /* Check parameter */
 
   if (dev->d_len > GMAC_TX_UNITSIZE)
     {
-      nllerr("ERROR: Packet too big: %d\n", dev->d_len);
+      nerr("ERROR: Packet too big: %d\n", dev->d_len);
       return -EINVAL;
     }
 
@@ -676,7 +676,7 @@ static int sam_transmit(struct sam_gmac_s *priv)
 
   if (sam_txfree(priv) < 1)
     {
-      nllerr("ERROR: No free TX descriptors\n");
+      nerr("ERROR: No free TX descriptors\n");
       return -EBUSY;
     }
 
@@ -738,7 +738,7 @@ static int sam_transmit(struct sam_gmac_s *priv)
 
   if (sam_txfree(priv) < 1)
     {
-      nllinfo("Disabling RX interrupts\n");
+      ninfo("Disabling RX interrupts\n");
       sam_putreg(priv, SAM_GMAC_IDR, GMAC_INT_RCOMP);
     }
 
@@ -918,7 +918,7 @@ static int sam_recvframe(struct sam_gmac_s *priv)
   arch_invalidate_dcache((uintptr_t)rxdesc,
                          (uintptr_t)rxdesc + sizeof(struct gmac_rxdesc_s));
 
-  nllinfo("rxndx: %d\n", rxndx);
+  ninfo("rxndx: %d\n", rxndx);
 
   while ((rxdesc->addr & GMACRXD_ADDR_OWNER) != 0)
     {
@@ -974,7 +974,7 @@ static int sam_recvframe(struct sam_gmac_s *priv)
         {
           if (rxndx == priv->rxndx)
             {
-              nllinfo("ERROR: No EOF (Invalid of buffers too small)\n");
+              nerr("ERROR: No EOF (Invalid of buffers too small)\n");
               do
                 {
                   /* Give ownership back to the GMAC */
@@ -1029,7 +1029,7 @@ static int sam_recvframe(struct sam_gmac_s *priv)
               /* Frame size from the GMAC */
 
               dev->d_len = (rxdesc->status & GMACRXD_STA_FRLEN_MASK);
-              nllinfo("packet %d-%d (%d)\n", priv->rxndx, rxndx, dev->d_len);
+              ninfo("packet %d-%d (%d)\n", priv->rxndx, rxndx, dev->d_len);
 
               /* All data have been copied in the application frame buffer,
                * release the RX descriptor
@@ -1060,11 +1060,11 @@ static int sam_recvframe(struct sam_gmac_s *priv)
                * all of the data.
                */
 
-              nllinfo("rxndx: %d d_len: %d\n", priv->rxndx, dev->d_len);
+              ninfo("rxndx: %d d_len: %d\n", priv->rxndx, dev->d_len);
 
               if (pktlen < dev->d_len)
                 {
-                  nllerr("ERROR: Buffer size %d; frame size %d\n", dev->d_len, pktlen);
+                  nerr("ERROR: Buffer size %d; frame size %d\n", dev->d_len, pktlen);
                   return -E2BIG;
                 }
 
@@ -1102,7 +1102,7 @@ static int sam_recvframe(struct sam_gmac_s *priv)
   /* No packet was found */
 
   priv->rxndx = rxndx;
-  nllinfo("rxndx: %d\n", priv->rxndx);
+  ninfo("rxndx: %d\n", priv->rxndx);
   return -EAGAIN;
 }
 
@@ -1142,7 +1142,7 @@ static void sam_receive(struct sam_gmac_s *priv)
 
       if (dev->d_len > CONFIG_NET_ETH_MTU)
         {
-          nllwarn("WARNING: Dropped, Too big: %d\n", dev->d_len);
+          nwarn("WARNING: Dropped, Too big: %d\n", dev->d_len);
           continue;
         }
 
@@ -1157,7 +1157,7 @@ static void sam_receive(struct sam_gmac_s *priv)
 #ifdef CONFIG_NET_IPv4
       if (BUF->type == HTONS(ETHTYPE_IP))
         {
-          nllinfo("IPv4 frame\n");
+          ninfo("IPv4 frame\n");
 
           /* Handle ARP on input then give the IPv4 packet to the network
            * layer
@@ -1197,7 +1197,7 @@ static void sam_receive(struct sam_gmac_s *priv)
 #ifdef CONFIG_NET_IPv6
       if (BUF->type == HTONS(ETHTYPE_IP6))
         {
-          nllinfo("Iv6 frame\n");
+          ninfo("Iv6 frame\n");
 
           /* Give the IPv6 packet to the network layer */
 
@@ -1234,7 +1234,7 @@ static void sam_receive(struct sam_gmac_s *priv)
 #ifdef CONFIG_NET_ARP
       if (BUF->type == htons(ETHTYPE_ARP))
         {
-          nllinfo("ARP frame\n");
+          ninfo("ARP frame\n");
 
           /* Handle ARP packet */
 
@@ -1252,7 +1252,7 @@ static void sam_receive(struct sam_gmac_s *priv)
       else
 #endif
         {
-          nllwarn("WARNING: Dropped, Unknown type: %04x\n", BUF->type);
+          nwarn("WARNING: Dropped, Unknown type: %04x\n", BUF->type);
         }
     }
 }
@@ -1377,7 +1377,7 @@ static int sam_gmac_interrupt(int irq, void *context)
   imr = sam_getreg(priv, SAM_GMAC_IMR);
 
   pending = isr & ~(imr | GMAC_INT_UNUSED);
-  nllinfo("isr: %08x pending: %08x\n", isr, pending);
+  ninfo("isr: %08x pending: %08x\n", isr, pending);
 
   /* Check for the completion of a transmission.  This should be done before
    * checking for received data (because receiving can cause another transmission
@@ -1403,7 +1403,7 @@ static int sam_gmac_interrupt(int irq, void *context)
           clrbits = GMAC_TSR_RLE | sam_txinuse(priv);
           sam_txreset(priv);
 
-          nllerr("ERROR: Retry Limit Exceeded TSR: %08x\n", tsr);
+          nerr("ERROR: Retry Limit Exceeded TSR: %08x\n", tsr);
 
           regval = sam_getreg(priv, SAM_GMAC_NCR);
           regval |= GMAC_NCR_TXEN;
@@ -1414,7 +1414,7 @@ static int sam_gmac_interrupt(int irq, void *context)
 
       if ((tsr & GMAC_TSR_COL) != 0)
         {
-          nllerr("ERROR: Collision occurred TSR: %08x\n", tsr);
+          nerr("ERROR: Collision occurred TSR: %08x\n", tsr);
           clrbits |= GMAC_TSR_COL;
         }
 
@@ -1422,7 +1422,7 @@ static int sam_gmac_interrupt(int irq, void *context)
 
       if ((tsr & GMAC_TSR_TFC) != 0)
         {
-          nllerr("ERROR: Buffers exhausted mid-frame TSR: %08x\n", tsr);
+          nerr("ERROR: Buffers exhausted mid-frame TSR: %08x\n", tsr);
           clrbits |= GMAC_TSR_TFC;
         }
 
@@ -1437,7 +1437,7 @@ static int sam_gmac_interrupt(int irq, void *context)
 
       if ((tsr & GMAC_TSR_UND) != 0)
         {
-          nllerr("ERROR: Transmit Underrun TSR: %08x\n", tsr);
+          nerr("ERROR: Transmit Underrun TSR: %08x\n", tsr);
           clrbits |= GMAC_TSR_UND;
         }
 
@@ -1445,7 +1445,7 @@ static int sam_gmac_interrupt(int irq, void *context)
 
       if ((tsr & GMAC_TSR_HRESP) != 0)
         {
-          nllerr("ERROR: HRESP not OK: %08x\n", tsr);
+          nerr("ERROR: HRESP not OK: %08x\n", tsr);
           clrbits |= GMAC_TSR_HRESP;
         }
 
@@ -1453,7 +1453,7 @@ static int sam_gmac_interrupt(int irq, void *context)
 
       if ((tsr & GMAC_TSR_LCO) != 0)
         {
-          nllerr("ERROR: Late collision: %08x\n", tsr);
+          nerr("ERROR: Late collision: %08x\n", tsr);
           clrbits |= GMAC_TSR_LCO;
         }
 
@@ -1490,7 +1490,7 @@ static int sam_gmac_interrupt(int irq, void *context)
 
       if ((rsr & GMAC_RSR_RXOVR) != 0)
         {
-          nllerr("ERROR: Receiver overrun RSR: %08x\n", rsr);
+          nerr("ERROR: Receiver overrun RSR: %08x\n", rsr);
           clrbits |= GMAC_RSR_RXOVR;
         }
 
@@ -1507,7 +1507,7 @@ static int sam_gmac_interrupt(int irq, void *context)
 
       if ((rsr & GMAC_RSR_BNA) != 0)
         {
-          nllerr("ERROR: Buffer not available RSR: %08x\n", rsr);
+          nerr("ERROR: Buffer not available RSR: %08x\n", rsr);
           clrbits |= GMAC_RSR_BNA;
         }
 
@@ -1515,7 +1515,7 @@ static int sam_gmac_interrupt(int irq, void *context)
 
       if ((rsr & GMAC_RSR_HNO) != 0)
         {
-          nllerr("ERROR: HRESP not OK: %08x\n", rsr);
+          nerr("ERROR: HRESP not OK: %08x\n", rsr);
           clrbits |= GMAC_RSR_HNO;
         }
 
@@ -1536,7 +1536,7 @@ static int sam_gmac_interrupt(int irq, void *context)
 
   if ((pending & GMAC_INT_PFNZ) != 0)
     {
-      nllwarn("WARNING: Pause frame received\n");
+      nwarn("WARNING: Pause frame received\n");
     }
 
   /* Check for Pause Time Zero (PTZ)
@@ -1546,7 +1546,7 @@ static int sam_gmac_interrupt(int irq, void *context)
 
   if ((pending & GMAC_INT_PTZ) != 0)
     {
-      nllwarn("WARNING: Pause TO!\n");
+      nwarn("WARNING: Pause TO!\n");
     }
 #endif
 
@@ -1576,7 +1576,7 @@ static void sam_txtimeout(int argc, uint32_t arg, ...)
 {
   struct sam_gmac_s *priv = (struct sam_gmac_s *)arg;
 
-  nllerr("ERROR: Timeout!\n");
+  nerr("ERROR: Timeout!\n");
 
   /* Then reset the hardware.  Just take the interface down, then back
    * up again.
@@ -1657,7 +1657,7 @@ static int sam_ifup(struct net_driver_s *dev)
 
   /* Configure the GMAC interface for normal operation. */
 
-  nllinfo("Initialize the GMAC\n");
+  ninfo("Initialize the GMAC\n");
   sam_gmac_configure(priv);
 
   /* Set the MAC address (should have been configured while we were down) */
@@ -1675,7 +1675,7 @@ static int sam_ifup(struct net_driver_s *dev)
   ret = sam_phyinit(priv);
   if (ret < 0)
     {
-      nllerr("ERROR: sam_phyinit failed: %d\n", ret);
+      nerr("ERROR: sam_phyinit failed: %d\n", ret);
       return ret;
     }
 
@@ -1685,7 +1685,7 @@ static int sam_ifup(struct net_driver_s *dev)
   ret = sam_autonegotiate(priv);
   if (ret < 0)
     {
-      nllerr("ERROR: sam_autonegotiate failed: %d\n", ret);
+      nerr("ERROR: sam_autonegotiate failed: %d\n", ret);
       return ret;
     }
 #else
@@ -1696,7 +1696,7 @@ static int sam_ifup(struct net_driver_s *dev)
 
   /* Enable normal MAC operation */
 
-  nllinfo("Enable normal operation\n");
+  ninfo("Enable normal operation\n");
 
   /* Set and activate a timer process */
 
@@ -1780,7 +1780,7 @@ static int sam_txavail(struct net_driver_s *dev)
   struct sam_gmac_s *priv = (struct sam_gmac_s *)dev->d_private;
   irqstate_t flags;
 
-  nllinfo("ifup: %d\n", priv->ifup);
+  ninfo("ifup: %d\n", priv->ifup);
 
   /* Disable interrupts because this function may be called from interrupt
    * level processing.
@@ -1958,8 +1958,8 @@ static int sam_addmac(struct net_driver_s *dev, const uint8_t *mac)
   unsigned int bit;
   UNUSED(priv);
 
-  nllinfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
-          mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+  ninfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
+        mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
 
   /* Calculate the 6-bit has table index */
 
@@ -2032,8 +2032,8 @@ static int sam_rmmac(struct net_driver_s *dev, const uint8_t *mac)
   unsigned int bit;
   UNUSED(priv);
 
-  nllinfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
-          mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+  ninfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
+        mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
 
   /* Calculate the 6-bit has table index */
 
@@ -2220,21 +2220,21 @@ static void sam_phydump(struct sam_gmac_s *priv)
 
   sam_enablemdio(priv);
 
-  nllinfo("GMII Registers (Address %02x)\n", priv->phyaddr);
+  ninfo("GMII Registers (Address %02x)\n", priv->phyaddr);
   sam_phyread(priv, priv->phyaddr, GMII_MCR, &phyval);
-  nllinfo("       MCR: %04x\n", phyval);
+  ninfo("       MCR: %04x\n", phyval);
   sam_phyread(priv, priv->phyaddr, GMII_MSR, &phyval);
-  nllinfo("       MSR: %04x\n", phyval);
+  ninfo("       MSR: %04x\n", phyval);
   sam_phyread(priv, priv->phyaddr, GMII_ADVERTISE, &phyval);
-  nllinfo(" ADVERTISE: %04x\n", phyval);
+  ninfo(" ADVERTISE: %04x\n", phyval);
   sam_phyread(priv, priv->phyaddr, GMII_LPA, &phyval);
-  nllinfo("       LPR: %04x\n", phyval);
+  ninfo("       LPR: %04x\n", phyval);
   sam_phyread(priv, priv->phyaddr, GMII_1000BTCR, &phyval);
-  nllinfo("  1000BTCR: %04x\n", phyval);
+  ninfo("  1000BTCR: %04x\n", phyval);
   sam_phyread(priv, priv->phyaddr, GMII_1000BTSR, &phyval);
-  nllinfo("  1000BTSR: %04x\n", phyval);
+  ninfo("  1000BTSR: %04x\n", phyval);
   sam_phyread(priv, priv->phyaddr, GMII_ESTATUS, &phyval);
-  nllinfo("   ESTATUS: %04x\n", phyval);
+  ninfo("   ESTATUS: %04x\n", phyval);
 
   /* Disable management port */
 
@@ -2418,7 +2418,7 @@ static int sam_phyreset(struct sam_gmac_s *priv)
   int timeout;
   int ret;
 
-  nllinfo(" sam_phyreset\n");
+  ninfo(" sam_phyreset\n");
 
   /* Enable management port */
 
@@ -2429,7 +2429,7 @@ static int sam_phyreset(struct sam_gmac_s *priv)
   ret = sam_phywrite(priv, priv->phyaddr, GMII_MCR, GMII_MCR_RESET);
   if (ret < 0)
     {
-      nllerr("ERROR: sam_phywrite failed: %d\n", ret);
+      nerr("ERROR: sam_phywrite failed: %d\n", ret);
     }
 
   /* Wait for the PHY reset to complete */
@@ -2441,7 +2441,7 @@ static int sam_phyreset(struct sam_gmac_s *priv)
       int result = sam_phyread(priv, priv->phyaddr, GMII_MCR, &mcr);
       if (result < 0)
         {
-          nllerr("ERROR: Failed to read the MCR register: %d\n", ret);
+          nerr("ERROR: Failed to read the MCR register: %d\n", ret);
           ret = result;
         }
       else if ((mcr & GMII_MCR_RESET) == 0)
@@ -2480,7 +2480,7 @@ static int sam_phyfind(struct sam_gmac_s *priv, uint8_t *phyaddr)
   unsigned int offset;
   int ret = -ESRCH;
 
-  nllinfo("Find a valid PHY address\n");
+  ninfo("Find a valid PHY address\n");
 
   /* Enable management port */
 
@@ -2501,8 +2501,8 @@ static int sam_phyfind(struct sam_gmac_s *priv, uint8_t *phyaddr)
 
   else
     {
-      nllerr("ERROR: sam_phyread failed for PHY address %02x: %d\n",
-             candidate, ret);
+      nerr("ERROR: sam_phyread failed for PHY address %02x: %d\n",
+           candidate, ret);
 
       for (offset = 0; offset < 32; offset++)
         {
@@ -2523,7 +2523,7 @@ static int sam_phyfind(struct sam_gmac_s *priv, uint8_t *phyaddr)
 
   if (ret == OK)
     {
-      nllinfo("  PHYID1: %04x PHY addr: %d\n", phyval, candidate);
+      ninfo("  PHYID1: %04x PHY addr: %d\n", phyval, candidate);
       *phyaddr = candidate;
     }
 
@@ -2563,7 +2563,7 @@ static int sam_phyread(struct sam_gmac_s *priv, uint8_t phyaddr,
   ret = sam_phywait(priv);
   if (ret < 0)
     {
-      nllerr("ERROR: sam_phywait failed: %d\n", ret);
+      nerr("ERROR: sam_phywait failed: %d\n", ret);
       return ret;
     }
 
@@ -2578,7 +2578,7 @@ static int sam_phyread(struct sam_gmac_s *priv, uint8_t phyaddr,
   ret = sam_phywait(priv);
   if (ret < 0)
     {
-      nllerr("ERROR: sam_phywait failed: %d\n", ret);
+      nerr("ERROR: sam_phywait failed: %d\n", ret);
       return ret;
     }
 
@@ -2618,7 +2618,7 @@ static int sam_phywrite(struct sam_gmac_s *priv, uint8_t phyaddr,
   ret = sam_phywait(priv);
   if (ret < 0)
     {
-      nllerr("ERROR: sam_phywait failed: %d\n", ret);
+      nerr("ERROR: sam_phywait failed: %d\n", ret);
       return ret;
     }
 
@@ -2633,7 +2633,7 @@ static int sam_phywrite(struct sam_gmac_s *priv, uint8_t phyaddr,
   ret = sam_phywait(priv);
   if (ret < 0)
     {
-      nllerr("ERROR: sam_phywait failed: %d\n", ret);
+      nerr("ERROR: sam_phywait failed: %d\n", ret);
       return ret;
     }
 
@@ -2679,35 +2679,35 @@ static int sam_autonegotiate(struct sam_gmac_s *priv)
   ret = sam_phyread(priv, priv->phyaddr, GMII_PHYID1, &phyid1);
   if (ret < 0)
     {
-      nllerr("ERROR: Failed to read PHYID1 register\n");
+      nerr("ERROR: Failed to read PHYID1 register\n");
       goto errout;
     }
 
-  nllinfo("PHYID1: %04x PHY address: %02x\n", phyid1, priv->phyaddr);
+  ninfo("PHYID1: %04x PHY address: %02x\n", phyid1, priv->phyaddr);
 
   /* Read the LS bits of the OUI from Pthe PHYID2 register */
 
   ret = sam_phyread(priv, priv->phyaddr, GMII_PHYID2, &phyid2);
   if (ret < 0)
     {
-      nllerr("ERROR: Failed to read PHYID2 register\n");
+      nerr("ERROR: Failed to read PHYID2 register\n");
       goto errout;
     }
 
-  nllinfo("PHYID2: %04x PHY address: %02x\n", phyid2, priv->phyaddr);
+  ninfo("PHYID2: %04x PHY address: %02x\n", phyid2, priv->phyaddr);
 
   if (phyid1 == GMII_OUI_MSB &&
      (phyid2 & GMII_PHYID2_OUI_MASK) == GMII_OUI_LSB)
     {
-      nllinfo("  Vendor Model Number:   %04x\n",
-             (phyid2 & GMII_PHYID2_MODEL_MASK) >> GMII_PHYID2_MODEL_SHIFT);
-      nllinfo("  Model Revision Number: %04x\n",
-             (phyid2 & GMII_PHYID2_REV_MASK) >> GMII_PHYID2_REV_SHIFT);
+      ninfo("  Vendor Model Number:   %04x\n",
+           (phyid2 & GMII_PHYID2_MODEL_MASK) >> GMII_PHYID2_MODEL_SHIFT);
+      ninfo("  Model Revision Number: %04x\n",
+           (phyid2 & GMII_PHYID2_REV_MASK) >> GMII_PHYID2_REV_SHIFT);
     }
   else
     {
-      nllerr("ERROR: PHY not recognized: PHYID1=%04x PHYID2=%04x\n",
-              phyid1, phyid2);
+      nerr("ERROR: PHY not recognized: PHYID1=%04x PHYID2=%04x\n",
+            phyid1, phyid2);
     }
 
 #ifdef SAMA5_GMAC_PHY_KSZ90x1
@@ -2735,7 +2735,7 @@ static int sam_autonegotiate(struct sam_gmac_s *priv)
   ret = sam_phywrite(priv, priv->phyaddr, GMII_ADVERTISE, advertise);
   if (ret < 0)
     {
-      nllerr("ERROR: Failed to write ADVERTISE register\n");
+      nerr("ERROR: Failed to write ADVERTISE register\n");
       goto errout;
     }
 
@@ -2746,7 +2746,7 @@ static int sam_autonegotiate(struct sam_gmac_s *priv)
   ret = sam_phyread(priv, priv->phyaddr, GMII_1000BTCR, &btcr);
   if (ret < 0)
     {
-      nllerr("ERROR: Failed to read 1000BTCR register: %d\n", ret);
+      nerr("ERROR: Failed to read 1000BTCR register: %d\n", ret);
       goto errout;
     }
 
@@ -2755,7 +2755,7 @@ static int sam_autonegotiate(struct sam_gmac_s *priv)
   ret = sam_phywrite(priv, priv->phyaddr, GMII_1000BTCR, btcr);
   if (ret < 0)
     {
-      nllerr("ERROR: Failed to write 1000BTCR register: %d\n", ret);
+      nerr("ERROR: Failed to write 1000BTCR register: %d\n", ret);
       goto errout;
     }
 
@@ -2764,7 +2764,7 @@ static int sam_autonegotiate(struct sam_gmac_s *priv)
   ret  = sam_phyread(priv, priv->phyaddr, GMII_MCR, &phyval);
   if (ret < 0)
     {
-      nllerr("ERROR: Failed to read MCR register: %d\n", ret);
+      nerr("ERROR: Failed to read MCR register: %d\n", ret);
       goto errout;
     }
 
@@ -2773,11 +2773,11 @@ static int sam_autonegotiate(struct sam_gmac_s *priv)
   ret = sam_phywrite(priv, priv->phyaddr, GMII_MCR, phyval);
   if (ret < 0)
     {
-      nllerr("ERROR: Failed to write MCR register: %d\n", ret);
+      nerr("ERROR: Failed to write MCR register: %d\n", ret);
       goto errout;
     }
 
-  nllinfo(" MCR: 0x%X\n", phyval);
+  ninfo(" MCR: 0x%X\n", phyval);
 
   /* Wait for autonegotion to complete */
 
@@ -2787,7 +2787,7 @@ static int sam_autonegotiate(struct sam_gmac_s *priv)
       ret  = sam_phyread(priv, priv->phyaddr, GMII_MSR, &phyval);
       if (ret < 0)
         {
-          nllerr("ERROR: Failed to read MSR register: %d\n", ret);
+          nerr("ERROR: Failed to read MSR register: %d\n", ret);
           goto errout;
         }
 
@@ -2797,7 +2797,7 @@ static int sam_autonegotiate(struct sam_gmac_s *priv)
         {
           /* Yes.. break out of the loop */
 
-          nllinfo("AutoNegotiate complete\n");
+          ninfo("AutoNegotiate complete\n");
           break;
         }
 
@@ -2805,7 +2805,7 @@ static int sam_autonegotiate(struct sam_gmac_s *priv)
 
       if (++timeout >= PHY_RETRY_MAX)
         {
-          nllerr("ERROR: TimeOut\n");
+          nerr("ERROR: TimeOut\n");
           sam_phydump(priv);
           ret = -ETIMEDOUT;
           goto errout;
@@ -2822,7 +2822,7 @@ static int sam_autonegotiate(struct sam_gmac_s *priv)
       ret  = sam_phyread(priv, priv->phyaddr, GMII_1000BTSR, &btsr);
       if (ret < 0)
         {
-          nllerr("ERROR: Failed to read 1000BTSR register: %d\n", ret);
+          nerr("ERROR: Failed to read 1000BTSR register: %d\n", ret);
           goto errout;
         }
 
@@ -2850,7 +2850,7 @@ static int sam_autonegotiate(struct sam_gmac_s *priv)
       ret  = sam_phyread(priv, priv->phyaddr, GMII_LPA, &lpa);
       if (ret < 0)
         {
-          nllerr("ERROR: Failed to read LPA register: %d\n", ret);
+          nerr("ERROR: Failed to read LPA register: %d\n", ret);
           goto errout;
         }
 
@@ -2892,7 +2892,7 @@ static int sam_autonegotiate(struct sam_gmac_s *priv)
 
       if (++timeout >= PHY_RETRY_MAX)
         {
-          nllerr("ERROR: TimeOut\n");
+          nerr("ERROR: TimeOut\n");
           sam_phydump(priv);
           ret = -ETIMEDOUT;
           goto errout;
@@ -3065,7 +3065,7 @@ static int sam_phyinit(struct sam_gmac_s *priv)
   ret = sam_phyfind(priv, &priv->phyaddr);
   if (ret < 0)
     {
-      nllerr("ERROR: sam_phyfind failed: %d\n", ret);
+      nerr("ERROR: sam_phyfind failed: %d\n", ret);
       return ret;
     }
 
@@ -3324,11 +3324,11 @@ static void sam_macaddress(struct sam_gmac_s *priv)
   struct net_driver_s *dev = &priv->dev;
   uint32_t regval;
 
-  nllinfo("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
-          dev->d_ifname,
-          dev->d_mac.ether_addr_octet[0], dev->d_mac.ether_addr_octet[1],
-          dev->d_mac.ether_addr_octet[2], dev->d_mac.ether_addr_octet[3],
-          dev->d_mac.ether_addr_octet[4], dev->d_mac.ether_addr_octet[5]);
+  ninfo("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
+        dev->d_ifname,
+        dev->d_mac.ether_addr_octet[0], dev->d_mac.ether_addr_octet[1],
+        dev->d_mac.ether_addr_octet[2], dev->d_mac.ether_addr_octet[3],
+        dev->d_mac.ether_addr_octet[4], dev->d_mac.ether_addr_octet[5]);
 
   /* Set the MAC address */
 
@@ -3436,7 +3436,7 @@ static int sam_gmac_configure(struct sam_gmac_s *priv)
 {
   uint32_t regval;
 
-  nllinfo("Entry\n");
+  ninfo("Entry\n");
 
   /* Enable clocking to the GMAC peripheral */
 
@@ -3573,7 +3573,7 @@ int sam_gmac_initialize(void)
   priv->txpoll = wd_create();
   if (!priv->txpoll)
     {
-      nllerr("ERROR: Failed to create periodic poll timer\n");
+      nerr("ERROR: Failed to create periodic poll timer\n");
       ret = -EAGAIN;
       goto errout;
     }
@@ -3581,7 +3581,7 @@ int sam_gmac_initialize(void)
   priv->txtimeout = wd_create();         /* Create TX timeout timer */
   if (!priv->txtimeout)
     {
-      nllerr("ERROR: Failed to create periodic poll timer\n");
+      nerr("ERROR: Failed to create periodic poll timer\n");
       ret = -EAGAIN;
       goto errout_with_txpoll;
     }
@@ -3595,7 +3595,7 @@ int sam_gmac_initialize(void)
   ret = sam_buffer_initialize(priv);
   if (ret < 0)
     {
-      nllerr("ERROR: sam_buffer_initialize failed: %d\n", ret);
+      nerr("ERROR: sam_buffer_initialize failed: %d\n", ret);
       goto errout_with_txtimeout;
     }
 
@@ -3606,7 +3606,7 @@ int sam_gmac_initialize(void)
   ret = irq_attach(SAM_IRQ_GMAC, sam_gmac_interrupt);
   if (ret < 0)
     {
-      nllerr("ERROR: Failed to attach the handler to the IRQ%d\n", SAM_IRQ_GMAC);
+      nerr("ERROR: Failed to attach the handler to the IRQ%d\n", SAM_IRQ_GMAC);
       goto errout_with_buffers;
     }
 
@@ -3619,7 +3619,7 @@ int sam_gmac_initialize(void)
   ret = sam_ifdown(&priv->dev);
   if (ret < 0)
     {
-      nllerr("ERROR: Failed to put the interface in the down state: %d\n", ret);
+      nerr("ERROR: Failed to put the interface in the down state: %d\n", ret);
       goto errout_with_buffers;
     }
 
@@ -3631,7 +3631,7 @@ int sam_gmac_initialize(void)
       return ret;
     }
 
-  nllerr("ERROR: netdev_register() failed: %d\n", ret);
+  nerr("ERROR: netdev_register() failed: %d\n", ret);
 
 errout_with_buffers:
   sam_buffer_free(priv);
diff --git a/arch/arm/src/sama5/sam_hsmci.c b/arch/arm/src/sama5/sam_hsmci.c
index db8054fe2d4..2b4eb8361a3 100644
--- a/arch/arm/src/sama5/sam_hsmci.c
+++ b/arch/arm/src/sama5/sam_hsmci.c
@@ -1241,7 +1241,7 @@ static void sam_dmacallback(DMA_HANDLE handle, void *arg, int result)
       if (result < 0)
         {
           wkupevent = (result == -ETIMEDOUT ? SDIOWAIT_TIMEOUT : SDIOWAIT_ERROR);
-          fllerr("ERROR: DMA failed: result=%d wkupevent=%04x\n", result, wkupevent);
+          mcerr("ERROR: DMA failed: result=%d wkupevent=%04x\n", result, wkupevent);
 
           /* sam_endtransfer will terminate the transfer and wait up the waiting
            * client in this case.
@@ -1341,7 +1341,7 @@ static void sam_eventtimeout(int argc, uint32_t arg)
       /* Yes.. wake up any waiting threads */
 
       sam_endwait(priv, SDIOWAIT_TIMEOUT);
-      fllerr("ERROR: Timeout\n");
+      mcerr("ERROR: Timeout\n");
     }
 }
 
@@ -1541,7 +1541,7 @@ static int sam_hsmci_interrupt(struct sam_dev_s *priv)
             {
               /* Yes.. Was it some kind of timeout error? */
 
-              fllerr("ERROR: enabled: %08x pending: %08x\n", enabled, pending);
+              mcerr("ERROR: enabled: %08x pending: %08x\n", enabled, pending);
               if ((pending & HSMCI_DATA_TIMEOUT_ERRORS) != 0)
                 {
                   /* Yes.. Terminate with a timeout. */
@@ -1613,8 +1613,8 @@ static int sam_hsmci_interrupt(struct sam_dev_s *priv)
                 {
                   /* Yes.. Was the error some kind of timeout? */
 
-                  fllinfo("ERROR: events: %08x SR: %08x\n",
-                          priv->cmdrmask, enabled);
+                  mcerr("ERROR: events: %08x SR: %08x\n",
+                        priv->cmdrmask, enabled);
 
                   if ((pending & HSMCI_RESPONSE_TIMEOUT_ERRORS) != 0)
                     {
@@ -2094,7 +2094,7 @@ static int sam_sendcmd(FAR struct sdio_dev_s *dev,
 
   /* Write the fully decorated command to CMDR */
 
-  finfo("cmd: %08x arg: %08x regval: %08x\n", cmd, arg, regval);
+  mcinfo("cmd: %08x arg: %08x regval: %08x\n", cmd, arg, regval);
   sam_putreg(priv, regval, SAM_HSMCI_CMDR_OFFSET);
   sam_cmdsample1(priv, SAMPLENDX_AFTER_CMDR);
   return OK;
@@ -2816,7 +2816,7 @@ static void sam_callbackenable(FAR struct sdio_dev_s *dev,
 {
   struct sam_dev_s *priv = (struct sam_dev_s *)dev;
 
-  finfo("eventset: %02x\n", eventset);
+  mcinfo("eventset: %02x\n", eventset);
   DEBUGASSERT(priv != NULL);
 
   priv->cbevents = eventset;
@@ -2852,7 +2852,7 @@ static int sam_registercallback(FAR struct sdio_dev_s *dev,
 
   /* Disable callbacks and register this callback and is argument */
 
-  finfo("Register %p(%p)\n", callback, arg);
+  mcinfo("Register %p(%p)\n", callback, arg);
   DEBUGASSERT(priv != NULL);
 
   priv->cbevents = 0;
@@ -3099,8 +3099,8 @@ static void sam_callback(void *arg)
   /* Is a callback registered? */
 
   DEBUGASSERT(priv != NULL);
-  finfo("Callback %p(%p) cbevents: %02x cdstatus: %02x\n",
-        priv->callback, priv->cbarg, priv->cbevents, priv->cdstatus);
+  mcinfo("Callback %p(%p) cbevents: %02x cdstatus: %02x\n",
+         priv->callback, priv->cbarg, priv->cbevents, priv->cdstatus);
 
   flags = enter_critical_section();
   if (priv->callback)
@@ -3157,7 +3157,7 @@ static void sam_callback(void *arg)
           lcderr("ERROR: Failed to cancel work: %d\n", ret);
         }
 
-      fllinfo("Queuing callback to %p(%p)\n", priv->callback, priv->cbarg);
+      mcinfo("Queuing callback to %p(%p)\n", priv->callback, priv->cbarg);
       ret = work_queue(LPWORK, &priv->cbwork, (worker_t)priv->callback,
                        priv->cbarg, 0);
       if (ret < 0)
@@ -3327,8 +3327,8 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno)
       return NULL;
     }
 
-  finfo("priv: %p base: %08x hsmci: %d dmac: %d pid: %d\n",
-        priv, priv->base, priv->hsmci, dmac, pid);
+  mcinfo("priv: %p base: %08x hsmci: %d dmac: %d pid: %d\n",
+         priv, priv->base, priv->hsmci, dmac, pid);
 
   /* Initialize the HSMCI slot structure */
 
@@ -3397,7 +3397,7 @@ void sdio_mediachange(FAR struct sdio_dev_s *dev, bool cardinslot)
       priv->cdstatus &= ~SDIO_STATUS_PRESENT;
     }
 
-  fllinfo("cdstatus OLD: %02x NEW: %02x\n", cdstatus, priv->cdstatus);
+  mcinfo("cdstatus OLD: %02x NEW: %02x\n", cdstatus, priv->cdstatus);
 
   /* Perform any requested callback if the status has changed */
 
@@ -3442,7 +3442,7 @@ void sdio_wrprotect(FAR struct sdio_dev_s *dev, bool wrprotect)
       priv->cdstatus &= ~SDIO_STATUS_WRPROTECTED;
     }
 
-  finfo("cdstatus: %02x\n", priv->cdstatus);
+  mcinfo("cdstatus: %02x\n", priv->cdstatus);
   leave_critical_section(flags);
 }
 
diff --git a/arch/arm/src/sama5/sam_nand.c b/arch/arm/src/sama5/sam_nand.c
index f063f22fb2b..0e6757c073e 100644
--- a/arch/arm/src/sama5/sam_nand.c
+++ b/arch/arm/src/sama5/sam_nand.c
@@ -999,7 +999,7 @@ static uint32_t nand_nfc_poll(void)
   sr = nand_getreg(SAM_HSMC_SR);
 
 #ifndef CONFIG_SAMA5_NAND_REGDEBUG
-  // fllinfo("sr=%08x\n", sr);
+  // finfo("sr=%08x\n", sr);
 #endif
 
   /* When set to one, this XFRDONE indicates that the NFC has terminated
@@ -1065,7 +1065,7 @@ static int hsmc_interrupt(int irq, void *context)
   uint32_t pending = sr & imr;
 
 #ifndef CONFIG_SAMA5_NAND_REGDEBUG
-  fllinfo("sr=%08x imr=%08x\n", sr, imr);
+  finfo("sr=%08x imr=%08x\n", sr, imr);
 #endif
 
   /* When set to one, this XFRDONE indicates that the NFC has terminated
diff --git a/arch/arm/src/sama5/sam_ohci.c b/arch/arm/src/sama5/sam_ohci.c
index bd3ec0b233b..7d4533dca68 100644
--- a/arch/arm/src/sama5/sam_ohci.c
+++ b/arch/arm/src/sama5/sam_ohci.c
@@ -3784,7 +3784,7 @@ static int sam_connect(struct usbhost_driver_s *drvr,
   /* Set the connected/disconnected flag */
 
   hport->connected = connected;
-  ullinfo("Hub port %d connected: %s\n", hport->port, connected ? "YES" : "NO");
+  uinfo("Hub port %d connected: %s\n", hport->port, connected ? "YES" : "NO");
 
   /* Report the connection event */
 
diff --git a/arch/arm/src/sama5/sam_oneshot.c b/arch/arm/src/sama5/sam_oneshot.c
index fc1985a45cc..5f011ea2874 100644
--- a/arch/arm/src/sama5/sam_oneshot.c
+++ b/arch/arm/src/sama5/sam_oneshot.c
@@ -108,7 +108,7 @@ static void sam_oneshot_handler(TC_HANDLE tch, void *arg, uint32_t sr)
   oneshot_handler_t oneshot_handler;
   void *oneshot_arg;
 
-  tmrllinfo("Expired...\n");
+  tmrinfo("Expired...\n");
   DEBUGASSERT(oneshot && oneshot->handler);
 
   /* The clock was stopped, but not disabled when the RC match occurred.
diff --git a/arch/arm/src/sama5/sam_rtc.c b/arch/arm/src/sama5/sam_rtc.c
index d710ff711f6..e73e473b706 100644
--- a/arch/arm/src/sama5/sam_rtc.c
+++ b/arch/arm/src/sama5/sam_rtc.c
@@ -265,7 +265,7 @@ static int rtc_interrupt(int irq, void *context)
   ret = work_queue(LPWORK, &g_alarmwork, rtc_worker, NULL, 0);
   if (ret < 0)
     {
-      rtcllerr("ERROR: work_queue failed: %d\n", ret);
+      rtcerr("ERROR: work_queue failed: %d\n", ret);
     }
 
   /* Disable any further alarm interrupts */
diff --git a/arch/arm/src/sama5/sam_ssc.c b/arch/arm/src/sama5/sam_ssc.c
index ff50c3988e8..8e4e66a0327 100644
--- a/arch/arm/src/sama5/sam_ssc.c
+++ b/arch/arm/src/sama5/sam_ssc.c
@@ -847,12 +847,12 @@ static void ssc_dump_queue(sq_queue_t *queue)
 
       if (!apb)
         {
-          i2sllinfo("    %p: No buffer\n", bfcontainer);
+          i2sinfo("    %p: No buffer\n", bfcontainer);
         }
       else
         {
-          i2sllinfo("    %p: buffer=%p nmaxbytes=%d nbytes=%d\n",
-                    bfcontainer, apb, apb->nmaxbytes, apb->nbytes);
+          i2sinfo("    %p: buffer=%p nmaxbytes=%d nbytes=%d\n",
+                  bfcontainer, apb, apb->nmaxbytes, apb->nbytes);
         }
     }
 }
@@ -862,12 +862,12 @@ static void ssc_dump_queues(struct sam_transport_s *xpt, const char *msg)
   irqstate_t flags;
 
   flags = enter_critical_section();
-  i2sllinfo("%s\n", msg);
-  i2sllinfo("  Pending:\n");
+  i2sinfo("%s\n", msg);
+  i2sinfo("  Pending:\n");
   ssc_dump_queue(&xpt->pend);
-  i2sllinfo("  Active:\n");
+  i2sinfo("  Active:\n");
   ssc_dump_queue(&xpt->act);
-  i2sllinfo("  Done:\n");
+  i2sinfo("  Done:\n");
   ssc_dump_queue(&xpt->done);
   leave_critical_section(flags);
 }
@@ -1377,7 +1377,7 @@ static int ssc_rxdma_setup(struct sam_ssc_s *priv)
 
       if (ret < 0)
         {
-          i2sllerr("ERROR: wd_start failed: %d\n", errno);
+          i2serr("ERROR: wd_start failed: %d\n", errno);
         }
     }
 
@@ -1565,7 +1565,7 @@ static void ssc_rx_schedule(struct sam_ssc_s *priv, int result)
       ret = work_queue(HPWORK, &priv->rx.work, ssc_rx_worker, priv, 0);
       if (ret != 0)
         {
-          i2sllerr("ERROR: Failed to queue RX work: %d\n", ret);
+          i2serr("ERROR: Failed to queue RX work: %d\n", ret);
         }
     }
 }
@@ -1790,7 +1790,7 @@ static int ssc_txdma_setup(struct sam_ssc_s *priv)
 
       if (ret < 0)
         {
-          i2sllerr("ERROR: wd_start failed: %d\n", errno);
+          i2serr("ERROR: wd_start failed: %d\n", errno);
         }
     }
 
@@ -1965,7 +1965,7 @@ static void ssc_tx_schedule(struct sam_ssc_s *priv, int result)
       ret = work_queue(HPWORK, &priv->tx.work, ssc_tx_worker, priv, 0);
       if (ret != 0)
         {
-          i2sllerr("ERROR: Failed to queue TX work: %d\n", ret);
+          i2serr("ERROR: Failed to queue TX work: %d\n", ret);
         }
     }
 }
diff --git a/arch/arm/src/sama5/sam_tc.c b/arch/arm/src/sama5/sam_tc.c
index fc0bc9c8766..7d8e19370cc 100644
--- a/arch/arm/src/sama5/sam_tc.c
+++ b/arch/arm/src/sama5/sam_tc.c
@@ -562,7 +562,7 @@ static bool sam_checkreg(struct sam_tc_s *tc, bool wr, uint32_t regaddr,
         {
           /* Yes... show how many times we did it */
 
-          tminfo("...[Repeats %d times]...\n", tc->ntimes);
+          tmrinfo("...[Repeats %d times]...\n", tc->ntimes);
         }
 
       /* Save information about the new access */
@@ -597,7 +597,7 @@ static inline uint32_t sam_tc_getreg(struct sam_chan_s *chan,
 #ifdef CONFIG_SAMA5_TC_REGDEBUG
   if (sam_checkreg(tc, false, regaddr, regval))
     {
-      tminfo("%08x->%08x\n", regaddr, regval);
+      tmrinfo("%08x->%08x\n", regaddr, regval);
     }
 #endif
 
@@ -621,7 +621,7 @@ static inline void sam_tc_putreg(struct sam_chan_s *chan, uint32_t regval,
 #ifdef CONFIG_SAMA5_TC_REGDEBUG
   if (sam_checkreg(tc, true, regaddr, regval))
     {
-      tminfo("%08x<-%08x\n", regaddr, regval);
+      tmrinfo("%08x<-%08x\n", regaddr, regval);
     }
 #endif
 
@@ -645,7 +645,7 @@ static inline uint32_t sam_chan_getreg(struct sam_chan_s *chan,
 #ifdef CONFIG_SAMA5_TC_REGDEBUG
   if (sam_checkreg(chan->tc, false, regaddr, regval))
     {
-      tminfo("%08x->%08x\n", regaddr, regval);
+      tmrinfo("%08x->%08x\n", regaddr, regval);
     }
 #endif
 
@@ -668,7 +668,7 @@ static inline void sam_chan_putreg(struct sam_chan_s *chan, unsigned int offset,
 #ifdef CONFIG_SAMA5_TC_REGDEBUG
   if (sam_checkreg(chan->tc, true, regaddr, regval))
     {
-      tminfo("%08x<-%08x\n", regaddr, regval);
+      tmrinfo("%08x<-%08x\n", regaddr, regval);
     }
 #endif
 
diff --git a/arch/arm/src/sama5/sam_tickless.c b/arch/arm/src/sama5/sam_tickless.c
index d3a1d34e011..4ae30bf7185 100644
--- a/arch/arm/src/sama5/sam_tickless.c
+++ b/arch/arm/src/sama5/sam_tickless.c
@@ -209,7 +209,7 @@ static struct sam_tickless_s g_tickless;
 
 static void sam_oneshot_handler(void *arg)
 {
-  tmrllinfo("Expired...\n");
+  tmrinfo("Expired...\n");
   sched_timer_expiration();
 }
 
@@ -256,7 +256,7 @@ void up_timer_initialize(void)
                                CONFIG_USEC_PER_TICK);
   if (ret < 0)
     {
-      tmrllerr("ERROR: sam_oneshot_initialize failed\n");
+      tmrerr("ERROR: sam_oneshot_initialize failed\n");
       PANIC();
     }
 
@@ -268,7 +268,7 @@ void up_timer_initialize(void)
   ret = sam_oneshot_max_delay(&g_tickless.oneshot, &max_delay);
   if (ret < 0)
     {
-      tmrllerr("ERROR: sam_oneshot_max_delay failed\n");
+      tmrerr("ERROR: sam_oneshot_max_delay failed\n");
       PANIC();
     }
 
@@ -292,7 +292,7 @@ void up_timer_initialize(void)
                                CONFIG_USEC_PER_TICK);
   if (ret < 0)
     {
-      tmrllerr("ERROR: sam_freerun_initialize failed\n");
+      tmrerr("ERROR: sam_freerun_initialize failed\n");
       PANIC();
     }
 
diff --git a/arch/arm/src/sama5/sam_tsd.c b/arch/arm/src/sama5/sam_tsd.c
index 9961cbee74c..edb2199f36c 100644
--- a/arch/arm/src/sama5/sam_tsd.c
+++ b/arch/arm/src/sama5/sam_tsd.c
@@ -799,7 +799,7 @@ static int sam_tsd_schedule(struct sam_tsd_s *priv)
   ret = work_queue(HPWORK, &priv->work, sam_tsd_bottomhalf, priv, 0);
   if (ret != 0)
     {
-      illerr("ERROR: Failed to queue work: %d\n", ret);
+      ierr("ERROR: Failed to queue work: %d\n", ret);
     }
 
   return OK;
diff --git a/arch/arm/src/sama5/sam_twi.c b/arch/arm/src/sama5/sam_twi.c
index a15ec4e1b1e..4af5f702b0b 100644
--- a/arch/arm/src/sama5/sam_twi.c
+++ b/arch/arm/src/sama5/sam_twi.c
@@ -563,7 +563,7 @@ static int twi_interrupt(struct twi_dev_s *priv)
   imr     = twi_getrel(priv, SAM_TWI_IMR_OFFSET);
   pending = sr & imr;
 
-  i2cllinfo("TWI%d pending: %08x\n", priv->attr->twi, pending);
+  i2cinfo("TWI%d pending: %08x\n", priv->attr->twi, pending);
 
   /* Byte received */
 
@@ -659,7 +659,7 @@ static int twi_interrupt(struct twi_dev_s *priv)
     {
       /* Wake up the thread with an I/O error indication */
 
-      i2cllerr("ERROR: TWI%d pending: %08x\n", priv->attr->twi, pending);
+      i2cerr("ERROR: TWI%d pending: %08x\n", priv->attr->twi, pending);
       twi_wakeup(priv, -EIO);
     }
 
@@ -709,7 +709,7 @@ static void twi_timeout(int argc, uint32_t arg, ...)
 {
   struct twi_dev_s *priv = (struct twi_dev_s *)arg;
 
-  i2cllerr("ERROR: TWI%d Timeout!\n", priv->attr->twi);
+  i2cerr("ERROR: TWI%d Timeout!\n", priv->attr->twi);
   twi_wakeup(priv, -ETIMEDOUT);
 }
 
diff --git a/arch/arm/src/sama5/sam_udphs.c b/arch/arm/src/sama5/sam_udphs.c
index b7e4b60357f..76f704d1f69 100644
--- a/arch/arm/src/sama5/sam_udphs.c
+++ b/arch/arm/src/sama5/sam_udphs.c
@@ -1353,9 +1353,9 @@ static int sam_req_write(struct sam_usbdev_s *priv, struct sam_ep_s *privep)
           return -ENOENT;
         }
 
-      ullinfo("epno=%d req=%p: len=%d xfrd=%d inflight=%d zlpneeded=%d\n",
-              epno, privreq, privreq->req.len, privreq->req.xfrd,
-              privreq->inflight, privep->zlpneeded);
+      uinfo("epno=%d req=%p: len=%d xfrd=%d inflight=%d zlpneeded=%d\n",
+            epno, privreq, privreq->req.len, privreq->req.xfrd,
+            privreq->inflight, privep->zlpneeded);
 
       /* Handle any bytes in flight. */
 
@@ -1596,8 +1596,8 @@ static int sam_req_read(struct sam_usbdev_s *priv, struct sam_ep_s *privep,
           return -ENOENT;
         }
 
-      ullinfo("EP%d: len=%d xfrd=%d\n",
-              epno, privreq->req.len, privreq->req.xfrd);
+      uinfo("EP%d: len=%d xfrd=%d\n",
+            epno, privreq->req.len, privreq->req.xfrd);
 
       /* Ignore any attempt to receive a zero length packet */
 
@@ -1881,8 +1881,8 @@ static void sam_ep0_setup(struct sam_usbdev_s *priv)
   index.w = GETUINT16(priv->ctrl.index);
   len.w   = GETUINT16(priv->ctrl.len);
 
-  ullinfo("SETUP: type=%02x req=%02x value=%04x index=%04x len=%04x\n",
-          priv->ctrl.type, priv->ctrl.req, value.w, index.w, len.w);
+  uinfo("SETUP: type=%02x req=%02x value=%04x index=%04x len=%04x\n",
+        priv->ctrl.type, priv->ctrl.req, value.w, index.w, len.w);
 
   /* Dispatch any non-standard requests */
 
@@ -2045,7 +2045,7 @@ static void sam_ep0_setup(struct sam_usbdev_s *priv)
           {
             /* Special case recipient=device test mode */
 
-            ullinfo("test mode: %d\n", index.w);
+            uinfo("test mode: %d\n", index.w);
           }
         else if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) != USB_REQ_RECIPIENT_ENDPOINT)
           {
@@ -3436,7 +3436,7 @@ static int sam_ep_disable(struct usbdev_ep_s *ep)
   if (!ep)
     {
       usbtrace(TRACE_DEVERROR(SAM_TRACEERR_INVALIDPARMS), 0);
-      ullerr("ERROR: ep=%p\n", ep);
+      uerr("ERROR: ep=%p\n", ep);
       return -EINVAL;
     }
 #endif
@@ -3568,7 +3568,8 @@ static int sam_ep_submit(struct usbdev_ep_s *ep, struct usbdev_req_s *req)
   if (!req || !req->callback || !req->buf || !ep)
     {
       usbtrace(TRACE_DEVERROR(SAM_TRACEERR_INVALIDPARMS), 0);
-      ullerr("ERROR: req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, ep);
+      uerr("ERROR: req=%p callback=%p buf=%p ep=%p\n",
+           req, req->callback, req->buf, ep);
       return -EINVAL;
     }
 #endif
@@ -3580,7 +3581,7 @@ static int sam_ep_submit(struct usbdev_ep_s *ep, struct usbdev_req_s *req)
   if (!priv->driver)
     {
       usbtrace(TRACE_DEVERROR(SAM_TRACEERR_NOTCONFIGURED), priv->usbdev.speed);
-      ullerr("ERROR: driver=%p\n", priv->driver);
+      uerr("ERROR: driver=%p\n", priv->driver);
       return -ESHUTDOWN;
     }
 #endif
@@ -3607,7 +3608,7 @@ static int sam_ep_submit(struct usbdev_ep_s *ep, struct usbdev_req_s *req)
       if (privep->stalled)
         {
           sam_req_abort(privep, privreq, -EBUSY);
-          ullerr("ERROR: stalled\n");
+          uerr("ERROR: stalled\n");
           ret = -EPERM;
         }
       else
diff --git a/arch/arm/src/sama5/sam_xdmac.c b/arch/arm/src/sama5/sam_xdmac.c
index ef7238a209c..9b819555569 100644
--- a/arch/arm/src/sama5/sam_xdmac.c
+++ b/arch/arm/src/sama5/sam_xdmac.c
@@ -1860,7 +1860,7 @@ static int sam_xdmac_interrupt(struct sam_xdmac_s *xdmac)
             {
               /* Yes... Terminate the transfer with an error? */
 
-              dmallerr("ERROR: DMA failed: %08x\n", chpending);
+              dmaerr("ERROR: DMA failed: %08x\n", chpending);
               sam_dmaterminate(xdmach, -EIO);
             }
 
@@ -1877,7 +1877,7 @@ static int sam_xdmac_interrupt(struct sam_xdmac_s *xdmac)
 
           else
             {
-              dmallerr("ERROR: Unexpected interrupt: %08x\n", chpending);
+              dmaerr("ERROR: Unexpected interrupt: %08x\n", chpending);
               DEBUGPANIC();
             }
 
@@ -1957,7 +1957,7 @@ void sam_dmainitialize(struct sam_xdmac_s *xdmac)
 void weak_function up_dmainitialize(void)
 {
 #ifdef CONFIG_SAMA5_XDMAC0
-  dmallinfo("Initialize XDMAC0\n");
+  dmainfo("Initialize XDMAC0\n");
 
   /* Enable peripheral clock */
 
@@ -1977,7 +1977,7 @@ void weak_function up_dmainitialize(void)
 #endif
 
 #ifdef CONFIG_SAMA5_XDMAC1
-  dmallinfo("Initialize XDMAC1\n");
+  dmainfo("Initialize XDMAC1\n");
 
   /* Enable peripheral clock */
 
diff --git a/arch/arm/src/samdl/sam_dmac.c b/arch/arm/src/samdl/sam_dmac.c
index f81d77f75dc..d465d4d5f87 100644
--- a/arch/arm/src/samdl/sam_dmac.c
+++ b/arch/arm/src/samdl/sam_dmac.c
@@ -769,7 +769,7 @@ static int sam_rxbuffer(struct sam_dmach_s *dmach, uint32_t paddr,
 
 void weak_function up_dmainitialize(void)
 {
-  dmallinfo("Initialize DMAC\n");
+  dmainfo("Initialize DMAC\n");
   int i;
 
   /* Initialize global semaphores */
diff --git a/arch/arm/src/samdl/sam_idle.c b/arch/arm/src/samdl/sam_idle.c
index a6fb0245270..b791f991191 100644
--- a/arch/arm/src/samdl/sam_idle.c
+++ b/arch/arm/src/samdl/sam_idle.c
@@ -99,7 +99,7 @@ static void up_idlepm(void)
 
       /* Perform board-specific, state-dependent logic here */
 
-      _llinfo("newstate= %d oldstate=%d\n", newstate, oldstate);
+      _info("newstate= %d oldstate=%d\n", newstate, oldstate);
 
       /* Then force the global state change */
 
diff --git a/arch/arm/src/samdl/sam_irq.c b/arch/arm/src/samdl/sam_irq.c
index ea20c689bf2..025c2008182 100644
--- a/arch/arm/src/samdl/sam_irq.c
+++ b/arch/arm/src/samdl/sam_irq.c
@@ -84,7 +84,7 @@ volatile uint32_t *g_current_regs[1];
 
 /****************************************************************************
  * Name: sam_nmi, sam_busfault, sam_usagefault, sam_pendsv,
- *       sam_errmonitor, sam_pendsv, sam_reserved
+ *       sam_dbgmonitor, sam_pendsv, sam_reserved
  *
  * Description:
  *   Handlers for various execptions.  None are handled and all are fatal
diff --git a/arch/arm/src/samv7/Kconfig b/arch/arm/src/samv7/Kconfig
index 1f217e5d4a3..55eb92d485d 100644
--- a/arch/arm/src/samv7/Kconfig
+++ b/arch/arm/src/samv7/Kconfig
@@ -1634,7 +1634,7 @@ config SAMV7_HSMCI_UNALIGNED
 
 config SAMV7_HSMCI_XFRDEBUG
 	bool "HSMCI transfer debug"
-	depends on DEBUG_FS && CONFIG_DEBUG_INFO
+	depends on DEBUG_FS_INFO
 	default n
 	---help---
 		Enable special debug instrumentation analyze HSMCI data transfers.
@@ -1646,7 +1646,7 @@ config SAMV7_HSMCI_XFRDEBUG
 
 config SAMV7_HSMCI_CMDDEBUG
 	bool "HSMCI command debug"
-	depends on DEBUG_FS && CONFIG_DEBUG_INFO
+	depends on DEBUG_FS_INFO
 	default n
 	---help---
 		Enable special debug instrumentation analyze HSMCI commands. This
diff --git a/arch/arm/src/samv7/sam_emac.c b/arch/arm/src/samv7/sam_emac.c
index ae1151a04f6..7fcedd85716 100644
--- a/arch/arm/src/samv7/sam_emac.c
+++ b/arch/arm/src/samv7/sam_emac.c
@@ -1147,7 +1147,7 @@ static int sam_buffer_allocate(struct sam_emac_s *priv)
   priv->xfrq[0].txdesc = (struct emac_txdesc_s *)kmm_memalign(EMAC_ALIGN, allocsize);
   if (!priv->xfrq[0].txdesc)
     {
-      nllerr("ERROR: Failed to allocate TX descriptors\n");
+      nerr("ERROR: Failed to allocate TX descriptors\n");
       return -ENOMEM;
     }
 
@@ -1158,7 +1158,7 @@ static int sam_buffer_allocate(struct sam_emac_s *priv)
   priv->xfrq[0].rxdesc = (struct emac_rxdesc_s *)kmm_memalign(EMAC_ALIGN, allocsize);
   if (!priv->xfrq[0].rxdesc)
     {
-      nllerr("ERROR: Failed to allocate RX descriptors\n");
+      nerr("ERROR: Failed to allocate RX descriptors\n");
       sam_buffer_free(priv);
       return -ENOMEM;
     }
@@ -1170,7 +1170,7 @@ static int sam_buffer_allocate(struct sam_emac_s *priv)
   priv->xfrq[0].txbuffer = (uint8_t *)kmm_memalign(EMAC_ALIGN, allocsize);
   if (!priv->xfrq[0].txbuffer)
     {
-      nllerr("ERROR: Failed to allocate TX buffer\n");
+      nerr("ERROR: Failed to allocate TX buffer\n");
       sam_buffer_free(priv);
       return -ENOMEM;
     }
@@ -1181,7 +1181,7 @@ static int sam_buffer_allocate(struct sam_emac_s *priv)
   priv->xfrq[0].rxbuffer = (uint8_t *)kmm_memalign(EMAC_ALIGN, allocsize);
   if (!priv->xfrq[0].rxbuffer)
     {
-      nllerr("ERROR: Failed to allocate RX buffer\n");
+      nerr("ERROR: Failed to allocate RX buffer\n");
       sam_buffer_free(priv);
       return -ENOMEM;
     }
@@ -1194,7 +1194,7 @@ static int sam_buffer_allocate(struct sam_emac_s *priv)
   priv->xfrq[1].txdesc = (struct emac_txdesc_s *)kmm_memalign(EMAC_ALIGN, allocsize);
   if (!priv->xfrq[1].txdesc)
     {
-      nllerr("ERROR: Failed to allocate TX descriptors\n");
+      nerr("ERROR: Failed to allocate TX descriptors\n");
       return -ENOMEM;
     }
 
@@ -1205,7 +1205,7 @@ static int sam_buffer_allocate(struct sam_emac_s *priv)
   priv->xfrq[1].rxdesc = (struct emac_rxdesc_s *)kmm_memalign(EMAC_ALIGN, allocsize);
   if (!priv->xfrq[1].rxdesc)
     {
-      nllerr("ERROR: Failed to allocate RX descriptors\n");
+      nerr("ERROR: Failed to allocate RX descriptors\n");
       sam_buffer_free(priv);
       return -ENOMEM;
     }
@@ -1217,7 +1217,7 @@ static int sam_buffer_allocate(struct sam_emac_s *priv)
   priv->xfrq[1].txbuffer = (uint8_t *)kmm_memalign(EMAC_ALIGN, allocsize);
   if (!priv->xfrq[1].txbuffer)
     {
-      nllerr("ERROR: Failed to allocate TX buffer\n");
+      nerr("ERROR: Failed to allocate TX buffer\n");
       sam_buffer_free(priv);
       return -ENOMEM;
     }
@@ -1228,7 +1228,7 @@ static int sam_buffer_allocate(struct sam_emac_s *priv)
   priv->xfrq[1].rxbuffer = (uint8_t *)kmm_memalign(EMAC_ALIGN, allocsize);
   if (!priv->xfrq[1].rxbuffer)
     {
-      nllerr("ERROR: Failed to allocate RX buffer\n");
+      nerr("ERROR: Failed to allocate RX buffer\n");
       sam_buffer_free(priv);
       return -ENOMEM;
     }
@@ -1369,7 +1369,7 @@ static int sam_transmit(struct sam_emac_s *priv, int qid)
 
   if (dev->d_len > EMAC_TX_UNITSIZE)
     {
-      nllerr("ERROR: Packet too big: %d\n", dev->d_len);
+      nerr("ERROR: Packet too big: %d\n", dev->d_len);
       return -EINVAL;
     }
 
@@ -1379,14 +1379,14 @@ static int sam_transmit(struct sam_emac_s *priv, int qid)
   txhead = xfrq->txhead;
   txdesc = &xfrq->txdesc[txhead];
 
-  nllinfo("d_len: %d txhead[%d]: %d\n",  dev->d_len, qid, xfrq->txhead);
+  ninfo("d_len: %d txhead[%d]: %d\n",  dev->d_len, qid, xfrq->txhead);
   sam_dumppacket("Transmit packet", dev->d_buf, dev->d_len);
 
   /* If no free TX descriptor, buffer can't be sent */
 
   if (sam_txfree(priv, qid) < 1)
     {
-      nllerr("ERROR: No free TX descriptors\n");
+      nerr("ERROR: No free TX descriptors\n");
       return -EBUSY;
     }
 
@@ -1460,7 +1460,7 @@ static int sam_transmit(struct sam_emac_s *priv, int qid)
 
   if (sam_txfree(priv, qid) < 1)
     {
-      nllinfo("Disabling RX interrupts\n");
+      ninfo("Disabling RX interrupts\n");
       sam_putreg(priv, SAM_EMAC_IDR_OFFSET, EMAC_INT_RCOMP);
     }
 
@@ -1646,7 +1646,7 @@ static int sam_recvframe(struct sam_emac_s *priv, int qid)
   arch_invalidate_dcache((uintptr_t)rxdesc,
                          (uintptr_t)rxdesc + sizeof(struct emac_rxdesc_s));
 
-  nllinfo("Entry rxndx[%d]: %d\n", qid, rxndx);
+  ninfo("Entry rxndx[%d]: %d\n", qid, rxndx);
 
   while ((rxdesc->addr & EMACRXD_ADDR_OWNER) != 0)
     {
@@ -1709,7 +1709,7 @@ static int sam_recvframe(struct sam_emac_s *priv, int qid)
         {
           if (rxndx == xfrq->rxndx)
             {
-              nllinfo("ERROR: No EOF (Invalid or buffers too small)\n");
+              nerr("ERROR: No EOF (Invalid or buffers too small)\n");
               do
                 {
                   /* Give ownership back to the EMAC */
@@ -1767,7 +1767,7 @@ static int sam_recvframe(struct sam_emac_s *priv, int qid)
               /* Frame size from the EMAC */
 
               dev->d_len = (rxdesc->status & EMACRXD_STA_FRLEN_MASK);
-              nllinfo("packet %d-%d (%d)\n", xfrq->rxndx, rxndx, dev->d_len);
+              ninfo("packet %d-%d (%d)\n", xfrq->rxndx, rxndx, dev->d_len);
 
               /* All data have been copied in the application frame buffer,
                * release the RX descriptor(s).  Loop until all descriptors
@@ -1801,12 +1801,12 @@ static int sam_recvframe(struct sam_emac_s *priv, int qid)
                * all of the data.
                */
 
-              nllinfo("rxndx: %d d_len: %d\n",
-                      xfrq->rxndx, dev->d_len);
+              ninfo("rxndx: %d d_len: %d\n",
+                    xfrq->rxndx, dev->d_len);
               if (pktlen < dev->d_len)
                 {
-                  nllerr("ERROR: Buffer size %d; frame size %d\n",
-                         dev->d_len, pktlen);
+                  nerr("ERROR: Buffer size %d; frame size %d\n",
+                       dev->d_len, pktlen);
                   NETDEV_RXERRORS(&priv->dev);
                   return -E2BIG;
                 }
@@ -1854,7 +1854,7 @@ static int sam_recvframe(struct sam_emac_s *priv, int qid)
   /* No packet was found */
 
   xfrq->rxndx = rxndx;
-  nllinfo("Exit rxndx[%d]: %d\n", qid, xfrq->rxndx);
+  ninfo("Exit rxndx[%d]: %d\n", qid, xfrq->rxndx);
   return -EAGAIN;
 }
 
@@ -1896,7 +1896,7 @@ static void sam_receive(struct sam_emac_s *priv, int qid)
 
       if (dev->d_len > CONFIG_NET_ETH_MTU)
         {
-          nllwarn("WARNING: Dropped, Too big: %d\n", dev->d_len);
+          nwarn("WARNING: Dropped, Too big: %d\n", dev->d_len);
           NETDEV_RXERRORS(&priv->dev);
           continue;
         }
@@ -1912,7 +1912,7 @@ static void sam_receive(struct sam_emac_s *priv, int qid)
 #ifdef CONFIG_NET_IPv4
       if (BUF->type == HTONS(ETHTYPE_IP))
         {
-          nllinfo("IPv4 frame\n");
+          ninfo("IPv4 frame\n");
           NETDEV_RXIPV4(&priv->dev);
 
           /* Handle ARP on input then give the IPv4 packet to the network
@@ -1953,7 +1953,7 @@ static void sam_receive(struct sam_emac_s *priv, int qid)
 #ifdef CONFIG_NET_IPv6
       if (BUF->type == HTONS(ETHTYPE_IP6))
         {
-          nllinfo("Iv6 frame\n");
+          ninfo("Iv6 frame\n");
           NETDEV_RXIPV6(&priv->dev);
 
           /* Give the IPv6 packet to the network layer */
@@ -1991,7 +1991,7 @@ static void sam_receive(struct sam_emac_s *priv, int qid)
 #ifdef CONFIG_NET_ARP
       if (BUF->type == htons(ETHTYPE_ARP))
         {
-          nllinfo("ARP frame\n");
+          ninfo("ARP frame\n");
           NETDEV_RXARP(&priv->dev);
 
           /* Handle ARP packet */
@@ -2010,7 +2010,7 @@ static void sam_receive(struct sam_emac_s *priv, int qid)
       else
 #endif
         {
-          nllwarn("WARNING: Dropped, Unknown type: %04x\n", BUF->type);
+          nwarn("WARNING: Dropped, Unknown type: %04x\n", BUF->type);
           NETDEV_RXDROPPED(&priv->dev);
         }
     }
@@ -2286,7 +2286,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv, int qid)
   imr = sam_getreg(priv, SAM_EMAC_IMR_OFFSET);
   pending = isr & ~(imr | EMAC_INT_UNUSED);
 
-  nllinfo("isr: %08x pending: %08x\n", isr, pending);
+  ninfo("isr: %08x pending: %08x\n", isr, pending);
 
   /* Check for the receipt of an RX packet.
    *
@@ -2312,7 +2312,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv, int qid)
 
       if ((rsr & EMAC_RSR_RXOVR) != 0)
         {
-          nllerr("ERROR: Receiver overrun RSR: %08x\n", rsr);
+          nerr("ERROR: Receiver overrun RSR: %08x\n", rsr);
           clrbits |= EMAC_RSR_RXOVR;
         }
 
@@ -2329,7 +2329,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv, int qid)
 
       if ((rsr & EMAC_RSR_BNA) != 0)
         {
-          nllerr("ERROR: Buffer not available RSR: %08x\n", rsr);
+          nerr("ERROR: Buffer not available RSR: %08x\n", rsr);
           clrbits |= EMAC_RSR_BNA;
         }
 
@@ -2370,7 +2370,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv, int qid)
           clrbits = EMAC_TSR_RLE | sam_txinuse(priv, qid);
           sam_txreset(priv, qid);
 
-          nllerr("ERROR: Retry Limit Exceeded TSR: %08x\n", tsr);
+          nerr("ERROR: Retry Limit Exceeded TSR: %08x\n", tsr);
 
           regval  = sam_getreg(priv, SAM_EMAC_NCR_OFFSET);
           regval |= EMAC_NCR_TXEN;
@@ -2381,7 +2381,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv, int qid)
 
       if ((tsr & EMAC_TSR_COL) != 0)
         {
-          nllerr("ERROR: Collision occurred TSR: %08x\n", tsr);
+          nerr("ERROR: Collision occurred TSR: %08x\n", tsr);
           NETDEV_TXERRORS(&priv->dev);
         }
 
@@ -2389,7 +2389,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv, int qid)
 
       if ((tsr & EMAC_TSR_TFC) != 0)
         {
-          nllerr("ERROR: Transmit Frame Corruption due to AHB error: %08x\n", tsr);
+          nerr("ERROR: Transmit Frame Corruption due to AHB error: %08x\n", tsr);
           NETDEV_TXERRORS(&priv->dev);
         }
 
@@ -2407,7 +2407,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv, int qid)
 
   if ((pending & EMAC_INT_HRESP) != 0)
     {
-      nllerr("ERROR: Hresp not OK\n");
+      nerr("ERROR: Hresp not OK\n");
     }
 
   /* Check for PAUSE Frame received (PFRE).
@@ -2418,7 +2418,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv, int qid)
 
   if ((pending & EMAC_INT_PFNZ) != 0)
     {
-      nllinfo("Pause frame received\n");
+      ninfo("Pause frame received\n");
     }
 
   /* Check for Pause Time Zero (PTZ)
@@ -2428,7 +2428,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv, int qid)
 
   if ((pending & EMAC_INT_PTZ) != 0)
     {
-      nllinfo("Pause TO!\n");
+      ninfo("Pause TO!\n");
     }
 #endif
 }
@@ -2593,7 +2593,7 @@ static int sam_emac1_interrupt(int irq, void *context)
 
 static inline void sam_txtimeout_process(FAR struct sam_emac_s *priv)
 {
-  nllerr("ERROR: Timeout!\n");
+  nerr("ERROR: Timeout!\n");
   NETDEV_TXTIMEOUTS(&priv->dev);
 
   /* Reset the hardware.  Just take the interface down, then back up again. */
@@ -2837,7 +2837,7 @@ static int sam_ifup(struct net_driver_s *dev)
 
   /* Configure the EMAC interface for normal operation. */
 
-  nllinfo("Initialize the EMAC\n");
+  ninfo("Initialize the EMAC\n");
   sam_emac_configure(priv);
   sam_queue_configure(priv, EMAC_QUEUE_1);
   sam_queue_configure(priv, EMAC_QUEUE_2);
@@ -2858,7 +2858,7 @@ static int sam_ifup(struct net_driver_s *dev)
   ret = sam_phyinit(priv);
   if (ret < 0)
     {
-      nllerr("ERROR: sam_phyinit failed: %d\n", ret);
+      nerr("ERROR: sam_phyinit failed: %d\n", ret);
       return ret;
     }
 
@@ -2867,16 +2867,16 @@ static int sam_ifup(struct net_driver_s *dev)
   ret = sam_autonegotiate(priv);
   if (ret < 0)
     {
-      nllerr("ERROR: sam_autonegotiate failed: %d\n", ret);
+      nerr("ERROR: sam_autonegotiate failed: %d\n", ret);
       return ret;
     }
 
   while (sam_linkup(priv) == 0);
-  nllinfo("Link detected \n");
+  ninfo("Link detected \n");
 
   /* Enable normal MAC operation */
 
-  nllinfo("Enable normal operation\n");
+  ninfo("Enable normal operation\n");
 
   /* Set and activate a timer process */
 
@@ -2910,7 +2910,7 @@ static int sam_ifdown(struct net_driver_s *dev)
   struct sam_emac_s *priv = (struct sam_emac_s *)dev->d_private;
   irqstate_t flags;
 
-  nllinfo("Taking the network down\n");
+  ninfo("Taking the network down\n");
 
   /* Disable the EMAC interrupt */
 
@@ -2955,7 +2955,7 @@ static int sam_ifdown(struct net_driver_s *dev)
 
 static inline void sam_txavail_process(FAR struct sam_emac_s *priv)
 {
-  nllinfo("ifup: %d\n", priv->ifup);
+  ninfo("ifup: %d\n", priv->ifup);
 
   /* Ignore the notification if the interface is not yet up */
 
@@ -3208,8 +3208,8 @@ static int sam_addmac(struct net_driver_s *dev, const uint8_t *mac)
   unsigned int ndx;
   unsigned int bit;
 
-  nllinfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
-          mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+  ninfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
+        mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
 
   /* Calculate the 6-bit has table index */
 
@@ -3281,8 +3281,8 @@ static int sam_rmmac(struct net_driver_s *dev, const uint8_t *mac)
   unsigned int ndx;
   unsigned int bit;
 
-  nllinfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
-          mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+  ninfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
+        mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
 
   /* Calculate the 6-bit has table index */
 
@@ -3476,19 +3476,19 @@ static void sam_phydump(struct sam_emac_s *priv)
   regval |= EMAC_NCR_MPE;
   sam_putreg(priv, SAM_EMAC_NCR_OFFSET, regval);
 
-  nllinfo("%s Registers (Address %02x)\n",
-          priv->attr->rmii ? "RMII" : "MII", priv->phyaddr);
+  ninfo("%s Registers (Address %02x)\n",
+        priv->attr->rmii ? "RMII" : "MII", priv->phyaddr);
 
   sam_phyread(priv, priv->phyaddr, MII_MCR, &phyval);
-  nllinfo("  MCR:       %04x\n", phyval);
+  ninfo("  MCR:       %04x\n", phyval);
   sam_phyread(priv, priv->phyaddr, MII_MSR, &phyval);
-  nllinfo("  MSR:       %04x\n", phyval);
+  ninfo("  MSR:       %04x\n", phyval);
   sam_phyread(priv, priv->phyaddr, MII_ADVERTISE, &phyval);
-  nllinfo("  ADVERTISE: %04x\n", phyval);
+  ninfo("  ADVERTISE: %04x\n", phyval);
   sam_phyread(priv, priv->phyaddr, MII_LPA, &phyval);
-  nllinfo("  LPR:       %04x\n", phyval);
+  ninfo("  LPR:       %04x\n", phyval);
   sam_phyread(priv, priv->phyaddr, priv->attr->physr, &phyval);
-  nllinfo("  PHYSR:     %04x\n", phyval);
+  ninfo("  PHYSR:     %04x\n", phyval);
 
   /* Disable management port */
 
@@ -3716,7 +3716,7 @@ static int sam_phyreset(struct sam_emac_s *priv)
   int timeout;
   int ret;
 
-  nllinfo(" sam_phyreset\n");
+  ninfo(" sam_phyreset\n");
 
   /* Enable management port */
 
@@ -3729,7 +3729,7 @@ static int sam_phyreset(struct sam_emac_s *priv)
   ret = sam_phywrite(priv, priv->phyaddr, MII_MCR, MII_MCR_RESET);
   if (ret < 0)
     {
-      nllerr("ERROR: sam_phywrite failed: %d\n", ret);
+      nerr("ERROR: sam_phywrite failed: %d\n", ret);
     }
 
   /* Wait for the PHY reset to complete */
@@ -3741,7 +3741,7 @@ static int sam_phyreset(struct sam_emac_s *priv)
       int result = sam_phyread(priv, priv->phyaddr, MII_MCR, &mcr);
       if (result < 0)
         {
-          nllerr("ERROR: Failed to read the MCR register: %d\n", ret);
+          nerr("ERROR: Failed to read the MCR register: %d\n", ret);
           ret = result;
         }
       else if ((mcr & MII_MCR_RESET) == 0)
@@ -3783,7 +3783,7 @@ static int sam_phyfind(struct sam_emac_s *priv, uint8_t *phyaddr)
   unsigned int offset;
   int ret = -ESRCH;
 
-  nllinfo("Find a valid PHY address\n");
+  ninfo("Find a valid PHY address\n");
 
   /* Enable management port */
 
@@ -3806,8 +3806,8 @@ static int sam_phyfind(struct sam_emac_s *priv, uint8_t *phyaddr)
 
   else
     {
-      nllerr("ERROR: sam_phyread failed for PHY address %02x: %d\n",
-             candidate, ret);
+      nerr("ERROR: sam_phyread failed for PHY address %02x: %d\n",
+           candidate, ret);
 
       for (offset = 0; offset < 32; offset++)
         {
@@ -3828,10 +3828,10 @@ static int sam_phyfind(struct sam_emac_s *priv, uint8_t *phyaddr)
 
   if (ret == OK)
     {
-      nllinfo("  PHYID1: %04x PHY addr: %d\n", phyval, candidate);
+      ninfo("  PHYID1: %04x PHY addr: %d\n", phyval, candidate);
       *phyaddr = candidate;
       sam_phyread(priv, candidate, priv->attr->physr, &phyval);
-      nllinfo("  PHYSR:  %04x PHY addr: %d\n", phyval, candidate);
+      ninfo("  PHYSR:  %04x PHY addr: %d\n", phyval, candidate);
     }
 
   /* Disable management port */
@@ -3872,7 +3872,7 @@ static int sam_phyread(struct sam_emac_s *priv, uint8_t phyaddr,
   ret = sam_phywait(priv);
   if (ret < 0)
     {
-      nllerr("ERROR: sam_phywait failed: %d\n", ret);
+      nerr("ERROR: sam_phywait failed: %d\n", ret);
       return ret;
     }
 
@@ -3897,7 +3897,7 @@ static int sam_phyread(struct sam_emac_s *priv, uint8_t phyaddr,
   ret = sam_phywait(priv);
   if (ret < 0)
     {
-      nllerr("ERROR: sam_phywait failed: %d\n", ret);
+      nerr("ERROR: sam_phywait failed: %d\n", ret);
       return ret;
     }
 
@@ -3937,7 +3937,7 @@ static int sam_phywrite(struct sam_emac_s *priv, uint8_t phyaddr,
   ret = sam_phywait(priv);
   if (ret < 0)
     {
-      nllerr("ERROR: sam_phywait failed: %d\n", ret);
+      nerr("ERROR: sam_phywait failed: %d\n", ret);
       return ret;
     }
 
@@ -3962,7 +3962,7 @@ static int sam_phywrite(struct sam_emac_s *priv, uint8_t phyaddr,
   ret = sam_phywait(priv);
   if (ret < 0)
     {
-      nllerr("ERROR: sam_phywait failed: %d\n", ret);
+      nerr("ERROR: sam_phywait failed: %d\n", ret);
       return ret;
     }
 
@@ -4007,33 +4007,33 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
   ret = sam_phyread(priv, priv->phyaddr, MII_PHYID1, &phyid1);
   if (ret < 0)
     {
-      nllerr("ERROR: Failed to read PHYID1\n");
+      nerr("ERROR: Failed to read PHYID1\n");
       goto errout;
     }
 
-  nllinfo("PHYID1: %04x PHY address: %02x\n", phyid1, priv->phyaddr);
+  ninfo("PHYID1: %04x PHY address: %02x\n", phyid1, priv->phyaddr);
 
   ret = sam_phyread(priv, priv->phyaddr, MII_PHYID2, &phyid2);
   if (ret < 0)
     {
-      nllerr("ERROR: Failed to read PHYID2\n");
+      nerr("ERROR: Failed to read PHYID2\n");
       goto errout;
     }
 
-  nllinfo("PHYID2: %04x PHY address: %02x\n", phyid2, priv->phyaddr);
+  ninfo("PHYID2: %04x PHY address: %02x\n", phyid2, priv->phyaddr);
 
   if (phyid1 == priv->attr->msoui &&
      ((phyid2 & MII_PHYID2_OUI_MASK) >> MII_PHYID2_OUI_SHIFT) ==
       (uint16_t)priv->attr->lsoui)
     {
-      nllinfo("  Vendor Model Number:   %04x\n",
-             (phyid2 & MII_PHYID2_MODEL_MASK) >> MII_PHYID2_MODEL_SHIFT);
-      nllinfo("  Model Revision Number: %04x\n",
-             (phyid2 & MII_PHYID2_REV_MASK) >> MII_PHYID2_REV_SHIFT);
+      ninfo("  Vendor Model Number:   %04x\n",
+           (phyid2 & MII_PHYID2_MODEL_MASK) >> MII_PHYID2_MODEL_SHIFT);
+      ninfo("  Model Revision Number: %04x\n",
+           (phyid2 & MII_PHYID2_REV_MASK) >> MII_PHYID2_REV_SHIFT);
     }
   else
     {
-      nllerr("ERROR: PHY not recognized\n");
+      nerr("ERROR: PHY not recognized\n");
     }
 
   /* Setup control register */
@@ -4041,7 +4041,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
   ret = sam_phyread(priv, priv->phyaddr, MII_MCR, &mcr);
   if (ret < 0)
     {
-      nllerr("ERROR: Failed to read MCR\n");
+      nerr("ERROR: Failed to read MCR\n");
       goto errout;
     }
 
@@ -4052,7 +4052,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
   ret = sam_phywrite(priv, priv->phyaddr, MII_MCR, mcr);
   if (ret < 0)
     {
-      nllerr("ERROR: Failed to write MCR\n");
+      nerr("ERROR: Failed to write MCR\n");
       goto errout;
     }
 
@@ -4067,7 +4067,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
   ret = sam_phywrite(priv, priv->phyaddr, MII_ADVERTISE, advertise);
   if (ret < 0)
     {
-      nllerr("ERROR: Failed to write ANAR\n");
+      nerr("ERROR: Failed to write ANAR\n");
       goto errout;
     }
 
@@ -4076,7 +4076,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
   ret = sam_phyread(priv, priv->phyaddr, MII_MCR, &mcr);
   if (ret < 0)
     {
-      nllerr("ERROR: Failed to read MCR\n");
+      nerr("ERROR: Failed to read MCR\n");
       goto errout;
     }
 
@@ -4084,7 +4084,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
   ret = sam_phywrite(priv, priv->phyaddr, MII_MCR, mcr);
   if (ret < 0)
     {
-      nllerr("ERROR: Failed to write MCR\n");
+      nerr("ERROR: Failed to write MCR\n");
       goto errout;
     }
 
@@ -4096,11 +4096,11 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
   ret = sam_phywrite(priv, priv->phyaddr, MII_MCR, mcr);
   if (ret < 0)
     {
-      nllerr("ERROR: Failed to write MCR\n");
+      nerr("ERROR: Failed to write MCR\n");
       goto errout;
     }
 
-  nllinfo("  MCR: %04x\n", mcr);
+  ninfo("  MCR: %04x\n", mcr);
 
   /* Check AutoNegotiate complete */
 
@@ -4110,7 +4110,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
       ret = sam_phyread(priv, priv->phyaddr, MII_MSR, &msr);
       if (ret < 0)
         {
-          nllerr("ERROR: Failed to read MSR\n");
+          nerr("ERROR: Failed to read MSR\n");
           goto errout;
         }
 
@@ -4120,7 +4120,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
         {
           /* Yes.. break out of the loop */
 
-          nllinfo("AutoNegotiate complete\n");
+          ninfo("AutoNegotiate complete\n");
           break;
         }
 
@@ -4128,7 +4128,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
 
       if (++timeout >= PHY_RETRY_MAX)
         {
-          nllerr("ERROR: TimeOut\n");
+          nerr("ERROR: TimeOut\n");
           sam_phydump(priv);
           ret = -ETIMEDOUT;
           goto errout;
@@ -4140,7 +4140,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
   ret = sam_phyread(priv, priv->phyaddr, MII_LPA, &lpa);
   if (ret < 0)
     {
-      nllerr("ERROR: Failed to read ANLPAR\n");
+      nerr("ERROR: Failed to read ANLPAR\n");
       goto errout;
     }
 
@@ -4235,13 +4235,13 @@ static bool sam_linkup(struct sam_emac_s *priv)
   ret = sam_phyread(priv, priv->phyaddr, MII_MSR, &msr);
   if (ret < 0)
     {
-      nllerr("ERROR: Failed to read MSR: %d\n", ret);
+      nerr("ERROR: Failed to read MSR: %d\n", ret);
       goto errout;
     }
 
   if ((msr & MII_MSR_LINKSTATUS) == 0)
     {
-      nllerr("ERROR: MSR LinkStatus: %04x\n", msr);
+      nerr("ERROR: MSR LinkStatus: %04x\n", msr);
       goto errout;
     }
 
@@ -4250,7 +4250,7 @@ static bool sam_linkup(struct sam_emac_s *priv)
   ret = sam_phyread(priv, priv->phyaddr, priv->attr->physr, &physr);
   if (ret < 0)
     {
-      nllerr("ERROR: Failed to read PHYSR: %d\n", ret);
+      nerr("ERROR: Failed to read PHYSR: %d\n", ret);
       goto errout;
     }
 
@@ -4288,7 +4288,7 @@ static bool sam_linkup(struct sam_emac_s *priv)
 
   /* Start the EMAC transfers */
 
-  nllinfo("Link is up\n");
+  ninfo("Link is up\n");
   linkup = true;
 
 errout:
@@ -4365,7 +4365,7 @@ static int sam_phyinit(struct sam_emac_s *priv)
   ret = sam_phyfind(priv, &priv->phyaddr);
   if (ret < 0)
     {
-      nllerr("ERROR: sam_phyfind failed: %d\n", ret);
+      nerr("ERROR: sam_phyfind failed: %d\n", ret);
       return ret;
     }
 
@@ -4480,7 +4480,7 @@ static inline void sam_ethgpioconfig(struct sam_emac_s *priv)
   else
 #endif
     {
-      ninfo("ERROR: emac=%d\n", priv->attr->emac);
+      nerr("ERROR: emac=%d\n", priv->attr->emac);
     }
 }
 
@@ -4803,11 +4803,11 @@ static void sam_macaddress(struct sam_emac_s *priv)
   struct net_driver_s *dev = &priv->dev;
   uint32_t regval;
 
-  nllinfo("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
-          dev->d_ifname,
-          dev->d_mac.ether_addr_octet[0], dev->d_mac.ether_addr_octet[1],
-          dev->d_mac.ether_addr_octet[2], dev->d_mac.ether_addr_octet[3],
-          dev->d_mac.ether_addr_octet[4], dev->d_mac.ether_addr_octet[5]);
+  ninfo("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
+        dev->d_ifname,
+        dev->d_mac.ether_addr_octet[0], dev->d_mac.ether_addr_octet[1],
+        dev->d_mac.ether_addr_octet[2], dev->d_mac.ether_addr_octet[3],
+        dev->d_mac.ether_addr_octet[4], dev->d_mac.ether_addr_octet[5]);
 
   /* Set the MAC address */
 
@@ -5006,7 +5006,7 @@ static int sam_emac_configure(struct sam_emac_s *priv)
 {
   uint32_t regval;
 
-  nllinfo("Entry\n");
+  ninfo("Entry\n");
 
   /* Enable clocking to the EMAC peripheral */
 
diff --git a/arch/arm/src/samv7/sam_ethernet.c b/arch/arm/src/samv7/sam_ethernet.c
index 84a883bfcba..0137b161153 100644
--- a/arch/arm/src/samv7/sam_ethernet.c
+++ b/arch/arm/src/samv7/sam_ethernet.c
@@ -99,7 +99,7 @@ void up_netinitialize(void)
   ret = sam_emac_initialize(EMAC0_INTF);
   if (ret < 0)
     {
-      nllerr("ERROR: up_emac_initialize(EMAC0) failed: %d\n", ret);
+      nerr("ERROR: up_emac_initialize(EMAC0) failed: %d\n", ret);
     }
 #endif
 
@@ -109,7 +109,7 @@ void up_netinitialize(void)
   ret = sam_emac_initialize(EMAC1_INTF);
   if (ret < 0)
     {
-      nllerr("ERROR: up_emac_initialize(EMAC1) failed: %d\n", ret);
+      nerr("ERROR: up_emac_initialize(EMAC1) failed: %d\n", ret);
     }
 #endif
 #endif
diff --git a/arch/arm/src/samv7/sam_hsmci.c b/arch/arm/src/samv7/sam_hsmci.c
index bddf8e7f9ae..cffada9e470 100644
--- a/arch/arm/src/samv7/sam_hsmci.c
+++ b/arch/arm/src/samv7/sam_hsmci.c
@@ -1173,7 +1173,7 @@ static void sam_dmacallback(DMA_HANDLE handle, void *arg, int result)
       if (result < 0)
         {
           wkupevent = (result == -ETIMEDOUT ? SDIOWAIT_TIMEOUT : SDIOWAIT_ERROR);
-          mcllerr("ERROR: DMA failed: result=%d wkupevent=%04x\n", result, wkupevent);
+          mcerr("ERROR: DMA failed: result=%d wkupevent=%04x\n", result, wkupevent);
 
           /* sam_endtransfer will terminate the transfer and wait up the waiting
            * client in this case.
@@ -1273,7 +1273,7 @@ static void sam_eventtimeout(int argc, uint32_t arg)
       /* Yes.. wake up any waiting threads */
 
       sam_endwait(priv, SDIOWAIT_TIMEOUT);
-      mcllerr("ERROR: Timeout\n");
+      mcerr("ERROR: Timeout\n");
     }
 }
 
@@ -1473,7 +1473,7 @@ static int sam_hsmci_interrupt(struct sam_dev_s *priv)
             {
               /* Yes.. Was it some kind of timeout error? */
 
-              mcllerr("ERROR: enabled: %08x pending: %08x\n", enabled, pending);
+              mcerr("ERROR: enabled: %08x pending: %08x\n", enabled, pending);
               if ((pending & HSMCI_DATA_TIMEOUT_ERRORS) != 0)
                 {
                   /* Yes.. Terminate with a timeout. */
@@ -1594,8 +1594,8 @@ static int sam_hsmci_interrupt(struct sam_dev_s *priv)
                 {
                   /* Yes.. Was the error some kind of timeout? */
 
-                  mcllinfo("ERROR: events: %08x SR: %08x\n",
-                          priv->cmdrmask, enabled);
+                  mcerr("ERROR: events: %08x SR: %08x\n",
+                         priv->cmdrmask, enabled);
 
                   if ((pending & HSMCI_RESPONSE_TIMEOUT_ERRORS) != 0)
                     {
@@ -3220,7 +3220,7 @@ static void sam_callback(void *arg)
           mcerr("ERROR: Failed to cancel work: %d\n", ret);
         }
 
-      mcllinfo("Queuing callback to %p(%p)\n", priv->callback, priv->cbarg);
+      mcinfo("Queuing callback to %p(%p)\n", priv->callback, priv->cbarg);
       ret = work_queue(LPWORK, &priv->cbwork, (worker_t)priv->callback,
                        priv->cbarg, 0);
       if (ret < 0)
@@ -3418,7 +3418,7 @@ void sdio_mediachange(FAR struct sdio_dev_s *dev, bool cardinslot)
       priv->cdstatus &= ~SDIO_STATUS_PRESENT;
     }
 
-  mcllinfo("cdstatus OLD: %02x NEW: %02x\n", cdstatus, priv->cdstatus);
+  mcinfo("cdstatus OLD: %02x NEW: %02x\n", cdstatus, priv->cdstatus);
 
   /* Perform any requested callback if the status has changed */
 
diff --git a/arch/arm/src/samv7/sam_irq.c b/arch/arm/src/samv7/sam_irq.c
index faf021fa47b..08537f65970 100644
--- a/arch/arm/src/samv7/sam_irq.c
+++ b/arch/arm/src/samv7/sam_irq.c
@@ -163,7 +163,7 @@ static void sam_dumpnvic(const char *msg, int irq)
 #endif
 
 /****************************************************************************
- * Name: sam_nmi, sam_busfault, sam_usagefault, sam_pendsv, sam_errmonitor,
+ * Name: sam_nmi, sam_busfault, sam_usagefault, sam_pendsv, sam_dbgmonitor,
  *       sam_pendsv, sam_reserved
  *
  * Description:
@@ -206,7 +206,7 @@ static int sam_pendsv(int irq, FAR void *context)
   return 0;
 }
 
-static int sam_errmonitor(int irq, FAR void *context)
+static int sam_dbgmonitor(int irq, FAR void *context)
 {
   (void)up_irq_save();
   _err("PANIC!!! Debug Monitor received\n");
@@ -466,7 +466,7 @@ void up_irqinitialize(void)
   irq_attach(SAM_IRQ_BUSFAULT, sam_busfault);
   irq_attach(SAM_IRQ_USAGEFAULT, sam_usagefault);
   irq_attach(SAM_IRQ_PENDSV, sam_pendsv);
-  irq_attach(SAM_IRQ_DBGMONITOR, sam_errmonitor);
+  irq_attach(SAM_IRQ_DBGMONITOR, sam_dbgmonitor);
   irq_attach(SAM_IRQ_RESERVED, sam_reserved);
 #endif
 
diff --git a/arch/arm/src/samv7/sam_mcan.c b/arch/arm/src/samv7/sam_mcan.c
index adade973637..2091390cab2 100644
--- a/arch/arm/src/samv7/sam_mcan.c
+++ b/arch/arm/src/samv7/sam_mcan.c
@@ -2137,7 +2137,7 @@ static void mcan_reset(FAR struct can_dev_s *dev)
   config = priv->config;
   DEBUGASSERT(config);
 
-  canllinfo("MCAN%d\n", config->port);
+  caninfo("MCAN%d\n", config->port);
   UNUSED(config);
 
   /* Get exclusive access to the MCAN peripheral */
@@ -2194,7 +2194,7 @@ static int mcan_setup(FAR struct can_dev_s *dev)
   config = priv->config;
   DEBUGASSERT(config);
 
-  canllinfo("MCAN%d pid: %d\n", config->port, config->pid);
+  caninfo("MCAN%d pid: %d\n", config->port, config->pid);
 
   /* Get exclusive access to the MCAN peripheral */
 
@@ -2205,7 +2205,7 @@ static int mcan_setup(FAR struct can_dev_s *dev)
   ret = mcan_hw_initialize(priv);
   if (ret < 0)
     {
-      canllerr("ERROR: MCAN%d H/W initialization failed: %d\n", config->port, ret);
+      canerr("ERROR: MCAN%d H/W initialization failed: %d\n", config->port, ret);
       return ret;
     }
 
@@ -2216,7 +2216,7 @@ static int mcan_setup(FAR struct can_dev_s *dev)
   ret = irq_attach(config->irq0, config->handler);
   if (ret < 0)
     {
-      canllerr("ERROR: Failed to attach MCAN%d line 0 IRQ (%d)",
+      canerr("ERROR: Failed to attach MCAN%d line 0 IRQ (%d)",
       config->port, config->irq0);
       return ret;
     }
@@ -2224,7 +2224,7 @@ static int mcan_setup(FAR struct can_dev_s *dev)
   ret = irq_attach(config->irq1, config->handler);
   if (ret < 0)
     {
-      canllerr("ERROR: Failed to attach MCAN%d line 1 IRQ (%d)",
+      canerr("ERROR: Failed to attach MCAN%d line 1 IRQ (%d)",
       config->port, config->irq1);
       return ret;
     }
@@ -2271,7 +2271,7 @@ static void mcan_shutdown(FAR struct can_dev_s *dev)
   config = priv->config;
   DEBUGASSERT(config);
 
-  canllinfo("MCAN%d\n", config->port);
+  caninfo("MCAN%d\n", config->port);
 
   /* Get exclusive access to the MCAN peripheral */
 
@@ -2320,7 +2320,7 @@ static void mcan_rxint(FAR struct can_dev_s *dev, bool enable)
 
   DEBUGASSERT(priv && priv->config);
 
-  canllinfo("MCAN%d enable: %d\n", priv->config->port, enable);
+  caninfo("MCAN%d enable: %d\n", priv->config->port, enable);
 
   /* Enable/disable the receive interrupts */
 
@@ -2362,7 +2362,7 @@ static void mcan_txint(FAR struct can_dev_s *dev, bool enable)
 
   DEBUGASSERT(priv && priv->config);
 
-  canllinfo("MCAN%d enable: %d\n", priv->config->port, enable);
+  caninfo("MCAN%d enable: %d\n", priv->config->port, enable);
 
   /* Enable/disable the receive interrupts */
 
@@ -2602,8 +2602,6 @@ static int mcan_ioctl(FAR struct can_dev_s *dev, int cmd, unsigned long arg)
         break;
     }
 
-  /* No CAN ioctls are supported */
-
   return ret;
 }
 
@@ -2669,9 +2667,9 @@ static int mcan_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg)
   DEBUGASSERT(priv && priv->config);
   config = priv->config;
 
-  canllinfo("MCAN%d\n", config->port);
-  canllinfo("MCAN%d ID: %d DLC: %d\n",
-            config->port, msg->cm_hdr.ch_id, msg->cm_hdr.ch_dlc);
+  caninfo("MCAN%d\n", config->port);
+  caninfo("MCAN%d ID: %d DLC: %d\n",
+          config->port, msg->cm_hdr.ch_id, msg->cm_hdr.ch_dlc);
 
   /* That that FIFO elements were configured.
    *
@@ -3141,7 +3139,7 @@ static void mcan_error(FAR struct can_dev_s *dev, uint32_t status,
       ret = can_receive(dev, &hdr, data);
       if (ret < 0)
         {
-          canllerr("ERROR: can_receive failed: %d\n", ret);
+          canerr("ERROR: can_receive failed: %d\n", ret);
         }
     }
 }
@@ -3235,7 +3233,7 @@ static void mcan_receive(FAR struct can_dev_s *dev, FAR uint32_t *rxbuffer,
   ret = can_receive(dev, &hdr, (FAR uint8_t *)rxbuffer);
   if (ret < 0)
     {
-      canllerr("ERROR: can_receive failed: %d\n", ret);
+      canerr("ERROR: can_receive failed: %d\n", ret);
     }
 }
 
@@ -3288,7 +3286,7 @@ static void mcan_interrupt(FAR struct can_dev_s *dev)
 
           if ((pending & MCAN_CMNERR_INTS) != 0)
             {
-              canllerr("ERROR: Common %08x\n", pending & MCAN_CMNERR_INTS);
+              canerr("ERROR: Common %08x\n", pending & MCAN_CMNERR_INTS);
 
               /* Clear the error indications */
 
@@ -3299,7 +3297,7 @@ static void mcan_interrupt(FAR struct can_dev_s *dev)
 
           if ((pending & MCAN_TXERR_INTS) != 0)
             {
-              canllerr("ERROR: TX %08x\n", pending & MCAN_TXERR_INTS);
+              canerr("ERROR: TX %08x\n", pending & MCAN_TXERR_INTS);
 
               /* Clear the error indications */
 
@@ -3320,7 +3318,7 @@ static void mcan_interrupt(FAR struct can_dev_s *dev)
 
           if ((pending & MCAN_RXERR_INTS) != 0)
             {
-              canllerr("ERROR: RX %08x\n", pending & MCAN_RXERR_INTS);
+              canerr("ERROR: RX %08x\n", pending & MCAN_RXERR_INTS);
 
               /* Clear the error indications */
 
@@ -3341,7 +3339,7 @@ static void mcan_interrupt(FAR struct can_dev_s *dev)
         {
           /* All (old) errors cleared  */
 
-          canllerr("ERROR: CLEARED\n");
+          canerr("ERROR: CLEARED\n");
 
           mcan_error(dev, 0, priv->olderrors);
 
@@ -3466,7 +3464,7 @@ static void mcan_interrupt(FAR struct can_dev_s *dev)
 
           if ((regval & MCAN_RXF0S_RF0L) != 0)
             {
-              canllerr("ERROR: Message lost: %08x\n", regval);
+              canerr("ERROR: Message lost: %08x\n", regval);
             }
           else
             {
@@ -3500,7 +3498,7 @@ static void mcan_interrupt(FAR struct can_dev_s *dev)
 
           if ((regval & MCAN_RXF0S_RF0L) != 0)
             {
-              canllerr("ERROR: Message lost: %08x\n", regval);
+              canerr("ERROR: Message lost: %08x\n", regval);
             }
           else
             {
@@ -3594,7 +3592,7 @@ static int mcan_hw_initialize(struct sam_mcan_s *priv)
   uint32_t cntr;
   uint32_t cmr;
 
-  canllinfo("MCAN%d\n", config->port);
+  caninfo("MCAN%d\n", config->port);
 
   /* Configure MCAN pins */
 
diff --git a/arch/arm/src/samv7/sam_oneshot.c b/arch/arm/src/samv7/sam_oneshot.c
index bb5555a7bb7..4ee2467a61e 100644
--- a/arch/arm/src/samv7/sam_oneshot.c
+++ b/arch/arm/src/samv7/sam_oneshot.c
@@ -109,7 +109,7 @@ static void sam_oneshot_handler(TC_HANDLE tch, void *arg, uint32_t sr)
   oneshot_handler_t oneshot_handler;
   void *oneshot_arg;
 
-  tmrllinfo("Expired...\n");
+  tmrinfo("Expired...\n");
   DEBUGASSERT(oneshot && oneshot->handler);
 
   /* The clock was stopped, but not disabled when the RC match occurred.
diff --git a/arch/arm/src/samv7/sam_spi.c b/arch/arm/src/samv7/sam_spi.c
index 34caed374cd..df176330991 100644
--- a/arch/arm/src/samv7/sam_spi.c
+++ b/arch/arm/src/samv7/sam_spi.c
@@ -1130,9 +1130,9 @@ static int spi_setdelay(struct spi_dev_s *dev, uint32_t startdelay,
   uint32_t regval;
   unsigned int offset;
 
-  spivdbg("cs=%d startdelay=%d\n", spics->cs, startdelay);
-  spivdbg("cs=%d stopdelay=%d\n", spics->cs, stopdelay);
-  spivdbg("cs=%d csdelay=%d\n", spics->cs, csdelay);
+  spiinfo("cs=%d startdelay=%d\n", spics->cs, startdelay);
+  spiinfo("cs=%d stopdelay=%d\n", spics->cs, stopdelay);
+  spiinfo("cs=%d csdelay=%d\n", spics->cs, csdelay);
 
   offset = (unsigned int)g_csroffset[spics->cs];
 
diff --git a/arch/arm/src/samv7/sam_ssc.c b/arch/arm/src/samv7/sam_ssc.c
index c07d5542587..11ae76c9f07 100644
--- a/arch/arm/src/samv7/sam_ssc.c
+++ b/arch/arm/src/samv7/sam_ssc.c
@@ -821,12 +821,12 @@ static void ssc_dump_queue(sq_queue_t *queue)
 
       if (!apb)
         {
-          i2sllinfo("    %p: No buffer\n", bfcontainer);
+          i2sinfo("    %p: No buffer\n", bfcontainer);
         }
       else
         {
-          i2sllinfo("    %p: buffer=%p nmaxbytes=%d nbytes=%d\n",
-                    bfcontainer, apb, apb->nmaxbytes, apb->nbytes);
+          i2sinfo("    %p: buffer=%p nmaxbytes=%d nbytes=%d\n",
+                  bfcontainer, apb, apb->nmaxbytes, apb->nbytes);
         }
     }
 }
@@ -836,12 +836,12 @@ static void ssc_dump_queues(struct sam_transport_s *xpt, const char *msg)
   irqstate_t flags;
 
   flags = enter_critical_section();
-  i2sllinfo("%s\n", msg);
-  i2sllinfo("  Pending:\n");
+  i2sinfo("%s\n", msg);
+  i2sinfo("  Pending:\n");
   ssc_dump_queue(&xpt->pend);
-  i2sllinfo("  Active:\n");
+  i2sinfo("  Active:\n");
   ssc_dump_queue(&xpt->act);
-  i2sllinfo("  Done:\n");
+  i2sinfo("  Done:\n");
   ssc_dump_queue(&xpt->done);
   leave_critical_section(flags);
 }
@@ -1064,7 +1064,7 @@ static void ssc_dma_sampleinit(struct sam_ssc_s *priv,
 #if defined(CONFIG_SAMV7_SSC_DMADEBUG) && defined(SSC_HAVE_RX)
 static void ssc_rxdma_sampledone(struct sam_ssc_s *priv, int result)
 {
-  i2sinfo("result: %d\n", result);
+  i2llsinfo("result: %d\n", result);
 
   /* Sample the final registers */
 
@@ -1352,7 +1352,7 @@ static int ssc_rxdma_setup(struct sam_ssc_s *priv)
 
       if (ret < 0)
         {
-          i2sllerr("ERROR: wd_start failed: %d\n", errno);
+          i2serr("ERROR: wd_start failed: %d\n", errno);
         }
     }
 
@@ -1540,7 +1540,7 @@ static void ssc_rx_schedule(struct sam_ssc_s *priv, int result)
       ret = work_queue(HPWORK, &priv->rx.work, ssc_rx_worker, priv, 0);
       if (ret != 0)
         {
-          i2sllerr("ERROR: Failed to queue RX work: %d\n", ret);
+          i2serr("ERROR: Failed to queue RX work: %d\n", ret);
         }
     }
 }
@@ -1769,7 +1769,7 @@ static int ssc_txdma_setup(struct sam_ssc_s *priv)
 
       if (ret < 0)
         {
-          i2sllerr("ERROR: wd_start failed: %d\n", errno);
+          i2serr("ERROR: wd_start failed: %d\n", errno);
         }
     }
 
@@ -1944,7 +1944,7 @@ static void ssc_tx_schedule(struct sam_ssc_s *priv, int result)
       ret = work_queue(HPWORK, &priv->tx.work, ssc_tx_worker, priv, 0);
       if (ret != 0)
         {
-          i2sllerr("ERROR: Failed to queue TX work: %d\n", ret);
+          i2serr("ERROR: Failed to queue TX work: %d\n", ret);
         }
     }
 }
diff --git a/arch/arm/src/samv7/sam_tc.c b/arch/arm/src/samv7/sam_tc.c
index 98c5347a8c6..691366af8f8 100644
--- a/arch/arm/src/samv7/sam_tc.c
+++ b/arch/arm/src/samv7/sam_tc.c
@@ -845,8 +845,8 @@ static int sam_tc_interrupt(struct sam_tc_s *tc, struct sam_chan_s *chan)
   imr     = sam_chan_getreg(chan, SAM_TC_IMR_OFFSET);
   pending = sr & imr;
 
-  tcllinfo("TC%d Channel %d: pending=%08lx\n",
-           tc->tc, chan->chan, (unsigned long)pending);
+  tmrinfo("TC%d Channel %d: pending=%08lx\n",
+          tc->tc, chan->chan, (unsigned long)pending);
 
   /* Are there any pending interrupts for this channel? */
 
diff --git a/arch/arm/src/samv7/sam_tickless.c b/arch/arm/src/samv7/sam_tickless.c
index 4a547a60e9d..95f4b8754f3 100644
--- a/arch/arm/src/samv7/sam_tickless.c
+++ b/arch/arm/src/samv7/sam_tickless.c
@@ -221,7 +221,7 @@ static struct sam_tickless_s g_tickless;
 
 static void sam_oneshot_handler(void *arg)
 {
-  tmrllinfo("Expired...\n");
+  tmrinfo("Expired...\n");
   sched_timer_expiration();
 }
 
@@ -265,7 +265,7 @@ void up_timer_initialize(void)
                                CONFIG_USEC_PER_TICK);
   if (ret < 0)
     {
-      tmrllerr("ERROR: sam_oneshot_initialize failed\n");
+      tmrerr("ERROR: sam_oneshot_initialize failed\n");
       PANIC();
     }
 
@@ -278,7 +278,7 @@ void up_timer_initialize(void)
                                CONFIG_USEC_PER_TICK);
   if (ret < 0)
     {
-      tmrllerr("ERROR: sam_freerun_initialize failed\n");
+      tmrerr("ERROR: sam_freerun_initialize failed\n");
       PANIC();
     }
 
diff --git a/arch/arm/src/samv7/sam_twihs.c b/arch/arm/src/samv7/sam_twihs.c
index 93d59f2a87f..6a0de18ef4d 100644
--- a/arch/arm/src/samv7/sam_twihs.c
+++ b/arch/arm/src/samv7/sam_twihs.c
@@ -543,7 +543,7 @@ static int twi_interrupt(struct twi_dev_s *priv)
   imr     = twi_getrel(priv, SAM_TWIHS_IMR_OFFSET);
   pending = sr & imr;
 
-  i2cllinfo("TWIHS%d pending: %08x\n", priv->attr->twi, pending);
+  i2cinfo("TWIHS%d pending: %08x\n", priv->attr->twi, pending);
 
   /* Byte received */
 
@@ -616,7 +616,7 @@ static int twi_interrupt(struct twi_dev_s *priv)
     {
       /* Wake up the thread with an I/O error indication */
 
-      i2cllerr("ERROR: TWIHS%d pending: %08x\n", priv->attr->twi, pending);
+      i2cerr("ERROR: TWIHS%d pending: %08x\n", priv->attr->twi, pending);
       twi_wakeup(priv, -EIO);
     }
 
@@ -739,7 +739,7 @@ static void twi_timeout(int argc, uint32_t arg, ...)
 {
   struct twi_dev_s *priv = (struct twi_dev_s *)arg;
 
-  i2cllerr("ERROR: TWIHS%d Timeout!\n", priv->attr->twi);
+  i2cerr("ERROR: TWIHS%d Timeout!\n", priv->attr->twi);
   twi_wakeup(priv, -ETIMEDOUT);
 }
 
diff --git a/arch/arm/src/samv7/sam_usbdevhs.c b/arch/arm/src/samv7/sam_usbdevhs.c
index e7660280b6e..07bfe1d2d4b 100644
--- a/arch/arm/src/samv7/sam_usbdevhs.c
+++ b/arch/arm/src/samv7/sam_usbdevhs.c
@@ -1405,9 +1405,9 @@ static int sam_req_write(struct sam_usbdev_s *priv, struct sam_ep_s *privep)
           return -ENOENT;
         }
 
-      ullinfo("epno=%d req=%p: len=%d xfrd=%d inflight=%d zlpneeded=%d\n",
-              epno, privreq, privreq->req.len, privreq->req.xfrd,
-              privreq->inflight, privep->zlpneeded);
+      uinfo("epno=%d req=%p: len=%d xfrd=%d inflight=%d zlpneeded=%d\n",
+            epno, privreq, privreq->req.len, privreq->req.xfrd,
+            privreq->inflight, privep->zlpneeded);
 
       /* Handle any bytes in flight. */
 
@@ -1640,8 +1640,8 @@ static int sam_req_read(struct sam_usbdev_s *priv, struct sam_ep_s *privep,
           return -ENOENT;
         }
 
-      ullinfo("EP%d: len=%d xfrd=%d\n",
-              epno, privreq->req.len, privreq->req.xfrd);
+      uinfo("EP%d: len=%d xfrd=%d\n",
+            epno, privreq->req.len, privreq->req.xfrd);
 
       /* Ignore any attempt to receive a zero length packet */
 
@@ -1975,8 +1975,8 @@ static void sam_ep0_setup(struct sam_usbdev_s *priv)
   index.w = GETUINT16(priv->ctrl.index);
   len.w   = GETUINT16(priv->ctrl.len);
 
-  ullinfo("SETUP: type=%02x req=%02x value=%04x index=%04x len=%04x\n",
-          priv->ctrl.type, priv->ctrl.req, value.w, index.w, len.w);
+  uinfo("SETUP: type=%02x req=%02x value=%04x index=%04x len=%04x\n",
+        priv->ctrl.type, priv->ctrl.req, value.w, index.w, len.w);
 
   /* Dispatch any non-standard requests */
 
@@ -2139,7 +2139,7 @@ static void sam_ep0_setup(struct sam_usbdev_s *priv)
           {
             /* Special case recipient=device test mode */
 
-            ullinfo("test mode: %d\n", index.w);
+            uinfo("test mode: %d\n", index.w);
           }
         else if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) != USB_REQ_RECIPIENT_ENDPOINT)
           {
@@ -3902,7 +3902,7 @@ static int sam_ep_submit(struct usbdev_ep_s *ep, struct usbdev_req_s *req)
       if (privep->stalled)
         {
           sam_req_abort(privep, privreq, -EBUSY);
-          ullerr("ERROR: stalled\n");
+          uerr("ERROR: stalled\n");
           ret = -EPERM;
         }
       else
diff --git a/arch/arm/src/samv7/sam_xdmac.c b/arch/arm/src/samv7/sam_xdmac.c
index 8835b0386dd..206ecb5d0f1 100644
--- a/arch/arm/src/samv7/sam_xdmac.c
+++ b/arch/arm/src/samv7/sam_xdmac.c
@@ -1542,7 +1542,7 @@ static int sam_xdmac_interrupt(int irq, void *context)
             {
               /* Yes... Terminate the transfer with an error? */
 
-              dmallerr("ERROR: DMA failed: %08x\n", chpending);
+              dmaerr("ERROR: DMA failed: %08x\n", chpending);
               sam_dmaterminate(xdmach, -EIO);
             }
 
@@ -1559,7 +1559,7 @@ static int sam_xdmac_interrupt(int irq, void *context)
 
           else
             {
-              dmallerr("ERROR: Unexpected interrupt: %08x\n", chpending);
+              dmaerr("ERROR: Unexpected interrupt: %08x\n", chpending);
               DEBUGPANIC();
             }
 
@@ -1616,7 +1616,7 @@ void sam_dmainitialize(struct sam_xdmac_s *xdmac)
 
 void weak_function up_dmainitialize(void)
 {
-  dmallinfo("Initialize XDMAC\n");
+  dmainfo("Initialize XDMAC\n");
 
   /* Enable peripheral clock */
 
diff --git a/arch/arm/src/stm32/Kconfig b/arch/arm/src/stm32/Kconfig
index 13d8af23849..4a838eb07d6 100644
--- a/arch/arm/src/stm32/Kconfig
+++ b/arch/arm/src/stm32/Kconfig
@@ -6333,21 +6333,21 @@ config STM32_USB_ITRMP
 		F3 family and selects the use of the dedicated USB interrupts.
 
 menu "CAN driver configuration"
-	depends on STM32_CAN1 || STM32_CAN2
+	depends on STM32_CAN
 
 config CAN1_BAUD
 	int "CAN1 BAUD"
 	default 250000
 	depends on STM32_CAN1
 	---help---
-		CAN1 BAUD rate.  Required if STM32_CAN1 is defined.
+		CAN1 BAUD rate.  Required if CONFIG_STM32_CAN1 is defined.
 
 config CAN2_BAUD
 	int "CAN2 BAUD"
 	default 250000
 	depends on STM32_CAN2
 	---help---
-		CAN2 BAUD rate.  Required if STM32_CAN2 is defined.
+		CAN2 BAUD rate.  Required if CONFIG_STM32_CAN2 is defined.
 
 config CAN_TSEG1
 	int "TSEG1 quanta"
@@ -6360,6 +6360,15 @@ config CAN_TSEG2
 	default 7
 	---help---
 		The number of CAN time quanta in segment 2. Default: 7
+
+config STM32_CAN_REGDEBUG
+	bool "CAN Register level debug"
+	depends on DEBUG_CAN_INFO
+	default n
+	---help---
+		Output detailed register-level CAN device debug information.
+		Requires also CONFIG_DEBUG_CAN_INFO.
+
 endmenu
 
 if STM32_LTDC
diff --git a/arch/arm/src/stm32/chip/stm32_adc.h b/arch/arm/src/stm32/chip/stm32_adc.h
index b0990a37bef..8a9eb956b67 100644
--- a/arch/arm/src/stm32/chip/stm32_adc.h
+++ b/arch/arm/src/stm32/chip/stm32_adc.h
@@ -478,7 +478,7 @@
 #  define ADC_SMPR1_SMP17_SHIFT      (21)      /* Bits 21-23: Channel 17 Sample time selection */
 #  define ADC_SMPR1_SMP17_MASK       (7 << ADC_SMPR1_SMP17_SHIFT)
 #  if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
-#    define ADC_SMPR1_SMP18_SHIFT    (21)      /* Bits 24-26: Channel 18 Sample time selection */
+#    define ADC_SMPR1_SMP18_SHIFT    (24)      /* Bits 24-26: Channel 18 Sample time selection */
 #    define ADC_SMPR1_SMP18_MASK     (7 << ADC_SMPR1_SMP17_SHIFT)
 #  endif
 #else
diff --git a/arch/arm/src/stm32/stm32_adc.c b/arch/arm/src/stm32/stm32_adc.c
index 3b541dde8a9..31109fd8f50 100644
--- a/arch/arm/src/stm32/stm32_adc.c
+++ b/arch/arm/src/stm32/stm32_adc.c
@@ -1717,7 +1717,7 @@ static void adc_reset(FAR struct adc_dev_s *dev)
   int ret;
 #endif
 
-  allinfo("intf: %d\n", priv->intf);
+  ainfo("intf: %d\n", priv->intf);
   flags = enter_critical_section();
 
 #if defined(CONFIG_STM32_STM32L15XX) && \
@@ -2718,12 +2718,12 @@ static int adc_interrupt(FAR struct adc_dev_s *dev)
 
   if ((regval & ADC_ISR_AWD) != 0)
     {
-      allwarn("WARNING: Analog Watchdog, Value converted out of range!\n");
+      awarn("WARNING: Analog Watchdog, Value converted out of range!\n");
     }
 
   if ((regval & ADC_ISR_OVR) != 0)
     {
-      allwarn("WARNING: Overrun has occurred!\n");
+      awarn("WARNING: Overrun has occurred!\n");
     }
 
   /* EOC: End of conversion */
diff --git a/arch/arm/src/stm32/stm32_can.c b/arch/arm/src/stm32/stm32_can.c
index 8d9de4f57b6..cd902bf7e2f 100644
--- a/arch/arm/src/stm32/stm32_can.c
+++ b/arch/arm/src/stm32/stm32_can.c
@@ -540,7 +540,7 @@ static void can_reset(FAR struct can_dev_s *dev)
   uint32_t regbit = 0;
   irqstate_t flags;
 
-  canllinfo("CAN%d\n", priv->port);
+  caninfo("CAN%d\n", priv->port);
 
   /* Get the bits in the AHB1RSTR register needed to reset this CAN device */
 
@@ -602,8 +602,8 @@ static int can_setup(FAR struct can_dev_s *dev)
   FAR struct stm32_can_s *priv = dev->cd_priv;
   int ret;
 
-  canllinfo("CAN%d RX0 irq: %d RX1 irq: %d TX irq: %d\n",
-            priv->port, priv->canrx[0], priv->canrx[1], priv->cantx);
+  caninfo("CAN%d RX0 irq: %d RX1 irq: %d TX irq: %d\n",
+          priv->port, priv->canrx[0], priv->canrx[1], priv->cantx);
 
   /* CAN cell initialization */
 
@@ -685,7 +685,7 @@ static void can_shutdown(FAR struct can_dev_s *dev)
 {
   FAR struct stm32_can_s *priv = dev->cd_priv;
 
-  canllinfo("CAN%d\n", priv->port);
+  caninfo("CAN%d\n", priv->port);
 
   /* Disable the RX FIFO 0/1 and TX interrupts */
 
@@ -723,7 +723,7 @@ static void can_rxint(FAR struct can_dev_s *dev, bool enable)
   FAR struct stm32_can_s *priv = dev->cd_priv;
   uint32_t regval;
 
-  canllinfo("CAN%d enable: %d\n", priv->port, enable);
+  caninfo("CAN%d enable: %d\n", priv->port, enable);
 
   /* Enable/disable the FIFO 0/1 message pending interrupt */
 
@@ -758,7 +758,7 @@ static void can_txint(FAR struct can_dev_s *dev, bool enable)
   FAR struct stm32_can_s *priv = dev->cd_priv;
   uint32_t regval;
 
-  canllinfo("CAN%d enable: %d\n", priv->port, enable);
+  caninfo("CAN%d enable: %d\n", priv->port, enable);
 
   /* Support only disabling the transmit mailbox interrupt */
 
@@ -843,8 +843,8 @@ static int can_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg)
   int dlc;
   int txmb;
 
-  canllinfo("CAN%d ID: %d DLC: %d\n",
-            priv->port, msg->cm_hdr.ch_id, msg->cm_hdr.ch_dlc);
+  caninfo("CAN%d ID: %d DLC: %d\n",
+          priv->port, msg->cm_hdr.ch_id, msg->cm_hdr.ch_dlc);
 
   /* Select one empty transmit mailbox */
 
@@ -996,7 +996,7 @@ static bool can_txready(FAR struct can_dev_s *dev)
   /* Return true if any mailbox is available */
 
   regval = can_getreg(priv, STM32_CAN_TSR_OFFSET);
-  canllinfo("CAN%d TSR: %08x\n", priv->port, regval);
+  caninfo("CAN%d TSR: %08x\n", priv->port, regval);
 
   return (regval & CAN_ALL_MAILBOXES) != 0;
 }
@@ -1027,7 +1027,7 @@ static bool can_txempty(FAR struct can_dev_s *dev)
   /* Return true if all mailboxes are available */
 
   regval = can_getreg(priv, STM32_CAN_TSR_OFFSET);
-  canllinfo("CAN%d TSR: %08x\n", priv->port, regval);
+  caninfo("CAN%d TSR: %08x\n", priv->port, regval);
 
   return (regval & CAN_ALL_MAILBOXES) == CAN_ALL_MAILBOXES;
 }
@@ -1379,8 +1379,8 @@ static int can_bittiming(FAR struct stm32_can_s *priv)
   uint32_t ts1;
   uint32_t ts2;
 
-  canllinfo("CAN%d PCLK1: %d baud: %d\n",
-            priv->port, STM32_PCLK1_FREQUENCY, priv->baud);
+  caninfo("CAN%d PCLK1: %d baud: %d\n",
+          priv->port, STM32_PCLK1_FREQUENCY, priv->baud);
 
   /* Try to get CAN_BIT_QUANTA quanta in one bit_time.
    *
@@ -1432,7 +1432,7 @@ static int can_bittiming(FAR struct stm32_can_s *priv)
       DEBUGASSERT(brp >= 1 && brp <= CAN_BTR_BRP_MAX);
     }
 
-  canllinfo("TS1: %d TS2: %d BRP: %d\n", ts1, ts2, brp);
+  caninfo("TS1: %d TS2: %d BRP: %d\n", ts1, ts2, brp);
 
   /* Configure bit timing.  This also does the following, less obvious
    * things.  Unless loopback mode is enabled, it:
@@ -1475,7 +1475,7 @@ static int can_cellinit(FAR struct stm32_can_s *priv)
   uint32_t regval;
   int ret;
 
-  canllinfo("CAN%d\n", priv->port);
+  caninfo("CAN%d\n", priv->port);
 
   /* Exit from sleep mode */
 
@@ -1601,7 +1601,7 @@ static int can_filterinit(FAR struct stm32_can_s *priv)
   uint32_t regval;
   uint32_t bitmask;
 
-  canllinfo("CAN%d filter: %d\n", priv->port, priv->filter);
+  caninfo("CAN%d filter: %d\n", priv->port, priv->filter);
 
   /* Get the bitmask associated with the filter used by this CAN block */
 
diff --git a/arch/arm/src/stm32/stm32_dumpgpio.c b/arch/arm/src/stm32/stm32_dumpgpio.c
index b50f8b84cc8..a8da3160d19 100644
--- a/arch/arm/src/stm32/stm32_dumpgpio.c
+++ b/arch/arm/src/stm32/stm32_dumpgpio.c
@@ -120,107 +120,107 @@ int stm32_dumpgpio(uint32_t pinset, const char *msg)
   flags = enter_critical_section();
 
 #if defined(CONFIG_STM32_STM32F10XX)
-  _llinfo("GPIO%c pinset: %08x base: %08x -- %s\n",
-         g_portchar[port], pinset, base, msg);
+  _info("GPIO%c pinset: %08x base: %08x -- %s\n",
+       g_portchar[port], pinset, base, msg);
 
   if ((getreg32(STM32_RCC_APB2ENR) & RCC_APB2ENR_IOPEN(port)) != 0)
     {
-      _llinfo("  CR: %08x %08x IDR: %04x ODR: %04x LCKR: %04x\n",
-             getreg32(base + STM32_GPIO_CRH_OFFSET),
-             getreg32(base + STM32_GPIO_CRL_OFFSET),
-             getreg32(base + STM32_GPIO_IDR_OFFSET),
-             getreg32(base + STM32_GPIO_ODR_OFFSET),
-             getreg32(base + STM32_GPIO_LCKR_OFFSET));
-      _llinfo("  EVCR: %02x MAPR: %08x CR: %04x %04x %04x %04x\n",
-             getreg32(STM32_AFIO_EVCR), getreg32(STM32_AFIO_MAPR),
-             getreg32(STM32_AFIO_EXTICR1),
-             getreg32(STM32_AFIO_EXTICR2),
-             getreg32(STM32_AFIO_EXTICR3),
-             getreg32(STM32_AFIO_EXTICR4));
+      _info("  CR: %08x %08x IDR: %04x ODR: %04x LCKR: %04x\n",
+           getreg32(base + STM32_GPIO_CRH_OFFSET),
+           getreg32(base + STM32_GPIO_CRL_OFFSET),
+           getreg32(base + STM32_GPIO_IDR_OFFSET),
+           getreg32(base + STM32_GPIO_ODR_OFFSET),
+           getreg32(base + STM32_GPIO_LCKR_OFFSET));
+      _info("  EVCR: %02x MAPR: %08x CR: %04x %04x %04x %04x\n",
+           getreg32(STM32_AFIO_EVCR), getreg32(STM32_AFIO_MAPR),
+           getreg32(STM32_AFIO_EXTICR1),
+           getreg32(STM32_AFIO_EXTICR2),
+           getreg32(STM32_AFIO_EXTICR3),
+           getreg32(STM32_AFIO_EXTICR4));
     }
   else
     {
-      _llinfo("  GPIO%c not enabled: APB2ENR: %08x\n",
-            g_portchar[port], getreg32(STM32_RCC_APB2ENR));
+      _info("  GPIO%c not enabled: APB2ENR: %08x\n",
+          g_portchar[port], getreg32(STM32_RCC_APB2ENR));
     }
 
 #elif defined(CONFIG_STM32_STM32L15XX)
   DEBUGASSERT(port < STM32_NGPIO_PORTS);
 
-  _llinfo("GPIO%c pinset: %08x base: %08x -- %s\n",
-         g_portchar[port], pinset, base, msg);
+  _info("GPIO%c pinset: %08x base: %08x -- %s\n",
+        g_portchar[port], pinset, base, msg);
 
   if ((getreg32(STM32_RCC_AHBENR) & RCC_AHBENR_GPIOEN(port)) != 0)
     {
-      _llinfo(" MODE: %08x OTYPE: %04x     OSPEED: %08x PUPDR: %08x\n",
-             getreg32(base + STM32_GPIO_MODER_OFFSET),
-             getreg32(base + STM32_GPIO_OTYPER_OFFSET),
-             getreg32(base + STM32_GPIO_OSPEED_OFFSET),
-             getreg32(base + STM32_GPIO_PUPDR_OFFSET));
-      _llinfo("  IDR: %04x       ODR: %04x       BSRR: %08x  LCKR: %04x\n",
-             getreg32(base + STM32_GPIO_IDR_OFFSET),
-             getreg32(base + STM32_GPIO_ODR_OFFSET),
-             getreg32(base + STM32_GPIO_BSRR_OFFSET),
-             getreg32(base + STM32_GPIO_LCKR_OFFSET));
-      _llinfo(" AFRH: %08x  AFRL: %08x\n",
-             getreg32(base + STM32_GPIO_AFRH_OFFSET),
-             getreg32(base + STM32_GPIO_AFRL_OFFSET));
+      _info(" MODE: %08x OTYPE: %04x     OSPEED: %08x PUPDR: %08x\n",
+           getreg32(base + STM32_GPIO_MODER_OFFSET),
+           getreg32(base + STM32_GPIO_OTYPER_OFFSET),
+           getreg32(base + STM32_GPIO_OSPEED_OFFSET),
+           getreg32(base + STM32_GPIO_PUPDR_OFFSET));
+      _info("  IDR: %04x       ODR: %04x       BSRR: %08x  LCKR: %04x\n",
+           getreg32(base + STM32_GPIO_IDR_OFFSET),
+           getreg32(base + STM32_GPIO_ODR_OFFSET),
+           getreg32(base + STM32_GPIO_BSRR_OFFSET),
+           getreg32(base + STM32_GPIO_LCKR_OFFSET));
+      _info(" AFRH: %08x  AFRL: %08x\n",
+           getreg32(base + STM32_GPIO_AFRH_OFFSET),
+           getreg32(base + STM32_GPIO_AFRL_OFFSET));
     }
   else
     {
-      _llinfo("  GPIO%c not enabled: AHBENR: %08x\n",
-             g_portchar[port], getreg32(STM32_RCC_AHBENR));
+      _info("  GPIO%c not enabled: AHBENR: %08x\n",
+            g_portchar[port], getreg32(STM32_RCC_AHBENR));
     }
 
 #elif defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX)
   DEBUGASSERT(port < STM32_NGPIO_PORTS);
 
-  _llinfo("GPIO%c pinset: %08x base: %08x -- %s\n",
-         g_portchar[port], pinset, base, msg);
+  _info("GPIO%c pinset: %08x base: %08x -- %s\n",
+        g_portchar[port], pinset, base, msg);
 
   /* GPIOs are always enabled */
 
-  _llinfo(" MODE: %08x OTYPE: %04x     OSPEED: %08x PUPDR: %08x\n",
-         getreg32(base + STM32_GPIO_MODER_OFFSET),
-         getreg32(base + STM32_GPIO_OTYPER_OFFSET),
-         getreg32(base + STM32_GPIO_OSPEED_OFFSET),
-         getreg32(base + STM32_GPIO_PUPDR_OFFSET));
-  _llinfo("  IDR: %04x       ODR: %04x       BSRR: %08x  LCKR: %04x\n",
-         getreg32(base + STM32_GPIO_IDR_OFFSET),
-         getreg32(base + STM32_GPIO_ODR_OFFSET),
-         getreg32(base + STM32_GPIO_BSRR_OFFSET),
-         getreg32(base + STM32_GPIO_LCKR_OFFSET));
-  _llinfo(" AFRH: %08x  AFRL: %08x   BRR: %04x\n",
-         getreg32(base + STM32_GPIO_AFRH_OFFSET),
-         getreg32(base + STM32_GPIO_AFRL_OFFSET),
-         getreg32(base + STM32_GPIO_BRR_OFFSET));
+  _info(" MODE: %08x OTYPE: %04x     OSPEED: %08x PUPDR: %08x\n",
+        getreg32(base + STM32_GPIO_MODER_OFFSET),
+        getreg32(base + STM32_GPIO_OTYPER_OFFSET),
+        getreg32(base + STM32_GPIO_OSPEED_OFFSET),
+        getreg32(base + STM32_GPIO_PUPDR_OFFSET));
+  _info("  IDR: %04x       ODR: %04x       BSRR: %08x  LCKR: %04x\n",
+        getreg32(base + STM32_GPIO_IDR_OFFSET),
+        getreg32(base + STM32_GPIO_ODR_OFFSET),
+        getreg32(base + STM32_GPIO_BSRR_OFFSET),
+        getreg32(base + STM32_GPIO_LCKR_OFFSET));
+  _info(" AFRH: %08x  AFRL: %08x   BRR: %04x\n",
+        getreg32(base + STM32_GPIO_AFRH_OFFSET),
+        getreg32(base + STM32_GPIO_AFRL_OFFSET),
+        getreg32(base + STM32_GPIO_BRR_OFFSET));
 
 #elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
   DEBUGASSERT(port < STM32_NGPIO_PORTS);
 
-  _llinfo("GPIO%c pinset: %08x base: %08x -- %s\n",
-         g_portchar[port], pinset, base, msg);
+  _info("GPIO%c pinset: %08x base: %08x -- %s\n",
+        g_portchar[port], pinset, base, msg);
 
   if ((getreg32(STM32_RCC_AHB1ENR) & RCC_AHB1ENR_GPIOEN(port)) != 0)
     {
-      _llinfo(" MODE: %08x OTYPE: %04x     OSPEED: %08x PUPDR: %08x\n",
-             getreg32(base + STM32_GPIO_MODER_OFFSET),
-             getreg32(base + STM32_GPIO_OTYPER_OFFSET),
-             getreg32(base + STM32_GPIO_OSPEED_OFFSET),
-             getreg32(base + STM32_GPIO_PUPDR_OFFSET));
-      _llinfo("  IDR: %04x       ODR: %04x       BSRR: %08x  LCKR: %04x\n",
-             getreg32(base + STM32_GPIO_IDR_OFFSET),
-             getreg32(base + STM32_GPIO_ODR_OFFSET),
-             getreg32(base + STM32_GPIO_BSRR_OFFSET),
-             getreg32(base + STM32_GPIO_LCKR_OFFSET));
-      _llinfo(" AFRH: %08x  AFRL: %08x\n",
-             getreg32(base + STM32_GPIO_AFRH_OFFSET),
-             getreg32(base + STM32_GPIO_AFRL_OFFSET));
+      _info(" MODE: %08x OTYPE: %04x     OSPEED: %08x PUPDR: %08x\n",
+            getreg32(base + STM32_GPIO_MODER_OFFSET),
+            getreg32(base + STM32_GPIO_OTYPER_OFFSET),
+            getreg32(base + STM32_GPIO_OSPEED_OFFSET),
+            getreg32(base + STM32_GPIO_PUPDR_OFFSET));
+      _info("  IDR: %04x       ODR: %04x       BSRR: %08x  LCKR: %04x\n",
+            getreg32(base + STM32_GPIO_IDR_OFFSET),
+            getreg32(base + STM32_GPIO_ODR_OFFSET),
+            getreg32(base + STM32_GPIO_BSRR_OFFSET),
+            getreg32(base + STM32_GPIO_LCKR_OFFSET));
+      _info(" AFRH: %08x  AFRL: %08x\n",
+            getreg32(base + STM32_GPIO_AFRH_OFFSET),
+            getreg32(base + STM32_GPIO_AFRL_OFFSET));
     }
   else
     {
-      _llinfo("  GPIO%c not enabled: AHB1ENR: %08x\n",
-             g_portchar[port], getreg32(STM32_RCC_AHB1ENR));
+      _info("  GPIO%c not enabled: AHB1ENR: %08x\n",
+            g_portchar[port], getreg32(STM32_RCC_AHB1ENR));
     }
 #else
 # error "Unsupported STM32 chip"
diff --git a/arch/arm/src/stm32/stm32_eth.c b/arch/arm/src/stm32/stm32_eth.c
index e4add738795..bced5def661 100644
--- a/arch/arm/src/stm32/stm32_eth.c
+++ b/arch/arm/src/stm32/stm32_eth.c
@@ -820,7 +820,7 @@ static uint32_t stm32_getreg(uint32_t addr)
  *
  ****************************************************************************/
 
-#ifdef CONFIG_STM32_ETHMAC_REGDEBUG
+#if defined(CONFIG_STM32_ETHMAC_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES)
 static void stm32_putreg(uint32_t val, uint32_t addr)
 {
   /* Show the register value being written */
@@ -1012,8 +1012,8 @@ static int stm32_transmit(FAR struct stm32_ethmac_s *priv)
   txdesc  = priv->txhead;
   txfirst = txdesc;
 
-  nllinfo("d_len: %d d_buf: %p txhead: %p tdes0: %08x\n",
-          priv->dev.d_len, priv->dev.d_buf, txdesc, txdesc->tdes0);
+  ninfo("d_len: %d d_buf: %p txhead: %p tdes0: %08x\n",
+        priv->dev.d_len, priv->dev.d_buf, txdesc, txdesc->tdes0);
 
   DEBUGASSERT(txdesc && (txdesc->tdes0 & ETH_TDES0_OWN) == 0);
 
@@ -1029,7 +1029,7 @@ static int stm32_transmit(FAR struct stm32_ethmac_s *priv)
       bufcount = (priv->dev.d_len + (CONFIG_STM32_ETH_BUFSIZE-1)) / CONFIG_STM32_ETH_BUFSIZE;
       lastsize = priv->dev.d_len - (bufcount - 1) * CONFIG_STM32_ETH_BUFSIZE;
 
-      nllinfo("bufcount: %d lastsize: %d\n", bufcount, lastsize);
+      ninfo("bufcount: %d lastsize: %d\n", bufcount, lastsize);
 
       /* Set the first segment bit in the first TX descriptor */
 
@@ -1139,8 +1139,8 @@ static int stm32_transmit(FAR struct stm32_ethmac_s *priv)
 
   priv->inflight++;
 
-  nllinfo("txhead: %p txtail: %p inflight: %d\n",
-          priv->txhead, priv->txtail, priv->inflight);
+  ninfo("txhead: %p txtail: %p inflight: %d\n",
+        priv->txhead, priv->txtail, priv->inflight);
 
   /* If all TX descriptors are in-flight, then we have to disable receive interrupts
    * too.  This is because receive events can trigger more un-stoppable transmit
@@ -1438,7 +1438,7 @@ static void stm32_freesegment(FAR struct stm32_ethmac_s *priv,
   struct eth_rxdesc_s *rxdesc;
   int i;
 
-  nllinfo("rxfirst: %p segments: %d\n", rxfirst, segments);
+  ninfo("rxfirst: %p segments: %d\n", rxfirst, segments);
 
   /* Set OWN bit in RX descriptors.  This gives the buffers back to DMA */
 
@@ -1496,8 +1496,8 @@ static int stm32_recvframe(FAR struct stm32_ethmac_s *priv)
   uint8_t *buffer;
   int i;
 
-  nllinfo("rxhead: %p rxcurr: %p segments: %d\n",
-          priv->rxhead, priv->rxcurr, priv->segments);
+  ninfo("rxhead: %p rxcurr: %p segments: %d\n",
+        priv->rxhead, priv->rxcurr, priv->segments);
 
   /* Check if there are free buffers.  We cannot receive new frames in this
    * design unless there is at least one free buffer.
@@ -1505,7 +1505,7 @@ static int stm32_recvframe(FAR struct stm32_ethmac_s *priv)
 
   if (!stm32_isfreebuffer(priv))
     {
-      nllerr("ERROR: No free buffers\n");
+      nerr("ERROR: No free buffers\n");
       return -ENOMEM;
     }
 
@@ -1562,7 +1562,7 @@ static int stm32_recvframe(FAR struct stm32_ethmac_s *priv)
               rxcurr = priv->rxcurr;
             }
 
-          nllinfo("rxhead: %p rxcurr: %p segments: %d\n",
+          ninfo("rxhead: %p rxcurr: %p segments: %d\n",
               priv->rxhead, priv->rxcurr, priv->segments);
 
           /* Check if any errors are reported in the frame */
@@ -1601,8 +1601,8 @@ static int stm32_recvframe(FAR struct stm32_ethmac_s *priv)
               priv->rxhead   = (struct eth_rxdesc_s *)rxdesc->rdes3;
               stm32_freesegment(priv, rxcurr, priv->segments);
 
-              nllinfo("rxhead: %p d_buf: %p d_len: %d\n",
-                      priv->rxhead, dev->d_buf, dev->d_len);
+              ninfo("rxhead: %p d_buf: %p d_len: %d\n",
+                    priv->rxhead, dev->d_buf, dev->d_len);
 
               return OK;
             }
@@ -1612,7 +1612,7 @@ static int stm32_recvframe(FAR struct stm32_ethmac_s *priv)
                * scanning logic, and continue scanning with the next frame.
                */
 
-              nllerr("ERROR: Dropped, RX descriptor errors: %08x\n", rxdesc->rdes0);
+              nerr("ERROR: Dropped, RX descriptor errors: %08x\n", rxdesc->rdes0);
               stm32_freesegment(priv, rxcurr, priv->segments);
             }
         }
@@ -1628,8 +1628,8 @@ static int stm32_recvframe(FAR struct stm32_ethmac_s *priv)
 
   priv->rxhead = rxdesc;
 
-  nllinfo("rxhead: %p rxcurr: %p segments: %d\n",
-          priv->rxhead, priv->rxcurr, priv->segments);
+  ninfo("rxhead: %p rxcurr: %p segments: %d\n",
+        priv->rxhead, priv->rxcurr, priv->segments);
 
   return -EAGAIN;
 }
@@ -1673,7 +1673,7 @@ static void stm32_receive(FAR struct stm32_ethmac_s *priv)
 
       if (dev->d_len > CONFIG_NET_ETH_MTU)
         {
-          nllerr("ERROR: Dropped, Too big: %d\n", dev->d_len);
+          nerr("ERROR: Dropped, Too big: %d\n", dev->d_len);
 
           /* Free dropped packet buffer */
 
@@ -1698,7 +1698,7 @@ static void stm32_receive(FAR struct stm32_ethmac_s *priv)
 #ifdef CONFIG_NET_IPv4
       if (BUF->type == HTONS(ETHTYPE_IP))
         {
-          nllinfo("IPv4 frame\n");
+          ninfo("IPv4 frame\n");
 
           /* Handle ARP on input then give the IPv4 packet to the network
            * layer
@@ -1738,7 +1738,7 @@ static void stm32_receive(FAR struct stm32_ethmac_s *priv)
 #ifdef CONFIG_NET_IPv6
       if (BUF->type == HTONS(ETHTYPE_IP6))
         {
-          nllinfo("Iv6 frame\n");
+          ninfo("Iv6 frame\n");
 
           /* Give the IPv6 packet to the network layer */
 
@@ -1775,7 +1775,7 @@ static void stm32_receive(FAR struct stm32_ethmac_s *priv)
 #ifdef CONFIG_NET_ARP
       if (BUF->type == htons(ETHTYPE_ARP))
         {
-          nllinfo("ARP frame\n");
+          ninfo("ARP frame\n");
 
           /* Handle ARP packet */
 
@@ -1793,7 +1793,7 @@ static void stm32_receive(FAR struct stm32_ethmac_s *priv)
       else
 #endif
         {
-          nllerr("ERROR: Dropped, Unknown type: %04x\n", BUF->type);
+          nerr("ERROR: Dropped, Unknown type: %04x\n", BUF->type);
         }
 
       /* We are finished with the RX buffer.  NOTE:  If the buffer is
@@ -1834,8 +1834,8 @@ static void stm32_freeframe(FAR struct stm32_ethmac_s *priv)
   struct eth_txdesc_s *txdesc;
   int i;
 
-  nllinfo("txhead: %p txtail: %p inflight: %d\n",
-          priv->txhead, priv->txtail, priv->inflight);
+  ninfo("txhead: %p txtail: %p inflight: %d\n",
+        priv->txhead, priv->txtail, priv->inflight);
 
   /* Scan for "in-flight" descriptors owned by the CPU */
 
@@ -1850,8 +1850,8 @@ static void stm32_freeframe(FAR struct stm32_ethmac_s *priv)
            * TX descriptors.
            */
 
-          nllinfo("txtail: %p tdes0: %08x tdes2: %08x tdes3: %08x\n",
-                  txdesc, txdesc->tdes0, txdesc->tdes2, txdesc->tdes3);
+          ninfo("txtail: %p tdes0: %08x tdes2: %08x tdes3: %08x\n",
+                txdesc, txdesc->tdes0, txdesc->tdes2, txdesc->tdes3);
 
           DEBUGASSERT(txdesc->tdes2 != 0);
 
@@ -1903,8 +1903,8 @@ static void stm32_freeframe(FAR struct stm32_ethmac_s *priv)
 
       priv->txtail = txdesc;
 
-      nllinfo("txhead: %p txtail: %p inflight: %d\n",
-              priv->txhead, priv->txtail, priv->inflight);
+      ninfo("txhead: %p txtail: %p inflight: %d\n",
+            priv->txhead, priv->txtail, priv->inflight);
     }
 }
 
@@ -2042,7 +2042,7 @@ static inline void stm32_interrupt_process(FAR struct stm32_ethmac_s *priv)
     {
       /* Just let the user know what happened */
 
-      nllerr("ERROR: Abormal event(s): %08x\n", dmasr);
+      nerr("ERROR: Abormal event(s): %08x\n", dmasr);
 
       /* Clear all pending abnormal events */
 
@@ -2246,7 +2246,7 @@ static void stm32_txtimeout_expiry(int argc, uint32_t arg, ...)
 {
   FAR struct stm32_ethmac_s *priv = (FAR struct stm32_ethmac_s *)arg;
 
-  nllerr("ERROR: Timeout!\n");
+  nerr("ERROR: Timeout!\n");
 
 #ifdef CONFIG_NET_NOINTS
   /* Disable further Ethernet interrupts.  This will prevent some race
@@ -2712,8 +2712,8 @@ static int stm32_addmac(struct net_driver_s *dev, FAR const uint8_t *mac)
   uint32_t temp;
   uint32_t registeraddress;
 
-  nllinfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
-          mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+  ninfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
+        mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
 
   /* Add the MAC address to the hardware multicast hash table */
 
@@ -2769,8 +2769,8 @@ static int stm32_rmmac(struct net_driver_s *dev, FAR const uint8_t *mac)
   uint32_t temp;
   uint32_t registeraddress;
 
-  nllinfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
-          mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+  ninfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
+        mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
 
   /* Remove the MAC address to the hardware multicast hash table */
 
@@ -3853,11 +3853,11 @@ static void stm32_macaddress(FAR struct stm32_ethmac_s *priv)
   FAR struct net_driver_s *dev = &priv->dev;
   uint32_t regval;
 
-  nllinfo("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
-          dev->d_ifname,
-          dev->d_mac.ether_addr_octet[0], dev->d_mac.ether_addr_octet[1],
-          dev->d_mac.ether_addr_octet[2], dev->d_mac.ether_addr_octet[3],
-          dev->d_mac.ether_addr_octet[4], dev->d_mac.ether_addr_octet[5]);
+  ninfo("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
+        dev->d_ifname,
+        dev->d_mac.ether_addr_octet[0], dev->d_mac.ether_addr_octet[1],
+        dev->d_mac.ether_addr_octet[2], dev->d_mac.ether_addr_octet[3],
+        dev->d_mac.ether_addr_octet[4], dev->d_mac.ether_addr_octet[5]);
 
   /* Set the MAC address high register */
 
@@ -4059,12 +4059,12 @@ static int stm32_ethconfig(FAR struct stm32_ethmac_s *priv)
 
   /* Reset the Ethernet block */
 
-  nllinfo("Reset the Ethernet block\n");
+  ninfo("Reset the Ethernet block\n");
   stm32_ethreset(priv);
 
   /* Initialize the PHY */
 
-  nllinfo("Initialize the PHY\n");
+  ninfo("Initialize the PHY\n");
   ret = stm32_phyinit(priv);
   if (ret < 0)
     {
@@ -4073,7 +4073,7 @@ static int stm32_ethconfig(FAR struct stm32_ethmac_s *priv)
 
   /* Initialize the MAC and DMA */
 
-  nllinfo("Initialize the MAC and DMA\n");
+  ninfo("Initialize the MAC and DMA\n");
   ret = stm32_macconfig(priv);
   if (ret < 0)
     {
@@ -4094,7 +4094,7 @@ static int stm32_ethconfig(FAR struct stm32_ethmac_s *priv)
 
   /* Enable normal MAC operation */
 
-  nllinfo("Enable normal operation\n");
+  ninfo("Enable normal operation\n");
   return stm32_macenable(priv);
 }
 
diff --git a/arch/arm/src/stm32/stm32_gpio.c b/arch/arm/src/stm32/stm32_gpio.c
index 6426107b3b4..63d09e982e4 100644
--- a/arch/arm/src/stm32/stm32_gpio.c
+++ b/arch/arm/src/stm32/stm32_gpio.c
@@ -469,6 +469,7 @@ int stm32_configgpio(uint32_t cfgset)
         break;
 
       case GPIO_OUTPUT:     /* General purpose output mode */
+        stm32_gpiowrite(cfgset, (cfgset & GPIO_OUTPUT_SET) != 0); /* Set the initial output value */
         pinmode = GPIO_MODER_OUTPUT;
         break;
 
@@ -619,17 +620,9 @@ int stm32_configgpio(uint32_t cfgset)
 
   putreg32(regval, base + STM32_GPIO_OTYPER_OFFSET);
 
-  /* If it is an output... set the pin to the correct initial state. */
-
-  if (pinmode == GPIO_MODER_OUTPUT)
-    {
-      bool value = ((cfgset & GPIO_OUTPUT_SET) != 0);
-      stm32_gpiowrite(cfgset, value);
-    }
-
   /* Otherwise, it is an input pin.  Should it configured as an EXTI interrupt? */
 
-  else if ((cfgset & GPIO_EXTI) != 0)
+  if (pinmode != GPIO_MODER_OUTPUT && (cfgset & GPIO_EXTI) != 0)
     {
       /* "In STM32 F1 the selection of the EXTI line source is performed through
        *  the EXTIx bits in the AFIO_EXTICRx registers, while in F2 series this
diff --git a/arch/arm/src/stm32/stm32_idle.c b/arch/arm/src/stm32/stm32_idle.c
index 888ed17ed7a..648c0c1521f 100644
--- a/arch/arm/src/stm32/stm32_idle.c
+++ b/arch/arm/src/stm32/stm32_idle.c
@@ -101,7 +101,7 @@ static void up_idlepm(void)
 
       /* Perform board-specific, state-dependent logic here */
 
-      _llinfo("newstate= %d oldstate=%d\n", newstate, oldstate);
+      _info("newstate= %d oldstate=%d\n", newstate, oldstate);
 
       /* Then force the global state change */
 
diff --git a/arch/arm/src/stm32/stm32_irq.c b/arch/arm/src/stm32/stm32_irq.c
index 1e9570cc90a..062d63fb749 100644
--- a/arch/arm/src/stm32/stm32_irq.c
+++ b/arch/arm/src/stm32/stm32_irq.c
@@ -151,7 +151,7 @@ static void stm32_dumpnvic(const char *msg, int irq)
 
 /****************************************************************************
  * Name: stm32_nmi, stm32_busfault, stm32_usagefault, stm32_pendsv,
- *       stm32_errmonitor, stm32_pendsv, stm32_reserved
+ *       stm32_dbgmonitor, stm32_pendsv, stm32_reserved
  *
  * Description:
  *   Handlers for various execptions.  None are handled and all are fatal
@@ -193,7 +193,7 @@ static int stm32_pendsv(int irq, FAR void *context)
   return 0;
 }
 
-static int stm32_errmonitor(int irq, FAR void *context)
+static int stm32_dbgmonitor(int irq, FAR void *context)
 {
   (void)up_irq_save();
   _err("PANIC!!! Debug Monitor received\n");
@@ -418,7 +418,7 @@ void up_irqinitialize(void)
   irq_attach(STM32_IRQ_BUSFAULT, stm32_busfault);
   irq_attach(STM32_IRQ_USAGEFAULT, stm32_usagefault);
   irq_attach(STM32_IRQ_PENDSV, stm32_pendsv);
-  irq_attach(STM32_IRQ_DBGMONITOR, stm32_errmonitor);
+  irq_attach(STM32_IRQ_DBGMONITOR, stm32_dbgmonitor);
   irq_attach(STM32_IRQ_RESERVED, stm32_reserved);
 #endif
 
diff --git a/arch/arm/src/stm32/stm32_otgfsdev.c b/arch/arm/src/stm32/stm32_otgfsdev.c
index 693da846b21..231d091a0cc 100644
--- a/arch/arm/src/stm32/stm32_otgfsdev.c
+++ b/arch/arm/src/stm32/stm32_otgfsdev.c
@@ -1222,9 +1222,9 @@ static void stm32_epin_request(FAR struct stm32_usbdev_s *priv,
       return;
     }
 
-  ullinfo("EP%d req=%p: len=%d xfrd=%d zlp=%d\n",
-          privep->epphy, privreq, privreq->req.len,
-          privreq->req.xfrd, privep->zlp);
+  uinfo("EP%d req=%p: len=%d xfrd=%d zlp=%d\n",
+        privep->epphy, privreq, privreq->req.len,
+        privreq->req.xfrd, privep->zlp);
 
   /* Check for a special case:  If we are just starting a request (xfrd==0) and
    * the class driver is trying to send a zero-length packet (len==0).  Then set
@@ -1488,8 +1488,8 @@ static void stm32_epout_complete(FAR struct stm32_usbdev_s *priv,
       return;
     }
 
-  ullinfo("EP%d: len=%d xfrd=%d\n",
-          privep->epphy, privreq->req.len, privreq->req.xfrd);
+  uinfo("EP%d: len=%d xfrd=%d\n",
+        privep->epphy, privreq->req.len, privreq->req.xfrd);
 
   /* Return the completed read request to the class driver and mark the state
    * IDLE.
@@ -1523,7 +1523,7 @@ static inline void stm32_ep0out_receive(FAR struct stm32_ep_s *privep, int bcnt)
   DEBUGASSERT(privep && privep->ep.priv);
   priv = (FAR struct stm32_usbdev_s *)privep->ep.priv;
 
-  ullinfo("EP0: bcnt=%d\n", bcnt);
+  uinfo("EP0: bcnt=%d\n", bcnt);
   usbtrace(TRACE_READ(EP0), bcnt);
 
   /* Verify that an OUT SETUP request as received before this data was
@@ -1616,7 +1616,8 @@ static inline void stm32_epout_receive(FAR struct stm32_ep_s *privep, int bcnt)
       return;
     }
 
-  ullinfo("EP%d: len=%d xfrd=%d\n", privep->epphy, privreq->req.len, privreq->req.xfrd);
+  uinfo("EP%d: len=%d xfrd=%d\n",
+        privep->epphy, privreq->req.len, privreq->req.xfrd);
   usbtrace(TRACE_READ(privep->epphy), bcnt);
 
   /* Get the number of bytes to transfer from the RxFIFO */
@@ -1700,7 +1701,7 @@ static void stm32_epout_request(FAR struct stm32_usbdev_s *priv,
               return;
             }
 
-          ullinfo("EP%d: len=%d\n", privep->epphy, privreq->req.len);
+          uinfo("EP%d: len=%d\n", privep->epphy, privreq->req.len);
 
           /* Ignore any attempt to receive a zero length packet (this really
            * should not happen.
@@ -2494,8 +2495,8 @@ static inline void stm32_ep0out_setup(struct stm32_usbdev_s *priv)
   ctrlreq.index = GETUINT16(priv->ctrlreq.index);
   ctrlreq.len   = GETUINT16(priv->ctrlreq.len);
 
-  ullinfo("type=%02x req=%02x value=%04x index=%04x len=%04x\n",
-          ctrlreq.type, ctrlreq.req, ctrlreq.value, ctrlreq.index, ctrlreq.len);
+  uinfo("type=%02x req=%02x value=%04x index=%04x len=%04x\n",
+        ctrlreq.type, ctrlreq.req, ctrlreq.value, ctrlreq.index, ctrlreq.len);
 
   /* Check for a standard request */
 
@@ -2629,7 +2630,7 @@ static inline void stm32_epout_interrupt(FAR struct stm32_usbdev_s *priv)
           if ((daint & 1) != 0)
             {
               regval = stm32_getreg(STM32_OTGFS_DOEPINT(epno));
-              ullinfo("DOEPINT(%d) = %08x\n", epno, regval);
+              uinfo("DOEPINT(%d) = %08x\n", epno, regval);
               stm32_putreg(0xFF, STM32_OTGFS_DOEPINT(epno));
             }
 
@@ -2859,8 +2860,8 @@ static inline void stm32_epin_interrupt(FAR struct stm32_usbdev_s *priv)
         {
           if ((daint & 1) != 0)
             {
-              ullinfo("DIEPINT(%d) = %08x\n",
-                      epno, stm32_getreg(STM32_OTGFS_DIEPINT(epno)));
+              uinfo("DIEPINT(%d) = %08x\n",
+                    epno, stm32_getreg(STM32_OTGFS_DIEPINT(epno)));
               stm32_putreg(0xFF, STM32_OTGFS_DIEPINT(epno));
             }
 
@@ -4338,7 +4339,7 @@ static int stm32_ep_submit(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s *
   if (!req || !req->callback || !req->buf || !ep)
     {
       usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0);
-      ullinfo("req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, ep);
+      uinfo("req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, ep);
       return -EINVAL;
     }
 #endif
diff --git a/arch/arm/src/stm32/stm32_otgfshost.c b/arch/arm/src/stm32/stm32_otgfshost.c
index ba5b76f124c..6c340c81fb1 100644
--- a/arch/arm/src/stm32/stm32_otgfshost.c
+++ b/arch/arm/src/stm32/stm32_otgfshost.c
@@ -2370,7 +2370,7 @@ static inline void stm32_gint_hcinisr(FAR struct stm32_usbhost_s *priv,
   /* AND the two to get the set of enabled, pending HC interrupts */
 
   pending &= regval;
-  ullinfo("HCINTMSK%d: %08x pending: %08x\n", chidx, regval, pending);
+  uinfo("HCINTMSK%d: %08x pending: %08x\n", chidx, regval, pending);
 
   /* Check for a pending ACK response received/transmitted (ACK) interrupt */
 
@@ -2631,7 +2631,7 @@ static inline void stm32_gint_hcoutisr(FAR struct stm32_usbhost_s *priv,
   /* AND the two to get the set of enabled, pending HC interrupts */
 
   pending &= regval;
-  ullinfo("HCINTMSK%d: %08x pending: %08x\n", chidx, regval, pending);
+  uinfo("HCINTMSK%d: %08x pending: %08x\n", chidx, regval, pending);
 
   /* Check for a pending ACK response received/transmitted (ACK) interrupt */
 
@@ -2949,7 +2949,7 @@ static inline void stm32_gint_rxflvlisr(FAR struct stm32_usbhost_s *priv)
   /* Read and pop the next status from the Rx FIFO */
 
   grxsts = stm32_getreg(STM32_OTGFS_GRXSTSP);
-  ullinfo("GRXSTS: %08x\n", grxsts);
+  uinfo("GRXSTS: %08x\n", grxsts);
 
   /* Isolate the channel number/index in the status word */
 
@@ -3102,8 +3102,8 @@ static inline void stm32_gint_nptxfeisr(FAR struct stm32_usbhost_s *priv)
 
   /* Write the next group of packets into the Tx FIFO */
 
-  ullinfo("HNPTXSTS: %08x chidx: %d avail: %d buflen: %d xfrd: %d wrsize: %d\n",
-           regval, chidx, avail, chan->buflen, chan->xfrd, wrsize);
+  uinfo("HNPTXSTS: %08x chidx: %d avail: %d buflen: %d xfrd: %d wrsize: %d\n",
+         regval, chidx, avail, chan->buflen, chan->xfrd, wrsize);
 
   stm32_gint_wrpacket(priv, chan->buffer, chidx, wrsize);
 }
@@ -3190,8 +3190,8 @@ static inline void stm32_gint_ptxfeisr(FAR struct stm32_usbhost_s *priv)
 
   /* Write the next group of packets into the Tx FIFO */
 
-  ullinfo("HPTXSTS: %08x chidx: %d avail: %d buflen: %d xfrd: %d wrsize: %d\n",
-           regval, chidx, avail, chan->buflen, chan->xfrd, wrsize);
+  uinfo("HPTXSTS: %08x chidx: %d avail: %d buflen: %d xfrd: %d wrsize: %d\n",
+         regval, chidx, avail, chan->buflen, chan->xfrd, wrsize);
 
   stm32_gint_wrpacket(priv, chan->buffer, chidx, wrsize);
 }
@@ -4727,7 +4727,7 @@ static int stm32_connect(FAR struct usbhost_driver_s *drvr,
   /* Set the connected/disconnected flag */
 
   hport->connected = connected;
-  ullinfo("Hub port %d connected: %s\n", hport->port, connected ? "YES" : "NO");
+  uinfo("Hub port %d connected: %s\n", hport->port, connected ? "YES" : "NO");
 
   /* Report the connection event */
 
diff --git a/arch/arm/src/stm32/stm32_otghsdev.c b/arch/arm/src/stm32/stm32_otghsdev.c
index daa9fc3c367..97d71aa0aa9 100644
--- a/arch/arm/src/stm32/stm32_otghsdev.c
+++ b/arch/arm/src/stm32/stm32_otghsdev.c
@@ -1222,9 +1222,9 @@ static void stm32_epin_request(FAR struct stm32_usbdev_s *priv,
       return;
     }
 
-  ullinfo("EP%d req=%p: len=%d xfrd=%d zlp=%d\n",
-          privep->epphy, privreq, privreq->req.len,
-          privreq->req.xfrd, privep->zlp);
+  uinfo("EP%d req=%p: len=%d xfrd=%d zlp=%d\n",
+        privep->epphy, privreq, privreq->req.len,
+        privreq->req.xfrd, privep->zlp);
 
   /* Check for a special case:  If we are just starting a request (xfrd==0) and
    * the class driver is trying to send a zero-length packet (len==0).  Then set
@@ -1488,8 +1488,8 @@ static void stm32_epout_complete(FAR struct stm32_usbdev_s *priv,
       return;
     }
 
-  ullinfo("EP%d: len=%d xfrd=%d\n",
-          privep->epphy, privreq->req.len, privreq->req.xfrd);
+  uinfo("EP%d: len=%d xfrd=%d\n",
+        privep->epphy, privreq->req.len, privreq->req.xfrd);
 
   /* Return the completed read request to the class driver and mark the state
    * IDLE.
@@ -1523,7 +1523,7 @@ static inline void stm32_ep0out_receive(FAR struct stm32_ep_s *privep, int bcnt)
   DEBUGASSERT(privep && privep->ep.priv);
   priv = (FAR struct stm32_usbdev_s *)privep->ep.priv;
 
-  ullinfo("EP0: bcnt=%d\n", bcnt);
+  uinfo("EP0: bcnt=%d\n", bcnt);
   usbtrace(TRACE_READ(EP0), bcnt);
 
   /* Verify that an OUT SETUP request as received before this data was
@@ -1616,7 +1616,8 @@ static inline void stm32_epout_receive(FAR struct stm32_ep_s *privep, int bcnt)
       return;
     }
 
-  ullinfo("EP%d: len=%d xfrd=%d\n", privep->epphy, privreq->req.len, privreq->req.xfrd);
+  uinfo("EP%d: len=%d xfrd=%d\n",
+        privep->epphy, privreq->req.len, privreq->req.xfrd);
   usbtrace(TRACE_READ(privep->epphy), bcnt);
 
   /* Get the number of bytes to transfer from the RxFIFO */
@@ -1700,7 +1701,7 @@ static void stm32_epout_request(FAR struct stm32_usbdev_s *priv,
               return;
             }
 
-          ullinfo("EP%d: len=%d\n", privep->epphy, privreq->req.len);
+          uinfo("EP%d: len=%d\n", privep->epphy, privreq->req.len);
 
           /* Ignore any attempt to receive a zero length packet (this really
            * should not happen.
@@ -2494,8 +2495,8 @@ static inline void stm32_ep0out_setup(struct stm32_usbdev_s *priv)
   ctrlreq.index = GETUINT16(priv->ctrlreq.index);
   ctrlreq.len   = GETUINT16(priv->ctrlreq.len);
 
-  ullinfo("type=%02x req=%02x value=%04x index=%04x len=%04x\n",
-          ctrlreq.type, ctrlreq.req, ctrlreq.value, ctrlreq.index, ctrlreq.len);
+  uinfo("type=%02x req=%02x value=%04x index=%04x len=%04x\n",
+        ctrlreq.type, ctrlreq.req, ctrlreq.value, ctrlreq.index, ctrlreq.len);
 
   /* Check for a standard request */
 
@@ -2629,7 +2630,7 @@ static inline void stm32_epout_interrupt(FAR struct stm32_usbdev_s *priv)
           if ((daint & 1) != 0)
             {
               regval = stm32_getreg(STM32_OTGHS_DOEPINT(epno));
-              ulinfo("("DOEPINT(%d) = %08x\n", epno, regval);
+              uinfo("DOEPINT(%d) = %08x\n", epno, regval);
               stm32_putreg(0xFF, STM32_OTGHS_DOEPINT(epno));
             }
 
@@ -2859,8 +2860,8 @@ static inline void stm32_epin_interrupt(FAR struct stm32_usbdev_s *priv)
         {
           if ((daint & 1) != 0)
             {
-              ulinfo("("DIEPINT(%d) = %08x\n",
-                     epno, stm32_getreg(STM32_OTGHS_DIEPINT(epno)));
+              uinfo("DIEPINT(%d) = %08x\n",
+                    epno, stm32_getreg(STM32_OTGHS_DIEPINT(epno)));
               stm32_putreg(0xFF, STM32_OTGHS_DIEPINT(epno));
             }
 
@@ -4338,7 +4339,7 @@ static int stm32_ep_submit(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s *
   if (!req || !req->callback || !req->buf || !ep)
     {
       usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0);
-      ullinfo("req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, ep);
+      uinfo("req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, ep);
       return -EINVAL;
     }
 #endif
diff --git a/arch/arm/src/stm32/stm32_otghshost.c b/arch/arm/src/stm32/stm32_otghshost.c
index 4ac58385c12..12a511415bd 100644
--- a/arch/arm/src/stm32/stm32_otghshost.c
+++ b/arch/arm/src/stm32/stm32_otghshost.c
@@ -2370,7 +2370,7 @@ static inline void stm32_gint_hcinisr(FAR struct stm32_usbhost_s *priv,
   /* AND the two to get the set of enabled, pending HC interrupts */
 
   pending &= regval;
-  ullinfo("HCINTMSK%d: %08x pending: %08x\n", chidx, regval, pending);
+  uinfo("HCINTMSK%d: %08x pending: %08x\n", chidx, regval, pending);
 
   /* Check for a pending ACK response received/transmitted (ACK) interrupt */
 
@@ -2631,7 +2631,7 @@ static inline void stm32_gint_hcoutisr(FAR struct stm32_usbhost_s *priv,
   /* AND the two to get the set of enabled, pending HC interrupts */
 
   pending &= regval;
-  ullinfo("HCINTMSK%d: %08x pending: %08x\n", chidx, regval, pending);
+  uinfo("HCINTMSK%d: %08x pending: %08x\n", chidx, regval, pending);
 
   /* Check for a pending ACK response received/transmitted (ACK) interrupt */
 
@@ -2949,7 +2949,7 @@ static inline void stm32_gint_rxflvlisr(FAR struct stm32_usbhost_s *priv)
   /* Read and pop the next status from the Rx FIFO */
 
   grxsts = stm32_getreg(STM32_OTGHS_GRXSTSP);
-  ullinfo("GRXSTS: %08x\n", grxsts);
+  uinfo("GRXSTS: %08x\n", grxsts);
 
   /* Isolate the channel number/index in the status word */
 
@@ -3102,8 +3102,8 @@ static inline void stm32_gint_nptxfeisr(FAR struct stm32_usbhost_s *priv)
 
   /* Write the next group of packets into the Tx FIFO */
 
-  ullinfo("HNPTXSTS: %08x chidx: %d avail: %d buflen: %d xfrd: %dwrsize: %d\n",
-           regval, chidx, avail, chan->buflen, chan->xfrd, wrsize);
+  uinfo("HNPTXSTS: %08x chidx: %d avail: %d buflen: %d xfrd: %dwrsize: %d\n",
+         regval, chidx, avail, chan->buflen, chan->xfrd, wrsize);
 
   stm32_gint_wrpacket(priv, chan->buffer, chidx, wrsize);
 }
@@ -3190,8 +3190,8 @@ static inline void stm32_gint_ptxfeisr(FAR struct stm32_usbhost_s *priv)
 
   /* Write the next group of packets into the Tx FIFO */
 
-  ullinfo("HPTXSTS: %08x chidx: %d avail: %d buflen: %d xfrd: %d wrsize: %d\n",
-           regval, chidx, avail, chan->buflen, chan->xfrd, wrsize);
+  uinfo("HPTXSTS: %08x chidx: %d avail: %d buflen: %d xfrd: %d wrsize: %d\n",
+         regval, chidx, avail, chan->buflen, chan->xfrd, wrsize);
 
   stm32_gint_wrpacket(priv, chan->buffer, chidx, wrsize);
 }
@@ -4727,7 +4727,7 @@ static int stm32_connect(FAR struct usbhost_driver_s *drvr,
   /* Set the connected/disconnected flag */
 
   hport->connected = connected;
-  ullinfo("Hub port %d connected: %s\n", hport->port, connected ? "YES" : "NO");
+  uinfo("Hub port %d connected: %s\n", hport->port, connected ? "YES" : "NO");
 
   /* Report the connection event */
 
diff --git a/arch/arm/src/stm32/stm32_pwm.c b/arch/arm/src/stm32/stm32_pwm.c
index 36f4aa4c134..7b8f4224e08 100644
--- a/arch/arm/src/stm32/stm32_pwm.c
+++ b/arch/arm/src/stm32/stm32_pwm.c
@@ -1776,8 +1776,8 @@ static int pwm_interrupt(struct stm32_pwmtimer_s *priv)
 
   /* Now all of the time critical stuff is done so we can do some debug output */
 
-  pwmllinfo("Update interrupt SR: %04x prev: %u curr: %u count: %u\n",
-            regval, priv->prev, priv->curr, priv->count);
+  pwminfo("Update interrupt SR: %04x prev: %u curr: %u count: %u\n",
+          regval, priv->prev, priv->curr, priv->count);
 
   return OK;
 }
diff --git a/arch/arm/src/stm32/stm32_rtcc.c b/arch/arm/src/stm32/stm32_rtcc.c
index 89d97dc46b7..da8f57db592 100644
--- a/arch/arm/src/stm32/stm32_rtcc.c
+++ b/arch/arm/src/stm32/stm32_rtcc.c
@@ -694,13 +694,13 @@ int up_rtc_initialize(void)
         {
           case OK:
             {
-              rtcllinfo("rtc_syncwait() okay\n");
+              rtcinfo("rtc_syncwait() okay\n");
               break;
             }
 
           default:
             {
-              rtcllerr("ERROR: rtc_syncwait() failed (%d)\n", ret);
+              rtcerr("ERROR: rtc_syncwait() failed (%d)\n", ret);
               break;
             }
         }
@@ -714,7 +714,7 @@ int up_rtc_initialize(void)
 
   if (regval != RTC_MAGIC)
     {
-      rtcllinfo("Do setup\n");
+      rtcinfo("Do setup\n");
 
       /* Perform the one-time setup of the LSE clocking to the RTC */
 
@@ -732,7 +732,7 @@ int up_rtc_initialize(void)
     }
   else
     {
-      rtcllinfo("Do resume\n");
+      rtcinfo("Do resume\n");
 
       /* RTC already set-up, just resume normal operation */
 
@@ -748,8 +748,8 @@ int up_rtc_initialize(void)
 
   if (ret != OK && nretry > 0)
     {
-      rtcllinfo("setup/resume ran %d times and failed with %d\n",
-                nretry, ret);
+      rtcinfo("setup/resume ran %d times and failed with %d\n",
+              nretry, ret);
       return -ETIMEDOUT;
     }
 
diff --git a/arch/arm/src/stm32/stm32_sdio.c b/arch/arm/src/stm32/stm32_sdio.c
index d1317e611eb..6cd372b7fd2 100644
--- a/arch/arm/src/stm32/stm32_sdio.c
+++ b/arch/arm/src/stm32/stm32_sdio.c
@@ -907,7 +907,7 @@ static void stm32_dmacallback(DMA_HANDLE handle, uint8_t status, void *arg)
 
   if ((status & DMA_STATUS_ERROR) != 0)
     {
-      mcllerr("ERROR: DMA error %02x, remaining: %d\n", status, priv->remaining);
+      mcerr("ERROR: DMA error %02x, remaining: %d\n", status, priv->remaining);
       result = SDIOWAIT_ERROR;
     }
   else
@@ -1172,7 +1172,7 @@ static void stm32_eventtimeout(int argc, uint32_t arg)
       /* Yes.. wake up any waiting threads */
 
       stm32_endwait(priv, SDIOWAIT_TIMEOUT);
-      mcllerr("ERROR: Timeout, remaining: %d\n", priv->remaining);
+      mcerr("ERROR: Timeout, remaining: %d\n", priv->remaining);
     }
 }
 
@@ -1412,7 +1412,7 @@ static int stm32_interrupt(int irq, void *context)
             {
               /* Terminate the transfer with an error */
 
-              mcllerr("ERROR: Data block CRC failure, remaining: %d\n", priv->remaining);
+              mcerr("ERROR: Data block CRC failure, remaining: %d\n", priv->remaining);
               stm32_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR);
             }
 
@@ -1422,7 +1422,7 @@ static int stm32_interrupt(int irq, void *context)
             {
               /* Terminate the transfer with an error */
 
-              mcllerr("ERROR: Data timeout, remaining: %d\n", priv->remaining);
+              mcerr("ERROR: Data timeout, remaining: %d\n", priv->remaining);
               stm32_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_TIMEOUT);
             }
 
@@ -1432,7 +1432,7 @@ static int stm32_interrupt(int irq, void *context)
             {
               /* Terminate the transfer with an error */
 
-              mcllerr("ERROR: RX FIFO overrun, remaining: %d\n", priv->remaining);
+              mcerr("ERROR: RX FIFO overrun, remaining: %d\n", priv->remaining);
               stm32_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR);
             }
 
@@ -1442,7 +1442,7 @@ static int stm32_interrupt(int irq, void *context)
             {
               /* Terminate the transfer with an error */
 
-              mcllerr("ERROR: TX FIFO underrun, remaining: %d\n", priv->remaining);
+              mcerr("ERROR: TX FIFO underrun, remaining: %d\n", priv->remaining);
               stm32_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR);
             }
 
@@ -1452,7 +1452,7 @@ static int stm32_interrupt(int irq, void *context)
             {
               /* Terminate the transfer with an error */
 
-              mcllerr("ERROR: Start bit, remaining: %d\n", priv->remaining);
+              mcerr("ERROR: Start bit, remaining: %d\n", priv->remaining);
               stm32_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR);
             }
         }
diff --git a/arch/arm/src/stm32/stm32_usbdev.c b/arch/arm/src/stm32/stm32_usbdev.c
index 1d69a4d1755..9c69a86b8fe 100644
--- a/arch/arm/src/stm32/stm32_usbdev.c
+++ b/arch/arm/src/stm32/stm32_usbdev.c
@@ -783,7 +783,7 @@ static void stm32_checksetup(void)
   if ((apb1rstr & RCC_APB1RSTR_USBRST) != 0 ||
       (apb1enr & RCC_APB1ENR_USBEN) == 0)
     {
-      uinfo("ERROR: USB is NOT setup correctly\n");
+      uerr("ERROR: USB is NOT setup correctly\n");
     }
 }
 #endif
@@ -1368,8 +1368,8 @@ static int stm32_wrrequest(struct stm32_usbdev_s *priv, struct stm32_ep_s *prive
     }
 
   epno = USB_EPNO(privep->ep.eplog);
-  ullinfo("epno=%d req=%p: len=%d xfrd=%d nullpkt=%d\n",
-          epno, privreq, privreq->req.len, privreq->req.xfrd, privep->txnullpkt);
+  uinfo("epno=%d req=%p: len=%d xfrd=%d nullpkt=%d\n",
+        epno, privreq, privreq->req.len, privreq->req.xfrd, privep->txnullpkt);
   UNUSED(epno);
 
   /* Get the number of bytes left to be sent in the packet */
@@ -1459,7 +1459,7 @@ static inline int stm32_ep0_rdrequest(struct stm32_usbdev_s *priv)
 
   pmalen  = stm32_geteprxcount(EP0);
 
-  ullinfo("EP0: pmalen=%d\n", pmalen);
+  uinfo("EP0: pmalen=%d\n", pmalen);
   usbtrace(TRACE_READ(EP0), pmalen);
 
   /* Read the data into our special buffer for SETUP data */
@@ -1511,7 +1511,7 @@ static int stm32_rdrequest(struct stm32_usbdev_s *priv, struct stm32_ep_s *prive
       return -ENOENT;
     }
 
-  ullinfo("EP%d: len=%d xfrd=%d\n", epno, privreq->req.len, privreq->req.xfrd);
+  uinfo("EP%d: len=%d xfrd=%d\n", epno, privreq->req.len, privreq->req.xfrd);
 
   /* Ignore any attempt to receive a zero length packet */
 
@@ -1769,8 +1769,8 @@ static void stm32_ep0setup(struct stm32_usbdev_s *priv)
       index.w = GETUINT16(priv->ctrl.index);
       len.w   = GETUINT16(priv->ctrl.len);
 
-      ullinfo("SETUP: type=%02x req=%02x value=%04x index=%04x len=%04x\n",
-              priv->ctrl.type, priv->ctrl.req, value.w, index.w, len.w);
+      uinfo("SETUP: type=%02x req=%02x value=%04x index=%04x len=%04x\n",
+            priv->ctrl.type, priv->ctrl.req, value.w, index.w, len.w);
 
       /* Is this an setup with OUT and data of length > 0 */
 
@@ -1960,7 +1960,7 @@ static void stm32_ep0setup(struct stm32_usbdev_s *priv)
           {
             /* Special case recipient=device test mode */
 
-            ullinfo("test mode: %d\n", index.w);
+            uinfo("test mode: %d\n", index.w);
           }
         else if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) != USB_REQ_RECIPIENT_ENDPOINT)
           {
@@ -3029,7 +3029,8 @@ static int stm32_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req)
   if (!req || !req->callback || !req->buf || !ep)
     {
       usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0);
-      uerr("ERROR: req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, ep);
+      uerr("ERROR: req=%p callback=%p buf=%p ep=%p\n",
+           req, req->callback, req->buf, ep);
       return -EINVAL;
     }
 #endif
diff --git a/arch/arm/src/stm32/stm32f40xxx_rcc.c b/arch/arm/src/stm32/stm32f40xxx_rcc.c
index d431ce6df7a..3d259ec5c39 100644
--- a/arch/arm/src/stm32/stm32f40xxx_rcc.c
+++ b/arch/arm/src/stm32/stm32f40xxx_rcc.c
@@ -911,7 +911,7 @@ static void stm32_stdclockconfig(void)
  *
  ****************************************************************************/
 
-#if defined(CONFIG_SYSLOG) && defined(CONFIG_ARMV7M_ITMSYSLOG)
+#ifdef CONFIG_ARMV7M_ITMSYSLOG
 static inline void rcc_itm_syslog(void)
 {
   /* Enable SWO output */
diff --git a/arch/arm/src/stm32/stm32f40xxx_rtcc.c b/arch/arm/src/stm32/stm32f40xxx_rtcc.c
index 52746879636..0e55a4ad7dd 100644
--- a/arch/arm/src/stm32/stm32f40xxx_rtcc.c
+++ b/arch/arm/src/stm32/stm32f40xxx_rtcc.c
@@ -954,13 +954,13 @@ int up_rtc_initialize(void)
         {
           case OK:
             {
-              rtcllinfo("rtc_syncwait() okay\n");
+              rtcinfo("rtc_syncwait() okay\n");
               break;
             }
 
           default:
             {
-              rtcllerr("ERROR: rtc_syncwait() failed (%d)\n", ret);
+              rtcerr("ERROR: rtc_syncwait() failed (%d)\n", ret);
               break;
             }
         }
@@ -974,7 +974,7 @@ int up_rtc_initialize(void)
 
   if (regval != RTC_MAGIC)
     {
-      rtcllinfo("Do setup\n");
+      rtcinfo("Do setup\n");
 
       /* Perform the one-time setup of the LSE clocking to the RTC */
 
@@ -992,7 +992,7 @@ int up_rtc_initialize(void)
     }
   else
     {
-      rtcllinfo("Do resume\n");
+      rtcinfo("Do resume\n");
 
       /* RTC already set-up, just resume normal operation */
 
@@ -1008,8 +1008,8 @@ int up_rtc_initialize(void)
 
   if (ret != OK && nretry > 0)
     {
-      rtcllinfo("setup/resume ran %d times and failed with %d\n",
-                nretry, ret);
+      rtcinfo("setup/resume ran %d times and failed with %d\n",
+              nretry, ret);
       return -ETIMEDOUT;
     }
 
@@ -1374,7 +1374,7 @@ int stm32_rtc_setalarm(FAR struct alm_setalarm_s *alminfo)
 #endif
 
       default:
-        rtcinfo("ERROR: Invalid ALARM%d\n", alminfo->as_id);
+        rtcerr("ERROR: Invalid ALARM%d\n", alminfo->as_id);
         break;
     }
 
@@ -1472,7 +1472,7 @@ int stm32_rtc_cancelalarm(enum alm_id_e alarmid)
 #endif
 
       default:
-        rtcinfo("ERROR: Invalid ALARM%d\n", alarmid);
+        rtcerr("ERROR: Invalid ALARM%d\n", alarmid);
         break;
     }
 
diff --git a/arch/arm/src/stm32f7/Kconfig b/arch/arm/src/stm32f7/Kconfig
index b43c48a9ddf..0f2f65f84a2 100644
--- a/arch/arm/src/stm32f7/Kconfig
+++ b/arch/arm/src/stm32f7/Kconfig
@@ -916,6 +916,19 @@ config STM32F7_HAVE_SDMMC2
 	bool
 	default n
 
+config STM32F7_HAVE_ADC1_DMA
+	bool
+	default n
+
+config STM32F7_HAVE_ADC2_DMA
+	bool
+	default n
+
+config STM32F7_HAVE_ADC3_DMA
+	bool
+	default n
+
+
 config STM32F7_HAVE_CAN3
 	bool
 	default n
@@ -993,20 +1006,26 @@ config STM32F7_USART
 
 # These are the peripheral selections proper
 
+
 config STM32F7_ADC1
 	bool "ADC1"
 	default n
 	select STM32F7_ADC
+	select STM32F7_HAVE_ADC1_DMA if STM32F7_DMA1
+	select STM32F7_HAVE_ADC1_DMA if STM32F7_DMA2
 
 config STM32F7_ADC2
 	bool "ADC2"
 	default n
 	select STM32F7_ADC
+	select STM32F7_HAVE_ADC2_DMA if STM32F7_DMA2
 
 config STM32F7_ADC3
 	bool "ADC3"
 	default n
 	select STM32F7_ADC
+	select STM32F7_HAVE_ADC1_DMA if STM32F7_DMA1
+	select STM32F7_HAVE_ADC1_DMA if STM32F7_DMA2
 
 config STM32F7_BKPSRAM
 	bool "Enable BKP RAM Domain"
@@ -1124,15 +1143,15 @@ config STM32F7_HASH
 	depends on STM32F7_HAVE_HASH
 	select ARCH_HAVE_HASH
 
+config STM32F7_CEC
+	bool "HDMI-CEC"
+	default n
+
 config STM32F7_I2C1
 	bool "I2C1"
 	default n
 	select STM32F7_I2C
 
-config STM32F7_CEC
-	bool "HDMI-CEC"
-	default n
-
 config STM32F7_I2C2
 	bool "I2C2"
 	default n
@@ -1143,6 +1162,11 @@ config STM32F7_I2C3
 	default n
 	select STM32F7_I2C
 
+config STM32F7_I2C4
+	bool "I2C4"
+	default n
+	select STM32F7_I2C
+
 config STM32F7_LPTIM1
 	bool "Low-power timer 1"
 	default n
@@ -1310,11 +1334,6 @@ config STM32F7_TIM14
 	default n
 	select STM32F7_TIM
 
-config STM32F7_TIM15
-	bool "TIM15"
-	default n
-	select STM32F7_TIM
-
 config STM32F7_USART1
 	bool "USART1"
 	default n
@@ -1651,6 +1670,46 @@ config STM32F7_SPI_DMA
 
 endmenu # "SPI Configuration"
 
+menu "I2C Configuration"
+	depends on STM32F7_I2C
+
+config STM32F7_I2C_DYNTIMEO
+	bool "Use dynamic timeouts"
+	default n
+	depends on STM32F7_I2C
+
+config STM32F7_I2C_DYNTIMEO_USECPERBYTE
+	int "Timeout Microseconds per Byte"
+	default 500
+	depends on STM32F7_I2C_DYNTIMEO
+
+config STM32F7_I2C_DYNTIMEO_STARTSTOP
+	int "Timeout for Start/Stop (Milliseconds)"
+	default 1000
+	depends on STM32F7_I2C_DYNTIMEO
+
+config STM32F7_I2CTIMEOSEC
+	int "Timeout seconds"
+	default 0
+	depends on STM32F7_I2C
+
+config STM32F7_I2CTIMEOMS
+	int "Timeout Milliseconds"
+	default 500
+	depends on STM32F7_I2C && !STM32F7_I2C_DYNTIMEO
+
+config STM32F7_I2CTIMEOTICKS
+	int "Timeout for Done and Stop (ticks)"
+	default 500
+	depends on STM32F7_I2C && !STM32F7_I2C_DYNTIMEO
+
+config STM32F7_I2C_DUTY16_9
+	bool "Frequency with Tlow/Thigh = 16/9 "
+	default n
+	depends on STM32F7_I2C
+
+endmenu # "I2C Configuration"
+
 config STM32F7_CUSTOM_CLOCKCONFIG
 		bool "Custom clock configuration"
 	default n
@@ -1669,14 +1728,2756 @@ config STM32F7_DTCM_PROCFS
 config STM32F7_DMACAPABLE
 	bool "Workaround non-DMA capable memory"
 	depends on ARCH_DMA
-	default y if !STM32_CCMEXCLUDE
-	default n if STM32_CCMEXCLUDE
+	default y if !STM32F7_CCMEXCLUDE
+	default n if STM32F7_CCMEXCLUDE
 	---help---
 		This option enables the DMA interface stm32_dmacapable that can be
 		used to check if it is possible to do DMA from the selected address.
 		Drivers then may use this information to determine if they should
 		attempt the DMA or fall back to a different transfer method.
 
+menu "Timer Configuration"
+
+config STM32F7_TIM1_PWM
+	bool "TIM1 PWM"
+	default n
+	depends on STM32F7_TIM1
+	select ARCH_HAVE_PWM_PULSECOUNT
+	---help---
+		Reserve timer 1 for use by PWM
+
+		Timer devices may be used for different purposes.  One special purpose is
+		to generate modulated outputs for such things as motor control.  If STM32F7_TIM1
+		is defined then THIS following may also be defined to indicate that
+		the timer is intended to be used for pulsed output modulation.
+
+if STM32F7_TIM1_PWM
+
+config STM32F7_TIM1_MODE
+	int "TIM1 Mode"
+	default 0
+	range 0 4
+	---help---
+		Specifies the timer mode.
+
+if STM32F7_PWM_MULTICHAN
+
+config STM32F7_TIM1_CHANNEL1
+	bool "TIM1 Channel 1"
+	default n
+	---help---
+		Enables channel 1.
+
+if STM32F7_TIM1_CHANNEL1
+
+config STM32F7_TIM1_CH1MODE
+	int "TIM1 Channel 1 Mode"
+	default 0
+	range 0 5
+	---help---
+		Specifies the channel mode.
+
+config STM32F7_TIM1_CH1OUT
+	bool "TIM1 Channel 1 Output"
+	default n
+	---help---
+		Enables channel 1 output.
+
+endif # STM32F7_TIM1_CHANNEL1
+
+config STM32F7_TIM1_CHANNEL2
+	bool "TIM1 Channel 2"
+	default n
+	---help---
+		Enables channel 2.
+
+if STM32F7_TIM1_CHANNEL2
+
+config STM32F7_TIM1_CH2MODE
+	int "TIM1 Channel 2 Mode"
+	default 0
+	range 0 5
+	---help---
+		Specifies the channel mode.
+
+config STM32F7_TIM1_CH2OUT
+	bool "TIM1 Channel 2 Output"
+	default n
+	---help---
+		Enables channel 2 output.
+
+endif # STM32F7_TIM1_CHANNEL2
+
+config STM32F7_TIM1_CHANNEL3
+	bool "TIM1 Channel 3"
+	default n
+	---help---
+		Enables channel 3.
+
+if STM32F7_TIM1_CHANNEL3
+
+config STM32F7_TIM1_CH3MODE
+	int "TIM1 Channel 3 Mode"
+	default 0
+	range 0 5
+	---help---
+		Specifies the channel mode.
+
+config STM32F7_TIM1_CH3OUT
+	bool "TIM1 Channel 3 Output"
+	default n
+	---help---
+		Enables channel 3 output.
+
+endif # STM32F7_TIM1_CHANNEL3
+
+config STM32F7_TIM1_CHANNEL4
+	bool "TIM1 Channel 4"
+	default n
+	---help---
+		Enables channel 4.
+
+if STM32F7_TIM1_CHANNEL4
+
+config STM32F7_TIM1_CH4MODE
+	int "TIM1 Channel 4 Mode"
+	default 0
+	range 0 5
+	---help---
+		Specifies the channel mode.
+
+config STM32F7_TIM1_CH4OUT
+	bool "TIM1 Channel 4 Output"
+	default n
+	---help---
+		Enables channel 4 output.
+
+endif # STM32F7_TIM1_CHANNEL4
+
+endif # STM32F7_PWM_MULTICHAN
+
+if !STM32F7_PWM_MULTICHAN
+
+config STM32F7_TIM1_CHANNEL
+	int "TIM1 PWM Output Channel"
+	default 1
+	range 1 4
+	---help---
+		If TIM1 is enabled for PWM usage, you also need specifies the timer output
+		channel {1,..,4}
+
+config STM32F7_TIM1_CHMODE
+	int "TIM1 Channel Mode"
+	default 0
+	range 0 5
+	---help---
+		Specifies the channel mode.
+
+endif # !STM32F7_PWM_MULTICHAN
+
+endif # STM32F7_TIM1_PWM
+
+config STM32F7_TIM2_PWM
+	bool "TIM2 PWM"
+	default n
+	depends on STM32F7_TIM2
+	select ARCH_HAVE_PWM_PULSECOUNT
+	---help---
+		Reserve timer 2 for use by PWM
+
+		Timer devices may be used for different purposes.  One special purpose is
+		to generate modulated outputs for such things as motor control.  If STM32F7_TIM2
+		is defined then THIS following may also be defined to indicate that
+		the timer is intended to be used for pulsed output modulation.
+
+if STM32F7_TIM2_PWM
+
+config STM32F7_TIM2_MODE
+	int "TIM2 Mode"
+	default 0
+	range 0 4
+	---help---
+		Specifies the timer mode.
+
+if STM32F7_PWM_MULTICHAN
+
+config STM32F7_TIM2_CHANNEL1
+	bool "TIM2 Channel 1"
+	default n
+	---help---
+		Enables channel 1.
+
+if STM32F7_TIM2_CHANNEL1
+
+config STM32F7_TIM2_CH1MODE
+	int "TIM2 Channel 1 Mode"
+	default 0
+	range 0 5
+	---help---
+		Specifies the channel mode.
+
+config STM32F7_TIM2_CH1OUT
+	bool "TIM2 Channel 1 Output"
+	default n
+	---help---
+		Enables channel 1 output.
+
+endif # STM32F7_TIM2_CHANNEL1
+
+config STM32F7_TIM2_CHANNEL2
+	bool "TIM2 Channel 2"
+	default n
+	---help---
+		Enables channel 2.
+
+if STM32F7_TIM2_CHANNEL2
+
+config STM32F7_TIM2_CH2MODE
+	int "TIM2 Channel 2 Mode"
+	default 0
+	range 0 5
+	---help---
+		Specifies the channel mode.
+
+config STM32F7_TIM2_CH2OUT
+	bool "TIM2 Channel 2 Output"
+	default n
+	---help---
+		Enables channel 2 output.
+
+endif # STM32F7_TIM2_CHANNEL2
+
+config STM32F7_TIM2_CHANNEL3
+	bool "TIM2 Channel 3"
+	default n
+	---help---
+		Enables channel 3.
+
+if STM32F7_TIM2_CHANNEL3
+
+config STM32F7_TIM2_CH3MODE
+	int "TIM2 Channel 3 Mode"
+	default 0
+	range 0 5
+	---help---
+		Specifies the channel mode.
+
+config STM32F7_TIM2_CH3OUT
+	bool "TIM2 Channel 3 Output"
+	default n
+	---help---
+		Enables channel 3 output.
+
+endif # STM32F7_TIM2_CHANNEL3
+
+config STM32F7_TIM2_CHANNEL4
+	bool "TIM2 Channel 4"
+	default n
+	---help---
+		Enables channel 4.
+
+if STM32F7_TIM2_CHANNEL4
+
+config STM32F7_TIM2_CH4MODE
+	int "TIM2 Channel 4 Mode"
+	default 0
+	range 0 5
+	---help---
+		Specifies the channel mode.
+
+config STM32F7_TIM2_CH4OUT
+	bool "TIM2 Channel 4 Output"
+	default n
+	---help---
+		Enables channel 4 output.
+
+endif # STM32F7_TIM2_CHANNEL4
+
+endif # STM32F7_PWM_MULTICHAN
+
+if !STM32F7_PWM_MULTICHAN
+
+config STM32F7_TIM2_CHANNEL
+	int "TIM2 PWM Output Channel"
+	default 1
+	range 1 4
+	---help---
+		If TIM2 is enabled for PWM usage, you also need specifies the timer output
+		channel {1,..,4}
+
+config STM32F7_TIM2_CHMODE
+	int "TIM2 Channel Mode"
+	default 0
+	range 0 5
+	---help---
+		Specifies the channel mode.
+
+endif # !STM32F7_PWM_MULTICHAN
+
+endif # STM32F7_TIM2_PWM
+
+config STM32F7_TIM3_PWM
+	bool "TIM3 PWM"
+	default n
+	depends on STM32F7_TIM3
+	select ARCH_HAVE_PWM_PULSECOUNT
+	---help---
+		Reserve timer 3 for use by PWM
+
+		Timer devices may be used for different purposes.  One special purpose is
+		to generate modulated outputs for such things as motor control.  If STM32F7_TIM3
+		is defined then THIS following may also be defined to indicate that
+		the timer is intended to be used for pulsed output modulation.
+
+if STM32F7_TIM3_PWM
+
+config STM32F7_TIM3_MODE
+	int "TIM3 Mode"
+	default 0
+	range 0 4
+	---help---
+		Specifies the timer mode.
+
+if STM32F7_PWM_MULTICHAN
+
+config STM32F7_TIM3_CHANNEL1
+	bool "TIM3 Channel 1"
+	default n
+	---help---
+		Enables channel 1.
+
+if STM32F7_TIM3_CHANNEL1
+
+config STM32F7_TIM3_CH1MODE
+	int "TIM3 Channel 1 Mode"
+	default 0
+	range 0 5
+	---help---
+		Specifies the channel mode.
+
+config STM32F7_TIM3_CH1OUT
+	bool "TIM3 Channel 1 Output"
+	default n
+	---help---
+		Enables channel 1 output.
+
+endif # STM32F7_TIM3_CHANNEL1
+
+config STM32F7_TIM3_CHANNEL2
+	bool "TIM3 Channel 2"
+	default n
+	---help---
+		Enables channel 2.
+
+if STM32F7_TIM3_CHANNEL2
+
+config STM32F7_TIM3_CH2MODE
+	int "TIM3 Channel 2 Mode"
+	default 0
+	range 0 5
+	---help---
+		Specifies the channel mode.
+
+config STM32F7_TIM3_CH2OUT
+	bool "TIM3 Channel 2 Output"
+	default n
+	---help---
+		Enables channel 2 output.
+
+endif # STM32F7_TIM3_CHANNEL2
+
+config STM32F7_TIM3_CHANNEL3
+	bool "TIM3 Channel 3"
+	default n
+	---help---
+		Enables channel 3.
+
+if STM32F7_TIM3_CHANNEL3
+
+config STM32F7_TIM3_CH3MODE
+	int "TIM3 Channel 3 Mode"
+	default 0
+	range 0 5
+	---help---
+		Specifies the channel mode.
+
+config STM32F7_TIM3_CH3OUT
+	bool "TIM3 Channel 3 Output"
+	default n
+	---help---
+		Enables channel 3 output.
+
+endif # STM32F7_TIM3_CHANNEL3
+
+config STM32F7_TIM3_CHANNEL4
+	bool "TIM3 Channel 4"
+	default n
+	---help---
+		Enables channel 4.
+
+if STM32F7_TIM3_CHANNEL4
+
+config STM32F7_TIM3_CH4MODE
+	int "TIM3 Channel 4 Mode"
+	default 0
+	range 0 5
+	---help---
+		Specifies the channel mode.
+
+config STM32F7_TIM3_CH4OUT
+	bool "TIM3 Channel 4 Output"
+	default n
+	---help---
+		Enables channel 4 output.
+
+endif # STM32F7_TIM3_CHANNEL4
+
+endif # STM32F7_PWM_MULTICHAN
+
+if !STM32F7_PWM_MULTICHAN
+
+config STM32F7_TIM3_CHANNEL
+	int "TIM3 PWM Output Channel"
+	default 1
+	range 1 4
+	---help---
+		If TIM3 is enabled for PWM usage, you also need specifies the timer output
+		channel {1,..,4}
+
+config STM32F7_TIM3_CHMODE
+	int "TIM3 Channel Mode"
+	default 0
+	range 0 5
+	---help---
+		Specifies the channel mode.
+
+endif # !STM32F7_PWM_MULTICHAN
+
+endif # STM32F7_TIM3_PWM
+
+config STM32F7_TIM4_PWM
+	bool "TIM4 PWM"
+	default n
+	depends on STM32F7_TIM4
+	select ARCH_HAVE_PWM_PULSECOUNT
+	---help---
+		Reserve timer 4 for use by PWM
+
+		Timer devices may be used for different purposes.  One special purpose is
+		to generate modulated outputs for such things as motor control.  If STM32F7_TIM4
+		is defined then THIS following may also be defined to indicate that
+		the timer is intended to be used for pulsed output modulation.
+
+if STM32F7_TIM4_PWM
+
+config STM32F7_TIM4_MODE
+	int "TIM4 Mode"
+	default 0
+	range 0 4
+	---help---
+		Specifies the timer mode.
+
+if STM32F7_PWM_MULTICHAN
+
+config STM32F7_TIM4_CHANNEL1
+	bool "TIM4 Channel 1"
+	default n
+	---help---
+		Enables channel 1.
+
+if STM32F7_TIM4_CHANNEL1
+
+config STM32F7_TIM4_CH1MODE
+	int "TIM4 Channel 1 Mode"
+	default 0
+	range 0 5
+	---help---
+		Specifies the channel mode.
+
+config STM32F7_TIM4_CH1OUT
+	bool "TIM4 Channel 1 Output"
+	default n
+	---help---
+		Enables channel 1 output.
+
+endif # STM32F7_TIM4_CHANNEL1
+
+config STM32F7_TIM4_CHANNEL2
+	bool "TIM4 Channel 2"
+	default n
+	---help---
+		Enables channel 2.
+
+if STM32F7_TIM4_CHANNEL2
+
+config STM32F7_TIM4_CH2MODE
+	int "TIM4 Channel 2 Mode"
+	default 0
+	range 0 5
+	---help---
+		Specifies the channel mode.
+
+config STM32F7_TIM4_CH2OUT
+	bool "TIM4 Channel 2 Output"
+	default n
+	---help---
+		Enables channel 2 output.
+
+endif # STM32F7_TIM4_CHANNEL2
+
+config STM32F7_TIM4_CHANNEL3
+	bool "TIM4 Channel 3"
+	default n
+	---help---
+		Enables channel 3.
+
+if STM32F7_TIM4_CHANNEL3
+
+config STM32F7_TIM4_CH3MODE
+	int "TIM4 Channel 3 Mode"
+	default 0
+	range 0 5
+	---help---
+		Specifies the channel mode.
+
+config STM32F7_TIM4_CH3OUT
+	bool "TIM4 Channel 3 Output"
+	default n
+	---help---
+		Enables channel 3 output.
+
+endif # STM32F7_TIM4_CHANNEL3
+
+config STM32F7_TIM4_CHANNEL4
+	bool "TIM4 Channel 4"
+	default n
+	---help---
+		Enables channel 4.
+
+if STM32F7_TIM4_CHANNEL4
+
+config STM32F7_TIM4_CH4MODE
+	int "TIM4 Channel 4 Mode"
+	default 0
+	range 0 5
+	---help---
+		Specifies the channel mode.
+
+config STM32F7_TIM4_CH4OUT
+	bool "TIM4 Channel 4 Output"
+	default n
+	---help---
+		Enables channel 4 output.
+
+endif # STM32F7_TIM4_CHANNEL4
+
+endif # STM32F7_PWM_MULTICHAN
+
+if !STM32F7_PWM_MULTICHAN
+
+config STM32F7_TIM4_CHANNEL
+	int "TIM4 PWM Output Channel"
+	default 1
+	range 1 4
+	---help---
+		If TIM4 is enabled for PWM usage, you also need specifies the timer output
+		channel {1,..,4}
+
+config STM32F7_TIM4_CHMODE
+	int "TIM4 Channel Mode"
+	default 0
+	range 0 5
+	---help---
+		Specifies the channel mode.
+
+endif # !STM32F7_PWM_MULTICHAN
+
+endif # STM32F7_TIM4_PWM
+
+config STM32F7_TIM5_PWM
+	bool "TIM5 PWM"
+	default n
+	depends on STM32F7_TIM5
+	select ARCH_HAVE_PWM_PULSECOUNT
+	---help---
+		Reserve timer 5 for use by PWM
+
+		Timer devices may be used for different purposes.  One special purpose is
+		to generate modulated outputs for such things as motor control.  If STM32F7_TIM5
+		is defined then THIS following may also be defined to indicate that
+		the timer is intended to be used for pulsed output modulation.
+
+if STM32F7_TIM5_PWM
+
+config STM32F7_TIM5_MODE
+	int "TIM5 Mode"
+	default 0
+	range 0 4
+	---help---
+		Specifies the timer mode.
+
+if STM32F7_PWM_MULTICHAN
+
+config STM32F7_TIM5_CHANNEL1
+	bool "TIM5 Channel 1"
+	default n
+	---help---
+		Enables channel 1.
+
+if STM32F7_TIM5_CHANNEL1
+
+config STM32F7_TIM5_CH1MODE
+	int "TIM5 Channel 1 Mode"
+	default 0
+	range 0 5
+	---help---
+		Specifies the channel mode.
+
+config STM32F7_TIM5_CH1OUT
+	bool "TIM5 Channel 1 Output"
+	default n
+	---help---
+		Enables channel 1 output.
+
+endif # STM32F7_TIM5_CHANNEL1
+
+config STM32F7_TIM5_CHANNEL2
+	bool "TIM5 Channel 2"
+	default n
+	---help---
+		Enables channel 2.
+
+if STM32F7_TIM5_CHANNEL2
+
+config STM32F7_TIM5_CH2MODE
+	int "TIM5 Channel 2 Mode"
+	default 0
+	range 0 5
+	---help---
+		Specifies the channel mode.
+
+config STM32F7_TIM5_CH2OUT
+	bool "TIM5 Channel 2 Output"
+	default n
+	---help---
+		Enables channel 2 output.
+
+endif # STM32F7_TIM5_CHANNEL2
+
+config STM32F7_TIM5_CHANNEL3
+	bool "TIM5 Channel 3"
+	default n
+	---help---
+		Enables channel 3.
+
+if STM32F7_TIM5_CHANNEL3
+
+config STM32F7_TIM5_CH3MODE
+	int "TIM5 Channel 3 Mode"
+	default 0
+	range 0 5
+	---help---
+		Specifies the channel mode.
+
+config STM32F7_TIM5_CH3OUT
+	bool "TIM5 Channel 3 Output"
+	default n
+	---help---
+		Enables channel 3 output.
+
+endif # STM32F7_TIM5_CHANNEL3
+
+config STM32F7_TIM5_CHANNEL4
+	bool "TIM5 Channel 4"
+	default n
+	---help---
+		Enables channel 4.
+
+if STM32F7_TIM5_CHANNEL4
+
+config STM32F7_TIM5_CH4MODE
+	int "TIM5 Channel 4 Mode"
+	default 0
+	range 0 5
+	---help---
+		Specifies the channel mode.
+
+config STM32F7_TIM5_CH4OUT
+	bool "TIM5 Channel 4 Output"
+	default n
+	---help---
+		Enables channel 4 output.
+
+endif # STM32F7_TIM5_CHANNEL4
+
+endif # STM32F7_PWM_MULTICHAN
+
+if !STM32F7_PWM_MULTICHAN
+
+config STM32F7_TIM5_CHANNEL
+	int "TIM5 PWM Output Channel"
+	default 1
+	range 1 4
+	---help---
+		If TIM5 is enabled for PWM usage, you also need specifies the timer output
+		channel {1,..,4}
+
+config STM32F7_TIM5_CHMODE
+	int "TIM5 Channel Mode"
+	default 0
+	range 0 5
+	---help---
+		Specifies the channel mode.
+
+endif # !STM32F7_PWM_MULTICHAN
+
+endif # STM32F7_TIM5_PWM
+
+config STM32F7_TIM8_PWM
+	bool "TIM8 PWM"
+	default n
+	depends on STM32F7_TIM8
+	select ARCH_HAVE_PWM_PULSECOUNT
+	---help---
+		Reserve timer 8 for use by PWM
+
+		Timer devices may be used for different purposes.  One special purpose is
+		to generate modulated outputs for such things as motor control.  If STM32F7_TIM8
+		is defined then THIS following may also be defined to indicate that
+		the timer is intended to be used for pulsed output modulation.
+
+if STM32F7_TIM8_PWM
+
+config STM32F7_TIM8_MODE
+	int "TIM8 Mode"
+	default 0
+	range 0 4
+	---help---
+		Specifies the timer mode.
+
+if STM32F7_PWM_MULTICHAN
+
+config STM32F7_TIM8_CHANNEL1
+	bool "TIM8 Channel 1"
+	default n
+	---help---
+		Enables channel 1.
+
+if STM32F7_TIM8_CHANNEL1
+
+config STM32F7_TIM8_CH1MODE
+	int "TIM8 Channel 1 Mode"
+	default 0
+	range 0 5
+	---help---
+		Specifies the channel mode.
+
+config STM32F7_TIM8_CH1OUT
+	bool "TIM8 Channel 1 Output"
+	default n
+	---help---
+		Enables channel 1 output.
+
+endif # STM32F7_TIM8_CHANNEL1
+
+config STM32F7_TIM8_CHANNEL2
+	bool "TIM8 Channel 2"
+	default n
+	---help---
+		Enables channel 2.
+
+if STM32F7_TIM8_CHANNEL2
+
+config STM32F7_TIM8_CH2MODE
+	int "TIM8 Channel 2 Mode"
+	default 0
+	range 0 5
+	---help---
+		Specifies the channel mode.
+
+config STM32F7_TIM8_CH2OUT
+	bool "TIM8 Channel 2 Output"
+	default n
+	---help---
+		Enables channel 2 output.
+
+endif # STM32F7_TIM8_CHANNEL2
+
+config STM32F7_TIM8_CHANNEL3
+	bool "TIM8 Channel 3"
+	default n
+	---help---
+		Enables channel 3.
+
+if STM32F7_TIM8_CHANNEL3
+
+config STM32F7_TIM8_CH3MODE
+	int "TIM8 Channel 3 Mode"
+	default 0
+	range 0 5
+	---help---
+		Specifies the channel mode.
+
+config STM32F7_TIM8_CH3OUT
+	bool "TIM8 Channel 3 Output"
+	default n
+	---help---
+		Enables channel 3 output.
+
+endif # STM32F7_TIM8_CHANNEL3
+
+config STM32F7_TIM8_CHANNEL4
+	bool "TIM8 Channel 4"
+	default n
+	---help---
+		Enables channel 4.
+
+if STM32F7_TIM8_CHANNEL4
+
+config STM32F7_TIM8_CH4MODE
+	int "TIM8 Channel 4 Mode"
+	default 0
+	range 0 5
+	---help---
+		Specifies the channel mode.
+
+config STM32F7_TIM8_CH4OUT
+	bool "TIM8 Channel 4 Output"
+	default n
+	---help---
+		Enables channel 4 output.
+
+endif # STM32F7_TIM8_CHANNEL4
+
+endif # STM32F7_PWM_MULTICHAN
+
+if !STM32F7_PWM_MULTICHAN
+
+config STM32F7_TIM8_CHANNEL
+	int "TIM8 PWM Output Channel"
+	default 1
+	range 1 4
+	---help---
+		If TIM8 is enabled for PWM usage, you also need specifies the timer output
+		channel {1,..,4}
+
+config STM32F7_TIM8_CHMODE
+	int "TIM8 Channel Mode"
+	default 0
+	range 0 5
+	---help---
+		Specifies the channel mode.
+
+endif # !STM32F7_PWM_MULTICHAN
+
+endif # STM32F7_TIM8_PWM
+
+config STM32F7_TIM9_PWM
+	bool "TIM9 PWM"
+	default n
+	depends on STM32F7_TIM9
+	select ARCH_HAVE_PWM_PULSECOUNT
+	---help---
+		Reserve timer 9 for use by PWM
+
+		Timer devices may be used for different purposes.  One special purpose is
+		to generate modulated outputs for such things as motor control.  If STM32F7_TIM9
+		is defined then THIS following may also be defined to indicate that
+		the timer is intended to be used for pulsed output modulation.
+
+if STM32F7_TIM9_PWM
+
+if STM32F7_PWM_MULTICHAN
+
+config STM32F7_TIM9_CHANNEL1
+	bool "TIM9 Channel 1"
+	default n
+	---help---
+		Enables channel 1.
+
+if STM32F7_TIM9_CHANNEL1
+
+config STM32F7_TIM9_CH1MODE
+	int "TIM9 Channel 1 Mode"
+	default 0
+	range 0 5
+	---help---
+		Specifies the channel mode.
+
+config STM32F7_TIM9_CH1OUT
+	bool "TIM9 Channel 1 Output"
+	default n
+	---help---
+		Enables channel 1 output.
+
+endif # STM32F7_TIM9_CHANNEL1
+
+config STM32F7_TIM9_CHANNEL2
+	bool "TIM9 Channel 2"
+	default n
+	---help---
+		Enables channel 2.
+
+if STM32F7_TIM9_CHANNEL2
+
+config STM32F7_TIM9_CH2MODE
+	int "TIM9 Channel 2 Mode"
+	default 0
+	range 0 5
+	---help---
+		Specifies the channel mode.
+
+config STM32F7_TIM9_CH2OUT
+	bool "TIM9 Channel 2 Output"
+	default n
+	---help---
+		Enables channel 2 output.
+
+endif # STM32F7_TIM9_CHANNEL2
+
+config STM32F7_TIM9_CHANNEL3
+	bool "TIM9 Channel 3"
+	default n
+	---help---
+		Enables channel 3.
+
+if STM32F7_TIM9_CHANNEL3
+
+config STM32F7_TIM9_CH3MODE
+	int "TIM9 Channel 3 Mode"
+	default 0
+	range 0 5
+	---help---
+		Specifies the channel mode.
+
+config STM32F7_TIM9_CH3OUT
+	bool "TIM9 Channel 3 Output"
+	default n
+	---help---
+		Enables channel 3 output.
+
+endif # STM32F7_TIM9_CHANNEL3
+
+config STM32F7_TIM9_CHANNEL4
+	bool "TIM9 Channel 4"
+	default n
+	---help---
+		Enables channel 4.
+
+if STM32F7_TIM9_CHANNEL4
+
+config STM32F7_TIM9_CH4MODE
+	int "TIM9 Channel 4 Mode"
+	default 0
+	range 0 5
+	---help---
+		Specifies the channel mode.
+
+config STM32F7_TIM9_CH4OUT
+	bool "TIM9 Channel 4 Output"
+	default n
+	---help---
+		Enables channel 4 output.
+
+endif # STM32F7_TIM9_CHANNEL4
+
+endif # STM32F7_PWM_MULTICHAN
+
+if !STM32F7_PWM_MULTICHAN
+
+config STM32F7_TIM9_CHANNEL
+	int "TIM9 PWM Output Channel"
+	default 1
+	range 1 4
+	---help---
+		If TIM9 is enabled for PWM usage, you also need specifies the timer output
+		channel {1,..,4}
+
+config STM32F7_TIM9_CHMODE
+	int "TIM9 Channel Mode"
+	default 0
+	range 0 5
+	---help---
+		Specifies the channel mode.
+
+endif # !STM32F7_PWM_MULTICHAN
+
+endif # STM32F7_TIM9_PWM
+
+config STM32F7_TIM10_PWM
+	bool "TIM10 PWM"
+	default n
+	depends on STM32F7_TIM10
+	select ARCH_HAVE_PWM_PULSECOUNT
+	---help---
+		Reserve timer 10 for use by PWM
+
+		Timer devices may be used for different purposes.  One special purpose is
+		to generate modulated outputs for such things as motor control.  If STM32F7_TIM10
+		is defined then THIS following may also be defined to indicate that
+		the timer is intended to be used for pulsed output modulation.
+
+if STM32F7_TIM10_PWM
+
+if STM32F7_PWM_MULTICHAN
+
+config STM32F7_TIM10_CHANNEL1
+	bool "TIM10 Channel 1"
+	default n
+	---help---
+		Enables channel 1.
+
+if STM32F7_TIM10_CHANNEL1
+
+config STM32F7_TIM10_CH1MODE
+	int "TIM10 Channel 1 Mode"
+	default 0
+	range 0 5
+	---help---
+		Specifies the channel mode.
+
+config STM32F7_TIM10_CH1OUT
+	bool "TIM10 Channel 1 Output"
+	default n
+	---help---
+		Enables channel 1 output.
+
+endif # STM32F7_TIM10_CHANNEL1
+
+config STM32F7_TIM10_CHANNEL2
+	bool "TIM10 Channel 2"
+	default n
+	---help---
+		Enables channel 2.
+
+if STM32F7_TIM10_CHANNEL2
+
+config STM32F7_TIM10_CH2MODE
+	int "TIM10 Channel 2 Mode"
+	default 0
+	range 0 5
+	---help---
+		Specifies the channel mode.
+
+config STM32F7_TIM10_CH2OUT
+	bool "TIM10 Channel 2 Output"
+	default n
+	---help---
+		Enables channel 2 output.
+
+endif # STM32F7_TIM10_CHANNEL2
+
+config STM32F7_TIM10_CHANNEL3
+	bool "TIM10 Channel 3"
+	default n
+	---help---
+		Enables channel 3.
+
+if STM32F7_TIM10_CHANNEL3
+
+config STM32F7_TIM10_CH3MODE
+	int "TIM10 Channel 3 Mode"
+	default 0
+	range 0 5
+	---help---
+		Specifies the channel mode.
+
+config STM32F7_TIM10_CH3OUT
+	bool "TIM10 Channel 3 Output"
+	default n
+	---help---
+		Enables channel 3 output.
+
+endif # STM32F7_TIM10_CHANNEL3
+
+config STM32F7_TIM10_CHANNEL4
+	bool "TIM10 Channel 4"
+	default n
+	---help---
+		Enables channel 4.
+
+if STM32F7_TIM10_CHANNEL4
+
+config STM32F7_TIM10_CH4MODE
+	int "TIM10 Channel 4 Mode"
+	default 0
+	range 0 5
+	---help---
+		Specifies the channel mode.
+
+config STM32F7_TIM10_CH4OUT
+	bool "TIM10 Channel 4 Output"
+	default n
+	---help---
+		Enables channel 4 output.
+
+endif # STM32F7_TIM10_CHANNEL4
+
+endif # STM32F7_PWM_MULTICHAN
+
+if !STM32F7_PWM_MULTICHAN
+
+config STM32F7_TIM10_CHANNEL
+	int "TIM10 PWM Output Channel"
+	default 1
+	range 1 4
+	---help---
+		If TIM10 is enabled for PWM usage, you also need specifies the timer output
+		channel {1,..,4}
+
+config STM32F7_TIM10_CHMODE
+	int "TIM10 Channel Mode"
+	default 0
+	range 0 5
+	---help---
+		Specifies the channel mode.
+
+endif # !STM32F7_PWM_MULTICHAN
+
+endif # STM32F7_TIM10_PWM
+
+config STM32F7_TIM11_PWM
+	bool "TIM11 PWM"
+	default n
+	depends on STM32F7_TIM11
+	select ARCH_HAVE_PWM_PULSECOUNT
+	---help---
+		Reserve timer 11 for use by PWM
+
+		Timer devices may be used for different purposes.  One special purpose is
+		to generate modulated outputs for such things as motor control.  If STM32F7_TIM11
+		is defined then THIS following may also be defined to indicate that
+		the timer is intended to be used for pulsed output modulation.
+
+if STM32F7_TIM11_PWM
+
+if STM32F7_PWM_MULTICHAN
+
+config STM32F7_TIM11_CHANNEL1
+	bool "TIM11 Channel 1"
+	default n
+	---help---
+		Enables channel 1.
+
+if STM32F7_TIM11_CHANNEL1
+
+config STM32F7_TIM11_CH1MODE
+	int "TIM11 Channel 1 Mode"
+	default 0
+	range 0 5
+	---help---
+		Specifies the channel mode.
+
+config STM32F7_TIM11_CH1OUT
+	bool "TIM11 Channel 1 Output"
+	default n
+	---help---
+		Enables channel 1 output.
+
+endif # STM32F7_TIM11_CHANNEL1
+
+config STM32F7_TIM11_CHANNEL2
+	bool "TIM11 Channel 2"
+	default n
+	---help---
+		Enables channel 2.
+
+if STM32F7_TIM11_CHANNEL2
+
+config STM32F7_TIM11_CH2MODE
+	int "TIM11 Channel 2 Mode"
+	default 0
+	range 0 5
+	---help---
+		Specifies the channel mode.
+
+config STM32F7_TIM11_CH2OUT
+	bool "TIM11 Channel 2 Output"
+	default n
+	---help---
+		Enables channel 2 output.
+
+endif # STM32F7_TIM11_CHANNEL2
+
+config STM32F7_TIM11_CHANNEL3
+	bool "TIM11 Channel 3"
+	default n
+	---help---
+		Enables channel 3.
+
+if STM32F7_TIM11_CHANNEL3
+
+config STM32F7_TIM11_CH3MODE
+	int "TIM11 Channel 3 Mode"
+	default 0
+	range 0 5
+	---help---
+		Specifies the channel mode.
+
+config STM32F7_TIM11_CH3OUT
+	bool "TIM11 Channel 3 Output"
+	default n
+	---help---
+		Enables channel 3 output.
+
+endif # STM32F7_TIM11_CHANNEL3
+
+config STM32F7_TIM11_CHANNEL4
+	bool "TIM11 Channel 4"
+	default n
+	---help---
+		Enables channel 4.
+
+if STM32F7_TIM11_CHANNEL4
+
+config STM32F7_TIM11_CH4MODE
+	int "TIM11 Channel 4 Mode"
+	default 0
+	range 0 5
+	---help---
+		Specifies the channel mode.
+
+config STM32F7_TIM11_CH4OUT
+	bool "TIM11 Channel 4 Output"
+	default n
+	---help---
+		Enables channel 4 output.
+
+endif # STM32F7_TIM11_CHANNEL4
+
+endif # STM32F7_PWM_MULTICHAN
+
+if !STM32F7_PWM_MULTICHAN
+
+config STM32F7_TIM11_CHANNEL
+	int "TIM11 PWM Output Channel"
+	default 1
+	range 1 4
+	---help---
+		If TIM11 is enabled for PWM usage, you also need specifies the timer output
+		channel {1,..,4}
+
+config STM32F7_TIM11_CHMODE
+	int "TIM11 Channel Mode"
+	default 0
+	range 0 5
+	---help---
+		Specifies the channel mode.
+
+endif # !STM32F7_PWM_MULTICHAN
+
+endif # STM32F7_TIM11_PWM
+
+config STM32F7_TIM12_PWM
+	bool "TIM12 PWM"
+	default n
+	depends on STM32F7_TIM12
+	select ARCH_HAVE_PWM_PULSECOUNT
+	---help---
+		Reserve timer 12 for use by PWM
+
+		Timer devices may be used for different purposes.  One special purpose is
+		to generate modulated outputs for such things as motor control.  If STM32F7_TIM12
+		is defined then THIS following may also be defined to indicate that
+		the timer is intended to be used for pulsed output modulation.
+
+if STM32F7_TIM12_PWM
+
+if STM32F7_PWM_MULTICHAN
+
+config STM32F7_TIM12_CHANNEL1
+	bool "TIM12 Channel 1"
+	default n
+	---help---
+		Enables channel 1.
+
+if STM32F7_TIM12_CHANNEL1
+
+config STM32F7_TIM12_CH1MODE
+	int "TIM12 Channel 1 Mode"
+	default 0
+	range 0 5
+	---help---
+		Specifies the channel mode.
+
+config STM32F7_TIM12_CH1OUT
+	bool "TIM12 Channel 1 Output"
+	default n
+	---help---
+		Enables channel 1 output.
+
+endif # STM32F7_TIM12_CHANNEL1
+
+config STM32F7_TIM12_CHANNEL2
+	bool "TIM12 Channel 2"
+	default n
+	---help---
+		Enables channel 2.
+
+if STM32F7_TIM12_CHANNEL2
+
+config STM32F7_TIM12_CH2MODE
+	int "TIM12 Channel 2 Mode"
+	default 0
+	range 0 5
+	---help---
+		Specifies the channel mode.
+
+config STM32F7_TIM12_CH2OUT
+	bool "TIM12 Channel 2 Output"
+	default n
+	---help---
+		Enables channel 2 output.
+
+endif # STM32F7_TIM12_CHANNEL2
+
+config STM32F7_TIM12_CHANNEL3
+	bool "TIM12 Channel 3"
+	default n
+	---help---
+		Enables channel 3.
+
+if STM32F7_TIM12_CHANNEL3
+
+config STM32F7_TIM12_CH3MODE
+	int "TIM12 Channel 3 Mode"
+	default 0
+	range 0 5
+	---help---
+		Specifies the channel mode.
+
+config STM32F7_TIM12_CH3OUT
+	bool "TIM12 Channel 3 Output"
+	default n
+	---help---
+		Enables channel 3 output.
+
+endif # STM32F7_TIM12_CHANNEL3
+
+config STM32F7_TIM12_CHANNEL4
+	bool "TIM12 Channel 4"
+	default n
+	---help---
+		Enables channel 4.
+
+if STM32F7_TIM12_CHANNEL4
+
+config STM32F7_TIM12_CH4MODE
+	int "TIM12 Channel 4 Mode"
+	default 0
+	range 0 5
+	---help---
+		Specifies the channel mode.
+
+config STM32F7_TIM12_CH4OUT
+	bool "TIM12 Channel 4 Output"
+	default n
+	---help---
+		Enables channel 4 output.
+
+endif # STM32F7_TIM12_CHANNEL4
+
+endif # STM32F7_PWM_MULTICHAN
+
+if !STM32F7_PWM_MULTICHAN
+
+config STM32F7_TIM12_CHANNEL
+	int "TIM12 PWM Output Channel"
+	default 1
+	range 1 4
+	---help---
+		If TIM12 is enabled for PWM usage, you also need specifies the timer output
+		channel {1,..,4}
+
+config STM32F7_TIM12_CHMODE
+	int "TIM12 Channel Mode"
+	default 0
+	range 0 5
+	---help---
+		Specifies the channel mode.
+
+endif # !STM32F7_PWM_MULTICHAN
+
+endif # STM32F7_TIM12_PWM
+
+config STM32F7_TIM13_PWM
+	bool "TIM13 PWM"
+	default n
+	depends on STM32F7_TIM13
+	select ARCH_HAVE_PWM_PULSECOUNT
+	---help---
+		Reserve timer 13 for use by PWM
+
+		Timer devices may be used for different purposes.  One special purpose is
+		to generate modulated outputs for such things as motor control.  If STM32F7_TIM13
+		is defined then THIS following may also be defined to indicate that
+		the timer is intended to be used for pulsed output modulation.
+
+if STM32F7_TIM13_PWM
+
+if STM32F7_PWM_MULTICHAN
+
+config STM32F7_TIM13_CHANNEL1
+	bool "TIM13 Channel 1"
+	default n
+	---help---
+		Enables channel 1.
+
+if STM32F7_TIM13_CHANNEL1
+
+config STM32F7_TIM13_CH1MODE
+	int "TIM13 Channel 1 Mode"
+	default 0
+	range 0 5
+	---help---
+		Specifies the channel mode.
+
+config STM32F7_TIM13_CH1OUT
+	bool "TIM13 Channel 1 Output"
+	default n
+	---help---
+		Enables channel 1 output.
+
+endif # STM32F7_TIM13_CHANNEL1
+
+config STM32F7_TIM13_CHANNEL2
+	bool "TIM13 Channel 2"
+	default n
+	---help---
+		Enables channel 2.
+
+if STM32F7_TIM13_CHANNEL2
+
+config STM32F7_TIM13_CH2MODE
+	int "TIM13 Channel 2 Mode"
+	default 0
+	range 0 5
+	---help---
+		Specifies the channel mode.
+
+config STM32F7_TIM13_CH2OUT
+	bool "TIM13 Channel 2 Output"
+	default n
+	---help---
+		Enables channel 2 output.
+
+endif # STM32F7_TIM13_CHANNEL2
+
+config STM32F7_TIM13_CHANNEL3
+	bool "TIM13 Channel 3"
+	default n
+	---help---
+		Enables channel 3.
+
+if STM32F7_TIM13_CHANNEL3
+
+config STM32F7_TIM13_CH3MODE
+	int "TIM13 Channel 3 Mode"
+	default 0
+	range 0 5
+	---help---
+		Specifies the channel mode.
+
+config STM32F7_TIM13_CH3OUT
+	bool "TIM13 Channel 3 Output"
+	default n
+	---help---
+		Enables channel 3 output.
+
+endif # STM32F7_TIM13_CHANNEL3
+
+config STM32F7_TIM13_CHANNEL4
+	bool "TIM13 Channel 4"
+	default n
+	---help---
+		Enables channel 4.
+
+if STM32F7_TIM13_CHANNEL4
+
+config STM32F7_TIM13_CH4MODE
+	int "TIM13 Channel 4 Mode"
+	default 0
+	range 0 5
+	---help---
+		Specifies the channel mode.
+
+config STM32F7_TIM13_CH4OUT
+	bool "TIM13 Channel 4 Output"
+	default n
+	---help---
+		Enables channel 4 output.
+
+endif # STM32F7_TIM13_CHANNEL4
+
+endif # STM32F7_PWM_MULTICHAN
+
+if !STM32F7_PWM_MULTICHAN
+
+config STM32F7_TIM13_CHANNEL
+	int "TIM13 PWM Output Channel"
+	default 1
+	range 1 4
+	---help---
+		If TIM13 is enabled for PWM usage, you also need specifies the timer output
+		channel {1,..,4}
+
+config STM32F7_TIM13_CHMODE
+	int "TIM13 Channel Mode"
+	default 0
+	range 0 5
+	---help---
+		Specifies the channel mode.
+
+endif # !STM32F7_PWM_MULTICHAN
+
+endif # STM32F7_TIM13_PWM
+
+config STM32F7_TIM14_PWM
+	bool "TIM14 PWM"
+	default n
+	depends on STM32F7_TIM14
+	select ARCH_HAVE_PWM_PULSECOUNT
+	---help---
+		Reserve timer 14 for use by PWM
+
+		Timer devices may be used for different purposes.  One special purpose is
+		to generate modulated outputs for such things as motor control.  If STM32F7_TIM14
+		is defined then THIS following may also be defined to indicate that
+		the timer is intended to be used for pulsed output modulation.
+
+if STM32F7_TIM14_PWM
+
+if STM32F7_PWM_MULTICHAN
+
+config STM32F7_TIM14_CHANNEL1
+	bool "TIM14 Channel 1"
+	default n
+	---help---
+		Enables channel 1.
+
+if STM32F7_TIM14_CHANNEL1
+
+config STM32F7_TIM14_CH1MODE
+	int "TIM14 Channel 1 Mode"
+	default 0
+	range 0 5
+	---help---
+		Specifies the channel mode.
+
+config STM32F7_TIM14_CH1OUT
+	bool "TIM14 Channel 1 Output"
+	default n
+	---help---
+		Enables channel 1 output.
+
+endif # STM32F7_TIM14_CHANNEL1
+
+config STM32F7_TIM14_CHANNEL2
+	bool "TIM14 Channel 2"
+	default n
+	---help---
+		Enables channel 2.
+
+if STM32F7_TIM14_CHANNEL2
+
+config STM32F7_TIM14_CH2MODE
+	int "TIM14 Channel 2 Mode"
+	default 0
+	range 0 5
+	---help---
+		Specifies the channel mode.
+
+config STM32F7_TIM14_CH2OUT
+	bool "TIM14 Channel 2 Output"
+	default n
+	---help---
+		Enables channel 2 output.
+
+endif # STM32F7_TIM14_CHANNEL2
+
+config STM32F7_TIM14_CHANNEL3
+	bool "TIM14 Channel 3"
+	default n
+	---help---
+		Enables channel 3.
+
+if STM32F7_TIM14_CHANNEL3
+
+config STM32F7_TIM14_CH3MODE
+	int "TIM14 Channel 3 Mode"
+	default 0
+	range 0 5
+	---help---
+		Specifies the channel mode.
+
+config STM32F7_TIM14_CH3OUT
+	bool "TIM14 Channel 3 Output"
+	default n
+	---help---
+		Enables channel 3 output.
+
+endif # STM32F7_TIM14_CHANNEL3
+
+config STM32F7_TIM14_CHANNEL4
+	bool "TIM14 Channel 4"
+	default n
+	---help---
+		Enables channel 4.
+
+if STM32F7_TIM14_CHANNEL4
+
+config STM32F7_TIM14_CH4MODE
+	int "TIM14 Channel 4 Mode"
+	default 0
+	range 0 5
+	---help---
+		Specifies the channel mode.
+
+config STM32F7_TIM14_CH4OUT
+	bool "TIM14 Channel 4 Output"
+	default n
+	---help---
+		Enables channel 4 output.
+
+endif # STM32F7_TIM14_CHANNEL4
+
+endif # STM32F7_PWM_MULTICHAN
+
+if !STM32F7_PWM_MULTICHAN
+
+config STM32F7_TIM14_CHANNEL
+	int "TIM14 PWM Output Channel"
+	default 1
+	range 1 4
+	---help---
+		If TIM14 is enabled for PWM usage, you also need specifies the timer output
+		channel {1,..,4}
+
+config STM32F7_TIM14_CHMODE
+	int "TIM14 Channel Mode"
+	default 0
+	range 0 5
+	---help---
+		Specifies the channel mode.
+
+endif # !STM32F7_PWM_MULTICHAN
+
+endif # STM32F7_TIM14_PWM
+
+config STM32F7_TIM15_PWM
+	bool "TIM15 PWM"
+	default n
+	depends on STM32F7_TIM15
+	---help---
+		Reserve timer 15 for use by PWM
+
+		Timer devices may be used for different purposes.  One special purpose is
+		to generate modulated outputs for such things as motor control.  If STM32F7_TIM15
+		is defined then THIS following may also be defined to indicate that
+		the timer is intended to be used for pulsed output modulation.
+
+if STM32F7_TIM15_PWM
+
+if STM32F7_PWM_MULTICHAN
+
+config STM32F7_TIM15_CHANNEL1
+	bool "TIM15 Channel 1"
+	default n
+	---help---
+		Enables channel 1.
+
+if STM32F7_TIM15_CHANNEL1
+
+config STM32F7_TIM15_CH1MODE
+	int "TIM15 Channel 1 Mode"
+	default 0
+	range 0 3 if STM32F7_STM32F30XX
+	range 0 1 if !STM32F7_STM32F30XX
+	---help---
+		Specifies the channel mode.
+
+config STM32F7_TIM15_CH1OUT
+	bool "TIM15 Channel 1 Output"
+	default n
+	---help---
+		Enables channel 1 output.
+
+endif # STM32F7_TIM15_CHANNEL1
+
+config STM32F7_TIM15_CHANNEL2
+	bool "TIM15 Channel 2"
+	default n
+	---help---
+		Enables channel 2.
+
+if STM32F7_TIM15_CHANNEL2
+
+config STM32F7_TIM15_CH2MODE
+	int "TIM15 Channel 2 Mode"
+	default 0
+	range 0 3 if STM32F7_STM32F30XX
+	range 0 1 if !STM32F7_STM32F30XX
+	---help---
+		Specifies the channel mode.
+
+config STM32F7_TIM15_CH2OUT
+	bool "TIM15 Channel 2 Output"
+	default n
+	---help---
+		Enables channel 2 output.
+
+endif # STM32F7_TIM15_CHANNEL2
+
+endif # STM32F7_PWM_MULTICHAN
+
+if !STM32F7_PWM_MULTICHAN
+
+config STM32F7_TIM15_CHANNEL
+	int "TIM15 PWM Output Channel"
+	default 1
+	range 1 2
+	---help---
+		If TIM15 is enabled for PWM usage, you also need specifies the timer output
+		channel {1,2}
+
+config STM32F7_TIM15_CHMODE
+	int "TIM15 Channel Mode"
+	default 0
+	range 0 3 if STM32F7_STM32F30XX
+	range 0 1 if !STM32F7_STM32F30XX
+	---help---
+		Specifies the channel mode.
+
+endif # !STM32F7_PWM_MULTICHAN
+
+endif # STM32F7_TIM15_PWM
+
+config STM32F7_TIM16_PWM
+	bool "TIM16 PWM"
+	default n
+	depends on STM32F7_TIM16
+	---help---
+		Reserve timer 16 for use by PWM
+
+		Timer devices may be used for different purposes.  One special purpose is
+		to generate modulated outputs for such things as motor control.  If STM32F7_TIM16
+		is defined then THIS following may also be defined to indicate that
+		the timer is intended to be used for pulsed output modulation.
+
+if STM32F7_TIM16_PWM
+
+if STM32F7_PWM_MULTICHAN
+
+config STM32F7_TIM16_CHANNEL1
+	bool "TIM16 Channel 1"
+	default n
+	---help---
+		Enables channel 1.
+
+if STM32F7_TIM16_CHANNEL1
+
+config STM32F7_TIM16_CH1MODE
+	int "TIM16 Channel 1 Mode"
+	default 0
+	range 0 1
+	---help---
+		Specifies the channel mode.
+
+config STM32F7_TIM16_CH1OUT
+	bool "TIM16 Channel 1 Output"
+	default n
+	---help---
+		Enables channel 1 output.
+
+endif # STM32F7_TIM16_CHANNEL1
+
+endif # STM32F7_PWM_MULTICHAN
+
+if !STM32F7_PWM_MULTICHAN
+
+config STM32F7_TIM16_CHANNEL
+	int "TIM16 PWM Output Channel"
+	default 1
+	range 1 1
+	---help---
+		If TIM16 is enabled for PWM usage, you also need specifies the timer output
+		channel {1}
+
+config STM32F7_TIM16_CHMODE
+	int "TIM16 Channel Mode"
+	default 0
+	range 0 1
+	---help---
+		Specifies the channel mode.
+
+endif # !STM32F7_PWM_MULTICHAN
+
+endif # STM32F7_TIM16_PWM
+
+config STM32F7_TIM17_PWM
+	bool "TIM17 PWM"
+	default n
+	depends on STM32F7_TIM17
+	---help---
+		Reserve timer 17 for use by PWM
+
+		Timer devices may be used for different purposes.  One special purpose is
+		to generate modulated outputs for such things as motor control.  If STM32F7_TIM17
+		is defined then THIS following may also be defined to indicate that
+		the timer is intended to be used for pulsed output modulation.
+
+if STM32F7_TIM17_PWM
+
+if STM32F7_PWM_MULTICHAN
+
+config STM32F7_TIM17_CHANNEL1
+	bool "TIM17 Channel 1"
+	default n
+	---help---
+		Enables channel 1.
+
+if STM32F7_TIM17_CHANNEL1
+
+config STM32F7_TIM17_CH1MODE
+	int "TIM17 Channel 1 Mode"
+	default 0
+	range 0 1
+	---help---
+		Specifies the channel mode.
+
+config STM32F7_TIM17_CH1OUT
+	bool "TIM17 Channel 1 Output"
+	default n
+	---help---
+		Enables channel 1 output.
+
+endif # STM32F7_TIM17_CHANNEL1
+
+endif # STM32F7_PWM_MULTICHAN
+
+if !STM32F7_PWM_MULTICHAN
+
+config STM32F7_TIM17_CHANNEL
+	int "TIM17 PWM Output Channel"
+	default 1
+	range 1 1
+	---help---
+		If TIM17 is enabled for PWM usage, you also need specifies the timer output
+		channel {1}
+
+config STM32F7_TIM17_CHMODE
+	int "TIM17 Channel Mode"
+	default 0
+	range 0 1
+	---help---
+		Specifies the channel mode.
+
+endif # !STM32F7_PWM_MULTICHAN
+
+endif # STM32F7_TIM17_PWM
+
+config STM32F7_PWM_MULTICHAN
+	bool "PWM Multiple Output Channels"
+	default n
+	depends on STM32F7_TIM1_PWM || STM32F7_TIM2_PWM || STM32F7_TIM3_PWM || STM32F7_TIM4_PWM || STM32F7_TIM5_PWM || STM32F7_TIM8_PWM || STM32F7_TIM9_PWM || STM32F7_TIM10_PWM || STM32F7_TIM11_PWM || STM32F7_TIM12_PWM || STM32F7_TIM13_PWM || STM32F7_TIM14_PWM || STM32F7_TIM15_PWM || STM32F7_TIM16_PWM || STM32F7_TIM17_PWM
+	select ARCH_HAVE_PWM_MULTICHAN
+	---help---
+		Specifies that the PWM driver supports multiple output
+		channels per timer.
+
+config STM32F7_TIM1_ADC
+	bool "TIM1 ADC"
+	default n
+	depends on STM32F7_TIM1 && STM32F7_ADC
+	---help---
+		Reserve timer 1 for use by ADC
+
+		Timer devices may be used for different purposes.  If STM32F7_TIM1 is
+		defined then the following may also be defined to indicate that the
+		timer is intended to be used for ADC conversion. Note that ADC usage
+		requires two definition:  Not only do you have to assign the timer
+		for used by the ADC, but then you also have to configure which ADC
+		channel it is assigned to.
+
+choice
+	prompt "Select TIM1 ADC channel"
+	default STM32F7_TIM1_ADC1
+	depends on STM32F7_TIM1_ADC
+
+config STM32F7_TIM1_ADC1
+	bool "TIM1 ADC channel 1"
+	depends on STM32F7_ADC1
+	select HAVE_ADC1_TIMER
+	---help---
+		Reserve TIM1 to trigger ADC1
+
+config STM32F7_TIM1_ADC2
+	bool "TIM1 ADC channel 2"
+	depends on STM32F7_ADC2
+	select HAVE_ADC2_TIMER
+	---help---
+		Reserve TIM1 to trigger ADC2
+
+config STM32F7_TIM1_ADC3
+	bool "TIM1 ADC channel 3"
+	depends on STM32F7_ADC3
+	select HAVE_ADC3_TIMER
+	---help---
+		Reserve TIM1 to trigger ADC3
+
+endchoice
+
+config STM32F7_TIM2_ADC
+	bool "TIM2 ADC"
+	default n
+	depends on STM32F7_TIM2 && STM32F7_ADC
+	---help---
+		Reserve timer 1 for use by ADC
+
+		Timer devices may be used for different purposes.  If STM32F7_TIM2 is
+		defined then the following may also be defined to indicate that the
+		timer is intended to be used for ADC conversion. Note that ADC usage
+		requires two definition:  Not only do you have to assign the timer
+		for used by the ADC, but then you also have to configure which ADC
+		channel it is assigned to.
+
+choice
+	prompt "Select TIM2 ADC channel"
+	default STM32F7_TIM2_ADC1
+	depends on STM32F7_TIM2_ADC
+
+config STM32F7_TIM2_ADC1
+	bool "TIM2 ADC channel 1"
+	depends on STM32F7_ADC1
+	select HAVE_ADC1_TIMER
+	---help---
+		Reserve TIM2 to trigger ADC1
+
+config STM32F7_TIM2_ADC2
+	bool "TIM2 ADC channel 2"
+	depends on STM32F7_ADC2
+	select HAVE_ADC2_TIMER
+	---help---
+		Reserve TIM2 to trigger ADC2
+
+config STM32F7_TIM2_ADC3
+	bool "TIM2 ADC channel 3"
+	depends on STM32F7_ADC3
+	select HAVE_ADC3_TIMER
+	---help---
+		Reserve TIM2 to trigger ADC3
+
+endchoice
+
+config STM32F7_TIM3_ADC
+	bool "TIM3 ADC"
+	default n
+	depends on STM32F7_TIM3 && STM32F7_ADC
+	---help---
+		Reserve timer 1 for use by ADC
+
+		Timer devices may be used for different purposes.  If STM32F7_TIM3 is
+		defined then the following may also be defined to indicate that the
+		timer is intended to be used for ADC conversion. Note that ADC usage
+		requires two definition:  Not only do you have to assign the timer
+		for used by the ADC, but then you also have to configure which ADC
+		channel it is assigned to.
+
+choice
+	prompt "Select TIM3 ADC channel"
+	default STM32F7_TIM3_ADC1
+	depends on STM32F7_TIM3_ADC
+
+config STM32F7_TIM3_ADC1
+	bool "TIM3 ADC channel 1"
+	depends on STM32F7_ADC1
+	select HAVE_ADC1_TIMER
+	---help---
+		Reserve TIM3 to trigger ADC1
+
+config STM32F7_TIM3_ADC2
+	bool "TIM3 ADC channel 2"
+	depends on STM32F7_ADC2
+	select HAVE_ADC2_TIMER
+	---help---
+		Reserve TIM3 to trigger ADC2
+
+config STM32F7_TIM3_ADC3
+	bool "TIM3 ADC channel 3"
+	depends on STM32F7_ADC3
+	select HAVE_ADC3_TIMER
+	---help---
+		Reserve TIM3 to trigger ADC3
+
+endchoice
+
+config STM32F7_TIM4_ADC
+	bool "TIM4 ADC"
+	default n
+	depends on STM32F7_TIM4 && STM32F7_ADC
+	---help---
+		Reserve timer 1 for use by ADC
+
+		Timer devices may be used for different purposes.  If STM32F7_TIM4 is
+		defined then the following may also be defined to indicate that the
+		timer is intended to be used for ADC conversion. Note that ADC usage
+		requires two definition:  Not only do you have to assign the timer
+		for used by the ADC, but then you also have to configure which ADC
+		channel it is assigned to.
+
+choice
+	prompt "Select TIM4 ADC channel"
+	default STM32F7_TIM4_ADC1
+	depends on STM32F7_TIM4_ADC
+
+config STM32F7_TIM4_ADC1
+	bool "TIM4 ADC channel 1"
+	depends on STM32F7_ADC1
+	select HAVE_ADC1_TIMER
+	---help---
+		Reserve TIM4 to trigger ADC1
+
+config STM32F7_TIM4_ADC2
+	bool "TIM4 ADC channel 2"
+	depends on STM32F7_ADC2
+	select HAVE_ADC2_TIMER
+	---help---
+		Reserve TIM4 to trigger ADC2
+
+config STM32F7_TIM4_ADC3
+	bool "TIM4 ADC channel 3"
+	depends on STM32F7_ADC3
+	select HAVE_ADC3_TIMER
+	---help---
+		Reserve TIM4 to trigger ADC3
+
+endchoice
+
+config STM32F7_TIM5_ADC
+	bool "TIM5 ADC"
+	default n
+	depends on STM32F7_TIM5 && STM32F7_ADC
+	---help---
+		Reserve timer 1 for use by ADC
+
+		Timer devices may be used for different purposes.  If STM32F7_TIM5 is
+		defined then the following may also be defined to indicate that the
+		timer is intended to be used for ADC conversion. Note that ADC usage
+		requires two definition:  Not only do you have to assign the timer
+		for used by the ADC, but then you also have to configure which ADC
+		channel it is assigned to.
+
+choice
+	prompt "Select TIM5 ADC channel"
+	default STM32F7_TIM5_ADC1
+	depends on STM32F7_TIM5_ADC
+
+config STM32F7_TIM5_ADC1
+	bool "TIM5 ADC channel 1"
+	depends on STM32F7_ADC1
+	select HAVE_ADC1_TIMER
+	---help---
+		Reserve TIM5 to trigger ADC1
+
+config STM32F7_TIM5_ADC2
+	bool "TIM5 ADC channel 2"
+	depends on STM32F7_ADC2
+	select HAVE_ADC2_TIMER
+	---help---
+		Reserve TIM5 to trigger ADC2
+
+config STM32F7_TIM5_ADC3
+	bool "TIM5 ADC channel 3"
+	depends on STM32F7_ADC3
+	select HAVE_ADC3_TIMER
+	---help---
+		Reserve TIM5 to trigger ADC3
+
+endchoice
+
+config STM32F7_TIM8_ADC
+	bool "TIM8 ADC"
+	default n
+	depends on STM32F7_TIM8 && STM32F7_ADC
+	---help---
+		Reserve timer 1 for use by ADC
+
+		Timer devices may be used for different purposes.  If STM32F7_TIM8 is
+		defined then the following may also be defined to indicate that the
+		timer is intended to be used for ADC conversion. Note that ADC usage
+		requires two definition:  Not only do you have to assign the timer
+		for used by the ADC, but then you also have to configure which ADC
+		channel it is assigned to.
+
+choice
+	prompt "Select TIM8 ADC channel"
+	default STM32F7_TIM8_ADC1
+	depends on STM32F7_TIM8_ADC
+
+config STM32F7_TIM8_ADC1
+	bool "TIM8 ADC channel 1"
+	depends on STM32F7_ADC1
+	select HAVE_ADC1_TIMER
+	---help---
+		Reserve TIM8 to trigger ADC1
+
+config STM32F7_TIM8_ADC2
+	bool "TIM8 ADC channel 2"
+	depends on STM32F7_ADC2
+	select HAVE_ADC2_TIMER
+	---help---
+		Reserve TIM8 to trigger ADC2
+
+config STM32F7_TIM8_ADC3
+	bool "TIM8 ADC channel 3"
+	depends on STM32F7_ADC3
+	select HAVE_ADC3_TIMER
+	---help---
+		Reserve TIM8 to trigger ADC3
+
+endchoice
+
+config HAVE_ADC1_TIMER
+	bool
+
+config HAVE_ADC2_TIMER
+	bool
+
+config HAVE_ADC3_TIMER
+	bool
+
+config STM32F7_ADC1_SAMPLE_FREQUENCY
+	int "ADC1 Sampling Frequency"
+	default 100
+	depends on HAVE_ADC1_TIMER
+	---help---
+		ADC1 sampling frequency.  Default:  100Hz
+
+config STM32F7_ADC1_TIMTRIG
+	int "ADC1 Timer Trigger"
+	default 0
+	range 0 4
+	depends on HAVE_ADC1_TIMER
+	---help---
+		Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO
+
+config STM32F7_ADC2_SAMPLE_FREQUENCY
+	int "ADC2 Sampling Frequency"
+	default 100
+	depends on HAVE_ADC2_TIMER
+	---help---
+		ADC2 sampling frequency.  Default:  100Hz
+
+config STM32F7_ADC2_TIMTRIG
+	int "ADC2 Timer Trigger"
+	default 0
+	range 0 4
+	depends on HAVE_ADC2_TIMER
+	---help---
+		Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO
+
+config STM32F7_ADC3_SAMPLE_FREQUENCY
+	int "ADC3 Sampling Frequency"
+	default 100
+	depends on HAVE_ADC3_TIMER
+	---help---
+		ADC3 sampling frequency.  Default:  100Hz
+
+config STM32F7_ADC3_TIMTRIG
+	int "ADC3 Timer Trigger"
+	default 0
+	range 0 4
+	depends on HAVE_ADC3_TIMER
+	---help---
+		Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO
+
+config STM32F7_TIM1_DAC
+	bool "TIM1 DAC"
+	default n
+	depends on STM32F7_TIM1 && STM32F7_DAC
+	---help---
+		Reserve timer 1 for use by DAC
+
+		Timer devices may be used for different purposes.  If STM32F7_TIM1 is
+		defined then the following may also be defined to indicate that the
+		timer is intended to be used for DAC conversion. Note that DAC usage
+		requires two definition:  Not only do you have to assign the timer
+		for used by the DAC, but then you also have to configure which DAC
+		channel it is assigned to.
+
+choice
+	prompt "Select TIM1 DAC channel"
+	default STM32F7_TIM1_DAC1
+	depends on STM32F7_TIM1_DAC
+
+config STM32F7_TIM1_DAC1
+	bool "TIM1 DAC channel 1"
+	---help---
+		Reserve TIM1 to trigger DAC1
+
+config STM32F7_TIM1_DAC2
+	bool "TIM1 DAC channel 2"
+	---help---
+		Reserve TIM1 to trigger DAC2
+
+endchoice
+
+config STM32F7_TIM2_DAC
+	bool "TIM2 DAC"
+	default n
+	depends on STM32F7_TIM2 && STM32F7_DAC
+	---help---
+		Reserve timer 2 for use by DAC
+
+		Timer devices may be used for different purposes.  If STM32F7_TIM2 is
+		defined then the following may also be defined to indicate that the
+		timer is intended to be used for DAC conversion. Note that DAC usage
+		requires two definition:  Not only do you have to assign the timer
+		for used by the DAC, but then you also have to configure which DAC
+		channel it is assigned to.
+
+choice
+	prompt "Select TIM2 DAC channel"
+	default STM32F7_TIM2_DAC1
+	depends on STM32F7_TIM2_DAC
+
+config STM32F7_TIM2_DAC1
+	bool "TIM2 DAC channel 1"
+	---help---
+		Reserve TIM2 to trigger DAC1
+
+config STM32F7_TIM2_DAC2
+	bool "TIM2 DAC channel 2"
+	---help---
+		Reserve TIM2 to trigger DAC2
+
+endchoice
+
+config STM32F7_TIM3_DAC
+	bool "TIM3 DAC"
+	default n
+	depends on STM32F7_TIM3 && STM32F7_DAC
+	---help---
+		Reserve timer 3 for use by DAC
+
+		Timer devices may be used for different purposes.  If STM32F7_TIM3 is
+		defined then the following may also be defined to indicate that the
+		timer is intended to be used for DAC conversion. Note that DAC usage
+		requires two definition:  Not only do you have to assign the timer
+		for used by the DAC, but then you also have to configure which DAC
+		channel it is assigned to.
+
+choice
+	prompt "Select TIM3 DAC channel"
+	default STM32F7_TIM3_DAC1
+	depends on STM32F7_TIM3_DAC
+
+config STM32F7_TIM3_DAC1
+	bool "TIM3 DAC channel 1"
+	---help---
+		Reserve TIM3 to trigger DAC1
+
+config STM32F7_TIM3_DAC2
+	bool "TIM3 DAC channel 2"
+	---help---
+		Reserve TIM3 to trigger DAC2
+
+endchoice
+
+config STM32F7_TIM4_DAC
+	bool "TIM4 DAC"
+	default n
+	depends on STM32F7_TIM4 && STM32F7_DAC
+	---help---
+		Reserve timer 4 for use by DAC
+
+		Timer devices may be used for different purposes.  If STM32F7_TIM4 is
+		defined then the following may also be defined to indicate that the
+		timer is intended to be used for DAC conversion. Note that DAC usage
+		requires two definition:  Not only do you have to assign the timer
+		for used by the DAC, but then you also have to configure which DAC
+		channel it is assigned to.
+
+choice
+	prompt "Select TIM4 DAC channel"
+	default STM32F7_TIM4_DAC1
+	depends on STM32F7_TIM4_DAC
+
+config STM32F7_TIM4_DAC1
+	bool "TIM4 DAC channel 1"
+	---help---
+		Reserve TIM4 to trigger DAC1
+
+config STM32F7_TIM4_DAC2
+	bool "TIM4 DAC channel 2"
+	---help---
+		Reserve TIM4 to trigger DAC2
+
+endchoice
+
+config STM32F7_TIM5_DAC
+	bool "TIM5 DAC"
+	default n
+	depends on STM32F7_TIM5 && STM32F7_DAC
+	---help---
+		Reserve timer 5 for use by DAC
+
+		Timer devices may be used for different purposes.  If STM32F7_TIM5 is
+		defined then the following may also be defined to indicate that the
+		timer is intended to be used for DAC conversion. Note that DAC usage
+		requires two definition:  Not only do you have to assign the timer
+		for used by the DAC, but then you also have to configure which DAC
+		channel it is assigned to.
+
+choice
+	prompt "Select TIM5 DAC channel"
+	default STM32F7_TIM5_DAC1
+	depends on STM32F7_TIM5_DAC
+
+config STM32F7_TIM5_DAC1
+	bool "TIM5 DAC channel 1"
+	---help---
+		Reserve TIM5 to trigger DAC1
+
+config STM32F7_TIM5_DAC2
+	bool "TIM5 DAC channel 2"
+	---help---
+		Reserve TIM5 to trigger DAC2
+
+endchoice
+
+config STM32F7_TIM6_DAC
+	bool "TIM6 DAC"
+	default n
+	depends on STM32F7_TIM6 && STM32F7_DAC
+	---help---
+		Reserve timer 6 for use by DAC
+
+		Timer devices may be used for different purposes.  If STM32F7_TIM6 is
+		defined then the following may also be defined to indicate that the
+		timer is intended to be used for DAC conversion. Note that DAC usage
+		requires two definition:  Not only do you have to assign the timer
+		for used by the DAC, but then you also have to configure which DAC
+		channel it is assigned to.
+
+choice
+	prompt "Select TIM6 DAC channel"
+	default STM32F7_TIM6_DAC1
+	depends on STM32F7_TIM6_DAC
+
+config STM32F7_TIM6_DAC1
+	bool "TIM6 DAC channel 1"
+	---help---
+		Reserve TIM6 to trigger DAC1
+
+config STM32F7_TIM6_DAC2
+	bool "TIM6 DAC channel 2"
+	---help---
+		Reserve TIM6 to trigger DAC2
+
+endchoice
+
+config STM32F7_TIM7_DAC
+	bool "TIM7 DAC"
+	default n
+	depends on STM32F7_TIM7 && STM32F7_DAC
+	---help---
+		Reserve timer 7 for use by DAC
+
+		Timer devices may be used for different purposes.  If STM32F7_TIM7 is
+		defined then the following may also be defined to indicate that the
+		timer is intended to be used for DAC conversion. Note that DAC usage
+		requires two definition:  Not only do you have to assign the timer
+		for used by the DAC, but then you also have to configure which DAC
+		channel it is assigned to.
+
+choice
+	prompt "Select TIM7 DAC channel"
+	default STM32F7_TIM7_DAC1
+	depends on STM32F7_TIM7_DAC
+
+config STM32F7_TIM7_DAC1
+	bool "TIM7 DAC channel 1"
+	---help---
+		Reserve TIM7 to trigger DAC1
+
+config STM32F7_TIM7_DAC2
+	bool "TIM7 DAC channel 2"
+	---help---
+		Reserve TIM7 to trigger DAC2
+
+endchoice
+
+config STM32F7_TIM8_DAC
+	bool "TIM8 DAC"
+	default n
+	depends on STM32F7_TIM8 && STM32F7_DAC
+	---help---
+		Reserve timer 8 for use by DAC
+
+		Timer devices may be used for different purposes.  If STM32F7_TIM8 is
+		defined then the following may also be defined to indicate that the
+		timer is intended to be used for DAC conversion. Note that DAC usage
+		requires two definition:  Not only do you have to assign the timer
+		for used by the DAC, but then you also have to configure which DAC
+		channel it is assigned to.
+
+choice
+	prompt "Select TIM8 DAC channel"
+	default STM32F7_TIM8_DAC1
+	depends on STM32F7_TIM8_DAC
+
+config STM32F7_TIM8_DAC1
+	bool "TIM8 DAC channel 1"
+	---help---
+		Reserve TIM8 to trigger DAC1
+
+config STM32F7_TIM8_DAC2
+	bool "TIM8 DAC channel 2"
+	---help---
+		Reserve TIM8 to trigger DAC2
+
+endchoice
+
+config STM32F7_TIM9_DAC
+	bool "TIM9 DAC"
+	default n
+	depends on STM32F7_TIM9 && STM32F7_DAC
+	---help---
+		Reserve timer 9 for use by DAC
+
+		Timer devices may be used for different purposes.  If STM32F7_TIM9 is
+		defined then the following may also be defined to indicate that the
+		timer is intended to be used for DAC conversion. Note that DAC usage
+		requires two definition:  Not only do you have to assign the timer
+		for used by the DAC, but then you also have to configure which DAC
+		channel it is assigned to.
+
+choice
+	prompt "Select TIM9 DAC channel"
+	default STM32F7_TIM9_DAC1
+	depends on STM32F7_TIM9_DAC
+
+config STM32F7_TIM9_DAC1
+	bool "TIM9 DAC channel 1"
+	---help---
+		Reserve TIM9 to trigger DAC1
+
+config STM32F7_TIM9_DAC2
+	bool "TIM9 DAC channel 2"
+	---help---
+		Reserve TIM9 to trigger DAC2
+
+endchoice
+
+config STM32F7_TIM10_DAC
+	bool "TIM10 DAC"
+	default n
+	depends on STM32F7_TIM10 && STM32F7_DAC
+	---help---
+		Reserve timer 10 for use by DAC
+
+		Timer devices may be used for different purposes.  If STM32F7_TIM10 is
+		defined then the following may also be defined to indicate that the
+		timer is intended to be used for DAC conversion. Note that DAC usage
+		requires two definition:  Not only do you have to assign the timer
+		for used by the DAC, but then you also have to configure which DAC
+		channel it is assigned to.
+
+choice
+	prompt "Select TIM10 DAC channel"
+	default STM32F7_TIM10_DAC1
+	depends on STM32F7_TIM10_DAC
+
+config STM32F7_TIM10_DAC1
+	bool "TIM10 DAC channel 1"
+	---help---
+		Reserve TIM10 to trigger DAC1
+
+config STM32F7_TIM10_DAC2
+	bool "TIM10 DAC channel 2"
+	---help---
+		Reserve TIM10 to trigger DAC2
+
+endchoice
+
+config STM32F7_TIM11_DAC
+	bool "TIM11 DAC"
+	default n
+	depends on STM32F7_TIM11 && STM32F7_DAC
+	---help---
+		Reserve timer 11 for use by DAC
+
+		Timer devices may be used for different purposes.  If STM32F7_TIM11 is
+		defined then the following may also be defined to indicate that the
+		timer is intended to be used for DAC conversion. Note that DAC usage
+		requires two definition:  Not only do you have to assign the timer
+		for used by the DAC, but then you also have to configure which DAC
+		channel it is assigned to.
+
+choice
+	prompt "Select TIM11 DAC channel"
+	default STM32F7_TIM11_DAC1
+	depends on STM32F7_TIM11_DAC
+
+config STM32F7_TIM11_DAC1
+	bool "TIM11 DAC channel 1"
+	---help---
+		Reserve TIM11 to trigger DAC1
+
+config STM32F7_TIM11_DAC2
+	bool "TIM11 DAC channel 2"
+	---help---
+		Reserve TIM11 to trigger DAC2
+
+endchoice
+
+config STM32F7_TIM12_DAC
+	bool "TIM12 DAC"
+	default n
+	depends on STM32F7_TIM12 && STM32F7_DAC
+	---help---
+		Reserve timer 12 for use by DAC
+
+		Timer devices may be used for different purposes.  If STM32F7_TIM12 is
+		defined then the following may also be defined to indicate that the
+		timer is intended to be used for DAC conversion. Note that DAC usage
+		requires two definition:  Not only do you have to assign the timer
+		for used by the DAC, but then you also have to configure which DAC
+		channel it is assigned to.
+
+choice
+	prompt "Select TIM12 DAC channel"
+	default STM32F7_TIM12_DAC1
+	depends on STM32F7_TIM12_DAC
+
+config STM32F7_TIM12_DAC1
+	bool "TIM12 DAC channel 1"
+	---help---
+		Reserve TIM12 to trigger DAC1
+
+config STM32F7_TIM12_DAC2
+	bool "TIM12 DAC channel 2"
+	---help---
+		Reserve TIM12 to trigger DAC2
+
+endchoice
+
+config STM32F7_TIM13_DAC
+	bool "TIM13 DAC"
+	default n
+	depends on STM32F7_TIM13 && STM32F7_DAC
+	---help---
+		Reserve timer 13 for use by DAC
+
+		Timer devices may be used for different purposes.  If STM32F7_TIM13 is
+		defined then the following may also be defined to indicate that the
+		timer is intended to be used for DAC conversion. Note that DAC usage
+		requires two definition:  Not only do you have to assign the timer
+		for used by the DAC, but then you also have to configure which DAC
+		channel it is assigned to.
+
+choice
+	prompt "Select TIM13 DAC channel"
+	default STM32F7_TIM13_DAC1
+	depends on STM32F7_TIM13_DAC
+
+config STM32F7_TIM13_DAC1
+	bool "TIM13 DAC channel 1"
+	---help---
+		Reserve TIM13 to trigger DAC1
+
+config STM32F7_TIM13_DAC2
+	bool "TIM13 DAC channel 2"
+	---help---
+		Reserve TIM13 to trigger DAC2
+
+endchoice
+
+config STM32F7_TIM14_DAC
+	bool "TIM14 DAC"
+	default n
+	depends on STM32F7_TIM14 && STM32F7_DAC
+	---help---
+		Reserve timer 14 for use by DAC
+
+		Timer devices may be used for different purposes.  If STM32F7_TIM14 is
+		defined then the following may also be defined to indicate that the
+		timer is intended to be used for DAC conversion. Note that DAC usage
+		requires two definition:  Not only do you have to assign the timer
+		for used by the DAC, but then you also have to configure which DAC
+		channel it is assigned to.
+
+choice
+	prompt "Select TIM14 DAC channel"
+	default STM32F7_TIM14_DAC1
+	depends on STM32F7_TIM14_DAC
+
+config STM32F7_TIM14_DAC1
+	bool "TIM14 DAC channel 1"
+	---help---
+		Reserve TIM14 to trigger DAC1
+
+config STM32F7_TIM14_DAC2
+	bool "TIM14 DAC channel 2"
+	---help---
+		Reserve TIM14 to trigger DAC2
+
+endchoice
+
+config STM32F7_TIM1_CAP
+	bool "TIM1 Capture"
+	default n
+	depends on STM32F7_HAVE_TIM1
+	---help---
+		Reserve timer 1 for use by Capture
+
+		Timer devices may be used for different purposes.  One special purpose is
+		to capture input.
+
+config STM32F7_TIM2_CAP
+	bool "TIM2 Capture"
+	default n
+	depends on STM32F7_HAVE_TIM2
+	---help---
+		Reserve timer 2 for use by Capture
+
+		Timer devices may be used for different purposes.  One special purpose is
+		to capture input.
+
+config STM32F7_TIM3_CAP
+	bool "TIM3 Capture"
+	default n
+	depends on STM32F7_HAVE_TIM3
+	---help---
+		Reserve timer 3 for use by Capture
+
+		Timer devices may be used for different purposes.  One special purpose is
+		to capture input.
+
+config STM32F7_TIM4_CAP
+	bool "TIM4 Capture"
+	default n
+	depends on STM32F7_HAVE_TIM4
+	---help---
+		Reserve timer 4 for use by Capture
+
+		Timer devices may be used for different purposes.  One special purpose is
+		to capture input.
+
+config STM32F7_TIM5_CAP
+	bool "TIM5 Capture"
+	default n
+	depends on STM32F7_HAVE_TIM5
+	---help---
+		Reserve timer 5 for use by Capture
+
+		Timer devices may be used for different purposes.  One special purpose is
+		to capture input.
+
+config STM32F7_TIM8_CAP
+	bool "TIM8 Capture"
+	default n
+	depends on STM32F7_HAVE_TIM8
+	---help---
+		Reserve timer 8 for use by Capture
+
+		Timer devices may be used for different purposes.  One special purpose is
+		to capture input.
+
+config STM32F7_TIM9_CAP
+	bool "TIM9 Capture"
+	default n
+	depends on STM32F7_HAVE_TIM9
+	---help---
+		Reserve timer 9 for use by Capture
+
+		Timer devices may be used for different purposes.  One special purpose is
+		to capture input.
+
+config STM32F7_TIM10_CAP
+	bool "TIM10 Capture"
+	default n
+	depends on STM32F7_HAVE_TIM10
+	---help---
+		Reserve timer 10 for use by Capture
+
+		Timer devices may be used for different purposes.  One special purpose is
+		to capture input.
+
+config STM32F7_TIM11_CAP
+	bool "TIM11 Capture"
+	default n
+	depends on STM32F7_HAVE_TIM11
+	---help---
+		Reserve timer 11 for use by Capture
+
+		Timer devices may be used for different purposes.  One special purpose is
+		to capture input.
+
+config STM32F7_TIM12_CAP
+	bool "TIM12 Capture"
+	default n
+	depends on STM32F7_HAVE_TIM12
+	---help---
+		Reserve timer 12 for use by Capture
+
+		Timer devices may be used for different purposes.  One special purpose is
+		to capture input.
+
+config STM32F7_TIM13_CAP
+	bool "TIM13 Capture"
+	default n
+	depends on STM32F7_HAVE_TIM13
+	---help---
+		Reserve timer 13 for use by Capture
+
+		Timer devices may be used for different purposes.  One special purpose is
+		to capture input.
+
+config STM32F7_TIM14_CAP
+	bool "TIM14 Capture"
+	default n
+	depends on STM32F7_HAVE_TIM14
+	---help---
+		Reserve timer 14 for use by Capture
+
+		Timer devices may be used for different purposes.  One special purpose is
+		to capture input.
+
+endmenu # Timer Configuration
+
+menu "ADC Configuration"
+	depends on STM32F7_ADC
+
+config STM32F7_ADC1_DMA
+	bool "ADC1 DMA"
+	depends on STM32F7_ADC1 && STM32F7_HAVE_ADC1_DMA
+	default n
+	---help---
+		If DMA is selected, then the ADC may be configured to support
+		DMA transfer, which is necessary if multiple channels are read
+		or if very high trigger frequencies are used.
+
+config STM32F7_ADC2_DMA
+	bool "ADC2 DMA"
+	depends on STM32F7_ADC2 && STM32F7_HAVE_ADC2_DMA
+	default n
+	---help---
+		If DMA is selected, then the ADC may be configured to support
+		DMA transfer, which is necessary if multiple channels are read
+		or if very high trigger frequencies are used.
+
+config STM32F7_ADC3_DMA
+	bool "ADC3 DMA"
+	depends on STM32F7_ADC3 && STM32F7_HAVE_ADC3_DMA
+	default n
+	---help---
+		If DMA is selected, then the ADC may be configured to support
+		DMA transfer, which is necessary if multiple channels are read
+		or if very high trigger frequencies are used.
+
+endmenu # "ADC Configuration"
 
 if STM32F7_ETHMAC
 menu "Ethernet MAC configuration"
diff --git a/arch/arm/src/stm32f7/Make.defs b/arch/arm/src/stm32f7/Make.defs
index 07aa380ebde..0680d17cfbc 100644
--- a/arch/arm/src/stm32f7/Make.defs
+++ b/arch/arm/src/stm32f7/Make.defs
@@ -151,11 +151,11 @@ ifeq ($(CONFIG_STM32F7_TIM),y)
 CHIP_CSRCS += stm32_tim.c
 endif
 
-ifeq ($(CONFIG_ADC),y)
+ifeq ($(CONFIG_STM32F7_ADC),y)
 CHIP_CSRCS += stm32_adc.c
 endif
 
-ifeq ($(CONFIG_RTC),y)
+ifeq ($(CONFIG_STM32F7_RTC),y)
 ifeq ($(CONFIG_RTC_ALARM),y)
 CHIP_CSRCS += stm32_exti_alarm.c
 endif
diff --git a/arch/arm/src/stm32f7/chip/stm32_adc.h b/arch/arm/src/stm32f7/chip/stm32_adc.h
index 067301d4c76..7b0861d77ef 100644
--- a/arch/arm/src/stm32f7/chip/stm32_adc.h
+++ b/arch/arm/src/stm32f7/chip/stm32_adc.h
@@ -2,7 +2,8 @@
  * arch/arm/src/stm32f7/chip/stm32_adc.h
  *
  *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *   Authors: Gregory Nutt <gnutt@nuttx.org>
+ *            David Sidrane <david_s5@nscdg.com>
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -33,8 +34,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F_CHIP_STM32_ADC_H
-#define __ARCH_ARM_SRC_STM32F_CHIP_STM32_ADC_H
+#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32_ADC_H
+#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32_ADC_H
 
 /****************************************************************************************************
  * Included Files
@@ -44,452 +45,14 @@
 
 #include "chip.h"
 
-/****************************************************************************************************
- * Pre-processor Definitions
- ****************************************************************************************************/
+#include <nuttx/config.h>
+#include "chip.h"
 
-/* Register Offsets *********************************************************************************/
-
-#define STM32_ADC_SR_OFFSET          0x0000  /* ADC status register (32-bit) */
-#define STM32_ADC_CR1_OFFSET         0x0004  /* ADC control register 1 (32-bit) */
-#define STM32_ADC_CR2_OFFSET         0x0008  /* ADC control register 2 (32-bit) */
-#define STM32_ADC_SMPR1_OFFSET       0x000c  /* ADC sample time register 1 (32-bit) */
-#define STM32_ADC_SMPR2_OFFSET       0x0010  /* ADC sample time register 2 (32-bit) */
-#define STM32_ADC_JOFR1_OFFSET       0x0014  /* ADC injected channel data offset register 1 (32-bit) */
-#define STM32_ADC_JOFR2_OFFSET       0x0018  /* ADC injected channel data offset register 2 (32-bit) */
-#define STM32_ADC_JOFR3_OFFSET       0x001c  /* ADC injected channel data offset register 3 (32-bit) */
-#define STM32_ADC_JOFR4_OFFSET       0x0020  /* ADC injected channel data offset register 4 (32-bit) */
-#define STM32_ADC_HTR_OFFSET         0x0024  /* ADC watchdog high threshold register (32-bit) */
-#define STM32_ADC_LTR_OFFSET         0x0028  /* ADC watchdog low threshold register (32-bit) */
-#define STM32_ADC_SQR1_OFFSET        0x002c  /* ADC regular sequence register 1 (32-bit) */
-#define STM32_ADC_SQR2_OFFSET        0x0030  /* ADC regular sequence register 2 (32-bit) */
-#define STM32_ADC_SQR3_OFFSET        0x0034  /* ADC regular sequence register 3 (32-bit) */
-#define STM32_ADC_JSQR_OFFSET        0x0038  /* ADC injected sequence register (32-bit) */
-#define STM32_ADC_JDR1_OFFSET        0x003c  /* ADC injected data register 1 (32-bit) */
-#define STM32_ADC_JDR2_OFFSET        0x0040  /* ADC injected data register 1 (32-bit) */
-#define STM32_ADC_JDR3_OFFSET        0x0044  /* ADC injected data register 1 (32-bit) */
-#define STM32_ADC_JDR4_OFFSET        0x0048  /* ADC injected data register 1 (32-bit) */
-#define STM32_ADC_DR_OFFSET          0x004c  /* ADC regular data register (32-bit) */
-
-
-#define STM32_ADC_CSR_OFFSET         0x0000  /* Common status register */
-#define STM32_ADC_CCR_OFFSET         0x0004  /* Common control register */
-#define STM32_ADC_CDR_OFFSET         0x0008  /* Data register for dual and triple modes */
-
-/* Register Addresses *******************************************************************************/
-
-#if STM32F7_NADC > 0
-#  define STM32_ADC1_SR              (STM32_ADC1_BASE+STM32_ADC_SR_OFFSET)
-#  define STM32_ADC1_CR1             (STM32_ADC1_BASE+STM32_ADC_CR1_OFFSET)
-#  define STM32_ADC1_CR2             (STM32_ADC1_BASE+STM32_ADC_CR2_OFFSET)
-#  define STM32_ADC1_SMPR1           (STM32_ADC1_BASE+STM32_ADC_SMPR1_OFFSET)
-#  define STM32_ADC1_SMPR2           (STM32_ADC1_BASE+STM32_ADC_SMPR2_OFFSET)
-#  define STM32_ADC1_JOFR1           (STM32_ADC1_BASE+STM32_ADC_JOFR1_OFFSET)
-#  define STM32_ADC1_JOFR2           (STM32_ADC1_BASE+STM32_ADC_JOFR2_OFFSET)
-#  define STM32_ADC1_JOFR3           (STM32_ADC1_BASE+STM32_ADC_JOFR3_OFFSET)
-#  define STM32_ADC1_JOFR4           (STM32_ADC1_BASE+STM32_ADC_JOFR4_OFFSET)
-#  define STM32_ADC1_HTR             (STM32_ADC1_BASE+STM32_ADC_HTR_OFFSET)
-#  define STM32_ADC1_LTR             (STM32_ADC1_BASE+STM32_ADC_LTR_OFFSET)
-#  define STM32_ADC1_SQR1            (STM32_ADC1_BASE+STM32_ADC_SQR1_OFFSET)
-#  define STM32_ADC1_SQR2            (STM32_ADC1_BASE+STM32_ADC_SQR2_OFFSET)
-#  define STM32_ADC1_SQR3            (STM32_ADC1_BASE+STM32_ADC_SQR3_OFFSET)
-#  define STM32_ADC1_JSQR            (STM32_ADC1_BASE+STM32_ADC_JSQR_OFFSET)
-#  define STM32_ADC1_JDR1            (STM32_ADC1_BASE+STM32_ADC_JDR1_OFFSET)
-#  define STM32_ADC1_JDR2            (STM32_ADC1_BASE+STM32_ADC_JDR2_OFFSET)
-#  define STM32_ADC1_JDR3            (STM32_ADC1_BASE+STM32_ADC_JDR3_OFFSET)
-#  define STM32_ADC1_JDR4            (STM32_ADC1_BASE+STM32_ADC_JDR4_OFFSET)
-#  define STM32_ADC1_DR              (STM32_ADC1_BASE+STM32_ADC_DR_OFFSET)
+#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \
+    defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
+#  include "chip/stm32f74xx77xx_adc.h"
+#else
+#  error "Unsupported STM32 F7 sub family"
 #endif
 
-#if STM32F7_NADC > 1
-#  define STM32_ADC2_SR              (STM32_ADC2_BASE+STM32_ADC_SR_OFFSET)
-#  define STM32_ADC2_CR1             (STM32_ADC2_BASE+STM32_ADC_CR1_OFFSET)
-#  define STM32_ADC2_CR2             (STM32_ADC2_BASE+STM32_ADC_CR2_OFFSET)
-#  define STM32_ADC2_SMPR1           (STM32_ADC2_BASE+STM32_ADC_SMPR1_OFFSET)
-#  define STM32_ADC2_SMPR2           (STM32_ADC2_BASE+STM32_ADC_SMPR2_OFFSET)
-#  define STM32_ADC2_JOFR1           (STM32_ADC2_BASE+STM32_ADC_JOFR1_OFFSET)
-#  define STM32_ADC2_JOFR2           (STM32_ADC2_BASE+STM32_ADC_JOFR2_OFFSET)
-#  define STM32_ADC2_JOFR3           (STM32_ADC2_BASE+STM32_ADC_JOFR3_OFFSET)
-#  define STM32_ADC2_JOFR4           (STM32_ADC2_BASE+STM32_ADC_JOFR4_OFFSET)
-#  define STM32_ADC2_HTR             (STM32_ADC2_BASE+STM32_ADC_HTR_OFFSET)
-#  define STM32_ADC2_LTR             (STM32_ADC2_BASE+STM32_ADC_LTR_OFFSET)
-#  define STM32_ADC2_SQR1            (STM32_ADC2_BASE+STM32_ADC_SQR1_OFFSET)
-#  define STM32_ADC2_SQR2            (STM32_ADC2_BASE+STM32_ADC_SQR2_OFFSET)
-#  define STM32_ADC2_SQR3            (STM32_ADC2_BASE+STM32_ADC_SQR3_OFFSET)
-#  define STM32_ADC2_JSQR            (STM32_ADC2_BASE+STM32_ADC_JSQR_OFFSET)
-#  define STM32_ADC2_JDR1            (STM32_ADC2_BASE+STM32_ADC_JDR1_OFFSET)
-#  define STM32_ADC2_JDR2            (STM32_ADC2_BASE+STM32_ADC_JDR2_OFFSET)
-#  define STM32_ADC2_JDR3            (STM32_ADC2_BASE+STM32_ADC_JDR3_OFFSET)
-#  define STM32_ADC2_JDR4            (STM32_ADC2_BASE+STM32_ADC_JDR4_OFFSET)
-#  define STM32_ADC2_DR              (STM32_ADC2_BASE+STM32_ADC_DR_OFFSET)
-#endif
-
-#if STM32F7_NADC > 2
-#  define STM32_ADC3_SR              (STM32_ADC3_BASE+STM32_ADC_SR_OFFSET)
-#  define STM32_ADC3_CR1             (STM32_ADC3_BASE+STM32_ADC_CR1_OFFSET)
-#  define STM32_ADC3_CR2             (STM32_ADC3_BASE+STM32_ADC_CR2_OFFSET)
-#  define STM32_ADC3_SMPR1           (STM32_ADC3_BASE+STM32_ADC_SMPR1_OFFSET)
-#  define STM32_ADC3_SMPR2           (STM32_ADC3_BASE+STM32_ADC_SMPR2_OFFSET)
-#  define STM32_ADC3_JOFR1           (STM32_ADC3_BASE+STM32_ADC_JOFR1_OFFSET)
-#  define STM32_ADC3_JOFR2           (STM32_ADC3_BASE+STM32_ADC_JOFR2_OFFSET)
-#  define STM32_ADC3_JOFR3           (STM32_ADC3_BASE+STM32_ADC_JOFR3_OFFSET)
-#  define STM32_ADC3_JOFR4           (STM32_ADC3_BASE+STM32_ADC_JOFR4_OFFSET)
-#  define STM32_ADC3_HTR             (STM32_ADC3_BASE+STM32_ADC_HTR_OFFSET)
-#  define STM32_ADC3_LTR             (STM32_ADC3_BASE+STM32_ADC_LTR_OFFSET)
-#  define STM32_ADC3_SQR1            (STM32_ADC3_BASE+STM32_ADC_SQR1_OFFSET)
-#  define STM32_ADC3_SQR2            (STM32_ADC3_BASE+STM32_ADC_SQR2_OFFSET)
-#  define STM32_ADC3_SQR3            (STM32_ADC3_BASE+STM32_ADC_SQR3_OFFSET)
-#  define STM32_ADC3_JSQR            (STM32_ADC3_BASE+STM32_ADC_JSQR_OFFSET)
-#  define STM32_ADC3_JDR1            (STM32_ADC3_BASE+STM32_ADC_JDR1_OFFSET)
-#  define STM32_ADC3_JDR2            (STM32_ADC3_BASE+STM32_ADC_JDR2_OFFSET)
-#  define STM32_ADC3_JDR3            (STM32_ADC3_BASE+STM32_ADC_JDR3_OFFSET)
-#  define STM32_ADC3_JDR4            (STM32_ADC3_BASE+STM32_ADC_JDR4_OFFSET)
-#  define STM32_ADC3_DR              (STM32_ADC3_BASE+STM32_ADC_DR_OFFSET)
-#endif
-
-#define STM32_ADC_CSR                (STM32_ADCCMN_BASE+STM32_ADC_CSR_OFFSET)
-#define STM32_ADC_CCR                (STM32_ADCCMN_BASE+STM32_ADC_CCR_OFFSET)
-#define STM32_ADC_CDR                (STM32_ADCCMN_BASE+STM32_ADC_CDR_OFFSET)
-
-/* Register Bitfield Definitions ********************************************************************/
-
-/* ADC status register */
-
-#define ADC_SR_AWD                   (1 << 0)  /* Bit 0 : Analog watchdog flag */
-#define ADC_SR_EOC                   (1 << 1)  /* Bit 1 : End of conversion */
-#define ADC_SR_JEOC                  (1 << 2)  /* Bit 2 : Injected channel end of conversion */
-#define ADC_SR_JSTRT                 (1 << 3)  /* Bit 3 : Injected channel Start flag */
-#define ADC_SR_STRT                  (1 << 4)  /* Bit 4 : Regular channel Start flag */
-#define ADC_SR_OVR                   (1 << 5)  /* Bit 5 : Overrun */
-
-/* ADC control register 1 */
-
-#define ADC_CR1_AWDCH_SHIFT          (0)       /* Bits 4-0: Analog watchdog channel select bits */
-#define ADC_CR1_AWDCH_MASK           (0x1f << ADC_CR1_AWDCH_SHIFT)
-
-#define ADC_CR1_EOCIE                (1 << 5)  /* Bit 5: Interrupt enable for EOC */
-#define ADC_CR1_AWDIE                (1 << 6)  /* Bit 6: Analog Watchdog interrupt enable */
-#define ADC_CR1_JEOCIE               (1 << 7)  /* Bit 7: Interrupt enable for injected channels */
-#define ADC_CR1_SCAN                 (1 << 8)  /* Bit 8: Scan mode */
-#define ADC_CR1_AWDSGL               (1 << 9)  /* Bit 9: Enable the watchdog on a single channel in scan mode */
-#define ADC_CR1_JAUTO                (1 << 10) /* Bit 10: Automatic Injected Group conversion */
-#define ADC_CR1_DISCEN               (1 << 11) /* Bit 11: Discontinuous mode on regular channels */
-#define ADC_CR1_JDISCEN              (1 << 12) /* Bit 12: Discontinuous mode on injected channels */
-
-#define ADC_CR1_DISCNUM_SHIFT        (13)      /* Bits 15-13: Discontinuous mode channel count */
-#define ADC_CR1_DISCNUM_MASK         (0x07 << ADC_CR1_DISCNUM_SHIFT)
-
-
-#define ADC_CR1_JAWDEN               (1 << 22) /* Bit 22: Analog watchdog enable on injected channels */
-#define ADC_CR1_AWDEN                (1 << 23) /* Bit 23: Analog watchdog enable on regular channels */
-
-#define ADC_CR1_RES_SHIFT            (24)      /* Bits 24-25: Resolution */
-#define ADC_CR1_RES_MASK             (3 << ADC_CR1_RES_SHIFT)
-#define ADC_CR1_RES_12BIT            (0 << ADC_CR1_RES_SHIFT) /* 15 ADCCLK cycles. For STM32L15XX: 12 ADCCLK cycles */
-#define ADC_CR1_RES_10BIT            (1 << ADC_CR1_RES_SHIFT) /* 13 ADCCLK cycles. For STM32L15XX: 11 ADCCLK cycles */
-#define ADC_CR1_RES_8BIT             (2 << ADC_CR1_RES_SHIFT) /* 11 ADCCLK cycles. For STM32L15XX: 9 ADCCLK cycles */
-#define ADC_CR1_RES_6BIT             (3 << ADC_CR1_RES_SHIFT) /* 9 ADCCLK cycles. For STM32L15XX: 7 ADCCLK cycles */
-#define ADC_CR1_OVRIE                (1 << 26) /* Bit 26: Overrun interrupt enable */
-
-/* ADC control register 2 */
-
-#define ADC_CR2_ADON                 (1 << 0)  /* Bit 0: A/D Converter ON / OFF */
-#define ADC_CR2_CONT                 (1 << 1)  /* Bit 1: Continuous Conversion */
-
-#define ADC_CR2_DMA                  (1 << 8)  /* Bit 8: Direct Memory access mode */
-
-#define ADC_CR2_DDS                  (1 << 9)  /* Bit 9: DMA disable selection (for single ADC mode) */
-#define ADC_CR2_EOCS                 (1 << 10) /* Bit 10: End of conversion selection */
-
-#define ADC_CR2_ALIGN                (1 << 11) /* Bit 11: Data Alignment */
-
-                                               /* Bits 12-15: Reserved */
-#define ADC_CR2_JEXTSEL_SHIFT        (16)      /* Bits 16-19: External event select for injected group */
-#define ADC_CR2_JEXTSEL_MASK         (0x0F << ADC_CR2_JEXTSEL_SHIFT)
-#define ADC_CR2_JEXTSEL_T1TRGO       (0x00 << ADC_CR2_JEXTSEL_SHIFT) /* 0000: Timer 1 TRGO event */
-#define ADC_CR2_JEXTSEL_T1CC4        (0x01 << ADC_CR2_JEXTSEL_SHIFT) /* 0001: Timer 1 CC4 event */
-#define ADC_CR2_JEXTSEL_T2TRGO       (0x02 << ADC_CR2_JEXTSEL_SHIFT) /* 0010: Timer 2 TRGO event */
-#define ADC_CR2_JEXTSEL_T2CC1        (0x03 << ADC_CR2_JEXTSEL_SHIFT) /* 0011: Timer 2 CC1 event */
-#define ADC_CR2_JEXTSEL_T3CC4        (0x04 << ADC_CR2_JEXTSEL_SHIFT) /* 0100: Timer 3 CC4 event */
-#define ADC_CR2_JEXTSEL_T4TRGO       (0x05 << ADC_CR2_JEXTSEL_SHIFT) /* 0101: Timer 4 TRGO event */
-                                                                     /* 0110: NA */
-#define ADC_CR2_JEXTSEL_T8CC4        (0x07 << ADC_CR2_JEXTSEL_SHIFT) /* 0111: Timer 8 CC4 event */
-#define ADC_CR2_JEXTSEL_T1TRGO2      (0x08 << ADC_CR2_JEXTSEL_SHIFT) /* 1000: Timer 1 TRGO2 event */
-#define ADC_CR2_JEXTSEL_T8TRGO       (0x09 << ADC_CR2_JEXTSEL_SHIFT) /* 1001: Timer 8 TRGO event */
-#define ADC_CR2_JEXTSEL_T8TRGO2      (0x0A << ADC_CR2_JEXTSEL_SHIFT) /* 1010: Timer 8 TRGO2 event */
-#define ADC_CR2_JEXTSEL_T3CC3        (0x0B << ADC_CR2_JEXTSEL_SHIFT) /* 1011: Timer 3 CC3 event */
-#define ADC_CR2_JEXTSEL_T5TRGO       (0x0C << ADC_CR2_JEXTSEL_SHIFT) /* 1100: Timer 5 TRGO event */
-#define ADC_CR2_JEXTSEL_T3CC1        (0x0D << ADC_CR2_JEXTSEL_SHIFT) /* 1101: Timer 3 CC1 event */
-#define ADC_CR2_JEXTSEL_T6TRGO       (0x0E << ADC_CR2_JEXTSEL_SHIFT) /* 1110: Timer 6 TRGO event */
-                                                                     /* 1111: NA */
-#define ADC_CR2_JEXTEN_SHIFT         (20)      /* Bits 20-21: External trigger enable for injected channels */
-#define ADC_CR2_JEXTEN_MASK          (3 << ADC_CR2_JEXTEN_SHIFT)
-#define ADC_CR2_JEXTEN_NONE          (0 << ADC_CR2_JEXTEN_SHIFT) /* 00: Trigger detection disabled */
-#define ADC_CR2_JEXTEN_RISING        (1 << ADC_CR2_JEXTEN_SHIFT) /* 01: Trigger detection on the rising edge */
-#define ADC_CR2_JEXTEN_FALLING       (2 << ADC_CR2_JEXTEN_SHIFT) /* 10: Trigger detection on the falling edge */
-#define ADC_CR2_JEXTEN_BOTH          (3 << ADC_CR2_JEXTEN_SHIFT) /* 11: Trigger detection on both the rising and falling edges */
-
-#define ADC_CR2_JSWSTART             (1 << 22) /* Bit 22: Start Conversion of injected channels */
-                                               /* Bit 23: Reserved, must be kept at reset value. */
-#define ADC_CR2_EXTSEL_SHIFT         (24)      /* Bits 24-27: External Event Select for regular group */
-#define ADC_CR2_EXTSEL_MASK          (0x0F << ADC_CR2_EXTSEL_SHIFT)
-#define ADC_CR2_EXTSEL_T1CC1         (0x0 << ADC_CR2_EXTSEL_SHIFT)  /* 0000: Timer 1 CC1 event */
-#define ADC_CR2_EXTSEL_T1CC2         (0x01 << ADC_CR2_EXTSEL_SHIFT) /* 0001: Timer 1 CC2 event */
-#define ADC_CR2_EXTSEL_T1CC3         (0x02 << ADC_CR2_EXTSEL_SHIFT) /* 0010: Timer 1 CC3 event */
-#define ADC_CR2_EXTSEL_T2CC2         (0x03 << ADC_CR2_EXTSEL_SHIFT) /* 0011: Timer 2 CC2 event */
-#define ADC_CR2_EXTSEL_T5TRGO        (0x04 << ADC_CR2_EXTSEL_SHIFT) /* 0100: Timer 5 TRGO event */
-#define ADC_CR2_EXTSEL_T4CC4         (0x05 << ADC_CR2_EXTSEL_SHIFT) /* 0101: Timer 4 CC4 event */
-#define ADC_CR2_EXTSEL_T3CC4         (0x06 << ADC_CR2_EXTSEL_SHIFT) /* 0110: Timer 3 CC4 event */
-#define ADC_CR2_EXTSEL_T8TRGO        (0x07 << ADC_CR2_EXTSEL_SHIFT) /* 0111: Timer 8 TRGO event */
-#define ADC_CR2_EXTSEL_T8TRGO2       (0x08 << ADC_CR2_EXTSEL_SHIFT) /* 1000: Timer 8 TRGO2 event */
-#define ADC_CR2_EXTSEL_T1TRGO        (0x09 << ADC_CR2_EXTSEL_SHIFT) /* 1001: Timer 1 TRGO event */
-#define ADC_CR2_EXTSEL_T1TRGO2       (0x0A << ADC_CR2_EXTSEL_SHIFT) /* 1010: Timer 1 TRGO2 event */
-#define ADC_CR2_EXTSEL_T2TRGO        (0x0B << ADC_CR2_EXTSEL_SHIFT) /* 1011: Timer 2 TRGO event */
-#define ADC_CR2_EXTSEL_T4TRGO        (0x0C << ADC_CR2_EXTSEL_SHIFT) /* 1100: Timer 4 TRGO event */
-#define ADC_CR2_EXTSEL_T6TRGO        (0x0D << ADC_CR2_EXTSEL_SHIFT) /* 1101: Timer 6 TRGO event */
-                                                                    /* 1110: NA */
-#define ADC_CR2_EXTSEL_EXTI11        (0x0F << ADC_CR2_EXTSEL_SHIFT) /* 1111: EXTI line 11 */
-
-#define ADC_CR2_EXTEN_SHIFT          (28)      /* Bits 28-29: External trigger enable for regular channels */
-#define ADC_CR2_EXTEN_MASK           (3 << ADC_CR2_EXTEN_SHIFT)
-#define ADC_CR2_EXTEN_NONE           (0 << ADC_CR2_EXTEN_SHIFT) /* 00: Trigger detection disabled */
-#define ADC_CR2_EXTEN_RISING         (1 << ADC_CR2_EXTEN_SHIFT) /* 01: Trigger detection on the rising edge */
-#define ADC_CR2_EXTEN_FALLING        (2 << ADC_CR2_EXTEN_SHIFT) /* 10: Trigger detection on the falling edge */
-#define ADC_CR2_EXTEN_BOTH           (3 << ADC_CR2_EXTEN_SHIFT) /* 11: Trigger detection on both the rising and falling edges */
-
-#  define ADC_CR2_SWSTART            (1 << 30) /* Bit 30: Start Conversion of regular channels */
-
-/* ADC sample time register 1 */
-
-#define ADC_SMPR_3                   0         /* 000: 3 cycles */
-#define ADC_SMPR_15                  1         /* 001: 15 cycles */
-#define ADC_SMPR_28                  2         /* 010: 28 cycles */
-#define ADC_SMPR_56                  3         /* 011: 56 cycles */
-#define ADC_SMPR_84                  4         /* 100: 84 cycles */
-#define ADC_SMPR_112                 5         /* 101: 112 cycles */
-#define ADC_SMPR_144                 6         /* 110: 144 cycles */
-#define ADC_SMPR_480                 7         /* 111: 480 cycles */
-
-#define ADC_SMPR1_SMP10_SHIFT        (0)       /* Bits 0-2: Channel 10 Sample time selection */
-#define ADC_SMPR1_SMP10_MASK         (7 << ADC_SMPR1_SMP10_SHIFT)
-#define ADC_SMPR1_SMP11_SHIFT        (3)       /* Bits 3-5: Channel 11 Sample time selection */
-#define ADC_SMPR1_SMP11_MASK         (7 << ADC_SMPR1_SMP11_SHIFT)
-#define ADC_SMPR1_SMP12_SHIFT        (6)       /* Bits 6-8: Channel 12 Sample time selection */
-#define ADC_SMPR1_SMP12_MASK         (7 << ADC_SMPR1_SMP12_SHIFT)
-#define ADC_SMPR1_SMP13_SHIFT        (9)       /* Bits 9-11: Channel 13 Sample time selection */
-#define ADC_SMPR1_SMP13_MASK         (7 << ADC_SMPR1_SMP13_SHIFT)
-#define ADC_SMPR1_SMP14_SHIFT        (12)      /* Bits 12-14: Channel 14 Sample time selection */
-#define ADC_SMPR1_SMP14_MASK         (7 << ADC_SMPR1_SMP14_SHIFT)
-#define ADC_SMPR1_SMP15_SHIFT        (15)      /* Bits 15-17: Channel 15 Sample time selection */
-#define ADC_SMPR1_SMP15_MASK         (7 << ADC_SMPR1_SMP15_SHIFT)
-#define ADC_SMPR1_SMP16_SHIFT        (18)      /* Bits 18-20: Channel 16 Sample time selection */
-#define ADC_SMPR1_SMP16_MASK         (7 << ADC_SMPR1_SMP16_SHIFT)
-#define ADC_SMPR1_SMP17_SHIFT        (21)      /* Bits 21-23: Channel 17 Sample time selection */
-#define ADC_SMPR1_SMP17_MASK         (7 << ADC_SMPR1_SMP17_SHIFT)
-#define ADC_SMPR1_SMP18_SHIFT        (21)      /* Bits 24-26: Channel 18 Sample time selection */
-#define ADC_SMPR1_SMP18_MASK         (7 << ADC_SMPR1_SMP17_SHIFT)
-
-
-/* ADC sample time register 2 */
-
-#define ADC_SMPR2_SMP0_SHIFT         (0)       /* Bits 2-0: Channel 0 Sample time selection */
-#define ADC_SMPR2_SMP0_MASK          (7 << ADC_SMPR2_SMP0_SHIFT)
-#define ADC_SMPR2_SMP1_SHIFT         (3)       /* Bits 5-3: Channel 1 Sample time selection */
-#define ADC_SMPR2_SMP1_MASK          (7 << ADC_SMPR2_SMP1_SHIFT)
-#define ADC_SMPR2_SMP2_SHIFT         (6)       /* Bits 8-6: Channel 2 Sample time selection */
-#define ADC_SMPR2_SMP2_MASK          (7 << ADC_SMPR2_SMP2_SHIFT)
-#define ADC_SMPR2_SMP3_SHIFT         (9)       /* Bits 11-9: Channel 3 Sample time selection */
-#define ADC_SMPR2_SMP3_MASK          (7 << ADC_SMPR2_SMP3_SHIFT)
-#define ADC_SMPR2_SMP4_SHIFT         (12)      /* Bits 14-12: Channel 4 Sample time selection */
-#define ADC_SMPR2_SMP4_MASK          (7 << ADC_SMPR2_SMP4_SHIFT)
-#define ADC_SMPR2_SMP5_SHIFT         (15)      /* Bits 17-15: Channel 5 Sample time selection */
-#define ADC_SMPR2_SMP5_MASK          (7 << ADC_SMPR2_SMP5_SHIFT)
-#define ADC_SMPR2_SMP6_SHIFT         (18)      /* Bits 20-18: Channel 6 Sample time selection */
-#define ADC_SMPR2_SMP6_MASK          (7 << ADC_SMPR2_SMP6_SHIFT)
-#define ADC_SMPR2_SMP7_SHIFT         (21)      /* Bits 23-21: Channel 7 Sample time selection */
-#define ADC_SMPR2_SMP7_MASK          (7 << ADC_SMPR2_SMP7_SHIFT)
-#define ADC_SMPR2_SMP8_SHIFT         (24)      /* Bits 26-24: Channel 8 Sample time selection */
-#define ADC_SMPR2_SMP8_MASK          (7 << ADC_SMPR2_SMP8_SHIFT)
-#define ADC_SMPR2_SMP9_SHIFT         (27)      /* Bits 29-27: Channel 9 Sample time selection */
-#define ADC_SMPR2_SMP9_MASK          (7 << ADC_SMPR2_SMP9_SHIFT)
-
-
-/* ADC injected channel data offset register 1-4 */
-
-#define ADC_JOFR_SHIFT               (0)       /* Bits 11-0: Data offset for injected channel x */
-#define ADC_JOFR_MASK                (0x0fff << ADC_JOFR_SHIFT)
-
-/* ADC watchdog high threshold register */
-
-#define ADC_HTR_SHIFT                (0)       /* Bits 11-0: Analog watchdog high threshold */
-#define ADC_HTR_MASK                 (0x0fff << ADC_HTR_SHIFT)
-
-/* ADC watchdog low threshold register */
-
-#define ADC_LTR_SHIFT                (0)       /* Bits 11-0: Analog watchdog low threshold */
-#define ADC_LTR_MASK                 (0x0fff << ADC_LTR_SHIFT)
-
-/* ADC regular sequence register 1 */
-
-#define ADC_SQR1_SQ13_SHIFT          (0)       /* Bits 4-0: 13th conversion in regular sequence */
-#define ADC_SQR1_SQ13_MASK           (0x1f << ADC_SQR1_SQ13_SHIFT)
-#define ADC_SQR1_SQ14_SHIFT          (5)       /* Bits 9-5: 14th conversion in regular sequence */
-#define ADC_SQR1_SQ14_MASK           (0x1f << ADC_SQR1_SQ14_SHIFT)
-#define ADC_SQR1_SQ15_SHIFT          (10)      /* Bits 14-10: 15th conversion in regular sequence */
-#define ADC_SQR1_SQ15_MASK           (0x1f << ADC_SQR1_SQ15_SHIFT)
-#define ADC_SQR1_SQ16_SHIFT          (15)      /* Bits 19-15: 16th conversion in regular sequence */
-#define ADC_SQR1_SQ16_MASK           (0x1f << ADC_SQR1_SQ16_SHIFT)
-#define ADC_SQR1_L_SHIFT             (20)      /* Bits 23-20: Regular channel sequence length */
-#define ADC_SQR1_L_MASK              (0x0f << ADC_SQR1_L_SHIFT)
-#define ADC_SQR1_RESERVED            (0xff000000)
-#define ADC_SQR1_FIRST               (13)
-#define ADC_SQR1_LAST                (16)
-#define ADC_SQR1_SQ_OFFSET           (0)
-
-/* ADC regular sequence register 2 */
-
-#define ADC_SQR2_SQ7_SHIFT           (0)       /* Bits 4-0: 7th conversion in regular sequence */
-#define ADC_SQR2_SQ7_MASK            (0x1f << ADC_SQR2_SQ7_SHIFT)
-#define ADC_SQR2_SQ8_SHIFT           (5)       /* Bits 9-5: 8th conversion in regular sequence */
-#define ADC_SQR2_SQ8_MASK            (0x1f << ADC_SQR2_SQ8_SHIFT)
-#define ADC_SQR2_SQ9_SHIFT           (10)      /* Bits 14-10: 9th conversion in regular sequence */
-#define ADC_SQR2_SQ9_MASK            (0x1f << ADC_SQR2_SQ9_SHIFT)
-#define ADC_SQR2_SQ10_SHIFT          (15)      /* Bits 19-15: 10th conversion in regular sequence */
-#define ADC_SQR2_SQ10_MASK           (0x1f << ADC_SQR2_SQ10_SHIFT)
-#define ADC_SQR2_SQ11_SHIFT          (20)      /* Bits 24-20: 11th conversion in regular sequence */
-#define ADC_SQR2_SQ11_MASK           (0x1f << ADC_SQR2_SQ11_SHIFT )
-#define ADC_SQR2_SQ12_SHIFT          (25)      /* Bits 29-25: 12th conversion in regular sequence */
-#define ADC_SQR2_SQ12_MASK           (0x1f << ADC_SQR2_SQ12_SHIFT)
-#define ADC_SQR2_RESERVED            (0xc0000000)
-#define ADC_SQR2_FIRST               (7)
-#define ADC_SQR2_LAST                (12)
-#define ADC_SQR2_SQ_OFFSET           (0)
-
-/* ADC regular sequence register 3 */
-
-#define ADC_SQR3_SQ1_SHIFT           (0)       /* Bits 4-0: 1st conversion in regular sequence */
-#define ADC_SQR3_SQ1_MASK            (0x1f << ADC_SQR3_SQ1_SHIFT)
-#define ADC_SQR3_SQ2_SHIFT           (5)       /* Bits 9-5: 2nd conversion in regular sequence */
-#define ADC_SQR3_SQ2_MASK            (0x1f << ADC_SQR3_SQ2_SHIFT)
-#define ADC_SQR3_SQ3_SHIFT           (10)      /* Bits 14-10: 3rd conversion in regular sequence */
-#define ADC_SQR3_SQ3_MASK            (0x1f << ADC_SQR3_SQ3_SHIFT)
-#define ADC_SQR3_SQ4_SHIFT           (15)      /* Bits 19-15: 4th conversion in regular sequence */
-#define ADC_SQR3_SQ4_MASK            (0x1f << ADC_SQR3_SQ4_SHIFT)
-#define ADC_SQR3_SQ5_SHIFT           (20)      /* Bits 24-20: 5th conversion in regular sequence */
-#define ADC_SQR3_SQ5_MASK            (0x1f << ADC_SQR3_SQ5_SHIFT )
-#define ADC_SQR3_SQ6_SHIFT           (25)      /* Bits 29-25: 6th conversion in regular sequence */
-#define ADC_SQR3_SQ6_MASK            (0x1f << ADC_SQR3_SQ6_SHIFT)
-#define ADC_SQR3_RESERVED            (0xc0000000)
-#define ADC_SQR3_FIRST               (1)
-#define ADC_SQR3_LAST                (6)
-#define ADC_SQR3_SQ_OFFSET           (0)
-
-/* Offset between SQ bits */
-
-#define ADC_SQ_OFFSET                (5)
-
-/* ADC injected sequence register */
-
-#define ADC_JSQR_JSQ1_SHIFT          (0)       /* Bits 4-0: 1st conversion in injected sequence */
-#define ADC_JSQR_JSQ1_MASK           (0x1f << ADC_JSQR_JSQ1_SHIFT)
-#define ADC_JSQR_JSQ2_SHIFT          (5)       /* Bits 9-5: 2nd conversion in injected sequence */
-#define ADC_JSQR_JSQ2_MASK           (0x1f << ADC_JSQR_JSQ2_SHIFT)
-#define ADC_JSQR_JSQ3_SHIFT          (10)      /* Bits 14-10: 3rd conversion in injected sequence */
-#define ADC_JSQR_JSQ3_MASK           (0x1f << ADC_JSQR_JSQ3_SHIFT)
-#define ADC_JSQR_JSQ4_SHIFT          (15)      /* Bits 19-15: 4th conversion in injected sequence */
-#define ADC_JSQR_JSQ4_MASK           (0x1f << ADC_JSQR_JSQ4_SHIFT)
-#define ADC_JSQR_JL_SHIFT            (20)      /* Bits 21-20: Injected Sequence length */
-#define ADC_JSQR_JL_MASK             (3 << ADC_JSQR_JL_SHIFT)
-
-/* ADC injected data register 1-4 */
-
-#define ADC_JDR_JDATA_SHIFT          (0)       /* Bits 15-0: Injected data */
-#define ADC_JDR_JDATA_MASK           (0xffff << ADC_JDR_JDATA_SHIFT)
-
-/* ADC regular data register */
-
-#define ADC_DR_RDATA_SHIFT           (0)       /* Bits 15-0 Regular data */
-#define ADC_DR_RDATA_MASK            (0xffff << ADC_DR_RDATA_SHIFT)
-
-/* Common status register */
-
-#define ADC_CSR_AWD1                 (1 << 0)  /* Bit 0:  Analog watchdog flag of ADC1 (copy of AWD in ADC1_SR) */
-#define ADC_CSR_EOC1                 (1 << 1)  /* Bit 1:  End of conversion of ADC1 (copy of EOC in ADC1_SR) */
-#define ADC_CSR_JEOC1                (1 << 2)  /* Bit 2:  Injected channel end of conversion of ADC1 (copy of JEOC in ADC1_SR) */
-#define ADC_CSR_JSTRT1               (1 << 3)  /* Bit 3:  Injected channel Start flag of ADC1 (copy of JSTRT in ADC1_SR) */
-#define ADC_CSR_STRT1                (1 << 4)  /* Bit 4:  Regular channel Start flag of ADC1 (copy of STRT in ADC1_SR) */
-#define ADC_CSR_OVR1                 (1 << 5)  /* Bit 5:  Overrun flag of ADC1 (copy of OVR in ADC1_SR) */
-
-#define ADC_CSR_AWD2                 (1 << 8)  /* Bit 8:  Analog watchdog flag of ADC2 (copy of AWD in ADC2_SR) */
-#define ADC_CSR_EOC2                 (1 << 9)  /* Bit 9:  End of conversion of ADC2 (copy of EOC in ADC2_SR) */
-#define ADC_CSR_JEOC2                (1 << 10) /* Bit 10: Injected channel end of conversion of ADC2 (copy of JEOC in ADC2_SR) */
-#define ADC_CSR_JSTRT2               (1 << 11) /* Bit 11: Injected channel Start flag of ADC2 (copy of JSTRT in ADC2_SR) */
-#define ADC_CSR_STRT2                (1 << 12) /* Bit 12: Regular channel Start flag of ADC2 (copy of STRT in ADC2_SR) */
-#define ADC_CSR_OVR2                 (1 << 13) /* Bit 13: Overrun flag of ADC2 (copy of OVR in ADC2_SR) */
-                                               /* Bits 14-15: Reserved, must be kept at reset value. */
-#define ADC_CSR_AWD3                 (1 << 16) /* Bit 16: ADC3 Analog watchdog flag (copy of AWD in ADC3_SR) */
-#define ADC_CSR_EOC3                 (1 << 17) /* Bit 17: ADC3 End of conversion (copy of EOC in ADC3_SR) */
-#define ADC_CSR_JEOC3                (1 << 18) /* Bit 18: ADC3 Injected channel end of conversion (copy of JEOC in ADC3_SR) */
-#define ADC_CSR_JSTRT3               (1 << 19) /* Bit 19: ADC3 Injected channel Start flag (copy of JSTRT in ADC3_SR) */
-#define ADC_CSR_STRT3                (1 << 20) /* Bit 20: ADC3 Regular channel Start flag (copy of STRT in ADC3_SR). */
-#define ADC_CSR_OVR3                 (1 << 21) /* Bit 21: ADC3 overrun flag (copy of OVR in ADC3_SR). */
-
-/* Common control register */
-
-#  define ADC_CCR_MULTI_SHIFT        (0)       /* Bits 0-4: Multi ADC mode selection */
-#  define ADC_CCR_MULTI_MASK         (31 << ADC_CCR_MULTI_SHIFT)
-#    define ADC_CCR_MULTI_NONE       (0 << ADC_CCR_MULTI_SHIFT)  /* 00000: Independent mode */
-                                                                 /* 00001 to 01001: Dual mode (ADC1 and ADC2), ADC3 independent */
-#    define ADC_CCR_MULTI_RSISM2     (1 << ADC_CCR_MULTI_SHIFT)  /* 00001: Combined regular simultaneous + injected simultaneous mode */
-#    define ADC_CCR_MULTI_RSATM2     (2 << ADC_CCR_MULTI_SHIFT)  /* 00010: Combined regular simultaneous + alternate trigger mode */
-#    define ADC_CCR_MULTI_ISM2       (5 << ADC_CCR_MULTI_SHIFT)  /* 00101: Injected simultaneous mode only */
-#    define ADC_CCR_MULTI_RSM2       (6 << ADC_CCR_MULTI_SHIFT)  /* 00110: Regular simultaneous mode only */
-#    define ADC_CCR_MULTI_IM2        (7 << ADC_CCR_MULTI_SHIFT)  /* 00111: interleaved mode only */
-#    define ADC_CCR_MULTI_ATM2       (9 << ADC_CCR_MULTI_SHIFT)  /* 01001: Alternate trigger mode only */
-                                                                 /* 10001 to 11001: Triple mode (ADC1, 2 and 3) */
-#    define ADC_CCR_MULTI_RSISM3     (17 << ADC_CCR_MULTI_SHIFT) /* 10001: Combined regular simultaneous + injected simultaneous mode */
-#    define ADC_CCR_MULTI_RSATM3     (18 << ADC_CCR_MULTI_SHIFT) /* 10010: Combined regular simultaneous + alternate trigger mode */
-#    define ADC_CCR_MULTI_ISM3       (21 << ADC_CCR_MULTI_SHIFT) /* 10101: Injected simultaneous mode only */
-#    define ADC_CCR_MULTI_RSM3       (22 << ADC_CCR_MULTI_SHIFT) /* 10110: Regular simultaneous mode only */
-#    define ADC_CCR_MULTI_IM3        (23 << ADC_CCR_MULTI_SHIFT) /* 10111: interleaved mode only */
-#    define ADC_CCR_MULTI_ATM3       (25 << ADC_CCR_MULTI_SHIFT) /* 11001: Alternate trigger mode only */
-                                               /* Bits 5-7: Reserved, must be kept at reset value. */
-#  define ADC_CCR_DELAY_SHIFT        (8)       /* Bits 8-11: Delay between 2 sampling phases */
-#  define ADC_CCR_DELAY_MASK         (15 << ADC_CCR_DELAY_SHIFT)
-#    define ADC_CCR_DELAY(n)         (((n)-5) << ADC_CCR_DELAY_SHIFT) /* n * TADCCLK, n=5-20 */
-                                               /* Bit 12 Reserved, must be kept at reset value. */
-#  define ADC_CCR_DDS                (1 << 13) /* Bit 13: DMA disable selection (for multi-ADC mode) */
-
-#  define ADC_CCR_DMA_SHIFT          (14)      /* Bits 14-15: Direct memory access mode for multi ADC mode */
-#  define ADC_CCR_DMA_MASK           (3 << ADC_CCR_DMA_SHIFT)
-#    define ADC_CCR_DMA_DISABLED     (0 << ADC_CCR_DMA_SHIFT) /* 00: DMA mode disabled */
-#    define ADC_CCR_DMA_MODE1        (1 << ADC_CCR_DMA_SHIFT) /* 01: DMA mode 1 enabled */
-#    define ADC_CCR_DMA_MODE2        (2 << ADC_CCR_DMA_SHIFT) /* 10: DMA mode 2 enabled */
-#    define ADC_CCR_DMA_MODE3        (3 << ADC_CCR_DMA_SHIFT) /* 11: DMA mode 3 enabled */
-
-#  define ADC_CCR_ADCPRE_SHIFT       (16)      /* Bits 16-17: ADC prescaler */
-#  define ADC_CCR_ADCPRE_MASK        (3 << ADC_CCR_ADCPRE_SHIFT)
-#    define ADC_CCR_ADCPRE_DIV2      (0 << ADC_CCR_ADCPRE_SHIFT) /* 00: PCLK2 divided by 2 */
-#    define ADC_CCR_ADCPRE_DIV4      (1 << ADC_CCR_ADCPRE_SHIFT) /* 01: PCLK2 divided by 4 */
-#    define ADC_CCR_ADCPRE_DIV6      (2 << ADC_CCR_ADCPRE_SHIFT) /* 10: PCLK2 divided by 6 */
-#    define ADC_CCR_ADCPRE_DIV8      (3 << ADC_CCR_ADCPRE_SHIFT) /* 11: PCLK2 divided by 8 */
-                                               /* Bits 18-21: Reserved, must be kept at reset value. */
-#  define ADC_CCR_VBATE              (1 << 22) /* Bit 22: VBAT enable */
-#  define ADC_CCR_TSVREFE            (1 << 23) /* Bit 23: Temperature sensor and VREFINT enable */
-                                               /* Bits 24-31 Reserved, must be kept at reset value. */
-
-/* Data register for dual and triple modes (32-bit data with no named fields) */
-
-/****************************************************************************************************
- * Public Types
- ****************************************************************************************************/
-
-/****************************************************************************************************
- * Public Data
- ****************************************************************************************************/
-
-/****************************************************************************************************
- * Public Function Prototypes
- ****************************************************************************************************/
-
-#endif /* __ARCH_ARM_SRC_STM32F_CHIP_STM32_ADC_H */
+#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32_ADC_H */
diff --git a/arch/arm/src/stm32f7/chip/stm32_i2c.h b/arch/arm/src/stm32f7/chip/stm32_i2c.h
index d8fd9f8ce63..f615eb6ec18 100644
--- a/arch/arm/src/stm32f7/chip/stm32_i2c.h
+++ b/arch/arm/src/stm32f7/chip/stm32_i2c.h
@@ -2,7 +2,8 @@
  * arch/arm/src/stm32f7/chip/stm32_i2c.h
  *
  *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *   Authors: Gregory Nutt <gnutt@nuttx.org>
+ *            David Sidrane <david_s5@nscdg.com>
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -43,10 +44,11 @@
 #include <nuttx/config.h>
 #include "chip.h"
 
-#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
-#  include "chip/stm32f74xx75xx_i2c.h"
+#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \
+    defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
+#  include "chip/stm32f74xx77xx_i2c.h"
 #else
-#  error "Unsupported STM32 F7 part"
+#  error "Unsupported STM32 F7 sub family"
 #endif
 
 #endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32_I2C_H */
diff --git a/arch/arm/src/stm32f7/chip/stm32_spi.h b/arch/arm/src/stm32f7/chip/stm32_spi.h
index dbd4d7301e3..1874d88bca6 100644
--- a/arch/arm/src/stm32f7/chip/stm32_spi.h
+++ b/arch/arm/src/stm32f7/chip/stm32_spi.h
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_STC_STM32F7_CHIP_STM32_SPI_H
-#define __ARCH_ARM_STC_STM32F7_CHIP_STM32_SPI_H
+#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32_SPI_H
+#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32_SPI_H
 
 /************************************************************************************
  * Included Files
@@ -44,215 +44,10 @@
 #include <nuttx/config.h>
 #include "chip.h"
 
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
-/* Maximum allowed speed as per data sheet for all SPIs (both pclk1 and pclk2)*/
-
-#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
-#  define STM32_SPI_CLK_MAX     50000000UL
-#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
-#  define STM32_SPI_CLK_MAX     54000000UL
+#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \
+    defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
+#  include "chip/stm32f74xx77xx_spi.h"
+#else
+#  error "Unsupported STM32 F7 sub family"
 #endif
-
-/* Register Offsets *****************************************************************/
-
-#define STM32_SPI_CR1_OFFSET       0x0000  /* SPI Control Register 1 (16-bit) */
-#define STM32_SPI_CR2_OFFSET       0x0004  /* SPI control register 2 (16-bit) */
-#define STM32_SPI_SR_OFFSET        0x0008  /* SPI status register (16-bit) */
-#define STM32_SPI_DR_OFFSET        0x000c  /* SPI data register (16-bit) */
-#define STM32_SPI_CRCPR_OFFSET     0x0010  /* SPI CRC polynomial register (16-bit) */
-#define STM32_SPI_RXCRCR_OFFSET    0x0014  /* SPI Rx CRC register (16-bit) */
-#define STM32_SPI_TXCRCR_OFFSET    0x0018  /* SPI Tx CRC register (16-bit) */
-#define STM32_SPI_I2SCFGR_OFFSET   0x001c  /* I2S configuration register */
-#define STM32_SPI_I2SPR_OFFSET     0x0020  /* I2S prescaler register */
-
-/* Register Addresses ***************************************************************/
-
-#if STM32F7_NSPI > 0
-#  define STM32_SPI1_CR1          (STM32_SPI1_BASE+STM32_SPI_CR1_OFFSET)
-#  define STM32_SPI1_CR2          (STM32_SPI1_BASE+STM32_SPI_CR2_OFFSET)
-#  define STM32_SPI1_SR           (STM32_SPI1_BASE+STM32_SPI_SR_OFFSET)
-#  define STM32_SPI1_DR           (STM32_SPI1_BASE+STM32_SPI_DR_OFFSET)
-#  define STM32_SPI1_CRCPR        (STM32_SPI1_BASE+STM32_SPI_CRCPR_OFFSET)
-#  define STM32_SPI1_RXCRCR       (STM32_SPI1_BASE+STM32_SPI_RXCRCR_OFFSET)
-#  define STM32_SPI1_TXCRCR       (STM32_SPI1_BASE+STM32_SPI_TXCRCR_OFFSET)
-#endif
-
-#if STM32F7_NSPI > 1
-#  define STM32_SPI2_CR1          (STM32_SPI2_BASE+STM32_SPI_CR1_OFFSET)
-#  define STM32_SPI2_CR2          (STM32_SPI2_BASE+STM32_SPI_CR2_OFFSET)
-#  define STM32_SPI2_SR           (STM32_SPI2_BASE+STM32_SPI_SR_OFFSET)
-#  define STM32_SPI2_DR           (STM32_SPI2_BASE+STM32_SPI_DR_OFFSET)
-#  define STM32_SPI2_CRCPR        (STM32_SPI2_BASE+STM32_SPI_CRCPR_OFFSET)
-#  define STM32_SPI2_RXCRCR       (STM32_SPI2_BASE+STM32_SPI_RXCRCR_OFFSET)
-#  define STM32_SPI2_TXCRCR       (STM32_SPI2_BASE+STM32_SPI_TXCRCR_OFFSET)
-#  define STM32_SPI2_I2SCFGR      (STM32_SPI2_BASE+STM32_SPI_I2SCFGR_OFFSET)
-#  define STM32_SPI2_I2SPR        (STM32_SPI2_BASE+STM32_SPI_I2SPR_OFFSET)
-#endif
-
-#if STM32F7_NSPI > 2
-#  define STM32_SPI3_CR1          (STM32_SPI3_BASE+STM32_SPI_CR1_OFFSET)
-#  define STM32_SPI3_CR2          (STM32_SPI3_BASE+STM32_SPI_CR2_OFFSET)
-#  define STM32_SPI3_SR           (STM32_SPI3_BASE+STM32_SPI_SR_OFFSET)
-#  define STM32_SPI3_DR           (STM32_SPI3_BASE+STM32_SPI_DR_OFFSET)
-#  define STM32_SPI3_CRCPR        (STM32_SPI3_BASE+STM32_SPI_CRCPR_OFFSET)
-#  define STM32_SPI3_RXCRCR       (STM32_SPI3_BASE+STM32_SPI_RXCRCR_OFFSET)
-#  define STM32_SPI3_TXCRCR       (STM32_SPI3_BASE+STM32_SPI_TXCRCR_OFFSET)
-#  define STM32_SPI3_I2SCFGR      (STM32_SPI3_BASE+STM32_SPI_I2SCFGR_OFFSET)
-#  define STM32_SPI3_I2SPR        (STM32_SPI3_BASE+STM32_SPI_I2SPR_OFFSET)
-#endif
-
-#if STM32F7_NSPI > 3
-#  define STM32_SPI4_CR1          (STM32_SPI4_BASE+STM32_SPI_CR1_OFFSET)
-#  define STM32_SPI4_CR2          (STM32_SPI4_BASE+STM32_SPI_CR2_OFFSET)
-#  define STM32_SPI4_SR           (STM32_SPI4_BASE+STM32_SPI_SR_OFFSET)
-#  define STM32_SPI4_DR           (STM32_SPI4_BASE+STM32_SPI_DR_OFFSET)
-#  define STM32_SPI4_CRCPR        (STM32_SPI4_BASE+STM32_SPI_CRCPR_OFFSET)
-#  define STM32_SPI4_RXCRCR       (STM32_SPI4_BASE+STM32_SPI_RXCRCR_OFFSET)
-#  define STM32_SPI4_TXCRCR       (STM32_SPI4_BASE+STM32_SPI_TXCRCR_OFFSET)
-#  define STM32_SPI4_I2SCFGR      (STM32_SPI4_BASE+STM32_SPI_I2SCFGR_OFFSET)
-#  define STM32_SPI4_I2SPR        (STM32_SPI4_BASE+STM32_SPI_I2SPR_OFFSET)
-#endif
-
-#if STM32F7_NSPI > 4
-#  define STM32_SPI5_CR1          (STM32_SPI5_BASE+STM32_SPI_CR1_OFFSET)
-#  define STM32_SPI5_CR2          (STM32_SPI5_BASE+STM32_SPI_CR2_OFFSET)
-#  define STM32_SPI5_SR           (STM32_SPI5_BASE+STM32_SPI_SR_OFFSET)
-#  define STM32_SPI5_DR           (STM32_SPI5_BASE+STM32_SPI_DR_OFFSET)
-#  define STM32_SPI5_CRCPR        (STM32_SPI5_BASE+STM32_SPI_CRCPR_OFFSET)
-#  define STM32_SPI5_RXCRCR       (STM32_SPI5_BASE+STM32_SPI_RXCRCR_OFFSET)
-#  define STM32_SPI5_TXCRCR       (STM32_SPI5_BASE+STM32_SPI_TXCRCR_OFFSET)
-#  define STM32_SPI5_I2SCFGR      (STM32_SPI5_BASE+STM32_SPI_I2SCFGR_OFFSET)
-#  define STM32_SPI5_I2SPR        (STM32_SPI5_BASE+STM32_SPI_I2SPR_OFFSET)
-#endif
-
-#if STM32F7_NSPI > 5
-#  define STM32_SPI6_CR1          (STM32_SPI6_BASE+STM32_SPI_CR1_OFFSET)
-#  define STM32_SPI6_CR2          (STM32_SPI6_BASE+STM32_SPI_CR2_OFFSET)
-#  define STM32_SPI6_SR           (STM32_SPI6_BASE+STM32_SPI_SR_OFFSET)
-#  define STM32_SPI6_DR           (STM32_SPI6_BASE+STM32_SPI_DR_OFFSET)
-#  define STM32_SPI6_CRCPR        (STM32_SPI6_BASE+STM32_SPI_CRCPR_OFFSET)
-#  define STM32_SPI6_RXCRCR       (STM32_SPI6_BASE+STM32_SPI_RXCRCR_OFFSET)
-#  define STM32_SPI6_TXCRCR       (STM32_SPI6_BASE+STM32_SPI_TXCRCR_OFFSET)
-#  define STM32_SPI6_I2SCFGR      (STM32_SPI6_BASE+STM32_SPI_I2SCFGR_OFFSET)
-#  define STM32_SPI6_I2SPR        (STM32_SPI6_BASE+STM32_SPI_I2SPR_OFFSET)
-#endif
-
-/* Register Bitfield Definitions ****************************************************/
-
-/* SPI Control Register 1 */
-
-#define SPI_CR1_CPHA              (1 << 0)  /* Bit 0: Clock Phase */
-#define SPI_CR1_CPOL              (1 << 1)  /* Bit 1: Clock Polarity */
-#define SPI_CR1_MSTR              (1 << 2)  /* Bit 2: Master Selection */
-#define SPI_CR1_BR_SHIFT          (3)       /* Bits 5:3 Baud Rate Control */
-#define SPI_CR1_BR_MASK           (7 << SPI_CR1_BR_SHIFT)
-#  define SPI_CR1_FPCLCKd2        (0 << SPI_CR1_BR_SHIFT) /* 000: fPCLK/2 */
-#  define SPI_CR1_FPCLCKd4        (1 << SPI_CR1_BR_SHIFT) /* 001: fPCLK/4 */
-#  define SPI_CR1_FPCLCKd8        (2 << SPI_CR1_BR_SHIFT) /* 010: fPCLK/8 */
-#  define SPI_CR1_FPCLCKd16       (3 << SPI_CR1_BR_SHIFT) /* 011: fPCLK/16 */
-#  define SPI_CR1_FPCLCKd32       (4 << SPI_CR1_BR_SHIFT) /* 100: fPCLK/32 */
-#  define SPI_CR1_FPCLCKd64       (5 << SPI_CR1_BR_SHIFT) /* 101: fPCLK/64 */
-#  define SPI_CR1_FPCLCKd128      (6 << SPI_CR1_BR_SHIFT) /* 110: fPCLK/128 */
-#  define SPI_CR1_FPCLCKd256      (7 << SPI_CR1_BR_SHIFT) /* 111: fPCLK/256 */
-#define SPI_CR1_SPE               (1 << 6)  /* Bit 6: SPI Enable */
-#define SPI_CR1_LSBFIRST          (1 << 7)  /* Bit 7: Frame Format */
-#define SPI_CR1_SSI               (1 << 8)  /* Bit 8: Internal slave select */
-#define SPI_CR1_SSM               (1 << 9)  /* Bit 9: Software slave management */
-#define SPI_CR1_RXONLY            (1 << 10) /* Bit 10: Receive only */
-#define SPI_CR1_CRCL              (1 << 11) /* Bit 11: CRC length */
-#define SPI_CR1_CRCNEXT           (1 << 12) /* Bit 12: Transmit CRC next */
-#define SPI_CR1_CRCEN             (1 << 13) /* Bit 13: Hardware CRC calculation enable */
-#define SPI_CR1_BIDIOE            (1 << 14) /* Bit 14: Output enable in bidirectional mode */
-#define SPI_CR1_BIDIMODE          (1 << 15) /* Bit 15: Bidirectional data mode enable */
-
-/* SPI Control Register 2 */
-
-#define SPI_CR2_RXDMAEN           (1 << 0)  /* Bit 0: Rx Buffer DMA Enable */
-#define SPI_CR2_TXDMAEN           (1 << 1)  /* Bit 1: Tx Buffer DMA Enable */
-#define SPI_CR2_SSOE              (1 << 2)  /* Bit 2: SS Output Enable */
-#define SPI_CR2_NSSP              (1 << 3)  /* Bit 3 NSSP: NSS pulse management */
-#define SPI_CR2_FRF               (1 << 4)  /* Bit 4: Frame format */
-#define SPI_CR2_ERRIE             (1 << 5)  /* Bit 5: Error interrupt enable */
-#define SPI_CR2_RXNEIE            (1 << 6)  /* Bit 6: RX buffer not empty interrupt enable */
-#define SPI_CR2_TXEIE             (1 << 7)  /* Bit 7: Tx buffer empty interrupt enable */
-#define SPI_CR2_DS_SHIFT          (8)       /* Bits 8-11:  Data size */
-#define SPI_CR2_DS_MASK           (0xf << SPI_CR2_DS_SHIFT)
-#  define SPI_CR2_DS_VAL(bits)    (((bits)-1) << SPI_CR2_DS_SHIFT)
-#  define SPI_CR2_DS_4BIT         SPI_CR2_DS_VAL(4)
-#  define SPI_CR2_DS_5BIT         SPI_CR2_DS_VAL(5)
-#  define SPI_CR2_DS_6BIT         SPI_CR2_DS_VAL(6)
-#  define SPI_CR2_DS_7BIT         SPI_CR2_DS_VAL(7)
-#  define SPI_CR2_DS_8BIT         SPI_CR2_DS_VAL(8)
-#  define SPI_CR2_DS_9BIT         SPI_CR2_DS_VAL(9)
-#  define SPI_CR2_DS_10BIT        SPI_CR2_DS_VAL(10)
-#  define SPI_CR2_DS_11BIT        SPI_CR2_DS_VAL(11)
-#  define SPI_CR2_DS_12BIT        SPI_CR2_DS_VAL(12)
-#  define SPI_CR2_DS_13BIT        SPI_CR2_DS_VAL(13)
-#  define SPI_CR2_DS_14BIT        SPI_CR2_DS_VAL(14)
-#  define SPI_CR2_DS_15BIT        SPI_CR2_DS_VAL(15)
-#  define SPI_CR2_DS_16BIT        SPI_CR2_DS_VAL(16)
-#define SPI_CR2_FRXTH             (1 << 12) /* Bit 12: FIFO reception threshold */
-#define SPI_CR2_LDMARX            (1 << 13) /* Bit 13: Last DMA transfer for receptione */
-#define SPI_CR2_LDMATX            (1 << 14) /* Bit 14: Last DMA transfer for transmission */
-
-/* SPI status register */
-
-#define SPI_SR_RXNE               (1 << 0)  /* Bit 0: Receive buffer not empty */
-#define SPI_SR_TXE                (1 << 1)  /* Bit 1: Transmit buffer empty */
-#define SPI_SR_CHSIDE             (1 << 2)  /* Bit 2: Channel side (i2s) */
-#define SPI_SR_UDR                (1 << 3)  /* Bit 3: Underrun flag (i2s) */
-#define SPI_SR_CRCERR             (1 << 4)  /* Bit 4: CRC error flag */
-#define SPI_SR_MODF               (1 << 5)  /* Bit 5: Mode fault */
-#define SPI_SR_OVR                (1 << 6)  /* Bit 6: Overrun flag */
-#define SPI_SR_BSY                (1 << 7)  /* Bit 7: Busy flag */
-#define SPI_SR_FRE                (1 << 8)  /* Bit 8: Frame format error */
-#define SPI_SR_FRLVL_SHIFT       (9)       /* Bits 9-10: FIFO reception level */
-#define SPI_SR_FRLVL_MASK        (0x3 << SPI_SR_FRLVL_SHIFT)
-#  define SPI_SR_FRLVL_EMPTY     (0 << SPI_SR_FRLVL_SHIFT) /* FIFO empty */
-#  define SPI_SR_FRLVL_QUARTER   (1 << SPI_SR_FRLVL_SHIFT) /* 1/4 FIFO */
-#  define SPI_SR_FRLVL_HALF      (2 << SPI_SR_FRLVL_SHIFT) /* 1/2 FIFO */
-#  define SPI_SR_FRLVL_FULL      (3 << SPI_SR_FRLVL_SHIFT) /* FIFO full */
-#define SPI_SR_FTLVL_SHIFT       (11)      /* Bits 11-12: FIFO transmission level */
-#define SPI_SR_FTLVL_MASK        (0x3 << SPI_SR_FTLVL_SHIFT)
-#  define SPI_SR_FTLVL_EMPTY     (0 << SPI_SR_FTLVL_SHIFT) /* FIFO empty */
-#  define SPI_SR_FTLVL_QUARTER   (1 << SPI_SR_FTLVL_SHIFT) /* 1/4 FIFO */
-#  define SPI_SR_FTLVL_HALF      (2 << SPI_SR_FTLVL_SHIFT) /* 1/2 FIFO */
-#  define SPI_SR_FTLVL_FULL      (3 << SPI_SR_FTLVL_SHIFT) /* FIFO full */
-
-/* I2S configuration register */
-
-#define SPI_I2SCFGR_CHLEN          (1 << 0)  /* Bit 0: Channel length (number of bits per audio channel) */
-#define SPI_I2SCFGR_DATLEN_SHIFT   (1)       /* Bit 1-2: Data length to be transferred */
-#define SPI_I2SCFGR_DATLEN_MASK    (3 << SPI_I2SCFGR_DATLEN_SHIFT)
-#  define SPI_I2SCFGR_DATLEN_16BIT (0 << SPI_I2SCFGR_DATLEN_SHIFT) /* 00: 16-bit data length */
-#  define SPI_I2SCFGR_DATLEN_8BIT  (1 << SPI_I2SCFGR_DATLEN_SHIFT) /* 01: 24-bit data length */
-#  define SPI_I2SCFGR_DATLEN_32BIT (2 << SPI_I2SCFGR_DATLEN_SHIFT) /* 10: 32-bit data length */
-#define SPI_I2SCFGR_CKPOL          (1 << 3)  /* Bit 3: Steady state clock polarity */
-#define SPI_I2SCFGR_I2SSTD_SHIFT   (4)       /* Bit 4-5: I2S standard selection */
-#define SPI_I2SCFGR_I2SSTD_MASK    (3 << SPI_I2SCFGR_I2SSTD_SHIFT)
-#  define SPI_I2SCFGR_I2SSTD_PHILLIPS    (00 << SPI_I2SCFGR_I2SSTD_SHIFT) /* 00: I2S Phillips standard. */
-#  define SPI_I2SCFGR_I2SSTD_MSB   (1 << SPI_I2SCFGR_I2SSTD_SHIFT) /* 01: MSB justified standard (left justified) */
-#  define SPI_I2SCFGR_I2SSTD_LSB   (2 << SPI_I2SCFGR_I2SSTD_SHIFT) /* 10: LSB justified standard (right justified) */
-#  define SPI_I2SCFGR_I2SSTD_PCM   (3 << SPI_I2SCFGR_I2SSTD_SHIFT) /* 11: PCM standard */
-#define SPI_I2SCFGR_PCMSYNC        (1 << 7)  /* Bit 7: PCM frame synchronization */
-#define SPI_I2SCFGR_I2SCFG_SHIFT   (8)       /* Bit 8-9: I2S configuration mode */
-#define SPI_I2SCFGR_I2SCFG_MASK    (3 << SPI_I2SCFGR_I2SCFG_SHIFT)
-#  define SPI_I2SCFGR_I2SCFG_STX   (0 << SPI_I2SCFGR_I2SCFG_SHIFT) /* 00: Slave - transmit */
-#  define SPI_I2SCFGR_I2SCFG_SRX   (1 << SPI_I2SCFGR_I2SCFG_SHIFT) /* 01: Slave - receive */
-#  define SPI_I2SCFGR_I2SCFG_MTX   (2 << SPI_I2SCFGR_I2SCFG_SHIFT) /* 10: Master - transmit */
-#  define SPI_I2SCFGR_I2SCFG_MRX   (3 << SPI_I2SCFGR_I2SCFG_SHIFT) /* 11: Master - receive */
-#define SPI_I2SCFGR_I2SE           (1 << 10) /* Bit 10: I2S Enable */
-#define SPI_I2SCFGR_I2SMOD         (1 << 11) /* Bit 11: I2S mode selection */
-#define SPI_I2SCFGR_ASTRTEN        (1 << 12) /* Bit 12: Asynchronous start enable */
-
-/* I2S prescaler register */
-
-#define SPI_I2SPR_I2SDIV_SHIFT     (0)       /* Bit 0-7: I2S Linear prescaler */
-#define SPI_I2SPR_I2SDIV_MASK      (0xff << SPI_I2SPR_I2SDIV_SHIFT)
-#define SPI_I2SPR_ODD              (1 << 8)  /* Bit 8: Odd factor for the prescaler */
-#define SPI_I2SPR_MCKOE            (1 << 9)  /* Bit 9: Master clock output enable */
-
-#endif /* __ARCH_ARM_STC_STM32F7_CHIP_STM32_SPI_H */
+#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32_SPI_H */
diff --git a/arch/arm/src/stm32f7/chip/stm32_tim.h b/arch/arm/src/stm32f7/chip/stm32_tim.h
index f4e04c39b1c..77204d861d8 100644
--- a/arch/arm/src/stm32f7/chip/stm32_tim.h
+++ b/arch/arm/src/stm32f7/chip/stm32_tim.h
@@ -2,7 +2,8 @@
  * arch/arm/src/stm32f7/chip/stm32_tim.h
  *
  *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *   Authors: Gregory Nutt <gnutt@nuttx.org>
+ *            David Sidrane <david_s5@nscdg.com>
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -36,1092 +37,19 @@
 #ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32_TIM_H
 #define __ARCH_ARM_SRC_STM32F7_CHIP_STM32_TIM_H
 
-/****************************************************************************************************
- * Pre-processor Definitions
- ****************************************************************************************************/
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
 
-/* Register Offsets *********************************************************************************/
+#include <nuttx/config.h>
+#include "chip.h"
 
-/* Basic Timers - TIM6 and TIM7 */
-
-#define STM32_BTIM_CR1_OFFSET     0x0000  /* Control register 1 (16-bit) */
-#define STM32_BTIM_CR2_OFFSET     0x0004  /* Control register 2 (16-bit) */
-#define STM32_BTIM_DIER_OFFSET    0x000c  /* DMA/Interrupt enable register (16-bit) */
-#define STM32_BTIM_SR_OFFSET      0x0010  /* Status register (16-bit) */
-#define STM32_BTIM_EGR_OFFSET     0x0014  /* Event generation register (16-bit) */
-#define STM32_BTIM_CNT_OFFSET     0x0024  /* Counter (16-bit) */
-#define STM32_BTIM_PSC_OFFSET     0x0028  /* Prescaler (16-bit) */
-#define STM32_BTIM_ARR_OFFSET     0x002c  /* Auto-reload register (16-bit) */
-
-/* 16-/32-bit General Timers with DMA: TIM2, TM3, TIM4, and TIM5
- * 16-bit General Timers without DMA: TIM9, TIM10, TIM11, TIM12, TIM13, and TIM14
- * For the STM32F10xx all timers are 16-bit.
- * For the STM32F20xx and STM32F40xx, TIM2 and 5 are 32-bit
- * The STM32 F1 Value Line and the STM32 F3 have variant general purpose registers
- *   that are not yet fully covered in this header file.
- */
-
-#define STM32_GTIM_CR1_OFFSET      0x0000  /* Control register 1 (16-bit) */
-#define STM32_GTIM_CR2_OFFSET      0x0004  /* Control register 2 (16-bit, TIM2-5 only) */
-#define STM32_GTIM_SMCR_OFFSET     0x0008  /* Slave mode control register (16-bit, TIM2-5 only) */
-#define STM32_GTIM_DIER_OFFSET     0x000c  /* DMA/Interrupt enable register (16-bit) */
-#define STM32_GTIM_SR_OFFSET       0x0010  /* Status register (16-bit) */
-#define STM32_GTIM_EGR_OFFSET      0x0014  /* Event generation register (16-bit) */
-#define STM32_GTIM_CCMR1_OFFSET    0x0018  /* Capture/compare mode register 1 (16-bit) */
-#define STM32_GTIM_CCMR2_OFFSET    0x001c  /* Capture/compare mode register 2 (16-bit, TIM2-5 only) */
-#define STM32_GTIM_CCER_OFFSET     0x0020  /* Capture/compare enable register (16-bit) */
-#define STM32_GTIM_CNT_OFFSET      0x0024  /* Counter (16-bit* or 32-bit STM3240 TIM2 and 5 only) */
-#define STM32_GTIM_PSC_OFFSET      0x0028  /* Prescaler (16-bit) */
-#define STM32_GTIM_ARR_OFFSET      0x002c  /* Auto-reload register (16-bit) */
-#define STM32_GTIM_CCR1_OFFSET     0x0034  /* Capture/compare register 1 (16-bit or 32-bit STM3240 TIM2/5 only) */
-#define STM32_GTIM_CCR2_OFFSET     0x0038  /* Capture/compare register 2 (16-bit TIM2-5 only or 32-bit STM32 F4 TIM2/5 or STM2 F3 TIM15 only) */
-#define STM32_GTIM_CCR3_OFFSET     0x003c  /* Capture/compare register 3 (16-bit TIM2-5 only or 32-bit STM32 F4 TIM2/5 only) */
-#define STM32_GTIM_CCR4_OFFSET     0x0040  /* Capture/compare register 4 (16-bit TIM2-5 only or 32-bit STM32 F4 TIM2/5 only) */
-#define STM32_GTIM_DCR_OFFSET      0x0048  /* DMA control register (16-bit, TIM2-5 only) */
-#define STM32_GTIM_DMAR_OFFSET     0x004c  /* DMA address for burst mode (16-bit, TIM2-5 only) */
-
-/* The Option register is available on in the
- *
- *   STM32 F1 value line, F2 and F4:  TIM2, TIM5, and TIM11
- *   STM32 F3 (and possibly the F1 value line): TIM16
- */
-
-#define STM32_GTIM_OR_OFFSET       0x0050  /* Timer 2/5/11/16 option register */
-
-/* TIM16, and 17 only.
- * Only available in the STM32 F1 Value Line and the STM32 F3 family.
- */
-
-#define STM32_GTIM_RCR_OFFSET      0x002c  /* Repetition counter register (TIM16/TIM17) */
-#define STM32_GTIM_BDTR_OFFSET     0x0044  /* Break and dead-time register (TIM16/TIM17) */
-
-/* Advanced Timers - TIM1 and TIM8 */
-
-#define STM32_ATIM_CR1_OFFSET      0x0000  /* Control register 1 (16-bit) */
-#define STM32_ATIM_CR2_OFFSET      0x0004  /* Control register 2 (16-bit*) */
-#define STM32_ATIM_SMCR_OFFSET     0x0008  /* Slave mode control register (16-bit) */
-#define STM32_ATIM_DIER_OFFSET     0x000c  /* DMA/Interrupt enable register (16-bit) */
-#define STM32_ATIM_SR_OFFSET       0x0010  /* Status register (16-bit*) */
-#define STM32_ATIM_EGR_OFFSET      0x0014  /* Event generation register (16-bit) */
-#define STM32_ATIM_CCMR1_OFFSET    0x0018  /* Capture/compare mode register 1 (16-bit*) */
-#define STM32_ATIM_CCMR2_OFFSET    0x001c  /* Capture/compare mode register 2 (16-bit*) */
-#define STM32_ATIM_CCER_OFFSET     0x0020  /* Capture/compare enable register (16-bit*) */
-#define STM32_ATIM_CNT_OFFSET      0x0024  /* Counter (16-bit) */
-#define STM32_ATIM_PSC_OFFSET      0x0028  /* Prescaler (16-bit) */
-#define STM32_ATIM_ARR_OFFSET      0x002c  /* Auto-reload register (16-bit) */
-#define STM32_ATIM_RCR_OFFSET      0x0030  /* Repetition counter register (16-bit) */
-#define STM32_ATIM_CCR1_OFFSET     0x0034  /* Capture/compare register 1 (16-bit) */
-#define STM32_ATIM_CCR2_OFFSET     0x0038  /* Capture/compare register 2 (16-bit) */
-#define STM32_ATIM_CCR3_OFFSET     0x003c  /* Capture/compare register 3 (16-bit) */
-#define STM32_ATIM_CCR4_OFFSET     0x0040  /* Capture/compare register 4 (16-bit) */
-#define STM32_ATIM_BDTR_OFFSET     0x0044  /* Break and dead-time register (16-bit*) */
-#define STM32_ATIM_DCR_OFFSET      0x0048  /* DMA control register (16-bit) */
-#define STM32_ATIM_DMAR_OFFSET     0x004c  /* DMA address for burst mode (16-bit) */
-
-/* Register Addresses *******************************************************************************/
-
-/* Advanced Timers - TIM1 and TIM8 */
-
-#if STM32F7_NATIM > 0
-#  define STM32_TIM1_CR1          (STM32_TIM1_BASE+STM32_ATIM_CR1_OFFSET)
-#  define STM32_TIM1_CR2          (STM32_TIM1_BASE+STM32_ATIM_CR2_OFFSET)
-#  define STM32_TIM1_SMCR         (STM32_TIM1_BASE+STM32_ATIM_SMCR_OFFSET)
-#  define STM32_TIM1_DIER         (STM32_TIM1_BASE+STM32_ATIM_DIER_OFFSET)
-#  define STM32_TIM1_SR           (STM32_TIM1_BASE+STM32_ATIM_SR_OFFSET)
-#  define STM32_TIM1_EGR          (STM32_TIM1_BASE+STM32_ATIM_EGR_OFFSET)
-#  define STM32_TIM1_CCMR1        (STM32_TIM1_BASE+STM32_ATIM_CCMR1_OFFSET)
-#  define STM32_TIM1_CCMR2        (STM32_TIM1_BASE+STM32_ATIM_CCMR2_OFFSET)
-#  define STM32_TIM1_CCER         (STM32_TIM1_BASE+STM32_ATIM_CCER_OFFSET)
-#  define STM32_TIM1_CNT          (STM32_TIM1_BASE+STM32_ATIM_CNT_OFFSET)
-#  define STM32_TIM1_PSC          (STM32_TIM1_BASE+STM32_ATIM_PSC_OFFSET)
-#  define STM32_TIM1_ARR          (STM32_TIM1_BASE+STM32_ATIM_ARR_OFFSET)
-#  define STM32_TIM1_RCR          (STM32_TIM1_BASE+STM32_ATIM_RCR_OFFSET)
-#  define STM32_TIM1_CCR1         (STM32_TIM1_BASE+STM32_ATIM_CCR1_OFFSET)
-#  define STM32_TIM1_CCR2         (STM32_TIM1_BASE+STM32_ATIM_CCR2_OFFSET)
-#  define STM32_TIM1_CCR3         (STM32_TIM1_BASE+STM32_ATIM_CCR3_OFFSET)
-#  define STM32_TIM1_CCR4         (STM32_TIM1_BASE+STM32_ATIM_CCR4_OFFSET)
-#  define STM32_TIM1_BDTR         (STM32_TIM1_BASE+STM32_ATIM_BDTR_OFFSET)
-#  define STM32_TIM1_DCR          (STM32_TIM1_BASE+STM32_ATIM_DCR_OFFSET)
-#  define STM32_TIM1_DMAR         (STM32_TIM1_BASE+STM32_ATIM_DMAR_OFFSET)
+#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
+#  include "chip/stm32f74xx75xx_tim.h"
+#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
+#  include "chip/stm32f76xx77xx_tim.h"
+#else
+#  error "Unsupported STM32 F7 sub family"
 #endif
 
-#if STM32F7_NATIM > 1
-#  define STM32_TIM8_CR1          (STM32_TIM8_BASE+STM32_ATIM_CR1_OFFSET)
-#  define STM32_TIM8_CR2          (STM32_TIM8_BASE+STM32_ATIM_CR2_OFFSET)
-#  define STM32_TIM8_SMCR         (STM32_TIM8_BASE+STM32_ATIM_SMCR_OFFSET)
-#  define STM32_TIM8_DIER         (STM32_TIM8_BASE+STM32_ATIM_DIER_OFFSET)
-#  define STM32_TIM8_SR           (STM32_TIM8_BASE+STM32_ATIM_SR_OFFSET)
-#  define STM32_TIM8_EGR          (STM32_TIM8_BASE+STM32_ATIM_EGR_OFFSET)
-#  define STM32_TIM8_CCMR1        (STM32_TIM8_BASE+STM32_ATIM_CCMR1_OFFSET)
-#  define STM32_TIM8_CCMR2        (STM32_TIM8_BASE+STM32_ATIM_CCMR2_OFFSET)
-#  define STM32_TIM8_CCER         (STM32_TIM8_BASE+STM32_ATIM_CCER_OFFSET)
-#  define STM32_TIM8_CNT          (STM32_TIM8_BASE+STM32_ATIM_CNT_OFFSET)
-#  define STM32_TIM8_PSC          (STM32_TIM8_BASE+STM32_ATIM_PSC_OFFSET)
-#  define STM32_TIM8_ARR          (STM32_TIM8_BASE+STM32_ATIM_ARR_OFFSET)
-#  define STM32_TIM8_RCR          (STM32_TIM8_BASE+STM32_ATIM_RCR_OFFSET)
-#  define STM32_TIM8_CCR1         (STM32_TIM8_BASE+STM32_ATIM_CCR1_OFFSET)
-#  define STM32_TIM8_CCR2         (STM32_TIM8_BASE+STM32_ATIM_CCR2_OFFSET)
-#  define STM32_TIM8_CCR3         (STM32_TIM8_BASE+STM32_ATIM_CCR3_OFFSET)
-#  define STM32_TIM8_CCR4         (STM32_TIM8_BASE+STM32_ATIM_CCR4_OFFSET)
-#  define STM32_TIM8_BDTR         (STM32_TIM8_BASE+STM32_ATIM_BDTR_OFFSET)
-#  define STM32_TIM8_DCR          (STM32_TIM8_BASE+STM32_ATIM_DCR_OFFSET)
-#  define STM32_TIM8_DMAR         (STM32_TIM8_BASE+STM32_ATIM_DMAR_OFFSET)
-#endif
-
-/* 16-/32-bit General Timers - TIM2, TIM3, TIM4, and TIM5 with DMA.
- * For the STM32F10xx all timers are 16-bit.
- * For the STM32F2xx and STM32F40xx, TIM2 and 5 are 32-bit
- */
-
-#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 0
-#  define STM32_TIM2_CR1          (STM32_TIM2_BASE+STM32_GTIM_CR1_OFFSET)
-#  define STM32_TIM2_CR2          (STM32_TIM2_BASE+STM32_GTIM_CR2_OFFSET)
-#  define STM32_TIM2_SMCR         (STM32_TIM2_BASE+STM32_GTIM_SMCR_OFFSET)
-#  define STM32_TIM2_DIER         (STM32_TIM2_BASE+STM32_GTIM_DIER_OFFSET)
-#  define STM32_TIM2_SR           (STM32_TIM2_BASE+STM32_GTIM_SR_OFFSET)
-#  define STM32_TIM2_EGR          (STM32_TIM2_BASE+STM32_GTIM_EGR_OFFSET)
-#  define STM32_TIM2_CCMR1        (STM32_TIM2_BASE+STM32_GTIM_CCMR1_OFFSET)
-#  define STM32_TIM2_CCMR2        (STM32_TIM2_BASE+STM32_GTIM_CCMR2_OFFSET)
-#  define STM32_TIM2_CCER         (STM32_TIM2_BASE+STM32_GTIM_CCER_OFFSET)
-#  define STM32_TIM2_CNT          (STM32_TIM2_BASE+STM32_GTIM_CNT_OFFSET)
-#  define STM32_TIM2_PSC          (STM32_TIM2_BASE+STM32_GTIM_PSC_OFFSET)
-#  define STM32_TIM2_ARR          (STM32_TIM2_BASE+STM32_GTIM_ARR_OFFSET)
-#  define STM32_TIM2_CCR1         (STM32_TIM2_BASE+STM32_GTIM_CCR1_OFFSET)
-#  define STM32_TIM2_CCR2         (STM32_TIM2_BASE+STM32_GTIM_CCR2_OFFSET)
-#  define STM32_TIM2_CCR3         (STM32_TIM2_BASE+STM32_GTIM_CCR3_OFFSET)
-#  define STM32_TIM2_CCR4         (STM32_TIM2_BASE+STM32_GTIM_CCR4_OFFSET)
-#  define STM32_TIM2_DCR          (STM32_TIM2_BASE+STM32_GTIM_DCR_OFFSET)
-#  define STM32_TIM2_DMAR         (STM32_TIM2_BASE+STM32_GTIM_DMAR_OFFSET)
-#endif
-
-#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 1
-#  define STM32_TIM3_CR1          (STM32_TIM3_BASE+STM32_GTIM_CR1_OFFSET)
-#  define STM32_TIM3_CR2          (STM32_TIM3_BASE+STM32_GTIM_CR2_OFFSET)
-#  define STM32_TIM3_SMCR         (STM32_TIM3_BASE+STM32_GTIM_SMCR_OFFSET)
-#  define STM32_TIM3_DIER         (STM32_TIM3_BASE+STM32_GTIM_DIER_OFFSET)
-#  define STM32_TIM3_SR           (STM32_TIM3_BASE+STM32_GTIM_SR_OFFSET)
-#  define STM32_TIM3_EGR          (STM32_TIM3_BASE+STM32_GTIM_EGR_OFFSET)
-#  define STM32_TIM3_CCMR1        (STM32_TIM3_BASE+STM32_GTIM_CCMR1_OFFSET)
-#  define STM32_TIM3_CCMR2        (STM32_TIM3_BASE+STM32_GTIM_CCMR2_OFFSET)
-#  define STM32_TIM3_CCER         (STM32_TIM3_BASE+STM32_GTIM_CCER_OFFSET)
-#  define STM32_TIM3_CNT          (STM32_TIM3_BASE+STM32_GTIM_CNT_OFFSET)
-#  define STM32_TIM3_PSC          (STM32_TIM3_BASE+STM32_GTIM_PSC_OFFSET)
-#  define STM32_TIM3_ARR          (STM32_TIM3_BASE+STM32_GTIM_ARR_OFFSET)
-#  define STM32_TIM3_CCR1         (STM32_TIM3_BASE+STM32_GTIM_CCR1_OFFSET)
-#  define STM32_TIM3_CCR2         (STM32_TIM3_BASE+STM32_GTIM_CCR2_OFFSET)
-#  define STM32_TIM3_CCR3         (STM32_TIM3_BASE+STM32_GTIM_CCR3_OFFSET)
-#  define STM32_TIM3_CCR4         (STM32_TIM3_BASE+STM32_GTIM_CCR4_OFFSET)
-#  define STM32_TIM3_DCR          (STM32_TIM3_BASE+STM32_GTIM_DCR_OFFSET)
-#  define STM32_TIM3_DMAR         (STM32_TIM3_BASE+STM32_GTIM_DMAR_OFFSET)
-#endif
-
-#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 2
-#  define STM32_TIM4_CR1          (STM32_TIM4_BASE+STM32_GTIM_CR1_OFFSET)
-#  define STM32_TIM4_CR2          (STM32_TIM4_BASE+STM32_GTIM_CR2_OFFSET)
-#  define STM32_TIM4_SMCR         (STM32_TIM4_BASE+STM32_GTIM_SMCR_OFFSET)
-#  define STM32_TIM4_DIER         (STM32_TIM4_BASE+STM32_GTIM_DIER_OFFSET)
-#  define STM32_TIM4_SR           (STM32_TIM4_BASE+STM32_GTIM_SR_OFFSET)
-#  define STM32_TIM4_EGR          (STM32_TIM4_BASE+STM32_GTIM_EGR_OFFSET)
-#  define STM32_TIM4_CCMR1        (STM32_TIM4_BASE+STM32_GTIM_CCMR1_OFFSET)
-#  define STM32_TIM4_CCMR2        (STM32_TIM4_BASE+STM32_GTIM_CCMR2_OFFSET)
-#  define STM32_TIM4_CCER         (STM32_TIM4_BASE+STM32_GTIM_CCER_OFFSET)
-#  define STM32_TIM4_CNT          (STM32_TIM4_BASE+STM32_GTIM_CNT_OFFSET)
-#  define STM32_TIM4_PSC          (STM32_TIM4_BASE+STM32_GTIM_PSC_OFFSET)
-#  define STM32_TIM4_ARR          (STM32_TIM4_BASE+STM32_GTIM_ARR_OFFSET)
-#  define STM32_TIM4_CCR1         (STM32_TIM4_BASE+STM32_GTIM_CCR1_OFFSET)
-#  define STM32_TIM4_CCR2         (STM32_TIM4_BASE+STM32_GTIM_CCR2_OFFSET)
-#  define STM32_TIM4_CCR3         (STM32_TIM4_BASE+STM32_GTIM_CCR3_OFFSET)
-#  define STM32_TIM4_CCR4         (STM32_TIM4_BASE+STM32_GTIM_CCR4_OFFSET)
-#  define STM32_TIM4_DCR          (STM32_TIM4_BASE+STM32_GTIM_DCR_OFFSET)
-#  define STM32_TIM4_DMAR         (STM32_TIM4_BASE+STM32_GTIM_DMAR_OFFSET)
-#endif
-
-#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 3
-#  define STM32_TIM5_CR1          (STM32_TIM5_BASE+STM32_GTIM_CR1_OFFSET)
-#  define STM32_TIM5_CR2          (STM32_TIM5_BASE+STM32_GTIM_CR2_OFFSET)
-#  define STM32_TIM5_SMCR         (STM32_TIM5_BASE+STM32_GTIM_SMCR_OFFSET)
-#  define STM32_TIM5_DIER         (STM32_TIM5_BASE+STM32_GTIM_DIER_OFFSET)
-#  define STM32_TIM5_SR           (STM32_TIM5_BASE+STM32_GTIM_SR_OFFSET)
-#  define STM32_TIM5_EGR          (STM32_TIM5_BASE+STM32_GTIM_EGR_OFFSET)
-#  define STM32_TIM5_CCMR1        (STM32_TIM5_BASE+STM32_GTIM_CCMR1_OFFSET)
-#  define STM32_TIM5_CCMR2        (STM32_TIM5_BASE+STM32_GTIM_CCMR2_OFFSET)
-#  define STM32_TIM5_CCER         (STM32_TIM5_BASE+STM32_GTIM_CCER_OFFSET)
-#  define STM32_TIM5_CNT          (STM32_TIM5_BASE+STM32_GTIM_CNT_OFFSET)
-#  define STM32_TIM5_PSC          (STM32_TIM5_BASE+STM32_GTIM_PSC_OFFSET)
-#  define STM32_TIM5_ARR          (STM32_TIM5_BASE+STM32_GTIM_ARR_OFFSET)
-#  define STM32_TIM5_CCR1         (STM32_TIM5_BASE+STM32_GTIM_CCR1_OFFSET)
-#  define STM32_TIM5_CCR2         (STM32_TIM5_BASE+STM32_GTIM_CCR2_OFFSET)
-#  define STM32_TIM5_CCR3         (STM32_TIM5_BASE+STM32_GTIM_CCR3_OFFSET)
-#  define STM32_TIM5_CCR4         (STM32_TIM5_BASE+STM32_GTIM_CCR4_OFFSET)
-#  define STM32_TIM5_DCR          (STM32_TIM5_BASE+STM32_GTIM_DCR_OFFSET)
-#  define STM32_TIM5_DMAR         (STM32_TIM5_BASE+STM32_GTIM_DMAR_OFFSET)
-#  define STM32_TIM2_OR           (STM32_TIM2_BASE+STM32_GTIM_OR_OFFSET)
-#endif
-
-#define STM32_TIM15_CR1           (STM32_TIM15_BASE+STM32_GTIM_CR1_OFFSET)
-#define STM32_TIM15_CR2           (STM32_TIM15_BASE+STM32_GTIM_CR2_OFFSET)
-#define STM32_TIM15_SMCR          (STM32_TIM15_BASE+STM32_GTIM_SMCR_OFFSET)
-#define STM32_TIM15_DIER          (STM32_TIM15_BASE+STM32_GTIM_DIER_OFFSET)
-#define STM32_TIM15_SR            (STM32_TIM15_BASE+STM32_GTIM_SR_OFFSET)
-#define STM32_TIM15_EGR           (STM32_TIM15_BASE+STM32_GTIM_EGR_OFFSET)
-#define STM32_TIM15_CCMR1         (STM32_TIM15_BASE+STM32_GTIM_CCMR1_OFFSET)
-#define STM32_TIM15_CCER          (STM32_TIM15_BASE+STM32_GTIM_CCER_OFFSET)
-#define STM32_TIM15_CNT           (STM32_TIM15_BASE+STM32_GTIM_CNT_OFFSET)
-#define STM32_TIM15_PSC           (STM32_TIM15_BASE+STM32_GTIM_PSC_OFFSET)
-#define STM32_TIM15_ARR           (STM32_TIM15_BASE+STM32_GTIM_ARR_OFFSET)
-#define STM32_TIM15_RCR           (STM32_TIM15_BASE+STM32_GTIM_RCR_OFFSET)
-#define STM32_TIM15_CCR1          (STM32_TIM15_BASE+STM32_GTIM_CCR1_OFFSET)
-#define STM32_TIM15_CCR2          (STM32_TIM15_BASE+STM32_GTIM_CCR2_OFFSET)
-#define STM32_TIM15_BDTR          (STM32_TIM15_BASE+STM32_GTIM_BDTR_OFFSET)
-#define STM32_TIM15_DCR           (STM32_TIM15_BASE+STM32_GTIM_DCR_OFFSET)
-#define STM32_TIM15_DMAR          (STM32_TIM15_BASE+STM32_GTIM_DMAR_OFFSET)
-
-#define STM32_TIM16_CR1           (STM32_TIM16_BASE+STM32_GTIM_CR1_OFFSET)
-#define STM32_TIM16_CR2           (STM32_TIM16_BASE+STM32_GTIM_CR2_OFFSET)
-#define STM32_TIM16_DIER          (STM32_TIM16_BASE+STM32_GTIM_DIER_OFFSET)
-#define STM32_TIM16_SR            (STM32_TIM16_BASE+STM32_GTIM_SR_OFFSET)
-#define STM32_TIM16_EGR           (STM32_TIM16_BASE+STM32_GTIM_EGR_OFFSET)
-#define STM32_TIM16_CCMR1         (STM32_TIM16_BASE+STM32_GTIM_CCMR1_OFFSET)
-#define STM32_TIM16_CCMR2         (STM32_TIM16_BASE+STM32_GTIM_CCMR2_OFFSET)
-#define STM32_TIM16_CCER          (STM32_TIM16_BASE+STM32_GTIM_CCER_OFFSET)
-#define STM32_TIM16_CNT           (STM32_TIM16_BASE+STM32_GTIM_CNT_OFFSET)
-#define STM32_TIM16_PSC           (STM32_TIM16_BASE+STM32_GTIM_PSC_OFFSET)
-#define STM32_TIM16_ARR           (STM32_TIM16_BASE+STM32_GTIM_ARR_OFFSET)
-#define STM32_TIM16_RCR           (STM32_TIM16_BASE+STM32_GTIM_RCR_OFFSET)
-#define STM32_TIM16_CCR1          (STM32_TIM16_BASE+STM32_GTIM_CCR1_OFFSET)
-#define STM32_TIM16_BDTR          (STM32_TIM16_BASE+STM32_GTIM_BDTR_OFFSET)
-#define STM32_TIM16_DCR           (STM32_TIM16_BASE+STM32_GTIM_DCR_OFFSET)
-#define STM32_TIM16_DMAR          (STM32_TIM16_BASE+STM32_GTIM_DMAR_OFFSET)
-#define STM32_TIM16_OR            (STM32_TIM16_BASE+STM32_GTIM_OR_OFFSET)
-
-#define STM32_TIM17_CR1           (STM32_TIM17_BASE+STM32_GTIM_CR1_OFFSET)
-#define STM32_TIM17_CR2           (STM32_TIM17_BASE+STM32_GTIM_CR2_OFFSET)
-#define STM32_TIM17_DIER          (STM32_TIM17_BASE+STM32_GTIM_DIER_OFFSET)
-#define STM32_TIM17_SR            (STM32_TIM17_BASE+STM32_GTIM_SR_OFFSET)
-#define STM32_TIM17_EGR           (STM32_TIM17_BASE+STM32_GTIM_EGR_OFFSET)
-#define STM32_TIM17_CCMR1         (STM32_TIM17_BASE+STM32_GTIM_CCMR1_OFFSET)
-#define STM32_TIM17_CCMR2         (STM32_TIM17_BASE+STM32_GTIM_CCMR2_OFFSET)
-#define STM32_TIM17_CCER          (STM32_TIM17_BASE+STM32_GTIM_CCER_OFFSET)
-#define STM32_TIM17_CNT           (STM32_TIM17_BASE+STM32_GTIM_CNT_OFFSET)
-#define STM32_TIM17_PSC           (STM32_TIM17_BASE+STM32_GTIM_PSC_OFFSET)
-#define STM32_TIM17_ARR           (STM32_TIM17_BASE+STM32_GTIM_ARR_OFFSET)
-#define STM32_TIM17_RCR           (STM32_TIM17_BASE+STM32_GTIM_RCR_OFFSET)
-#define STM32_TIM17_CCR1          (STM32_TIM17_BASE+STM32_GTIM_CCR1_OFFSET)
-#define STM32_TIM17_BDTR          (STM32_TIM17_BASE+STM32_GTIM_BDTR_OFFSET)
-#define STM32_TIM17_DCR           (STM32_TIM17_BASE+STM32_GTIM_DCR_OFFSET)
-#define STM32_TIM17_DMAR          (STM32_TIM17_BASE+STM32_GTIM_DMAR_OFFSET)
-
-/* 16-bit General Timers - TIM9-14 without DMA.  Note that (1) these timers
- * support only a subset of the general timer registers are supported, and
- * (2) TIM9 and TIM12 differ from the others.
- */
-
-#if STM32F7_NGTIMNDMA > 0
-#  define STM32_TIM9_CR1          (STM32_TIM9_BASE+STM32_GTIM_CR1_OFFSET)
-#  define STM32_TIM9_CR2          (STM32_TIM9_BASE+STM32_GTIM_CR2_OFFSET)
-#  define STM32_TIM9_DIER         (STM32_TIM9_BASE+STM32_GTIM_DIER_OFFSET)
-#  define STM32_TIM9_SR           (STM32_TIM9_BASE+STM32_GTIM_SR_OFFSET)
-#  define STM32_TIM9_EGR          (STM32_TIM9_BASE+STM32_GTIM_EGR_OFFSET)
-#  define STM32_TIM9_CCMR1        (STM32_TIM9_BASE+STM32_GTIM_CCMR1_OFFSET)
-#  define STM32_TIM9_CCER         (STM32_TIM9_BASE+STM32_GTIM_CCER_OFFSET)
-#  define STM32_TIM9_CNT          (STM32_TIM9_BASE+STM32_GTIM_CNT_OFFSET)
-#  define STM32_TIM9_PSC          (STM32_TIM9_BASE+STM32_GTIM_PSC_OFFSET)
-#  define STM32_TIM9_ARR          (STM32_TIM9_BASE+STM32_GTIM_ARR_OFFSET)
-#  define STM32_TIM9_CCR1         (STM32_TIM9_BASE+STM32_GTIM_CCR1_OFFSET)
-#  define STM32_TIM9_CCR2         (STM32_TIM9_BASE+STM32_GTIM_CCR2_OFFSET)
-#endif
-
-#if STM32F7_NGTIMNDMA > 1
-#  define STM32_TIM10_CR1         (STM32_TIM10_BASE+STM32_GTIM_CR1_OFFSET)
-#  define STM32_TIM10_DIER        (STM32_TIM10_BASE+STM32_GTIM_DIER_OFFSET)
-#  define STM32_TIM10_SR          (STM32_TIM10_BASE+STM32_GTIM_SR_OFFSET)
-#  define STM32_TIM10_EGR         (STM32_TIM10_BASE+STM32_GTIM_EGR_OFFSET)
-#  define STM32_TIM10_CCMR1       (STM32_TIM10_BASE+STM32_GTIM_CCMR1_OFFSET)
-#  define STM32_TIM10_CCER        (STM32_TIM10_BASE+STM32_GTIM_CCER_OFFSET)
-#  define STM32_TIM10_CNT         (STM32_TIM10_BASE+STM32_GTIM_CNT_OFFSET)
-#  define STM32_TIM10_PSC         (STM32_TIM10_BASE+STM32_GTIM_PSC_OFFSET)
-#  define STM32_TIM10_ARR         (STM32_TIM10_BASE+STM32_GTIM_ARR_OFFSET)
-#  define STM32_TIM10_CCR1        (STM32_TIM10_BASE+STM32_GTIM_CCR1_OFFSET)
-#endif
-
-#if STM32F7_NGTIMNDMA > 2
-#  define STM32_TIM11_CR1         (STM32_TIM11_BASE+STM32_GTIM_CR1_OFFSET)
-#  define STM32_TIM11_DIER        (STM32_TIM11_BASE+STM32_GTIM_DIER_OFFSET)
-#  define STM32_TIM11_SR          (STM32_TIM11_BASE+STM32_GTIM_SR_OFFSET)
-#  define STM32_TIM11_EGR         (STM32_TIM11_BASE+STM32_GTIM_EGR_OFFSET)
-#  define STM32_TIM11_CCMR1       (STM32_TIM11_BASE+STM32_GTIM_CCMR1_OFFSET)
-#  define STM32_TIM11_CCER        (STM32_TIM11_BASE+STM32_GTIM_CCER_OFFSET)
-#  define STM32_TIM11_CNT         (STM32_TIM11_BASE+STM32_GTIM_CNT_OFFSET)
-#  define STM32_TIM11_PSC         (STM32_TIM11_BASE+STM32_GTIM_PSC_OFFSET)
-#  define STM32_TIM11_ARR         (STM32_TIM11_BASE+STM32_GTIM_ARR_OFFSET)
-#  define STM32_TIM11_CCR1        (STM32_TIM11_BASE+STM32_GTIM_CCR1_OFFSET)
-#  define STM32_TIM11_OR          (STM32_TIM11_BASE+STM32_GTIM_OR_OFFSET)
-#endif
-
-#if STM32F7_NGTIMNDMA > 3
-#  define STM32_TIM12_CR1         (STM32_TIM12_BASE+STM32_GTIM_CR1_OFFSET)
-#  define STM32_TIM12_CR2         (STM32_TIM9_BASE+STM32_GTIM_CR2_OFFSET)
-#  define STM32_TIM12_DIER        (STM32_TIM12_BASE+STM32_GTIM_DIER_OFFSET)
-#  define STM32_TIM12_SR          (STM32_TIM12_BASE+STM32_GTIM_SR_OFFSET)
-#  define STM32_TIM12_EGR         (STM32_TIM12_BASE+STM32_GTIM_EGR_OFFSET)
-#  define STM32_TIM12_CCMR1       (STM32_TIM12_BASE+STM32_GTIM_CCMR1_OFFSET)
-#  define STM32_TIM12_CCER        (STM32_TIM12_BASE+STM32_GTIM_CCER_OFFSET)
-#  define STM32_TIM12_CNT         (STM32_TIM12_BASE+STM32_GTIM_CNT_OFFSET)
-#  define STM32_TIM12_PSC         (STM32_TIM12_BASE+STM32_GTIM_PSC_OFFSET)
-#  define STM32_TIM12_ARR         (STM32_TIM12_BASE+STM32_GTIM_ARR_OFFSET)
-#  define STM32_TIM12_CCR1        (STM32_TIM12_BASE+STM32_GTIM_CCR1_OFFSET)
-#  define STM32_TIM12_CCR2        (STM32_TIM12_BASE+STM32_GTIM_CCR2_OFFSET)
-#endif
-
-#if STM32F7_NGTIMNDMA > 4
-#  define STM32_TIM13_CR1         (STM32_TIM13_BASE+STM32_GTIM_CR1_OFFSET)
-#  define STM32_TIM13_DIER        (STM32_TIM13_BASE+STM32_GTIM_DIER_OFFSET)
-#  define STM32_TIM13_SR          (STM32_TIM13_BASE+STM32_GTIM_SR_OFFSET)
-#  define STM32_TIM13_EGR         (STM32_TIM13_BASE+STM32_GTIM_EGR_OFFSET)
-#  define STM32_TIM13_CCMR1       (STM32_TIM13_BASE+STM32_GTIM_CCMR1_OFFSET)
-#  define STM32_TIM13_CCER        (STM32_TIM13_BASE+STM32_GTIM_CCER_OFFSET)
-#  define STM32_TIM13_CNT         (STM32_TIM13_BASE+STM32_GTIM_CNT_OFFSET)
-#  define STM32_TIM13_PSC         (STM32_TIM13_BASE+STM32_GTIM_PSC_OFFSET)
-#  define STM32_TIM13_ARR         (STM32_TIM13_BASE+STM32_GTIM_ARR_OFFSET)
-#  define STM32_TIM13_CCR1        (STM32_TIM13_BASE+STM32_GTIM_CCR1_OFFSET)
-#endif
-
-#if STM32F7_NGTIMNDMA > 5
-#  define STM32_TIM14_CR1         (STM32_TIM14_BASE+STM32_GTIM_CR1_OFFSET)
-#  define STM32_TIM14_DIER        (STM32_TIM14_BASE+STM32_GTIM_DIER_OFFSET)
-#  define STM32_TIM14_SR          (STM32_TIM14_BASE+STM32_GTIM_SR_OFFSET)
-#  define STM32_TIM14_EGR         (STM32_TIM14_BASE+STM32_GTIM_EGR_OFFSET)
-#  define STM32_TIM14_CCMR1       (STM32_TIM14_BASE+STM32_GTIM_CCMR1_OFFSET)
-#  define STM32_TIM14_CCER        (STM32_TIM14_BASE+STM32_GTIM_CCER_OFFSET)
-#  define STM32_TIM14_CNT         (STM32_TIM14_BASE+STM32_GTIM_CNT_OFFSET)
-#  define STM32_TIM14_PSC         (STM32_TIM14_BASE+STM32_GTIM_PSC_OFFSET)
-#  define STM32_TIM14_ARR         (STM32_TIM14_BASE+STM32_GTIM_ARR_OFFSET)
-#  define STM32_TIM14_CCR1        (STM32_TIM14_BASE+STM32_GTIM_CCR1_OFFSET)
-#endif
-
-/* Basic Timers - TIM6 and TIM7 */
-
-#if STM32F7_NBTIM > 0
-#  define STM32_TIM6_CR1          (STM32_TIM6_BASE+STM32_BTIM_CR1_OFFSET)
-#  define STM32_TIM6_CR2          (STM32_TIM6_BASE+STM32_BTIM_CR2_OFFSET)
-#  define STM32_TIM6_DIER         (STM32_TIM6_BASE+STM32_BTIM_DIER_OFFSET)
-#  define STM32_TIM6_SR           (STM32_TIM6_BASE+STM32_BTIM_SR_OFFSET)
-#  define STM32_TIM6_EGR          (STM32_TIM6_BASE+STM32_BTIM_EGR_OFFSET)
-#  define STM32_TIM6_CNT          (STM32_TIM6_BASE+STM32_BTIM_CNT_OFFSET)
-#  define STM32_TIM6_PSC          (STM32_TIM6_BASE+STM32_BTIM_PSC_OFFSET)
-#  define STM32_TIM6_ARR          (STM32_TIM6_BASE+STM32_BTIM_ARR_OFFSET)
-#endif
-
-#if STM32F7_NBTIM > 1
-#  define STM32_TIM7_CR1          (STM32_TIM7_BASE+STM32_BTIM_CR1_OFFSET)
-#  define STM32_TIM7_CR2          (STM32_TIM7_BASE+STM32_BTIM_CR2_OFFSET)
-#  define STM32_TIM7_DIER         (STM32_TIM7_BASE+STM32_BTIM_DIER_OFFSET)
-#  define STM32_TIM7_SR           (STM32_TIM7_BASE+STM32_BTIM_SR_OFFSET)
-#  define STM32_TIM7_EGR          (STM32_TIM7_BASE+STM32_BTIM_EGR_OFFSET)
-#  define STM32_TIM7_CNT          (STM32_TIM7_BASE+STM32_BTIM_CNT_OFFSET)
-#  define STM32_TIM7_PSC          (STM32_TIM7_BASE+STM32_BTIM_PSC_OFFSET)
-#  define STM32_TIM7_ARR          (STM32_TIM7_BASE+STM32_BTIM_ARR_OFFSET)
-#endif
-
-/* Register Bitfield Definitions ********************************************************************/
-
-/* Control register 1 */
-
-#define ATIM_CR1_CEN              (1 << 0)  /* Bit 0: Counter enable */
-#define ATIM_CR1_UDIS             (1 << 1)  /* Bit 1: Update disable */
-#define ATIM_CR1_URS              (1 << 2)  /* Bit 2: Update request source */
-#define ATIM_CR1_OPM              (1 << 3)  /* Bit 3: One pulse mode */
-#define ATIM_CR1_DIR              (1 << 4)  /* Bit 4: Direction */
-#define ATIM_CR1_CMS_SHIFT        (5)       /* Bits 6-5: Center-aligned mode selection */
-#define ATIM_CR1_CMS_MASK         (3 << ATIM_CR1_CMS_SHIFT)
-#  define ATIM_CR1_EDGE           (0 << ATIM_CR1_CMS_SHIFT) /* 00: Edge-aligned mode */
-#  define ATIM_CR1_CENTER1        (1 << ATIM_CR1_CMS_SHIFT) /* 01: Center-aligned mode 1 */
-#  define ATIM_CR1_CENTER2        (2 << ATIM_CR1_CMS_SHIFT) /* 10: Center-aligned mode 2 */
-#  define ATIM_CR1_CENTER3        (3 << ATIM_CR1_CMS_SHIFT) /* 11: Center-aligned mode 3 */
-#define ATIM_CR1_ARPE             (1 << 7)  /* Bit 7: Auto-reload preload enable */
-#define ATIM_CR1_CKD_SHIFT        (8)       /* Bits 9-8: Clock division */
-#define ATIM_CR1_CKD_MASK         (3 << ATIM_CR1_CKD_SHIFT)
-#  define ATIM_CR1_TCKINT         (0 << ATIM_CR1_CKD_SHIFT) /* 00: tDTS=tCK_INT */
-#  define ATIM_CR1_2TCKINT        (1 << ATIM_CR1_CKD_SHIFT) /* 01: tDTS=2*tCK_INT */
-#  define ATIM_CR1_4TCKINT        (2 << ATIM_CR1_CKD_SHIFT) /* 10: tDTS=4*tCK_INT */
-
-/* Control register 2 */
-
-#define ATIM_CR2_CCPC             (1 << 0)  /* Bit 0:  Capture/Compare Preloaded Control */
-#define ATIM_CR2_CCUS             (1 << 2)  /* Bit 2:  Capture/Compare Control Update Selection */
-#define ATIM_CR2_CCDS             (1 << 3)  /* Bit 3:  Capture/Compare DMA Selection */
-#define ATIM_CR2_MMS_SHIFT        (4)       /* Bits 6-4: Master Mode Selection */
-#define ATIM_CR2_MMS_MASK         (7 << ATIM_CR2_MMS_SHIFT)
-#  define ATIM_CR2_MMS_RESET      (0 << ATIM_CR2_MMS_SHIFT) /* 000: Reset - TIMx_EGR UG bit is TRGO */
-#  define ATIM_CR2_MMS_ENABLE     (1 << ATIM_CR2_MMS_SHIFT) /* 001: Enable - CNT_EN is TRGO */
-#  define ATIM_CR2_MMS_UPDATE     (2 << ATIM_CR2_MMS_SHIFT) /* 010: Update event is TRGO */
-#  define ATIM_CR2_MMS_COMPP      (3 << ATIM_CR2_MMS_SHIFT) /* 010: Compare Pulse - CC1IF flag */
-#  define ATIM_CR2_MMS_OC1REF     (4 << ATIM_CR2_MMS_SHIFT) /* 100: Compare OC1REF is TRGO */
-#  define ATIM_CR2_MMS_OC2REF     (5 << ATIM_CR2_MMS_SHIFT) /* 101: Compare OC2REF is TRGO */
-#  define ATIM_CR2_MMS_OC3REF     (6 << ATIM_CR2_MMS_SHIFT) /* 110: Compare OC3REF is TRGO */
-#  define ATIM_CR2_MMS_OC4REF     (7 << ATIM_CR2_MMS_SHIFT) /* 111: Compare OC4REF is TRGO */
-#define ATIM_CR2_TI1S             (1 << 7)  /* Bit 7: TI1 Selection */
-#define ATIM_CR2_OIS1             (1 << 8)  /* Bit 8:  Output Idle state 1 (OC1 output) */
-#define ATIM_CR2_OIS1N            (1 << 9)  /* Bit 9:  Output Idle state 1 (OC1N output) */
-#define ATIM_CR2_OIS2             (1 << 10) /* Bit 10: Output Idle state 2 (OC2 output) */
-#define ATIM_CR2_OIS2N            (1 << 11) /* Bit 11: Output Idle state 2 (OC2N output) */
-#define ATIM_CR2_OIS3             (1 << 12) /* Bit 12: Output Idle state 3 (OC3 output) */
-#define ATIM_CR2_OIS3N            (1 << 13) /* Bit 13: Output Idle state 3 (OC3N output) */
-#define ATIM_CR2_OIS4             (1 << 14) /* Bit 14: Output Idle state 4 (OC4 output) */
-
-/* Slave mode control register */
-
-#define ATIM_SMCR_SMS_SHIFT       (0)       /* Bits 0-2: Slave mode selection */
-#define ATIM_SMCR_SMS_MASK        (7 << ATIM_SMCR_SMS_SHIFT)
-#  define ATIM_SMCR_DISAB         (0 << ATIM_SMCR_SMS_SHIFT) /* 000: Slave mode disabled */
-#  define ATIM_SMCR_ENCMD1        (1 << ATIM_SMCR_SMS_SHIFT) /* 001: Encoder mode 1 */
-#  define ATIM_SMCR_ENCMD2        (2 << ATIM_SMCR_SMS_SHIFT) /* 010: Encoder mode 2 */
-#  define ATIM_SMCR_ENCMD3        (3 << ATIM_SMCR_SMS_SHIFT) /* 011: Encoder mode 3 */
-#  define ATIM_SMCR_RESET         (4 << ATIM_SMCR_SMS_SHIFT) /* 100: Reset Mode */
-#  define ATIM_SMCR_GATED         (5 << ATIM_SMCR_SMS_SHIFT) /* 101: Gated Mode */
-#  define ATIM_SMCR_TRIGGER       (6 << ATIM_SMCR_SMS_SHIFT) /* 110: Trigger Mode */
-#  define ATIM_SMCR_EXTCLK1       (7 << ATIM_SMCR_SMS_SHIFT) /* 111: External Clock Mode 1 */
-#define ATIM_SMCR_TS_SHIFT        (4)       /* Bits 4-6: Trigger selection */
-#define ATIM_SMCR_TS_MASK         (7 << ATIM_SMCR_TS_SHIFT)
-#  define ATIM_SMCR_ITR0          (0 << ATIM_SMCR_TS_SHIFT) /* 000: Internal trigger 0 (ITR0) */
-#  define ATIM_SMCR_ITR1          (1 << ATIM_SMCR_TS_SHIFT) /* 001: Internal trigger 1 (ITR1) */
-#  define ATIM_SMCR_ITR2          (2 << ATIM_SMCR_TS_SHIFT) /* 010: Internal trigger 2 (ITR2) */
-#  define ATIM_SMCR_ITR3          (3 << ATIM_SMCR_TS_SHIFT) /* 011: Internal trigger 3 (ITR3) */
-#  define ATIM_SMCR_T1FED         (4 << ATIM_SMCR_TS_SHIFT) /* 100: TI1 Edge Detector (TI1F_ED) */
-#  define ATIM_SMCR_TI1FP1        (5 << ATIM_SMCR_TS_SHIFT) /* 101: Filtered Timer Input 1 (TI1FP1) */
-#  define ATIM_SMCR_T12FP2        (6 << ATIM_SMCR_TS_SHIFT) /* 110: Filtered Timer Input 2 (TI2FP2) */
-#  define ATIM_SMCR_ETRF          (7 << ATIM_SMCR_TS_SHIFT) /* 111: External Trigger input (ETRF) */
-#define ATIM_SMCR_MSM             (1 << 7)  /* Bit 7: Master/slave mode */
-#define ATIM_SMCR_ETF_SHIFT       (8)       /* Bits 8-11: External trigger filter */
-#define ATIM_SMCR_ETF_MASK        (0x0f << ATIM_SMCR_ETF_SHIFT)
-#  define ATIM_SMCR_NOFILT        (0 << ATIM_SMCR_ETF_SHIFT) /* 0000: No filter, sampling is done at fDTS */
-#  define ATIM_SMCR_FCKINT2       (1 << ATIM_SMCR_ETF_SHIFT) /* 0001: fSAMPLING=fCK_INT, N=2 */
-#  define ATIM_SMCR_FCKINT4       (2 << ATIM_SMCR_ETF_SHIFT) /* 0010: fSAMPLING=fCK_INT, N=4 */
-#  define ATIM_SMCR_FCKINT8       (3 << ATIM_SMCR_ETF_SHIFT) /* 0011: fSAMPLING=fCK_INT, N=8 */
-#  define ATIM_SMCR_FDTSd26       (4 << ATIM_SMCR_ETF_SHIFT) /* 0100: fSAMPLING=fDTS/2, N=6 */
-#  define ATIM_SMCR_FDTSd28       (5 << ATIM_SMCR_ETF_SHIFT) /* 0101: fSAMPLING=fDTS/2, N=8 */
-#  define ATIM_SMCR_FDTSd46       (6 << ATIM_SMCR_ETF_SHIFT) /* 0110: fSAMPLING=fDTS/4, N=6 */
-#  define ATIM_SMCR_FDTSd48       (7 << ATIM_SMCR_ETF_SHIFT) /* 0111: fSAMPLING=fDTS/4, N=8 */
-#  define ATIM_SMCR_FDTSd86       (8 << ATIM_SMCR_ETF_SHIFT) /* 1000: fSAMPLING=fDTS/8, N=6 */
-#  define ATIM_SMCR_FDTSd88       (9 << ATIM_SMCR_ETF_SHIFT) /* 1001: fSAMPLING=fDTS/8, N=8 */
-#  define ATIM_SMCR_FDTSd165      (10 << ATIM_SMCR_ETF_SHIFT) /* 1010: fSAMPLING=fDTS/16, N=5 */
-#  define ATIM_SMCR_FDTSd166      (11 << ATIM_SMCR_ETF_SHIFT) /* 1011: fSAMPLING=fDTS/16, N=6 */
-#  define ATIM_SMCR_FDTSd168      (12 << ATIM_SMCR_ETF_SHIFT) /* 1100: fSAMPLING=fDTS/16, N=8 */
-#  define ATIM_SMCR_FDTSd325      (13 << ATIM_SMCR_ETF_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */
-#  define ATIM_SMCR_FDTSd326      (14 << ATIM_SMCR_ETF_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */
-#  define ATIM_SMCR_FDTSd328      (15 << ATIM_SMCR_ETF_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */
-#define ATIM_SMCR_ETPS_SHIFT      (12)      /* Bits 12-13: External trigger prescaler */
-#define ATIM_SMCR_ETPS_MASK       (3 << ATIM_SMCR_ETPS_SHIFT)
-#  define ATIM_SMCR_PSCOFF        (0 << ATIM_SMCR_ETPS_SHIFT) /* 00: Prescaler OFF */
-#  define ATIM_SMCR_ETRPd2        (1 << ATIM_SMCR_ETPS_SHIFT) /* 01: ETRP frequency divided by 2 */
-#  define ATIM_SMCR_ETRPd4        (2 << ATIM_SMCR_ETPS_SHIFT) /* 10: ETRP frequency divided by 4 */
-#  define ATIM_SMCR_ETRPd8        (3 << ATIM_SMCR_ETPS_SHIFT) /* 11: ETRP frequency divided by 8 */
-#define ATIM_SMCR_ECE             (1 << 14) /* Bit 14: External clock enable */
-#define ATIM_SMCR_ETP             (1 << 15) /* Bit 15: External trigger polarity */
-
-/* DMA/Interrupt enable register */
-
-#define ATIM_DIER_UIE             (1 << 0)  /* Bit 0: Update interrupt enable */
-#define ATIM_DIER_CC1IE           (1 << 1)  /* Bit 1: Capture/Compare 1 interrupt enable */
-#define ATIM_DIER_CC2IE           (1 << 2)  /* Bit 2: Capture/Compare 2 interrupt enable */
-#define ATIM_DIER_CC3IE           (1 << 3)  /* Bit 3: Capture/Compare 3 interrupt enable */
-#define ATIM_DIER_CC4IE           (1 << 4)  /* Bit 4: Capture/Compare 4 interrupt enable */
-
-#define ATIM_DIER_TIE             (1 << 6)  /* Bit 6: Trigger interrupt enable */
-
-#define ATIM_DIER_UDE             (1 << 8)  /* Bit 8: Update DMA request enable */
-#define ATIM_DIER_CC1DE           (1 << 9)  /* Bit 9: Capture/Compare 1 DMA request enable */
-#define ATIM_DIER_CC2DE           (1 << 10) /* Bit 10: Capture/Compare 2 DMA request enable */
-#define ATIM_DIER_CC3DE           (1 << 11) /* Bit 11: Capture/Compare 3 DMA request enable */
-#define ATIM_DIER_CC4DE           (1 << 12) /* Bit 12: Capture/Compare 4 DMA request enable */
-
-#define ATIM_DIER_TDE             (1 << 14) /* Bit 14: Trigger DMA request enable */
-
-/* Status register */
-
-#define ATIM_SR_UIF               (1 << 0)  /* Bit 0:  Update interrupt Flag */
-#define ATIM_SR_CC1IF             (1 << 1)  /* Bit 1:  Capture/Compare 1 interrupt Flag */
-#define ATIM_SR_CC2IF             (1 << 2)  /* Bit 2:  Capture/Compare 2 interrupt Flag */
-#define ATIM_SR_CC3IF             (1 << 3)  /* Bit 3:  Capture/Compare 3 interrupt Flag */
-#define ATIM_SR_CC4IF             (1 << 4)  /* Bit 4:  Capture/Compare 4 interrupt Flag */
-#define ATIM_SR_COMIF             (1 << 5)  /* Bit 5:  COM interrupt Flag */
-#define ATIM_SR_TIF               (1 << 6)  /* Bit 6:  Trigger interrupt Flag */
-
-#define ATIM_SR_CC1OF             (1 << 9)  /* Bit 9:  Capture/Compare 1 Overcapture Flag */
-#define ATIM_SR_CC2OF             (1 << 10) /* Bit 10: Capture/Compare 2 Overcapture Flag */
-#define ATIM_SR_CC3OF             (1 << 11) /* Bit 11: Capture/Compare 3 Overcapture Flag */
-#define ATIM_SR_CC4OF             (1 << 12) /* Bit 12: Capture/Compare 4 Overcapture Flag */
-
-/* Event generation register */
-
-#define ATIM_EGR_UG               (1 << 0)  /* Bit 0: Update Generation */
-#define ATIM_EGR_CC1G             (1 << 1)  /* Bit 1: Capture/Compare 1 Generation */
-#define ATIM_EGR_CC2G             (1 << 2)  /* Bit 2: Capture/Compare 2 Generation */
-#define ATIM_EGR_CC3G             (1 << 3)  /* Bit 3: Capture/Compare 3 Generation */
-#define ATIM_EGR_CC4G             (1 << 4)  /* Bit 4: Capture/Compare 4 Generation */
-
-#define ATIM_EGR_TG               (1 << 6)  /* Bit 6: Trigger Generation */
-
-/* Capture/compare mode register 1 -- Output compare mode */
-
-#define ATIM_CCMR1_CC1S_SHIFT     (0)       /* Bits 1-0: Capture/Compare 1 Selection */
-#define ATIM_CCMR1_CC1S_MASK      (3 << ATIM_CCMR1_CC1S_SHIFT)
-                                            /* (See common (unshifted) bit field definitions below) */
-#define ATIM_CCMR1_OC1FE          (1 << 2)  /* Bit 2: Output Compare 1 Fast enable */
-#define ATIM_CCMR1_OC1PE          (1 << 3)  /* Bit 3: Output Compare 1 Preload enable */
-#define ATIM_CCMR1_OC1M_SHIFT     (4)       /* Bits 6-4: Output Compare 1 Mode */
-#define ATIM_CCMR1_OC1M_MASK      (7 << ATIM_CCMR1_OC1M_SHIFT)
-                                            /* (See common (unshifted) bit field definitions below) */
-#define ATIM_CCMR1_OC1CE          (1 << 7)  /* Bit 7: Output Compare 1Clear Enable */
-#define ATIM_CCMR1_CC2S_SHIFT     (8)       /* Bits 8-9: Capture/Compare 2 Selection */
-#define ATIM_CCMR1_CC2S_MASK      (3 << ATIM_CCMR1_CC2S_SHIFT)
-                                            /* (See common (unshifted) bit field definitions below) */
-#define ATIM_CCMR1_OC2FE          (1 << 10) /* Bit 10: Output Compare 2 Fast enable */
-#define ATIM_CCMR1_OC2PE          (1 << 11) /* Bit 11: Output Compare 2 Preload enable */
-#define ATIM_CCMR1_OC2M_SHIFT     (12)      /* Bits 14-12: Output Compare 2 Mode */
-#define ATIM_CCMR1_OC2M_MASK      (7 << ATIM_CCMR1_OC2M_SHIFT)
-                                            /* (See common (unshifted) bit field definitions below) */
-#define ATIM_CCMR1_OC2CE          (1 << 15) /* Bit 15: Output Compare 2 Clear Enable */
-
-/* Common CCMR (unshifted) Capture/Compare Selection bit-field definitions */
-
-#define ATIM_CCMR_CCS_CCOUT       (0)       /* 00: CCx channel  output */
-#define ATIM_CCMR_CCS_CCIN1       (1)       /* 01: CCx channel input, ICx is TIx */
-#define ATIM_CCMR_CCS_CCIN2       (2)       /* 10: CCx channel input, ICx is TIy */
-#define ATIM_CCMR_CCS_CCINTRC     (3)       /* 11: CCx channel input, ICx is TRC */
-
-/* Common CCMR (unshifted) Compare Mode bit field definitions */
-
-#define ATIM_CCMR_MODE_FRZN       (0)       /* 000: Frozen */
-#define ATIM_CCMR_MODE_CHACT      (1)       /* 001: Channel x active on match */
-#define ATIM_CCMR_MODE_CHINACT    (2)       /* 010: Channel x inactive on match */
-#define ATIM_CCMR_MODE_OCREFTOG   (3)       /* 011: OCxREF toggle ATIM_CNT=ATIM_CCRx */
-#define ATIM_CCMR_MODE_OCREFLO    (4)       /* 100: OCxREF forced low */
-#define ATIM_CCMR_MODE_OCREFHI    (5)       /* 101: OCxREF forced high */
-#define ATIM_CCMR_MODE_PWM1       (6)       /* 110: PWM mode 1 */
-#define ATIM_CCMR_MODE_PWM2       (7)       /* 111: PWM mode 2 */
-#define ATIM_CCMR_MODE_COMBINED1  (12)      /* 1100: Combined PWM mode 1 */
-#define ATIM_CCMR_MODE_COMBINED2  (13)      /* 1101: Combined PWM mode 2 */
-#define ATIM_CCMR_MODE_ASYMMETRIC1 (14)     /* 1110: Asymmetric PWM mode 1 */
-#define ATIM_CCMR_MODE_ASYMMETRIC2 (15)     /* 1111: Asymmetric PWM mode 2 */
-
-/* Capture/compare mode register 1 -- Input capture mode */
-
-                                            /* Bits 1-0:(same as output compare mode) */
-#define ATIM_CCMR1_IC1PSC_SHIFT   (2)       /* Bits 3-2: Input Capture 1 Prescaler */
-#define ATIM_CCMR1_IC1PSC_MASK    (3 << ATIM_CCMR1_IC1PSC_SHIFT)
-                                            /* (See common (unshifted) bit field definitions below) */
-#define ATIM_CCMR1_IC1F_SHIFT     (4)       /* Bits 7-4: Input Capture 1 Filter */
-#define ATIM_CCMR1_IC1F_MASK      (0x0f << ATIM_CCMR1_IC1F_SHIFT)
-                                            /* (See common (unshifted) bit field definitions below) */
-                                            /* Bits 9:8 (same as output compare mode) */
-#define ATIM_CCMR1_IC2PSC_SHIFT   (10)      /* Bits 11:10: Input Capture 2 Prescaler */
-#define ATIM_CCMR1_IC2PSC_MASK    (3 << ATIM_CCMR1_IC2PSC_SHIFT)
-                                            /* (See common (unshifted) bit field definitions below) */
-#define ATIM_CCMR1_IC2F_SHIFT     (12)      /* Bits 15-12: Input Capture 2 Filter */
-#define ATIM_CCMR1_IC2F_MASK      (0x0f << ATIM_CCMR1_IC2F_SHIFT)
-                                            /* (See common (unshifted) bit field definitions below) */
-
-/* Common CCMR (unshifted) Input Capture Prescaler bit-field definitions */
-
-#define ATIM_CCMR_ICPSC_NOPSC     (0)       /* 00: no prescaler, capture each edge */
-#define ATIM_CCMR_ICPSC_EVENTS2   (1)       /* 01: capture once every 2 events */
-#define ATIM_CCMR_ICPSC_EVENTS4   (2)       /* 10: capture once every 4 events */
-#define ATIM_CCMR_ICPSC_EVENTS8   (3)       /* 11: capture once every 8 events */
-
-/* Common CCMR (unshifted) Input Capture Filter bit-field definitions */
-
-#define ATIM_CCMR_ICF_NOFILT      (0)       /* 0000: No filter, sampling at fDTS */
-#define ATIM_CCMR_ICF_FCKINT2     (1)       /* 0001: fSAMPLING=fCK_INT, N=2 */
-#define ATIM_CCMR_ICF_FCKINT4     (2)       /* 0010: fSAMPLING=fCK_INT, N=4 */
-#define ATIM_CCMR_ICF_FCKINT8     (3)       /* 0011: fSAMPLING=fCK_INT, N=8 */
-#define ATIM_CCMR_ICF_FDTSd26     (4)       /* 0100: fSAMPLING=fDTS/2, N=6 */
-#define ATIM_CCMR_ICF_FDTSd28     (5)       /* 0101: fSAMPLING=fDTS/2, N=8 */
-#define ATIM_CCMR_ICF_FDTSd46     (6)       /* 0110: fSAMPLING=fDTS/4, N=6 */
-#define ATIM_CCMR_ICF_FDTSd48     (7)       /* 0111: fSAMPLING=fDTS/4, N=8 */
-#define ATIM_CCMR_ICF_FDTSd86     (8)       /* 1000: fSAMPLING=fDTS/8, N=6 */
-#define ATIM_CCMR_ICF_FDTSd88     (9)       /* 1001: fSAMPLING=fDTS/8, N=8 */
-#define ATIM_CCMR_ICF_FDTSd165    (10)      /* 1010: fSAMPLING=fDTS/16, N=5 */
-#define ATIM_CCMR_ICF_FDTSd166    (11)      /* 1011: fSAMPLING=fDTS/16, N=6 */
-#define ATIM_CCMR_ICF_FDTSd168    (12)      /* 1100: fSAMPLING=fDTS/16, N=8 */
-#define ATIM_CCMR_ICF_FDTSd325    (13)      /* 1101: fSAMPLING=fDTS/32, N=5 */
-#define ATIM_CCMR_ICF_FDTSd326    (14)      /* 1110: fSAMPLING=fDTS/32, N=6 */
-#define ATIM_CCMR_ICF_FDTSd328    (15)      /* 1111: fSAMPLING=fDTS/32, N=8 */
-
-/* Capture/compare mode register 2 - Output Compare mode */
-
-#define ATIM_CCMR2_CC3S_SHIFT     (0)       /* Bits 1-0: Capture/Compare 3 Selection */
-#define ATIM_CCMR2_CC3S_MASK      (3 << ATIM_CCMR2_CC3S_SHIFT)
-                                            /* (See common (unshifted) bit field definitions above) */
-#define ATIM_CCMR2_OC3FE          (1 << 2)  /* Bit 2: Output Compare 3 Fast enable */
-#define ATIM_CCMR2_OC3PE          (1 << 3)  /* Bit 3: Output Compare 3 Preload enable */
-#define ATIM_CCMR2_OC3M_SHIFT     (4)       /* Bits 6-4: Output Compare 3 Mode */
-#define ATIM_CCMR2_OC3M_MASK      (7 << ATIM_CCMR2_OC3M_SHIFT)
-                                            /* (See common (unshifted) bit field definitions above) */
-#define ATIM_CCMR2_OC3CE          (1 << 7)  /* Bit 7: Output Compare 3 Clear Enable */
-#define ATIM_CCMR2_CC4S_SHIFT     (8)       /* Bits 9-8: Capture/Compare 4 Selection */
-#define ATIM_CCMR2_CC4S_MASK      (3 << ATIM_CCMR2_CC4S_SHIFT)
-                                            /* (See common (unshifted) bit field definitions above) */
-#define ATIM_CCMR2_OC4FE          (1 << 10) /* Bit 10: Output Compare 4 Fast enable */
-#define ATIM_CCMR2_OC4PE          (1 << 11) /* Bit 11: Output Compare 4 Preload enable */
-#define ATIM_CCMR2_OC4M_SHIFT     (12)      /* Bits 14-12: Output Compare 4 Mode */
-#define ATIM_CCMR2_OC4M_MASK      (7 << ATIM_CCMR2_OC4M_SHIFT)
-                                            /* (See common (unshifted) bit field definitions above) */
-#define ATIM_CCMR2_OC4CE          (1 << 15) /* Bit 15: Output Compare 4 Clear Enable */
-
-/* Capture/compare mode register 2 - Input Capture Mode */
-
-                                            /* Bits 1-0:(same as output compare mode) */
-#define ATIM_CCMR2_IC3PSC_SHIFT   (2)       /* Bits 3-2: Input Capture 3 Prescaler */
-#define ATIM_CCMR1_IC3PSC_MASK    (3 << ATIM_CCMR2_IC3PSC_SHIFT)
-                                            /* (See common (unshifted) bit field definitions above) */
-#define ATIM_CCMR2_IC3F_SHIFT     (4)       /* Bits 7-4: Input Capture 3 Filter */
-#define ATIM_CCMR2_IC3F_MASK      (0x0f << ATIM_CCMR2_IC3F_SHIFT)
-                                            /* (See common (unshifted) bit field definitions above) */
-                                            /* Bits 9:8 (same as output compare mode) */
-#define ATIM_CCMR2_IC4PSC_SHIFT   (10)      /* Bits 11:10: Input Capture 4 Prescaler */
-#define ATIM_CCMR2_IC4PSC_MASK    (3 << ATIM_CCMR2_IC4PSC_SHIFT)
-                                            /* (See common (unshifted) bit field definitions above) */
-#define ATIM_CCMR2_IC4F_SHIFT     (12)      /* Bits 15-12: Input Capture 4 Filter */
-#define ATIM_CCMR2_IC4F_MASK      (0x0f << ATIM_CCMR2_IC4F_SHIFT)
-                                            /* (See common (unshifted) bit field definitions above) */
-
-/* Capture/compare enable register */
-
-#define ATIM_CCER_CC1E            (1 << 0)  /* Bit 0: Capture/Compare 1 output enable */
-#define ATIM_CCER_CC1P            (1 << 1)  /* Bit 1: Capture/Compare 1 output Polarity */
-#define ATIM_CCER_CC1NE           (1 << 2)  /* Bit 2: Capture/Compare 1 Complementary output enable */
-#define ATIM_CCER_CC1NP           (1 << 3)  /* Bit 3: Capture/Compare 1 Complementary output polarity */
-#define ATIM_CCER_CC2E            (1 << 4)  /* Bit 4: Capture/Compare 2 output enable */
-#define ATIM_CCER_CC2P            (1 << 5)  /* Bit 5: Capture/Compare 2 output Polarity */
-#define ATIM_CCER_CC2NE           (1 << 6)  /* Bit 6: Capture/Compare 2 Complementary output enable */
-#define ATIM_CCER_CC2NP           (1 << 7)  /* Bit 7: Capture/Compare 2 Complementary output polarity */
-#define ATIM_CCER_CC3E            (1 << 8)  /* Bit 8: Capture/Compare 3 output enable */
-#define ATIM_CCER_CC3P            (1 << 9)  /* Bit 9: Capture/Compare 3 output Polarity */
-#define ATIM_CCER_CC3NE           (1 << 10) /* Bit 10: Capture/Compare 3 Complementary output enable */
-#define ATIM_CCER_CC3NP           (1 << 11) /* Bit 11: Capture/Compare 3 Complementary output polarity */
-#define ATIM_CCER_CC4E            (1 << 12) /* Bit 12: Capture/Compare 4 output enable */
-#define ATIM_CCER_CC4P            (1 << 13) /* Bit 13: Capture/Compare 4 output Polarity */
-#define ATIM_CCER_CC4NP           (1 << 15) /* Bit 15: Capture/Compare 4 Complementary output polarity */
-
-
-/* 16-bit counter register */
-
-#define ATIM_CNT_SHIFT            (0)       /* Bits 0-15: Timer counter value */
-#define ATIM_CNT_MASK             (0xffff << ATIM_CNT_SHIFT)
-
-/* Repetition counter register */
-
-#define ATIM_RCR_REP_SHIFT        (0)       /* Bits 0-7: Repetition Counter Value */
-#define ATIM_RCR_REP_MASK         (0xff << ATIM_RCR_REP_SHIFT)
-
-#define ATIM_RCR_REP_MAX          128
-
-/* Capture/compare registers (CCR) */
-
-
-#define ATIM_CCR_MASK             (0xffff)
-
-/* Break and dead-time register */
-
-#define ATIM_BDTR_DTG_SHIFT       (0)       /* Bits 7:0 [7:0]: Dead-Time Generator set-up */
-#define ATIM_BDTR_DTG_MASK        (0xff << ATIM_BDTR_DTG_SHIFT)
-#define ATIM_BDTR_LOCK_SHIFT      (8)       /* Bits 9:8 [1:0]: Lock Configuration */
-#define ATIM_BDTR_LOCK_MASK       (3 << ATIM_BDTR_LOCK_SHIFT)
-#  define ATIM_BDTR_LOCKOFF       (0 << ATIM_BDTR_LOCK_SHIFT) /* 00: LOCK OFF - No bit is write protected */
-#  define ATIM_BDTR_LOCK1         (1 << ATIM_BDTR_LOCK_SHIFT) /* 01: LOCK Level 1 protection */
-#  define ATIM_BDTR_LOCK2         (2 << ATIM_BDTR_LOCK_SHIFT) /* 10: LOCK Level 2 protection */
-#  define ATIM_BDTR_LOCK3         (3 << ATIM_BDTR_LOCK_SHIFT) /* 11: LOCK Level 3 protection */ */
-#define ATIM_BDTR_OSSI            (1 << 10) /* Bit 10: Off-State Selection for Idle mode */
-#define ATIM_BDTR_OSSR            (1 << 11) /* Bit 11: Off-State Selection for Run mode */
-#define ATIM_BDTR_BKE             (1 << 12) /* Bit 12: Break enable */
-#define ATIM_BDTR_BKP             (1 << 13) /* Bit 13: Break Polarity */
-#define ATIM_BDTR_AOE             (1 << 14) /* Bit 14: Automatic Output enable */
-#define ATIM_BDTR_MOE             (1 << 15) /* Bit 15: Main Output enable */
-
-/* DMA control register */
-
-#define ATIM_DCR_DBA_SHIFT        (0)       /* Bits 4-0: DMA Base Address */
-#define ATIM_DCR_DBA_MASK         (0x1f << ATIM_DCR_DBA_SHIFT)
-#define ATIM_DCR_DBL_SHIFT        (8)       /* Bits 12-8: DMA Burst Length */
-#define ATIM_DCR_DBL_MASK         (0x1f << ATIM_DCR_DBL_SHIFT)
-#  define ATIM_DCR_DBL(n)         (((n)-1) << ATIM_DCR_DBL_SHIFT) /* n transfers, n = 1..18 */
-
-/* Control register 1 (TIM2-5 and TIM9-14) */
-
-#define GTIM_CR1_CEN              (1 << 0)  /* Bit 0: Counter enable */
-#define GTIM_CR1_UDIS             (1 << 1)  /* Bit 1: Update Disable */
-#define GTIM_CR1_URS              (1 << 2)  /* Bit 2: Update Request Source */
-#define GTIM_CR1_OPM              (1 << 3)  /* Bit 3: One Pulse Mode (TIM2-5, 9, and 12 only) */
-#define GTIM_CR1_DIR              (1 << 4)  /* Bit 4: Direction (TIM2-5 only) */
-#define GTIM_CR1_CMS_SHIFT        (5)       /* Bits 6-5: Center-aligned Mode Selection (TIM2-5 only) */
-#define GTIM_CR1_CMS_MASK         (3 << GTIM_CR1_CMS_SHIFT)
-#  define GTIM_CR1_EDGE           (0 << GTIM_CR1_CMS_SHIFT) /* 00: Edge-aligned mode.  */
-#  define GTIM_CR1_CENTER1        (1 << GTIM_CR1_CMS_SHIFT) /* 01: Center-aligned mode 1 */
-#  define GTIM_CR1_CENTER2        (2 << GTIM_CR1_CMS_SHIFT) /* 10: Center-aligned mode 2 */
-#  define GTIM_CR1_CENTER3        (3 << GTIM_CR1_CMS_SHIFT) /* 11: Center-aligned mode 3 */
-#define GTIM_CR1_ARPE             (1 << 7)  /* Bit 7: Auto-Reload Preload enable */
-#define GTIM_CR1_CKD_SHIFT        (8)       /* Bits 9-8: Clock Division */
-#define GTIM_CR1_CKD_MASK         (3 << GTIM_CR1_CKD_SHIFT)
-#  define GTIM_CR1_TCKINT         (0 << GTIM_CR1_CKD_SHIFT) /* 00: tDTS = tCK_INT */
-#  define GTIM_CR1_2TCKINT        (1 << GTIM_CR1_CKD_SHIFT) /* 01: tDTS = 2 x tCK_INT */
-#  define GTIM_CR1_4TCKINT        (2 << GTIM_CR1_CKD_SHIFT) /* 10: tDTS = 4 x tCK_INT */
-
-/* Control register 2 (TIM2-5, TIM9-12, and TIM15-17 only) */
-
-#define GTIM_CR2_CCPC             (1 << 0)  /* Bit 0: Capture/compare preloaded control (TIM15-17 only) */
-#define GTIM_CR2_CCUS             (1 << 2)  /* Bit 2: Capture/compare control update selection (TIM15-17 only) */
-#define GTIM_CR2_CCDS             (1 << 3)  /* Bit 3: Capture/Compare DMA Selection (TIM2-5,1,&16 only) */
-#define GTIM_CR2_MMS_SHIFT        (4)       /* Bits 6-4: Master Mode Selection (not TIM16) */
-#define GTIM_CR2_MMS_MASK         (7 << GTIM_CR2_MMS_SHIFT)
-#  define GTIM_CR2_MMS_RESET      (0 << GTIM_CR2_MMS_SHIFT) /* 000: Reset */
-#  define GTIM_CR2_MMS_ENABLE     (1 << GTIM_CR2_MMS_SHIFT) /* 001: Enable */
-#  define GTIM_CR2_MMS_UPDATE     (2 << GTIM_CR2_MMS_SHIFT) /* 010: Update */
-#  define GTIM_CR2_MMS_COMPP      (3 << GTIM_CR2_MMS_SHIFT) /* 011: Compare Pulse */
-#  define GTIM_CR2_MMS_OC1REF     (4 << GTIM_CR2_MMS_SHIFT) /* 100: Compare - OC1REF signal is used as trigger output (TRGO) */
-#  define GTIM_CR2_MMS_OC2REF     (5 << GTIM_CR2_MMS_SHIFT) /* 101: Compare - OC2REF signal is used as trigger output (TRGO) */
-#  define GTIM_CR2_MMS_OC3REF     (6 << GTIM_CR2_MMS_SHIFT) /* 110: Compare - OC3REF signal is used as trigger output (TRGO, TIM2-5 and TIM15 only) */
-#  define GTIM_CR2_MMS_OC4REF     (7 << GTIM_CR2_MMS_SHIFT) /* 111: Compare - OC4REF signal is used as trigger output (TRGO, TIM2-5 and TIM15 only) */
-#define GTIM_CR2_TI1S             (1 << 7)  /* Bit 7: TI1 Selection (not TIM16) */
-#define GTIM_CR2_OIS1             (1 << 8)  /* Bit 8: COutput Idle state 1 (OC1 output) (TIM15-17 only) */
-#define GTIM_CR2_OIS1N            (1 << 9)  /* Bit 9: Output Idle state 1 (OC1N output) (TIM15-17 only) */
-#define GTIM_CR2_OIS2             (1 << 10) /* Bit 10: Output idle state 2 (OC2 output) (TIM15 only) */
-
-/* Slave mode control register (TIM2-5 and TIM15 only) */
-
-#define GTIM_SMCR_SMS_SHIFT       (0)       /* Bits 2-0: Slave Mode Selection */
-#define GTIM_SMCR_SMS_MASK        (7 << GTIM_SMCR_SMS_SHIFT)
-#  define GTIM_SMCR_DISAB         (0 << GTIM_SMCR_SMS_SHIFT) /* 000: Slave mode disabled */
-#  define GTIM_SMCR_ENCMD1        (1 << GTIM_SMCR_SMS_SHIFT) /* 001: Encoder mode 1 */
-#  define GTIM_SMCR_ENCMD2        (2 << GTIM_SMCR_SMS_SHIFT) /* 010: Encoder mode 2 */
-#  define GTIM_SMCR_ENCMD3        (3 << GTIM_SMCR_SMS_SHIFT) /* 011: Encoder mode 3 */
-#  define GTIM_SMCR_RESET         (4 << GTIM_SMCR_SMS_SHIFT) /* 100: Reset Mode  */
-#  define GTIM_SMCR_GATED         (5 << GTIM_SMCR_SMS_SHIFT) /* 101: Gated Mode  */
-#  define GTIM_SMCR_TRIGGER       (6 << GTIM_SMCR_SMS_SHIFT) /* 110: Trigger Mode */
-#  define GTIM_SMCR_EXTCLK1       (7 << GTIM_SMCR_SMS_SHIFT) /* 111: External Clock Mode 1 */
-#define GTIM_SMCR_TS_SHIFT        (4)       /* Bits 6-4: Trigger Selection */
-#define GTIM_SMCR_TS_MASK         (7 << GTIM_SMCR_TS_SHIFT)
-#  define GTIM_SMCR_ITR0          (0 << GTIM_SMCR_TS_SHIFT) /* 000: Internal Trigger 0 (ITR0). TIM1 */
-#  define GTIM_SMCR_ITR1          (1 << GTIM_SMCR_TS_SHIFT) /* 001: Internal Trigger 1 (ITR1). TIM2 */
-#  define GTIM_SMCR_ITR2          (2 << GTIM_SMCR_TS_SHIFT) /* 010: Internal Trigger 2 (ITR2). TIM3 */
-#  define GTIM_SMCR_ITR3          (3 << GTIM_SMCR_TS_SHIFT) /* 011: Internal Trigger 3 (ITR3). TIM4 */
-#  define GTIM_SMCR_TI1FED        (4 << GTIM_SMCR_TS_SHIFT) /* 100: TI1 Edge Detector (TI1F_ED) */
-#  define GTIM_SMCR_TI1FP1        (5 << GTIM_SMCR_TS_SHIFT) /* 101: Filtered Timer Input 1 (TI1FP1) */
-#  define GTIM_SMCR_TI2FP2        (6 << GTIM_SMCR_TS_SHIFT) /* 110: Filtered Timer Input 2 (TI2FP2) */
-#  define GTIM_SMCR_ETRF          (7 << GTIM_SMCR_TS_SHIFT) /* 111: External Trigger input (ETRF) */
-#define GTIM_SMCR_MSM             (1 << 7)  /* Bit 7: Master/Slave mode */
-#define GTIM_SMCR_ETF_SHIFT       (8)       /* Bits 11-8: External Trigger Filter (not TIM15) */
-#define GTIM_SMCR_ETF_MASK        (0x0f << GTIM_SMCR_ETF_SHIFT)
-#  define GTIM_SMCR_NOFILT        (0 << GTIM_SMCR_ETF_SHIFT)  /* 0000: No filter, sampling is done at fDTS */
-#  define GTIM_SMCR_FCKINT2       (1 << GTIM_SMCR_ETF_SHIFT)  /* 0001: fSAMPLING=fCK_INT, N=2 */
-#  define GTIM_SMCR_FCKINT4       (2 << GTIM_SMCR_ETF_SHIFT)  /* 0010: fSAMPLING=fCK_INT, N=4 */
-#  define GTIM_SMCR_FCKINT8       (3 << GTIM_SMCR_ETF_SHIFT)  /* 0011: fSAMPLING=fCK_INT, N=8 */
-#  define GTIM_SMCR_FDTSd26       (4 << GTIM_SMCR_ETF_SHIFT)  /* 0100: fSAMPLING=fDTS/2, N=6 */
-#  define GTIM_SMCR_FDTSd28       (5 << GTIM_SMCR_ETF_SHIFT)  /* 0101: fSAMPLING=fDTS/2, N=8 */
-#  define GTIM_SMCR_FDTSd36       (6 << GTIM_SMCR_ETF_SHIFT)  /* 0110: fSAMPLING=fDTS/4, N=6 */
-#  define GTIM_SMCR_FDTSd38       (7 << GTIM_SMCR_ETF_SHIFT)  /* 0111: fSAMPLING=fDTS/4, N=8 */
-#  define GTIM_SMCR_FDTSd86       (8 << GTIM_SMCR_ETF_SHIFT)  /* 1000: fSAMPLING=fDTS/8, N=6 */
-#  define GTIM_SMCR_FDTSd88       (9 << GTIM_SMCR_ETF_SHIFT)  /* 1001: fSAMPLING=fDTS/8, N=8 */
-#  define GTIM_SMCR_FDTSd165      (10 << GTIM_SMCR_ETF_SHIFT) /* 1010: fSAMPLING=fDTS/16, N=5 */
-#  define GTIM_SMCR_FDTSd166      (11 << GTIM_SMCR_ETF_SHIFT) /* 1011: fSAMPLING=fDTS/16, N=6 */
-#  define GTIM_SMCR_FDTSd168      (12 << GTIM_SMCR_ETF_SHIFT) /* 1100: fSAMPLING=fDTS/16, N=8 */
-#  define GTIM_SMCR_FDTSd325      (13 << GTIM_SMCR_ETF_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */
-#  define GTIM_SMCR_FDTSd326      (14 << GTIM_SMCR_ETF_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */
-#  define GTIM_SMCR_FDTSd328      (15 << GTIM_SMCR_ETF_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */
-#define GTIM_SMCR_ETPS_SHIFT      (12)      /* Bits 13-12: External Trigger Prescaler (not TIM15) */
-#define GTIM_SMCR_ETPS_MASK       (3 << GTIM_SMCR_ETPS_SHIFT)
-#  define GTIM_SMCR_PSCOFF        (0 << GTIM_SMCR_ETPS_SHIFT) /* 00: Prescaler OFF */
-#  define GTIM_SMCR_ETRPd2        (1 << GTIM_SMCR_ETPS_SHIFT) /* 01: ETRP frequency divided by 2 */
-#  define GTIM_SMCR_ETRPd4        (2 << GTIM_SMCR_ETPS_SHIFT) /* 10: ETRP frequency divided by 4 */
-#  define GTIM_SMCR_ETRPd8        (3 << GTIM_SMCR_ETPS_SHIFT) /* 11: ETRP frequency divided by 8 */
-#define GTIM_SMCR_ECE             (1 << 14) /* Bit 14: External Clock enable */
-#define GTIM_SMCR_ETP             (1 << 15) /* Bit 15: External Trigger Polarity */
-
-/* DMA/Interrupt enable register (TIM2-5 and TIM9-14) */
-
-#define GTIM_DIER_UIE             (1 << 0)  /* Bit 0: Update interrupt enable */
-#define GTIM_DIER_CC1IE           (1 << 1)  /* Bit 1: Capture/Compare 1 interrupt enable */
-#define GTIM_DIER_CC2IE           (1 << 2)  /* Bit 2: Capture/Compare 2 interrupt enable (TIM2-5,9,12,&15 only) */
-#define GTIM_DIER_CC3IE           (1 << 3)  /* Bit 3: Capture/Compare 3 interrupt enable (TIM2-5 only) */
-#define GTIM_DIER_CC4IE           (1 << 4)  /* Bit 4: Capture/Compare 4 interrupt enable (TIM2-5 only) */
-#define GTIM_DIER_COMIE           (1 << 5)  /* Bit 5: COM interrupt enable (TIM15-17 only) */
-#define GTIM_DIER_TIE             (1 << 6)  /* Bit 6: Trigger interrupt enable (TIM2-5,9,&12 only) */
-#define GTIM_DIER_BIE             (1 << 7)  /* Bit 7: Break interrupt enable (TIM15-17 only) */
-#define GTIM_DIER_UDE             (1 << 8)  /* Bit 8: Update DMA request enable (TIM2-5&15-17 only) */
-#define GTIM_DIER_CC1DE           (1 << 9)  /* Bit 9: Capture/Compare 1 DMA request enable (TIM2-5&15-17 only) */
-#define GTIM_DIER_CC2DE           (1 << 10) /* Bit 10: Capture/Compare 2 DMA request enable (TIM2-5&15 only) */
-#define GTIM_DIER_CC3DE           (1 << 11) /* Bit 11: Capture/Compare 3 DMA request enable (TIM2-5 only) */
-#define GTIM_DIER_CC4DE           (1 << 12) /* Bit 12: Capture/Compare 4 DMA request enable (TIM2-5 only) */
-#define GTIM_DIER_COMDE           (1 << 13) /* Bit 13: COM DMA request enable (TIM15-17 only) */
-#define GTIM_DIER_TDE             (1 << 14) /* Bit 14: Trigger DMA request enable (TIM2-5&15-17 only) */
-
-/* Status register */
-
-#define GTIM_SR_UIF               (1 << 0)  /* Bit 0: Update interrupt flag */
-#define GTIM_SR_CC1IF             (1 << 1)  /* Bit 1: Capture/compare 1 interrupt flag */
-#define GTIM_SR_CC2IF             (1 << 2)  /* Bit 2: Capture/Compare 2 interrupt flag (TIM2-5,9,12,&15 only) */
-#define GTIM_SR_CC3IF             (1 << 3)  /* Bit 3: Capture/Compare 3 interrupt flag (TIM2-5 only) */
-#define GTIM_SR_CC4IF             (1 << 4)  /* Bit 4: Capture/Compare 4 interrupt flag (TIM2-5 only) */
-#define GTIM_SR_COMIF             (1 << 5)  /* Bit 5: COM interrupt flag (TIM15-17 only) */
-#define GTIM_SR_TIF               (1 << 6)  /* Bit 6: Trigger interrupt Flag (TIM2-5,9,12&15-17 only) */
-#define GTIM_SR_BIF               (1 << 7)  /* Bit 7: Break interrupt flag (TIM15-17 only) */
-#define GTIM_SR_CC1OF             (1 << 9)  /* Bit 9: Capture/Compare 1 Overcapture flag */
-#define GTIM_SR_CC2OF             (1 << 10) /* Bit 10: Capture/Compare 2 Overcapture flag (TIM2-5,9,12&15 only) */
-#define GTIM_SR_CC3OF             (1 << 11) /* Bit 11: Capture/Compare 3 Overcapture flag (TIM2-5 only) */
-#define GTIM_SR_CC4OF             (1 << 12) /* Bit 12: Capture/Compare 4 Overcapture flag (TIM2-5 only) */
-
-/* Event generation register (TIM2-5 and TIM9-14) */
-
-#define GTIM_EGR_UG               (1 << 0)  /* Bit 0: Update generation */
-#define GTIM_EGR_CC1G             (1 << 1)  /* Bit 1: Capture/compare 1 generation */
-#define GTIM_EGR_CC2G             (1 << 2)  /* Bit 2: Capture/compare 2 generation (TIM2-5,9,12,&15 only) */
-#define GTIM_EGR_CC3G             (1 << 3)  /* Bit 3: Capture/compare 3 generation (TIM2-5 only) */
-#define GTIM_EGR_CC4G             (1 << 4)  /* Bit 4: Capture/compare 4 generation (TIM2-5 only) */
-#define GTIM_EGR_COMIG            (1 << 5)  /* Bit 5: Capture/Compare control update generation (TIM15-17 only) */
-#define GTIM_EGR_TG               (1 << 6)  /* Bit 6: Trigger generation (TIM2-5,9,12&16-17 only) */
-#define GTIM_EGR_BG               (1 << 7)  /* Bit 7: Break generation (TIM15-17 only) */
-
-/* Capture/compare mode register 1 - Output compare mode (TIM2-5 and TIM9-14) */
-
-#define GTIM_CCMR1_CC1S_SHIFT     (0)       /* Bits 1-0: Capture/Compare 1 Selection */
-#define GTIM_CCMR1_CC1S_MASK      (3 << GTIM_CCMR1_CC1S_SHIFT)
-                                            /* (See common CCMR Capture/Compare Selection definitions below) */
-#define GTIM_CCMR1_OC1FE          (1 << 2)  /* Bit 2: Output Compare 1 Fast enable */
-#define GTIM_CCMR1_OC1PE          (1 << 3)  /* Bit 3: Output Compare 1 Preload enable */
-#define GTIM_CCMR1_OC1M_SHIFT     (4)       /* Bits 6-4: Output Compare 1 Mode */
-#define GTIM_CCMR1_OC1M_MASK      (7 << GTIM_CCMR1_OC1M_SHIFT)
-                                            /* (See common CCMR Output Compare Mode definitions below) */
-#define GTIM_CCMR1_OC1CE          (1 << 7)  /* Bit 7: Output Compare 1Clear Enable */
-#define GTIM_CCMR1_CC2S_SHIFT     (8)       /* Bits 9-8: Capture/Compare 2 Selection */
-#define GTIM_CCMR1_CC2S_MASK      (3 << GTIM_CCMR1_CC2S_SHIFT)
-                                            /* (See common CCMR Capture/Compare Selection definitions below) */
-#define GTIM_CCMR1_OC2FE          (1 << 10) /* Bit 10: Output Compare 2 Fast enable */
-#define GTIM_CCMR1_OC2PE          (1 << 11) /* Bit 11: Output Compare 2 Preload enable */
-#define GTIM_CCMR1_OC2M_SHIFT     (12)      /* Bits 14-12: Output Compare 2 Mode */
-#define GTIM_CCMR1_OC2M_MASK      (7 << GTIM_CCMR1_OC2M_SHIFT)
-                                            /* (See common CCMR Output Compare Mode definitions below) */
-#define GTIM_CCMR1_OC2CE          (1 << 15) /* Bit 15: Output Compare 2 Clear Enable */
-
-/* Common CCMR (unshifted) Capture/Compare Selection bit-field definitions */
-
-#define GTIM_CCMR_CCS_CCOUT       (0)       /* 00: CCx channel output */
-#define GTIM_CCMR_CCS_CCIN1       (1)       /* 01: CCx channel input, ICx is TIx */
-#define GTIM_CCMR_CCS_CCIN2       (2)       /* 10: CCx channel input, ICx is TIy */
-#define GTIM_CCMR_CCS_CCINTRC     (3)       /* 11: CCx channel input, ICx is TRC */
-
-/* Common CCMR (unshifted) Compare Mode bit field definitions */
-
-#define GTIM_CCMR_MODE_FRZN       (0)       /* 000: Frozen */
-#define GTIM_CCMR_MODE_CHACT      (1)       /* 001: Channel x active on match */
-#define GTIM_CCMR_MODE_CHINACT    (2)       /* 010: Channel x inactive on match */
-#define GTIM_CCMR_MODE_OCREFTOG   (3)       /* 011: OCxREF toggle ATIM_CNT=ATIM_CCRx */
-#define GTIM_CCMR_MODE_OCREFLO    (4)       /* 100: OCxREF forced low */
-#define GTIM_CCMR_MODE_OCREFHI    (5)       /* 101: OCxREF forced high */
-#define GTIM_CCMR_MODE_PWM1       (6)       /* 110: PWM mode 1 */
-#define GTIM_CCMR_MODE_PWM2       (7)       /* 111: PWM mode 2 */
-
-/* Capture/compare mode register 1 - Input capture mode (TIM2-5 and TIM9-14) */
-
-                                            /* Bits 1-0 (Same as Output Compare Mode) */
-#define GTIM_CCMR1_IC1PSC_SHIFT   (2)       /* Bits 3-2: Input Capture 1 Prescaler */
-#define GTIM_CCMR1_IC1PSC_MASK    (3 << GTIM_CCMR1_IC1PSC_SHIFT)
-                                            /* (See common CCMR Input Capture Prescaler definitions below) */
-#define GTIM_CCMR1_IC1F_SHIFT     (4)       /* Bits 7-4: Input Capture 1 Filter */
-#define GTIM_CCMR1_IC1F_MASK      (0x0f << GTIM_CCMR1_IC1F_SHIFT)
-                                            /* (See common CCMR Input Capture Filter definitions below) */
-                                            /* Bits 9-8: (Same as Output Compare Mode) */
-#define GTIM_CCMR1_IC2PSC_SHIFT   (10)      /* Bits 11-10: Input Capture 2 Prescaler */
-#define GTIM_CCMR1_IC2PSC_MASK    (3 << GTIM_CCMR1_IC2PSC_SHIFT)
-                                            /* (See common CCMR Input Capture Prescaler definitions below) */
-#define GTIM_CCMR1_IC2F_SHIFT     (12)      /* Bits 15-12: Input Capture 2 Filter */
-#define GTIM_CCMR1_IC2F_MASK      (0x0f << GTIM_CCMR1_IC2F_SHIFT)
-                                            /* (See common CCMR Input Capture Filter definitions below) */
-
-/* Common CCMR (unshifted) Input Capture Prescaler bit-field definitions */
-
-#define GTIM_CCMR_ICPSC_NOPSC     (0)       /* 00: no prescaler, capture each edge */
-#define GTIM_CCMR_ICPSC_EVENTS2   (1)       /* 01: capture once every 2 events */
-#define GTIM_CCMR_ICPSC_EVENTS4   (2)       /* 10: capture once every 4 events */
-#define GTIM_CCMR_ICPSC_EVENTS8   (3)       /* 11: capture once every 8 events */
-
-/* Common CCMR (unshifted) Input Capture Filter bit-field definitions */
-
-#define GTIM_CCMR_ICF_NOFILT      (0)       /* 0000: No filter, sampling at fDTS */
-#define GTIM_CCMR_ICF_FCKINT2     (1)       /* 0001: fSAMPLING=fCK_INT, N=2 */
-#define GTIM_CCMR_ICF_FCKINT4     (2)       /* 0010: fSAMPLING=fCK_INT, N=4 */
-#define GTIM_CCMR_ICF_FCKINT8     (3)       /* 0011: fSAMPLING=fCK_INT, N=8 */
-#define GTIM_CCMR_ICF_FDTSd26     (4)       /* 0100: fSAMPLING=fDTS/2, N=6 */
-#define GTIM_CCMR_ICF_FDTSd28     (5)       /* 0101: fSAMPLING=fDTS/2, N=8 */
-#define GTIM_CCMR_ICF_FDTSd46     (6)       /* 0110: fSAMPLING=fDTS/4, N=6 */
-#define GTIM_CCMR_ICF_FDTSd48     (7)       /* 0111: fSAMPLING=fDTS/4, N=8 */
-#define GTIM_CCMR_ICF_FDTSd86     (8)       /* 1000: fSAMPLING=fDTS/8, N=6 */
-#define GTIM_CCMR_ICF_FDTSd88     (9)       /* 1001: fSAMPLING=fDTS/8, N=8 */
-#define GTIM_CCMR_ICF_FDTSd165    (10)      /* 1010: fSAMPLING=fDTS/16, N=5 */
-#define GTIM_CCMR_ICF_FDTSd166    (11)      /* 1011: fSAMPLING=fDTS/16, N=6 */
-#define GTIM_CCMR_ICF_FDTSd168    (12)      /* 1100: fSAMPLING=fDTS/16, N=8 */
-#define GTIM_CCMR_ICF_FDTSd325    (13)      /* 1101: fSAMPLING=fDTS/32, N=5 */
-#define GTIM_CCMR_ICF_FDTSd326    (14)      /* 1110: fSAMPLING=fDTS/32, N=6 */
-#define GTIM_CCMR_ICF_FDTSd328    (15)      /* 1111: fSAMPLING=fDTS/32, N=8 */
-
-/* Capture/compare mode register 2 - Output Compare mode (TIM2-5 only) */
-
-#define GTIM_CCMR2_CC3S_SHIFT     (0)       /* Bits 1-0: Capture/Compare 3 Selection */
-#define GTIM_CCMR2_CC3S_MASK      (3 << GTIM_CCMR2_CC3S_SHIFT)
-                                            /* (See common CCMR Capture/Compare Selection definitions above) */
-#define GTIM_CCMR2_OC3FE          (1 << 2)  /* Bit 2: Output Compare 3 Fast enable */
-#define GTIM_CCMR2_OC3PE          (1 << 3)  /* Bit 3: Output Compare 3 Preload enable */
-#define GTIM_CCMR2_OC3M_SHIFT     (4)       /* Bits 6-4: Output Compare 3 Mode */
-#define GTIM_CCMR2_OC3M_MASK      (7 << GTIM_CCMR2_OC3M_SHIFT)
-                                            /* (See common CCMR Output Compare Mode definitions above) */
-#define GTIM_CCMR2_OC3CE          (1 << 7)  /* Bit 7: Output Compare 3 Clear Enable */
-#define GTIM_CCMR2_CC4S_SHIFT     (8)       /* Bits 9-8: Capture/Compare 4 Selection */
-#define GTIM_CCMR2_CC4S_MASK      (3 << GTIM_CCMR2_CC4S_SHIFT)
-                                            /* (See common CCMR Capture/Compare Selection definitions above) */
-#define GTIM_CCMR2_OC4FE          (1 << 10) /* Bit 10: Output Compare 4 Fast enable */
-#define GTIM_CCMR2_OC4PE          (1 << 11) /* Bit 11: Output Compare 4 Preload enable */
-#define GTIM_CCMR2_OC4M_SHIFT     (12)      /* Bits 14-12: Output Compare 4 Mode */
-#define GTIM_CCMR2_OC4M_MASK      (7 << GTIM_CCMR2_OC4M_SHIFT)
-                                            /* (See common CCMR Output Compare Mode definitions above) */
-#define GTIM_CCMR2_OC4CE          (1 << 15) /* Bit 15: Output Compare 4 Clear Enable */
-
-/* Capture/compare mode register 2 - Input capture mode (TIM2-5 only) */
-
-                                            /* Bits 1-0 (Same as Output Compare Mode) */
-#define GTIM_CCMR2_IC3PSC_SHIFT   (2)       /* Bits 3-2: Input Capture 3 Prescaler */
-#define GTIM_CCMR2_IC3PSC_MASK    (3 << GTIM_CCMR2_IC3PSC_SHIFT)
-                                            /* (See common CCMR Input Capture Prescaler definitions below) */
-#define GTIM_CCMR2_IC3F_SHIFT     (4)       /* Bits 7-4: Input Capture 3 Filter */
-#define GTIM_CCMR2_IC3F_MASK      (0x0f << GTIM_CCMR2_IC3F_SHIFT)
-                                            /* (See common CCMR Input Capture Filter definitions below) */
-                                            /* Bits 9-8: (Same as Output Compare Mode) */
-#define GTIM_CCMR2_IC4PSC_SHIFT   (10)      /* Bits 11-10: Input Capture 4 Prescaler */
-#define GTIM_CCMR2_IC4PSC_MASK    (3 << GTIM_CCMR2_IC4PSC_SHIFT)
-                                            /* (See common CCMR Input Capture Prescaler definitions below) */
-#define GTIM_CCMR2_IC4F_SHIFT     (12)      /* Bits 15-12: Input Capture 4 Filter */
-#define GTIM_CCMR2_IC4F_MASK      (0x0f << GTIM_CCMR2_IC4F_SHIFT)
-                                            /* (See common CCMR Input Capture Filter definitions below) */
-
-/* Capture/compare enable register (TIM1 and TIM8, TIM2-5 and TIM9-14) */
-
-#define GTIM_CCER_CC1E            (1 << 0)  /* Bit 0: Capture/Compare 1 output enable */
-#define GTIM_CCER_CC1P            (1 << 1)  /* Bit 1: Capture/Compare 1 output polarity */
-#define GTIM_CCER_CC1NE           (1 << 2)  /* Bit 2: Capture/Compare 1 complementary output enable (TIM1 and TIM8 only) */
-#define GTIM_CCER_CC1NP           (1 << 3)  /* Bit 3: Capture/Compare 1 output Polarity (F2,F3,F4 and TIM15-17) */
-#define GTIM_CCER_CC2E            (1 << 4)  /* Bit 4: Capture/Compare 2 output enable (TIM2-5,9&12 only) */
-#define GTIM_CCER_CC2P            (1 << 5)  /* Bit 5: Capture/Compare 2 output polarity (TIM2-5,9&12 only) */
-#define GTIM_CCER_CC2NE           (1 << 6)  /* Bit 6: Capture/Compare 2 complementary output enable (TIM1 and TIM8 only) */
-#define GTIM_CCER_CC2NP           (1 << 7)  /* Bit 7: Capture/Compare 2 output Polarity (F2,F3,F4 and TIM2-5,9,12&15 only) */
-#define GTIM_CCER_CC3E            (1 << 8)  /* Bit 8: Capture/Compare 3 output enable (TIM2-5 only) */
-#define GTIM_CCER_CC3P            (1 << 9)  /* Bit 9: Capture/Compare 3 output Polarity (TIM2-5 only) */
-#define GTIM_CCER_CC3NE           (1 << 10) /* Bit 10: Capture/Compare 3 complementary output enable (TIM1 and TIM8 only) */
-#define GTIM_CCER_CC3NP           (1 << 11) /* Bit 11: Capture/Compare 3 output Polarity (F2,F4 and TIM2-5 only) */
-#define GTIM_CCER_CC4E            (1 << 12) /* Bit 12: Capture/Compare 4 output enable (TIM2-5 only) */
-#define GTIM_CCER_CC4P            (1 << 13) /* Bit 13: Capture/Compare 4 output Polarity (TIM2-5 only) */
-#define GTIM_CCER_CC4NP           (1 << 15) /* Bit 15: Capture/Compare 4 output Polarity */
-
-/* 16-bit counter register */
-
-#define GTIM_CNT_SHIFT            (0)       /* Bits 0-15: Timer counter value */
-#define GTIM_CNT_MASK             (0xffff << ATIM_CNT_SHIFT)
-
-/* Repitition counter (TIM15-17 only) */
-
-#define GTIM_RCR_REP_SHIFT        (0)       /* Bits 0-7: Repetition Counter Value */
-#define GTIM_RCR_REP_MASK         (0xff << GTIM_RCR_REP_SHIFT)
-
-#define GTIM_RCR_REP_MAX          128
-
-/* Break and dead-time register (TIM15-17 only */
-
-#define GTIM_BDTR_DTG_SHIFT       (0)       /* Bits 7:0 [7:0]: Dead-Time Generator set-up */
-#define GTIM_BDTR_DTG_MASK        (0xff << GTIM_BDTR_DTG_SHIFT)
-#define GTIM_BDTR_LOCK_SHIFT      (8)       /* Bits 9:8 [1:0]: Lock Configuration */
-#define GTIM_BDTR_LOCK_MASK       (3 << GTIM_BDTR_LOCK_SHIFT)
-#  define GTIM_BDTR_LOCKOFF       (0 << GTIM_BDTR_LOCK_SHIFT) /* 00: LOCK OFF - No bit is write protected */
-#  define GTIM_BDTR_LOCK1         (1 << GTIM_BDTR_LOCK_SHIFT) /* 01: LOCK Level 1 protection */
-#  define GTIM_BDTR_LOCK2         (2 << GTIM_BDTR_LOCK_SHIFT) /* 10: LOCK Level 2 protection */
-#  define GTIM_BDTR_LOCK3         (3 << GTIM_BDTR_LOCK_SHIFT) /* 11: LOCK Level 3 protection */ */
-#define GTIM_BDTR_OSSI            (1 << 10) /* Bit 10: Off-State Selection for Idle mode */
-#define GTIM_BDTR_OSSR            (1 << 11) /* Bit 11: Off-State Selection for Run mode */
-#define GTIM_BDTR_BKE             (1 << 12) /* Bit 12: Break enable */
-#define GTIM_BDTR_BKP             (1 << 13) /* Bit 13: Break Polarity */
-#define GTIM_BDTR_AOE             (1 << 14) /* Bit 14: Automatic Output enable */
-#define GTIM_BDTR_MOE             (1 << 15) /* Bit 15: Main Output enable */
-#define GTIM_BDTR_BKF_SHIFT       (16)      /* Bits 16-19: Break filter */
-#define GTIM_BDTR_BKF_MASK        (15 << GTIM_BDTR_BKF_SHIFT)
-#  define GTIM_BDTR_BKF_NOFILT    (0 << GTIM_BDTR_BKF_SHIFT)   /* 0000: No filter, BRK acts asynchronously */
-#  define GTIM_BDTR_BKF_FCKINT2   (1 << GTIM_BDTR_BKF_SHIFT)   /* 0001: fSAMPLING=fCK_INT, N=2 */
-#  define GTIM_BDTR_BKF_FCKINT4   (2 << GTIM_BDTR_BKF_SHIFT)   /* 0010: fSAMPLING=fCK_INT, N=4 */
-#  define GTIM_BDTR_BKF_FCKINT8   (3 << GTIM_BDTR_BKF_SHIFT)   /* 0011: fSAMPLING=fCK_INT, N=8 */
-#  define GTIM_BDTR_BKF_FDTSd26   (4 << GTIM_BDTR_BKF_SHIFT)   /* 0100: fSAMPLING=fDTS/2, N=6 */
-#  define GTIM_BDTR_BKF_FDTSd28   (5 << GTIM_BDTR_BKF_SHIFT)   /* 0101: fSAMPLING=fDTS/2, N=8 */
-#  define GTIM_BDTR_BKF_FDTSd36   (6 << GTIM_BDTR_BKF_SHIFT)   /* 0110: fSAMPLING=fDTS/4, N=6 */
-#  define GTIM_BDTR_BKF_FDTSd38   (7 << GTIM_BDTR_BKF_SHIFT)   /* 0111: fSAMPLING=fDTS/4, N=8 */
-#  define GTIM_BDTR_BKF_FDTSd86   (8 << GTIM_BDTR_BKF_SHIFT)   /* 1000: fSAMPLING=fDTS/8, N=6 */
-#  define GTIM_BDTR_BKF_FDTSd88   (9 << GTIM_BDTR_BKF_SHIFT)   /* 1001: fSAMPLING=fDTS/8, N=8 */
-#  define GTIM_BDTR_BKF_FDTSd165  (10 << GTIM_BDTR_BKF_SHIFT)  /* 1010: fSAMPLING=fDTS/16, N=5 */
-#  define GTIM_BDTR_BKF_FDTSd166  (11 << GTIM_BDTR_BKF_SHIFT)  /* 1011: fSAMPLING=fDTS/16, N=6 */
-#  define GTIM_BDTR_BKF_FDTSd168  (12 << GTIM_BDTR_BKF_SHIFT)  /* 1100: fSAMPLING=fDTS/16, N=8 */
-#  define GTIM_BDTR_BKF_FDTSd325  (13 << GTIM_BDTR_BKF_SHIFT)  /* 1101: fSAMPLING=fDTS/32, N=5 */
-#  define GTIM_BDTR_BKF_FDTSd326  (14 << GTIM_BDTR_BKF_SHIFT)  /* 1110: fSAMPLING=fDTS/32, N=6 */
-#  define GTIM_BDTR_BKF_FDTSd328  (15 << GTIM_BDTR_BKF_SHIFT)  /* 1111: fSAMPLING=fDTS/32, N=8 */
-
-/* DMA control register */
-
-#define GTIM_DCR_DBA_SHIFT        (0)       /* Bits 4-0: DMA Base Address */
-#define GTIM_DCR_DBA_MASK         (0x1f << GTIM_DCR_DBA_SHIFT)
-#define GTIM_DCR_DBL_SHIFT        (8)       /* Bits 12-8: DMA Burst Length */
-#define GTIM_DCR_DBL_MASK         (0x1f << GTIM_DCR_DBL_SHIFT)
-
-/* Timer 2/5 option register */
-
-#  define TIM2_OR_ITR1_RMP_SHIFT  (10)     /* Bits 10-11: Internal trigger 1 remap */
-#  define TIM2_OR_ITR1_RMP_MASK   (3 << TIM2_OR_ITR1_RMP_SHIFT)
-#    define TIM2_OR_ITR1_TIM8_TRGOUT (0 << TIM2_OR_ITR1_RMP_SHIFT) /* 00: TIM2_ITR1 input connected to TIM8_TRGOUT */
-#    define TIM2_OR_ITR1_PTP      (1 << TIM2_OR_ITR1_RMP_SHIFT) /* 01: TIM2_ITR1 input connected to PTP trigger output */
-#    define TIM2_OR_ITR1_OTGFSSOF (2 << TIM2_OR_ITR1_RMP_SHIFT) /* 10: TIM2_ITR1 input connected to OTG FS SOF */
-#    define TIM2_OR_ITR1_OTGHSSOF (3 << TIM2_OR_ITR1_RMP_SHIFT) /* 11: TIM2_ITR1 input connected to OTG HS SOF */
-
-#  define TIM5_OR_TI4_RMP_SHIFT   (6)     /* Bits 6-7: Internal trigger 4 remap */
-#  define TIM5_OR_TI4_RMP_MASK    (3 << TIM5_OR_TI4_RMP_SHIFT)
-#    define TIM5_OR_TI4_GPIO      (0 << TIM5_OR_TI4_RMP_SHIFT) /* 00: TIM5_CH4 input connected to GPIO */
-#    define TIM5_OR_TI4_LSI       (1 << TIM5_OR_TI4_RMP_SHIFT) /* 01: TIM5_CH4 input connected to LSI internal clock */
-#    define TIM5_OR_TI4_LSE       (2 << TIM5_OR_TI4_RMP_SHIFT) /* 10: TIM5_CH4 input connected to LSE internal clock */
-#    define TIM5_OR_TI4_RTC       (3 << TIM5_OR_TI4_RMP_SHIFT) /* 11: TIM5_CH4 input connected to RTC output event */
-
-#  define TIM11_OR_TI1_RMP_SHIFT  (6)     /* Bits 6-7: Internal trigger 4 remap */
-#  define TIM11_OR_TI1_RMP_MASK   (3 << TIM11_OR_TI1_RMP_SHIFT)
-#    define TIM11_OR_TI1_GPIO     (0 << TIM11_OR_TI1_RMP_SHIFT) /* 00-11: TIM11_CH1 input connected to GPIO */
-#    define TIM11_OR_TI1_HSERTC   (3 << TIM11_OR_TI1_RMP_SHIFT) /* 11: TIM11_CH1 input connected to HSE_RTC clock */
-
-
-/* Control register 1 */
-
-#define BTIM_CR1_CEN              (1 << 0)  /* Bit 0: Counter enable */
-#define BTIM_CR1_UDIS             (1 << 1)  /* Bit 1: Update Disable */
-#define BTIM_CR1_URS              (1 << 2)  /* Bit 2: Update Request Source */
-#define BTIM_CR1_OPM              (1 << 3)  /* Bit 3: One Pulse Mode */
-#define BTIM_CR1_ARPE             (1 << 7)  /* Bit 7: Auto-Reload Preload enable */
-
-/* Control register 2 */
-
-#define BTIM_CR2_MMS_SHIFT        (4)       /* Bits 6-4: Master Mode Selection */
-#define BTIM_CR2_MMS_MASK         (7 << BTIM_CR2_MMS_SHIFT)
-#  define BTIM_CR2_RESET          (0 << BTIM_CR2_MMS_SHIFT) /* 000: Reset */
-#  define BTIM_CR2_ENAB           (1 << BTIM_CR2_MMS_SHIFT) /* 001: Enable */
-#  define BTIM_CR2_UPDT           (2 << BTIM_CR2_MMS_SHIFT) /* 010: Update */
-
-/* DMA/Interrupt enable register */
-
-#define BTIM_DIER_UIE             (1 << 0)  /* Bit 0: Update interrupt enable */
-#define BTIM_DIER_UDE             (1 << 8)  /* Bit 8: Update DMA request enable */
-
-/* Status register */
-
-#define BTIM_SR_UIF               (1 << 0)  /* Bit 0: Update interrupt flag */
-
-/* Event generation register */
-
-#define BTIM_EGR_UG               (1 << 0)  /* Bit 0: Update generation */
-
 #endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32_TIM_H */
diff --git a/arch/arm/src/stm32f7/chip/stm32_uart.h b/arch/arm/src/stm32f7/chip/stm32_uart.h
index 89177c89876..7669c675cc3 100644
--- a/arch/arm/src/stm32f7/chip/stm32_uart.h
+++ b/arch/arm/src/stm32f7/chip/stm32_uart.h
@@ -1,6 +1,7 @@
 /************************************************************************************
  * arch/arm/src/stm32f7/chip/stm32_uart.h
  *
+ *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt <gnutt@nuttx.org>
  *            David Sidrane <david_s5@nscdg.com>
  *
diff --git a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_i2c.h b/arch/arm/src/stm32f7/chip/stm32f74xx75xx_i2c.h
deleted file mode 100644
index 17c8012fdd3..00000000000
--- a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_i2c.h
+++ /dev/null
@@ -1,249 +0,0 @@
-/************************************************************************************
- * arch/arm/src/stm32f7/chip/stm32f74xx75xx_i2c.h
- *
- *   Copyright (C) 2009, 2011, 2013 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_STM32F7_STM32F74XX75XX_I2C_H
-#define __ARCH_ARM_SRC_STM32F7_STM32F74XX75XX_I2C_H
-
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
-/* Register Offsets *****************************************************************/
-
-#define STM32F7_I2C_CR1_OFFSET      0x0000 /* Control register 1 (32-bit) */
-#define STM32F7_I2C_CR2_OFFSET      0x0004 /* Control register 2 (32-bit) */
-#define STM32F7_I2C_OAR1_OFFSET     0x0008 /* Own address register 1 (16-bit) */
-#define STM32F7_I2C_OAR2_OFFSET     0x000c /* Own address register 2 (16-bit) */
-#define STM32F7_I2C_TIMINGR_OFFSET  0x0010 /* Timing register */
-#define STM32F7_I2C_TIMEOUTR_OFFSET 0x0014 /* Timeout register */
-#define STM32F7_I2C_ISR_OFFSET      0x0018 /* Interrupt and Status register */
-#define STM32F7_I2C_ICR_OFFSET      0x001c /* Interrupt clear register */
-#define STM32F7_I2C_PECR_OFFSET     0x0020 /* Packet error checking register */
-#define STM32F7_I2C_RXDR_OFFSET     0x0024 /* Receive data register */
-#define STM32F7_I2C_TXDR_OFFSET     0x0028 /* Transmit data register */
-
-/* Register Addresses ***************************************************************/
-
-#if STM32F7_NI2C > 0
-#  define STM32F7_I2C1_CR1          (STM32F7_I2C1_BASE+STM32F7_I2C_CR1_OFFSET)
-#  define STM32F7_I2C1_CR2          (STM32F7_I2C1_BASE+STM32F7_I2C_CR2_OFFSET)
-#  define STM32F7_I2C1_OAR1         (STM32F7_I2C1_BASE+STM32F7_I2C_OAR1_OFFSET)
-#  define STM32F7_I2C1_OAR2         (STM32F7_I2C1_BASE+STM32F7_I2C_OAR2_OFFSET)
-#  define STM32F7_I2C1_TIMINGR      (STM32F7_I2C1_BASE+STM32F7_I2C_TIMINGR_OFFSET)
-#  define STM32F7_I2C1_TIMEOUTR     (STM32F7_I2C1_BASE+STM32F7_I2C_TIMEOUTR_OFFSET)
-#  define STM32F7_I2C1_ISR          (STM32F7_I2C1_BASE+STM32F7_I2C_ISR_OFFSET)
-#  define STM32F7_I2C1_ICR          (STM32F7_I2C1_BASE+STM32F7_I2C_ICR_OFFSET)
-#  define STM32F7_I2C1_PECR         (STM32F7_I2C1_BASE+STM32F7_I2C_PECR_OFFSET)
-#  define STM32F7_I2C1_RXDR         (STM32F7_I2C1_BASE+STM32F7_I2C_RXDR_OFFSET)
-#  define STM32F7_I2C1_TXDR         (STM32F7_I2C1_BASE+STM32F7_I2C_TXDR_OFFSET)
-#endif
-
-#if STM32F7_NI2C > 1
-#  define STM32F7_I2C2_CR1          (STM32F7_I2C2_BASE+STM32F7_I2C_CR1_OFFSET)
-#  define STM32F7_I2C2_CR2          (STM32F7_I2C2_BASE+STM32F7_I2C_CR2_OFFSET)
-#  define STM32F7_I2C2_OAR1         (STM32F7_I2C2_BASE+STM32F7_I2C_OAR1_OFFSET)
-#  define STM32F7_I2C2_OAR2         (STM32F7_I2C2_BASE+STM32F7_I2C_OAR2_OFFSET)
-#  define STM32F7_I2C2_TIMINGR      (STM32F7_I2C2_BASE+STM32F7_I2C_TIMINGR_OFFSET)
-#  define STM32F7_I2C2_TIMEOUTR     (STM32F7_I2C2_BASE+STM32F7_I2C_TIMEOUTR_OFFSET)
-#  define STM32F7_I2C2_ISR          (STM32F7_I2C2_BASE+STM32F7_I2C_ISR_OFFSET)
-#  define STM32F7_I2C2_ICR          (STM32F7_I2C2_BASE+STM32F7_I2C_ICR_OFFSET)
-#  define STM32F7_I2C2_PECR         (STM32F7_I2C2_BASE+STM32F7_I2C_PECR_OFFSET)
-#  define STM32F7_I2C2_RXDR         (STM32F7_I2C2_BASE+STM32F7_I2C_RXDR_OFFSET)
-#  define STM32F7_I2C2_TXDR         (STM32F7_I2C2_BASE+STM32F7_I2C_TXDR_OFFSET)
-#endif
-
-#if STM32F7_NI2C > 2
-#  define STM32F7_I2C3_CR1          (STM32F7_I2C3_BASE+STM32F7_I2C_CR1_OFFSET)
-#  define STM32F7_I2C3_CR2          (STM32F7_I2C3_BASE+STM32F7_I2C_CR2_OFFSET)
-#  define STM32F7_I2C3_OAR1         (STM32F7_I2C3_BASE+STM32F7_I2C_OAR1_OFFSET)
-#  define STM32F7_I2C3_OAR2         (STM32F7_I2C3_BASE+STM32F7_I2C_OAR2_OFFSET)
-#  define STM32F7_I2C3_TIMINGR      (STM32F7_I2C3_BASE+STM32F7_I2C_TIMINGR_OFFSET)
-#  define STM32F7_I2C3_TIMEOUTR     (STM32F7_I2C3_BASE+STM32F7_I2C_TIMEOUTR_OFFSET)
-#  define STM32F7_I2C3_ISR          (STM32F7_I2C3_BASE+STM32F7_I2C_ISR_OFFSET)
-#  define STM32F7_I2C3_ICR          (STM32F7_I2C3_BASE+STM32F7_I2C_ICR_OFFSET)
-#  define STM32F7_I2C3_PECR         (STM32F7_I2C3_BASE+STM32F7_I2C_PECR_OFFSET)
-#  define STM32F7_I2C3_RXDR         (STM32F7_I2C3_BASE+STM32F7_I2C_RXDR_OFFSET)
-#  define STM32F7_I2C3_TXDR         (STM32F7_I2C3_BASE+STM32F7_I2C_TXDR_OFFSET)
-#endif
-
-/* Register Bitfield Definitions ****************************************************/
-
-/* Control register 1 */
-
-#define I2C_CR1_PE                  (1 << 0)  /* Bit 0:  Peripheral Enable */
-#define I2C_CR1_TXIE                (1 << 1)  /* Bit 1:  TX Interrupt enable */
-#define I2C_CR1_RXIE                (1 << 2)  /* Bit 2:  RX Interrupt enable */
-#define I2C_CR1_ADDRIE              (1 << 3)  /* Bit 3:  Address match interrupt enable (slave) */
-#define I2C_CR1_NACKIE              (1 << 4)  /* Bit 4:  Not acknowledge received interrupt enable */
-#define I2C_CR1_STOPIE              (1 << 5)  /* Bit 5:  STOP detection interrupt enable */
-#define I2C_CR1_TCIE                (1 << 6)  /* Bit 6:  Transfer Complete interrupt enable */
-#define I2C_CR1_ERRIE               (1 << 7)  /* Bit 7:  Error interrupts enable */
-#define I2C_CR1_DNF_SHIFT           (8)       /* Bits 8-11: Digital noise filter */
-#define I2C_CR1_DNF_MASK            (15 << I2C_CR1_DNF_SHIFT)
-#  define I2C_CR1_DNF_DISABLE       (0 << I2C_CR1_DNF_SHIFT)
-#  define I2C_CR1_DNF(n)            ((n) << I2C_CR1_DNF_SHIFT) /* Up to n * Ti2cclk, n=1..15 */
-#define I2C_CR1_ANFOFF              (1 << 12) /* Bit 12: Analog noise filter OFF */
-#define I2C_CR1_TXDMAEN             (1 << 14) /* Bit 14: DMA transmission requests enable */
-#define I2C_CR1_RXDMAEN             (1 << 15) /* Bit 15: DMA reception requests enable */
-#define I2C_CR1_SBC                 (1 << 16) /* Bit 16: Slave byte control */
-#define I2C_CR1_NOSTRETCH           (1 << 17) /* Bit 17: Clock stretching disable */
-#define I2C_CR1_WUPEN               (1 << 18) /* Bit 18: Wakeup from STOP enable */
-#define I2C_CR1_GCEN                (1 << 19) /* Bit 19: General call enable */
-#define I2C_CR1_SMBHEN              (1 << 20) /* Bit 20: SMBus Host address enable */
-#define I2C_CR1_SMBDEN              (1 << 21) /* Bit 21: SMBus Device Default address enable */
-#define I2C_CR1_ALERTEN             (1 << 22) /* Bit 22: SMBus alert enable */
-#define I2C_CR1_PECEN               (1 << 23) /* Bit 23: PEC enable */
-
-/* Control register 2 */
-
-#define I2C_CR2_SADD10_SHIFT        (0)       /* Bits 0-9: Slave 10-bit address (master) */
-#define I2C_CR2_SADD10_MASK         (0x3ff << I2C_CR2_SADD10_SHIFT)
-#define I2C_CR2_SADD7_SHIFT         (1)       /* Bits 1-7: Slave 7-bit address (master) */
-#define I2C_CR2_SADD7_MASK          (0x7f << I2C_CR2_SADD7_SHIFT)
-#define I2C_CR2_RD_WRN              (1 << 10) /* Bit 10: Transfer direction (master) */
-#define I2C_CR2_ADD10               (1 << 11) /* Bit 11: 10-bit addressing mode (master) */
-#define I2C_CR2_HEAD10R             (1 << 12) /* Bit 12: 10-bit address header only read direction (master) */
-#define I2C_CR2_START               (1 << 13) /* Bit 13: Start generation */
-#define I2C_CR2_STOP                (1 << 14) /* Bit 14: Stop generation (master) */
-#define I2C_CR2_NACK                (1 << 15) /* Bit 15: NACK generation (slave) */
-#define I2C_CR2_NBYTES_SHIFT        (16)      /* Bits 16-23: Number of bytes */
-#define I2C_CR2_NBYTES_MASK         (0xff << I2C_CR2_NBYTES_SHIFT)
-#define I2C_CR2_RELOAD              (1 << 24) /* Bit 24: NBYTES reload mode */
-#define I2C_CR2_AUTOEND             (1 << 25) /* Bit 25: Automatic end mode (master) */
-#define I2C_CR2_PECBYTE             (1 << 26) /* Bit 26: Packet error checking byte */
-
-/* Own address register 1 */
-
-#define I2C_OAR1_OA1_10_SHIFT       (0)       /* Bits 0-9: 10-bit interface address */
-#define I2C_OAR1_OA1_10_MASK        (0x3ff << I2C_OAR1_OA1_10_SHIFT)
-#define I2C_OAR1_OA1_7_SHIFT        (1)       /* Bits 1-7: 7-bit interface address */
-#define I2C_OAR1_OA1_7_MASK         (0x7f << I2C_OAR1_OA1_7_SHIFT)
-#define I2C_OAR1_OA1MODE            (1 << 10) /* Bit 10: Own Address 1 10-bit mode */
-#define I2C_OAR1_OA1EN              (1 << 15) /* Bit 15: Own Address 1 enable */
-
-/* Own address register 2 */
-
-#define I2C_OAR2_OA2_SHIFT          (1)       /* Bits 1-7: 7-bit interface address */
-#define I2C_OAR2_OA2_MASK           (0x7f << I2C_OAR2_OA2_SHIFT)
-#define I2C_OAR2_OA2MSK_SHIFT       (8)       /* Bits 8-10: Own Address 2 masks */
-#define I2C_OAR2_OA2MSK_MASK        (7 << I2C_OAR2_OA2MSK_SHIFT)
-#  define I2C_OAR2_OA2MSK_NONE      (0 << I2C_OAR2_OA2MSK_SHIFT) /* No mask */
-#  define I2C_OAR2_OA2MSK_2_7       (1 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:2] are compared */
-#  define I2C_OAR2_OA2MSK_3_7       (2 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:3] are compared */
-#  define I2C_OAR2_OA2MSK_4_7       (3 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:4] are compared */
-#  define I2C_OAR2_OA2MSK_5_7       (4 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:5] are compared */
-#  define I2C_OAR2_OA2MSK_6_7       (5 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:6] are compared */
-#  define I2C_OAR2_OA2MSK_7         (6 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7] is compared */
-#  define I2C_OAR2_OA2MSK_ALL       (7 << I2C_OAR2_OA2MSK_SHIFT) /* All 7-bit addresses acknowledged */
-#define I2C_OAR2_OA2EN              (1 << 15)  /* Bit 15: Own Address 2 enable */
-
-/* Timing register */
-
-#define I2C_TIMINGR_SCLL_SHIFT      (0)        /* Bits 0-7: SCL low period (master) */
-#define I2C_TIMINGR_SCLL_MASK       (0xff << I2C_TIMINGR_SCLL_SHIFT)
-#  define I2C_TIMINGR_SCLL(n)       (((n)-1) << I2C_TIMINGR_SCLL_SHIFT) /* tSCLL = n x tPRESC */
-
-#define I2C_TIMINGR_SCLH_SHIFT      (8)        /* Bits 8-15: SCL high period (master) */
-#define I2C_TIMINGR_SCLH_MASK       (0xff << I2C_TIMINGR_SCLH_SHIFT)
-#  define I2C_TIMINGR_SCLH(n)       (((n)-1) << I2C_TIMINGR_SCLH_SHIFT) /* tSCLH = n x tPRESC */
-
-#define I2C_TIMINGR_SDADEL_SHIFT    (16)        /* Bits 16-19: Data hold time */
-#define I2C_TIMINGR_SDADEL_MASK     (15 << I2C_TIMINGR_SDADEL_SHIFT)
-#  define I2C_TIMINGR_SDADEL(n)     ((n) << I2C_TIMINGR_SDADEL_SHIFT) /* tSDADEL= n x tPRESC */
-
-#define I2C_TIMINGR_SCLDEL_SHIFT    (20)        /* Bits 20-23: Data setup time */
-#define I2C_TIMINGR_SCLDEL_MASK     (15 << I2C_TIMINGR_SCLDEL_SHIFT)
-#  define I2C_TIMINGR_SCLDEL(n)     (((n)-1) << I2C_TIMINGR_SCLDEL_SHIFT) /* tSCLDEL = n x tPRESC */
-
-#define I2C_TIMINGR_PRESC_SHIFT     (28)        /* Bits 28-31: Timing prescaler */
-#define I2C_TIMINGR_PRESC_MASK      (15 << I2C_TIMINGR_PRESC_SHIFT)
-#  define I2C_TIMINGR_PRESC(n)      (((n)-1) << I2C_TIMINGR_PRESC_SHIFT) /* tPRESC = n x tI2CCLK */
-
-/* Timeout register */
-
-#define I2C_TIMEOUTR_A_SHIFT        (0)       /* Bits 0-11: Bus Timeout A */
-#define I2C_TIMEOUTR_A_MASK         (0x0fff << I2C_TIMEOUTR_A_SHIFT)
-#  define I2C_TIMEOUTR_A(n)         ((n) << I2C_TIMEOUTR_A_SHIFT)
-#define I2C_TIMEOUTR_TIDLE          (1 << 12) /* Bit 12: Idle clock timeout detection */
-#define I2C_TIMEOUTR_TIMOUTEN       (1 << 15) /* Bit 15: Clock timeout enable */
-#define I2C_TIMEOUTR_B_SHIFT        (16)      /* Bits 16-27: Bus Timeout B */
-#define I2C_TIMEOUTR_B_MASK         (0x0fff << I2C_TIMEOUTR_B_SHIFT)
-#  define I2C_TIMEOUTR_B(n)         ((n) << I2C_TIMEOUTR_B_SHIFT)
-#define I2C_TIMEOUTR_TEXTEN         (1 << 31) /* Bits 31: Extended clock timeout enable */
-
-/* Interrupt and Status register and interrupt clear register */
-/* Common interrupt bits */
-
-#define I2C_INT_ADDR                (1 << 3)  /* Bit 3:  Address matched (slave) */
-#define I2C_INT_NACK                (1 << 4)  /* Bit 4:  Not Acknowledge received flag */
-#define I2C_INT_STOP                (1 << 5)  /* Bit 5:  Stop detection flag */
-#define I2C_INT_BERR                (1 << 8)  /* Bit 8:  Bus error */
-#define I2C_INT_ARLO                (1 << 9)  /* Bit 9:  Arbitration lost */
-#define I2C_INT_OVR                 (1 << 10) /* Bit 10: Overrun/Underrun (slave) */
-#define I2C_INT_PECERR              (1 << 11) /* Bit 11: PEC Error in reception */
-#define I2C_INT_TIMEOUT             (1 << 12) /* Bit 12: Timeout or tLOW detection flag */
-#define I2C_INT_ALERT               (1 << 13) /* Bit 13: SMBus alert */
-
-/* Fields unique to the Interrupt and Status register */
-
-#define I2C_ISR_TXE                 (1 << 0)  /* Bit 0:  Transmit data register empty (transmitters) */
-#define I2C_ISR_TXIS                (1 << 1)  /* Bit 1:  Transmit interrupt status (transmitters) */
-#define I2C_ISR_RXNE                (1 << 2)  /* Bit 2:  Receive data register not empty (receivers) */
-#define I2C_ISR_TC                  (1 << 6)  /* Bit 6:  Transfer Complete (master) */
-#define I2C_ISR_TCR                 (1 << 7)  /* Bit 7:  Transfer Complete Reload */
-#define I2C_ISR_BUSY                (1 << 15) /* Bit 15: Bus busy */
-#define I2C_ISR_DIR                 (1 << 16) /* Bit 16: Transfer direction (slave) */
-#define I2C_ISR_ADDCODE_SHIFT       (17)      /* Bits 17-23: Address match code (slave) */
-#define I2C_ISR_ADDCODE_MASK        (0x7f << I2C_ISR_ADDCODE_SHIFT)
-
-#define I2C_ISR_ERRORMASK (I2C_INT_BERR | I2C_INT_ARLO | I2C_INT_OVR | I2C_INT_PECERR | I2C_INT_TIMEOUT)
-
-#define I2C_ICR_CLEARMASK (I2C_INT_ADDR | I2C_INT_NACK | I2C_INT_STOP | I2C_INT_BERR | I2C_INT_ARLO \
-                           | I2C_INT_OVR | I2C_INT_PECERR | I2C_INT_TIMEOUT | I2C_INT_ALERT)
-
-/* Packet error checking register */
-
-#define I2C_PECR_MASK               (0xff)
-
-/* Receive data register */
-
-#define I2C_RXDR_MASK               (0xff)
-
-/* Transmit data register */
-
-#define I2C_TXDR_MASK               (0xff)
-
-#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX75XX_I2C_H */
-
diff --git a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_rcc.h b/arch/arm/src/stm32f7/chip/stm32f74xx75xx_rcc.h
index 0cdc92c7276..881f17dc560 100644
--- a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_rcc.h
+++ b/arch/arm/src/stm32f7/chip/stm32f74xx75xx_rcc.h
@@ -1,8 +1,9 @@
 /****************************************************************************************************
  * arch/arm/src/stm32f7/chip/stm32f74xx75xx_rcc.h
  *
- *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *   Copyright (C) 2015-2016 Gregory Nutt. All rights reserved.
+ *   Authors: Gregory Nutt <gnutt@nuttx.org>
+ *            David Sidrane <david_s5@nscdg.com>
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -616,7 +617,7 @@
 #define RCC_DCKCFGR1_SAI2SEL_SHIFT   (22)      /* Bits 22-23: SAI 2 clock source selection */
 #define RCC_DCKCFGR1_SAI2SEL_MASK    (0x3 << RCC_DCKCFGR1_SAI2SEL_SHIFT)
 #  define RCC_DCKCFGR1_SAI2SEL(n)    ((n) << RCC_DCKCFGR1_SAI2SEL_SHIFT)
-#define RCC_DCKCFGR1_TIMPRE          (1 << 24) /* Bit 24: Timer clock prescaler selection */
+#define RCC_DCKCFGR1_TIMPRESEL       (1 << 24) /* Bit 24: Timer clock prescaler selection */
 
 /* Dedicated clocks configuration register 2 */
 
diff --git a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_spi.h b/arch/arm/src/stm32f7/chip/stm32f74xx75xx_spi.h
deleted file mode 100644
index 57d86d98521..00000000000
--- a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_spi.h
+++ /dev/null
@@ -1,207 +0,0 @@
-/************************************************************************************
- * arch/arm/src/stm32f7/chip/stm32f74xx75xx_spi.h
- *
- *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX75XX_SPI_H
-#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX75XX_SPI_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-#include "chip.h"
-
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
-/* Maximum allowed speed as per specifications for all SPIs */
-
-#define STM32F7_SPI_CLK_MAX         27000000UL
-
-/* Register Offsets *****************************************************************/
-
-#define STM32F7_SPI_CR1_OFFSET      0x0000  /* SPI Control Register 1 (16-bit) */
-#define STM32F7_SPI_CR2_OFFSET      0x0004  /* SPI control register 2 (16-bit) */
-#define STM32F7_SPI_SR_OFFSET       0x0008  /* SPI status register (16-bit) */
-#define STM32F7_SPI_DR_OFFSET       0x000c  /* SPI data register (16-bit) */
-#define STM32F7_SPI_CRCPR_OFFSET    0x0010  /* SPI CRC polynomial register (16-bit) */
-#define STM32F7_SPI_RXCRCR_OFFSET   0x0014  /* SPI Rx CRC register (16-bit) */
-#define STM32F7_SPI_TXCRCR_OFFSET   0x0018  /* SPI Tx CRC register (16-bit) */
-
-/* Register Addresses ***************************************************************/
-
-#if STM32F7_NSPI > 0
-#  define STM32F7_SPI1_CR1          (STM32_SPI1_BASE+STM32F7_SPI_CR1_OFFSET)
-#  define STM32F7_SPI1_CR2          (STM32_SPI1_BASE+STM32F7_SPI_CR2_OFFSET)
-#  define STM32F7_SPI1_SR           (STM32_SPI1_BASE+STM32F7_SPI_SR_OFFSET)
-#  define STM32F7_SPI1_DR           (STM32_SPI1_BASE+STM32F7_SPI_DR_OFFSET)
-#  define STM32F7_SPI1_CRCPR        (STM32_SPI1_BASE+STM32F7_SPI_CRCPR_OFFSET)
-#  define STM32F7_SPI1_RXCRCR       (STM32_SPI1_BASE+STM32F7_SPI_RXCRCR_OFFSET)
-#  define STM32F7_SPI1_TXCRCR       (STM32_SPI1_BASE+STM32F7_SPI_TXCRCR_OFFSET)
-#endif
-
-#if STM32F7_NSPI > 1
-#  define STM32F7_SPI2_CR1          (STM32_SPI2_BASE+STM32F7_SPI_CR1_OFFSET)
-#  define STM32F7_SPI2_CR2          (STM32_SPI2_BASE+STM32F7_SPI_CR2_OFFSET)
-#  define STM32F7_SPI2_SR           (STM32_SPI2_BASE+STM32F7_SPI_SR_OFFSET)
-#  define STM32F7_SPI2_DR           (STM32_SPI2_BASE+STM32F7_SPI_DR_OFFSET)
-#  define STM32F7_SPI2_CRCPR        (STM32_SPI2_BASE+STM32F7_SPI_CRCPR_OFFSET)
-#  define STM32F7_SPI2_RXCRCR       (STM32_SPI2_BASE+STM32F7_SPI_RXCRCR_OFFSET)
-#  define STM32F7_SPI2_TXCRCR       (STM32_SPI2_BASE+STM32F7_SPI_TXCRCR_OFFSET)
-#endif
-
-#if STM32F7_NSPI > 2
-#  define STM32F7_SPI3_CR1          (STM32_SPI3_BASE+STM32F7_SPI_CR1_OFFSET)
-#  define STM32F7_SPI3_CR2          (STM32_SPI3_BASE+STM32F7_SPI_CR2_OFFSET)
-#  define STM32F7_SPI3_SR           (STM32_SPI3_BASE+STM32F7_SPI_SR_OFFSET)
-#  define STM32F7_SPI3_DR           (STM32_SPI3_BASE+STM32F7_SPI_DR_OFFSET)
-#  define STM32F7_SPI3_CRCPR        (STM32_SPI3_BASE+STM32F7_SPI_CRCPR_OFFSET)
-#  define STM32F7_SPI3_RXCRCR       (STM32_SPI3_BASE+STM32F7_SPI_RXCRCR_OFFSET)
-#  define STM32F7_SPI3_TXCRCR       (STM32_SPI3_BASE+STM32F7_SPI_TXCRCR_OFFSET)
-#endif
-
-#if STM32F7_NSPI > 3
-#  define STM32F7_SPI4_CR1          (STM32_SPI4_BASE+STM32F7_SPI_CR1_OFFSET)
-#  define STM32F7_SPI4_CR2          (STM32_SPI4_BASE+STM32F7_SPI_CR2_OFFSET)
-#  define STM32F7_SPI4_SR           (STM32_SPI4_BASE+STM32F7_SPI_SR_OFFSET)
-#  define STM32F7_SPI4_DR           (STM32_SPI4_BASE+STM32F7_SPI_DR_OFFSET)
-#  define STM32F7_SPI4_CRCPR        (STM32_SPI4_BASE+STM32F7_SPI_CRCPR_OFFSET)
-#  define STM32F7_SPI4_RXCRCR       (STM32_SPI4_BASE+STM32F7_SPI_RXCRCR_OFFSET)
-#  define STM32F7_SPI4_TXCRCR       (STM32_SPI4_BASE+STM32F7_SPI_TXCRCR_OFFSET)
-#endif
-
-#if STM32F7_NSPI > 4
-#  define STM32F7_SPI5_CR1          (STM32_SPI5_BASE+STM32F7_SPI_CR1_OFFSET)
-#  define STM32F7_SPI5_CR2          (STM32_SPI5_BASE+STM32F7_SPI_CR2_OFFSET)
-#  define STM32F7_SPI5_SR           (STM32_SPI5_BASE+STM32F7_SPI_SR_OFFSET)
-#  define STM32F7_SPI5_DR           (STM32_SPI5_BASE+STM32F7_SPI_DR_OFFSET)
-#  define STM32F7_SPI5_CRCPR        (STM32_SPI5_BASE+STM32F7_SPI_CRCPR_OFFSET)
-#  define STM32F7_SPI5_RXCRCR       (STM32_SPI5_BASE+STM32F7_SPI_RXCRCR_OFFSET)
-#  define STM32F7_SPI5_TXCRCR       (STM32_SPI5_BASE+STM32F7_SPI_TXCRCR_OFFSET)
-#endif
-
-#if STM32F7_NSPI > 5
-#  define STM32F7_SPI6_CR1          (STM32_SPI6_BASE+STM32F7_SPI_CR1_OFFSET)
-#  define STM32F7_SPI6_CR2          (STM32_SPI6_BASE+STM32F7_SPI_CR2_OFFSET)
-#  define STM32F7_SPI6_SR           (STM32_SPI6_BASE+STM32F7_SPI_SR_OFFSET)
-#  define STM32F7_SPI6_DR           (STM32_SPI6_BASE+STM32F7_SPI_DR_OFFSET)
-#  define STM32F7_SPI6_CRCPR        (STM32_SPI6_BASE+STM32F7_SPI_CRCPR_OFFSET)
-#  define STM32F7_SPI6_RXCRCR       (STM32_SPI6_BASE+STM32F7_SPI_RXCRCR_OFFSET)
-#  define STM32F7_SPI6_TXCRCR       (STM32_SPI6_BASE+STM32F7_SPI_TXCRCR_OFFSET)
-#endif
-
-/* Register Bitfield Definitions ****************************************************/
-
-/* SPI Control Register 1 */
-
-#define SPI_CR1_CPHA                (1 << 0)  /* Bit 0: Clock Phase */
-#define SPI_CR1_CPOL                (1 << 1)  /* Bit 1: Clock Polarity */
-#define SPI_CR1_MSTR                (1 << 2)  /* Bit 2: Master Selection */
-#define SPI_CR1_BR_SHIFT            (3)       /* Bits 5:3 Baud Rate Control */
-#define SPI_CR1_BR_MASK             (7 << SPI_CR1_BR_SHIFT)
-#  define SPI_CR1_FPCLCKd2          (0 << SPI_CR1_BR_SHIFT) /* 000: fPCLK/2 */
-#  define SPI_CR1_FPCLCKd4          (1 << SPI_CR1_BR_SHIFT) /* 001: fPCLK/4 */
-#  define SPI_CR1_FPCLCKd8          (2 << SPI_CR1_BR_SHIFT) /* 010: fPCLK/8 */
-#  define SPI_CR1_FPCLCKd16         (3 << SPI_CR1_BR_SHIFT) /* 011: fPCLK/16 */
-#  define SPI_CR1_FPCLCKd32         (4 << SPI_CR1_BR_SHIFT) /* 100: fPCLK/32 */
-#  define SPI_CR1_FPCLCKd64         (5 << SPI_CR1_BR_SHIFT) /* 101: fPCLK/64 */
-#  define SPI_CR1_FPCLCKd128        (6 << SPI_CR1_BR_SHIFT) /* 110: fPCLK/128 */
-#  define SPI_CR1_FPCLCKd256        (7 << SPI_CR1_BR_SHIFT) /* 111: fPCLK/256 */
-#define SPI_CR1_SPE                 (1 << 6)  /* Bit 6: SPI Enable */
-#define SPI_CR1_LSBFIRST            (1 << 7)  /* Bit 7: Frame Format */
-#define SPI_CR1_SSI                 (1 << 8)  /* Bit 8: Internal slave select */
-#define SPI_CR1_SSM                 (1 << 9)  /* Bit 9: Software slave management */
-#define SPI_CR1_RXONLY              (1 << 10) /* Bit 10: Receive only */
-#define SPI_CR1_CRCL                (1 << 11) /* Bit 11: CRC length */
-#define SPI_CR1_CRCNEXT             (1 << 12) /* Bit 12: Transmit CRC next */
-#define SPI_CR1_CRCEN               (1 << 13) /* Bit 13: Hardware CRC calculation enable */
-#define SPI_CR1_BIDIOE              (1 << 14) /* Bit 14: Output enable in bidirectional mode */
-#define SPI_CR1_BIDIMODE            (1 << 15) /* Bit 15: Bidirectional data mode enable */
-
-/* SPI Control Register 2 */
-
-#define SPI_CR2_RXDMAEN             (1 << 0)  /* Bit 0: Rx Buffer DMA Enable */
-#define SPI_CR2_TXDMAEN             (1 << 1)  /* Bit 1: Tx Buffer DMA Enable */
-#define SPI_CR2_SSOE                (1 << 2)  /* Bit 2: SS Output Enable */
-#define SPI_CR2_NSSP                (1 << 3)  /* Bit 3: NSS pulse management */
-#define SPI_CR2_FRF                 (1 << 4)  /* Bit 4: Frame format */
-#define SPI_CR2_ERRIE               (1 << 5)  /* Bit 5: Error interrupt enable */
-#define SPI_CR2_RXNEIE              (1 << 6)  /* Bit 6: RX buffer not empty interrupt enable */
-#define SPI_CR2_TXEIE               (1 << 7)  /* Bit 7: Tx buffer empty interrupt enable */
-#define SPI_CR2_DS_SHIFT            (8)       /* Bits 8-11:  Data size */
-#define SPI_CR2_DS_MASK             (15 << SPI_CR2_DS_SHIFT)
-#  define SPI_CR2_DS_VAL(bits)      (((uint32_t)(bits)-1) << SPI_CR2_DS_SHIFT)
-#  define SPI_CR2_DS_4BIT           SPI_CR2_DS_VAL( 4)
-#  define SPI_CR2_DS_5BIT           SPI_CR2_DS_VAL( 5)
-#  define SPI_CR2_DS_6BIT           SPI_CR2_DS_VAL( 6)
-#  define SPI_CR2_DS_7BIT           SPI_CR2_DS_VAL( 7)
-#  define SPI_CR2_DS_8BIT           SPI_CR2_DS_VAL( 8)
-#  define SPI_CR2_DS_9BIT           SPI_CR2_DS_VAL( 9)
-#  define SPI_CR2_DS_10BIT          SPI_CR2_DS_VAL(10)
-#  define SPI_CR2_DS_11BIT          SPI_CR2_DS_VAL(11)
-#  define SPI_CR2_DS_12BIT          SPI_CR2_DS_VAL(12)
-#  define SPI_CR2_DS_13BIT          SPI_CR2_DS_VAL(13)
-#  define SPI_CR2_DS_14BIT          SPI_CR2_DS_VAL(14)
-#  define SPI_CR2_DS_15BIT          SPI_CR2_DS_VAL(15)
-#  define SPI_CR2_DS_16BIT          SPI_CR2_DS_VAL(16)
-#define SPI_CR2_FRXTH               (1 << 12) /* Bit 12: FIFO reception threshold */
-#define SPI_CR2_LDMARX              (1 << 13) /* Bit 13: Last DMA transfer for receptione */
-#define SPI_CR2_LDMATX              (1 << 14) /* Bit 14: Last DMA transfer for transmission */
-
-/* SPI status register */
-
-#define SPI_SR_RXNE                 (1 << 0)  /* Bit 0: Receive buffer not empty */
-#define SPI_SR_TXE                  (1 << 1)  /* Bit 1: Transmit buffer empty */
-#define SPI_SR_CRCERR               (1 << 4)  /* Bit 4: CRC error flag */
-#define SPI_SR_MODF                 (1 << 5)  /* Bit 5: Mode fault */
-#define SPI_SR_OVR                  (1 << 6)  /* Bit 6: Overrun flag */
-#define SPI_SR_BSY                  (1 << 7)  /* Bit 7: Busy flag */
-#define SPI_SR_FRE                  (1 << 8)  /* Bit 8: Frame format error */
-#define SPI_SR_FRLVL_SHIFT          (9)       /* Bits 9-10: FIFO reception level */
-#define SPI_SR_FRLVL_MASK           (3 << SPI_SR_FRLVL_SHIFT)
-#  define SPI_SR_FRLVL_EMPTY        (0 << SPI_SR_FRLVL_SHIFT) /* FIFO empty */
-#  define SPI_SR_FRLVL_QUARTER      (1 << SPI_SR_FRLVL_SHIFT) /* 1/4 FIFO */
-#  define SPI_SR_FRLVL_HALF         (2 << SPI_SR_FRLVL_SHIFT) /* 1/2 FIFO */
-#  define SPI_SR_FRLVL_FULL         (3 << SPI_SR_FRLVL_SHIFT) /* FIFO full */
-#define SPI_SR_FTLVL_SHIFT          (11)      /* Bits 11-12: FIFO transmission level */
-#define SPI_SR_FTLVL_MASK           (3 << SPI_SR_FTLVL_SHIFT)
-#  define SPI_SR_FTLVL_EMPTY        (0 << SPI_SR_FTLVL_SHIFT) /* FIFO empty */
-#  define SPI_SR_FTLVL_QUARTER      (1 << SPI_SR_FTLVL_SHIFT) /* 1/4 FIFO */
-#  define SPI_SR_FTLVL_HALF         (2 << SPI_SR_FTLVL_SHIFT) /* 1/2 FIFO */
-#  define SPI_SR_FTLVL_FULL         (3 << SPI_SR_FTLVL_SHIFT) /* FIFO full */
-
-#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX75XX_SPI_H */
-
diff --git a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_tim.h b/arch/arm/src/stm32f7/chip/stm32f74xx75xx_tim.h
new file mode 100644
index 00000000000..eca76e95aae
--- /dev/null
+++ b/arch/arm/src/stm32f7/chip/stm32f74xx75xx_tim.h
@@ -0,0 +1,1129 @@
+/****************************************************************************************************
+ * arch/arm/src/stm32f7/chip/stm32f74xx75xx_tim.h
+ *
+ *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ *   Authors: Gregory Nutt <gnutt@nuttx.org>
+ *            David Sidrane <david_s5@nscdg.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX75XX_TIM_H
+#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX75XX_TIM_H
+
+/****************************************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************************************/
+
+/* Register Offsets *********************************************************************************/
+
+/* Basic Timers - TIM6 and TIM7 */
+
+#define STM32_BTIM_CR1_OFFSET     0x0000  /* Control register 1 (16-bit) */
+#define STM32_BTIM_CR2_OFFSET     0x0004  /* Control register 2 (16-bit) */
+#define STM32_BTIM_DIER_OFFSET    0x000c  /* DMA/Interrupt enable register (16-bit) */
+#define STM32_BTIM_SR_OFFSET      0x0010  /* Status register (16-bit) */
+#define STM32_BTIM_EGR_OFFSET     0x0014  /* Event generation register (16-bit) */
+#define STM32_BTIM_CNT_OFFSET     0x0024  /* Counter (16-bit) */
+#define STM32_BTIM_PSC_OFFSET     0x0028  /* Prescaler (16-bit) */
+#define STM32_BTIM_ARR_OFFSET     0x002c  /* Auto-reload register (16-bit) */
+
+/* 16-/32-bit General Timers with DMA: TIM2, TM3, TIM4, and TIM5
+ * 16-bit General Timers without DMA: TIM9, TIM10, TIM11, TIM12, TIM13, and TIM14
+ * timers are 16-bit except for TIM2 and 5 are 32-bit
+ * timers TIM9 and 12 are different then  TIM10, TIM11, TIM13, and TIM14
+ */
+
+#define STM32_GTIM_CR1_OFFSET      0x0000  /* Control register 1 (16-bit) */
+#define STM32_GTIM_CR2_OFFSET      0x0004  /* Control register 2 (16-bit, TIM2, 5 only) */
+#define STM32_GTIM_SMCR_OFFSET     0x0008  /* Slave mode control register (32-bit, TIM2, 5, 9, 12 only) */
+#define STM32_GTIM_DIER_OFFSET     0x000c  /* DMA/Interrupt enable register (16-bit) */
+#define STM32_GTIM_SR_OFFSET       0x0010  /* Status register (16-bit) */
+#define STM32_GTIM_EGR_OFFSET      0x0014  /* Event generation register (16-bit) */
+#define STM32_GTIM_CCMR1_OFFSET    0x0018  /* Capture/compare mode register 1 (32-bit) */
+#define STM32_GTIM_CCMR2_OFFSET    0x001c  /* Capture/compare mode register 2 (32-bit on TIM2,5 only) */
+#define STM32_GTIM_CCER_OFFSET     0x0020  /* Capture/compare enable register (16-bit) */
+#define STM32_GTIM_CNT_OFFSET      0x0024  /* Counter (16 bit and 32-bit on TIM2, 5 only) */
+#define STM32_GTIM_PSC_OFFSET      0x0028  /* Prescaler (16-bit) */
+#define STM32_GTIM_ARR_OFFSET      0x002c  /* Auto-reload register (16 bit and 32-bit on TIM2, 5 only) */
+#define STM32_GTIM_CCR1_OFFSET     0x0034  /* Capture/compare register 1 (16-bit on all TIMx and 32-bit on TIM2,5 only) */
+#define STM32_GTIM_CCR2_OFFSET     0x0038  /* Capture/compare register 2 (16-bit TIM 3-4, 9, 12 and 32-bit on TIM2,5 only) */
+#define STM32_GTIM_CCR3_OFFSET     0x003c  /* Capture/compare register 3 (16-bit TIM 3-4 and 32-bit on TIM2,5 only) */
+#define STM32_GTIM_CCR4_OFFSET     0x0040  /* Capture/compare register 4 (16-bit TIM 3-4 and 32-bit on TIM2,5 only) */
+#define STM32_GTIM_DCR_OFFSET      0x0048  /* DMA control register (16-bit, TIM2-5 only) */
+#define STM32_GTIM_DMAR_OFFSET     0x004c  /* DMA address for burst mode (16-bit, TIM2-5 only) */
+#define STM32_GTIM_OR_OFFSET       0x0050  /* Timer 2/5/11 option register */
+
+/* Advanced Timers - TIM1 and TIM8 */
+
+#define STM32_ATIM_CR1_OFFSET      0x0000  /* Control register 1 (16-bit) */
+#define STM32_ATIM_CR2_OFFSET      0x0004  /* Control register 2 (32-bit*) */
+#define STM32_ATIM_SMCR_OFFSET     0x0008  /* Slave mode control register (32 -bit) */
+#define STM32_ATIM_DIER_OFFSET     0x000c  /* DMA/Interrupt enable register (16-bit) */
+#define STM32_ATIM_SR_OFFSET       0x0010  /* Status register (32-bit*) */
+#define STM32_ATIM_EGR_OFFSET      0x0014  /* Event generation register (16-bit) */
+#define STM32_ATIM_CCMR1_OFFSET    0x0018  /* Capture/compare mode register 1 (32-bit*) */
+#define STM32_ATIM_CCMR2_OFFSET    0x001c  /* Capture/compare mode register 2 (32-bit*) */
+#define STM32_ATIM_CCER_OFFSET     0x0020  /* Capture/compare enable register (32-bit*) */
+#define STM32_ATIM_CNT_OFFSET      0x0024  /* Counter (32-bit cnt in lower 16 bit ) */
+#define STM32_ATIM_PSC_OFFSET      0x0028  /* Prescaler (16-bit) */
+#define STM32_ATIM_ARR_OFFSET      0x002c  /* Auto-reload register (16-bit) */
+#define STM32_ATIM_RCR_OFFSET      0x0030  /* Repetition counter register (16-bit) */
+#define STM32_ATIM_CCR1_OFFSET     0x0034  /* Capture/compare register 1 (16-bit) */
+#define STM32_ATIM_CCR2_OFFSET     0x0038  /* Capture/compare register 2 (16-bit) */
+#define STM32_ATIM_CCR3_OFFSET     0x003c  /* Capture/compare register 3 (16-bit) */
+#define STM32_ATIM_CCR4_OFFSET     0x0040  /* Capture/compare register 4 (16-bit) */
+#define STM32_ATIM_BDTR_OFFSET     0x0044  /* Break and dead-time register (32-bit*) */
+#define STM32_ATIM_DCR_OFFSET      0x0048  /* DMA control register (16-bit) */
+#define STM32_ATIM_DMAR_OFFSET     0x004c  /* DMA address for burst mode (16-bit) */
+#define STM32_ATIM_CCMR3_OFFSET    0x0054  /* Capture/compare mode register 3 (32-bit) */
+#define STM32_ATIM_CCR5_OFFSET     0x0058  /* Capture/compare register 5 (32-bit) */
+#define STM32_ATIM_CCR6_OFFSET     0x005c  /* Capture/compare register 6 (16-bit) */
+
+/* Register Addresses *******************************************************************************/
+
+/* Advanced Timers - TIM1 and TIM8 */
+
+#if STM32F7_NATIM > 0
+#  define STM32_TIM1_CR1          (STM32_TIM1_BASE+STM32_ATIM_CR1_OFFSET)
+#  define STM32_TIM1_CR2          (STM32_TIM1_BASE+STM32_ATIM_CR2_OFFSET)
+#  define STM32_TIM1_SMCR         (STM32_TIM1_BASE+STM32_ATIM_SMCR_OFFSET)
+#  define STM32_TIM1_DIER         (STM32_TIM1_BASE+STM32_ATIM_DIER_OFFSET)
+#  define STM32_TIM1_SR           (STM32_TIM1_BASE+STM32_ATIM_SR_OFFSET)
+#  define STM32_TIM1_EGR          (STM32_TIM1_BASE+STM32_ATIM_EGR_OFFSET)
+#  define STM32_TIM1_CCMR1        (STM32_TIM1_BASE+STM32_ATIM_CCMR1_OFFSET)
+#  define STM32_TIM1_CCMR2        (STM32_TIM1_BASE+STM32_ATIM_CCMR2_OFFSET)
+#  define STM32_TIM1_CCER         (STM32_TIM1_BASE+STM32_ATIM_CCER_OFFSET)
+#  define STM32_TIM1_CNT          (STM32_TIM1_BASE+STM32_ATIM_CNT_OFFSET)
+#  define STM32_TIM1_PSC          (STM32_TIM1_BASE+STM32_ATIM_PSC_OFFSET)
+#  define STM32_TIM1_ARR          (STM32_TIM1_BASE+STM32_ATIM_ARR_OFFSET)
+#  define STM32_TIM1_RCR          (STM32_TIM1_BASE+STM32_ATIM_RCR_OFFSET)
+#  define STM32_TIM1_CCR1         (STM32_TIM1_BASE+STM32_ATIM_CCR1_OFFSET)
+#  define STM32_TIM1_CCR2         (STM32_TIM1_BASE+STM32_ATIM_CCR2_OFFSET)
+#  define STM32_TIM1_CCR3         (STM32_TIM1_BASE+STM32_ATIM_CCR3_OFFSET)
+#  define STM32_TIM1_CCR4         (STM32_TIM1_BASE+STM32_ATIM_CCR4_OFFSET)
+#  define STM32_TIM1_BDTR         (STM32_TIM1_BASE+STM32_ATIM_BDTR_OFFSET)
+#  define STM32_TIM1_DCR          (STM32_TIM1_BASE+STM32_ATIM_DCR_OFFSET)
+#  define STM32_TIM1_DMAR         (STM32_TIM1_BASE+STM32_ATIM_DMAR_OFFSET)
+#  define STM32_TIM1_CCMR3        (STM32_TIM1_BASE+STM32_ATIM_CCMR3_OFFSET)
+#  define STM32_TIM1_CCR5         (STM32_TIM1_BASE+STM32_ATIM_CCR5_OFFSET)
+#  define STM32_TIM1_CCR6         (STM32_TIM1_BASE+STM32_ATIM_CCR6_OFFSET)
+#endif
+
+#if STM32F7_NATIM > 1
+#  define STM32_TIM8_CR1          (STM32_TIM8_BASE+STM32_ATIM_CR1_OFFSET)
+#  define STM32_TIM8_CR2          (STM32_TIM8_BASE+STM32_ATIM_CR2_OFFSET)
+#  define STM32_TIM8_SMCR         (STM32_TIM8_BASE+STM32_ATIM_SMCR_OFFSET)
+#  define STM32_TIM8_DIER         (STM32_TIM8_BASE+STM32_ATIM_DIER_OFFSET)
+#  define STM32_TIM8_SR           (STM32_TIM8_BASE+STM32_ATIM_SR_OFFSET)
+#  define STM32_TIM8_EGR          (STM32_TIM8_BASE+STM32_ATIM_EGR_OFFSET)
+#  define STM32_TIM8_CCMR1        (STM32_TIM8_BASE+STM32_ATIM_CCMR1_OFFSET)
+#  define STM32_TIM8_CCMR2        (STM32_TIM8_BASE+STM32_ATIM_CCMR2_OFFSET)
+#  define STM32_TIM8_CCER         (STM32_TIM8_BASE+STM32_ATIM_CCER_OFFSET)
+#  define STM32_TIM8_CNT          (STM32_TIM8_BASE+STM32_ATIM_CNT_OFFSET)
+#  define STM32_TIM8_PSC          (STM32_TIM8_BASE+STM32_ATIM_PSC_OFFSET)
+#  define STM32_TIM8_ARR          (STM32_TIM8_BASE+STM32_ATIM_ARR_OFFSET)
+#  define STM32_TIM8_RCR          (STM32_TIM8_BASE+STM32_ATIM_RCR_OFFSET)
+#  define STM32_TIM8_CCR1         (STM32_TIM8_BASE+STM32_ATIM_CCR1_OFFSET)
+#  define STM32_TIM8_CCR2         (STM32_TIM8_BASE+STM32_ATIM_CCR2_OFFSET)
+#  define STM32_TIM8_CCR3         (STM32_TIM8_BASE+STM32_ATIM_CCR3_OFFSET)
+#  define STM32_TIM8_CCR4         (STM32_TIM8_BASE+STM32_ATIM_CCR4_OFFSET)
+#  define STM32_TIM8_BDTR         (STM32_TIM8_BASE+STM32_ATIM_BDTR_OFFSET)
+#  define STM32_TIM8_DCR          (STM32_TIM8_BASE+STM32_ATIM_DCR_OFFSET)
+#  define STM32_TIM8_DMAR         (STM32_TIM8_BASE+STM32_ATIM_DMAR_OFFSET)
+#  define STM32_TIM8_CCMR3        (STM32_TIM8_BASE+STM32_ATIM_CCMR3_OFFSET)
+#  define STM32_TIM8_CCR5         (STM32_TIM8_BASE+STM32_ATIM_CCR5_OFFSET)
+#  define STM32_TIM8_CCR6         (STM32_TIM8_BASE+STM32_ATIM_CCR6_OFFSET)
+#endif
+
+/* 16-/32-bit General Timers - TIM2, TIM3, TIM4, and TIM5 with DMA.
+ * All timers are 16-bit except for TIM2 and 5 are 32-bit
+ */
+
+#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 0
+#  define STM32_TIM2_CR1          (STM32_TIM2_BASE+STM32_GTIM_CR1_OFFSET)
+#  define STM32_TIM2_CR2          (STM32_TIM2_BASE+STM32_GTIM_CR2_OFFSET)
+#  define STM32_TIM2_SMCR         (STM32_TIM2_BASE+STM32_GTIM_SMCR_OFFSET)
+#  define STM32_TIM2_DIER         (STM32_TIM2_BASE+STM32_GTIM_DIER_OFFSET)
+#  define STM32_TIM2_SR           (STM32_TIM2_BASE+STM32_GTIM_SR_OFFSET)
+#  define STM32_TIM2_EGR          (STM32_TIM2_BASE+STM32_GTIM_EGR_OFFSET)
+#  define STM32_TIM2_CCMR1        (STM32_TIM2_BASE+STM32_GTIM_CCMR1_OFFSET)
+#  define STM32_TIM2_CCMR2        (STM32_TIM2_BASE+STM32_GTIM_CCMR2_OFFSET)
+#  define STM32_TIM2_CCER         (STM32_TIM2_BASE+STM32_GTIM_CCER_OFFSET)
+#  define STM32_TIM2_CNT          (STM32_TIM2_BASE+STM32_GTIM_CNT_OFFSET)
+#  define STM32_TIM2_PSC          (STM32_TIM2_BASE+STM32_GTIM_PSC_OFFSET)
+#  define STM32_TIM2_ARR          (STM32_TIM2_BASE+STM32_GTIM_ARR_OFFSET)
+#  define STM32_TIM2_CCR1         (STM32_TIM2_BASE+STM32_GTIM_CCR1_OFFSET)
+#  define STM32_TIM2_CCR2         (STM32_TIM2_BASE+STM32_GTIM_CCR2_OFFSET)
+#  define STM32_TIM2_CCR3         (STM32_TIM2_BASE+STM32_GTIM_CCR3_OFFSET)
+#  define STM32_TIM2_CCR4         (STM32_TIM2_BASE+STM32_GTIM_CCR4_OFFSET)
+#  define STM32_TIM2_DCR          (STM32_TIM2_BASE+STM32_GTIM_DCR_OFFSET)
+#  define STM32_TIM2_DMAR         (STM32_TIM2_BASE+STM32_GTIM_DMAR_OFFSET)
+#  define STM32_TIM2_OR           (STM32_TIM2_BASE+STM32_GTIM_OR_OFFSET)
+#endif
+
+#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 1
+#  define STM32_TIM3_CR1          (STM32_TIM3_BASE+STM32_GTIM_CR1_OFFSET)
+#  define STM32_TIM3_CR2          (STM32_TIM3_BASE+STM32_GTIM_CR2_OFFSET)
+#  define STM32_TIM3_SMCR         (STM32_TIM3_BASE+STM32_GTIM_SMCR_OFFSET)
+#  define STM32_TIM3_DIER         (STM32_TIM3_BASE+STM32_GTIM_DIER_OFFSET)
+#  define STM32_TIM3_SR           (STM32_TIM3_BASE+STM32_GTIM_SR_OFFSET)
+#  define STM32_TIM3_EGR          (STM32_TIM3_BASE+STM32_GTIM_EGR_OFFSET)
+#  define STM32_TIM3_CCMR1        (STM32_TIM3_BASE+STM32_GTIM_CCMR1_OFFSET)
+#  define STM32_TIM3_CCMR2        (STM32_TIM3_BASE+STM32_GTIM_CCMR2_OFFSET)
+#  define STM32_TIM3_CCER         (STM32_TIM3_BASE+STM32_GTIM_CCER_OFFSET)
+#  define STM32_TIM3_CNT          (STM32_TIM3_BASE+STM32_GTIM_CNT_OFFSET)
+#  define STM32_TIM3_PSC          (STM32_TIM3_BASE+STM32_GTIM_PSC_OFFSET)
+#  define STM32_TIM3_ARR          (STM32_TIM3_BASE+STM32_GTIM_ARR_OFFSET)
+#  define STM32_TIM3_CCR1         (STM32_TIM3_BASE+STM32_GTIM_CCR1_OFFSET)
+#  define STM32_TIM3_CCR2         (STM32_TIM3_BASE+STM32_GTIM_CCR2_OFFSET)
+#  define STM32_TIM3_CCR3         (STM32_TIM3_BASE+STM32_GTIM_CCR3_OFFSET)
+#  define STM32_TIM3_CCR4         (STM32_TIM3_BASE+STM32_GTIM_CCR4_OFFSET)
+#  define STM32_TIM3_DCR          (STM32_TIM3_BASE+STM32_GTIM_DCR_OFFSET)
+#  define STM32_TIM3_DMAR         (STM32_TIM3_BASE+STM32_GTIM_DMAR_OFFSET)
+#endif
+
+#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 2
+#  define STM32_TIM4_CR1          (STM32_TIM4_BASE+STM32_GTIM_CR1_OFFSET)
+#  define STM32_TIM4_CR2          (STM32_TIM4_BASE+STM32_GTIM_CR2_OFFSET)
+#  define STM32_TIM4_SMCR         (STM32_TIM4_BASE+STM32_GTIM_SMCR_OFFSET)
+#  define STM32_TIM4_DIER         (STM32_TIM4_BASE+STM32_GTIM_DIER_OFFSET)
+#  define STM32_TIM4_SR           (STM32_TIM4_BASE+STM32_GTIM_SR_OFFSET)
+#  define STM32_TIM4_EGR          (STM32_TIM4_BASE+STM32_GTIM_EGR_OFFSET)
+#  define STM32_TIM4_CCMR1        (STM32_TIM4_BASE+STM32_GTIM_CCMR1_OFFSET)
+#  define STM32_TIM4_CCMR2        (STM32_TIM4_BASE+STM32_GTIM_CCMR2_OFFSET)
+#  define STM32_TIM4_CCER         (STM32_TIM4_BASE+STM32_GTIM_CCER_OFFSET)
+#  define STM32_TIM4_CNT          (STM32_TIM4_BASE+STM32_GTIM_CNT_OFFSET)
+#  define STM32_TIM4_PSC          (STM32_TIM4_BASE+STM32_GTIM_PSC_OFFSET)
+#  define STM32_TIM4_ARR          (STM32_TIM4_BASE+STM32_GTIM_ARR_OFFSET)
+#  define STM32_TIM4_CCR1         (STM32_TIM4_BASE+STM32_GTIM_CCR1_OFFSET)
+#  define STM32_TIM4_CCR2         (STM32_TIM4_BASE+STM32_GTIM_CCR2_OFFSET)
+#  define STM32_TIM4_CCR3         (STM32_TIM4_BASE+STM32_GTIM_CCR3_OFFSET)
+#  define STM32_TIM4_CCR4         (STM32_TIM4_BASE+STM32_GTIM_CCR4_OFFSET)
+#  define STM32_TIM4_DCR          (STM32_TIM4_BASE+STM32_GTIM_DCR_OFFSET)
+#  define STM32_TIM4_DMAR         (STM32_TIM4_BASE+STM32_GTIM_DMAR_OFFSET)
+#endif
+
+#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 3
+#  define STM32_TIM5_CR1          (STM32_TIM5_BASE+STM32_GTIM_CR1_OFFSET)
+#  define STM32_TIM5_CR2          (STM32_TIM5_BASE+STM32_GTIM_CR2_OFFSET)
+#  define STM32_TIM5_SMCR         (STM32_TIM5_BASE+STM32_GTIM_SMCR_OFFSET)
+#  define STM32_TIM5_DIER         (STM32_TIM5_BASE+STM32_GTIM_DIER_OFFSET)
+#  define STM32_TIM5_SR           (STM32_TIM5_BASE+STM32_GTIM_SR_OFFSET)
+#  define STM32_TIM5_EGR          (STM32_TIM5_BASE+STM32_GTIM_EGR_OFFSET)
+#  define STM32_TIM5_CCMR1        (STM32_TIM5_BASE+STM32_GTIM_CCMR1_OFFSET)
+#  define STM32_TIM5_CCMR2        (STM32_TIM5_BASE+STM32_GTIM_CCMR2_OFFSET)
+#  define STM32_TIM5_CCER         (STM32_TIM5_BASE+STM32_GTIM_CCER_OFFSET)
+#  define STM32_TIM5_CNT          (STM32_TIM5_BASE+STM32_GTIM_CNT_OFFSET)
+#  define STM32_TIM5_PSC          (STM32_TIM5_BASE+STM32_GTIM_PSC_OFFSET)
+#  define STM32_TIM5_ARR          (STM32_TIM5_BASE+STM32_GTIM_ARR_OFFSET)
+#  define STM32_TIM5_CCR1         (STM32_TIM5_BASE+STM32_GTIM_CCR1_OFFSET)
+#  define STM32_TIM5_CCR2         (STM32_TIM5_BASE+STM32_GTIM_CCR2_OFFSET)
+#  define STM32_TIM5_CCR3         (STM32_TIM5_BASE+STM32_GTIM_CCR3_OFFSET)
+#  define STM32_TIM5_CCR4         (STM32_TIM5_BASE+STM32_GTIM_CCR4_OFFSET)
+#  define STM32_TIM5_DCR          (STM32_TIM5_BASE+STM32_GTIM_DCR_OFFSET)
+#  define STM32_TIM5_DMAR         (STM32_TIM5_BASE+STM32_GTIM_DMAR_OFFSET)
+#  define STM32_TIM5_OR           (STM32_TIM5_BASE+STM32_GTIM_OR_OFFSET)
+#endif
+
+
+/* 16-bit General Timers - TIM9-14 without DMA.  Note that (1) these timers
+ * support only a subset of the general timer registers are supported, and
+ * (2) TIM9 and TIM12 differ from the others.
+ */
+
+#if STM32F7_NGTIMNDMA > 0
+#  define STM32_TIM9_CR1          (STM32_TIM9_BASE+STM32_GTIM_CR1_OFFSET)
+#  define STM32_TIM9_CR2          (STM32_TIM9_BASE+STM32_GTIM_CR2_OFFSET)
+#  define STM32_TIM9_DIER         (STM32_TIM9_BASE+STM32_GTIM_DIER_OFFSET)
+#  define STM32_TIM9_SR           (STM32_TIM9_BASE+STM32_GTIM_SR_OFFSET)
+#  define STM32_TIM9_EGR          (STM32_TIM9_BASE+STM32_GTIM_EGR_OFFSET)
+#  define STM32_TIM9_CCMR1        (STM32_TIM9_BASE+STM32_GTIM_CCMR1_OFFSET)
+#  define STM32_TIM9_CCER         (STM32_TIM9_BASE+STM32_GTIM_CCER_OFFSET)
+#  define STM32_TIM9_CNT          (STM32_TIM9_BASE+STM32_GTIM_CNT_OFFSET)
+#  define STM32_TIM9_PSC          (STM32_TIM9_BASE+STM32_GTIM_PSC_OFFSET)
+#  define STM32_TIM9_ARR          (STM32_TIM9_BASE+STM32_GTIM_ARR_OFFSET)
+#  define STM32_TIM9_CCR1         (STM32_TIM9_BASE+STM32_GTIM_CCR1_OFFSET)
+#  define STM32_TIM9_CCR2         (STM32_TIM9_BASE+STM32_GTIM_CCR2_OFFSET)
+#endif
+
+#if STM32F7_NGTIMNDMA > 1
+#  define STM32_TIM10_CR1         (STM32_TIM10_BASE+STM32_GTIM_CR1_OFFSET)
+#  define STM32_TIM10_DIER        (STM32_TIM10_BASE+STM32_GTIM_DIER_OFFSET)
+#  define STM32_TIM10_SR          (STM32_TIM10_BASE+STM32_GTIM_SR_OFFSET)
+#  define STM32_TIM10_EGR         (STM32_TIM10_BASE+STM32_GTIM_EGR_OFFSET)
+#  define STM32_TIM10_CCMR1       (STM32_TIM10_BASE+STM32_GTIM_CCMR1_OFFSET)
+#  define STM32_TIM10_CCER        (STM32_TIM10_BASE+STM32_GTIM_CCER_OFFSET)
+#  define STM32_TIM10_CNT         (STM32_TIM10_BASE+STM32_GTIM_CNT_OFFSET)
+#  define STM32_TIM10_PSC         (STM32_TIM10_BASE+STM32_GTIM_PSC_OFFSET)
+#  define STM32_TIM10_ARR         (STM32_TIM10_BASE+STM32_GTIM_ARR_OFFSET)
+#  define STM32_TIM10_CCR1        (STM32_TIM10_BASE+STM32_GTIM_CCR1_OFFSET)
+#endif
+
+#if STM32F7_NGTIMNDMA > 2
+#  define STM32_TIM11_CR1         (STM32_TIM11_BASE+STM32_GTIM_CR1_OFFSET)
+#  define STM32_TIM11_DIER        (STM32_TIM11_BASE+STM32_GTIM_DIER_OFFSET)
+#  define STM32_TIM11_SR          (STM32_TIM11_BASE+STM32_GTIM_SR_OFFSET)
+#  define STM32_TIM11_EGR         (STM32_TIM11_BASE+STM32_GTIM_EGR_OFFSET)
+#  define STM32_TIM11_CCMR1       (STM32_TIM11_BASE+STM32_GTIM_CCMR1_OFFSET)
+#  define STM32_TIM11_CCER        (STM32_TIM11_BASE+STM32_GTIM_CCER_OFFSET)
+#  define STM32_TIM11_CNT         (STM32_TIM11_BASE+STM32_GTIM_CNT_OFFSET)
+#  define STM32_TIM11_PSC         (STM32_TIM11_BASE+STM32_GTIM_PSC_OFFSET)
+#  define STM32_TIM11_ARR         (STM32_TIM11_BASE+STM32_GTIM_ARR_OFFSET)
+#  define STM32_TIM11_CCR1        (STM32_TIM11_BASE+STM32_GTIM_CCR1_OFFSET)
+#  define STM32_TIM11_OR          (STM32_TIM11_BASE+STM32_GTIM_OR_OFFSET)
+#endif
+
+#if STM32F7_NGTIMNDMA > 3
+#  define STM32_TIM12_CR1         (STM32_TIM12_BASE+STM32_GTIM_CR1_OFFSET)
+#  define STM32_TIM12_CR2         (STM32_TIM9_BASE+STM32_GTIM_CR2_OFFSET)
+#  define STM32_TIM12_DIER        (STM32_TIM12_BASE+STM32_GTIM_DIER_OFFSET)
+#  define STM32_TIM12_SR          (STM32_TIM12_BASE+STM32_GTIM_SR_OFFSET)
+#  define STM32_TIM12_EGR         (STM32_TIM12_BASE+STM32_GTIM_EGR_OFFSET)
+#  define STM32_TIM12_CCMR1       (STM32_TIM12_BASE+STM32_GTIM_CCMR1_OFFSET)
+#  define STM32_TIM12_CCER        (STM32_TIM12_BASE+STM32_GTIM_CCER_OFFSET)
+#  define STM32_TIM12_CNT         (STM32_TIM12_BASE+STM32_GTIM_CNT_OFFSET)
+#  define STM32_TIM12_PSC         (STM32_TIM12_BASE+STM32_GTIM_PSC_OFFSET)
+#  define STM32_TIM12_ARR         (STM32_TIM12_BASE+STM32_GTIM_ARR_OFFSET)
+#  define STM32_TIM12_CCR1        (STM32_TIM12_BASE+STM32_GTIM_CCR1_OFFSET)
+#  define STM32_TIM12_CCR2        (STM32_TIM12_BASE+STM32_GTIM_CCR2_OFFSET)
+#endif
+
+#if STM32F7_NGTIMNDMA > 4
+#  define STM32_TIM13_CR1         (STM32_TIM13_BASE+STM32_GTIM_CR1_OFFSET)
+#  define STM32_TIM13_DIER        (STM32_TIM13_BASE+STM32_GTIM_DIER_OFFSET)
+#  define STM32_TIM13_SR          (STM32_TIM13_BASE+STM32_GTIM_SR_OFFSET)
+#  define STM32_TIM13_EGR         (STM32_TIM13_BASE+STM32_GTIM_EGR_OFFSET)
+#  define STM32_TIM13_CCMR1       (STM32_TIM13_BASE+STM32_GTIM_CCMR1_OFFSET)
+#  define STM32_TIM13_CCER        (STM32_TIM13_BASE+STM32_GTIM_CCER_OFFSET)
+#  define STM32_TIM13_CNT         (STM32_TIM13_BASE+STM32_GTIM_CNT_OFFSET)
+#  define STM32_TIM13_PSC         (STM32_TIM13_BASE+STM32_GTIM_PSC_OFFSET)
+#  define STM32_TIM13_ARR         (STM32_TIM13_BASE+STM32_GTIM_ARR_OFFSET)
+#  define STM32_TIM13_CCR1        (STM32_TIM13_BASE+STM32_GTIM_CCR1_OFFSET)
+#endif
+
+#if STM32F7_NGTIMNDMA > 5
+#  define STM32_TIM14_CR1         (STM32_TIM14_BASE+STM32_GTIM_CR1_OFFSET)
+#  define STM32_TIM14_DIER        (STM32_TIM14_BASE+STM32_GTIM_DIER_OFFSET)
+#  define STM32_TIM14_SR          (STM32_TIM14_BASE+STM32_GTIM_SR_OFFSET)
+#  define STM32_TIM14_EGR         (STM32_TIM14_BASE+STM32_GTIM_EGR_OFFSET)
+#  define STM32_TIM14_CCMR1       (STM32_TIM14_BASE+STM32_GTIM_CCMR1_OFFSET)
+#  define STM32_TIM14_CCER        (STM32_TIM14_BASE+STM32_GTIM_CCER_OFFSET)
+#  define STM32_TIM14_CNT         (STM32_TIM14_BASE+STM32_GTIM_CNT_OFFSET)
+#  define STM32_TIM14_PSC         (STM32_TIM14_BASE+STM32_GTIM_PSC_OFFSET)
+#  define STM32_TIM14_ARR         (STM32_TIM14_BASE+STM32_GTIM_ARR_OFFSET)
+#  define STM32_TIM14_CCR1        (STM32_TIM14_BASE+STM32_GTIM_CCR1_OFFSET)
+#endif
+
+/* Basic Timers - TIM6 and TIM7 */
+
+#if STM32F7_NBTIM > 0
+#  define STM32_TIM6_CR1          (STM32_TIM6_BASE+STM32_BTIM_CR1_OFFSET)
+#  define STM32_TIM6_CR2          (STM32_TIM6_BASE+STM32_BTIM_CR2_OFFSET)
+#  define STM32_TIM6_DIER         (STM32_TIM6_BASE+STM32_BTIM_DIER_OFFSET)
+#  define STM32_TIM6_SR           (STM32_TIM6_BASE+STM32_BTIM_SR_OFFSET)
+#  define STM32_TIM6_EGR          (STM32_TIM6_BASE+STM32_BTIM_EGR_OFFSET)
+#  define STM32_TIM6_CNT          (STM32_TIM6_BASE+STM32_BTIM_CNT_OFFSET)
+#  define STM32_TIM6_PSC          (STM32_TIM6_BASE+STM32_BTIM_PSC_OFFSET)
+#  define STM32_TIM6_ARR          (STM32_TIM6_BASE+STM32_BTIM_ARR_OFFSET)
+#endif
+
+#if STM32F7_NBTIM > 1
+#  define STM32_TIM7_CR1          (STM32_TIM7_BASE+STM32_BTIM_CR1_OFFSET)
+#  define STM32_TIM7_CR2          (STM32_TIM7_BASE+STM32_BTIM_CR2_OFFSET)
+#  define STM32_TIM7_DIER         (STM32_TIM7_BASE+STM32_BTIM_DIER_OFFSET)
+#  define STM32_TIM7_SR           (STM32_TIM7_BASE+STM32_BTIM_SR_OFFSET)
+#  define STM32_TIM7_EGR          (STM32_TIM7_BASE+STM32_BTIM_EGR_OFFSET)
+#  define STM32_TIM7_CNT          (STM32_TIM7_BASE+STM32_BTIM_CNT_OFFSET)
+#  define STM32_TIM7_PSC          (STM32_TIM7_BASE+STM32_BTIM_PSC_OFFSET)
+#  define STM32_TIM7_ARR          (STM32_TIM7_BASE+STM32_BTIM_ARR_OFFSET)
+#endif
+
+/* Register Bitfield Definitions ********************************************************************/
+
+/* Control register 1 */
+
+#define ATIM_CR1_CEN              (1 << 0)  /* Bit 0: Counter enable */
+#define ATIM_CR1_UDIS             (1 << 1)  /* Bit 1: Update disable */
+#define ATIM_CR1_URS              (1 << 2)  /* Bit 2: Update request source */
+#define ATIM_CR1_OPM              (1 << 3)  /* Bit 3: One pulse mode */
+#define ATIM_CR1_DIR              (1 << 4)  /* Bit 4: Direction */
+#define ATIM_CR1_CMS_SHIFT        (5)       /* Bits 6-5: Center-aligned mode selection */
+#define ATIM_CR1_CMS_MASK         (3 << ATIM_CR1_CMS_SHIFT)
+#  define ATIM_CR1_EDGE           (0 << ATIM_CR1_CMS_SHIFT) /* 00: Edge-aligned mode */
+#  define ATIM_CR1_CENTER1        (1 << ATIM_CR1_CMS_SHIFT) /* 01: Center-aligned mode 1 */
+#  define ATIM_CR1_CENTER2        (2 << ATIM_CR1_CMS_SHIFT) /* 10: Center-aligned mode 2 */
+#  define ATIM_CR1_CENTER3        (3 << ATIM_CR1_CMS_SHIFT) /* 11: Center-aligned mode 3 */
+#define ATIM_CR1_ARPE             (1 << 7)  /* Bit 7: Auto-reload preload enable */
+#define ATIM_CR1_CKD_SHIFT        (8)       /* Bits 9-8: Clock division */
+#define ATIM_CR1_CKD_MASK         (3 << ATIM_CR1_CKD_SHIFT)
+#  define ATIM_CR1_TCKINT         (0 << ATIM_CR1_CKD_SHIFT) /* 00: tDTS=tCK_INT */
+#  define ATIM_CR1_2TCKINT        (1 << ATIM_CR1_CKD_SHIFT) /* 01: tDTS=2*tCK_INT */
+#  define ATIM_CR1_4TCKINT        (2 << ATIM_CR1_CKD_SHIFT) /* 10: tDTS=4*tCK_INT */
+#define ATIM_CR1_UIFREMAP         (1 << 11) /* Bit 11: UIF status bit remapping */
+
+/* Control register 2 */
+
+#define ATIM_CR2_CCPC             (1 << 0)  /* Bit 0:  Capture/Compare Preloaded Control */
+#define ATIM_CR2_CCUS             (1 << 2)  /* Bit 2:  Capture/Compare Control Update Selection */
+#define ATIM_CR2_CCDS             (1 << 3)  /* Bit 3:  Capture/Compare DMA Selection */
+#define ATIM_CR2_MMS_SHIFT        (4)       /* Bits 6-4: Master Mode Selection */
+#define ATIM_CR2_MMS_MASK         (7 << ATIM_CR2_MMS_SHIFT)
+#  define ATIM_CR2_MMS_RESET      (0 << ATIM_CR2_MMS_SHIFT) /* 000: Reset - TIMx_EGR UG bit is TRGO */
+#  define ATIM_CR2_MMS_ENABLE     (1 << ATIM_CR2_MMS_SHIFT) /* 001: Enable - CNT_EN is TRGO */
+#  define ATIM_CR2_MMS_UPDATE     (2 << ATIM_CR2_MMS_SHIFT) /* 010: Update event is TRGO */
+#  define ATIM_CR2_MMS_COMPP      (3 << ATIM_CR2_MMS_SHIFT) /* 010: Compare Pulse - CC1IF flag */
+#  define ATIM_CR2_MMS_OC1REF     (4 << ATIM_CR2_MMS_SHIFT) /* 100: Compare OC1REF is TRGO */
+#  define ATIM_CR2_MMS_OC2REF     (5 << ATIM_CR2_MMS_SHIFT) /* 101: Compare OC2REF is TRGO */
+#  define ATIM_CR2_MMS_OC3REF     (6 << ATIM_CR2_MMS_SHIFT) /* 110: Compare OC3REF is TRGO */
+#  define ATIM_CR2_MMS_OC4REF     (7 << ATIM_CR2_MMS_SHIFT) /* 111: Compare OC4REF is TRGO */
+#define ATIM_CR2_TI1S             (1 << 7)  /* Bit 7: TI1 Selection */
+#define ATIM_CR2_OIS1             (1 << 8)  /* Bit 8:  Output Idle state 1 (OC1 output) */
+#define ATIM_CR2_OIS1N            (1 << 9)  /* Bit 9:  Output Idle state 1 (OC1N output) */
+#define ATIM_CR2_OIS2             (1 << 10) /* Bit 10: Output Idle state 2 (OC2 output) */
+#define ATIM_CR2_OIS2N            (1 << 11) /* Bit 11: Output Idle state 2 (OC2N output) */
+#define ATIM_CR2_OIS3             (1 << 12) /* Bit 12: Output Idle state 3 (OC3 output) */
+#define ATIM_CR2_OIS3N            (1 << 13) /* Bit 13: Output Idle state 3 (OC3N output) */
+#define ATIM_CR2_OIS4             (1 << 14) /* Bit 14: Output Idle state 4 (OC4 output) */
+#define ATIM_CR2_OIS5             (1 << 16) /* Bit 16: OOutput Idle state 5 (OC5 output) */
+#define ATIM_CR2_OIS6             (1 << 18) /* Bit 18: Output Idle state 6 (OC6 output) */
+#define ATIM_CR2_MMS2_SHIFT       (20)      /* Bits 20-23: Master Mode Selection 2 */
+#define ATIM_CR2_MMS2_MASK        (15 << ATIM_CR2_MMS2_SHIFT)
+#  define ATIM_CR2_MMS2_RESET     (0 << ATIM_CR2_MMS2_SHIFT)  /* 0000: Reset - TIMx_EGR UG bit is TRG9 */
+#  define ATIM_CR2_MMS2_ENABLE    (1 << ATIM_CR2_MMS2_SHIFT)  /* 0001: Enable - CNT_EN is TRGO2 */
+#  define ATIM_CR2_MMS2_UPDATE    (2 << ATIM_CR2_MMS2_SHIFT)  /* 0010: Update event is TRGH0*/
+#  define ATIM_CR2_MMS2_COMPP     (3 << ATIM_CR2_MMS2_SHIFT)  /* 0010: Compare Pulse - CC1IF flag */
+#  define ATIM_CR2_MMS2_OC1REF    (4 << ATIM_CR2_MMS2_SHIFT)  /* 0100: Compare OC1REF is TRGO2 */
+#  define ATIM_CR2_MMS2_OC2REF    (5 << ATIM_CR2_MMS2_SHIFT)  /* 0101: Compare OC2REF is TRGO2 */
+#  define ATIM_CR2_MMS2_OC3REF    (6 << ATIM_CR2_MMS2_SHIFT)  /* 0110: Compare OC3REF is TRGO2 */
+#  define ATIM_CR2_MMS2_OC4REF    (7 << ATIM_CR2_MMS2_SHIFT)  /* 0111: Compare OC4REF is TRGO2 */
+#  define ATIM_CR2_MMS2_OC5REF    (8 << ATIM_CR2_MMS2_SHIFT)  /* 1000: Compare OC5REF is TRGO2 */
+#  define ATIM_CR2_MMS2_OC6REF    (9 << ATIM_CR2_MMS2_SHIFT)  /* 1001: Compare OC6REF is TRGO2 */
+#  define ATIM_CR2_MMS2_CMPOC4    (10 << ATIM_CR2_MMS2_SHIFT) /* 1010: Compare pulse - OC4REF edge is TRGO2 */
+#  define ATIM_CR2_MMS2_CMPOC6    (11 << ATIM_CR2_MMS2_SHIFT) /* 1011: Compare pulse - OC6REF edge is TRGO2 */
+#  define ATIM_CR2_MMS2_CMPOC4R6R (12 << ATIM_CR2_MMS2_SHIFT) /* 1100: Compare pulse - OC4REF/OC6REF rising */
+#  define ATIM_CR2_MMS2_CMPOC4R6F (13 << ATIM_CR2_MMS2_SHIFT) /* 1101: Compare pulse - OC4REF rising/OC6REF falling */
+#  define ATIM_CR2_MMS2_CMPOC5R6R (14 << ATIM_CR2_MMS2_SHIFT) /* 1110: Compare pulse - OC5REF/OC6REF rising */
+#  define ATIM_CR2_MMS2_CMPOC5R6F (15 << ATIM_CR2_MMS2_SHIFT) /* 1111: Compare pulse - OC5REF rising/OC6REF falling */
+
+/* Slave mode control register */
+
+#define ATIM_SMCR_SMS_SHIFT       (0)       /* Bits 0-2: Slave mode selection */
+#define ATIM_SMCR_SMS_MASK        (7 << ATIM_SMCR_SMS_SHIFT)
+#  define ATIM_SMCR_DISAB         (0 << ATIM_SMCR_SMS_SHIFT) /* 000: Slave mode disabled */
+#  define ATIM_SMCR_ENCMD1        (1 << ATIM_SMCR_SMS_SHIFT) /* 001: Encoder mode 1 */
+#  define ATIM_SMCR_ENCMD2        (2 << ATIM_SMCR_SMS_SHIFT) /* 010: Encoder mode 2 */
+#  define ATIM_SMCR_ENCMD3        (3 << ATIM_SMCR_SMS_SHIFT) /* 011: Encoder mode 3 */
+#  define ATIM_SMCR_RESET         (4 << ATIM_SMCR_SMS_SHIFT) /* 100: Reset Mode */
+#  define ATIM_SMCR_GATED         (5 << ATIM_SMCR_SMS_SHIFT) /* 101: Gated Mode */
+#  define ATIM_SMCR_TRIGGER       (6 << ATIM_SMCR_SMS_SHIFT) /* 110: Trigger Mode */
+#  define ATIM_SMCR_EXTCLK1       (7 << ATIM_SMCR_SMS_SHIFT) /* 111: External Clock Mode 1 */
+#define ATIM_SMCR_TS_SHIFT        (4)       /* Bits 4-6: Trigger selection */
+#define ATIM_SMCR_TS_MASK         (7 << ATIM_SMCR_TS_SHIFT)
+#  define ATIM_SMCR_ITR0          (0 << ATIM_SMCR_TS_SHIFT) /* 000: Internal trigger 0 (ITR0) */
+#  define ATIM_SMCR_ITR1          (1 << ATIM_SMCR_TS_SHIFT) /* 001: Internal trigger 1 (ITR1) */
+#  define ATIM_SMCR_ITR2          (2 << ATIM_SMCR_TS_SHIFT) /* 010: Internal trigger 2 (ITR2) */
+#  define ATIM_SMCR_ITR3          (3 << ATIM_SMCR_TS_SHIFT) /* 011: Internal trigger 3 (ITR3) */
+#  define ATIM_SMCR_T1FED         (4 << ATIM_SMCR_TS_SHIFT) /* 100: TI1 Edge Detector (TI1F_ED) */
+#  define ATIM_SMCR_TI1FP1        (5 << ATIM_SMCR_TS_SHIFT) /* 101: Filtered Timer Input 1 (TI1FP1) */
+#  define ATIM_SMCR_T12FP2        (6 << ATIM_SMCR_TS_SHIFT) /* 110: Filtered Timer Input 2 (TI2FP2) */
+#  define ATIM_SMCR_ETRF          (7 << ATIM_SMCR_TS_SHIFT) /* 111: External Trigger input (ETRF) */
+#define ATIM_SMCR_MSM             (1 << 7)  /* Bit 7: Master/slave mode */
+#define ATIM_SMCR_ETF_SHIFT       (8)       /* Bits 8-11: External trigger filter */
+#define ATIM_SMCR_ETF_MASK        (0x0f << ATIM_SMCR_ETF_SHIFT)
+#  define ATIM_SMCR_NOFILT        (0 << ATIM_SMCR_ETF_SHIFT) /* 0000: No filter, sampling is done at fDTS */
+#  define ATIM_SMCR_FCKINT2       (1 << ATIM_SMCR_ETF_SHIFT) /* 0001: fSAMPLING=fCK_INT, N=2 */
+#  define ATIM_SMCR_FCKINT4       (2 << ATIM_SMCR_ETF_SHIFT) /* 0010: fSAMPLING=fCK_INT, N=4 */
+#  define ATIM_SMCR_FCKINT8       (3 << ATIM_SMCR_ETF_SHIFT) /* 0011: fSAMPLING=fCK_INT, N=8 */
+#  define ATIM_SMCR_FDTSd26       (4 << ATIM_SMCR_ETF_SHIFT) /* 0100: fSAMPLING=fDTS/2, N=6 */
+#  define ATIM_SMCR_FDTSd28       (5 << ATIM_SMCR_ETF_SHIFT) /* 0101: fSAMPLING=fDTS/2, N=8 */
+#  define ATIM_SMCR_FDTSd46       (6 << ATIM_SMCR_ETF_SHIFT) /* 0110: fSAMPLING=fDTS/4, N=6 */
+#  define ATIM_SMCR_FDTSd48       (7 << ATIM_SMCR_ETF_SHIFT) /* 0111: fSAMPLING=fDTS/4, N=8 */
+#  define ATIM_SMCR_FDTSd86       (8 << ATIM_SMCR_ETF_SHIFT) /* 1000: fSAMPLING=fDTS/8, N=6 */
+#  define ATIM_SMCR_FDTSd88       (9 << ATIM_SMCR_ETF_SHIFT) /* 1001: fSAMPLING=fDTS/8, N=8 */
+#  define ATIM_SMCR_FDTSd165      (10 << ATIM_SMCR_ETF_SHIFT) /* 1010: fSAMPLING=fDTS/16, N=5 */
+#  define ATIM_SMCR_FDTSd166      (11 << ATIM_SMCR_ETF_SHIFT) /* 1011: fSAMPLING=fDTS/16, N=6 */
+#  define ATIM_SMCR_FDTSd168      (12 << ATIM_SMCR_ETF_SHIFT) /* 1100: fSAMPLING=fDTS/16, N=8 */
+#  define ATIM_SMCR_FDTSd325      (13 << ATIM_SMCR_ETF_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */
+#  define ATIM_SMCR_FDTSd326      (14 << ATIM_SMCR_ETF_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */
+#  define ATIM_SMCR_FDTSd328      (15 << ATIM_SMCR_ETF_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */
+#define ATIM_SMCR_ETPS_SHIFT      (12)      /* Bits 12-13: External trigger prescaler */
+#define ATIM_SMCR_ETPS_MASK       (3 << ATIM_SMCR_ETPS_SHIFT)
+#  define ATIM_SMCR_PSCOFF        (0 << ATIM_SMCR_ETPS_SHIFT) /* 00: Prescaler OFF */
+#  define ATIM_SMCR_ETRPd2        (1 << ATIM_SMCR_ETPS_SHIFT) /* 01: ETRP frequency divided by 2 */
+#  define ATIM_SMCR_ETRPd4        (2 << ATIM_SMCR_ETPS_SHIFT) /* 10: ETRP frequency divided by 4 */
+#  define ATIM_SMCR_ETRPd8        (3 << ATIM_SMCR_ETPS_SHIFT) /* 11: ETRP frequency divided by 8 */
+#define ATIM_SMCR_ECE             (1 << 14) /* Bit 14: External clock enable */
+#define ATIM_SMCR_ETP             (1 << 15) /* Bit 15: External trigger polarity */
+#define ATIM_SMCR_SMS             (1 << 16) /* Bit 16: Slave mode selection - bit 3 */
+
+/* DMA/Interrupt enable register */
+
+#define ATIM_DIER_UIE             (1 << 0)  /* Bit 0: Update interrupt enable */
+#define ATIM_DIER_CC1IE           (1 << 1)  /* Bit 1: Capture/Compare 1 interrupt enable */
+#define ATIM_DIER_CC2IE           (1 << 2)  /* Bit 2: Capture/Compare 2 interrupt enable */
+#define ATIM_DIER_CC3IE           (1 << 3)  /* Bit 3: Capture/Compare 3 interrupt enable */
+#define ATIM_DIER_CC4IE           (1 << 4)  /* Bit 4: Capture/Compare 4 interrupt enable */
+#define ATIM_DIER_COMIE           (1 << 5)  /* Bit 5: COM interrupt enable */
+#define ATIM_DIER_TIE             (1 << 6)  /* Bit 6: Trigger interrupt enable */
+#define ATIM_DIER_BIE             (1 << 7)  /* Bit 7: Break interrupt enable */
+#define ATIM_DIER_UDE             (1 << 8)  /* Bit 8: Update DMA request enable */
+#define ATIM_DIER_CC1DE           (1 << 9)  /* Bit 9: Capture/Compare 1 DMA request enable */
+#define ATIM_DIER_CC2DE           (1 << 10) /* Bit 10: Capture/Compare 2 DMA request enable */
+#define ATIM_DIER_CC3DE           (1 << 11) /* Bit 11: Capture/Compare 3 DMA request enable */
+#define ATIM_DIER_CC4DE           (1 << 12) /* Bit 12: Capture/Compare 4 DMA request enable */
+#define ATIM_DIER_COMDE           (1 << 13) /* Bit 13: COM DMA request enable */
+#define ATIM_DIER_TDE             (1 << 14) /* Bit 14: Trigger DMA request enable */
+
+/* Status register */
+
+#define ATIM_SR_UIF               (1 << 0)  /* Bit 0:  Update interrupt Flag */
+#define ATIM_SR_CC1IF             (1 << 1)  /* Bit 1:  Capture/Compare 1 interrupt Flag */
+#define ATIM_SR_CC2IF             (1 << 2)  /* Bit 2:  Capture/Compare 2 interrupt Flag */
+#define ATIM_SR_CC3IF             (1 << 3)  /* Bit 3:  Capture/Compare 3 interrupt Flag */
+#define ATIM_SR_CC4IF             (1 << 4)  /* Bit 4:  Capture/Compare 4 interrupt Flag */
+#define ATIM_SR_COMIF             (1 << 5)  /* Bit 5:  COM interrupt Flag */
+#define ATIM_SR_TIF               (1 << 6)  /* Bit 6:  Trigger interrupt Flag */
+#define ATIM_SR_BIF               (1 << 7)  /* Bit 7:  Break interrupt Flag */
+#define ATIM_SR_B2IF              (1 << 8)  /* Bit 8:  Break 2 interrupt Flag */
+#define ATIM_SR_CC1OF             (1 << 9)  /* Bit 9:  Capture/Compare 1 Overcapture Flag */
+#define ATIM_SR_CC2OF             (1 << 10) /* Bit 10: Capture/Compare 2 Overcapture Flag */
+#define ATIM_SR_CC3OF             (1 << 11) /* Bit 11: Capture/Compare 3 Overcapture Flag */
+#define ATIM_SR_CC4OF             (1 << 12) /* Bit 12: Capture/Compare 4 Overcapture Flag */
+#define ATIM_SR_CC5IF             (1 << 16) /* Bit 16: Compare 5 interrupt flag */
+#define ATIM_SR_CC6IF             (1 << 17) /* Bit 17: Compare 6 interrupt flag */
+
+/* Event generation register */
+
+#define ATIM_EGR_UG               (1 << 0)  /* Bit 0: Update Generation */
+#define ATIM_EGR_CC1G             (1 << 1)  /* Bit 1: Capture/Compare 1 Generation */
+#define ATIM_EGR_CC2G             (1 << 2)  /* Bit 2: Capture/Compare 2 Generation */
+#define ATIM_EGR_CC3G             (1 << 3)  /* Bit 3: Capture/Compare 3 Generation */
+#define ATIM_EGR_CC4G             (1 << 4)  /* Bit 4: Capture/Compare 4 Generation */
+#define ATIM_EGR_COMG             (1 << 5)  /* Bit 5: Capture/Compare Control Update Generation */
+#define ATIM_EGR_TG               (1 << 6)  /* Bit 6: Trigger Generation */
+#define ATIM_EGR_BG               (1 << 7)  /* Bit 7: Break Generation */
+#define ATIM_EGR_B2G              (1 << 8)  /* Bit 8: Break 2 Generation */
+
+/* Capture/compare mode register 1 -- Output compare mode */
+
+#define ATIM_CCMR1_CC1S_SHIFT     (0)       /* Bits 1-0: Capture/Compare 1 Selection */
+#define ATIM_CCMR1_CC1S_MASK      (3 << ATIM_CCMR1_CC1S_SHIFT)
+                                            /* (See common (unshifted) bit field definitions below) */
+#define ATIM_CCMR1_OC1FE          (1 << 2)  /* Bit 2: Output Compare 1 Fast enable */
+#define ATIM_CCMR1_OC1PE          (1 << 3)  /* Bit 3: Output Compare 1 Preload enable */
+#define ATIM_CCMR1_OC1M_SHIFT     (4)       /* Bits 6-4: Output Compare 1 Mode */
+#define ATIM_CCMR1_OC1M_MASK      (7 << ATIM_CCMR1_OC1M_SHIFT)
+                                            /* (See common (unshifted) bit field definitions below) */
+#define ATIM_CCMR1_OC1CE          (1 << 7)  /* Bit 7: Output Compare 1Clear Enable */
+#define ATIM_CCMR1_CC2S_SHIFT     (8)       /* Bits 8-9: Capture/Compare 2 Selection */
+#define ATIM_CCMR1_CC2S_MASK      (3 << ATIM_CCMR1_CC2S_SHIFT)
+                                            /* (See common (unshifted) bit field definitions below) */
+#define ATIM_CCMR1_OC2FE          (1 << 10) /* Bit 10: Output Compare 2 Fast enable */
+#define ATIM_CCMR1_OC2PE          (1 << 11) /* Bit 11: Output Compare 2 Preload enable */
+#define ATIM_CCMR1_OC2M_SHIFT     (12)      /* Bits 14-12: Output Compare 2 Mode */
+#define ATIM_CCMR1_OC2M_MASK      (7 << ATIM_CCMR1_OC2M_SHIFT)
+                                            /* (See common (unshifted) bit field definitions below) */
+#define ATIM_CCMR1_OC2CE          (1 << 15) /* Bit 15: Output Compare 2 Clear Enable */
+#define ATIM_CCMR1_OC1M           (1 << 16) /* Bit 16: Output Compare 1 mode - bit 3 */
+#define ATIM_CCMR1_OC2M           (1 << 24) /* Bit 24: Output Compare 2 mode - bit 3 */
+
+
+/* Common CCMR (unshifted) Capture/Compare Selection bit-field definitions */
+
+#define ATIM_CCMR_CCS_CCOUT       (0)       /* 00: CCx channel  output */
+#define ATIM_CCMR_CCS_CCIN1       (1)       /* 01: CCx channel input, ICx is TIx */
+#define ATIM_CCMR_CCS_CCIN2       (2)       /* 10: CCx channel input, ICx is TIy */
+#define ATIM_CCMR_CCS_CCINTRC     (3)       /* 11: CCx channel input, ICx is TRC */
+
+/* Common CCMR (unshifted) Compare Mode bit field definitions */
+
+#define ATIM_CCMR_MODE_FRZN        (0)      /* 0000: Frozen */
+#define ATIM_CCMR_MODE_CHACT       (1)      /* 0001: Channel x active on match */
+#define ATIM_CCMR_MODE_CHINACT     (2)      /* 0010: Channel x inactive on match */
+#define ATIM_CCMR_MODE_OCREFTOG    (3)      /* 0011: OCxREF toggle ATIM_CNT=ATIM_CCRx */
+#define ATIM_CCMR_MODE_OCREFLO     (4)      /* 0100: OCxREF forced low */
+#define ATIM_CCMR_MODE_OCREFHI     (5)      /* 0101: OCxREF forced high */
+#define ATIM_CCMR_MODE_PWM1        (6)      /* 0110: PWM mode 1 */
+#define ATIM_CCMR_MODE_PWM2        (7)      /* 0111: PWM mode 2 */
+#define ATIM_CCMR_MODE_OPM1        (8)      /* 1000: Retrigerrable OPM mode 1 */
+#define ATIM_CCMR_MODE_OPM2        (9)      /* 1001: Retrigerrable OPM mode 2 */
+#define ATIM_CCMR_MODE_COMBINED1   (12)     /* 1100: Combined PWM mode 1 */
+#define ATIM_CCMR_MODE_COMBINED2   (13)     /* 1101: Combined PWM mode 2 */
+#define ATIM_CCMR_MODE_ASYMMETRIC1 (14)     /* 1110: Asymmetric PWM mode 1 */
+#define ATIM_CCMR_MODE_ASYMMETRIC2 (15)     /* 1111: Asymmetric PWM mode 2 */
+
+/* Capture/compare mode register 1 -- Input capture mode */
+
+                                            /* Bits 1-0:(same as output compare mode) */
+#define ATIM_CCMR1_IC1PSC_SHIFT   (2)       /* Bits 3-2: Input Capture 1 Prescaler */
+#define ATIM_CCMR1_IC1PSC_MASK    (3 << ATIM_CCMR1_IC1PSC_SHIFT)
+                                            /* (See common (unshifted) bit field definitions below) */
+#define ATIM_CCMR1_IC1F_SHIFT     (4)       /* Bits 7-4: Input Capture 1 Filter */
+#define ATIM_CCMR1_IC1F_MASK      (0x0f << ATIM_CCMR1_IC1F_SHIFT)
+                                            /* (See common (unshifted) bit field definitions below) */
+                                            /* Bits 9:8 (same as output compare mode) */
+#define ATIM_CCMR1_IC2PSC_SHIFT   (10)      /* Bits 11:10: Input Capture 2 Prescaler */
+#define ATIM_CCMR1_IC2PSC_MASK    (3 << ATIM_CCMR1_IC2PSC_SHIFT)
+                                            /* (See common (unshifted) bit field definitions below) */
+#define ATIM_CCMR1_IC2F_SHIFT     (12)      /* Bits 15-12: Input Capture 2 Filter */
+#define ATIM_CCMR1_IC2F_MASK      (0x0f << ATIM_CCMR1_IC2F_SHIFT)
+                                            /* (See common (unshifted) bit field definitions below) */
+
+/* Common CCMR (unshifted) Input Capture Prescaler bit-field definitions */
+
+#define ATIM_CCMR_ICPSC_NOPSC     (0)       /* 00: no prescaler, capture each edge */
+#define ATIM_CCMR_ICPSC_EVENTS2   (1)       /* 01: capture once every 2 events */
+#define ATIM_CCMR_ICPSC_EVENTS4   (2)       /* 10: capture once every 4 events */
+#define ATIM_CCMR_ICPSC_EVENTS8   (3)       /* 11: capture once every 8 events */
+
+/* Common CCMR (unshifted) Input Capture Filter bit-field definitions */
+
+#define ATIM_CCMR_ICF_NOFILT      (0)       /* 0000: No filter, sampling at fDTS */
+#define ATIM_CCMR_ICF_FCKINT2     (1)       /* 0001: fSAMPLING=fCK_INT, N=2 */
+#define ATIM_CCMR_ICF_FCKINT4     (2)       /* 0010: fSAMPLING=fCK_INT, N=4 */
+#define ATIM_CCMR_ICF_FCKINT8     (3)       /* 0011: fSAMPLING=fCK_INT, N=8 */
+#define ATIM_CCMR_ICF_FDTSd26     (4)       /* 0100: fSAMPLING=fDTS/2, N=6 */
+#define ATIM_CCMR_ICF_FDTSd28     (5)       /* 0101: fSAMPLING=fDTS/2, N=8 */
+#define ATIM_CCMR_ICF_FDTSd46     (6)       /* 0110: fSAMPLING=fDTS/4, N=6 */
+#define ATIM_CCMR_ICF_FDTSd48     (7)       /* 0111: fSAMPLING=fDTS/4, N=8 */
+#define ATIM_CCMR_ICF_FDTSd86     (8)       /* 1000: fSAMPLING=fDTS/8, N=6 */
+#define ATIM_CCMR_ICF_FDTSd88     (9)       /* 1001: fSAMPLING=fDTS/8, N=8 */
+#define ATIM_CCMR_ICF_FDTSd165    (10)      /* 1010: fSAMPLING=fDTS/16, N=5 */
+#define ATIM_CCMR_ICF_FDTSd166    (11)      /* 1011: fSAMPLING=fDTS/16, N=6 */
+#define ATIM_CCMR_ICF_FDTSd168    (12)      /* 1100: fSAMPLING=fDTS/16, N=8 */
+#define ATIM_CCMR_ICF_FDTSd325    (13)      /* 1101: fSAMPLING=fDTS/32, N=5 */
+#define ATIM_CCMR_ICF_FDTSd326    (14)      /* 1110: fSAMPLING=fDTS/32, N=6 */
+#define ATIM_CCMR_ICF_FDTSd328    (15)      /* 1111: fSAMPLING=fDTS/32, N=8 */
+
+/* Capture/compare mode register 2 - Output Compare mode */
+
+#define ATIM_CCMR2_CC3S_SHIFT     (0)       /* Bits 1-0: Capture/Compare 3 Selection */
+#define ATIM_CCMR2_CC3S_MASK      (3 << ATIM_CCMR2_CC3S_SHIFT)
+                                            /* (See common (unshifted) bit field definitions above) */
+#define ATIM_CCMR2_OC3FE          (1 << 2)  /* Bit 2: Output Compare 3 Fast enable */
+#define ATIM_CCMR2_OC3PE          (1 << 3)  /* Bit 3: Output Compare 3 Preload enable */
+#define ATIM_CCMR2_OC3M_SHIFT     (4)       /* Bits 6-4: Output Compare 3 Mode */
+#define ATIM_CCMR2_OC3M_MASK      (7 << ATIM_CCMR2_OC3M_SHIFT)
+                                            /* (See common (unshifted) bit field definitions above) */
+#define ATIM_CCMR2_OC3CE          (1 << 7)  /* Bit 7: Output Compare 3 Clear Enable */
+#define ATIM_CCMR2_CC4S_SHIFT     (8)       /* Bits 9-8: Capture/Compare 4 Selection */
+#define ATIM_CCMR2_CC4S_MASK      (3 << ATIM_CCMR2_CC4S_SHIFT)
+                                            /* (See common (unshifted) bit field definitions above) */
+#define ATIM_CCMR2_OC4FE          (1 << 10) /* Bit 10: Output Compare 4 Fast enable */
+#define ATIM_CCMR2_OC4PE          (1 << 11) /* Bit 11: Output Compare 4 Preload enable */
+#define ATIM_CCMR2_OC4M_SHIFT     (12)      /* Bits 14-12: Output Compare 4 Mode */
+#define ATIM_CCMR2_OC4M_MASK      (7 << ATIM_CCMR2_OC4M_SHIFT)
+                                            /* (See common (unshifted) bit field definitions above) */
+#define ATIM_CCMR2_OC4CE          (1 << 15) /* Bit 15: Output Compare 4 Clear Enable */
+#define ATIM_CCMR2_OC3M           (1 << 16) /* Bit 16: Output Compare 3 mode - bit 3 */
+#define ATIM_CCMR2_OC4M           (1 << 24) /* Bit 24: Output Compare 4 mode - bit 3 */
+
+/* Capture/compare mode register 2 - Input Capture Mode */
+
+                                            /* Bits 1-0:(same as output compare mode) */
+#define ATIM_CCMR2_IC3PSC_SHIFT   (2)       /* Bits 3-2: Input Capture 3 Prescaler */
+#define ATIM_CCMR1_IC3PSC_MASK    (3 << ATIM_CCMR2_IC3PSC_SHIFT)
+                                            /* (See common (unshifted) bit field definitions above) */
+#define ATIM_CCMR2_IC3F_SHIFT     (4)       /* Bits 7-4: Input Capture 3 Filter */
+#define ATIM_CCMR2_IC3F_MASK      (0x0f << ATIM_CCMR2_IC3F_SHIFT)
+                                            /* (See common (unshifted) bit field definitions above) */
+                                            /* Bits 9:8 (same as output compare mode) */
+#define ATIM_CCMR2_IC4PSC_SHIFT   (10)      /* Bits 11:10: Input Capture 4 Prescaler */
+#define ATIM_CCMR2_IC4PSC_MASK    (3 << ATIM_CCMR2_IC4PSC_SHIFT)
+                                            /* (See common (unshifted) bit field definitions above) */
+#define ATIM_CCMR2_IC4F_SHIFT     (12)      /* Bits 15-12: Input Capture 4 Filter */
+#define ATIM_CCMR2_IC4F_MASK      (0x0f << ATIM_CCMR2_IC4F_SHIFT)
+                                            /* (See common (unshifted) bit field definitions above) */
+
+/* Capture/compare mode register 3 -- Output compare mode */
+
+#define ATIM_CCMR3_OC5FE          (1 << 2)  /* Bit 2: Output Compare 5 Fast enable */
+#define ATIM_CCMR3_OC5PE          (1 << 3)  /* Bit 3: Output Compare 5 Preload enable */
+#define ATIM_CCMR3_OC5M_SHIFT     (4)       /* Bits 6-4: Output Compare 5 Mode */
+#define ATIM_CCMR3_OC5M_MASK      (7 << ATIM_CCMR3_OC5M_SHIFT)
+                                            /* (See common (unshifted) bit field definitions below) */
+#define ATIM_CCMR3_OC5CE          (1 << 7)  /* Bit 7: Output Compare 5 Clear Enable */
+#define ATIM_CCMR3_OC6FE          (1 << 10) /* Bit 10: Output Compare 6 Fast enable */
+#define ATIM_CCMR3_OC6PE          (1 << 11) /* Bit 11: Output Compare 6 Preload enable */
+#define ATIM_CCMR3_OC6M_SHIFT     (12)      /* Bits 14-12: Output Compare 7 Mode */
+#define ATIM_CCMR3_OC6M_MASK      (7 << ATIM_CCMR3_OC6M_SHIFT)
+                                            /* (See common (unshifted) bit field definitions below) */
+#define ATIM_CCMR3_OC6CE          (1 << 15) /* Bit 15: Output Compare 7 Clear Enable */
+#define ATIM_CCMR3_OC5M           (1 << 16) /* Bit 16: Output Compare 5 mode - bit 3 */
+#define ATIM_CCMR3_OC6M           (1 << 24) /* Bit 24: Output Compare 6 mode - bit 3 */
+                                            
+
+/* Capture/compare enable register */
+
+#define ATIM_CCER_CC1E            (1 << 0)  /* Bit 0: Capture/Compare 1 output enable */
+#define ATIM_CCER_CC1P            (1 << 1)  /* Bit 1: Capture/Compare 1 output Polarity */
+#define ATIM_CCER_CC1NE           (1 << 2)  /* Bit 2: Capture/Compare 1 Complementary output enable */
+#define ATIM_CCER_CC1NP           (1 << 3)  /* Bit 3: Capture/Compare 1 Complementary output polarity */
+#define ATIM_CCER_CC2E            (1 << 4)  /* Bit 4: Capture/Compare 2 output enable */
+#define ATIM_CCER_CC2P            (1 << 5)  /* Bit 5: Capture/Compare 2 output Polarity */
+#define ATIM_CCER_CC2NE           (1 << 6)  /* Bit 6: Capture/Compare 2 Complementary output enable */
+#define ATIM_CCER_CC2NP           (1 << 7)  /* Bit 7: Capture/Compare 2 Complementary output polarity */
+#define ATIM_CCER_CC3E            (1 << 8)  /* Bit 8: Capture/Compare 3 output enable */
+#define ATIM_CCER_CC3P            (1 << 9)  /* Bit 9: Capture/Compare 3 output Polarity */
+#define ATIM_CCER_CC3NE           (1 << 10) /* Bit 10: Capture/Compare 3 Complementary output enable */
+#define ATIM_CCER_CC3NP           (1 << 11) /* Bit 11: Capture/Compare 3 Complementary output polarity */
+#define ATIM_CCER_CC4E            (1 << 12) /* Bit 12: Capture/Compare 4 output enable */
+#define ATIM_CCER_CC4P            (1 << 13) /* Bit 13: Capture/Compare 4 output Polarity */
+#define ATIM_CCER_CC4NP           (1 << 15) /* Bit 15: Capture/Compare 4 Complementary output polarity */
+#define ATIM_CCER_CC5E            (1 << 16) /* Bit 16: Capture/Compare 5 output enable */
+#define ATIM_CCER_CC5P            (1 << 17) /* Bit 17: Capture/Compare 5 output Polarity */
+#define ATIM_CCER_CC6E            (1 << 20) /* Bit 20: Capture/Compare 6 output enable */
+#define ATIM_CCER_CC6P            (1 << 21) /* Bit 21: Capture/Compare 6 output Polarity */
+
+
+/* 16-bit counter register */
+
+#define ATIM_CNT_SHIFT            (0)       /* Bits 0-15: Timer counter value */
+#define ATIM_CNT_MASK             (0xffff << ATIM_CNT_SHIFT)
+
+/* Repetition counter register */
+
+#define ATIM_RCR_REP_SHIFT        (0)       /* Bits 0-15: Repetition Counter Value */
+#define ATIM_RCR_REP_MASK         (0xffff << ATIM_RCR_REP_SHIFT)
+
+#define ATIM_RCR_REP_MAX          65536
+
+/* Capture/compare registers (CCR) */
+
+#define ATIM_CCR5_GC5C1           (1 << 29)  /* Bit 29: Group Channel 5 and Channel 1 */
+#define ATIM_CCR5_GC5C2           (1 << 30)  /* Bit 30: Group Channel 5 and Channel 2 */
+#define ATIM_CCR5_GC5C3           (1 << 31)  /* Bit 31: Group Channel 5 and Channel 3 */
+
+#define ATIM_CCR_MASK             (0xffff)
+
+/* Break and dead-time register */
+
+#define ATIM_BDTR_DTG_SHIFT       (0)       /* Bits 7:0 [7:0]: Dead-Time Generator set-up */
+#define ATIM_BDTR_DTG_MASK        (0xff << ATIM_BDTR_DTG_SHIFT)
+#define ATIM_BDTR_LOCK_SHIFT      (8)       /* Bits 9:8 [1:0]: Lock Configuration */
+#define ATIM_BDTR_LOCK_MASK       (3 << ATIM_BDTR_LOCK_SHIFT)
+#  define ATIM_BDTR_LOCKOFF       (0 << ATIM_BDTR_LOCK_SHIFT) /* 00: LOCK OFF - No bit is write protected */
+#  define ATIM_BDTR_LOCK1         (1 << ATIM_BDTR_LOCK_SHIFT) /* 01: LOCK Level 1 protection */
+#  define ATIM_BDTR_LOCK2         (2 << ATIM_BDTR_LOCK_SHIFT) /* 10: LOCK Level 2 protection */
+#  define ATIM_BDTR_LOCK3         (3 << ATIM_BDTR_LOCK_SHIFT) /* 11: LOCK Level 3 protection */ */
+#define ATIM_BDTR_OSSI            (1 << 10) /* Bit 10: Off-State Selection for Idle mode */
+#define ATIM_BDTR_OSSR            (1 << 11) /* Bit 11: Off-State Selection for Run mode */
+#define ATIM_BDTR_BKE             (1 << 12) /* Bit 12: Break enable */
+#define ATIM_BDTR_BKP             (1 << 13) /* Bit 13: Break Polarity */
+#define ATIM_BDTR_AOE             (1 << 14) /* Bit 14: Automatic Output enable */
+#define ATIM_BDTR_MOE             (1 << 15) /* Bit 15: Main Output enable */
+#define ATIM_BDTR_BKF_SHIFT       (16)      /* Bits 16-19: Break filter */
+#define ATIM_BDTR_BKF_MASK        (0xf << ATIM_BDTR_BKF_SHIFT)
+#  define ATIM_BDTR_BKF_NOFILT    (0 << ATIM_BDTR_BKF_SHIFT)   /* 0000: No filter, BRK acts asynchronously */
+#  define ATIM_BDTR_BKF_FCKINT2   (1 << ATIM_BDTR_BKF_SHIFT)   /* 0001: fSAMPLING=fCK_INT, N=2 */
+#  define ATIM_BDTR_BKF_FCKINT4   (2 << ATIM_BDTR_BKF_SHIFT)   /* 0010: fSAMPLING=fCK_INT, N=4 */
+#  define ATIM_BDTR_BKF_FCKINT8   (3 << ATIM_BDTR_BKF_SHIFT)   /* 0011: fSAMPLING=fCK_INT, N=8 */
+#  define ATIM_BDTR_BKF_FDTSd26   (4 << ATIM_BDTR_BKF_SHIFT)   /* 0100: fSAMPLING=fDTS/2, N=6 */
+#  define ATIM_BDTR_BKF_FDTSd28   (5 << ATIM_BDTR_BKF_SHIFT)   /* 0101: fSAMPLING=fDTS/2, N=8 */
+#  define ATIM_BDTR_BKF_FDTSd36   (6 << ATIM_BDTR_BKF_SHIFT)   /* 0110: fSAMPLING=fDTS/4, N=6 */
+#  define ATIM_BDTR_BKF_FDTSd38   (7 << ATIM_BDTR_BKF_SHIFT)   /* 0111: fSAMPLING=fDTS/4, N=8 */
+#  define ATIM_BDTR_BKF_FDTSd86   (8 << ATIM_BDTR_BKF_SHIFT)   /* 1000: fSAMPLING=fDTS/8, N=6 */
+#  define ATIM_BDTR_BKF_FDTSd88   (9 << ATIM_BDTR_BKF_SHIFT)   /* 1001: fSAMPLING=fDTS/8, N=8 */
+#  define ATIM_BDTR_BKF_FDTSd165  (10 << ATIM_BDTR_BKF_SHIFT)  /* 1010: fSAMPLING=fDTS/16, N=5 */
+#  define ATIM_BDTR_BKF_FDTSd166  (11 << ATIM_BDTR_BKF_SHIFT)  /* 1011: fSAMPLING=fDTS/16, N=6 */
+#  define ATIM_BDTR_BKF_FDTSd168  (12 << ATIM_BDTR_BKF_SHIFT)  /* 1100: fSAMPLING=fDTS/16, N=8 */
+#  define ATIM_BDTR_BKF_FDTSd325  (13 << ATIM_BDTR_BKF_SHIFT)  /* 1101: fSAMPLING=fDTS/32, N=5 */
+#  define ATIM_BDTR_BKF_FDTSd326  (14 << ATIM_BDTR_BKF_SHIFT)  /* 1110: fSAMPLING=fDTS/32, N=6 */
+#  define ATIM_BDTR_BKF_FDTSd328  (15 << ATIM_BDTR_BKF_SHIFT)  /* 1111: fSAMPLING=fDTS/32, N=8 */
+#define ATIM_BDTR_BK2F_SHIFT      (20)      /* Bits 20-23: Break 2 filter */
+#define ATIM_BDTR_BK2F_MASK       (0xf << ATIM_BDTR_BK2F_SHIFT)
+#  define ATIM_BDTR_BK2F_NOFILT   (0 << ATIM_BDTR_BK2F_SHIFT)  /* 0000: No filter, BRK 2 acts asynchronously */
+#  define ATIM_BDTR_BK2F_FCKINT2  (1 << ATIM_BDTR_BK2F_SHIFT)  /* 0001: fSAMPLING=fCK_INT, N=2 */
+#  define ATIM_BDTR_BK2F_FCKINT4  (2 << ATIM_BDTR_BK2F_SHIFT)  /* 0010: fSAMPLING=fCK_INT, N=4 */
+#  define ATIM_BDTR_BK2F_FCKINT8  (3 << ATIM_BDTR_BK2F_SHIFT)  /* 0011: fSAMPLING=fCK_INT, N=8 */
+#  define ATIM_BDTR_BK2F_FDTSd26  (4 << ATIM_BDTR_BK2F_SHIFT)  /* 0100: fSAMPLING=fDTS/2, N=6 */
+#  define ATIM_BDTR_BK2F_FDTSd28  (5 << ATIM_BDTR_BK2F_SHIFT)  /* 0101: fSAMPLING=fDTS/2, N=8 */
+#  define ATIM_BDTR_BK2F_FDTSd36  (6 << ATIM_BDTR_BK2F_SHIFT)  /* 0110: fSAMPLING=fDTS/4, N=6 */
+#  define ATIM_BDTR_BK2F_FDTSd38  (7 << ATIM_BDTR_BK2F_SHIFT)  /* 0111: fSAMPLING=fDTS/4, N=8 */
+#  define ATIM_BDTR_BK2F_FDTSd86  (8 << ATIM_BDTR_BK2F_SHIFT)  /* 1000: fSAMPLING=fDTS/8, N=6 */
+#  define ATIM_BDTR_BK2F_FDTSd88  (9 << ATIM_BDTR_BK2F_SHIFT)  /* 1001: fSAMPLING=fDTS/8, N=8 */
+#  define ATIM_BDTR_BK2F_FDTSd165 (10 << ATIM_BDTR_BK2F_SHIFT) /* 1010: fSAMPLING=fDTS/16, N=5 */
+#  define ATIM_BDTR_BK2F_FDTSd166 (11 << ATIM_BDTR_BK2F_SHIFT) /* 1011: fSAMPLING=fDTS/16, N=6 */
+#  define ATIM_BDTR_BK2F_FDTSd168 (12 << ATIM_BDTR_BK2F_SHIFT) /* 1100: fSAMPLING=fDTS/16, N=8 */
+#  define ATIM_BDTR_BK2F_FDTSd325 (13 << ATIM_BDTR_BK2F_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */
+#  define ATIM_BDTR_BK2F_FDTSd326 (14 << ATIM_BDTR_BK2F_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */
+#  define ATIM_BDTR_BK2F_FDTSd328 (15 << ATIM_BDTR_BK2F_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */
+#define ATIM_BDTR_BK2E            (1 << 24) /* Bit 24: Break 2 enable */
+#define ATIM_BDTR_BK2P            (1 << 1525 /* Bit 25:Break 2 polarity */
+
+
+/* DMA control register */
+
+#define ATIM_DCR_DBA_SHIFT        (0)       /* Bits 4-0: DMA Base Address */
+#define ATIM_DCR_DBA_MASK         (0x1f << ATIM_DCR_DBA_SHIFT)
+#define ATIM_DCR_DBL_SHIFT        (8)       /* Bits 12-8: DMA Burst Length */
+#define ATIM_DCR_DBL_MASK         (0x1f << ATIM_DCR_DBL_SHIFT)
+#  define ATIM_DCR_DBL(n)         (((n)-1) << ATIM_DCR_DBL_SHIFT) /* n transfers, n = 1..18 */
+
+/* Control register 1 (TIM2-5 and TIM9-14) */
+
+#define GTIM_CR1_CEN              (1 << 0)  /* Bit 0: Counter enable */
+#define GTIM_CR1_UDIS             (1 << 1)  /* Bit 1: Update Disable */
+#define GTIM_CR1_URS              (1 << 2)  /* Bit 2: Update Request Source */
+#define GTIM_CR1_OPM              (1 << 3)  /* Bit 3: One Pulse Mode (TIM2-5, 9, and 12 only) */
+#define GTIM_CR1_DIR              (1 << 4)  /* Bit 4: Direction (TIM2-5 only) */
+#define GTIM_CR1_CMS_SHIFT        (5)       /* Bits 6-5: Center-aligned Mode Selection (TIM2-5 only) */
+#define GTIM_CR1_CMS_MASK         (3 << GTIM_CR1_CMS_SHIFT)
+#  define GTIM_CR1_EDGE           (0 << GTIM_CR1_CMS_SHIFT) /* 00: Edge-aligned mode.  */
+#  define GTIM_CR1_CENTER1        (1 << GTIM_CR1_CMS_SHIFT) /* 01: Center-aligned mode 1 */
+#  define GTIM_CR1_CENTER2        (2 << GTIM_CR1_CMS_SHIFT) /* 10: Center-aligned mode 2 */
+#  define GTIM_CR1_CENTER3        (3 << GTIM_CR1_CMS_SHIFT) /* 11: Center-aligned mode 3 */
+#define GTIM_CR1_ARPE             (1 << 7)  /* Bit 7: Auto-Reload Preload enable */
+#define GTIM_CR1_CKD_SHIFT        (8)       /* Bits 9-8: Clock Division */
+#define GTIM_CR1_CKD_MASK         (3 << GTIM_CR1_CKD_SHIFT)
+#  define GTIM_CR1_TCKINT         (0 << GTIM_CR1_CKD_SHIFT) /* 00: tDTS = tCK_INT */
+#  define GTIM_CR1_2TCKINT        (1 << GTIM_CR1_CKD_SHIFT) /* 01: tDTS = 2 x tCK_INT */
+#  define GTIM_CR1_4TCKINT        (2 << GTIM_CR1_CKD_SHIFT) /* 10: tDTS = 4 x tCK_INT */
+#define GTIM_CR1_UIFREMAP         (1 << 11) /* Bit 11: UIF status bit remapping */
+
+/* Control register 2 (TIM2-5, TIM9-12) */
+
+#define GTIM_CR2_CCPC             (1 << 0)  /* Bit 0: Capture/compare preloaded control (TIM15-17 only) */
+#define GTIM_CR2_CCUS             (1 << 2)  /* Bit 2: Capture/compare control update selection (TIM15-17 only) */
+#define GTIM_CR2_CCDS             (1 << 3)  /* Bit 3: Capture/Compare DMA Selection (TIM2-5,1,&16 only) */
+#define GTIM_CR2_MMS_SHIFT        (4)       /* Bits 6-4: Master Mode Selection (not TIM16) */
+#define GTIM_CR2_MMS_MASK         (7 << GTIM_CR2_MMS_SHIFT)
+#  define GTIM_CR2_MMS_RESET      (0 << GTIM_CR2_MMS_SHIFT) /* 000: Reset */
+#  define GTIM_CR2_MMS_ENABLE     (1 << GTIM_CR2_MMS_SHIFT) /* 001: Enable */
+#  define GTIM_CR2_MMS_UPDATE     (2 << GTIM_CR2_MMS_SHIFT) /* 010: Update */
+#  define GTIM_CR2_MMS_COMPP      (3 << GTIM_CR2_MMS_SHIFT) /* 011: Compare Pulse */
+#  define GTIM_CR2_MMS_OC1REF     (4 << GTIM_CR2_MMS_SHIFT) /* 100: Compare - OC1REF signal is used as trigger output (TRGO) */
+#  define GTIM_CR2_MMS_OC2REF     (5 << GTIM_CR2_MMS_SHIFT) /* 101: Compare - OC2REF signal is used as trigger output (TRGO) */
+#  define GTIM_CR2_MMS_OC3REF     (6 << GTIM_CR2_MMS_SHIFT) /* 110: Compare - OC3REF signal is used as trigger output (TRGO, TIM2-5 and TIM15 only) */
+#  define GTIM_CR2_MMS_OC4REF     (7 << GTIM_CR2_MMS_SHIFT) /* 111: Compare - OC4REF signal is used as trigger output (TRGO, TIM2-5 and TIM15 only) */
+#define GTIM_CR2_TI1S             (1 << 7)  /* Bit 7: TI1 Selection (not TIM16) */
+#define GTIM_CR2_OIS1             (1 << 8)  /* Bit 8: COutput Idle state 1 (OC1 output) (TIM15-17 only) */
+#define GTIM_CR2_OIS1N            (1 << 9)  /* Bit 9: Output Idle state 1 (OC1N output) (TIM15-17 only) */
+#define GTIM_CR2_OIS2             (1 << 10) /* Bit 10: Output idle state 2 (OC2 output) (TIM15 only) */
+
+/* Slave mode control register (TIM2-5) */
+
+#define GTIM_SMCR_SMS_SHIFT       (0)       /* Bits 2-0: Slave Mode Selection */
+#define GTIM_SMCR_SMS_MASK        (7 << GTIM_SMCR_SMS_SHIFT)
+#  define GTIM_SMCR_DISAB         (0 << GTIM_SMCR_SMS_SHIFT) /* 000: Slave mode disabled */
+#  define GTIM_SMCR_ENCMD1        (1 << GTIM_SMCR_SMS_SHIFT) /* 001: Encoder mode 1 */
+#  define GTIM_SMCR_ENCMD2        (2 << GTIM_SMCR_SMS_SHIFT) /* 010: Encoder mode 2 */
+#  define GTIM_SMCR_ENCMD3        (3 << GTIM_SMCR_SMS_SHIFT) /* 011: Encoder mode 3 */
+#  define GTIM_SMCR_RESET         (4 << GTIM_SMCR_SMS_SHIFT) /* 100: Reset Mode  */
+#  define GTIM_SMCR_GATED         (5 << GTIM_SMCR_SMS_SHIFT) /* 101: Gated Mode  */
+#  define GTIM_SMCR_TRIGGER       (6 << GTIM_SMCR_SMS_SHIFT) /* 110: Trigger Mode */
+#  define GTIM_SMCR_EXTCLK1       (7 << GTIM_SMCR_SMS_SHIFT) /* 111: External Clock Mode 1 */
+#define GTIM_SMCR_TS_SHIFT        (4)       /* Bits 6-4: Trigger Selection */
+#define GTIM_SMCR_TS_MASK         (7 << GTIM_SMCR_TS_SHIFT)
+#  define GTIM_SMCR_ITR0          (0 << GTIM_SMCR_TS_SHIFT) /* 000: Internal Trigger 0 (ITR0). TIM1 */
+#  define GTIM_SMCR_ITR1          (1 << GTIM_SMCR_TS_SHIFT) /* 001: Internal Trigger 1 (ITR1). TIM2 */
+#  define GTIM_SMCR_ITR2          (2 << GTIM_SMCR_TS_SHIFT) /* 010: Internal Trigger 2 (ITR2). TIM3 */
+#  define GTIM_SMCR_ITR3          (3 << GTIM_SMCR_TS_SHIFT) /* 011: Internal Trigger 3 (ITR3). TIM4 */
+#  define GTIM_SMCR_TI1FED        (4 << GTIM_SMCR_TS_SHIFT) /* 100: TI1 Edge Detector (TI1F_ED) */
+#  define GTIM_SMCR_TI1FP1        (5 << GTIM_SMCR_TS_SHIFT) /* 101: Filtered Timer Input 1 (TI1FP1) */
+#  define GTIM_SMCR_TI2FP2        (6 << GTIM_SMCR_TS_SHIFT) /* 110: Filtered Timer Input 2 (TI2FP2) */
+#  define GTIM_SMCR_ETRF          (7 << GTIM_SMCR_TS_SHIFT) /* 111: External Trigger input (ETRF) */
+#define GTIM_SMCR_MSM             (1 << 7)  /* Bit 7: Master/Slave mode */
+#define GTIM_SMCR_ETF_SHIFT       (8)       /* Bits 11-8: External Trigger Filter (not TIM15) */
+#define GTIM_SMCR_ETF_MASK        (0x0f << GTIM_SMCR_ETF_SHIFT)
+#  define GTIM_SMCR_NOFILT        (0 << GTIM_SMCR_ETF_SHIFT)  /* 0000: No filter, sampling is done at fDTS */
+#  define GTIM_SMCR_FCKINT2       (1 << GTIM_SMCR_ETF_SHIFT)  /* 0001: fSAMPLING=fCK_INT, N=2 */
+#  define GTIM_SMCR_FCKINT4       (2 << GTIM_SMCR_ETF_SHIFT)  /* 0010: fSAMPLING=fCK_INT, N=4 */
+#  define GTIM_SMCR_FCKINT8       (3 << GTIM_SMCR_ETF_SHIFT)  /* 0011: fSAMPLING=fCK_INT, N=8 */
+#  define GTIM_SMCR_FDTSd26       (4 << GTIM_SMCR_ETF_SHIFT)  /* 0100: fSAMPLING=fDTS/2, N=6 */
+#  define GTIM_SMCR_FDTSd28       (5 << GTIM_SMCR_ETF_SHIFT)  /* 0101: fSAMPLING=fDTS/2, N=8 */
+#  define GTIM_SMCR_FDTSd36       (6 << GTIM_SMCR_ETF_SHIFT)  /* 0110: fSAMPLING=fDTS/4, N=6 */
+#  define GTIM_SMCR_FDTSd38       (7 << GTIM_SMCR_ETF_SHIFT)  /* 0111: fSAMPLING=fDTS/4, N=8 */
+#  define GTIM_SMCR_FDTSd86       (8 << GTIM_SMCR_ETF_SHIFT)  /* 1000: fSAMPLING=fDTS/8, N=6 */
+#  define GTIM_SMCR_FDTSd88       (9 << GTIM_SMCR_ETF_SHIFT)  /* 1001: fSAMPLING=fDTS/8, N=8 */
+#  define GTIM_SMCR_FDTSd165      (10 << GTIM_SMCR_ETF_SHIFT) /* 1010: fSAMPLING=fDTS/16, N=5 */
+#  define GTIM_SMCR_FDTSd166      (11 << GTIM_SMCR_ETF_SHIFT) /* 1011: fSAMPLING=fDTS/16, N=6 */
+#  define GTIM_SMCR_FDTSd168      (12 << GTIM_SMCR_ETF_SHIFT) /* 1100: fSAMPLING=fDTS/16, N=8 */
+#  define GTIM_SMCR_FDTSd325      (13 << GTIM_SMCR_ETF_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */
+#  define GTIM_SMCR_FDTSd326      (14 << GTIM_SMCR_ETF_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */
+#  define GTIM_SMCR_FDTSd328      (15 << GTIM_SMCR_ETF_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */
+#define GTIM_SMCR_ETPS_SHIFT      (12)      /* Bits 13-12: External Trigger Prescaler (not TIM15) */
+#define GTIM_SMCR_ETPS_MASK       (3 << GTIM_SMCR_ETPS_SHIFT)
+#  define GTIM_SMCR_PSCOFF        (0 << GTIM_SMCR_ETPS_SHIFT) /* 00: Prescaler OFF */
+#  define GTIM_SMCR_ETRPd2        (1 << GTIM_SMCR_ETPS_SHIFT) /* 01: ETRP frequency divided by 2 */
+#  define GTIM_SMCR_ETRPd4        (2 << GTIM_SMCR_ETPS_SHIFT) /* 10: ETRP frequency divided by 4 */
+#  define GTIM_SMCR_ETRPd8        (3 << GTIM_SMCR_ETPS_SHIFT) /* 11: ETRP frequency divided by 8 */
+#define GTIM_SMCR_ECE             (1 << 14) /* Bit 14: External Clock enable */
+#define GTIM_SMCR_ETP             (1 << 15) /* Bit 15: External Trigger Polarity */
+#define GTIM_SMCR_SMS             (1 << 16) /* Bit 16: Slave mode selection - bit 3 */
+
+/* DMA/Interrupt enable register (TIM2-5 and TIM9-14) */
+
+#define GTIM_DIER_UIE             (1 << 0)  /* Bit 0: Update interrupt enable */
+#define GTIM_DIER_CC1IE           (1 << 1)  /* Bit 1: Capture/Compare 1 interrupt enable */
+#define GTIM_DIER_CC2IE           (1 << 2)  /* Bit 2: Capture/Compare 2 interrupt enable (TIM2-5,9,12,&15 only) */
+#define GTIM_DIER_CC3IE           (1 << 3)  /* Bit 3: Capture/Compare 3 interrupt enable (TIM2-5 only) */
+#define GTIM_DIER_CC4IE           (1 << 4)  /* Bit 4: Capture/Compare 4 interrupt enable (TIM2-5 only) */
+#define GTIM_DIER_COMIE           (1 << 5)  /* Bit 5: COM interrupt enable (TIM15-17 only) */
+#define GTIM_DIER_TIE             (1 << 6)  /* Bit 6: Trigger interrupt enable (TIM2-5,9,&12 only) */
+#define GTIM_DIER_BIE             (1 << 7)  /* Bit 7: Break interrupt enable (TIM15-17 only) */
+#define GTIM_DIER_UDE             (1 << 8)  /* Bit 8: Update DMA request enable (TIM2-5&15-17 only) */
+#define GTIM_DIER_CC1DE           (1 << 9)  /* Bit 9: Capture/Compare 1 DMA request enable (TIM2-5&15-17 only) */
+#define GTIM_DIER_CC2DE           (1 << 10) /* Bit 10: Capture/Compare 2 DMA request enable (TIM2-5&15 only) */
+#define GTIM_DIER_CC3DE           (1 << 11) /* Bit 11: Capture/Compare 3 DMA request enable (TIM2-5 only) */
+#define GTIM_DIER_CC4DE           (1 << 12) /* Bit 12: Capture/Compare 4 DMA request enable (TIM2-5 only) */
+#define GTIM_DIER_COMDE           (1 << 13) /* Bit 13: COM DMA request enable (TIM15-17 only) */
+#define GTIM_DIER_TDE             (1 << 14) /* Bit 14: Trigger DMA request enable (TIM2-5&15-17 only) */
+
+/* Status register */
+
+#define GTIM_SR_UIF               (1 << 0)  /* Bit 0: Update interrupt flag */
+#define GTIM_SR_CC1IF             (1 << 1)  /* Bit 1: Capture/compare 1 interrupt flag */
+#define GTIM_SR_CC2IF             (1 << 2)  /* Bit 2: Capture/Compare 2 interrupt flag (TIM2-5,9,12,&15 only) */
+#define GTIM_SR_CC3IF             (1 << 3)  /* Bit 3: Capture/Compare 3 interrupt flag (TIM2-5 only) */
+#define GTIM_SR_CC4IF             (1 << 4)  /* Bit 4: Capture/Compare 4 interrupt flag (TIM2-5 only) */
+#define GTIM_SR_COMIF             (1 << 5)  /* Bit 5: COM interrupt flag (TIM15-17 only) */
+#define GTIM_SR_TIF               (1 << 6)  /* Bit 6: Trigger interrupt Flag (TIM2-5,9,12&15-17 only) */
+#define GTIM_SR_BIF               (1 << 7)  /* Bit 7: Break interrupt flag (TIM15-17 only) */
+#define GTIM_SR_CC1OF             (1 << 9)  /* Bit 9: Capture/Compare 1 Overcapture flag */
+#define GTIM_SR_CC2OF             (1 << 10) /* Bit 10: Capture/Compare 2 Overcapture flag (TIM2-5,9,12&15 only) */
+#define GTIM_SR_CC3OF             (1 << 11) /* Bit 11: Capture/Compare 3 Overcapture flag (TIM2-5 only) */
+#define GTIM_SR_CC4OF             (1 << 12) /* Bit 12: Capture/Compare 4 Overcapture flag (TIM2-5 only) */
+
+/* Event generation register (TIM2-5 and TIM9-14) */
+
+#define GTIM_EGR_UG               (1 << 0)  /* Bit 0: Update generation */
+#define GTIM_EGR_CC1G             (1 << 1)  /* Bit 1: Capture/compare 1 generation */
+#define GTIM_EGR_CC2G             (1 << 2)  /* Bit 2: Capture/compare 2 generation (TIM2-5,9,12,&15 only) */
+#define GTIM_EGR_CC3G             (1 << 3)  /* Bit 3: Capture/compare 3 generation (TIM2-5 only) */
+#define GTIM_EGR_CC4G             (1 << 4)  /* Bit 4: Capture/compare 4 generation (TIM2-5 only) */
+#define GTIM_EGR_COMIG            (1 << 5)  /* Bit 5: Capture/Compare control update generation (TIM15-17 only) */
+#define GTIM_EGR_TG               (1 << 6)  /* Bit 6: Trigger generation (TIM2-5,9,12&16-17 only) */
+#define GTIM_EGR_BG               (1 << 7)  /* Bit 7: Break generation (TIM15-17 only) */
+
+/* Capture/compare mode register 1 - Output compare mode (TIM2-5 and TIM9-14) */
+
+#define GTIM_CCMR1_CC1S_SHIFT     (0)       /* Bits 1-0: Capture/Compare 1 Selection */
+#define GTIM_CCMR1_CC1S_MASK      (3 << GTIM_CCMR1_CC1S_SHIFT)
+                                            /* (See common CCMR Capture/Compare Selection definitions below) */
+#define GTIM_CCMR1_OC1FE          (1 << 2)  /* Bit 2: Output Compare 1 Fast enable */
+#define GTIM_CCMR1_OC1PE          (1 << 3)  /* Bit 3: Output Compare 1 Preload enable */
+#define GTIM_CCMR1_OC1M_SHIFT     (4)       /* Bits 6-4: Output Compare 1 Mode */
+#define GTIM_CCMR1_OC1M_MASK      (7 << GTIM_CCMR1_OC1M_SHIFT)
+                                            /* (See common CCMR Output Compare Mode definitions below) */
+#define GTIM_CCMR1_OC1CE          (1 << 7)  /* Bit 7: Output Compare 1Clear Enable */
+#define GTIM_CCMR1_CC2S_SHIFT     (8)       /* Bits 9-8: Capture/Compare 2 Selection */
+#define GTIM_CCMR1_CC2S_MASK      (3 << GTIM_CCMR1_CC2S_SHIFT)
+                                            /* (See common CCMR Capture/Compare Selection definitions below) */
+#define GTIM_CCMR1_OC2FE          (1 << 10) /* Bit 10: Output Compare 2 Fast enable */
+#define GTIM_CCMR1_OC2PE          (1 << 11) /* Bit 11: Output Compare 2 Preload enable */
+#define GTIM_CCMR1_OC2M_SHIFT     (12)      /* Bits 14-12: Output Compare 2 Mode */
+#define GTIM_CCMR1_OC2M_MASK      (7 << GTIM_CCMR1_OC2M_SHIFT)
+                                            /* (See common CCMR Output Compare Mode definitions below) */
+#define GTIM_CCMR1_OC2CE          (1 << 15) /* Bit 15: Output Compare 2 Clear Enable */
+#define GTIM_CCMR1_OC1M           (1 << 16) /* Bit 16: Output Compare 1 mode - bit 3 */
+#define GTIM_CCMR1_OC2M           (1 << 24) /* Bit 24: Output Compare 2 mode - bit 3 */
+
+/* Common CCMR (unshifted) Capture/Compare Selection bit-field definitions */
+
+#define GTIM_CCMR_CCS_CCOUT       (0)       /* 00: CCx channel output */
+#define GTIM_CCMR_CCS_CCIN1       (1)       /* 01: CCx channel input, ICx is TIx */
+#define GTIM_CCMR_CCS_CCIN2       (2)       /* 10: CCx channel input, ICx is TIy */
+#define GTIM_CCMR_CCS_CCINTRC     (3)       /* 11: CCx channel input, ICx is TRC */
+
+/* Common CCMR (unshifted) Compare Mode bit field definitions */
+
+#define GTIM_CCMR_MODE_FRZN       (0)       /* 000: Frozen */
+#define GTIM_CCMR_MODE_CHACT      (1)       /* 001: Channel x active on match */
+#define GTIM_CCMR_MODE_CHINACT    (2)       /* 010: Channel x inactive on match */
+#define GTIM_CCMR_MODE_OCREFTOG   (3)       /* 011: OCxREF toggle ATIM_CNT=ATIM_CCRx */
+#define GTIM_CCMR_MODE_OCREFLO    (4)       /* 100: OCxREF forced low */
+#define GTIM_CCMR_MODE_OCREFHI    (5)       /* 101: OCxREF forced high */
+#define GTIM_CCMR_MODE_PWM1       (6)       /* 110: PWM mode 1 */
+#define GTIM_CCMR_MODE_PWM2       (7)       /* 111: PWM mode 2 */
+
+/* Capture/compare mode register 1 - Input capture mode (TIM2-5 and TIM9-14) */
+
+                                            /* Bits 1-0 (Same as Output Compare Mode) */
+#define GTIM_CCMR1_IC1PSC_SHIFT   (2)       /* Bits 3-2: Input Capture 1 Prescaler */
+#define GTIM_CCMR1_IC1PSC_MASK    (3 << GTIM_CCMR1_IC1PSC_SHIFT)
+                                            /* (See common CCMR Input Capture Prescaler definitions below) */
+#define GTIM_CCMR1_IC1F_SHIFT     (4)       /* Bits 7-4: Input Capture 1 Filter */
+#define GTIM_CCMR1_IC1F_MASK      (0x0f << GTIM_CCMR1_IC1F_SHIFT)
+                                            /* (See common CCMR Input Capture Filter definitions below) */
+                                            /* Bits 9-8: (Same as Output Compare Mode) */
+#define GTIM_CCMR1_IC2PSC_SHIFT   (10)      /* Bits 11-10: Input Capture 2 Prescaler */
+#define GTIM_CCMR1_IC2PSC_MASK    (3 << GTIM_CCMR1_IC2PSC_SHIFT)
+                                            /* (See common CCMR Input Capture Prescaler definitions below) */
+#define GTIM_CCMR1_IC2F_SHIFT     (12)      /* Bits 15-12: Input Capture 2 Filter */
+#define GTIM_CCMR1_IC2F_MASK      (0x0f << GTIM_CCMR1_IC2F_SHIFT)
+                                            /* (See common CCMR Input Capture Filter definitions below) */
+
+/* Common CCMR (unshifted) Input Capture Prescaler bit-field definitions */
+
+#define GTIM_CCMR_ICPSC_NOPSC     (0)       /* 00: no prescaler, capture each edge */
+#define GTIM_CCMR_ICPSC_EVENTS2   (1)       /* 01: capture once every 2 events */
+#define GTIM_CCMR_ICPSC_EVENTS4   (2)       /* 10: capture once every 4 events */
+#define GTIM_CCMR_ICPSC_EVENTS8   (3)       /* 11: capture once every 8 events */
+
+/* Common CCMR (unshifted) Input Capture Filter bit-field definitions */
+
+#define GTIM_CCMR_ICF_NOFILT      (0)       /* 0000: No filter, sampling at fDTS */
+#define GTIM_CCMR_ICF_FCKINT2     (1)       /* 0001: fSAMPLING=fCK_INT, N=2 */
+#define GTIM_CCMR_ICF_FCKINT4     (2)       /* 0010: fSAMPLING=fCK_INT, N=4 */
+#define GTIM_CCMR_ICF_FCKINT8     (3)       /* 0011: fSAMPLING=fCK_INT, N=8 */
+#define GTIM_CCMR_ICF_FDTSd26     (4)       /* 0100: fSAMPLING=fDTS/2, N=6 */
+#define GTIM_CCMR_ICF_FDTSd28     (5)       /* 0101: fSAMPLING=fDTS/2, N=8 */
+#define GTIM_CCMR_ICF_FDTSd46     (6)       /* 0110: fSAMPLING=fDTS/4, N=6 */
+#define GTIM_CCMR_ICF_FDTSd48     (7)       /* 0111: fSAMPLING=fDTS/4, N=8 */
+#define GTIM_CCMR_ICF_FDTSd86     (8)       /* 1000: fSAMPLING=fDTS/8, N=6 */
+#define GTIM_CCMR_ICF_FDTSd88     (9)       /* 1001: fSAMPLING=fDTS/8, N=8 */
+#define GTIM_CCMR_ICF_FDTSd165    (10)      /* 1010: fSAMPLING=fDTS/16, N=5 */
+#define GTIM_CCMR_ICF_FDTSd166    (11)      /* 1011: fSAMPLING=fDTS/16, N=6 */
+#define GTIM_CCMR_ICF_FDTSd168    (12)      /* 1100: fSAMPLING=fDTS/16, N=8 */
+#define GTIM_CCMR_ICF_FDTSd325    (13)      /* 1101: fSAMPLING=fDTS/32, N=5 */
+#define GTIM_CCMR_ICF_FDTSd326    (14)      /* 1110: fSAMPLING=fDTS/32, N=6 */
+#define GTIM_CCMR_ICF_FDTSd328    (15)      /* 1111: fSAMPLING=fDTS/32, N=8 */
+
+/* Capture/compare mode register 2 - Output Compare mode (TIM2-5 only) */
+
+#define GTIM_CCMR2_CC3S_SHIFT     (0)       /* Bits 1-0: Capture/Compare 3 Selection */
+#define GTIM_CCMR2_CC3S_MASK      (3 << GTIM_CCMR2_CC3S_SHIFT)
+                                            /* (See common CCMR Capture/Compare Selection definitions above) */
+#define GTIM_CCMR2_OC3FE          (1 << 2)  /* Bit 2: Output Compare 3 Fast enable */
+#define GTIM_CCMR2_OC3PE          (1 << 3)  /* Bit 3: Output Compare 3 Preload enable */
+#define GTIM_CCMR2_OC3M_SHIFT     (4)       /* Bits 6-4: Output Compare 3 Mode */
+#define GTIM_CCMR2_OC3M_MASK      (7 << GTIM_CCMR2_OC3M_SHIFT)
+                                            /* (See common CCMR Output Compare Mode definitions above) */
+#define GTIM_CCMR2_OC3CE          (1 << 7)  /* Bit 7: Output Compare 3 Clear Enable */
+#define GTIM_CCMR2_CC4S_SHIFT     (8)       /* Bits 9-8: Capture/Compare 4 Selection */
+#define GTIM_CCMR2_CC4S_MASK      (3 << GTIM_CCMR2_CC4S_SHIFT)
+                                            /* (See common CCMR Capture/Compare Selection definitions above) */
+#define GTIM_CCMR2_OC4FE          (1 << 10) /* Bit 10: Output Compare 4 Fast enable */
+#define GTIM_CCMR2_OC4PE          (1 << 11) /* Bit 11: Output Compare 4 Preload enable */
+#define GTIM_CCMR2_OC4M_SHIFT     (12)      /* Bits 14-12: Output Compare 4 Mode */
+#define GTIM_CCMR2_OC4M_MASK      (7 << GTIM_CCMR2_OC4M_SHIFT)
+                                            /* (See common CCMR Output Compare Mode definitions above) */
+#define GTIM_CCMR2_OC4CE          (1 << 15) /* Bit 15: Output Compare 4 Clear Enable */
+
+/* Capture/compare mode register 2 - Input capture mode (TIM2-5 only) */
+
+                                            /* Bits 1-0 (Same as Output Compare Mode) */
+#define GTIM_CCMR2_IC3PSC_SHIFT   (2)       /* Bits 3-2: Input Capture 3 Prescaler */
+#define GTIM_CCMR2_IC3PSC_MASK    (3 << GTIM_CCMR2_IC3PSC_SHIFT)
+                                            /* (See common CCMR Input Capture Prescaler definitions below) */
+#define GTIM_CCMR2_IC3F_SHIFT     (4)       /* Bits 7-4: Input Capture 3 Filter */
+#define GTIM_CCMR2_IC3F_MASK      (0x0f << GTIM_CCMR2_IC3F_SHIFT)
+                                            /* (See common CCMR Input Capture Filter definitions below) */
+                                            /* Bits 9-8: (Same as Output Compare Mode) */
+#define GTIM_CCMR2_IC4PSC_SHIFT   (10)      /* Bits 11-10: Input Capture 4 Prescaler */
+#define GTIM_CCMR2_IC4PSC_MASK    (3 << GTIM_CCMR2_IC4PSC_SHIFT)
+                                            /* (See common CCMR Input Capture Prescaler definitions below) */
+#define GTIM_CCMR2_IC4F_SHIFT     (12)      /* Bits 15-12: Input Capture 4 Filter */
+#define GTIM_CCMR2_IC4F_MASK      (0x0f << GTIM_CCMR2_IC4F_SHIFT)
+                                            /* (See common CCMR Input Capture Filter definitions below) */
+
+/* Capture/compare enable register (TIM1 and TIM8, TIM2-5 and TIM9-14) */
+
+#define GTIM_CCER_CC1E            (1 << 0)  /* Bit 0: Capture/Compare 1 output enable */
+#define GTIM_CCER_CC1P            (1 << 1)  /* Bit 1: Capture/Compare 1 output polarity */
+#define GTIM_CCER_CC1NE           (1 << 2)  /* Bit 2: Capture/Compare 1 complementary output enable (TIM1 and TIM8 only) */
+#define GTIM_CCER_CC1NP           (1 << 3)  /* Bit 3: Capture/Compare 1 output Polarity (F2,F3,F4 and TIM15-17) */
+#define GTIM_CCER_CC2E            (1 << 4)  /* Bit 4: Capture/Compare 2 output enable (TIM2-5,9&12 only) */
+#define GTIM_CCER_CC2P            (1 << 5)  /* Bit 5: Capture/Compare 2 output polarity (TIM2-5,9&12 only) */
+#define GTIM_CCER_CC2NE           (1 << 6)  /* Bit 6: Capture/Compare 2 complementary output enable (TIM1 and TIM8 only) */
+#define GTIM_CCER_CC2NP           (1 << 7)  /* Bit 7: Capture/Compare 2 output Polarity (F2,F3,F4 and TIM2-5,9,12&15 only) */
+#define GTIM_CCER_CC3E            (1 << 8)  /* Bit 8: Capture/Compare 3 output enable (TIM2-5 only) */
+#define GTIM_CCER_CC3P            (1 << 9)  /* Bit 9: Capture/Compare 3 output Polarity (TIM2-5 only) */
+#define GTIM_CCER_CC3NE           (1 << 10) /* Bit 10: Capture/Compare 3 complementary output enable (TIM1 and TIM8 only) */
+#define GTIM_CCER_CC3NP           (1 << 11) /* Bit 11: Capture/Compare 3 output Polarity (F2,F4 and TIM2-5 only) */
+#define GTIM_CCER_CC4E            (1 << 12) /* Bit 12: Capture/Compare 4 output enable (TIM2-5 only) */
+#define GTIM_CCER_CC4P            (1 << 13) /* Bit 13: Capture/Compare 4 output Polarity (TIM2-5 only) */
+#define GTIM_CCER_CC4NP           (1 << 15) /* Bit 15: Capture/Compare 4 output Polarity */
+
+/* 16-bit counter register */
+
+#define GTIM_CNT_SHIFT            (0)       /* Bits 0-15: Timer counter value */
+#define GTIM_CNT_MASK             (0xffff << ATIM_CNT_SHIFT)
+
+/* DMA control register */
+
+#define GTIM_DCR_DBA_SHIFT        (0)       /* Bits 4-0: DMA Base Address */
+#define GTIM_DCR_DBA_MASK         (0x1f << GTIM_DCR_DBA_SHIFT)
+#define GTIM_DCR_DBL_SHIFT        (8)       /* Bits 12-8: DMA Burst Length */
+#define GTIM_DCR_DBL_MASK         (0x1f << GTIM_DCR_DBL_SHIFT)
+
+/* Timer 2/5 option register */
+
+#define TIM2_OR_ITR1_RMP_SHIFT    (10)     /* Bits 10-11: Internal trigger 1 remap */
+#define TIM2_OR_ITR1_RMP_MASK     (3 << TIM2_OR_ITR1_RMP_SHIFT)
+#  define TIM2_OR_ITR1_TIM8_TRGOUT (0 << TIM2_OR_ITR1_RMP_SHIFT) /* 00: TIM2_ITR1 input connected to TIM8_TRGOUT */
+#  define TIM2_OR_ITR1_PTP        (1 << TIM2_OR_ITR1_RMP_SHIFT) /* 01: TIM2_ITR1 input connected to PTP trigger output */
+#  define TIM2_OR_ITR1_OTGFSSOF   (2 << TIM2_OR_ITR1_RMP_SHIFT) /* 10: TIM2_ITR1 input connected to OTG FS SOF */
+#  define TIM2_OR_ITR1_OTGHSSOF   (3 << TIM2_OR_ITR1_RMP_SHIFT) /* 11: TIM2_ITR1 input connected to OTG HS SOF */
+
+#define TIM5_OR_TI4_RMP_SHIFT     (6)     /* Bits 6-7: Internal trigger 4 remap */
+#define TIM5_OR_TI4_RMP_MASK      (3 << TIM5_OR_TI4_RMP_SHIFT)
+#  define TIM5_OR_TI4_GPIO        (0 << TIM5_OR_TI4_RMP_SHIFT) /* 00: TIM5_CH4 input connected to GPIO */
+#  define TIM5_OR_TI4_LSI         (1 << TIM5_OR_TI4_RMP_SHIFT) /* 01: TIM5_CH4 input connected to LSI internal clock */
+#  define TIM5_OR_TI4_LSE         (2 << TIM5_OR_TI4_RMP_SHIFT) /* 10: TIM5_CH4 input connected to LSE internal clock */
+#  define TIM5_OR_TI4_RTC         (3 << TIM5_OR_TI4_RMP_SHIFT) /* 11: TIM5_CH4 input connected to RTC output event */
+
+#define TIM11_OR_TI1_RMP_SHIFT    (6)     /* Bits 6-7: Internal trigger 4 remap */
+#define TIM11_OR_TI1_RMP_MASK     (3 << TIM11_OR_TI1_RMP_SHIFT)
+#  define TIM11_OR_TI1_GPIO       (0 << TIM11_OR_TI1_RMP_SHIFT) /* 00-11: TIM11_CH1 input connected to GPIO */
+#  define TIM11_OR_TI1_HSERTC     (3 << TIM11_OR_TI1_RMP_SHIFT) /* 11: TIM11_CH1 input connected to HSE_RTC clock */
+
+
+/* Control register 1 */
+
+#define BTIM_CR1_CEN              (1 << 0)  /* Bit 0: Counter enable */
+#define BTIM_CR1_UDIS             (1 << 1)  /* Bit 1: Update Disable */
+#define BTIM_CR1_URS              (1 << 2)  /* Bit 2: Update Request Source */
+#define BTIM_CR1_OPM              (1 << 3)  /* Bit 3: One Pulse Mode */
+#define BTIM_CR1_ARPE             (1 << 7)  /* Bit 7: Auto-Reload Preload enable */
+
+/* Control register 2 */
+
+#define BTIM_CR2_MMS_SHIFT        (4)       /* Bits 6-4: Master Mode Selection */
+#define BTIM_CR2_MMS_MASK         (7 << BTIM_CR2_MMS_SHIFT)
+#  define BTIM_CR2_RESET          (0 << BTIM_CR2_MMS_SHIFT) /* 000: Reset */
+#  define BTIM_CR2_ENAB           (1 << BTIM_CR2_MMS_SHIFT) /* 001: Enable */
+#  define BTIM_CR2_UPDT           (2 << BTIM_CR2_MMS_SHIFT) /* 010: Update */
+
+/* DMA/Interrupt enable register */
+
+#define BTIM_DIER_UIE             (1 << 0)  /* Bit 0: Update interrupt enable */
+#define BTIM_DIER_UDE             (1 << 8)  /* Bit 8: Update DMA request enable */
+
+/* Status register */
+
+#define BTIM_SR_UIF               (1 << 0)  /* Bit 0: Update interrupt flag */
+
+/* Event generation register */
+
+#define BTIM_EGR_UG               (1 << 0)  /* Bit 0: Update generation */
+
+#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX75XX_TIM_H */
diff --git a/arch/arm/src/stm32f7/chip/stm32f74xx77xx_adc.h b/arch/arm/src/stm32f7/chip/stm32f74xx77xx_adc.h
new file mode 100644
index 00000000000..bc79490798b
--- /dev/null
+++ b/arch/arm/src/stm32f7/chip/stm32f74xx77xx_adc.h
@@ -0,0 +1,484 @@
+/****************************************************************************************************
+ * arch/arm/src/stm32f7/chip/stm32f74xx77xx_adc.h
+ *
+ *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ *   Authors: Gregory Nutt <gnutt@nuttx.org>
+ *            David Sidrane <david_s5@nscdg.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX77XX_ADC_H
+#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX77XX_ADC_H
+
+/****************************************************************************************************
+ * Included Files
+ ****************************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "chip.h"
+
+/****************************************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************************************/
+
+/* Register Offsets *********************************************************************************/
+
+#define STM32_ADC_SR_OFFSET          0x0000  /* ADC status register (32-bit) */
+#define STM32_ADC_CR1_OFFSET         0x0004  /* ADC control register 1 (32-bit) */
+#define STM32_ADC_CR2_OFFSET         0x0008  /* ADC control register 2 (32-bit) */
+#define STM32_ADC_SMPR1_OFFSET       0x000c  /* ADC sample time register 1 (32-bit) */
+#define STM32_ADC_SMPR2_OFFSET       0x0010  /* ADC sample time register 2 (32-bit) */
+#define STM32_ADC_JOFR1_OFFSET       0x0014  /* ADC injected channel data offset register 1 (32-bit) */
+#define STM32_ADC_JOFR2_OFFSET       0x0018  /* ADC injected channel data offset register 2 (32-bit) */
+#define STM32_ADC_JOFR3_OFFSET       0x001c  /* ADC injected channel data offset register 3 (32-bit) */
+#define STM32_ADC_JOFR4_OFFSET       0x0020  /* ADC injected channel data offset register 4 (32-bit) */
+#define STM32_ADC_HTR_OFFSET         0x0024  /* ADC watchdog high threshold register (32-bit) */
+#define STM32_ADC_LTR_OFFSET         0x0028  /* ADC watchdog low threshold register (32-bit) */
+#define STM32_ADC_SQR1_OFFSET        0x002c  /* ADC regular sequence register 1 (32-bit) */
+#define STM32_ADC_SQR2_OFFSET        0x0030  /* ADC regular sequence register 2 (32-bit) */
+#define STM32_ADC_SQR3_OFFSET        0x0034  /* ADC regular sequence register 3 (32-bit) */
+#define STM32_ADC_JSQR_OFFSET        0x0038  /* ADC injected sequence register (32-bit) */
+#define STM32_ADC_JDR1_OFFSET        0x003c  /* ADC injected data register 1 (32-bit) */
+#define STM32_ADC_JDR2_OFFSET        0x0040  /* ADC injected data register 1 (32-bit) */
+#define STM32_ADC_JDR3_OFFSET        0x0044  /* ADC injected data register 1 (32-bit) */
+#define STM32_ADC_JDR4_OFFSET        0x0048  /* ADC injected data register 1 (32-bit) */
+#define STM32_ADC_DR_OFFSET          0x004c  /* ADC regular data register (32-bit) */
+
+
+#define STM32_ADC_CSR_OFFSET         0x0000  /* Common status register */
+#define STM32_ADC_CCR_OFFSET         0x0004  /* Common control register */
+#define STM32_ADC_CDR_OFFSET         0x0008  /* Data register for dual and triple modes */
+
+/* Register Addresses *******************************************************************************/
+
+#if STM32F7_NADC > 0
+#  define STM32_ADC1_SR              (STM32_ADC1_BASE+STM32_ADC_SR_OFFSET)
+#  define STM32_ADC1_CR1             (STM32_ADC1_BASE+STM32_ADC_CR1_OFFSET)
+#  define STM32_ADC1_CR2             (STM32_ADC1_BASE+STM32_ADC_CR2_OFFSET)
+#  define STM32_ADC1_SMPR1           (STM32_ADC1_BASE+STM32_ADC_SMPR1_OFFSET)
+#  define STM32_ADC1_SMPR2           (STM32_ADC1_BASE+STM32_ADC_SMPR2_OFFSET)
+#  define STM32_ADC1_JOFR1           (STM32_ADC1_BASE+STM32_ADC_JOFR1_OFFSET)
+#  define STM32_ADC1_JOFR2           (STM32_ADC1_BASE+STM32_ADC_JOFR2_OFFSET)
+#  define STM32_ADC1_JOFR3           (STM32_ADC1_BASE+STM32_ADC_JOFR3_OFFSET)
+#  define STM32_ADC1_JOFR4           (STM32_ADC1_BASE+STM32_ADC_JOFR4_OFFSET)
+#  define STM32_ADC1_HTR             (STM32_ADC1_BASE+STM32_ADC_HTR_OFFSET)
+#  define STM32_ADC1_LTR             (STM32_ADC1_BASE+STM32_ADC_LTR_OFFSET)
+#  define STM32_ADC1_SQR1            (STM32_ADC1_BASE+STM32_ADC_SQR1_OFFSET)
+#  define STM32_ADC1_SQR2            (STM32_ADC1_BASE+STM32_ADC_SQR2_OFFSET)
+#  define STM32_ADC1_SQR3            (STM32_ADC1_BASE+STM32_ADC_SQR3_OFFSET)
+#  define STM32_ADC1_JSQR            (STM32_ADC1_BASE+STM32_ADC_JSQR_OFFSET)
+#  define STM32_ADC1_JDR1            (STM32_ADC1_BASE+STM32_ADC_JDR1_OFFSET)
+#  define STM32_ADC1_JDR2            (STM32_ADC1_BASE+STM32_ADC_JDR2_OFFSET)
+#  define STM32_ADC1_JDR3            (STM32_ADC1_BASE+STM32_ADC_JDR3_OFFSET)
+#  define STM32_ADC1_JDR4            (STM32_ADC1_BASE+STM32_ADC_JDR4_OFFSET)
+#  define STM32_ADC1_DR              (STM32_ADC1_BASE+STM32_ADC_DR_OFFSET)
+#endif
+
+#if STM32F7_NADC > 1
+#  define STM32_ADC2_SR              (STM32_ADC2_BASE+STM32_ADC_SR_OFFSET)
+#  define STM32_ADC2_CR1             (STM32_ADC2_BASE+STM32_ADC_CR1_OFFSET)
+#  define STM32_ADC2_CR2             (STM32_ADC2_BASE+STM32_ADC_CR2_OFFSET)
+#  define STM32_ADC2_SMPR1           (STM32_ADC2_BASE+STM32_ADC_SMPR1_OFFSET)
+#  define STM32_ADC2_SMPR2           (STM32_ADC2_BASE+STM32_ADC_SMPR2_OFFSET)
+#  define STM32_ADC2_JOFR1           (STM32_ADC2_BASE+STM32_ADC_JOFR1_OFFSET)
+#  define STM32_ADC2_JOFR2           (STM32_ADC2_BASE+STM32_ADC_JOFR2_OFFSET)
+#  define STM32_ADC2_JOFR3           (STM32_ADC2_BASE+STM32_ADC_JOFR3_OFFSET)
+#  define STM32_ADC2_JOFR4           (STM32_ADC2_BASE+STM32_ADC_JOFR4_OFFSET)
+#  define STM32_ADC2_HTR             (STM32_ADC2_BASE+STM32_ADC_HTR_OFFSET)
+#  define STM32_ADC2_LTR             (STM32_ADC2_BASE+STM32_ADC_LTR_OFFSET)
+#  define STM32_ADC2_SQR1            (STM32_ADC2_BASE+STM32_ADC_SQR1_OFFSET)
+#  define STM32_ADC2_SQR2            (STM32_ADC2_BASE+STM32_ADC_SQR2_OFFSET)
+#  define STM32_ADC2_SQR3            (STM32_ADC2_BASE+STM32_ADC_SQR3_OFFSET)
+#  define STM32_ADC2_JSQR            (STM32_ADC2_BASE+STM32_ADC_JSQR_OFFSET)
+#  define STM32_ADC2_JDR1            (STM32_ADC2_BASE+STM32_ADC_JDR1_OFFSET)
+#  define STM32_ADC2_JDR2            (STM32_ADC2_BASE+STM32_ADC_JDR2_OFFSET)
+#  define STM32_ADC2_JDR3            (STM32_ADC2_BASE+STM32_ADC_JDR3_OFFSET)
+#  define STM32_ADC2_JDR4            (STM32_ADC2_BASE+STM32_ADC_JDR4_OFFSET)
+#  define STM32_ADC2_DR              (STM32_ADC2_BASE+STM32_ADC_DR_OFFSET)
+#endif
+
+#if STM32F7_NADC > 2
+#  define STM32_ADC3_SR              (STM32_ADC3_BASE+STM32_ADC_SR_OFFSET)
+#  define STM32_ADC3_CR1             (STM32_ADC3_BASE+STM32_ADC_CR1_OFFSET)
+#  define STM32_ADC3_CR2             (STM32_ADC3_BASE+STM32_ADC_CR2_OFFSET)
+#  define STM32_ADC3_SMPR1           (STM32_ADC3_BASE+STM32_ADC_SMPR1_OFFSET)
+#  define STM32_ADC3_SMPR2           (STM32_ADC3_BASE+STM32_ADC_SMPR2_OFFSET)
+#  define STM32_ADC3_JOFR1           (STM32_ADC3_BASE+STM32_ADC_JOFR1_OFFSET)
+#  define STM32_ADC3_JOFR2           (STM32_ADC3_BASE+STM32_ADC_JOFR2_OFFSET)
+#  define STM32_ADC3_JOFR3           (STM32_ADC3_BASE+STM32_ADC_JOFR3_OFFSET)
+#  define STM32_ADC3_JOFR4           (STM32_ADC3_BASE+STM32_ADC_JOFR4_OFFSET)
+#  define STM32_ADC3_HTR             (STM32_ADC3_BASE+STM32_ADC_HTR_OFFSET)
+#  define STM32_ADC3_LTR             (STM32_ADC3_BASE+STM32_ADC_LTR_OFFSET)
+#  define STM32_ADC3_SQR1            (STM32_ADC3_BASE+STM32_ADC_SQR1_OFFSET)
+#  define STM32_ADC3_SQR2            (STM32_ADC3_BASE+STM32_ADC_SQR2_OFFSET)
+#  define STM32_ADC3_SQR3            (STM32_ADC3_BASE+STM32_ADC_SQR3_OFFSET)
+#  define STM32_ADC3_JSQR            (STM32_ADC3_BASE+STM32_ADC_JSQR_OFFSET)
+#  define STM32_ADC3_JDR1            (STM32_ADC3_BASE+STM32_ADC_JDR1_OFFSET)
+#  define STM32_ADC3_JDR2            (STM32_ADC3_BASE+STM32_ADC_JDR2_OFFSET)
+#  define STM32_ADC3_JDR3            (STM32_ADC3_BASE+STM32_ADC_JDR3_OFFSET)
+#  define STM32_ADC3_JDR4            (STM32_ADC3_BASE+STM32_ADC_JDR4_OFFSET)
+#  define STM32_ADC3_DR              (STM32_ADC3_BASE+STM32_ADC_DR_OFFSET)
+#endif
+
+#define STM32_ADC_CSR                (STM32_ADCCMN_BASE+STM32_ADC_CSR_OFFSET)
+#define STM32_ADC_CCR                (STM32_ADCCMN_BASE+STM32_ADC_CCR_OFFSET)
+#define STM32_ADC_CDR                (STM32_ADCCMN_BASE+STM32_ADC_CDR_OFFSET)
+
+/* Register Bitfield Definitions ********************************************************************/
+
+/* ADC status register */
+
+#define ADC_SR_AWD                   (1 << 0)  /* Bit 0 : Analog watchdog flag */
+#define ADC_SR_EOC                   (1 << 1)  /* Bit 1 : End of conversion */
+#define ADC_SR_JEOC                  (1 << 2)  /* Bit 2 : Injected channel end of conversion */
+#define ADC_SR_JSTRT                 (1 << 3)  /* Bit 3 : Injected channel Start flag */
+#define ADC_SR_STRT                  (1 << 4)  /* Bit 4 : Regular channel Start flag */
+#define ADC_SR_OVR                   (1 << 5)  /* Bit 5 : Overrun */
+
+/* ADC control register 1 */
+
+#define ADC_CR1_AWDCH_SHIFT          (0)       /* Bits 4-0: Analog watchdog channel select bits */
+#define ADC_CR1_AWDCH_MASK           (0x1f << ADC_CR1_AWDCH_SHIFT)
+#define ADC_CR1_EOCIE                (1 << 5)  /* Bit 5: Interrupt enable for EOC */
+#define ADC_CR1_AWDIE                (1 << 6)  /* Bit 6: Analog Watchdog interrupt enable */
+#define ADC_CR1_JEOCIE               (1 << 7)  /* Bit 7: Interrupt enable for injected channels */
+#define ADC_CR1_SCAN                 (1 << 8)  /* Bit 8: Scan mode */
+#define ADC_CR1_AWDSGL               (1 << 9)  /* Bit 9: Enable the watchdog on a single channel in scan mode */
+#define ADC_CR1_JAUTO                (1 << 10) /* Bit 10: Automatic Injected Group conversion */
+#define ADC_CR1_DISCEN               (1 << 11) /* Bit 11: Discontinuous mode on regular channels */
+#define ADC_CR1_JDISCEN              (1 << 12) /* Bit 12: Discontinuous mode on injected channels */
+#define ADC_CR1_DISCNUM_SHIFT        (13)      /* Bits 15-13: Discontinuous mode channel count */
+#define ADC_CR1_DISCNUM_MASK         (0x07 << ADC_CR1_DISCNUM_SHIFT)
+#define ADC_CR1_JAWDEN               (1 << 22) /* Bit 22: Analog watchdog enable on injected channels */
+#define ADC_CR1_AWDEN                (1 << 23) /* Bit 23: Analog watchdog enable on regular channels */
+#define ADC_CR1_RES_SHIFT            (24)      /* Bits 24-25: Resolution */
+#define ADC_CR1_RES_MASK             (3 << ADC_CR1_RES_SHIFT)
+#define ADC_CR1_RES_12BIT            (0 << ADC_CR1_RES_SHIFT) /* 15 ADCCLK cycles. For STM32L15XX: 12 ADCCLK cycles */
+#define ADC_CR1_RES_10BIT            (1 << ADC_CR1_RES_SHIFT) /* 13 ADCCLK cycles. For STM32L15XX: 11 ADCCLK cycles */
+#define ADC_CR1_RES_8BIT             (2 << ADC_CR1_RES_SHIFT) /* 11 ADCCLK cycles. For STM32L15XX: 9 ADCCLK cycles */
+#define ADC_CR1_RES_6BIT             (3 << ADC_CR1_RES_SHIFT) /* 9 ADCCLK cycles. For STM32L15XX: 7 ADCCLK cycles */
+#define ADC_CR1_OVRIE                (1 << 26) /* Bit 26: Overrun interrupt enable */
+
+/* ADC control register 2 */
+
+#define ADC_CR2_ADON                 (1 << 0)  /* Bit 0: A/D Converter ON / OFF */
+#define ADC_CR2_CONT                 (1 << 1)  /* Bit 1: Continuous Conversion */
+#define ADC_CR2_DMA                  (1 << 8)  /* Bit 8: Direct Memory access mode */
+#define ADC_CR2_DDS                  (1 << 9)  /* Bit 9: DMA disable selection (for single ADC mode) */
+#define ADC_CR2_EOCS                 (1 << 10) /* Bit 10: End of conversion selection */
+#define ADC_CR2_ALIGN                (1 << 11) /* Bit 11: Data Alignment */
+                                               /* Bits 12-15: Reserved */
+#define ADC_CR2_JEXTSEL_SHIFT        (16)      /* Bits 16-19: External event select for injected group */
+#define ADC_CR2_JEXTSEL_MASK         (0x0f << ADC_CR2_JEXTSEL_SHIFT)
+#define ADC_CR2_JEXTSEL_T1TRGO       (0x00 << ADC_CR2_JEXTSEL_SHIFT) /* 0000: Timer 1 TRGO event */
+#define ADC_CR2_JEXTSEL_T1CC4        (0x01 << ADC_CR2_JEXTSEL_SHIFT) /* 0001: Timer 1 CC4 event */
+#define ADC_CR2_JEXTSEL_T2TRGO       (0x02 << ADC_CR2_JEXTSEL_SHIFT) /* 0010: Timer 2 TRGO event */
+#define ADC_CR2_JEXTSEL_T2CC1        (0x03 << ADC_CR2_JEXTSEL_SHIFT) /* 0011: Timer 2 CC1 event */
+#define ADC_CR2_JEXTSEL_T3CC4        (0x04 << ADC_CR2_JEXTSEL_SHIFT) /* 0100: Timer 3 CC4 event */
+#define ADC_CR2_JEXTSEL_T4TRGO       (0x05 << ADC_CR2_JEXTSEL_SHIFT) /* 0101: Timer 4 TRGO event */
+                                                                     /* 0110: NA */
+#define ADC_CR2_JEXTSEL_T8CC4        (0x07 << ADC_CR2_JEXTSEL_SHIFT) /* 0111: Timer 8 CC4 event */
+#define ADC_CR2_JEXTSEL_T1TRGO2      (0x08 << ADC_CR2_JEXTSEL_SHIFT) /* 1000: Timer 1 TRGO2 event */
+#define ADC_CR2_JEXTSEL_T8TRGO       (0x09 << ADC_CR2_JEXTSEL_SHIFT) /* 1001: Timer 8 TRGO event */
+#define ADC_CR2_JEXTSEL_T8TRGO2      (0x0a << ADC_CR2_JEXTSEL_SHIFT) /* 1010: Timer 8 TRGO2 event */
+#define ADC_CR2_JEXTSEL_T3CC3        (0x0b << ADC_CR2_JEXTSEL_SHIFT) /* 1011: Timer 3 CC3 event */
+#define ADC_CR2_JEXTSEL_T5TRGO       (0x0c << ADC_CR2_JEXTSEL_SHIFT) /* 1100: Timer 5 TRGO event */
+#define ADC_CR2_JEXTSEL_T3CC1        (0x0d << ADC_CR2_JEXTSEL_SHIFT) /* 1101: Timer 3 CC1 event */
+#define ADC_CR2_JEXTSEL_T6TRGO       (0x0e << ADC_CR2_JEXTSEL_SHIFT) /* 1110: Timer 6 TRGO event */
+                                                                     /* 1111: Reserved */
+#define ADC_CR2_JEXTEN_SHIFT         (20)      /* Bits 20-21: External trigger enable for injected channels */
+#define ADC_CR2_JEXTEN_MASK          (3 << ADC_CR2_JEXTEN_SHIFT)
+#define ADC_CR2_JEXTEN_NONE          (0 << ADC_CR2_JEXTEN_SHIFT) /* 00: Trigger detection disabled */
+#define ADC_CR2_JEXTEN_RISING        (1 << ADC_CR2_JEXTEN_SHIFT) /* 01: Trigger detection on the rising edge */
+#define ADC_CR2_JEXTEN_FALLING       (2 << ADC_CR2_JEXTEN_SHIFT) /* 10: Trigger detection on the falling edge */
+#define ADC_CR2_JEXTEN_BOTH          (3 << ADC_CR2_JEXTEN_SHIFT) /* 11: Trigger detection on both the rising and falling edges */
+#define ADC_CR2_JSWSTART             (1 << 22) /* Bit 22: Start Conversion of injected channels */
+                                               /* Bit 23: Reserved, must be kept at reset value. */
+#define ADC_CR2_EXTSEL_SHIFT         (24)      /* Bits 24-27: External Event Select for regular group */
+#define ADC_CR2_EXTSEL_MASK          (0x0f << ADC_CR2_EXTSEL_SHIFT)
+#define ADC_CR2_EXTSEL_T1CC1         (0x0 << ADC_CR2_EXTSEL_SHIFT)  /* 0000: Timer 1 CC1 event */
+#define ADC_CR2_EXTSEL_T1CC2         (0x01 << ADC_CR2_EXTSEL_SHIFT) /* 0001: Timer 1 CC2 event */
+#define ADC_CR2_EXTSEL_T1CC3         (0x02 << ADC_CR2_EXTSEL_SHIFT) /* 0010: Timer 1 CC3 event */
+#define ADC_CR2_EXTSEL_T2CC2         (0x03 << ADC_CR2_EXTSEL_SHIFT) /* 0011: Timer 2 CC2 event */
+#define ADC_CR2_EXTSEL_T5TRGO        (0x04 << ADC_CR2_EXTSEL_SHIFT) /* 0100: Timer 5 TRGO event */
+#define ADC_CR2_EXTSEL_T4CC4         (0x05 << ADC_CR2_EXTSEL_SHIFT) /* 0101: Timer 4 CC4 event */
+#define ADC_CR2_EXTSEL_T3CC4         (0x06 << ADC_CR2_EXTSEL_SHIFT) /* 0110: Timer 3 CC4 event */
+#define ADC_CR2_EXTSEL_T8TRGO        (0x07 << ADC_CR2_EXTSEL_SHIFT) /* 0111: Timer 8 TRGO event */
+#define ADC_CR2_EXTSEL_T8TRGO2       (0x08 << ADC_CR2_EXTSEL_SHIFT) /* 1000: Timer 8 TRGO2 event */
+#define ADC_CR2_EXTSEL_T1TRGO        (0x09 << ADC_CR2_EXTSEL_SHIFT) /* 1001: Timer 1 TRGO event */
+#define ADC_CR2_EXTSEL_T1TRGO2       (0x0a << ADC_CR2_EXTSEL_SHIFT) /* 1010: Timer 1 TRGO2 event */
+#define ADC_CR2_EXTSEL_T2TRGO        (0x0b << ADC_CR2_EXTSEL_SHIFT) /* 1011: Timer 2 TRGO event */
+#define ADC_CR2_EXTSEL_T4TRGO        (0x0c << ADC_CR2_EXTSEL_SHIFT) /* 1100: Timer 4 TRGO event */
+#define ADC_CR2_EXTSEL_T6TRGO        (0x0d << ADC_CR2_EXTSEL_SHIFT) /* 1101: Timer 6 TRGO event */
+                                                                    /* 1110: NA */
+#define ADC_CR2_EXTSEL_EXTI11        (0x0f << ADC_CR2_EXTSEL_SHIFT) /* 1111: EXTI line 11 */
+#define ADC_CR2_EXTEN_SHIFT          (28)      /* Bits 28-29: External trigger enable for regular channels */
+#define ADC_CR2_EXTEN_MASK           (3 << ADC_CR2_EXTEN_SHIFT)
+#define ADC_CR2_EXTEN_NONE           (0 << ADC_CR2_EXTEN_SHIFT) /* 00: Trigger detection disabled */
+#define ADC_CR2_EXTEN_RISING         (1 << ADC_CR2_EXTEN_SHIFT) /* 01: Trigger detection on the rising edge */
+#define ADC_CR2_EXTEN_FALLING        (2 << ADC_CR2_EXTEN_SHIFT) /* 10: Trigger detection on the falling edge */
+#define ADC_CR2_EXTEN_BOTH           (3 << ADC_CR2_EXTEN_SHIFT) /* 11: Trigger detection on both the rising and falling edges */
+
+#  define ADC_CR2_SWSTART            (1 << 30) /* Bit 30: Start Conversion of regular channels */
+
+/* ADC sample time register 1 */
+
+#define ADC_SMPR_3                   0         /* 000: 3 cycles */
+#define ADC_SMPR_15                  1         /* 001: 15 cycles */
+#define ADC_SMPR_28                  2         /* 010: 28 cycles */
+#define ADC_SMPR_56                  3         /* 011: 56 cycles */
+#define ADC_SMPR_84                  4         /* 100: 84 cycles */
+#define ADC_SMPR_112                 5         /* 101: 112 cycles */
+#define ADC_SMPR_144                 6         /* 110: 144 cycles */
+#define ADC_SMPR_480                 7         /* 111: 480 cycles */
+#define ADC_SMPR1_SMP10_SHIFT        (0)       /* Bits 0-2: Channel 10 Sample time selection */
+#define ADC_SMPR1_SMP10_MASK         (7 << ADC_SMPR1_SMP10_SHIFT)
+#define ADC_SMPR1_SMP11_SHIFT        (3)       /* Bits 3-5: Channel 11 Sample time selection */
+#define ADC_SMPR1_SMP11_MASK         (7 << ADC_SMPR1_SMP11_SHIFT)
+#define ADC_SMPR1_SMP12_SHIFT        (6)       /* Bits 6-8: Channel 12 Sample time selection */
+#define ADC_SMPR1_SMP12_MASK         (7 << ADC_SMPR1_SMP12_SHIFT)
+#define ADC_SMPR1_SMP13_SHIFT        (9)       /* Bits 9-11: Channel 13 Sample time selection */
+#define ADC_SMPR1_SMP13_MASK         (7 << ADC_SMPR1_SMP13_SHIFT)
+#define ADC_SMPR1_SMP14_SHIFT        (12)      /* Bits 12-14: Channel 14 Sample time selection */
+#define ADC_SMPR1_SMP14_MASK         (7 << ADC_SMPR1_SMP14_SHIFT)
+#define ADC_SMPR1_SMP15_SHIFT        (15)      /* Bits 15-17: Channel 15 Sample time selection */
+#define ADC_SMPR1_SMP15_MASK         (7 << ADC_SMPR1_SMP15_SHIFT)
+#define ADC_SMPR1_SMP16_SHIFT        (18)      /* Bits 18-20: Channel 16 Sample time selection */
+#define ADC_SMPR1_SMP16_MASK         (7 << ADC_SMPR1_SMP16_SHIFT)
+#define ADC_SMPR1_SMP17_SHIFT        (21)      /* Bits 21-23: Channel 17 Sample time selection */
+#define ADC_SMPR1_SMP17_MASK         (7 << ADC_SMPR1_SMP17_SHIFT)
+#define ADC_SMPR1_SMP18_SHIFT        (24)      /* Bits 24-26: Channel 18 Sample time selection */
+#define ADC_SMPR1_SMP18_MASK         (7 << ADC_SMPR1_SMP17_SHIFT)
+
+
+/* ADC sample time register 2 */
+
+#define ADC_SMPR2_SMP0_SHIFT         (0)       /* Bits 2-0: Channel 0 Sample time selection */
+#define ADC_SMPR2_SMP0_MASK          (7 << ADC_SMPR2_SMP0_SHIFT)
+#define ADC_SMPR2_SMP1_SHIFT         (3)       /* Bits 5-3: Channel 1 Sample time selection */
+#define ADC_SMPR2_SMP1_MASK          (7 << ADC_SMPR2_SMP1_SHIFT)
+#define ADC_SMPR2_SMP2_SHIFT         (6)       /* Bits 8-6: Channel 2 Sample time selection */
+#define ADC_SMPR2_SMP2_MASK          (7 << ADC_SMPR2_SMP2_SHIFT)
+#define ADC_SMPR2_SMP3_SHIFT         (9)       /* Bits 11-9: Channel 3 Sample time selection */
+#define ADC_SMPR2_SMP3_MASK          (7 << ADC_SMPR2_SMP3_SHIFT)
+#define ADC_SMPR2_SMP4_SHIFT         (12)      /* Bits 14-12: Channel 4 Sample time selection */
+#define ADC_SMPR2_SMP4_MASK          (7 << ADC_SMPR2_SMP4_SHIFT)
+#define ADC_SMPR2_SMP5_SHIFT         (15)      /* Bits 17-15: Channel 5 Sample time selection */
+#define ADC_SMPR2_SMP5_MASK          (7 << ADC_SMPR2_SMP5_SHIFT)
+#define ADC_SMPR2_SMP6_SHIFT         (18)      /* Bits 20-18: Channel 6 Sample time selection */
+#define ADC_SMPR2_SMP6_MASK          (7 << ADC_SMPR2_SMP6_SHIFT)
+#define ADC_SMPR2_SMP7_SHIFT         (21)      /* Bits 23-21: Channel 7 Sample time selection */
+#define ADC_SMPR2_SMP7_MASK          (7 << ADC_SMPR2_SMP7_SHIFT)
+#define ADC_SMPR2_SMP8_SHIFT         (24)      /* Bits 26-24: Channel 8 Sample time selection */
+#define ADC_SMPR2_SMP8_MASK          (7 << ADC_SMPR2_SMP8_SHIFT)
+#define ADC_SMPR2_SMP9_SHIFT         (27)      /* Bits 29-27: Channel 9 Sample time selection */
+#define ADC_SMPR2_SMP9_MASK          (7 << ADC_SMPR2_SMP9_SHIFT)
+
+
+/* ADC injected channel data offset register 1-4 */
+
+#define ADC_JOFR_SHIFT               (0)       /* Bits 11-0: Data offset for injected channel x */
+#define ADC_JOFR_MASK                (0x0fff << ADC_JOFR_SHIFT)
+
+/* ADC watchdog high threshold register */
+
+#define ADC_HTR_SHIFT                (0)       /* Bits 11-0: Analog watchdog high threshold */
+#define ADC_HTR_MASK                 (0x0fff << ADC_HTR_SHIFT)
+
+/* ADC watchdog low threshold register */
+
+#define ADC_LTR_SHIFT                (0)       /* Bits 11-0: Analog watchdog low threshold */
+#define ADC_LTR_MASK                 (0x0fff << ADC_LTR_SHIFT)
+
+/* ADC regular sequence register 1 */
+
+#define ADC_SQR1_SQ13_SHIFT          (0)       /* Bits 4-0: 13th conversion in regular sequence */
+#define ADC_SQR1_SQ13_MASK           (0x1f << ADC_SQR1_SQ13_SHIFT)
+#define ADC_SQR1_SQ14_SHIFT          (5)       /* Bits 9-5: 14th conversion in regular sequence */
+#define ADC_SQR1_SQ14_MASK           (0x1f << ADC_SQR1_SQ14_SHIFT)
+#define ADC_SQR1_SQ15_SHIFT          (10)      /* Bits 14-10: 15th conversion in regular sequence */
+#define ADC_SQR1_SQ15_MASK           (0x1f << ADC_SQR1_SQ15_SHIFT)
+#define ADC_SQR1_SQ16_SHIFT          (15)      /* Bits 19-15: 16th conversion in regular sequence */
+#define ADC_SQR1_SQ16_MASK           (0x1f << ADC_SQR1_SQ16_SHIFT)
+#define ADC_SQR1_L_SHIFT             (20)      /* Bits 23-20: Regular channel sequence length */
+#define ADC_SQR1_L_MASK              (0x0f << ADC_SQR1_L_SHIFT)
+#define ADC_SQR1_RESERVED            (0xff000000)
+#define ADC_SQR1_FIRST               (13)
+#define ADC_SQR1_LAST                (16)
+#define ADC_SQR1_SQ_OFFSET           (0)
+
+/* ADC regular sequence register 2 */
+
+#define ADC_SQR2_SQ7_SHIFT           (0)       /* Bits 4-0: 7th conversion in regular sequence */
+#define ADC_SQR2_SQ7_MASK            (0x1f << ADC_SQR2_SQ7_SHIFT)
+#define ADC_SQR2_SQ8_SHIFT           (5)       /* Bits 9-5: 8th conversion in regular sequence */
+#define ADC_SQR2_SQ8_MASK            (0x1f << ADC_SQR2_SQ8_SHIFT)
+#define ADC_SQR2_SQ9_SHIFT           (10)      /* Bits 14-10: 9th conversion in regular sequence */
+#define ADC_SQR2_SQ9_MASK            (0x1f << ADC_SQR2_SQ9_SHIFT)
+#define ADC_SQR2_SQ10_SHIFT          (15)      /* Bits 19-15: 10th conversion in regular sequence */
+#define ADC_SQR2_SQ10_MASK           (0x1f << ADC_SQR2_SQ10_SHIFT)
+#define ADC_SQR2_SQ11_SHIFT          (20)      /* Bits 24-20: 11th conversion in regular sequence */
+#define ADC_SQR2_SQ11_MASK           (0x1f << ADC_SQR2_SQ11_SHIFT )
+#define ADC_SQR2_SQ12_SHIFT          (25)      /* Bits 29-25: 12th conversion in regular sequence */
+#define ADC_SQR2_SQ12_MASK           (0x1f << ADC_SQR2_SQ12_SHIFT)
+#define ADC_SQR2_RESERVED            (0xc0000000)
+#define ADC_SQR2_FIRST               (7)
+#define ADC_SQR2_LAST                (12)
+#define ADC_SQR2_SQ_OFFSET           (0)
+
+/* ADC regular sequence register 3 */
+
+#define ADC_SQR3_SQ1_SHIFT           (0)       /* Bits 4-0: 1st conversion in regular sequence */
+#define ADC_SQR3_SQ1_MASK            (0x1f << ADC_SQR3_SQ1_SHIFT)
+#define ADC_SQR3_SQ2_SHIFT           (5)       /* Bits 9-5: 2nd conversion in regular sequence */
+#define ADC_SQR3_SQ2_MASK            (0x1f << ADC_SQR3_SQ2_SHIFT)
+#define ADC_SQR3_SQ3_SHIFT           (10)      /* Bits 14-10: 3rd conversion in regular sequence */
+#define ADC_SQR3_SQ3_MASK            (0x1f << ADC_SQR3_SQ3_SHIFT)
+#define ADC_SQR3_SQ4_SHIFT           (15)      /* Bits 19-15: 4th conversion in regular sequence */
+#define ADC_SQR3_SQ4_MASK            (0x1f << ADC_SQR3_SQ4_SHIFT)
+#define ADC_SQR3_SQ5_SHIFT           (20)      /* Bits 24-20: 5th conversion in regular sequence */
+#define ADC_SQR3_SQ5_MASK            (0x1f << ADC_SQR3_SQ5_SHIFT )
+#define ADC_SQR3_SQ6_SHIFT           (25)      /* Bits 29-25: 6th conversion in regular sequence */
+#define ADC_SQR3_SQ6_MASK            (0x1f << ADC_SQR3_SQ6_SHIFT)
+#define ADC_SQR3_RESERVED            (0xc0000000)
+#define ADC_SQR3_FIRST               (1)
+#define ADC_SQR3_LAST                (6)
+#define ADC_SQR3_SQ_OFFSET           (0)
+
+/* Offset between SQ bits */
+
+#define ADC_SQ_OFFSET                (5)
+
+/* ADC injected sequence register */
+
+#define ADC_JSQR_JSQ1_SHIFT          (0)       /* Bits 4-0: 1st conversion in injected sequence */
+#define ADC_JSQR_JSQ1_MASK           (0x1f << ADC_JSQR_JSQ1_SHIFT)
+#define ADC_JSQR_JSQ2_SHIFT          (5)       /* Bits 9-5: 2nd conversion in injected sequence */
+#define ADC_JSQR_JSQ2_MASK           (0x1f << ADC_JSQR_JSQ2_SHIFT)
+#define ADC_JSQR_JSQ3_SHIFT          (10)      /* Bits 14-10: 3rd conversion in injected sequence */
+#define ADC_JSQR_JSQ3_MASK           (0x1f << ADC_JSQR_JSQ3_SHIFT)
+#define ADC_JSQR_JSQ4_SHIFT          (15)      /* Bits 19-15: 4th conversion in injected sequence */
+#define ADC_JSQR_JSQ4_MASK           (0x1f << ADC_JSQR_JSQ4_SHIFT)
+#define ADC_JSQR_JL_SHIFT            (20)      /* Bits 21-20: Injected Sequence length */
+#define ADC_JSQR_JL_MASK             (3 << ADC_JSQR_JL_SHIFT)
+
+/* ADC injected data register 1-4 */
+
+#define ADC_JDR_JDATA_SHIFT          (0)       /* Bits 15-0: Injected data */
+#define ADC_JDR_JDATA_MASK           (0xffff << ADC_JDR_JDATA_SHIFT)
+
+/* ADC regular data register */
+
+#define ADC_DR_RDATA_SHIFT           (0)       /* Bits 15-0 Regular data */
+#define ADC_DR_RDATA_MASK            (0xffff << ADC_DR_RDATA_SHIFT)
+
+/* Common status register */
+
+#define ADC_CSR_AWD1                 (1 << 0)  /* Bit 0:  Analog watchdog flag of ADC1 (copy of AWD in ADC1_SR) */
+#define ADC_CSR_EOC1                 (1 << 1)  /* Bit 1:  End of conversion of ADC1 (copy of EOC in ADC1_SR) */
+#define ADC_CSR_JEOC1                (1 << 2)  /* Bit 2:  Injected channel end of conversion of ADC1 (copy of JEOC in ADC1_SR) */
+#define ADC_CSR_JSTRT1               (1 << 3)  /* Bit 3:  Injected channel Start flag of ADC1 (copy of JSTRT in ADC1_SR) */
+#define ADC_CSR_STRT1                (1 << 4)  /* Bit 4:  Regular channel Start flag of ADC1 (copy of STRT in ADC1_SR) */
+#define ADC_CSR_OVR1                 (1 << 5)  /* Bit 5:  Overrun flag of ADC1 (copy of OVR in ADC1_SR) */
+
+#define ADC_CSR_AWD2                 (1 << 8)  /* Bit 8:  Analog watchdog flag of ADC2 (copy of AWD in ADC2_SR) */
+#define ADC_CSR_EOC2                 (1 << 9)  /* Bit 9:  End of conversion of ADC2 (copy of EOC in ADC2_SR) */
+#define ADC_CSR_JEOC2                (1 << 10) /* Bit 10: Injected channel end of conversion of ADC2 (copy of JEOC in ADC2_SR) */
+#define ADC_CSR_JSTRT2               (1 << 11) /* Bit 11: Injected channel Start flag of ADC2 (copy of JSTRT in ADC2_SR) */
+#define ADC_CSR_STRT2                (1 << 12) /* Bit 12: Regular channel Start flag of ADC2 (copy of STRT in ADC2_SR) */
+#define ADC_CSR_OVR2                 (1 << 13) /* Bit 13: Overrun flag of ADC2 (copy of OVR in ADC2_SR) */
+                                               /* Bits 14-15: Reserved, must be kept at reset value. */
+#define ADC_CSR_AWD3                 (1 << 16) /* Bit 16: ADC3 Analog watchdog flag (copy of AWD in ADC3_SR) */
+#define ADC_CSR_EOC3                 (1 << 17) /* Bit 17: ADC3 End of conversion (copy of EOC in ADC3_SR) */
+#define ADC_CSR_JEOC3                (1 << 18) /* Bit 18: ADC3 Injected channel end of conversion (copy of JEOC in ADC3_SR) */
+#define ADC_CSR_JSTRT3               (1 << 19) /* Bit 19: ADC3 Injected channel Start flag (copy of JSTRT in ADC3_SR) */
+#define ADC_CSR_STRT3                (1 << 20) /* Bit 20: ADC3 Regular channel Start flag (copy of STRT in ADC3_SR). */
+#define ADC_CSR_OVR3                 (1 << 21) /* Bit 21: ADC3 overrun flag (copy of OVR in ADC3_SR). */
+
+/* Common control register */
+
+#  define ADC_CCR_MULTI_SHIFT        (0)       /* Bits 0-4: Multi ADC mode selection */
+#  define ADC_CCR_MULTI_MASK         (0x1f << ADC_CCR_MULTI_SHIFT)
+#    define ADC_CCR_MULTI_NONE       (0 << ADC_CCR_MULTI_SHIFT)  /* 00000: Independent mode */
+                                                                 /* 00001 to 01001: Dual mode (ADC1 and ADC2), ADC3 independent */
+#    define ADC_CCR_MULTI_RSISM2     (1 << ADC_CCR_MULTI_SHIFT)  /* 00001: Combined regular simultaneous + injected simultaneous mode */
+#    define ADC_CCR_MULTI_RSATM2     (2 << ADC_CCR_MULTI_SHIFT)  /* 00010: Combined regular simultaneous + alternate trigger mode */
+#    define ADC_CCR_MULTI_ISM2       (5 << ADC_CCR_MULTI_SHIFT)  /* 00101: Injected simultaneous mode only */
+#    define ADC_CCR_MULTI_RSM2       (6 << ADC_CCR_MULTI_SHIFT)  /* 00110: Regular simultaneous mode only */
+#    define ADC_CCR_MULTI_IM2        (7 << ADC_CCR_MULTI_SHIFT)  /* 00111: interleaved mode only */
+#    define ADC_CCR_MULTI_ATM2       (9 << ADC_CCR_MULTI_SHIFT)  /* 01001: Alternate trigger mode only */
+                                                                 /* 10001 to 11001: Triple mode (ADC1, 2 and 3) */
+#    define ADC_CCR_MULTI_RSISM3     (17 << ADC_CCR_MULTI_SHIFT) /* 10001: Combined regular simultaneous + injected simultaneous mode */
+#    define ADC_CCR_MULTI_RSATM3     (18 << ADC_CCR_MULTI_SHIFT) /* 10010: Combined regular simultaneous + alternate trigger mode */
+#    define ADC_CCR_MULTI_ISM3       (21 << ADC_CCR_MULTI_SHIFT) /* 10101: Injected simultaneous mode only */
+#    define ADC_CCR_MULTI_RSM3       (22 << ADC_CCR_MULTI_SHIFT) /* 10110: Regular simultaneous mode only */
+#    define ADC_CCR_MULTI_IM3        (23 << ADC_CCR_MULTI_SHIFT) /* 10111: interleaved mode only */
+#    define ADC_CCR_MULTI_ATM3       (25 << ADC_CCR_MULTI_SHIFT) /* 11001: Alternate trigger mode only */
+                                               /* Bits 5-7: Reserved, must be kept at reset value. */
+#  define ADC_CCR_DELAY_SHIFT        (8)       /* Bits 8-11: Delay between 2 sampling phases */
+#  define ADC_CCR_DELAY_MASK         (0xf << ADC_CCR_DELAY_SHIFT)
+#    define ADC_CCR_DELAY(n)         (((n)-5) << ADC_CCR_DELAY_SHIFT) /* n * TADCCLK, n=5-20 */
+                                               /* Bit 12 Reserved, must be kept at reset value. */
+#  define ADC_CCR_DDS                (1 << 13) /* Bit 13: DMA disable selection (for multi-ADC mode) */
+
+#  define ADC_CCR_DMA_SHIFT          (14)      /* Bits 14-15: Direct memory access mode for multi ADC mode */
+#  define ADC_CCR_DMA_MASK           (3 << ADC_CCR_DMA_SHIFT)
+#    define ADC_CCR_DMA_DISABLED     (0 << ADC_CCR_DMA_SHIFT) /* 00: DMA mode disabled */
+#    define ADC_CCR_DMA_MODE1        (1 << ADC_CCR_DMA_SHIFT) /* 01: DMA mode 1 enabled */
+#    define ADC_CCR_DMA_MODE2        (2 << ADC_CCR_DMA_SHIFT) /* 10: DMA mode 2 enabled */
+#    define ADC_CCR_DMA_MODE3        (3 << ADC_CCR_DMA_SHIFT) /* 11: DMA mode 3 enabled */
+
+#  define ADC_CCR_ADCPRE_SHIFT       (16)      /* Bits 16-17: ADC prescaler */
+#  define ADC_CCR_ADCPRE_MASK        (3 << ADC_CCR_ADCPRE_SHIFT)
+#    define ADC_CCR_ADCPRE_DIV2      (0 << ADC_CCR_ADCPRE_SHIFT) /* 00: PCLK2 divided by 2 */
+#    define ADC_CCR_ADCPRE_DIV4      (1 << ADC_CCR_ADCPRE_SHIFT) /* 01: PCLK2 divided by 4 */
+#    define ADC_CCR_ADCPRE_DIV6      (2 << ADC_CCR_ADCPRE_SHIFT) /* 10: PCLK2 divided by 6 */
+#    define ADC_CCR_ADCPRE_DIV8      (3 << ADC_CCR_ADCPRE_SHIFT) /* 11: PCLK2 divided by 8 */
+                                               /* Bits 18-21: Reserved, must be kept at reset value. */
+#  define ADC_CCR_VBATE              (1 << 22) /* Bit 22: VBAT enable */
+#  define ADC_CCR_TSVREFE            (1 << 23) /* Bit 23: Temperature sensor and VREFINT enable */
+                                               /* Bits 24-31 Reserved, must be kept at reset value. */
+
+/* Data register for dual and triple modes (32-bit data with no named fields) */
+
+/****************************************************************************************************
+ * Public Types
+ ****************************************************************************************************/
+
+/****************************************************************************************************
+ * Public Data
+ ****************************************************************************************************/
+
+/****************************************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX77XX_ADC_H */
diff --git a/arch/arm/src/stm32f7/chip/stm32f74xx77xx_i2c.h b/arch/arm/src/stm32f7/chip/stm32f74xx77xx_i2c.h
new file mode 100644
index 00000000000..7e2d801dc90
--- /dev/null
+++ b/arch/arm/src/stm32f7/chip/stm32f74xx77xx_i2c.h
@@ -0,0 +1,264 @@
+/************************************************************************************
+ * arch/arm/src/stm32f7/chip/stm32f74xx77xx_i2c.h
+ *
+ *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ *   Authors: Gregory Nutt <gnutt@nuttx.org>
+ *            David Sidrane <david_s5@nscdg.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32F7_STM32F74XX77XX_I2C_H
+#define __ARCH_ARM_SRC_STM32F7_STM32F74XX77XX_I2C_H
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Register Offsets *****************************************************************/
+
+#define STM32_I2C_CR1_OFFSET      0x0000 /* Control register 1 (32-bit) */
+#define STM32_I2C_CR2_OFFSET      0x0004 /* Control register 2 (32-bit) */
+#define STM32_I2C_OAR1_OFFSET     0x0008 /* Own address register 1 (16-bit) */
+#define STM32_I2C_OAR2_OFFSET     0x000c /* Own address register 2 (16-bit) */
+#define STM32_I2C_TIMINGR_OFFSET  0x0010 /* Timing register */
+#define STM32_I2C_TIMEOUTR_OFFSET 0x0014 /* Timeout register */
+#define STM32_I2C_ISR_OFFSET      0x0018 /* Interrupt and Status register */
+#define STM32_I2C_ICR_OFFSET      0x001c /* Interrupt clear register */
+#define STM32_I2C_PECR_OFFSET     0x0020 /* Packet error checking register */
+#define STM32_I2C_RXDR_OFFSET     0x0024 /* Receive data register */
+#define STM32_I2C_TXDR_OFFSET     0x0028 /* Transmit data register */
+
+/* Register Addresses ***************************************************************/
+
+#if STM32F7_NI2C > 0
+#  define STM32_I2C1_CR1          (STM32_I2C1_BASE+STM32_I2C_CR1_OFFSET)
+#  define STM32_I2C1_CR2          (STM32_I2C1_BASE+STM32_I2C_CR2_OFFSET)
+#  define STM32_I2C1_OAR1         (STM32_I2C1_BASE+STM32_I2C_OAR1_OFFSET)
+#  define STM32_I2C1_OAR2         (STM32_I2C1_BASE+STM32_I2C_OAR2_OFFSET)
+#  define STM32_I2C1_TIMINGR      (STM32_I2C1_BASE+STM32_I2C_TIMINGR_OFFSET)
+#  define STM32_I2C1_TIMEOUTR     (STM32_I2C1_BASE+STM32_I2C_TIMEOUTR_OFFSET)
+#  define STM32_I2C1_ISR          (STM32_I2C1_BASE+STM32_I2C_ISR_OFFSET)
+#  define STM32_I2C1_ICR          (STM32_I2C1_BASE+STM32_I2C_ICR_OFFSET)
+#  define STM32_I2C1_PECR         (STM32_I2C1_BASE+STM32_I2C_PECR_OFFSET)
+#  define STM32_I2C1_RXDR         (STM32_I2C1_BASE+STM32_I2C_RXDR_OFFSET)
+#  define STM32_I2C1_TXDR         (STM32_I2C1_BASE+STM32_I2C_TXDR_OFFSET)
+#endif
+
+#if STM32F7_NI2C > 1
+#  define STM32_I2C2_CR1          (STM32_I2C2_BASE+STM32_I2C_CR1_OFFSET)
+#  define STM32_I2C2_CR2          (STM32_I2C2_BASE+STM32_I2C_CR2_OFFSET)
+#  define STM32_I2C2_OAR1         (STM32_I2C2_BASE+STM32_I2C_OAR1_OFFSET)
+#  define STM32_I2C2_OAR2         (STM32_I2C2_BASE+STM32_I2C_OAR2_OFFSET)
+#  define STM32_I2C2_TIMINGR      (STM32_I2C2_BASE+STM32_I2C_TIMINGR_OFFSET)
+#  define STM32_I2C2_TIMEOUTR     (STM32_I2C2_BASE+STM32_I2C_TIMEOUTR_OFFSET)
+#  define STM32_I2C2_ISR          (STM32_I2C2_BASE+STM32_I2C_ISR_OFFSET)
+#  define STM32_I2C2_ICR          (STM32_I2C2_BASE+STM32_I2C_ICR_OFFSET)
+#  define STM32_I2C2_PECR         (STM32_I2C2_BASE+STM32_I2C_PECR_OFFSET)
+#  define STM32_I2C2_RXDR         (STM32_I2C2_BASE+STM32_I2C_RXDR_OFFSET)
+#  define STM32_I2C2_TXDR         (STM32_I2C2_BASE+STM32_I2C_TXDR_OFFSET)
+#endif
+
+#if STM32F7_NI2C > 2
+#  define STM32_I2C3_CR1          (STM32_I2C3_BASE+STM32_I2C_CR1_OFFSET)
+#  define STM32_I2C3_CR2          (STM32_I2C3_BASE+STM32_I2C_CR2_OFFSET)
+#  define STM32_I2C3_OAR1         (STM32_I2C3_BASE+STM32_I2C_OAR1_OFFSET)
+#  define STM32_I2C3_OAR2         (STM32_I2C3_BASE+STM32_I2C_OAR2_OFFSET)
+#  define STM32_I2C3_TIMINGR      (STM32_I2C3_BASE+STM32_I2C_TIMINGR_OFFSET)
+#  define STM32_I2C3_TIMEOUTR     (STM32_I2C3_BASE+STM32_I2C_TIMEOUTR_OFFSET)
+#  define STM32_I2C3_ISR          (STM32_I2C3_BASE+STM32_I2C_ISR_OFFSET)
+#  define STM32_I2C3_ICR          (STM32_I2C3_BASE+STM32_I2C_ICR_OFFSET)
+#  define STM32_I2C3_PECR         (STM32_I2C3_BASE+STM32_I2C_PECR_OFFSET)
+#  define STM32_I2C3_RXDR         (STM32_I2C3_BASE+STM32_I2C_RXDR_OFFSET)
+#  define STM32_I2C3_TXDR         (STM32_I2C3_BASE+STM32_I2C_TXDR_OFFSET)
+#endif
+
+#if STM32F7_NI2C > 3
+#  define STM32_I2C4_CR1          (STM32_I2C4_BASE+STM32_I2C_CR1_OFFSET)
+#  define STM32_I2C4_CR2          (STM32_I2C4_BASE+STM32_I2C_CR2_OFFSET)
+#  define STM32_I2C4_OAR1         (STM32_I2C4_BASE+STM32_I2C_OAR1_OFFSET)
+#  define STM32_I2C4_OAR2         (STM32_I2C4_BASE+STM32_I2C_OAR2_OFFSET)
+#  define STM32_I2C4_TIMINGR      (STM32_I2C4_BASE+STM32_I2C_TIMINGR_OFFSET)
+#  define STM32_I2C4_TIMEOUTR     (STM32_I2C4_BASE+STM32_I2C_TIMEOUTR_OFFSET)
+#  define STM32_I2C4_ISR          (STM32_I2C4_BASE+STM32_I2C_ISR_OFFSET)
+#  define STM32_I2C4_ICR          (STM32_I2C4_BASE+STM32_I2C_ICR_OFFSET)
+#  define STM32_I2C4_PECR         (STM32_I2C4_BASE+STM32_I2C_PECR_OFFSET)
+#  define STM32_I2C4_RXDR         (STM32_I2C4_BASE+STM32_I2C_RXDR_OFFSET)
+#  define STM32_I2C4_TXDR         (STM32_I2C4_BASE+STM32_I2C_TXDR_OFFSET)
+#endif
+
+/* Register Bitfield Definitions ****************************************************/
+
+/* Control register 1 */
+
+#define I2C_CR1_PE                (1 << 0)  /* Bit 0:  Peripheral Enable */
+#define I2C_CR1_TXIE              (1 << 1)  /* Bit 1:  TX Interrupt enable */
+#define I2C_CR1_RXIE              (1 << 2)  /* Bit 2:  RX Interrupt enable */
+#define I2C_CR1_ADDRIE            (1 << 3)  /* Bit 3:  Address match interrupt enable (slave) */
+#define I2C_CR1_NACKIE            (1 << 4)  /* Bit 4:  Not acknowledge received interrupt enable */
+#define I2C_CR1_STOPIE            (1 << 5)  /* Bit 5:  STOP detection interrupt enable */
+#define I2C_CR1_TCIE              (1 << 6)  /* Bit 6:  Transfer Complete interrupt enable */
+#define I2C_CR1_ERRIE             (1 << 7)  /* Bit 7:  Error interrupts enable */
+#define I2C_CR1_DNF_SHIFT         (8)       /* Bits 8-11: Digital noise filter */
+#define I2C_CR1_DNF_MASK          (0xf << I2C_CR1_DNF_SHIFT)
+#  define I2C_CR1_DNF_DISABLE     (0 << I2C_CR1_DNF_SHIFT)
+#  define I2C_CR1_DNF(n)          ((n) << I2C_CR1_DNF_SHIFT) /* Up to n * Ti2cclk, n=1..15 */
+#define I2C_CR1_ANFOFF            (1 << 12) /* Bit 12: Analog noise filter OFF */
+#define I2C_CR1_TXDMAEN           (1 << 14) /* Bit 14: DMA transmission requests enable */
+#define I2C_CR1_RXDMAEN           (1 << 15) /* Bit 15: DMA reception requests enable */
+#define I2C_CR1_SBC               (1 << 16) /* Bit 16: Slave byte control */
+#define I2C_CR1_NOSTRETCH         (1 << 17) /* Bit 17: Clock stretching disable */
+#define I2C_CR1_GCEN              (1 << 19) /* Bit 19: General call enable */
+#define I2C_CR1_SMBHEN            (1 << 20) /* Bit 20: SMBus Host address enable */
+#define I2C_CR1_SMBDEN            (1 << 21) /* Bit 21: SMBus Device Default address enable */
+#define I2C_CR1_ALERTEN           (1 << 22) /* Bit 22: SMBus alert enable */
+#define I2C_CR1_PECEN             (1 << 23) /* Bit 23: PEC enable */
+
+/* Control register 2 */
+
+#define I2C_CR2_SADD10_SHIFT      (0)       /* Bits 0-9: Slave 10-bit address (master) */
+#define I2C_CR2_SADD10_MASK       (0x3ff << I2C_CR2_SADD10_SHIFT)
+#define I2C_CR2_SADD7_SHIFT       (1)       /* Bits 1-7: Slave 7-bit address (master) */
+#define I2C_CR2_SADD7_MASK        (0x7f << I2C_CR2_SADD7_SHIFT)
+#define I2C_CR2_RD_WRN            (1 << 10) /* Bit 10: Transfer direction (master) */
+#define I2C_CR2_ADD10             (1 << 11) /* Bit 11: 10-bit addressing mode (master) */
+#define I2C_CR2_HEAD10R           (1 << 12) /* Bit 12: 10-bit address header only read direction (master) */
+#define I2C_CR2_START             (1 << 13) /* Bit 13: Start generation */
+#define I2C_CR2_STOP              (1 << 14) /* Bit 14: Stop generation (master) */
+#define I2C_CR2_NACK              (1 << 15) /* Bit 15: NACK generation (slave) */
+#define I2C_CR2_NBYTES_SHIFT      (16)      /* Bits 16-23: Number of bytes */
+#define I2C_CR2_NBYTES_MASK       (0xff << I2C_CR2_NBYTES_SHIFT)
+#define I2C_CR2_RELOAD            (1 << 24) /* Bit 24: NBYTES reload mode */
+#define I2C_CR2_AUTOEND           (1 << 25) /* Bit 25: Automatic end mode (master) */
+#define I2C_CR2_PECBYTE           (1 << 26) /* Bit 26: Packet error checking byte */
+
+/* Own address register 1 */
+
+#define I2C_OAR1_OA1_10_SHIFT     (0)       /* Bits 0-9: 10-bit interface address */
+#define I2C_OAR1_OA1_10_MASK      (0x3ff << I2C_OAR1_OA1_10_SHIFT)
+#define I2C_OAR1_OA1_7_SHIFT      (1)       /* Bits 1-7: 7-bit interface address */
+#define I2C_OAR1_OA1_7_MASK       (0x7f << I2C_OAR1_OA1_7_SHIFT)
+#define I2C_OAR1_OA1MODE          (1 << 10) /* Bit 10: Own Address 1 10-bit mode */
+#define I2C_OAR1_OA1EN            (1 << 15) /* Bit 15: Own Address 1 enable */
+
+/* Own address register 2 */
+
+#define I2C_OAR2_OA2_SHIFT        (1)       /* Bits 1-7: 7-bit interface address */
+#define I2C_OAR2_OA2_MASK         (0x7f << I2C_OAR2_OA2_SHIFT)
+#define I2C_OAR2_OA2MSK_SHIFT     (8)       /* Bits 8-10: Own Address 2 masks */
+#define I2C_OAR2_OA2MSK_MASK      (7 << I2C_OAR2_OA2MSK_SHIFT)
+#  define I2C_OAR2_OA2MSK_NONE    (0 << I2C_OAR2_OA2MSK_SHIFT) /* No mask */
+#  define I2C_OAR2_OA2MSK_2_7     (1 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:2] are compared */
+#  define I2C_OAR2_OA2MSK_3_7     (2 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:3] are compared */
+#  define I2C_OAR2_OA2MSK_4_7     (3 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:4] are compared */
+#  define I2C_OAR2_OA2MSK_5_7     (4 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:5] are compared */
+#  define I2C_OAR2_OA2MSK_6_7     (5 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:6] are compared */
+#  define I2C_OAR2_OA2MSK_7       (6 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7] is compared */
+#  define I2C_OAR2_OA2MSK_ALL     (7 << I2C_OAR2_OA2MSK_SHIFT) /* All 7-bit addresses acknowledged */
+#define I2C_OAR2_OA2EN            (1 << 15)  /* Bit 15: Own Address 2 enable */
+
+/* Timing register */
+
+#define I2C_TIMINGR_SCLL_SHIFT    (0)        /* Bits 0-7: SCL low period (master) */
+#define I2C_TIMINGR_SCLL_MASK     (0xff << I2C_TIMINGR_SCLL_SHIFT)
+#  define I2C_TIMINGR_SCLL(n)     (((n)-1) << I2C_TIMINGR_SCLL_SHIFT) /* tSCLL = n x tPRESC */
+
+#define I2C_TIMINGR_SCLH_SHIFT    (8)        /* Bits 8-15: SCL high period (master) */
+#define I2C_TIMINGR_SCLH_MASK     (0xff << I2C_TIMINGR_SCLH_SHIFT)
+#  define I2C_TIMINGR_SCLH(n)     (((n)-1) << I2C_TIMINGR_SCLH_SHIFT) /* tSCLH = n x tPRESC */
+
+#define I2C_TIMINGR_SDADEL_SHIFT  (16)        /* Bits 16-19: Data hold time */
+#define I2C_TIMINGR_SDADEL_MASK   (0xf << I2C_TIMINGR_SDADEL_SHIFT)
+#  define I2C_TIMINGR_SDADEL(n)   ((n) << I2C_TIMINGR_SDADEL_SHIFT) /* tSDADEL= n x tPRESC */
+
+#define I2C_TIMINGR_SCLDEL_SHIFT  (20)        /* Bits 20-23: Data setup time */
+#define I2C_TIMINGR_SCLDEL_MASK   (0xf << I2C_TIMINGR_SCLDEL_SHIFT)
+#  define I2C_TIMINGR_SCLDEL(n)   (((n)-1) << I2C_TIMINGR_SCLDEL_SHIFT) /* tSCLDEL = n x tPRESC */
+
+#define I2C_TIMINGR_PRESC_SHIFT   (28)        /* Bits 28-31: Timing prescaler */
+#define I2C_TIMINGR_PRESC_MASK    (0xf << I2C_TIMINGR_PRESC_SHIFT)
+#  define I2C_TIMINGR_PRESC(n)    (((n)-1) << I2C_TIMINGR_PRESC_SHIFT) /* tPRESC = n x tI2CCLK */
+
+/* Timeout register */
+
+#define I2C_TIMEOUTR_A_SHIFT      (0)       /* Bits 0-11: Bus Timeout A */
+#define I2C_TIMEOUTR_A_MASK       (0x0fff << I2C_TIMEOUTR_A_SHIFT)
+#  define I2C_TIMEOUTR_A(n)       ((n) << I2C_TIMEOUTR_A_SHIFT)
+#define I2C_TIMEOUTR_TIDLE        (1 << 12) /* Bit 12: Idle clock timeout detection */
+#define I2C_TIMEOUTR_TIMOUTEN     (1 << 15) /* Bit 15: Clock timeout enable */
+#define I2C_TIMEOUTR_B_SHIFT      (16)      /* Bits 16-27: Bus Timeout B */
+#define I2C_TIMEOUTR_B_MASK       (0x0fff << I2C_TIMEOUTR_B_SHIFT)
+#  define I2C_TIMEOUTR_B(n)       ((n) << I2C_TIMEOUTR_B_SHIFT)
+#define I2C_TIMEOUTR_TEXTEN       (1 << 31) /* Bits 31: Extended clock timeout enable */
+
+
+/* Fields unique to the Interrupt and Status register */
+
+#define I2C_ISR_TXE               (1 << 0)  /* Bit 0:  Transmit data register empty (transmitters) */
+#define I2C_ISR_TXIS              (1 << 1)  /* Bit 1:  Transmit interrupt status (transmitters) */
+#define I2C_ISR_RXNE              (1 << 2)  /* Bit 2:  Receive data register not empty (receivers) */
+#define I2C_ISR_TC                (1 << 6)  /* Bit 6:  Transfer Complete (master) */
+#define I2C_ISR_TCR               (1 << 7)  /* Bit 7:  Transfer Complete Reload */
+#define I2C_ISR_BUSY              (1 << 15) /* Bit 15: Bus busy */
+#define I2C_ISR_DIR               (1 << 16) /* Bit 16: Transfer direction (slave) */
+#define I2C_ISR_ADDCODE_SHIFT     (17)      /* Bits 17-23: Address match code (slave) */
+#define I2C_ISR_ADDCODE_MASK      (0x7f << I2C_ISR_ADDCODE_SHIFT)
+
+/* Interrupt and Status register and interrupt clear register */
+/* Common interrupt bits */
+
+#define I2C_INT_ADDR              (1 << 3)  /* Bit 3:  Address matched (slave) */
+#define I2C_INT_NACK              (1 << 4)  /* Bit 4:  Not Acknowledge received flag */
+#define I2C_INT_STOP              (1 << 5)  /* Bit 5:  Stop detection flag */
+#define I2C_INT_BERR              (1 << 8)  /* Bit 8:  Bus error */
+#define I2C_INT_ARLO              (1 << 9)  /* Bit 9:  Arbitration lost */
+#define I2C_INT_OVR               (1 << 10) /* Bit 10: Overrun/Underrun (slave) */
+#define I2C_INT_PECERR            (1 << 11) /* Bit 11: PEC Error in reception */
+#define I2C_INT_TIMEOUT           (1 << 12) /* Bit 12: Timeout or tLOW detection flag */
+#define I2C_INT_ALERT             (1 << 13) /* Bit 13: SMBus alert */
+
+#define I2C_ISR_ERRORMASK (I2C_INT_BERR | I2C_INT_ARLO | I2C_INT_OVR | I2C_INT_PECERR | I2C_INT_TIMEOUT)
+
+#define I2C_ICR_CLEARMASK (I2C_INT_ADDR | I2C_INT_NACK | I2C_INT_STOP | I2C_INT_BERR | I2C_INT_ARLO \
+                           | I2C_INT_OVR | I2C_INT_PECERR | I2C_INT_TIMEOUT | I2C_INT_ALERT)
+
+/* Packet error checking register */
+
+#define I2C_PECR_MASK             (0xff)
+
+/* Receive data register */
+
+#define I2C_RXDR_MASK             (0xff)
+
+/* Transmit data register */
+
+#define I2C_TXDR_MASK             (0xff)
+
+#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX77XX_I2C_H */
+
diff --git a/arch/arm/src/stm32f7/chip/stm32f74xx77xx_spi.h b/arch/arm/src/stm32f7/chip/stm32f74xx77xx_spi.h
new file mode 100644
index 00000000000..fe8c899c564
--- /dev/null
+++ b/arch/arm/src/stm32f7/chip/stm32f74xx77xx_spi.h
@@ -0,0 +1,258 @@
+/************************************************************************************
+ * arch/arm/src/stm32f7/chip/stm32f74xx77xx_spi.h
+ *stm32f74xx77xx
+ *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ *   Authors: Gregory Nutt <gnutt@nuttx.org>
+ *            David Sidrane <david_s5@nscdg.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX77XX_SPI_H
+#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX77XX_SPI_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#include "chip.h"
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Maximum allowed speed as per data sheet for all SPIs (both pclk1 and pclk2)*/
+
+#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
+#  define STM32_SPI_CLK_MAX       50000000UL
+#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
+#  define STM32_SPI_CLK_MAX       54000000UL
+#endif
+
+/* Register Offsets *****************************************************************/
+
+#define STM32_SPI_CR1_OFFSET      0x0000  /* SPI Control Register 1 (16-bit) */
+#define STM32_SPI_CR2_OFFSET      0x0004  /* SPI control register 2 (16-bit) */
+#define STM32_SPI_SR_OFFSET       0x0008  /* SPI status register (16-bit) */
+#define STM32_SPI_DR_OFFSET       0x000c  /* SPI data register (16-bit) */
+#define STM32_SPI_CRCPR_OFFSET    0x0010  /* SPI CRC polynomial register (16-bit) */
+#define STM32_SPI_RXCRCR_OFFSET   0x0014  /* SPI Rx CRC register (16-bit) */
+#define STM32_SPI_TXCRCR_OFFSET   0x0018  /* SPI Tx CRC register (16-bit) */
+#define STM32_SPI_I2SCFGR_OFFSET  0x001c  /* I2S configuration register */
+#define STM32_SPI_I2SPR_OFFSET    0x0020  /* I2S prescaler register */
+
+/* Register Addresses ***************************************************************/
+
+#if STM32F7_NSPI > 0
+#  define STM32_SPI1_CR1          (STM32_SPI1_BASE+STM32_SPI_CR1_OFFSET)
+#  define STM32_SPI1_CR2          (STM32_SPI1_BASE+STM32_SPI_CR2_OFFSET)
+#  define STM32_SPI1_SR           (STM32_SPI1_BASE+STM32_SPI_SR_OFFSET)
+#  define STM32_SPI1_DR           (STM32_SPI1_BASE+STM32_SPI_DR_OFFSET)
+#  define STM32_SPI1_CRCPR        (STM32_SPI1_BASE+STM32_SPI_CRCPR_OFFSET)
+#  define STM32_SPI1_RXCRCR       (STM32_SPI1_BASE+STM32_SPI_RXCRCR_OFFSET)
+#  define STM32_SPI1_TXCRCR       (STM32_SPI1_BASE+STM32_SPI_TXCRCR_OFFSET)
+#endif
+
+#if STM32F7_NSPI > 1
+#  define STM32_SPI2_CR1          (STM32_SPI2_BASE+STM32_SPI_CR1_OFFSET)
+#  define STM32_SPI2_CR2          (STM32_SPI2_BASE+STM32_SPI_CR2_OFFSET)
+#  define STM32_SPI2_SR           (STM32_SPI2_BASE+STM32_SPI_SR_OFFSET)
+#  define STM32_SPI2_DR           (STM32_SPI2_BASE+STM32_SPI_DR_OFFSET)
+#  define STM32_SPI2_CRCPR        (STM32_SPI2_BASE+STM32_SPI_CRCPR_OFFSET)
+#  define STM32_SPI2_RXCRCR       (STM32_SPI2_BASE+STM32_SPI_RXCRCR_OFFSET)
+#  define STM32_SPI2_TXCRCR       (STM32_SPI2_BASE+STM32_SPI_TXCRCR_OFFSET)
+#  define STM32_SPI2_I2SCFGR      (STM32_SPI2_BASE+STM32_SPI_I2SCFGR_OFFSET)
+#  define STM32_SPI2_I2SPR        (STM32_SPI2_BASE+STM32_SPI_I2SPR_OFFSET)
+#endif
+
+#if STM32F7_NSPI > 2
+#  define STM32_SPI3_CR1          (STM32_SPI3_BASE+STM32_SPI_CR1_OFFSET)
+#  define STM32_SPI3_CR2          (STM32_SPI3_BASE+STM32_SPI_CR2_OFFSET)
+#  define STM32_SPI3_SR           (STM32_SPI3_BASE+STM32_SPI_SR_OFFSET)
+#  define STM32_SPI3_DR           (STM32_SPI3_BASE+STM32_SPI_DR_OFFSET)
+#  define STM32_SPI3_CRCPR        (STM32_SPI3_BASE+STM32_SPI_CRCPR_OFFSET)
+#  define STM32_SPI3_RXCRCR       (STM32_SPI3_BASE+STM32_SPI_RXCRCR_OFFSET)
+#  define STM32_SPI3_TXCRCR       (STM32_SPI3_BASE+STM32_SPI_TXCRCR_OFFSET)
+#  define STM32_SPI3_I2SCFGR      (STM32_SPI3_BASE+STM32_SPI_I2SCFGR_OFFSET)
+#  define STM32_SPI3_I2SPR        (STM32_SPI3_BASE+STM32_SPI_I2SPR_OFFSET)
+#endif
+
+#if STM32F7_NSPI > 3
+#  define STM32_SPI4_CR1          (STM32_SPI4_BASE+STM32_SPI_CR1_OFFSET)
+#  define STM32_SPI4_CR2          (STM32_SPI4_BASE+STM32_SPI_CR2_OFFSET)
+#  define STM32_SPI4_SR           (STM32_SPI4_BASE+STM32_SPI_SR_OFFSET)
+#  define STM32_SPI4_DR           (STM32_SPI4_BASE+STM32_SPI_DR_OFFSET)
+#  define STM32_SPI4_CRCPR        (STM32_SPI4_BASE+STM32_SPI_CRCPR_OFFSET)
+#  define STM32_SPI4_RXCRCR       (STM32_SPI4_BASE+STM32_SPI_RXCRCR_OFFSET)
+#  define STM32_SPI4_TXCRCR       (STM32_SPI4_BASE+STM32_SPI_TXCRCR_OFFSET)
+#  define STM32_SPI4_I2SCFGR      (STM32_SPI4_BASE+STM32_SPI_I2SCFGR_OFFSET)
+#  define STM32_SPI4_I2SPR        (STM32_SPI4_BASE+STM32_SPI_I2SPR_OFFSET)
+#endif
+
+#if STM32F7_NSPI > 4
+#  define STM32_SPI5_CR1          (STM32_SPI5_BASE+STM32_SPI_CR1_OFFSET)
+#  define STM32_SPI5_CR2          (STM32_SPI5_BASE+STM32_SPI_CR2_OFFSET)
+#  define STM32_SPI5_SR           (STM32_SPI5_BASE+STM32_SPI_SR_OFFSET)
+#  define STM32_SPI5_DR           (STM32_SPI5_BASE+STM32_SPI_DR_OFFSET)
+#  define STM32_SPI5_CRCPR        (STM32_SPI5_BASE+STM32_SPI_CRCPR_OFFSET)
+#  define STM32_SPI5_RXCRCR       (STM32_SPI5_BASE+STM32_SPI_RXCRCR_OFFSET)
+#  define STM32_SPI5_TXCRCR       (STM32_SPI5_BASE+STM32_SPI_TXCRCR_OFFSET)
+#  define STM32_SPI5_I2SCFGR      (STM32_SPI5_BASE+STM32_SPI_I2SCFGR_OFFSET)
+#  define STM32_SPI5_I2SPR        (STM32_SPI5_BASE+STM32_SPI_I2SPR_OFFSET)
+#endif
+
+#if STM32F7_NSPI > 5
+#  define STM32_SPI6_CR1          (STM32_SPI6_BASE+STM32_SPI_CR1_OFFSET)
+#  define STM32_SPI6_CR2          (STM32_SPI6_BASE+STM32_SPI_CR2_OFFSET)
+#  define STM32_SPI6_SR           (STM32_SPI6_BASE+STM32_SPI_SR_OFFSET)
+#  define STM32_SPI6_DR           (STM32_SPI6_BASE+STM32_SPI_DR_OFFSET)
+#  define STM32_SPI6_CRCPR        (STM32_SPI6_BASE+STM32_SPI_CRCPR_OFFSET)
+#  define STM32_SPI6_RXCRCR       (STM32_SPI6_BASE+STM32_SPI_RXCRCR_OFFSET)
+#  define STM32_SPI6_TXCRCR       (STM32_SPI6_BASE+STM32_SPI_TXCRCR_OFFSET)
+#  define STM32_SPI6_I2SCFGR      (STM32_SPI6_BASE+STM32_SPI_I2SCFGR_OFFSET)
+#  define STM32_SPI6_I2SPR        (STM32_SPI6_BASE+STM32_SPI_I2SPR_OFFSET)
+#endif
+
+/* Register Bitfield Definitions ****************************************************/
+
+/* SPI Control Register 1 */
+
+#define SPI_CR1_CPHA              (1 << 0)  /* Bit 0: Clock Phase */
+#define SPI_CR1_CPOL              (1 << 1)  /* Bit 1: Clock Polarity */
+#define SPI_CR1_MSTR              (1 << 2)  /* Bit 2: Master Selection */
+#define SPI_CR1_BR_SHIFT          (3)       /* Bits 5:3 Baud Rate Control */
+#define SPI_CR1_BR_MASK           (7 << SPI_CR1_BR_SHIFT)
+#  define SPI_CR1_FPCLCKd2        (0 << SPI_CR1_BR_SHIFT) /* 000: fPCLK/2 */
+#  define SPI_CR1_FPCLCKd4        (1 << SPI_CR1_BR_SHIFT) /* 001: fPCLK/4 */
+#  define SPI_CR1_FPCLCKd8        (2 << SPI_CR1_BR_SHIFT) /* 010: fPCLK/8 */
+#  define SPI_CR1_FPCLCKd16       (3 << SPI_CR1_BR_SHIFT) /* 011: fPCLK/16 */
+#  define SPI_CR1_FPCLCKd32       (4 << SPI_CR1_BR_SHIFT) /* 100: fPCLK/32 */
+#  define SPI_CR1_FPCLCKd64       (5 << SPI_CR1_BR_SHIFT) /* 101: fPCLK/64 */
+#  define SPI_CR1_FPCLCKd128      (6 << SPI_CR1_BR_SHIFT) /* 110: fPCLK/128 */
+#  define SPI_CR1_FPCLCKd256      (7 << SPI_CR1_BR_SHIFT) /* 111: fPCLK/256 */
+#define SPI_CR1_SPE               (1 << 6)  /* Bit 6: SPI Enable */
+#define SPI_CR1_LSBFIRST          (1 << 7)  /* Bit 7: Frame Format */
+#define SPI_CR1_SSI               (1 << 8)  /* Bit 8: Internal slave select */
+#define SPI_CR1_SSM               (1 << 9)  /* Bit 9: Software slave management */
+#define SPI_CR1_RXONLY            (1 << 10) /* Bit 10: Receive only */
+#define SPI_CR1_CRCL              (1 << 11) /* Bit 11: CRC length */
+#define SPI_CR1_CRCNEXT           (1 << 12) /* Bit 12: Transmit CRC next */
+#define SPI_CR1_CRCEN             (1 << 13) /* Bit 13: Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE            (1 << 14) /* Bit 14: Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE          (1 << 15) /* Bit 15: Bidirectional data mode enable */
+
+/* SPI Control Register 2 */
+
+#define SPI_CR2_RXDMAEN           (1 << 0)  /* Bit 0: Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN           (1 << 1)  /* Bit 1: Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE              (1 << 2)  /* Bit 2: SS Output Enable */
+#define SPI_CR2_NSSP              (1 << 3)  /* Bit 3 NSSP: NSS pulse management */
+#define SPI_CR2_FRF               (1 << 4)  /* Bit 4: Frame format */
+#define SPI_CR2_ERRIE             (1 << 5)  /* Bit 5: Error interrupt enable */
+#define SPI_CR2_RXNEIE            (1 << 6)  /* Bit 6: RX buffer not empty interrupt enable */
+#define SPI_CR2_TXEIE             (1 << 7)  /* Bit 7: Tx buffer empty interrupt enable */
+#define SPI_CR2_DS_SHIFT          (8)       /* Bits 8-11:  Data size */
+#define SPI_CR2_DS_MASK           (0xf << SPI_CR2_DS_SHIFT)
+#  define SPI_CR2_DS_VAL(bits)    (((bits)-1) << SPI_CR2_DS_SHIFT)
+#  define SPI_CR2_DS_4BIT         SPI_CR2_DS_VAL(4)
+#  define SPI_CR2_DS_5BIT         SPI_CR2_DS_VAL(5)
+#  define SPI_CR2_DS_6BIT         SPI_CR2_DS_VAL(6)
+#  define SPI_CR2_DS_7BIT         SPI_CR2_DS_VAL(7)
+#  define SPI_CR2_DS_8BIT         SPI_CR2_DS_VAL(8)
+#  define SPI_CR2_DS_9BIT         SPI_CR2_DS_VAL(9)
+#  define SPI_CR2_DS_10BIT        SPI_CR2_DS_VAL(10)
+#  define SPI_CR2_DS_11BIT        SPI_CR2_DS_VAL(11)
+#  define SPI_CR2_DS_12BIT        SPI_CR2_DS_VAL(12)
+#  define SPI_CR2_DS_13BIT        SPI_CR2_DS_VAL(13)
+#  define SPI_CR2_DS_14BIT        SPI_CR2_DS_VAL(14)
+#  define SPI_CR2_DS_15BIT        SPI_CR2_DS_VAL(15)
+#  define SPI_CR2_DS_16BIT        SPI_CR2_DS_VAL(16)
+#define SPI_CR2_FRXTH             (1 << 12) /* Bit 12: FIFO reception threshold */
+#define SPI_CR2_LDMARX            (1 << 13) /* Bit 13: Last DMA transfer for receptione */
+#define SPI_CR2_LDMATX            (1 << 14) /* Bit 14: Last DMA transfer for transmission */
+
+/* SPI status register */
+
+#define SPI_SR_RXNE               (1 << 0)  /* Bit 0: Receive buffer not empty */
+#define SPI_SR_TXE                (1 << 1)  /* Bit 1: Transmit buffer empty */
+#define SPI_SR_CHSIDE             (1 << 2)  /* Bit 2: Channel side (i2s) */
+#define SPI_SR_UDR                (1 << 3)  /* Bit 3: Underrun flag (i2s) */
+#define SPI_SR_CRCERR             (1 << 4)  /* Bit 4: CRC error flag */
+#define SPI_SR_MODF               (1 << 5)  /* Bit 5: Mode fault */
+#define SPI_SR_OVR                (1 << 6)  /* Bit 6: Overrun flag */
+#define SPI_SR_BSY                (1 << 7)  /* Bit 7: Busy flag */
+#define SPI_SR_FRE                (1 << 8)  /* Bit 8: Frame format error */
+#define SPI_SR_FRLVL_SHIFT        (9)       /* Bits 9-10: FIFO reception level */
+#define SPI_SR_FRLVL_MASK         (3 << SPI_SR_FRLVL_SHIFT)
+#  define SPI_SR_FRLVL_EMPTY      (0 << SPI_SR_FRLVL_SHIFT) /* FIFO empty */
+#  define SPI_SR_FRLVL_QUARTER    (1 << SPI_SR_FRLVL_SHIFT) /* 1/4 FIFO */
+#  define SPI_SR_FRLVL_HALF       (2 << SPI_SR_FRLVL_SHIFT) /* 1/2 FIFO */
+#  define SPI_SR_FRLVL_FULL       (3 << SPI_SR_FRLVL_SHIFT) /* FIFO full */
+#define SPI_SR_FTLVL_SHIFT        (11)      /* Bits 11-12: FIFO transmission level */
+#define SPI_SR_FTLVL_MASK         (3 << SPI_SR_FTLVL_SHIFT)
+#  define SPI_SR_FTLVL_EMPTY      (0 << SPI_SR_FTLVL_SHIFT) /* FIFO empty */
+#  define SPI_SR_FTLVL_QUARTER    (1 << SPI_SR_FTLVL_SHIFT) /* 1/4 FIFO */
+#  define SPI_SR_FTLVL_HALF       (2 << SPI_SR_FTLVL_SHIFT) /* 1/2 FIFO */
+#  define SPI_SR_FTLVL_FULL       (3 << SPI_SR_FTLVL_SHIFT) /* FIFO full */
+
+/* I2S configuration register */
+
+#define SPI_I2SCFGR_CHLEN          (1 << 0)  /* Bit 0: Channel length (number of bits per audio channel) */
+#define SPI_I2SCFGR_DATLEN_SHIFT   (1)       /* Bit 1-2: Data length to be transferred */
+#define SPI_I2SCFGR_DATLEN_MASK    (3 << SPI_I2SCFGR_DATLEN_SHIFT)
+#  define SPI_I2SCFGR_DATLEN_16BIT (0 << SPI_I2SCFGR_DATLEN_SHIFT) /* 00: 16-bit data length */
+#  define SPI_I2SCFGR_DATLEN_8BIT  (1 << SPI_I2SCFGR_DATLEN_SHIFT) /* 01: 24-bit data length */
+#  define SPI_I2SCFGR_DATLEN_32BIT (2 << SPI_I2SCFGR_DATLEN_SHIFT) /* 10: 32-bit data length */
+#define SPI_I2SCFGR_CKPOL          (1 << 3)  /* Bit 3: Steady state clock polarity */
+#define SPI_I2SCFGR_I2SSTD_SHIFT   (4)       /* Bit 4-5: I2S standard selection */
+#define SPI_I2SCFGR_I2SSTD_MASK    (3 << SPI_I2SCFGR_I2SSTD_SHIFT)
+#  define SPI_I2SCFGR_I2SSTD_PHILLIPS (0 << SPI_I2SCFGR_I2SSTD_SHIFT) /* 00: I2S Phillips standard. */
+#  define SPI_I2SCFGR_I2SSTD_MSB      (1 << SPI_I2SCFGR_I2SSTD_SHIFT) /* 01: MSB justified standard (left justified) */
+#  define SPI_I2SCFGR_I2SSTD_LSB      (2 << SPI_I2SCFGR_I2SSTD_SHIFT) /* 10: LSB justified standard (right justified) */
+#  define SPI_I2SCFGR_I2SSTD_PCM      (3 << SPI_I2SCFGR_I2SSTD_SHIFT) /* 11: PCM standard */
+#define SPI_I2SCFGR_PCMSYNC        (1 << 7)  /* Bit 7: PCM frame synchronization */
+#define SPI_I2SCFGR_I2SCFG_SHIFT   (8)       /* Bit 8-9: I2S configuration mode */
+#define SPI_I2SCFGR_I2SCFG_MASK    (3 << SPI_I2SCFGR_I2SCFG_SHIFT)
+#  define SPI_I2SCFGR_I2SCFG_STX   (0 << SPI_I2SCFGR_I2SCFG_SHIFT) /* 00: Slave - transmit */
+#  define SPI_I2SCFGR_I2SCFG_SRX   (1 << SPI_I2SCFGR_I2SCFG_SHIFT) /* 01: Slave - receive */
+#  define SPI_I2SCFGR_I2SCFG_MTX   (2 << SPI_I2SCFGR_I2SCFG_SHIFT) /* 10: Master - transmit */
+#  define SPI_I2SCFGR_I2SCFG_MRX   (3 << SPI_I2SCFGR_I2SCFG_SHIFT) /* 11: Master - receive */
+#define SPI_I2SCFGR_I2SE           (1 << 10) /* Bit 10: I2S Enable */
+#define SPI_I2SCFGR_I2SMOD         (1 << 11) /* Bit 11: I2S mode selection */
+#define SPI_I2SCFGR_ASTRTEN        (1 << 12) /* Bit 12: Asynchronous start enable */
+
+/* I2S prescaler register */
+
+#define SPI_I2SPR_I2SDIV_SHIFT    (0)       /* Bit 0-7: I2S Linear prescaler */
+#define SPI_I2SPR_I2SDIV_MASK     (0xff << SPI_I2SPR_I2SDIV_SHIFT)
+#define SPI_I2SPR_ODD             (1 << 8)  /* Bit 8: Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE           (1 << 9)  /* Bit 9: Master clock output enable */
+
+#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX77XX_SPI_H */
diff --git a/arch/arm/src/stm32f7/chip/stm32f74xx77xx_uart.h b/arch/arm/src/stm32f7/chip/stm32f74xx77xx_uart.h
index e33030cd8da..4d109bead0d 100644
--- a/arch/arm/src/stm32f7/chip/stm32f74xx77xx_uart.h
+++ b/arch/arm/src/stm32f7/chip/stm32f74xx77xx_uart.h
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_STC_STM32F7_CHIP_STM32F74XX77XX_UART_H
-#define __ARCH_ARM_STC_STM32F7_CHIP_STM32F74XX77XX_UART_H
+#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX77XX_UART_H
+#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX77XX_UART_H
 
 /************************************************************************************
  * Included Files
@@ -368,4 +368,4 @@
 #define USART_TDR_MASK            (0x1ff << USART_TDR_SHIFT)
 
 #endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */
-#endif /* __ARCH_ARM_STC_STM32F7_CHIP_STM32F74XX77XX_UART_H */
+#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX77XX_UART_H */
diff --git a/arch/arm/src/stm32f7/chip/stm32f76xx77xx_memorymap.h b/arch/arm/src/stm32f7/chip/stm32f76xx77xx_memorymap.h
index 204311e0003..fd1a41f36de 100644
--- a/arch/arm/src/stm32f7/chip/stm32f76xx77xx_memorymap.h
+++ b/arch/arm/src/stm32f7/chip/stm32f76xx77xx_memorymap.h
@@ -82,6 +82,7 @@
 
 
 #define STM32_SYSMEM_AXIM    0x1ff00000     /* 0x1ff00000-0x1ff0edbf: System memory (AXIM) */
+#define STM32_SYSMEM_UID     0x1ff0f420     /* The 96-bit unique device identifier */
 #define STM32_OTP_ICTM       0x0010f000     /* 0x0010f000-0x0010edbf: OTP (ITCM) */
 #define STM32_OTP_AXIM       0x1ff0f000     /* 0x1ff00000-0x1ff0f41f: OTP (AXIM) */
 
@@ -145,6 +146,10 @@
 #define STM32_USART6_BASE    0x40011400     /* 0x40011400-0x400117ff: USART6 */
 #define STM32_SDMMC2_BASE    0x40011c00     /* 0x40011c00-0x40011fff: SDMMC2 */
 #define STM32_ADC_BASE       0x40012000     /* 0x40012000-0x400123ff: ADC1 - ADC2 - ADC3 */
+#  define STM32_ADC1_BASE    0x40012000     /*                        ADC1 */
+#  define STM32_ADC2_BASE    0x40012100     /*                        ADC2 */
+#  define STM32_ADC3_BASE    0x40012200     /*                        ADC3 */
+#  define STM32_ADCCMN_BASE  0x40012300     /*                        Common */
 #define STM32_SDMMC1_BASE    0x40012c00     /* 0x40012c00-0x40012fff: SDMMC1 */
 #define STM32_SPI1_BASE      0x40013000     /* 0x40013000-0x400133ff: SPI1 */
 #define STM32_SPI4_BASE      0x40013400     /* 0x40013400-0x400137ff: SPI4 */
@@ -210,5 +215,7 @@
  * address range
  */
 
-#endif /* CONFIG_STM32F7_STM32F76XX || CONFIG_STM32F7_STM32F77XX */
-#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F76XXX77XXX_MEMORYMAP_H */
+#define STM32_DEBUGMCU_BASE 0xe0042000
+ 
+#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */
+#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XXX75XXX_MEMORYMAP_H */
diff --git a/arch/arm/src/stm32f7/chip/stm32f76xx77xx_rcc.h b/arch/arm/src/stm32f7/chip/stm32f76xx77xx_rcc.h
index 23c8b2db0b2..a63cc1911a4 100644
--- a/arch/arm/src/stm32f7/chip/stm32f76xx77xx_rcc.h
+++ b/arch/arm/src/stm32f7/chip/stm32f76xx77xx_rcc.h
@@ -638,7 +638,7 @@
 #define RCC_DCKCFGR1_SAI2SEL_SHIFT   (22)      /* Bits 22-23: SAI 2 clock source selection */
 #define RCC_DCKCFGR1_SAI2SEL_MASK    (0x3 << RCC_DCKCFGR1_SAI2SEL_SHIFT)
 #  define RCC_DCKCFGR1_SAI2SEL(n)    ((n) << RCC_DCKCFGR1_SAI2SEL_SHIFT)
-#define RCC_DCKCFGR1_TIMPRE          (1 << 24) /* Bit 24: Timer clock prescaler selection */
+#define RCC_DCKCFGR1_TIMPRESEL       (1 << 24) /* Bit 24: Timer clock prescaler selection */
 #define RCC_DCKCFGR1_DFSDM1SEL       (1 << 25) /* Bit 25: DFSDM1 clock prescaler selection */
 #define RCC_DCKCFGR1_ADFSDM1SEL      (1 << 26) /* Bit 26: DFSDM1 AUDIO clock prescaler selection */
 
diff --git a/arch/arm/src/stm32f7/chip/stm32f76xx77xx_tim.h b/arch/arm/src/stm32f7/chip/stm32f76xx77xx_tim.h
new file mode 100644
index 00000000000..bb6a657aa84
--- /dev/null
+++ b/arch/arm/src/stm32f7/chip/stm32f76xx77xx_tim.h
@@ -0,0 +1,1147 @@
+/****************************************************************************************************
+ * arch/arm/src/stm32f7/chip/stm32f76xx77xx_tim.h
+ *
+ *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ *   Authors: Gregory Nutt <gnutt@nuttx.org>
+ *            David Sidrane <david_s5@nscdg.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F76XX77XX_TIM_H
+#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F76XX77XX_TIM_H
+
+/****************************************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************************************/
+
+/* Register Offsets *********************************************************************************/
+
+/* Basic Timers - TIM6 and TIM7 */
+
+#define STM32_BTIM_CR1_OFFSET     0x0000  /* Control register 1 (16-bit) */
+#define STM32_BTIM_CR2_OFFSET     0x0004  /* Control register 2 (16-bit) */
+#define STM32_BTIM_DIER_OFFSET    0x000c  /* DMA/Interrupt enable register (16-bit) */
+#define STM32_BTIM_SR_OFFSET      0x0010  /* Status register (16-bit) */
+#define STM32_BTIM_EGR_OFFSET     0x0014  /* Event generation register (16-bit) */
+#define STM32_BTIM_CNT_OFFSET     0x0024  /* Counter (16-bit) */
+#define STM32_BTIM_PSC_OFFSET     0x0028  /* Prescaler (16-bit) */
+#define STM32_BTIM_ARR_OFFSET     0x002c  /* Auto-reload register (16-bit) */
+
+/* 16-/32-bit General Timers with DMA: TIM2, TM3, TIM4, and TIM5
+ * 16-bit General Timers without DMA: TIM9, TIM10, TIM11, TIM12, TIM13, and TIM14
+ * timers are 16-bit except for TIM2 and 5 are 32-bit
+ * timers TIM9 and 12 are different then  TIM10, TIM11, TIM13, and TIM14
+ */
+
+#define STM32_GTIM_CR1_OFFSET      0x0000  /* Control register 1 (16-bit) */
+#define STM32_GTIM_CR2_OFFSET      0x0004  /* Control register 2 (16-bit, TIM2, 5 only) */
+#define STM32_GTIM_SMCR_OFFSET     0x0008  /* Slave mode control register (32-bit, TIM2, 5, 9, 12 only) */
+#define STM32_GTIM_DIER_OFFSET     0x000c  /* DMA/Interrupt enable register (16-bit) */
+#define STM32_GTIM_SR_OFFSET       0x0010  /* Status register (16-bit) */
+#define STM32_GTIM_EGR_OFFSET      0x0014  /* Event generation register (16-bit) */
+#define STM32_GTIM_CCMR1_OFFSET    0x0018  /* Capture/compare mode register 1 (32-bit) */
+#define STM32_GTIM_CCMR2_OFFSET    0x001c  /* Capture/compare mode register 2 (32-bit on TIM2,5 only) */
+#define STM32_GTIM_CCER_OFFSET     0x0020  /* Capture/compare enable register (16-bit) */
+#define STM32_GTIM_CNT_OFFSET      0x0024  /* Counter (16 bit and 32-bit on TIM2, 5 only) */
+#define STM32_GTIM_PSC_OFFSET      0x0028  /* Prescaler (16-bit) */
+#define STM32_GTIM_ARR_OFFSET      0x002c  /* Auto-reload register (16 bit and 32-bit on TIM2, 5 only) */
+#define STM32_GTIM_CCR1_OFFSET     0x0034  /* Capture/compare register 1 (16-bit on all TIMx and 32-bit on TIM2,5 only) */
+#define STM32_GTIM_CCR2_OFFSET     0x0038  /* Capture/compare register 2 (16-bit TIM 3-4, 9, 12 and 32-bit on TIM2,5 only) */
+#define STM32_GTIM_CCR3_OFFSET     0x003c  /* Capture/compare register 3 (16-bit TIM 3-4 and 32-bit on TIM2,5 only) */
+#define STM32_GTIM_CCR4_OFFSET     0x0040  /* Capture/compare register 4 (16-bit TIM 3-4 and 32-bit on TIM2,5 only) */
+#define STM32_GTIM_DCR_OFFSET      0x0048  /* DMA control register (16-bit, TIM2-5 only) */
+#define STM32_GTIM_DMAR_OFFSET     0x004c  /* DMA address for burst mode (16-bit, TIM2-5 only) */
+#define STM32_GTIM_OR_OFFSET       0x0050  /* Timer 2/5/11 option register */
+
+/* Advanced Timers - TIM1 and TIM8 */
+
+#define STM32_ATIM_CR1_OFFSET      0x0000  /* Control register 1 (16-bit) */
+#define STM32_ATIM_CR2_OFFSET      0x0004  /* Control register 2 (32-bit*) */
+#define STM32_ATIM_SMCR_OFFSET     0x0008  /* Slave mode control register (32 -bit) */
+#define STM32_ATIM_DIER_OFFSET     0x000c  /* DMA/Interrupt enable register (16-bit) */
+#define STM32_ATIM_SR_OFFSET       0x0010  /* Status register (32-bit*) */
+#define STM32_ATIM_EGR_OFFSET      0x0014  /* Event generation register (16-bit) */
+#define STM32_ATIM_CCMR1_OFFSET    0x0018  /* Capture/compare mode register 1 (32-bit*) */
+#define STM32_ATIM_CCMR2_OFFSET    0x001c  /* Capture/compare mode register 2 (32-bit*) */
+#define STM32_ATIM_CCER_OFFSET     0x0020  /* Capture/compare enable register (32-bit*) */
+#define STM32_ATIM_CNT_OFFSET      0x0024  /* Counter (32-bit cnt in lower 16 bit ) */
+#define STM32_ATIM_PSC_OFFSET      0x0028  /* Prescaler (16-bit) */
+#define STM32_ATIM_ARR_OFFSET      0x002c  /* Auto-reload register (16-bit) */
+#define STM32_ATIM_RCR_OFFSET      0x0030  /* Repetition counter register (16-bit) */
+#define STM32_ATIM_CCR1_OFFSET     0x0034  /* Capture/compare register 1 (16-bit) */
+#define STM32_ATIM_CCR2_OFFSET     0x0038  /* Capture/compare register 2 (16-bit) */
+#define STM32_ATIM_CCR3_OFFSET     0x003c  /* Capture/compare register 3 (16-bit) */
+#define STM32_ATIM_CCR4_OFFSET     0x0040  /* Capture/compare register 4 (16-bit) */
+#define STM32_ATIM_BDTR_OFFSET     0x0044  /* Break and dead-time register (32-bit*) */
+#define STM32_ATIM_DCR_OFFSET      0x0048  /* DMA control register (16-bit) */
+#define STM32_ATIM_DMAR_OFFSET     0x004c  /* DMA address for burst mode (16-bit) */
+#define STM32_ATIM_CCMR3_OFFSET    0x0054  /* Capture/compare mode register 3 (32-bit) */
+#define STM32_ATIM_CCR5_OFFSET     0x0058  /* Capture/compare register 5 (32-bit) */
+#define STM32_ATIM_CCR6_OFFSET     0x005c  /* Capture/compare register 6 (16-bit) */
+#define STM32_ATIM_AF1_OFFSET      0x0060  /* Alternate function option register 1 (16-bit) */
+#define STM32_ATIM_AF2_OFFSET      0x0064  /* Alternate function option register 2 (16-bit) */
+
+/* Register Addresses *******************************************************************************/
+
+/* Advanced Timers - TIM1 and TIM8 */
+
+#if STM32F7_NATIM > 0
+#  define STM32_TIM1_CR1          (STM32_TIM1_BASE+STM32_ATIM_CR1_OFFSET)
+#  define STM32_TIM1_CR2          (STM32_TIM1_BASE+STM32_ATIM_CR2_OFFSET)
+#  define STM32_TIM1_SMCR         (STM32_TIM1_BASE+STM32_ATIM_SMCR_OFFSET)
+#  define STM32_TIM1_DIER         (STM32_TIM1_BASE+STM32_ATIM_DIER_OFFSET)
+#  define STM32_TIM1_SR           (STM32_TIM1_BASE+STM32_ATIM_SR_OFFSET)
+#  define STM32_TIM1_EGR          (STM32_TIM1_BASE+STM32_ATIM_EGR_OFFSET)
+#  define STM32_TIM1_CCMR1        (STM32_TIM1_BASE+STM32_ATIM_CCMR1_OFFSET)
+#  define STM32_TIM1_CCMR2        (STM32_TIM1_BASE+STM32_ATIM_CCMR2_OFFSET)
+#  define STM32_TIM1_CCER         (STM32_TIM1_BASE+STM32_ATIM_CCER_OFFSET)
+#  define STM32_TIM1_CNT          (STM32_TIM1_BASE+STM32_ATIM_CNT_OFFSET)
+#  define STM32_TIM1_PSC          (STM32_TIM1_BASE+STM32_ATIM_PSC_OFFSET)
+#  define STM32_TIM1_ARR          (STM32_TIM1_BASE+STM32_ATIM_ARR_OFFSET)
+#  define STM32_TIM1_RCR          (STM32_TIM1_BASE+STM32_ATIM_RCR_OFFSET)
+#  define STM32_TIM1_CCR1         (STM32_TIM1_BASE+STM32_ATIM_CCR1_OFFSET)
+#  define STM32_TIM1_CCR2         (STM32_TIM1_BASE+STM32_ATIM_CCR2_OFFSET)
+#  define STM32_TIM1_CCR3         (STM32_TIM1_BASE+STM32_ATIM_CCR3_OFFSET)
+#  define STM32_TIM1_CCR4         (STM32_TIM1_BASE+STM32_ATIM_CCR4_OFFSET)
+#  define STM32_TIM1_BDTR         (STM32_TIM1_BASE+STM32_ATIM_BDTR_OFFSET)
+#  define STM32_TIM1_DCR          (STM32_TIM1_BASE+STM32_ATIM_DCR_OFFSET)
+#  define STM32_TIM1_DMAR         (STM32_TIM1_BASE+STM32_ATIM_DMAR_OFFSET)
+#  define STM32_TIM1_CCMR3        (STM32_TIM1_BASE+STM32_ATIM_CCMR3_OFFSET)
+#  define STM32_TIM1_CCR5         (STM32_TIM1_BASE+STM32_ATIM_CCR5_OFFSET)
+#  define STM32_TIM1_CCR6         (STM32_TIM1_BASE+STM32_ATIM_CCR6_OFFSET)
+#  define STM32_TIM1_AF1          (STM32_TIM1_BASE+STM32_ATIM_AF1_OFFSET)
+#  define STM32_TIM1_AF2          (STM32_TIM1_BASE+STM32_ATIM_AF2_OFFSET)
+#endif
+
+#if STM32F7_NATIM > 1
+#  define STM32_TIM8_CR1          (STM32_TIM8_BASE+STM32_ATIM_CR1_OFFSET)
+#  define STM32_TIM8_CR2          (STM32_TIM8_BASE+STM32_ATIM_CR2_OFFSET)
+#  define STM32_TIM8_SMCR         (STM32_TIM8_BASE+STM32_ATIM_SMCR_OFFSET)
+#  define STM32_TIM8_DIER         (STM32_TIM8_BASE+STM32_ATIM_DIER_OFFSET)
+#  define STM32_TIM8_SR           (STM32_TIM8_BASE+STM32_ATIM_SR_OFFSET)
+#  define STM32_TIM8_EGR          (STM32_TIM8_BASE+STM32_ATIM_EGR_OFFSET)
+#  define STM32_TIM8_CCMR1        (STM32_TIM8_BASE+STM32_ATIM_CCMR1_OFFSET)
+#  define STM32_TIM8_CCMR2        (STM32_TIM8_BASE+STM32_ATIM_CCMR2_OFFSET)
+#  define STM32_TIM8_CCER         (STM32_TIM8_BASE+STM32_ATIM_CCER_OFFSET)
+#  define STM32_TIM8_CNT          (STM32_TIM8_BASE+STM32_ATIM_CNT_OFFSET)
+#  define STM32_TIM8_PSC          (STM32_TIM8_BASE+STM32_ATIM_PSC_OFFSET)
+#  define STM32_TIM8_ARR          (STM32_TIM8_BASE+STM32_ATIM_ARR_OFFSET)
+#  define STM32_TIM8_RCR          (STM32_TIM8_BASE+STM32_ATIM_RCR_OFFSET)
+#  define STM32_TIM8_CCR1         (STM32_TIM8_BASE+STM32_ATIM_CCR1_OFFSET)
+#  define STM32_TIM8_CCR2         (STM32_TIM8_BASE+STM32_ATIM_CCR2_OFFSET)
+#  define STM32_TIM8_CCR3         (STM32_TIM8_BASE+STM32_ATIM_CCR3_OFFSET)
+#  define STM32_TIM8_CCR4         (STM32_TIM8_BASE+STM32_ATIM_CCR4_OFFSET)
+#  define STM32_TIM8_BDTR         (STM32_TIM8_BASE+STM32_ATIM_BDTR_OFFSET)
+#  define STM32_TIM8_DCR          (STM32_TIM8_BASE+STM32_ATIM_DCR_OFFSET)
+#  define STM32_TIM8_DMAR         (STM32_TIM8_BASE+STM32_ATIM_DMAR_OFFSET)
+#  define STM32_TIM8_CCMR3        (STM32_TIM8_BASE+STM32_ATIM_CCMR3_OFFSET)
+#  define STM32_TIM8_CCR5         (STM32_TIM8_BASE+STM32_ATIM_CCR5_OFFSET)
+#  define STM32_TIM8_CCR6         (STM32_TIM8_BASE+STM32_ATIM_CCR6_OFFSET)
+#  define STM32_TIM8_AF1          (STM32_TIM8_BASE+STM32_ATIM_AF1_OFFSET)
+#  define STM32_TIM8_AF2          (STM32_TIM8_BASE+STM32_ATIM_AF2_OFFSET)
+#endif
+
+/* 16-/32-bit General Timers - TIM2, TIM3, TIM4, and TIM5 with DMA.
+ * All timers are 16-bit except for TIM2 and 5 are 32-bit
+ */
+
+#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 0
+#  define STM32_TIM2_CR1          (STM32_TIM2_BASE+STM32_GTIM_CR1_OFFSET)
+#  define STM32_TIM2_CR2          (STM32_TIM2_BASE+STM32_GTIM_CR2_OFFSET)
+#  define STM32_TIM2_SMCR         (STM32_TIM2_BASE+STM32_GTIM_SMCR_OFFSET)
+#  define STM32_TIM2_DIER         (STM32_TIM2_BASE+STM32_GTIM_DIER_OFFSET)
+#  define STM32_TIM2_SR           (STM32_TIM2_BASE+STM32_GTIM_SR_OFFSET)
+#  define STM32_TIM2_EGR          (STM32_TIM2_BASE+STM32_GTIM_EGR_OFFSET)
+#  define STM32_TIM2_CCMR1        (STM32_TIM2_BASE+STM32_GTIM_CCMR1_OFFSET)
+#  define STM32_TIM2_CCMR2        (STM32_TIM2_BASE+STM32_GTIM_CCMR2_OFFSET)
+#  define STM32_TIM2_CCER         (STM32_TIM2_BASE+STM32_GTIM_CCER_OFFSET)
+#  define STM32_TIM2_CNT          (STM32_TIM2_BASE+STM32_GTIM_CNT_OFFSET)
+#  define STM32_TIM2_PSC          (STM32_TIM2_BASE+STM32_GTIM_PSC_OFFSET)
+#  define STM32_TIM2_ARR          (STM32_TIM2_BASE+STM32_GTIM_ARR_OFFSET)
+#  define STM32_TIM2_CCR1         (STM32_TIM2_BASE+STM32_GTIM_CCR1_OFFSET)
+#  define STM32_TIM2_CCR2         (STM32_TIM2_BASE+STM32_GTIM_CCR2_OFFSET)
+#  define STM32_TIM2_CCR3         (STM32_TIM2_BASE+STM32_GTIM_CCR3_OFFSET)
+#  define STM32_TIM2_CCR4         (STM32_TIM2_BASE+STM32_GTIM_CCR4_OFFSET)
+#  define STM32_TIM2_DCR          (STM32_TIM2_BASE+STM32_GTIM_DCR_OFFSET)
+#  define STM32_TIM2_DMAR         (STM32_TIM2_BASE+STM32_GTIM_DMAR_OFFSET)
+#  define STM32_TIM2_OR           (STM32_TIM2_BASE+STM32_GTIM_OR_OFFSET)
+#endif
+
+#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 1
+#  define STM32_TIM3_CR1          (STM32_TIM3_BASE+STM32_GTIM_CR1_OFFSET)
+#  define STM32_TIM3_CR2          (STM32_TIM3_BASE+STM32_GTIM_CR2_OFFSET)
+#  define STM32_TIM3_SMCR         (STM32_TIM3_BASE+STM32_GTIM_SMCR_OFFSET)
+#  define STM32_TIM3_DIER         (STM32_TIM3_BASE+STM32_GTIM_DIER_OFFSET)
+#  define STM32_TIM3_SR           (STM32_TIM3_BASE+STM32_GTIM_SR_OFFSET)
+#  define STM32_TIM3_EGR          (STM32_TIM3_BASE+STM32_GTIM_EGR_OFFSET)
+#  define STM32_TIM3_CCMR1        (STM32_TIM3_BASE+STM32_GTIM_CCMR1_OFFSET)
+#  define STM32_TIM3_CCMR2        (STM32_TIM3_BASE+STM32_GTIM_CCMR2_OFFSET)
+#  define STM32_TIM3_CCER         (STM32_TIM3_BASE+STM32_GTIM_CCER_OFFSET)
+#  define STM32_TIM3_CNT          (STM32_TIM3_BASE+STM32_GTIM_CNT_OFFSET)
+#  define STM32_TIM3_PSC          (STM32_TIM3_BASE+STM32_GTIM_PSC_OFFSET)
+#  define STM32_TIM3_ARR          (STM32_TIM3_BASE+STM32_GTIM_ARR_OFFSET)
+#  define STM32_TIM3_CCR1         (STM32_TIM3_BASE+STM32_GTIM_CCR1_OFFSET)
+#  define STM32_TIM3_CCR2         (STM32_TIM3_BASE+STM32_GTIM_CCR2_OFFSET)
+#  define STM32_TIM3_CCR3         (STM32_TIM3_BASE+STM32_GTIM_CCR3_OFFSET)
+#  define STM32_TIM3_CCR4         (STM32_TIM3_BASE+STM32_GTIM_CCR4_OFFSET)
+#  define STM32_TIM3_DCR          (STM32_TIM3_BASE+STM32_GTIM_DCR_OFFSET)
+#  define STM32_TIM3_DMAR         (STM32_TIM3_BASE+STM32_GTIM_DMAR_OFFSET)
+#endif
+
+#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 2
+#  define STM32_TIM4_CR1          (STM32_TIM4_BASE+STM32_GTIM_CR1_OFFSET)
+#  define STM32_TIM4_CR2          (STM32_TIM4_BASE+STM32_GTIM_CR2_OFFSET)
+#  define STM32_TIM4_SMCR         (STM32_TIM4_BASE+STM32_GTIM_SMCR_OFFSET)
+#  define STM32_TIM4_DIER         (STM32_TIM4_BASE+STM32_GTIM_DIER_OFFSET)
+#  define STM32_TIM4_SR           (STM32_TIM4_BASE+STM32_GTIM_SR_OFFSET)
+#  define STM32_TIM4_EGR          (STM32_TIM4_BASE+STM32_GTIM_EGR_OFFSET)
+#  define STM32_TIM4_CCMR1        (STM32_TIM4_BASE+STM32_GTIM_CCMR1_OFFSET)
+#  define STM32_TIM4_CCMR2        (STM32_TIM4_BASE+STM32_GTIM_CCMR2_OFFSET)
+#  define STM32_TIM4_CCER         (STM32_TIM4_BASE+STM32_GTIM_CCER_OFFSET)
+#  define STM32_TIM4_CNT          (STM32_TIM4_BASE+STM32_GTIM_CNT_OFFSET)
+#  define STM32_TIM4_PSC          (STM32_TIM4_BASE+STM32_GTIM_PSC_OFFSET)
+#  define STM32_TIM4_ARR          (STM32_TIM4_BASE+STM32_GTIM_ARR_OFFSET)
+#  define STM32_TIM4_CCR1         (STM32_TIM4_BASE+STM32_GTIM_CCR1_OFFSET)
+#  define STM32_TIM4_CCR2         (STM32_TIM4_BASE+STM32_GTIM_CCR2_OFFSET)
+#  define STM32_TIM4_CCR3         (STM32_TIM4_BASE+STM32_GTIM_CCR3_OFFSET)
+#  define STM32_TIM4_CCR4         (STM32_TIM4_BASE+STM32_GTIM_CCR4_OFFSET)
+#  define STM32_TIM4_DCR          (STM32_TIM4_BASE+STM32_GTIM_DCR_OFFSET)
+#  define STM32_TIM4_DMAR         (STM32_TIM4_BASE+STM32_GTIM_DMAR_OFFSET)
+#endif
+
+#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 3
+#  define STM32_TIM5_CR1          (STM32_TIM5_BASE+STM32_GTIM_CR1_OFFSET)
+#  define STM32_TIM5_CR2          (STM32_TIM5_BASE+STM32_GTIM_CR2_OFFSET)
+#  define STM32_TIM5_SMCR         (STM32_TIM5_BASE+STM32_GTIM_SMCR_OFFSET)
+#  define STM32_TIM5_DIER         (STM32_TIM5_BASE+STM32_GTIM_DIER_OFFSET)
+#  define STM32_TIM5_SR           (STM32_TIM5_BASE+STM32_GTIM_SR_OFFSET)
+#  define STM32_TIM5_EGR          (STM32_TIM5_BASE+STM32_GTIM_EGR_OFFSET)
+#  define STM32_TIM5_CCMR1        (STM32_TIM5_BASE+STM32_GTIM_CCMR1_OFFSET)
+#  define STM32_TIM5_CCMR2        (STM32_TIM5_BASE+STM32_GTIM_CCMR2_OFFSET)
+#  define STM32_TIM5_CCER         (STM32_TIM5_BASE+STM32_GTIM_CCER_OFFSET)
+#  define STM32_TIM5_CNT          (STM32_TIM5_BASE+STM32_GTIM_CNT_OFFSET)
+#  define STM32_TIM5_PSC          (STM32_TIM5_BASE+STM32_GTIM_PSC_OFFSET)
+#  define STM32_TIM5_ARR          (STM32_TIM5_BASE+STM32_GTIM_ARR_OFFSET)
+#  define STM32_TIM5_CCR1         (STM32_TIM5_BASE+STM32_GTIM_CCR1_OFFSET)
+#  define STM32_TIM5_CCR2         (STM32_TIM5_BASE+STM32_GTIM_CCR2_OFFSET)
+#  define STM32_TIM5_CCR3         (STM32_TIM5_BASE+STM32_GTIM_CCR3_OFFSET)
+#  define STM32_TIM5_CCR4         (STM32_TIM5_BASE+STM32_GTIM_CCR4_OFFSET)
+#  define STM32_TIM5_DCR          (STM32_TIM5_BASE+STM32_GTIM_DCR_OFFSET)
+#  define STM32_TIM5_DMAR         (STM32_TIM5_BASE+STM32_GTIM_DMAR_OFFSET)
+#  define STM32_TIM5_OR           (STM32_TIM5_BASE+STM32_GTIM_OR_OFFSET)
+#endif
+
+
+/* 16-bit General Timers - TIM9-14 without DMA.  Note that (1) these timers
+ * support only a subset of the general timer registers are supported, and
+ * (2) TIM9 and TIM12 differ from the others.
+ */
+
+#if STM32F7_NGTIMNDMA > 0
+#  define STM32_TIM9_CR1          (STM32_TIM9_BASE+STM32_GTIM_CR1_OFFSET)
+#  define STM32_TIM9_CR2          (STM32_TIM9_BASE+STM32_GTIM_CR2_OFFSET)
+#  define STM32_TIM9_DIER         (STM32_TIM9_BASE+STM32_GTIM_DIER_OFFSET)
+#  define STM32_TIM9_SR           (STM32_TIM9_BASE+STM32_GTIM_SR_OFFSET)
+#  define STM32_TIM9_EGR          (STM32_TIM9_BASE+STM32_GTIM_EGR_OFFSET)
+#  define STM32_TIM9_CCMR1        (STM32_TIM9_BASE+STM32_GTIM_CCMR1_OFFSET)
+#  define STM32_TIM9_CCER         (STM32_TIM9_BASE+STM32_GTIM_CCER_OFFSET)
+#  define STM32_TIM9_CNT          (STM32_TIM9_BASE+STM32_GTIM_CNT_OFFSET)
+#  define STM32_TIM9_PSC          (STM32_TIM9_BASE+STM32_GTIM_PSC_OFFSET)
+#  define STM32_TIM9_ARR          (STM32_TIM9_BASE+STM32_GTIM_ARR_OFFSET)
+#  define STM32_TIM9_CCR1         (STM32_TIM9_BASE+STM32_GTIM_CCR1_OFFSET)
+#  define STM32_TIM9_CCR2         (STM32_TIM9_BASE+STM32_GTIM_CCR2_OFFSET)
+#endif
+
+#if STM32F7_NGTIMNDMA > 1
+#  define STM32_TIM10_CR1         (STM32_TIM10_BASE+STM32_GTIM_CR1_OFFSET)
+#  define STM32_TIM10_DIER        (STM32_TIM10_BASE+STM32_GTIM_DIER_OFFSET)
+#  define STM32_TIM10_SR          (STM32_TIM10_BASE+STM32_GTIM_SR_OFFSET)
+#  define STM32_TIM10_EGR         (STM32_TIM10_BASE+STM32_GTIM_EGR_OFFSET)
+#  define STM32_TIM10_CCMR1       (STM32_TIM10_BASE+STM32_GTIM_CCMR1_OFFSET)
+#  define STM32_TIM10_CCER        (STM32_TIM10_BASE+STM32_GTIM_CCER_OFFSET)
+#  define STM32_TIM10_CNT         (STM32_TIM10_BASE+STM32_GTIM_CNT_OFFSET)
+#  define STM32_TIM10_PSC         (STM32_TIM10_BASE+STM32_GTIM_PSC_OFFSET)
+#  define STM32_TIM10_ARR         (STM32_TIM10_BASE+STM32_GTIM_ARR_OFFSET)
+#  define STM32_TIM10_CCR1        (STM32_TIM10_BASE+STM32_GTIM_CCR1_OFFSET)
+#endif
+
+#if STM32F7_NGTIMNDMA > 2
+#  define STM32_TIM11_CR1         (STM32_TIM11_BASE+STM32_GTIM_CR1_OFFSET)
+#  define STM32_TIM11_DIER        (STM32_TIM11_BASE+STM32_GTIM_DIER_OFFSET)
+#  define STM32_TIM11_SR          (STM32_TIM11_BASE+STM32_GTIM_SR_OFFSET)
+#  define STM32_TIM11_EGR         (STM32_TIM11_BASE+STM32_GTIM_EGR_OFFSET)
+#  define STM32_TIM11_CCMR1       (STM32_TIM11_BASE+STM32_GTIM_CCMR1_OFFSET)
+#  define STM32_TIM11_CCER        (STM32_TIM11_BASE+STM32_GTIM_CCER_OFFSET)
+#  define STM32_TIM11_CNT         (STM32_TIM11_BASE+STM32_GTIM_CNT_OFFSET)
+#  define STM32_TIM11_PSC         (STM32_TIM11_BASE+STM32_GTIM_PSC_OFFSET)
+#  define STM32_TIM11_ARR         (STM32_TIM11_BASE+STM32_GTIM_ARR_OFFSET)
+#  define STM32_TIM11_CCR1        (STM32_TIM11_BASE+STM32_GTIM_CCR1_OFFSET)
+#  define STM32_TIM11_OR          (STM32_TIM11_BASE+STM32_GTIM_OR_OFFSET)
+#endif
+
+#if STM32F7_NGTIMNDMA > 3
+#  define STM32_TIM12_CR1         (STM32_TIM12_BASE+STM32_GTIM_CR1_OFFSET)
+#  define STM32_TIM12_CR2         (STM32_TIM9_BASE+STM32_GTIM_CR2_OFFSET)
+#  define STM32_TIM12_DIER        (STM32_TIM12_BASE+STM32_GTIM_DIER_OFFSET)
+#  define STM32_TIM12_SR          (STM32_TIM12_BASE+STM32_GTIM_SR_OFFSET)
+#  define STM32_TIM12_EGR         (STM32_TIM12_BASE+STM32_GTIM_EGR_OFFSET)
+#  define STM32_TIM12_CCMR1       (STM32_TIM12_BASE+STM32_GTIM_CCMR1_OFFSET)
+#  define STM32_TIM12_CCER        (STM32_TIM12_BASE+STM32_GTIM_CCER_OFFSET)
+#  define STM32_TIM12_CNT         (STM32_TIM12_BASE+STM32_GTIM_CNT_OFFSET)
+#  define STM32_TIM12_PSC         (STM32_TIM12_BASE+STM32_GTIM_PSC_OFFSET)
+#  define STM32_TIM12_ARR         (STM32_TIM12_BASE+STM32_GTIM_ARR_OFFSET)
+#  define STM32_TIM12_CCR1        (STM32_TIM12_BASE+STM32_GTIM_CCR1_OFFSET)
+#  define STM32_TIM12_CCR2        (STM32_TIM12_BASE+STM32_GTIM_CCR2_OFFSET)
+#endif
+
+#if STM32F7_NGTIMNDMA > 4
+#  define STM32_TIM13_CR1         (STM32_TIM13_BASE+STM32_GTIM_CR1_OFFSET)
+#  define STM32_TIM13_DIER        (STM32_TIM13_BASE+STM32_GTIM_DIER_OFFSET)
+#  define STM32_TIM13_SR          (STM32_TIM13_BASE+STM32_GTIM_SR_OFFSET)
+#  define STM32_TIM13_EGR         (STM32_TIM13_BASE+STM32_GTIM_EGR_OFFSET)
+#  define STM32_TIM13_CCMR1       (STM32_TIM13_BASE+STM32_GTIM_CCMR1_OFFSET)
+#  define STM32_TIM13_CCER        (STM32_TIM13_BASE+STM32_GTIM_CCER_OFFSET)
+#  define STM32_TIM13_CNT         (STM32_TIM13_BASE+STM32_GTIM_CNT_OFFSET)
+#  define STM32_TIM13_PSC         (STM32_TIM13_BASE+STM32_GTIM_PSC_OFFSET)
+#  define STM32_TIM13_ARR         (STM32_TIM13_BASE+STM32_GTIM_ARR_OFFSET)
+#  define STM32_TIM13_CCR1        (STM32_TIM13_BASE+STM32_GTIM_CCR1_OFFSET)
+#endif
+
+#if STM32F7_NGTIMNDMA > 5
+#  define STM32_TIM14_CR1         (STM32_TIM14_BASE+STM32_GTIM_CR1_OFFSET)
+#  define STM32_TIM14_DIER        (STM32_TIM14_BASE+STM32_GTIM_DIER_OFFSET)
+#  define STM32_TIM14_SR          (STM32_TIM14_BASE+STM32_GTIM_SR_OFFSET)
+#  define STM32_TIM14_EGR         (STM32_TIM14_BASE+STM32_GTIM_EGR_OFFSET)
+#  define STM32_TIM14_CCMR1       (STM32_TIM14_BASE+STM32_GTIM_CCMR1_OFFSET)
+#  define STM32_TIM14_CCER        (STM32_TIM14_BASE+STM32_GTIM_CCER_OFFSET)
+#  define STM32_TIM14_CNT         (STM32_TIM14_BASE+STM32_GTIM_CNT_OFFSET)
+#  define STM32_TIM14_PSC         (STM32_TIM14_BASE+STM32_GTIM_PSC_OFFSET)
+#  define STM32_TIM14_ARR         (STM32_TIM14_BASE+STM32_GTIM_ARR_OFFSET)
+#  define STM32_TIM14_CCR1        (STM32_TIM14_BASE+STM32_GTIM_CCR1_OFFSET)
+#endif
+
+/* Basic Timers - TIM6 and TIM7 */
+
+#if STM32F7_NBTIM > 0
+#  define STM32_TIM6_CR1          (STM32_TIM6_BASE+STM32_BTIM_CR1_OFFSET)
+#  define STM32_TIM6_CR2          (STM32_TIM6_BASE+STM32_BTIM_CR2_OFFSET)
+#  define STM32_TIM6_DIER         (STM32_TIM6_BASE+STM32_BTIM_DIER_OFFSET)
+#  define STM32_TIM6_SR           (STM32_TIM6_BASE+STM32_BTIM_SR_OFFSET)
+#  define STM32_TIM6_EGR          (STM32_TIM6_BASE+STM32_BTIM_EGR_OFFSET)
+#  define STM32_TIM6_CNT          (STM32_TIM6_BASE+STM32_BTIM_CNT_OFFSET)
+#  define STM32_TIM6_PSC          (STM32_TIM6_BASE+STM32_BTIM_PSC_OFFSET)
+#  define STM32_TIM6_ARR          (STM32_TIM6_BASE+STM32_BTIM_ARR_OFFSET)
+#endif
+
+#if STM32F7_NBTIM > 1
+#  define STM32_TIM7_CR1          (STM32_TIM7_BASE+STM32_BTIM_CR1_OFFSET)
+#  define STM32_TIM7_CR2          (STM32_TIM7_BASE+STM32_BTIM_CR2_OFFSET)
+#  define STM32_TIM7_DIER         (STM32_TIM7_BASE+STM32_BTIM_DIER_OFFSET)
+#  define STM32_TIM7_SR           (STM32_TIM7_BASE+STM32_BTIM_SR_OFFSET)
+#  define STM32_TIM7_EGR          (STM32_TIM7_BASE+STM32_BTIM_EGR_OFFSET)
+#  define STM32_TIM7_CNT          (STM32_TIM7_BASE+STM32_BTIM_CNT_OFFSET)
+#  define STM32_TIM7_PSC          (STM32_TIM7_BASE+STM32_BTIM_PSC_OFFSET)
+#  define STM32_TIM7_ARR          (STM32_TIM7_BASE+STM32_BTIM_ARR_OFFSET)
+#endif
+
+/* Register Bitfield Definitions ********************************************************************/
+
+/* Control register 1 */
+
+#define ATIM_CR1_CEN              (1 << 0)  /* Bit 0: Counter enable */
+#define ATIM_CR1_UDIS             (1 << 1)  /* Bit 1: Update disable */
+#define ATIM_CR1_URS              (1 << 2)  /* Bit 2: Update request source */
+#define ATIM_CR1_OPM              (1 << 3)  /* Bit 3: One pulse mode */
+#define ATIM_CR1_DIR              (1 << 4)  /* Bit 4: Direction */
+#define ATIM_CR1_CMS_SHIFT        (5)       /* Bits 6-5: Center-aligned mode selection */
+#define ATIM_CR1_CMS_MASK         (3 << ATIM_CR1_CMS_SHIFT)
+#  define ATIM_CR1_EDGE           (0 << ATIM_CR1_CMS_SHIFT) /* 00: Edge-aligned mode */
+#  define ATIM_CR1_CENTER1        (1 << ATIM_CR1_CMS_SHIFT) /* 01: Center-aligned mode 1 */
+#  define ATIM_CR1_CENTER2        (2 << ATIM_CR1_CMS_SHIFT) /* 10: Center-aligned mode 2 */
+#  define ATIM_CR1_CENTER3        (3 << ATIM_CR1_CMS_SHIFT) /* 11: Center-aligned mode 3 */
+#define ATIM_CR1_ARPE             (1 << 7)  /* Bit 7: Auto-reload preload enable */
+#define ATIM_CR1_CKD_SHIFT        (8)       /* Bits 9-8: Clock division */
+#define ATIM_CR1_CKD_MASK         (3 << ATIM_CR1_CKD_SHIFT)
+#  define ATIM_CR1_TCKINT         (0 << ATIM_CR1_CKD_SHIFT) /* 00: tDTS=tCK_INT */
+#  define ATIM_CR1_2TCKINT        (1 << ATIM_CR1_CKD_SHIFT) /* 01: tDTS=2*tCK_INT */
+#  define ATIM_CR1_4TCKINT        (2 << ATIM_CR1_CKD_SHIFT) /* 10: tDTS=4*tCK_INT */
+#define ATIM_CR1_UIFREMAP         (1 << 11) /* Bit 11: UIF status bit remapping */
+
+/* Control register 2 */
+
+#define ATIM_CR2_CCPC             (1 << 0)  /* Bit 0:  Capture/Compare Preloaded Control */
+#define ATIM_CR2_CCUS             (1 << 2)  /* Bit 2:  Capture/Compare Control Update Selection */
+#define ATIM_CR2_CCDS             (1 << 3)  /* Bit 3:  Capture/Compare DMA Selection */
+#define ATIM_CR2_MMS_SHIFT        (4)       /* Bits 6-4: Master Mode Selection */
+#define ATIM_CR2_MMS_MASK         (7 << ATIM_CR2_MMS_SHIFT)
+#  define ATIM_CR2_MMS_RESET      (0 << ATIM_CR2_MMS_SHIFT) /* 000: Reset - TIMx_EGR UG bit is TRGO */
+#  define ATIM_CR2_MMS_ENABLE     (1 << ATIM_CR2_MMS_SHIFT) /* 001: Enable - CNT_EN is TRGO */
+#  define ATIM_CR2_MMS_UPDATE     (2 << ATIM_CR2_MMS_SHIFT) /* 010: Update event is TRGO */
+#  define ATIM_CR2_MMS_COMPP      (3 << ATIM_CR2_MMS_SHIFT) /* 010: Compare Pulse - CC1IF flag */
+#  define ATIM_CR2_MMS_OC1REF     (4 << ATIM_CR2_MMS_SHIFT) /* 100: Compare OC1REF is TRGO */
+#  define ATIM_CR2_MMS_OC2REF     (5 << ATIM_CR2_MMS_SHIFT) /* 101: Compare OC2REF is TRGO */
+#  define ATIM_CR2_MMS_OC3REF     (6 << ATIM_CR2_MMS_SHIFT) /* 110: Compare OC3REF is TRGO */
+#  define ATIM_CR2_MMS_OC4REF     (7 << ATIM_CR2_MMS_SHIFT) /* 111: Compare OC4REF is TRGO */
+#define ATIM_CR2_TI1S             (1 << 7)  /* Bit 7: TI1 Selection */
+#define ATIM_CR2_OIS1             (1 << 8)  /* Bit 8:  Output Idle state 1 (OC1 output) */
+#define ATIM_CR2_OIS1N            (1 << 9)  /* Bit 9:  Output Idle state 1 (OC1N output) */
+#define ATIM_CR2_OIS2             (1 << 10) /* Bit 10: Output Idle state 2 (OC2 output) */
+#define ATIM_CR2_OIS2N            (1 << 11) /* Bit 11: Output Idle state 2 (OC2N output) */
+#define ATIM_CR2_OIS3             (1 << 12) /* Bit 12: Output Idle state 3 (OC3 output) */
+#define ATIM_CR2_OIS3N            (1 << 13) /* Bit 13: Output Idle state 3 (OC3N output) */
+#define ATIM_CR2_OIS4             (1 << 14) /* Bit 14: Output Idle state 4 (OC4 output) */
+#define ATIM_CR2_OIS5             (1 << 16) /* Bit 16: OOutput Idle state 5 (OC5 output) */
+#define ATIM_CR2_OIS6             (1 << 18) /* Bit 18: Output Idle state 6 (OC6 output) */
+#define ATIM_CR2_MMS2_SHIFT       (20)      /* Bits 20-23: Master Mode Selection 2 */
+#define ATIM_CR2_MMS2_MASK        (15 << ATIM_CR2_MMS2_SHIFT)
+#  define ATIM_CR2_MMS2_RESET     (0 << ATIM_CR2_MMS2_SHIFT)  /* 0000: Reset - TIMx_EGR UG bit is TRG9 */
+#  define ATIM_CR2_MMS2_ENABLE    (1 << ATIM_CR2_MMS2_SHIFT)  /* 0001: Enable - CNT_EN is TRGO2 */
+#  define ATIM_CR2_MMS2_UPDATE    (2 << ATIM_CR2_MMS2_SHIFT)  /* 0010: Update event is TRGH0*/
+#  define ATIM_CR2_MMS2_COMPP     (3 << ATIM_CR2_MMS2_SHIFT)  /* 0010: Compare Pulse - CC1IF flag */
+#  define ATIM_CR2_MMS2_OC1REF    (4 << ATIM_CR2_MMS2_SHIFT)  /* 0100: Compare OC1REF is TRGO2 */
+#  define ATIM_CR2_MMS2_OC2REF    (5 << ATIM_CR2_MMS2_SHIFT)  /* 0101: Compare OC2REF is TRGO2 */
+#  define ATIM_CR2_MMS2_OC3REF    (6 << ATIM_CR2_MMS2_SHIFT)  /* 0110: Compare OC3REF is TRGO2 */
+#  define ATIM_CR2_MMS2_OC4REF    (7 << ATIM_CR2_MMS2_SHIFT)  /* 0111: Compare OC4REF is TRGO2 */
+#  define ATIM_CR2_MMS2_OC5REF    (8 << ATIM_CR2_MMS2_SHIFT)  /* 1000: Compare OC5REF is TRGO2 */
+#  define ATIM_CR2_MMS2_OC6REF    (9 << ATIM_CR2_MMS2_SHIFT)  /* 1001: Compare OC6REF is TRGO2 */
+#  define ATIM_CR2_MMS2_CMPOC4    (10 << ATIM_CR2_MMS2_SHIFT) /* 1010: Compare pulse - OC4REF edge is TRGO2 */
+#  define ATIM_CR2_MMS2_CMPOC6    (11 << ATIM_CR2_MMS2_SHIFT) /* 1011: Compare pulse - OC6REF edge is TRGO2 */
+#  define ATIM_CR2_MMS2_CMPOC4R6R (12 << ATIM_CR2_MMS2_SHIFT) /* 1100: Compare pulse - OC4REF/OC6REF rising */
+#  define ATIM_CR2_MMS2_CMPOC4R6F (13 << ATIM_CR2_MMS2_SHIFT) /* 1101: Compare pulse - OC4REF rising/OC6REF falling */
+#  define ATIM_CR2_MMS2_CMPOC5R6R (14 << ATIM_CR2_MMS2_SHIFT) /* 1110: Compare pulse - OC5REF/OC6REF rising */
+#  define ATIM_CR2_MMS2_CMPOC5R6F (15 << ATIM_CR2_MMS2_SHIFT) /* 1111: Compare pulse - OC5REF rising/OC6REF falling */
+
+/* Slave mode control register */
+
+#define ATIM_SMCR_SMS_SHIFT       (0)       /* Bits 0-2: Slave mode selection */
+#define ATIM_SMCR_SMS_MASK        (7 << ATIM_SMCR_SMS_SHIFT)
+#  define ATIM_SMCR_DISAB         (0 << ATIM_SMCR_SMS_SHIFT) /* 000: Slave mode disabled */
+#  define ATIM_SMCR_ENCMD1        (1 << ATIM_SMCR_SMS_SHIFT) /* 001: Encoder mode 1 */
+#  define ATIM_SMCR_ENCMD2        (2 << ATIM_SMCR_SMS_SHIFT) /* 010: Encoder mode 2 */
+#  define ATIM_SMCR_ENCMD3        (3 << ATIM_SMCR_SMS_SHIFT) /* 011: Encoder mode 3 */
+#  define ATIM_SMCR_RESET         (4 << ATIM_SMCR_SMS_SHIFT) /* 100: Reset Mode */
+#  define ATIM_SMCR_GATED         (5 << ATIM_SMCR_SMS_SHIFT) /* 101: Gated Mode */
+#  define ATIM_SMCR_TRIGGER       (6 << ATIM_SMCR_SMS_SHIFT) /* 110: Trigger Mode */
+#  define ATIM_SMCR_EXTCLK1       (7 << ATIM_SMCR_SMS_SHIFT) /* 111: External Clock Mode 1 */
+#define ATIM_SMCR_TS_SHIFT        (4)       /* Bits 4-6: Trigger selection */
+#define ATIM_SMCR_TS_MASK         (7 << ATIM_SMCR_TS_SHIFT)
+#  define ATIM_SMCR_ITR0          (0 << ATIM_SMCR_TS_SHIFT) /* 000: Internal trigger 0 (ITR0) */
+#  define ATIM_SMCR_ITR1          (1 << ATIM_SMCR_TS_SHIFT) /* 001: Internal trigger 1 (ITR1) */
+#  define ATIM_SMCR_ITR2          (2 << ATIM_SMCR_TS_SHIFT) /* 010: Internal trigger 2 (ITR2) */
+#  define ATIM_SMCR_ITR3          (3 << ATIM_SMCR_TS_SHIFT) /* 011: Internal trigger 3 (ITR3) */
+#  define ATIM_SMCR_T1FED         (4 << ATIM_SMCR_TS_SHIFT) /* 100: TI1 Edge Detector (TI1F_ED) */
+#  define ATIM_SMCR_TI1FP1        (5 << ATIM_SMCR_TS_SHIFT) /* 101: Filtered Timer Input 1 (TI1FP1) */
+#  define ATIM_SMCR_T12FP2        (6 << ATIM_SMCR_TS_SHIFT) /* 110: Filtered Timer Input 2 (TI2FP2) */
+#  define ATIM_SMCR_ETRF          (7 << ATIM_SMCR_TS_SHIFT) /* 111: External Trigger input (ETRF) */
+#define ATIM_SMCR_MSM             (1 << 7)  /* Bit 7: Master/slave mode */
+#define ATIM_SMCR_ETF_SHIFT       (8)       /* Bits 8-11: External trigger filter */
+#define ATIM_SMCR_ETF_MASK        (0x0f << ATIM_SMCR_ETF_SHIFT)
+#  define ATIM_SMCR_NOFILT        (0 << ATIM_SMCR_ETF_SHIFT) /* 0000: No filter, sampling is done at fDTS */
+#  define ATIM_SMCR_FCKINT2       (1 << ATIM_SMCR_ETF_SHIFT) /* 0001: fSAMPLING=fCK_INT, N=2 */
+#  define ATIM_SMCR_FCKINT4       (2 << ATIM_SMCR_ETF_SHIFT) /* 0010: fSAMPLING=fCK_INT, N=4 */
+#  define ATIM_SMCR_FCKINT8       (3 << ATIM_SMCR_ETF_SHIFT) /* 0011: fSAMPLING=fCK_INT, N=8 */
+#  define ATIM_SMCR_FDTSd26       (4 << ATIM_SMCR_ETF_SHIFT) /* 0100: fSAMPLING=fDTS/2, N=6 */
+#  define ATIM_SMCR_FDTSd28       (5 << ATIM_SMCR_ETF_SHIFT) /* 0101: fSAMPLING=fDTS/2, N=8 */
+#  define ATIM_SMCR_FDTSd46       (6 << ATIM_SMCR_ETF_SHIFT) /* 0110: fSAMPLING=fDTS/4, N=6 */
+#  define ATIM_SMCR_FDTSd48       (7 << ATIM_SMCR_ETF_SHIFT) /* 0111: fSAMPLING=fDTS/4, N=8 */
+#  define ATIM_SMCR_FDTSd86       (8 << ATIM_SMCR_ETF_SHIFT) /* 1000: fSAMPLING=fDTS/8, N=6 */
+#  define ATIM_SMCR_FDTSd88       (9 << ATIM_SMCR_ETF_SHIFT) /* 1001: fSAMPLING=fDTS/8, N=8 */
+#  define ATIM_SMCR_FDTSd165      (10 << ATIM_SMCR_ETF_SHIFT) /* 1010: fSAMPLING=fDTS/16, N=5 */
+#  define ATIM_SMCR_FDTSd166      (11 << ATIM_SMCR_ETF_SHIFT) /* 1011: fSAMPLING=fDTS/16, N=6 */
+#  define ATIM_SMCR_FDTSd168      (12 << ATIM_SMCR_ETF_SHIFT) /* 1100: fSAMPLING=fDTS/16, N=8 */
+#  define ATIM_SMCR_FDTSd325      (13 << ATIM_SMCR_ETF_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */
+#  define ATIM_SMCR_FDTSd326      (14 << ATIM_SMCR_ETF_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */
+#  define ATIM_SMCR_FDTSd328      (15 << ATIM_SMCR_ETF_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */
+#define ATIM_SMCR_ETPS_SHIFT      (12)      /* Bits 12-13: External trigger prescaler */
+#define ATIM_SMCR_ETPS_MASK       (3 << ATIM_SMCR_ETPS_SHIFT)
+#  define ATIM_SMCR_PSCOFF        (0 << ATIM_SMCR_ETPS_SHIFT) /* 00: Prescaler OFF */
+#  define ATIM_SMCR_ETRPd2        (1 << ATIM_SMCR_ETPS_SHIFT) /* 01: ETRP frequency divided by 2 */
+#  define ATIM_SMCR_ETRPd4        (2 << ATIM_SMCR_ETPS_SHIFT) /* 10: ETRP frequency divided by 4 */
+#  define ATIM_SMCR_ETRPd8        (3 << ATIM_SMCR_ETPS_SHIFT) /* 11: ETRP frequency divided by 8 */
+#define ATIM_SMCR_ECE             (1 << 14) /* Bit 14: External clock enable */
+#define ATIM_SMCR_ETP             (1 << 15) /* Bit 15: External trigger polarity */
+#define ATIM_SMCR_SMS             (1 << 16) /* Bit 16: Slave mode selection - bit 3 */
+
+/* DMA/Interrupt enable register */
+
+#define ATIM_DIER_UIE             (1 << 0)  /* Bit 0: Update interrupt enable */
+#define ATIM_DIER_CC1IE           (1 << 1)  /* Bit 1: Capture/Compare 1 interrupt enable */
+#define ATIM_DIER_CC2IE           (1 << 2)  /* Bit 2: Capture/Compare 2 interrupt enable */
+#define ATIM_DIER_CC3IE           (1 << 3)  /* Bit 3: Capture/Compare 3 interrupt enable */
+#define ATIM_DIER_CC4IE           (1 << 4)  /* Bit 4: Capture/Compare 4 interrupt enable */
+#define ATIM_DIER_COMIE           (1 << 5)  /* Bit 5: COM interrupt enable */
+#define ATIM_DIER_TIE             (1 << 6)  /* Bit 6: Trigger interrupt enable */
+#define ATIM_DIER_BIE             (1 << 7)  /* Bit 7: Break interrupt enable */
+#define ATIM_DIER_UDE             (1 << 8)  /* Bit 8: Update DMA request enable */
+#define ATIM_DIER_CC1DE           (1 << 9)  /* Bit 9: Capture/Compare 1 DMA request enable */
+#define ATIM_DIER_CC2DE           (1 << 10) /* Bit 10: Capture/Compare 2 DMA request enable */
+#define ATIM_DIER_CC3DE           (1 << 11) /* Bit 11: Capture/Compare 3 DMA request enable */
+#define ATIM_DIER_CC4DE           (1 << 12) /* Bit 12: Capture/Compare 4 DMA request enable */
+#define ATIM_DIER_COMDE           (1 << 13) /* Bit 13: COM DMA request enable */
+#define ATIM_DIER_TDE             (1 << 14) /* Bit 14: Trigger DMA request enable */
+
+/* Status register */
+
+#define ATIM_SR_UIF               (1 << 0)  /* Bit 0:  Update interrupt Flag */
+#define ATIM_SR_CC1IF             (1 << 1)  /* Bit 1:  Capture/Compare 1 interrupt Flag */
+#define ATIM_SR_CC2IF             (1 << 2)  /* Bit 2:  Capture/Compare 2 interrupt Flag */
+#define ATIM_SR_CC3IF             (1 << 3)  /* Bit 3:  Capture/Compare 3 interrupt Flag */
+#define ATIM_SR_CC4IF             (1 << 4)  /* Bit 4:  Capture/Compare 4 interrupt Flag */
+#define ATIM_SR_COMIF             (1 << 5)  /* Bit 5:  COM interrupt Flag */
+#define ATIM_SR_TIF               (1 << 6)  /* Bit 6:  Trigger interrupt Flag */
+#define ATIM_SR_BIF               (1 << 7)  /* Bit 7:  Break interrupt Flag */
+#define ATIM_SR_B2IF              (1 << 8)  /* Bit 8:  Break 2 interrupt Flag */
+#define ATIM_SR_CC1OF             (1 << 9)  /* Bit 9:  Capture/Compare 1 Overcapture Flag */
+#define ATIM_SR_CC2OF             (1 << 10) /* Bit 10: Capture/Compare 2 Overcapture Flag */
+#define ATIM_SR_CC3OF             (1 << 11) /* Bit 11: Capture/Compare 3 Overcapture Flag */
+#define ATIM_SR_CC4OF             (1 << 12) /* Bit 12: Capture/Compare 4 Overcapture Flag */
+#define ATIM_SR_CC5IF             (1 << 16) /* Bit 16: Compare 5 interrupt flag */
+#define ATIM_SR_CC6IF             (1 << 17) /* Bit 17: Compare 6 interrupt flag */
+
+/* Event generation register */
+
+#define ATIM_EGR_UG               (1 << 0)  /* Bit 0: Update Generation */
+#define ATIM_EGR_CC1G             (1 << 1)  /* Bit 1: Capture/Compare 1 Generation */
+#define ATIM_EGR_CC2G             (1 << 2)  /* Bit 2: Capture/Compare 2 Generation */
+#define ATIM_EGR_CC3G             (1 << 3)  /* Bit 3: Capture/Compare 3 Generation */
+#define ATIM_EGR_CC4G             (1 << 4)  /* Bit 4: Capture/Compare 4 Generation */
+#define ATIM_EGR_COMG             (1 << 5)  /* Bit 5: Capture/Compare Control Update Generation */
+#define ATIM_EGR_TG               (1 << 6)  /* Bit 6: Trigger Generation */
+#define ATIM_EGR_BG               (1 << 7)  /* Bit 7: Break Generation */
+#define ATIM_EGR_B2G              (1 << 8)  /* Bit 8: Break 2 Generation */
+
+/* Capture/compare mode register 1 -- Output compare mode */
+
+#define ATIM_CCMR1_CC1S_SHIFT     (0)       /* Bits 1-0: Capture/Compare 1 Selection */
+#define ATIM_CCMR1_CC1S_MASK      (3 << ATIM_CCMR1_CC1S_SHIFT)
+                                            /* (See common (unshifted) bit field definitions below) */
+#define ATIM_CCMR1_OC1FE          (1 << 2)  /* Bit 2: Output Compare 1 Fast enable */
+#define ATIM_CCMR1_OC1PE          (1 << 3)  /* Bit 3: Output Compare 1 Preload enable */
+#define ATIM_CCMR1_OC1M_SHIFT     (4)       /* Bits 6-4: Output Compare 1 Mode */
+#define ATIM_CCMR1_OC1M_MASK      (7 << ATIM_CCMR1_OC1M_SHIFT)
+                                            /* (See common (unshifted) bit field definitions below) */
+#define ATIM_CCMR1_OC1CE          (1 << 7)  /* Bit 7: Output Compare 1Clear Enable */
+#define ATIM_CCMR1_CC2S_SHIFT     (8)       /* Bits 8-9: Capture/Compare 2 Selection */
+#define ATIM_CCMR1_CC2S_MASK      (3 << ATIM_CCMR1_CC2S_SHIFT)
+                                            /* (See common (unshifted) bit field definitions below) */
+#define ATIM_CCMR1_OC2FE          (1 << 10) /* Bit 10: Output Compare 2 Fast enable */
+#define ATIM_CCMR1_OC2PE          (1 << 11) /* Bit 11: Output Compare 2 Preload enable */
+#define ATIM_CCMR1_OC2M_SHIFT     (12)      /* Bits 14-12: Output Compare 2 Mode */
+#define ATIM_CCMR1_OC2M_MASK      (7 << ATIM_CCMR1_OC2M_SHIFT)
+                                            /* (See common (unshifted) bit field definitions below) */
+#define ATIM_CCMR1_OC2CE          (1 << 15) /* Bit 15: Output Compare 2 Clear Enable */
+#define ATIM_CCMR1_OC1M           (1 << 16) /* Bit 16: Output Compare 1 mode - bit 3 */
+#define ATIM_CCMR1_OC2M           (1 << 24) /* Bit 24: Output Compare 2 mode - bit 3 */
+
+
+/* Common CCMR (unshifted) Capture/Compare Selection bit-field definitions */
+
+#define ATIM_CCMR_CCS_CCOUT       (0)       /* 00: CCx channel  output */
+#define ATIM_CCMR_CCS_CCIN1       (1)       /* 01: CCx channel input, ICx is TIx */
+#define ATIM_CCMR_CCS_CCIN2       (2)       /* 10: CCx channel input, ICx is TIy */
+#define ATIM_CCMR_CCS_CCINTRC     (3)       /* 11: CCx channel input, ICx is TRC */
+
+/* Common CCMR (unshifted) Compare Mode bit field definitions */
+
+#define ATIM_CCMR_MODE_FRZN        (0)      /* 0000: Frozen */
+#define ATIM_CCMR_MODE_CHACT       (1)      /* 0001: Channel x active on match */
+#define ATIM_CCMR_MODE_CHINACT     (2)      /* 0010: Channel x inactive on match */
+#define ATIM_CCMR_MODE_OCREFTOG    (3)      /* 0011: OCxREF toggle ATIM_CNT=ATIM_CCRx */
+#define ATIM_CCMR_MODE_OCREFLO     (4)      /* 0100: OCxREF forced low */
+#define ATIM_CCMR_MODE_OCREFHI     (5)      /* 0101: OCxREF forced high */
+#define ATIM_CCMR_MODE_PWM1        (6)      /* 0110: PWM mode 1 */
+#define ATIM_CCMR_MODE_PWM2        (7)      /* 0111: PWM mode 2 */
+#define ATIM_CCMR_MODE_OPM1        (8)      /* 1000: Retrigerrable OPM mode 1 */
+#define ATIM_CCMR_MODE_OPM2        (9)      /* 1001: Retrigerrable OPM mode 2 */
+#define ATIM_CCMR_MODE_COMBINED1   (12)     /* 1100: Combined PWM mode 1 */
+#define ATIM_CCMR_MODE_COMBINED2   (13)     /* 1101: Combined PWM mode 2 */
+#define ATIM_CCMR_MODE_ASYMMETRIC1 (14)     /* 1110: Asymmetric PWM mode 1 */
+#define ATIM_CCMR_MODE_ASYMMETRIC2 (15)     /* 1111: Asymmetric PWM mode 2 */
+
+/* Capture/compare mode register 1 -- Input capture mode */
+
+                                            /* Bits 1-0:(same as output compare mode) */
+#define ATIM_CCMR1_IC1PSC_SHIFT   (2)       /* Bits 3-2: Input Capture 1 Prescaler */
+#define ATIM_CCMR1_IC1PSC_MASK    (3 << ATIM_CCMR1_IC1PSC_SHIFT)
+                                            /* (See common (unshifted) bit field definitions below) */
+#define ATIM_CCMR1_IC1F_SHIFT     (4)       /* Bits 7-4: Input Capture 1 Filter */
+#define ATIM_CCMR1_IC1F_MASK      (0x0f << ATIM_CCMR1_IC1F_SHIFT)
+                                            /* (See common (unshifted) bit field definitions below) */
+                                            /* Bits 9:8 (same as output compare mode) */
+#define ATIM_CCMR1_IC2PSC_SHIFT   (10)      /* Bits 11:10: Input Capture 2 Prescaler */
+#define ATIM_CCMR1_IC2PSC_MASK    (3 << ATIM_CCMR1_IC2PSC_SHIFT)
+                                            /* (See common (unshifted) bit field definitions below) */
+#define ATIM_CCMR1_IC2F_SHIFT     (12)      /* Bits 15-12: Input Capture 2 Filter */
+#define ATIM_CCMR1_IC2F_MASK      (0x0f << ATIM_CCMR1_IC2F_SHIFT)
+                                            /* (See common (unshifted) bit field definitions below) */
+
+/* Common CCMR (unshifted) Input Capture Prescaler bit-field definitions */
+
+#define ATIM_CCMR_ICPSC_NOPSC     (0)       /* 00: no prescaler, capture each edge */
+#define ATIM_CCMR_ICPSC_EVENTS2   (1)       /* 01: capture once every 2 events */
+#define ATIM_CCMR_ICPSC_EVENTS4   (2)       /* 10: capture once every 4 events */
+#define ATIM_CCMR_ICPSC_EVENTS8   (3)       /* 11: capture once every 8 events */
+
+/* Common CCMR (unshifted) Input Capture Filter bit-field definitions */
+
+#define ATIM_CCMR_ICF_NOFILT      (0)       /* 0000: No filter, sampling at fDTS */
+#define ATIM_CCMR_ICF_FCKINT2     (1)       /* 0001: fSAMPLING=fCK_INT, N=2 */
+#define ATIM_CCMR_ICF_FCKINT4     (2)       /* 0010: fSAMPLING=fCK_INT, N=4 */
+#define ATIM_CCMR_ICF_FCKINT8     (3)       /* 0011: fSAMPLING=fCK_INT, N=8 */
+#define ATIM_CCMR_ICF_FDTSd26     (4)       /* 0100: fSAMPLING=fDTS/2, N=6 */
+#define ATIM_CCMR_ICF_FDTSd28     (5)       /* 0101: fSAMPLING=fDTS/2, N=8 */
+#define ATIM_CCMR_ICF_FDTSd46     (6)       /* 0110: fSAMPLING=fDTS/4, N=6 */
+#define ATIM_CCMR_ICF_FDTSd48     (7)       /* 0111: fSAMPLING=fDTS/4, N=8 */
+#define ATIM_CCMR_ICF_FDTSd86     (8)       /* 1000: fSAMPLING=fDTS/8, N=6 */
+#define ATIM_CCMR_ICF_FDTSd88     (9)       /* 1001: fSAMPLING=fDTS/8, N=8 */
+#define ATIM_CCMR_ICF_FDTSd165    (10)      /* 1010: fSAMPLING=fDTS/16, N=5 */
+#define ATIM_CCMR_ICF_FDTSd166    (11)      /* 1011: fSAMPLING=fDTS/16, N=6 */
+#define ATIM_CCMR_ICF_FDTSd168    (12)      /* 1100: fSAMPLING=fDTS/16, N=8 */
+#define ATIM_CCMR_ICF_FDTSd325    (13)      /* 1101: fSAMPLING=fDTS/32, N=5 */
+#define ATIM_CCMR_ICF_FDTSd326    (14)      /* 1110: fSAMPLING=fDTS/32, N=6 */
+#define ATIM_CCMR_ICF_FDTSd328    (15)      /* 1111: fSAMPLING=fDTS/32, N=8 */
+
+/* Capture/compare mode register 2 - Output Compare mode */
+
+#define ATIM_CCMR2_CC3S_SHIFT     (0)       /* Bits 1-0: Capture/Compare 3 Selection */
+#define ATIM_CCMR2_CC3S_MASK      (3 << ATIM_CCMR2_CC3S_SHIFT)
+                                            /* (See common (unshifted) bit field definitions above) */
+#define ATIM_CCMR2_OC3FE          (1 << 2)  /* Bit 2: Output Compare 3 Fast enable */
+#define ATIM_CCMR2_OC3PE          (1 << 3)  /* Bit 3: Output Compare 3 Preload enable */
+#define ATIM_CCMR2_OC3M_SHIFT     (4)       /* Bits 6-4: Output Compare 3 Mode */
+#define ATIM_CCMR2_OC3M_MASK      (7 << ATIM_CCMR2_OC3M_SHIFT)
+                                            /* (See common (unshifted) bit field definitions above) */
+#define ATIM_CCMR2_OC3CE          (1 << 7)  /* Bit 7: Output Compare 3 Clear Enable */
+#define ATIM_CCMR2_CC4S_SHIFT     (8)       /* Bits 9-8: Capture/Compare 4 Selection */
+#define ATIM_CCMR2_CC4S_MASK      (3 << ATIM_CCMR2_CC4S_SHIFT)
+                                            /* (See common (unshifted) bit field definitions above) */
+#define ATIM_CCMR2_OC4FE          (1 << 10) /* Bit 10: Output Compare 4 Fast enable */
+#define ATIM_CCMR2_OC4PE          (1 << 11) /* Bit 11: Output Compare 4 Preload enable */
+#define ATIM_CCMR2_OC4M_SHIFT     (12)      /* Bits 14-12: Output Compare 4 Mode */
+#define ATIM_CCMR2_OC4M_MASK      (7 << ATIM_CCMR2_OC4M_SHIFT)
+                                            /* (See common (unshifted) bit field definitions above) */
+#define ATIM_CCMR2_OC4CE          (1 << 15) /* Bit 15: Output Compare 4 Clear Enable */
+#define ATIM_CCMR2_OC3M           (1 << 16) /* Bit 16: Output Compare 3 mode - bit 3 */
+#define ATIM_CCMR2_OC4M           (1 << 24) /* Bit 24: Output Compare 4 mode - bit 3 */
+
+/* Capture/compare mode register 2 - Input Capture Mode */
+
+                                            /* Bits 1-0:(same as output compare mode) */
+#define ATIM_CCMR2_IC3PSC_SHIFT   (2)       /* Bits 3-2: Input Capture 3 Prescaler */
+#define ATIM_CCMR1_IC3PSC_MASK    (3 << ATIM_CCMR2_IC3PSC_SHIFT)
+                                            /* (See common (unshifted) bit field definitions above) */
+#define ATIM_CCMR2_IC3F_SHIFT     (4)       /* Bits 7-4: Input Capture 3 Filter */
+#define ATIM_CCMR2_IC3F_MASK      (0x0f << ATIM_CCMR2_IC3F_SHIFT)
+                                            /* (See common (unshifted) bit field definitions above) */
+                                            /* Bits 9:8 (same as output compare mode) */
+#define ATIM_CCMR2_IC4PSC_SHIFT   (10)      /* Bits 11:10: Input Capture 4 Prescaler */
+#define ATIM_CCMR2_IC4PSC_MASK    (3 << ATIM_CCMR2_IC4PSC_SHIFT)
+                                            /* (See common (unshifted) bit field definitions above) */
+#define ATIM_CCMR2_IC4F_SHIFT     (12)      /* Bits 15-12: Input Capture 4 Filter */
+#define ATIM_CCMR2_IC4F_MASK      (0x0f << ATIM_CCMR2_IC4F_SHIFT)
+                                            /* (See common (unshifted) bit field definitions above) */
+
+/* Capture/compare mode register 3 -- Output compare mode */
+
+#define ATIM_CCMR3_OC5FE          (1 << 2)  /* Bit 2: Output Compare 5 Fast enable */
+#define ATIM_CCMR3_OC5PE          (1 << 3)  /* Bit 3: Output Compare 5 Preload enable */
+#define ATIM_CCMR3_OC5M_SHIFT     (4)       /* Bits 6-4: Output Compare 5 Mode */
+#define ATIM_CCMR3_OC5M_MASK      (7 << ATIM_CCMR3_OC5M_SHIFT)
+                                            /* (See common (unshifted) bit field definitions below) */
+#define ATIM_CCMR3_OC5CE          (1 << 7)  /* Bit 7: Output Compare 5 Clear Enable */
+#define ATIM_CCMR3_OC6FE          (1 << 10) /* Bit 10: Output Compare 6 Fast enable */
+#define ATIM_CCMR3_OC6PE          (1 << 11) /* Bit 11: Output Compare 6 Preload enable */
+#define ATIM_CCMR3_OC6M_SHIFT     (12)      /* Bits 14-12: Output Compare 7 Mode */
+#define ATIM_CCMR3_OC6M_MASK      (7 << ATIM_CCMR3_OC6M_SHIFT)
+                                            /* (See common (unshifted) bit field definitions below) */
+#define ATIM_CCMR3_OC6CE          (1 << 15) /* Bit 15: Output Compare 7 Clear Enable */
+#define ATIM_CCMR3_OC5M           (1 << 16) /* Bit 16: Output Compare 5 mode - bit 3 */
+#define ATIM_CCMR3_OC6M           (1 << 24) /* Bit 24: Output Compare 6 mode - bit 3 */
+
+
+/* Capture/compare enable register */
+
+#define ATIM_CCER_CC1E            (1 << 0)  /* Bit 0: Capture/Compare 1 output enable */
+#define ATIM_CCER_CC1P            (1 << 1)  /* Bit 1: Capture/Compare 1 output Polarity */
+#define ATIM_CCER_CC1NE           (1 << 2)  /* Bit 2: Capture/Compare 1 Complementary output enable */
+#define ATIM_CCER_CC1NP           (1 << 3)  /* Bit 3: Capture/Compare 1 Complementary output polarity */
+#define ATIM_CCER_CC2E            (1 << 4)  /* Bit 4: Capture/Compare 2 output enable */
+#define ATIM_CCER_CC2P            (1 << 5)  /* Bit 5: Capture/Compare 2 output Polarity */
+#define ATIM_CCER_CC2NE           (1 << 6)  /* Bit 6: Capture/Compare 2 Complementary output enable */
+#define ATIM_CCER_CC2NP           (1 << 7)  /* Bit 7: Capture/Compare 2 Complementary output polarity */
+#define ATIM_CCER_CC3E            (1 << 8)  /* Bit 8: Capture/Compare 3 output enable */
+#define ATIM_CCER_CC3P            (1 << 9)  /* Bit 9: Capture/Compare 3 output Polarity */
+#define ATIM_CCER_CC3NE           (1 << 10) /* Bit 10: Capture/Compare 3 Complementary output enable */
+#define ATIM_CCER_CC3NP           (1 << 11) /* Bit 11: Capture/Compare 3 Complementary output polarity */
+#define ATIM_CCER_CC4E            (1 << 12) /* Bit 12: Capture/Compare 4 output enable */
+#define ATIM_CCER_CC4P            (1 << 13) /* Bit 13: Capture/Compare 4 output Polarity */
+#define ATIM_CCER_CC4NP           (1 << 15) /* Bit 15: Capture/Compare 4 Complementary output polarity */
+#define ATIM_CCER_CC5E            (1 << 16) /* Bit 16: Capture/Compare 5 output enable */
+#define ATIM_CCER_CC5P            (1 << 17) /* Bit 17: Capture/Compare 5 output Polarity */
+#define ATIM_CCER_CC6E            (1 << 20) /* Bit 20: Capture/Compare 6 output enable */
+#define ATIM_CCER_CC6P            (1 << 21) /* Bit 21: Capture/Compare 6 output Polarity */
+
+
+/* 16-bit counter register */
+
+#define ATIM_CNT_SHIFT            (0)       /* Bits 0-15: Timer counter value */
+#define ATIM_CNT_MASK             (0xffff << ATIM_CNT_SHIFT)
+
+/* Repetition counter register */
+
+#define ATIM_RCR_REP_SHIFT        (0)       /* Bits 0-15: Repetition Counter Value */
+#define ATIM_RCR_REP_MASK         (0xffff << ATIM_RCR_REP_SHIFT)
+
+#define ATIM_RCR_REP_MAX          65536
+
+/* Capture/compare registers (CCR) */
+
+#define ATIM_CCR5_GC5C1           (1 << 29)  /* Bit 29: Group Channel 5 and Channel 1 */
+#define ATIM_CCR5_GC5C2           (1 << 30)  /* Bit 30: Group Channel 5 and Channel 2 */
+#define ATIM_CCR5_GC5C3           (1 << 31)  /* Bit 31: Group Channel 5 and Channel 3 */
+
+#define ATIM_CCR_MASK             (0xffff)
+
+/* Alternate function option register 1 (TIMx_AF1) */
+
+#define ATIM_AF1_BKINE            (1 << 0)  /* Bit 0: BRK BKIN input enable */
+#define ATIM_AF1_BKDFBKE          (1 << 8)  /* Bit 8: BRK DFSDM_BREAK[0] enable */
+#define ATIM_AF1_BKINP            (1 << 9)  /* Bit 9: BRK BKIN input polarity */
+
+/* Alternate function option register 2 (TIMx_AF2) */
+
+#define ATIM_AF1_BK2INE           (1 << 0)  /* Bit 0: BRK2 BKIN input enable */
+#define ATIM_AF1_BK2DFBKE         (1 << 8)  /* Bit 8: BRK2 DFSDM_BREAK enable */
+#define ATIM_AF1_BK2INP           (1 << 9)  /* Bit 9: BRK2 BKIN2 input polarity */
+
+/* Break and dead-time register */
+
+#define ATIM_BDTR_DTG_SHIFT       (0)       /* Bits 7:0 [7:0]: Dead-Time Generator set-up */
+#define ATIM_BDTR_DTG_MASK        (0xff << ATIM_BDTR_DTG_SHIFT)
+#define ATIM_BDTR_LOCK_SHIFT      (8)       /* Bits 9:8 [1:0]: Lock Configuration */
+#define ATIM_BDTR_LOCK_MASK       (3 << ATIM_BDTR_LOCK_SHIFT)
+#  define ATIM_BDTR_LOCKOFF       (0 << ATIM_BDTR_LOCK_SHIFT) /* 00: LOCK OFF - No bit is write protected */
+#  define ATIM_BDTR_LOCK1         (1 << ATIM_BDTR_LOCK_SHIFT) /* 01: LOCK Level 1 protection */
+#  define ATIM_BDTR_LOCK2         (2 << ATIM_BDTR_LOCK_SHIFT) /* 10: LOCK Level 2 protection */
+#  define ATIM_BDTR_LOCK3         (3 << ATIM_BDTR_LOCK_SHIFT) /* 11: LOCK Level 3 protection */ */
+#define ATIM_BDTR_OSSI            (1 << 10) /* Bit 10: Off-State Selection for Idle mode */
+#define ATIM_BDTR_OSSR            (1 << 11) /* Bit 11: Off-State Selection for Run mode */
+#define ATIM_BDTR_BKE             (1 << 12) /* Bit 12: Break enable */
+#define ATIM_BDTR_BKP             (1 << 13) /* Bit 13: Break Polarity */
+#define ATIM_BDTR_AOE             (1 << 14) /* Bit 14: Automatic Output enable */
+#define ATIM_BDTR_MOE             (1 << 15) /* Bit 15: Main Output enable */
+#define ATIM_BDTR_BKF_SHIFT       (16)      /* Bits 16-19: Break filter */
+#define ATIM_BDTR_BKF_MASK        (0xf << ATIM_BDTR_BKF_SHIFT)
+#  define ATIM_BDTR_BKF_NOFILT    (0 << ATIM_BDTR_BKF_SHIFT)   /* 0000: No filter, BRK acts asynchronously */
+#  define ATIM_BDTR_BKF_FCKINT2   (1 << ATIM_BDTR_BKF_SHIFT)   /* 0001: fSAMPLING=fCK_INT, N=2 */
+#  define ATIM_BDTR_BKF_FCKINT4   (2 << ATIM_BDTR_BKF_SHIFT)   /* 0010: fSAMPLING=fCK_INT, N=4 */
+#  define ATIM_BDTR_BKF_FCKINT8   (3 << ATIM_BDTR_BKF_SHIFT)   /* 0011: fSAMPLING=fCK_INT, N=8 */
+#  define ATIM_BDTR_BKF_FDTSd26   (4 << ATIM_BDTR_BKF_SHIFT)   /* 0100: fSAMPLING=fDTS/2, N=6 */
+#  define ATIM_BDTR_BKF_FDTSd28   (5 << ATIM_BDTR_BKF_SHIFT)   /* 0101: fSAMPLING=fDTS/2, N=8 */
+#  define ATIM_BDTR_BKF_FDTSd36   (6 << ATIM_BDTR_BKF_SHIFT)   /* 0110: fSAMPLING=fDTS/4, N=6 */
+#  define ATIM_BDTR_BKF_FDTSd38   (7 << ATIM_BDTR_BKF_SHIFT)   /* 0111: fSAMPLING=fDTS/4, N=8 */
+#  define ATIM_BDTR_BKF_FDTSd86   (8 << ATIM_BDTR_BKF_SHIFT)   /* 1000: fSAMPLING=fDTS/8, N=6 */
+#  define ATIM_BDTR_BKF_FDTSd88   (9 << ATIM_BDTR_BKF_SHIFT)   /* 1001: fSAMPLING=fDTS/8, N=8 */
+#  define ATIM_BDTR_BKF_FDTSd165  (10 << ATIM_BDTR_BKF_SHIFT)  /* 1010: fSAMPLING=fDTS/16, N=5 */
+#  define ATIM_BDTR_BKF_FDTSd166  (11 << ATIM_BDTR_BKF_SHIFT)  /* 1011: fSAMPLING=fDTS/16, N=6 */
+#  define ATIM_BDTR_BKF_FDTSd168  (12 << ATIM_BDTR_BKF_SHIFT)  /* 1100: fSAMPLING=fDTS/16, N=8 */
+#  define ATIM_BDTR_BKF_FDTSd325  (13 << ATIM_BDTR_BKF_SHIFT)  /* 1101: fSAMPLING=fDTS/32, N=5 */
+#  define ATIM_BDTR_BKF_FDTSd326  (14 << ATIM_BDTR_BKF_SHIFT)  /* 1110: fSAMPLING=fDTS/32, N=6 */
+#  define ATIM_BDTR_BKF_FDTSd328  (15 << ATIM_BDTR_BKF_SHIFT)  /* 1111: fSAMPLING=fDTS/32, N=8 */
+#define ATIM_BDTR_BK2F_SHIFT      (20)      /* Bits 20-23: Break 2 filter */
+#define ATIM_BDTR_BK2F_MASK       (0xf << ATIM_BDTR_BK2F_SHIFT)
+#  define ATIM_BDTR_BK2F_NOFILT   (0 << ATIM_BDTR_BK2F_SHIFT)  /* 0000: No filter, BRK 2 acts asynchronously */
+#  define ATIM_BDTR_BK2F_FCKINT2  (1 << ATIM_BDTR_BK2F_SHIFT)  /* 0001: fSAMPLING=fCK_INT, N=2 */
+#  define ATIM_BDTR_BK2F_FCKINT4  (2 << ATIM_BDTR_BK2F_SHIFT)  /* 0010: fSAMPLING=fCK_INT, N=4 */
+#  define ATIM_BDTR_BK2F_FCKINT8  (3 << ATIM_BDTR_BK2F_SHIFT)  /* 0011: fSAMPLING=fCK_INT, N=8 */
+#  define ATIM_BDTR_BK2F_FDTSd26  (4 << ATIM_BDTR_BK2F_SHIFT)  /* 0100: fSAMPLING=fDTS/2, N=6 */
+#  define ATIM_BDTR_BK2F_FDTSd28  (5 << ATIM_BDTR_BK2F_SHIFT)  /* 0101: fSAMPLING=fDTS/2, N=8 */
+#  define ATIM_BDTR_BK2F_FDTSd36  (6 << ATIM_BDTR_BK2F_SHIFT)  /* 0110: fSAMPLING=fDTS/4, N=6 */
+#  define ATIM_BDTR_BK2F_FDTSd38  (7 << ATIM_BDTR_BK2F_SHIFT)  /* 0111: fSAMPLING=fDTS/4, N=8 */
+#  define ATIM_BDTR_BK2F_FDTSd86  (8 << ATIM_BDTR_BK2F_SHIFT)  /* 1000: fSAMPLING=fDTS/8, N=6 */
+#  define ATIM_BDTR_BK2F_FDTSd88  (9 << ATIM_BDTR_BK2F_SHIFT)  /* 1001: fSAMPLING=fDTS/8, N=8 */
+#  define ATIM_BDTR_BK2F_FDTSd165 (10 << ATIM_BDTR_BK2F_SHIFT) /* 1010: fSAMPLING=fDTS/16, N=5 */
+#  define ATIM_BDTR_BK2F_FDTSd166 (11 << ATIM_BDTR_BK2F_SHIFT) /* 1011: fSAMPLING=fDTS/16, N=6 */
+#  define ATIM_BDTR_BK2F_FDTSd168 (12 << ATIM_BDTR_BK2F_SHIFT) /* 1100: fSAMPLING=fDTS/16, N=8 */
+#  define ATIM_BDTR_BK2F_FDTSd325 (13 << ATIM_BDTR_BK2F_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */
+#  define ATIM_BDTR_BK2F_FDTSd326 (14 << ATIM_BDTR_BK2F_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */
+#  define ATIM_BDTR_BK2F_FDTSd328 (15 << ATIM_BDTR_BK2F_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */
+#define ATIM_BDTR_BK2E            (1 << 24) /* Bit 24: Break 2 enable */
+#define ATIM_BDTR_BK2P            (1 << 1525 /* Bit 25:Break 2 polarity */
+
+
+/* DMA control register */
+
+#define ATIM_DCR_DBA_SHIFT        (0)       /* Bits 4-0: DMA Base Address */
+#define ATIM_DCR_DBA_MASK         (0x1f << ATIM_DCR_DBA_SHIFT)
+#define ATIM_DCR_DBL_SHIFT        (8)       /* Bits 12-8: DMA Burst Length */
+#define ATIM_DCR_DBL_MASK         (0x1f << ATIM_DCR_DBL_SHIFT)
+#  define ATIM_DCR_DBL(n)         (((n)-1) << ATIM_DCR_DBL_SHIFT) /* n transfers, n = 1..18 */
+
+/* Control register 1 (TIM2-5 and TIM9-14) */
+
+#define GTIM_CR1_CEN              (1 << 0)  /* Bit 0: Counter enable */
+#define GTIM_CR1_UDIS             (1 << 1)  /* Bit 1: Update Disable */
+#define GTIM_CR1_URS              (1 << 2)  /* Bit 2: Update Request Source */
+#define GTIM_CR1_OPM              (1 << 3)  /* Bit 3: One Pulse Mode (TIM2-5, 9, and 12 only) */
+#define GTIM_CR1_DIR              (1 << 4)  /* Bit 4: Direction (TIM2-5 only) */
+#define GTIM_CR1_CMS_SHIFT        (5)       /* Bits 6-5: Center-aligned Mode Selection (TIM2-5 only) */
+#define GTIM_CR1_CMS_MASK         (3 << GTIM_CR1_CMS_SHIFT)
+#  define GTIM_CR1_EDGE           (0 << GTIM_CR1_CMS_SHIFT) /* 00: Edge-aligned mode.  */
+#  define GTIM_CR1_CENTER1        (1 << GTIM_CR1_CMS_SHIFT) /* 01: Center-aligned mode 1 */
+#  define GTIM_CR1_CENTER2        (2 << GTIM_CR1_CMS_SHIFT) /* 10: Center-aligned mode 2 */
+#  define GTIM_CR1_CENTER3        (3 << GTIM_CR1_CMS_SHIFT) /* 11: Center-aligned mode 3 */
+#define GTIM_CR1_ARPE             (1 << 7)  /* Bit 7: Auto-Reload Preload enable */
+#define GTIM_CR1_CKD_SHIFT        (8)       /* Bits 9-8: Clock Division */
+#define GTIM_CR1_CKD_MASK         (3 << GTIM_CR1_CKD_SHIFT)
+#  define GTIM_CR1_TCKINT         (0 << GTIM_CR1_CKD_SHIFT) /* 00: tDTS = tCK_INT */
+#  define GTIM_CR1_2TCKINT        (1 << GTIM_CR1_CKD_SHIFT) /* 01: tDTS = 2 x tCK_INT */
+#  define GTIM_CR1_4TCKINT        (2 << GTIM_CR1_CKD_SHIFT) /* 10: tDTS = 4 x tCK_INT */
+#define GTIM_CR1_UIFREMAP         (1 << 11) /* Bit 11: UIF status bit remapping */
+
+/* Control register 2 (TIM2-5, TIM9-12) */
+
+#define GTIM_CR2_CCPC             (1 << 0)  /* Bit 0: Capture/compare preloaded control (TIM15-17 only) */
+#define GTIM_CR2_CCUS             (1 << 2)  /* Bit 2: Capture/compare control update selection (TIM15-17 only) */
+#define GTIM_CR2_CCDS             (1 << 3)  /* Bit 3: Capture/Compare DMA Selection (TIM2-5,1,&16 only) */
+#define GTIM_CR2_MMS_SHIFT        (4)       /* Bits 6-4: Master Mode Selection (not TIM16) */
+#define GTIM_CR2_MMS_MASK         (7 << GTIM_CR2_MMS_SHIFT)
+#  define GTIM_CR2_MMS_RESET      (0 << GTIM_CR2_MMS_SHIFT) /* 000: Reset */
+#  define GTIM_CR2_MMS_ENABLE     (1 << GTIM_CR2_MMS_SHIFT) /* 001: Enable */
+#  define GTIM_CR2_MMS_UPDATE     (2 << GTIM_CR2_MMS_SHIFT) /* 010: Update */
+#  define GTIM_CR2_MMS_COMPP      (3 << GTIM_CR2_MMS_SHIFT) /* 011: Compare Pulse */
+#  define GTIM_CR2_MMS_OC1REF     (4 << GTIM_CR2_MMS_SHIFT) /* 100: Compare - OC1REF signal is used as trigger output (TRGO) */
+#  define GTIM_CR2_MMS_OC2REF     (5 << GTIM_CR2_MMS_SHIFT) /* 101: Compare - OC2REF signal is used as trigger output (TRGO) */
+#  define GTIM_CR2_MMS_OC3REF     (6 << GTIM_CR2_MMS_SHIFT) /* 110: Compare - OC3REF signal is used as trigger output (TRGO, TIM2-5 and TIM15 only) */
+#  define GTIM_CR2_MMS_OC4REF     (7 << GTIM_CR2_MMS_SHIFT) /* 111: Compare - OC4REF signal is used as trigger output (TRGO, TIM2-5 and TIM15 only) */
+#define GTIM_CR2_TI1S             (1 << 7)  /* Bit 7: TI1 Selection (not TIM16) */
+#define GTIM_CR2_OIS1             (1 << 8)  /* Bit 8: COutput Idle state 1 (OC1 output) (TIM15-17 only) */
+#define GTIM_CR2_OIS1N            (1 << 9)  /* Bit 9: Output Idle state 1 (OC1N output) (TIM15-17 only) */
+#define GTIM_CR2_OIS2             (1 << 10) /* Bit 10: Output idle state 2 (OC2 output) (TIM15 only) */
+
+/* Slave mode control register (TIM2-5) */
+
+#define GTIM_SMCR_SMS_SHIFT       (0)       /* Bits 2-0: Slave Mode Selection */
+#define GTIM_SMCR_SMS_MASK        (7 << GTIM_SMCR_SMS_SHIFT)
+#  define GTIM_SMCR_DISAB         (0 << GTIM_SMCR_SMS_SHIFT) /* 000: Slave mode disabled */
+#  define GTIM_SMCR_ENCMD1        (1 << GTIM_SMCR_SMS_SHIFT) /* 001: Encoder mode 1 */
+#  define GTIM_SMCR_ENCMD2        (2 << GTIM_SMCR_SMS_SHIFT) /* 010: Encoder mode 2 */
+#  define GTIM_SMCR_ENCMD3        (3 << GTIM_SMCR_SMS_SHIFT) /* 011: Encoder mode 3 */
+#  define GTIM_SMCR_RESET         (4 << GTIM_SMCR_SMS_SHIFT) /* 100: Reset Mode  */
+#  define GTIM_SMCR_GATED         (5 << GTIM_SMCR_SMS_SHIFT) /* 101: Gated Mode  */
+#  define GTIM_SMCR_TRIGGER       (6 << GTIM_SMCR_SMS_SHIFT) /* 110: Trigger Mode */
+#  define GTIM_SMCR_EXTCLK1       (7 << GTIM_SMCR_SMS_SHIFT) /* 111: External Clock Mode 1 */
+#define GTIM_SMCR_TS_SHIFT        (4)       /* Bits 6-4: Trigger Selection */
+#define GTIM_SMCR_TS_MASK         (7 << GTIM_SMCR_TS_SHIFT)
+#  define GTIM_SMCR_ITR0          (0 << GTIM_SMCR_TS_SHIFT) /* 000: Internal Trigger 0 (ITR0). TIM1 */
+#  define GTIM_SMCR_ITR1          (1 << GTIM_SMCR_TS_SHIFT) /* 001: Internal Trigger 1 (ITR1). TIM2 */
+#  define GTIM_SMCR_ITR2          (2 << GTIM_SMCR_TS_SHIFT) /* 010: Internal Trigger 2 (ITR2). TIM3 */
+#  define GTIM_SMCR_ITR3          (3 << GTIM_SMCR_TS_SHIFT) /* 011: Internal Trigger 3 (ITR3). TIM4 */
+#  define GTIM_SMCR_TI1FED        (4 << GTIM_SMCR_TS_SHIFT) /* 100: TI1 Edge Detector (TI1F_ED) */
+#  define GTIM_SMCR_TI1FP1        (5 << GTIM_SMCR_TS_SHIFT) /* 101: Filtered Timer Input 1 (TI1FP1) */
+#  define GTIM_SMCR_TI2FP2        (6 << GTIM_SMCR_TS_SHIFT) /* 110: Filtered Timer Input 2 (TI2FP2) */
+#  define GTIM_SMCR_ETRF          (7 << GTIM_SMCR_TS_SHIFT) /* 111: External Trigger input (ETRF) */
+#define GTIM_SMCR_MSM             (1 << 7)  /* Bit 7: Master/Slave mode */
+#define GTIM_SMCR_ETF_SHIFT       (8)       /* Bits 11-8: External Trigger Filter (not TIM15) */
+#define GTIM_SMCR_ETF_MASK        (0x0f << GTIM_SMCR_ETF_SHIFT)
+#  define GTIM_SMCR_NOFILT        (0 << GTIM_SMCR_ETF_SHIFT)  /* 0000: No filter, sampling is done at fDTS */
+#  define GTIM_SMCR_FCKINT2       (1 << GTIM_SMCR_ETF_SHIFT)  /* 0001: fSAMPLING=fCK_INT, N=2 */
+#  define GTIM_SMCR_FCKINT4       (2 << GTIM_SMCR_ETF_SHIFT)  /* 0010: fSAMPLING=fCK_INT, N=4 */
+#  define GTIM_SMCR_FCKINT8       (3 << GTIM_SMCR_ETF_SHIFT)  /* 0011: fSAMPLING=fCK_INT, N=8 */
+#  define GTIM_SMCR_FDTSd26       (4 << GTIM_SMCR_ETF_SHIFT)  /* 0100: fSAMPLING=fDTS/2, N=6 */
+#  define GTIM_SMCR_FDTSd28       (5 << GTIM_SMCR_ETF_SHIFT)  /* 0101: fSAMPLING=fDTS/2, N=8 */
+#  define GTIM_SMCR_FDTSd36       (6 << GTIM_SMCR_ETF_SHIFT)  /* 0110: fSAMPLING=fDTS/4, N=6 */
+#  define GTIM_SMCR_FDTSd38       (7 << GTIM_SMCR_ETF_SHIFT)  /* 0111: fSAMPLING=fDTS/4, N=8 */
+#  define GTIM_SMCR_FDTSd86       (8 << GTIM_SMCR_ETF_SHIFT)  /* 1000: fSAMPLING=fDTS/8, N=6 */
+#  define GTIM_SMCR_FDTSd88       (9 << GTIM_SMCR_ETF_SHIFT)  /* 1001: fSAMPLING=fDTS/8, N=8 */
+#  define GTIM_SMCR_FDTSd165      (10 << GTIM_SMCR_ETF_SHIFT) /* 1010: fSAMPLING=fDTS/16, N=5 */
+#  define GTIM_SMCR_FDTSd166      (11 << GTIM_SMCR_ETF_SHIFT) /* 1011: fSAMPLING=fDTS/16, N=6 */
+#  define GTIM_SMCR_FDTSd168      (12 << GTIM_SMCR_ETF_SHIFT) /* 1100: fSAMPLING=fDTS/16, N=8 */
+#  define GTIM_SMCR_FDTSd325      (13 << GTIM_SMCR_ETF_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */
+#  define GTIM_SMCR_FDTSd326      (14 << GTIM_SMCR_ETF_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */
+#  define GTIM_SMCR_FDTSd328      (15 << GTIM_SMCR_ETF_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */
+#define GTIM_SMCR_ETPS_SHIFT      (12)      /* Bits 13-12: External Trigger Prescaler (not TIM15) */
+#define GTIM_SMCR_ETPS_MASK       (3 << GTIM_SMCR_ETPS_SHIFT)
+#  define GTIM_SMCR_PSCOFF        (0 << GTIM_SMCR_ETPS_SHIFT) /* 00: Prescaler OFF */
+#  define GTIM_SMCR_ETRPd2        (1 << GTIM_SMCR_ETPS_SHIFT) /* 01: ETRP frequency divided by 2 */
+#  define GTIM_SMCR_ETRPd4        (2 << GTIM_SMCR_ETPS_SHIFT) /* 10: ETRP frequency divided by 4 */
+#  define GTIM_SMCR_ETRPd8        (3 << GTIM_SMCR_ETPS_SHIFT) /* 11: ETRP frequency divided by 8 */
+#define GTIM_SMCR_ECE             (1 << 14) /* Bit 14: External Clock enable */
+#define GTIM_SMCR_ETP             (1 << 15) /* Bit 15: External Trigger Polarity */
+#define GTIM_SMCR_SMS             (1 << 16) /* Bit 16: Slave mode selection - bit 3 */
+
+/* DMA/Interrupt enable register (TIM2-5 and TIM9-14) */
+
+#define GTIM_DIER_UIE             (1 << 0)  /* Bit 0: Update interrupt enable */
+#define GTIM_DIER_CC1IE           (1 << 1)  /* Bit 1: Capture/Compare 1 interrupt enable */
+#define GTIM_DIER_CC2IE           (1 << 2)  /* Bit 2: Capture/Compare 2 interrupt enable (TIM2-5,9,12,&15 only) */
+#define GTIM_DIER_CC3IE           (1 << 3)  /* Bit 3: Capture/Compare 3 interrupt enable (TIM2-5 only) */
+#define GTIM_DIER_CC4IE           (1 << 4)  /* Bit 4: Capture/Compare 4 interrupt enable (TIM2-5 only) */
+#define GTIM_DIER_COMIE           (1 << 5)  /* Bit 5: COM interrupt enable (TIM15-17 only) */
+#define GTIM_DIER_TIE             (1 << 6)  /* Bit 6: Trigger interrupt enable (TIM2-5,9,&12 only) */
+#define GTIM_DIER_BIE             (1 << 7)  /* Bit 7: Break interrupt enable (TIM15-17 only) */
+#define GTIM_DIER_UDE             (1 << 8)  /* Bit 8: Update DMA request enable (TIM2-5&15-17 only) */
+#define GTIM_DIER_CC1DE           (1 << 9)  /* Bit 9: Capture/Compare 1 DMA request enable (TIM2-5&15-17 only) */
+#define GTIM_DIER_CC2DE           (1 << 10) /* Bit 10: Capture/Compare 2 DMA request enable (TIM2-5&15 only) */
+#define GTIM_DIER_CC3DE           (1 << 11) /* Bit 11: Capture/Compare 3 DMA request enable (TIM2-5 only) */
+#define GTIM_DIER_CC4DE           (1 << 12) /* Bit 12: Capture/Compare 4 DMA request enable (TIM2-5 only) */
+#define GTIM_DIER_COMDE           (1 << 13) /* Bit 13: COM DMA request enable (TIM15-17 only) */
+#define GTIM_DIER_TDE             (1 << 14) /* Bit 14: Trigger DMA request enable (TIM2-5&15-17 only) */
+
+/* Status register */
+
+#define GTIM_SR_UIF               (1 << 0)  /* Bit 0: Update interrupt flag */
+#define GTIM_SR_CC1IF             (1 << 1)  /* Bit 1: Capture/compare 1 interrupt flag */
+#define GTIM_SR_CC2IF             (1 << 2)  /* Bit 2: Capture/Compare 2 interrupt flag (TIM2-5,9,12,&15 only) */
+#define GTIM_SR_CC3IF             (1 << 3)  /* Bit 3: Capture/Compare 3 interrupt flag (TIM2-5 only) */
+#define GTIM_SR_CC4IF             (1 << 4)  /* Bit 4: Capture/Compare 4 interrupt flag (TIM2-5 only) */
+#define GTIM_SR_COMIF             (1 << 5)  /* Bit 5: COM interrupt flag (TIM15-17 only) */
+#define GTIM_SR_TIF               (1 << 6)  /* Bit 6: Trigger interrupt Flag (TIM2-5,9,12&15-17 only) */
+#define GTIM_SR_BIF               (1 << 7)  /* Bit 7: Break interrupt flag (TIM15-17 only) */
+#define GTIM_SR_CC1OF             (1 << 9)  /* Bit 9: Capture/Compare 1 Overcapture flag */
+#define GTIM_SR_CC2OF             (1 << 10) /* Bit 10: Capture/Compare 2 Overcapture flag (TIM2-5,9,12&15 only) */
+#define GTIM_SR_CC3OF             (1 << 11) /* Bit 11: Capture/Compare 3 Overcapture flag (TIM2-5 only) */
+#define GTIM_SR_CC4OF             (1 << 12) /* Bit 12: Capture/Compare 4 Overcapture flag (TIM2-5 only) */
+
+/* Event generation register (TIM2-5 and TIM9-14) */
+
+#define GTIM_EGR_UG               (1 << 0)  /* Bit 0: Update generation */
+#define GTIM_EGR_CC1G             (1 << 1)  /* Bit 1: Capture/compare 1 generation */
+#define GTIM_EGR_CC2G             (1 << 2)  /* Bit 2: Capture/compare 2 generation (TIM2-5,9,12,&15 only) */
+#define GTIM_EGR_CC3G             (1 << 3)  /* Bit 3: Capture/compare 3 generation (TIM2-5 only) */
+#define GTIM_EGR_CC4G             (1 << 4)  /* Bit 4: Capture/compare 4 generation (TIM2-5 only) */
+#define GTIM_EGR_COMIG            (1 << 5)  /* Bit 5: Capture/Compare control update generation (TIM15-17 only) */
+#define GTIM_EGR_TG               (1 << 6)  /* Bit 6: Trigger generation (TIM2-5,9,12&16-17 only) */
+#define GTIM_EGR_BG               (1 << 7)  /* Bit 7: Break generation (TIM15-17 only) */
+
+/* Capture/compare mode register 1 - Output compare mode (TIM2-5 and TIM9-14) */
+
+#define GTIM_CCMR1_CC1S_SHIFT     (0)       /* Bits 1-0: Capture/Compare 1 Selection */
+#define GTIM_CCMR1_CC1S_MASK      (3 << GTIM_CCMR1_CC1S_SHIFT)
+                                            /* (See common CCMR Capture/Compare Selection definitions below) */
+#define GTIM_CCMR1_OC1FE          (1 << 2)  /* Bit 2: Output Compare 1 Fast enable */
+#define GTIM_CCMR1_OC1PE          (1 << 3)  /* Bit 3: Output Compare 1 Preload enable */
+#define GTIM_CCMR1_OC1M_SHIFT     (4)       /* Bits 6-4: Output Compare 1 Mode */
+#define GTIM_CCMR1_OC1M_MASK      (7 << GTIM_CCMR1_OC1M_SHIFT)
+                                            /* (See common CCMR Output Compare Mode definitions below) */
+#define GTIM_CCMR1_OC1CE          (1 << 7)  /* Bit 7: Output Compare 1Clear Enable */
+#define GTIM_CCMR1_CC2S_SHIFT     (8)       /* Bits 9-8: Capture/Compare 2 Selection */
+#define GTIM_CCMR1_CC2S_MASK      (3 << GTIM_CCMR1_CC2S_SHIFT)
+                                            /* (See common CCMR Capture/Compare Selection definitions below) */
+#define GTIM_CCMR1_OC2FE          (1 << 10) /* Bit 10: Output Compare 2 Fast enable */
+#define GTIM_CCMR1_OC2PE          (1 << 11) /* Bit 11: Output Compare 2 Preload enable */
+#define GTIM_CCMR1_OC2M_SHIFT     (12)      /* Bits 14-12: Output Compare 2 Mode */
+#define GTIM_CCMR1_OC2M_MASK      (7 << GTIM_CCMR1_OC2M_SHIFT)
+                                            /* (See common CCMR Output Compare Mode definitions below) */
+#define GTIM_CCMR1_OC2CE          (1 << 15) /* Bit 15: Output Compare 2 Clear Enable */
+#define GTIM_CCMR1_OC1M           (1 << 16) /* Bit 16: Output Compare 1 mode - bit 3 */
+#define GTIM_CCMR1_OC2M           (1 << 24) /* Bit 24: Output Compare 2 mode - bit 3 */
+
+/* Common CCMR (unshifted) Capture/Compare Selection bit-field definitions */
+
+#define GTIM_CCMR_CCS_CCOUT       (0)       /* 00: CCx channel output */
+#define GTIM_CCMR_CCS_CCIN1       (1)       /* 01: CCx channel input, ICx is TIx */
+#define GTIM_CCMR_CCS_CCIN2       (2)       /* 10: CCx channel input, ICx is TIy */
+#define GTIM_CCMR_CCS_CCINTRC     (3)       /* 11: CCx channel input, ICx is TRC */
+
+/* Common CCMR (unshifted) Compare Mode bit field definitions */
+
+#define GTIM_CCMR_MODE_FRZN       (0)       /* 000: Frozen */
+#define GTIM_CCMR_MODE_CHACT      (1)       /* 001: Channel x active on match */
+#define GTIM_CCMR_MODE_CHINACT    (2)       /* 010: Channel x inactive on match */
+#define GTIM_CCMR_MODE_OCREFTOG   (3)       /* 011: OCxREF toggle ATIM_CNT=ATIM_CCRx */
+#define GTIM_CCMR_MODE_OCREFLO    (4)       /* 100: OCxREF forced low */
+#define GTIM_CCMR_MODE_OCREFHI    (5)       /* 101: OCxREF forced high */
+#define GTIM_CCMR_MODE_PWM1       (6)       /* 110: PWM mode 1 */
+#define GTIM_CCMR_MODE_PWM2       (7)       /* 111: PWM mode 2 */
+
+/* Capture/compare mode register 1 - Input capture mode (TIM2-5 and TIM9-14) */
+
+                                            /* Bits 1-0 (Same as Output Compare Mode) */
+#define GTIM_CCMR1_IC1PSC_SHIFT   (2)       /* Bits 3-2: Input Capture 1 Prescaler */
+#define GTIM_CCMR1_IC1PSC_MASK    (3 << GTIM_CCMR1_IC1PSC_SHIFT)
+                                            /* (See common CCMR Input Capture Prescaler definitions below) */
+#define GTIM_CCMR1_IC1F_SHIFT     (4)       /* Bits 7-4: Input Capture 1 Filter */
+#define GTIM_CCMR1_IC1F_MASK      (0x0f << GTIM_CCMR1_IC1F_SHIFT)
+                                            /* (See common CCMR Input Capture Filter definitions below) */
+                                            /* Bits 9-8: (Same as Output Compare Mode) */
+#define GTIM_CCMR1_IC2PSC_SHIFT   (10)      /* Bits 11-10: Input Capture 2 Prescaler */
+#define GTIM_CCMR1_IC2PSC_MASK    (3 << GTIM_CCMR1_IC2PSC_SHIFT)
+                                            /* (See common CCMR Input Capture Prescaler definitions below) */
+#define GTIM_CCMR1_IC2F_SHIFT     (12)      /* Bits 15-12: Input Capture 2 Filter */
+#define GTIM_CCMR1_IC2F_MASK      (0x0f << GTIM_CCMR1_IC2F_SHIFT)
+                                            /* (See common CCMR Input Capture Filter definitions below) */
+
+/* Common CCMR (unshifted) Input Capture Prescaler bit-field definitions */
+
+#define GTIM_CCMR_ICPSC_NOPSC     (0)       /* 00: no prescaler, capture each edge */
+#define GTIM_CCMR_ICPSC_EVENTS2   (1)       /* 01: capture once every 2 events */
+#define GTIM_CCMR_ICPSC_EVENTS4   (2)       /* 10: capture once every 4 events */
+#define GTIM_CCMR_ICPSC_EVENTS8   (3)       /* 11: capture once every 8 events */
+
+/* Common CCMR (unshifted) Input Capture Filter bit-field definitions */
+
+#define GTIM_CCMR_ICF_NOFILT      (0)       /* 0000: No filter, sampling at fDTS */
+#define GTIM_CCMR_ICF_FCKINT2     (1)       /* 0001: fSAMPLING=fCK_INT, N=2 */
+#define GTIM_CCMR_ICF_FCKINT4     (2)       /* 0010: fSAMPLING=fCK_INT, N=4 */
+#define GTIM_CCMR_ICF_FCKINT8     (3)       /* 0011: fSAMPLING=fCK_INT, N=8 */
+#define GTIM_CCMR_ICF_FDTSd26     (4)       /* 0100: fSAMPLING=fDTS/2, N=6 */
+#define GTIM_CCMR_ICF_FDTSd28     (5)       /* 0101: fSAMPLING=fDTS/2, N=8 */
+#define GTIM_CCMR_ICF_FDTSd46     (6)       /* 0110: fSAMPLING=fDTS/4, N=6 */
+#define GTIM_CCMR_ICF_FDTSd48     (7)       /* 0111: fSAMPLING=fDTS/4, N=8 */
+#define GTIM_CCMR_ICF_FDTSd86     (8)       /* 1000: fSAMPLING=fDTS/8, N=6 */
+#define GTIM_CCMR_ICF_FDTSd88     (9)       /* 1001: fSAMPLING=fDTS/8, N=8 */
+#define GTIM_CCMR_ICF_FDTSd165    (10)      /* 1010: fSAMPLING=fDTS/16, N=5 */
+#define GTIM_CCMR_ICF_FDTSd166    (11)      /* 1011: fSAMPLING=fDTS/16, N=6 */
+#define GTIM_CCMR_ICF_FDTSd168    (12)      /* 1100: fSAMPLING=fDTS/16, N=8 */
+#define GTIM_CCMR_ICF_FDTSd325    (13)      /* 1101: fSAMPLING=fDTS/32, N=5 */
+#define GTIM_CCMR_ICF_FDTSd326    (14)      /* 1110: fSAMPLING=fDTS/32, N=6 */
+#define GTIM_CCMR_ICF_FDTSd328    (15)      /* 1111: fSAMPLING=fDTS/32, N=8 */
+
+/* Capture/compare mode register 2 - Output Compare mode (TIM2-5 only) */
+
+#define GTIM_CCMR2_CC3S_SHIFT     (0)       /* Bits 1-0: Capture/Compare 3 Selection */
+#define GTIM_CCMR2_CC3S_MASK      (3 << GTIM_CCMR2_CC3S_SHIFT)
+                                            /* (See common CCMR Capture/Compare Selection definitions above) */
+#define GTIM_CCMR2_OC3FE          (1 << 2)  /* Bit 2: Output Compare 3 Fast enable */
+#define GTIM_CCMR2_OC3PE          (1 << 3)  /* Bit 3: Output Compare 3 Preload enable */
+#define GTIM_CCMR2_OC3M_SHIFT     (4)       /* Bits 6-4: Output Compare 3 Mode */
+#define GTIM_CCMR2_OC3M_MASK      (7 << GTIM_CCMR2_OC3M_SHIFT)
+                                            /* (See common CCMR Output Compare Mode definitions above) */
+#define GTIM_CCMR2_OC3CE          (1 << 7)  /* Bit 7: Output Compare 3 Clear Enable */
+#define GTIM_CCMR2_CC4S_SHIFT     (8)       /* Bits 9-8: Capture/Compare 4 Selection */
+#define GTIM_CCMR2_CC4S_MASK      (3 << GTIM_CCMR2_CC4S_SHIFT)
+                                            /* (See common CCMR Capture/Compare Selection definitions above) */
+#define GTIM_CCMR2_OC4FE          (1 << 10) /* Bit 10: Output Compare 4 Fast enable */
+#define GTIM_CCMR2_OC4PE          (1 << 11) /* Bit 11: Output Compare 4 Preload enable */
+#define GTIM_CCMR2_OC4M_SHIFT     (12)      /* Bits 14-12: Output Compare 4 Mode */
+#define GTIM_CCMR2_OC4M_MASK      (7 << GTIM_CCMR2_OC4M_SHIFT)
+                                            /* (See common CCMR Output Compare Mode definitions above) */
+#define GTIM_CCMR2_OC4CE          (1 << 15) /* Bit 15: Output Compare 4 Clear Enable */
+
+/* Capture/compare mode register 2 - Input capture mode (TIM2-5 only) */
+
+                                            /* Bits 1-0 (Same as Output Compare Mode) */
+#define GTIM_CCMR2_IC3PSC_SHIFT   (2)       /* Bits 3-2: Input Capture 3 Prescaler */
+#define GTIM_CCMR2_IC3PSC_MASK    (3 << GTIM_CCMR2_IC3PSC_SHIFT)
+                                            /* (See common CCMR Input Capture Prescaler definitions below) */
+#define GTIM_CCMR2_IC3F_SHIFT     (4)       /* Bits 7-4: Input Capture 3 Filter */
+#define GTIM_CCMR2_IC3F_MASK      (0x0f << GTIM_CCMR2_IC3F_SHIFT)
+                                            /* (See common CCMR Input Capture Filter definitions below) */
+                                            /* Bits 9-8: (Same as Output Compare Mode) */
+#define GTIM_CCMR2_IC4PSC_SHIFT   (10)      /* Bits 11-10: Input Capture 4 Prescaler */
+#define GTIM_CCMR2_IC4PSC_MASK    (3 << GTIM_CCMR2_IC4PSC_SHIFT)
+                                            /* (See common CCMR Input Capture Prescaler definitions below) */
+#define GTIM_CCMR2_IC4F_SHIFT     (12)      /* Bits 15-12: Input Capture 4 Filter */
+#define GTIM_CCMR2_IC4F_MASK      (0x0f << GTIM_CCMR2_IC4F_SHIFT)
+                                            /* (See common CCMR Input Capture Filter definitions below) */
+
+/* Capture/compare enable register (TIM1 and TIM8, TIM2-5 and TIM9-14) */
+
+#define GTIM_CCER_CC1E            (1 << 0)  /* Bit 0: Capture/Compare 1 output enable */
+#define GTIM_CCER_CC1P            (1 << 1)  /* Bit 1: Capture/Compare 1 output polarity */
+#define GTIM_CCER_CC1NE           (1 << 2)  /* Bit 2: Capture/Compare 1 complementary output enable (TIM1 and TIM8 only) */
+#define GTIM_CCER_CC1NP           (1 << 3)  /* Bit 3: Capture/Compare 1 output Polarity (F2,F3,F4 and TIM15-17) */
+#define GTIM_CCER_CC2E            (1 << 4)  /* Bit 4: Capture/Compare 2 output enable (TIM2-5,9&12 only) */
+#define GTIM_CCER_CC2P            (1 << 5)  /* Bit 5: Capture/Compare 2 output polarity (TIM2-5,9&12 only) */
+#define GTIM_CCER_CC2NE           (1 << 6)  /* Bit 6: Capture/Compare 2 complementary output enable (TIM1 and TIM8 only) */
+#define GTIM_CCER_CC2NP           (1 << 7)  /* Bit 7: Capture/Compare 2 output Polarity (F2,F3,F4 and TIM2-5,9,12&15 only) */
+#define GTIM_CCER_CC3E            (1 << 8)  /* Bit 8: Capture/Compare 3 output enable (TIM2-5 only) */
+#define GTIM_CCER_CC3P            (1 << 9)  /* Bit 9: Capture/Compare 3 output Polarity (TIM2-5 only) */
+#define GTIM_CCER_CC3NE           (1 << 10) /* Bit 10: Capture/Compare 3 complementary output enable (TIM1 and TIM8 only) */
+#define GTIM_CCER_CC3NP           (1 << 11) /* Bit 11: Capture/Compare 3 output Polarity (F2,F4 and TIM2-5 only) */
+#define GTIM_CCER_CC4E            (1 << 12) /* Bit 12: Capture/Compare 4 output enable (TIM2-5 only) */
+#define GTIM_CCER_CC4P            (1 << 13) /* Bit 13: Capture/Compare 4 output Polarity (TIM2-5 only) */
+#define GTIM_CCER_CC4NP           (1 << 15) /* Bit 15: Capture/Compare 4 output Polarity */
+
+/* 16-bit counter register */
+
+#define GTIM_CNT_SHIFT            (0)       /* Bits 0-15: Timer counter value */
+#define GTIM_CNT_MASK             (0xffff << ATIM_CNT_SHIFT)
+
+/* DMA control register */
+
+#define GTIM_DCR_DBA_SHIFT        (0)       /* Bits 4-0: DMA Base Address */
+#define GTIM_DCR_DBA_MASK         (0x1f << GTIM_DCR_DBA_SHIFT)
+#define GTIM_DCR_DBL_SHIFT        (8)       /* Bits 12-8: DMA Burst Length */
+#define GTIM_DCR_DBL_MASK         (0x1f << GTIM_DCR_DBL_SHIFT)
+
+/* Timer 2/5 option register */
+
+#define TIM2_OR_ITR1_RMP_SHIFT    (10)     /* Bits 10-11: Internal trigger 1 remap */
+#define TIM2_OR_ITR1_RMP_MASK     (3 << TIM2_OR_ITR1_RMP_SHIFT)
+#  define TIM2_OR_ITR1_TIM8_TRGOUT (0 << TIM2_OR_ITR1_RMP_SHIFT) /* 00: TIM2_ITR1 input connected to TIM8_TRGOUT */
+#  define TIM2_OR_ITR1_PTP        (1 << TIM2_OR_ITR1_RMP_SHIFT) /* 01: TIM2_ITR1 input connected to PTP trigger output */
+#  define TIM2_OR_ITR1_OTGFSSOF   (2 << TIM2_OR_ITR1_RMP_SHIFT) /* 10: TIM2_ITR1 input connected to OTG FS SOF */
+#  define TIM2_OR_ITR1_OTGHSSOF   (3 << TIM2_OR_ITR1_RMP_SHIFT) /* 11: TIM2_ITR1 input connected to OTG HS SOF */
+
+#define TIM5_OR_TI4_RMP_SHIFT     (6)     /* Bits 6-7: Internal trigger 4 remap */
+#define TIM5_OR_TI4_RMP_MASK      (3 << TIM5_OR_TI4_RMP_SHIFT)
+#  define TIM5_OR_TI4_GPIO        (0 << TIM5_OR_TI4_RMP_SHIFT) /* 00: TIM5_CH4 input connected to GPIO */
+#  define TIM5_OR_TI4_LSI         (1 << TIM5_OR_TI4_RMP_SHIFT) /* 01: TIM5_CH4 input connected to LSI internal clock */
+#  define TIM5_OR_TI4_LSE         (2 << TIM5_OR_TI4_RMP_SHIFT) /* 10: TIM5_CH4 input connected to LSE internal clock */
+#  define TIM5_OR_TI4_RTC         (3 << TIM5_OR_TI4_RMP_SHIFT) /* 11: TIM5_CH4 input connected to RTC output event */
+
+#define TIM11_OR_TI1_RMP_SHIFT    (6)     /* Bits 6-7: Internal trigger 4 remap */
+#define TIM11_OR_TI1_RMP_MASK     (3 << TIM11_OR_TI1_RMP_SHIFT)
+#  define TIM11_OR_TI1_GPIO       (0 << TIM11_OR_TI1_RMP_SHIFT) /* 00-11: TIM11_CH1 input connected to GPIO */
+#  define TIM11_OR_TI1_HSERTC     (3 << TIM11_OR_TI1_RMP_SHIFT) /* 11: TIM11_CH1 input connected to HSE_RTC clock */
+
+
+/* Control register 1 */
+
+#define BTIM_CR1_CEN              (1 << 0)  /* Bit 0: Counter enable */
+#define BTIM_CR1_UDIS             (1 << 1)  /* Bit 1: Update Disable */
+#define BTIM_CR1_URS              (1 << 2)  /* Bit 2: Update Request Source */
+#define BTIM_CR1_OPM              (1 << 3)  /* Bit 3: One Pulse Mode */
+#define BTIM_CR1_ARPE             (1 << 7)  /* Bit 7: Auto-Reload Preload enable */
+
+/* Control register 2 */
+
+#define BTIM_CR2_MMS_SHIFT        (4)       /* Bits 6-4: Master Mode Selection */
+#define BTIM_CR2_MMS_MASK         (7 << BTIM_CR2_MMS_SHIFT)
+#  define BTIM_CR2_RESET          (0 << BTIM_CR2_MMS_SHIFT) /* 000: Reset */
+#  define BTIM_CR2_ENAB           (1 << BTIM_CR2_MMS_SHIFT) /* 001: Enable */
+#  define BTIM_CR2_UPDT           (2 << BTIM_CR2_MMS_SHIFT) /* 010: Update */
+
+/* DMA/Interrupt enable register */
+
+#define BTIM_DIER_UIE             (1 << 0)  /* Bit 0: Update interrupt enable */
+#define BTIM_DIER_UDE             (1 << 8)  /* Bit 8: Update DMA request enable */
+
+/* Status register */
+
+#define BTIM_SR_UIF               (1 << 0)  /* Bit 0: Update interrupt flag */
+
+/* Event generation register */
+
+#define BTIM_EGR_UG               (1 << 0)  /* Bit 0: Update generation */
+
+#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F76XX77XX_TIM_H */
diff --git a/arch/arm/src/stm32f7/stm32_adc.c b/arch/arm/src/stm32f7/stm32_adc.c
index 89c4f03b1fb..df9232048e8 100644
--- a/arch/arm/src/stm32f7/stm32_adc.c
+++ b/arch/arm/src/stm32f7/stm32_adc.c
@@ -6,6 +6,7 @@
  *   Authors: Gregory Nutt <gnutt@nuttx.org>
  *            Diego Sanchez <dsanchez@nx-engineering.com>
  *            Paul Alexander Patience <paul-a.patience@polymtl.ca>
+ *            David Sidrane <david_s5@nscdg.com>
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -42,8 +43,10 @@
 
 #include <nuttx/config.h>
 
-#include <stdio.h>
 #include <sys/types.h>
+#include <sys/ioctl.h>
+
+#include <stdio.h>
 #include <stdint.h>
 #include <stdbool.h>
 #include <unistd.h>
@@ -58,11 +61,14 @@
 #include <nuttx/irq.h>
 #include <nuttx/arch.h>
 #include <nuttx/analog/adc.h>
+#include <nuttx/fs/ioctl.h>
 
 #include "up_internal.h"
 #include "up_arch.h"
 
 #include "chip.h"
+#include "stm32_rcc.h"
+#include "stm32_tim.h"
 #include "stm32_dma.h"
 #include "stm32_adc.h"
 
@@ -75,9 +81,10 @@
 #if defined(CONFIG_STM32F7_ADC1) || defined(CONFIG_STM32F7_ADC2) || \
     defined(CONFIG_STM32F7_ADC3)
 
-/* This implementation is for the STM32 F7 only */
+/* This implementation is for the STM32 F7[4-7] only */
 
-#if defined(CONFIG_STM32F7_STM32F74XX)
+#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \
+    defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
 
 /****************************************************************************
  * Pre-processor Definitions
@@ -158,6 +165,26 @@
                                (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP8_SHIFT) | \
                                (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP9_SHIFT))
 
+/* The last external channel on ADC 1 to enable Reading Vref or Vbat / Vsence */
+
+#define ADC_LAST_EXTERNAL_CHAN 15
+
+/* Assuming VDC 2.4 - 3.6 */
+
+#define ADC_MAX_FADC 36000000
+
+#if STM32_PCLK2_FREQUENCY/2 <= ADC_MAX_FADC
+# define ADC_CCR_ADCPRE_DIV     ADC_CCR_ADCPRE_DIV2
+#elif STM32_PCLK2_FREQUENCY/4 <= ADC_MAX_FADC
+# define ADC_CCR_ADCPRE_DIV     ADC_CCR_ADCPRE_DIV4
+#elif STM32_PCLK2_FREQUENCY/6 <= ADC_MAX_FADC
+# define ADC_CCR_ADCPRE_DIV     ADC_CCR_ADCPRE_DIV6
+#elif STM32_PCLK2_FREQUENCY/8 <= ADC_MAX_FADC
+# define ADC_CCR_ADCPRE_DIV     ADC_CCR_ADCPRE_DIV8
+#else
+# error "PCLK2 too high - no divisor found "
+#endif
+
 /****************************************************************************
  * Private Types
  ****************************************************************************/
@@ -166,6 +193,7 @@
 
 struct stm32_dev_s
 {
+  FAR const struct adc_callback_s *cb;
   uint8_t irq;          /* Interrupt generated by this ADC block */
   uint8_t nchannels;    /* Number of channels */
   uint8_t cchannels;    /* Number of configured channels */
@@ -227,11 +255,14 @@ static void     tim_dumpregs(FAR struct stm32_dev_s *priv,
 static void adc_rccreset(FAR struct stm32_dev_s *priv, bool reset);
 
 /* ADC Interrupt Handler */
+
 static int adc_interrupt(FAR struct adc_dev_s *dev);
 static int adc123_interrupt(int irq, FAR void *context);
 
 /* ADC Driver Methods */
 
+static int  adc_bind(FAR struct adc_dev_s *dev,
+                     FAR const struct adc_callback_s *callback);
 static void adc_reset(FAR struct adc_dev_s *dev);
 static int  adc_setup(FAR struct adc_dev_s *dev);
 static void adc_shutdown(FAR struct adc_dev_s *dev);
@@ -242,6 +273,7 @@ static void adc_enable(FAR struct stm32_dev_s *priv, bool enable);
 static uint32_t adc_sqrbits(FAR struct stm32_dev_s *priv, int first, int last,
                             int offset);
 static int      adc_set_ch(FAR struct adc_dev_s *dev, uint8_t ch);
+static bool     adc_internal(FAR struct stm32_dev_s * priv);
 
 #ifdef ADC_HAVE_TIMER
 static void adc_timstart(FAR struct stm32_dev_s *priv, bool enable);
@@ -263,6 +295,7 @@ static void adc_startconv(FAR struct stm32_dev_s *priv, bool enable);
 
 static const struct adc_ops_s g_adcops =
 {
+  .ao_bind        = adc_bind,
   .ao_reset       = adc_reset,
   .ao_setup       = adc_setup,
   .ao_shutdown    = adc_shutdown,
@@ -536,29 +569,29 @@ static void tim_modifyreg(FAR struct stm32_dev_s *priv, int offset,
 #ifdef ADC_HAVE_TIMER
 static void tim_dumpregs(FAR struct stm32_dev_s *priv, FAR const char *msg)
 {
-  avdbg("%s:\n", msg);
-  avdbg("  CR1: %04x CR2:  %04x SMCR:  %04x DIER:  %04x\n",
+  ainfo("%s:\n", msg);
+  ainfo("  CR1: %04x CR2:  %04x SMCR:  %04x DIER:  %04x\n",
         tim_getreg(priv, STM32_GTIM_CR1_OFFSET),
         tim_getreg(priv, STM32_GTIM_CR2_OFFSET),
         tim_getreg(priv, STM32_GTIM_SMCR_OFFSET),
         tim_getreg(priv, STM32_GTIM_DIER_OFFSET));
-  avdbg("   SR: %04x EGR:  0000 CCMR1: %04x CCMR2: %04x\n",
+  ainfo("   SR: %04x EGR:  0000 CCMR1: %04x CCMR2: %04x\n",
         tim_getreg(priv, STM32_GTIM_SR_OFFSET),
         tim_getreg(priv, STM32_GTIM_CCMR1_OFFSET),
         tim_getreg(priv, STM32_GTIM_CCMR2_OFFSET));
-  avdbg(" CCER: %04x CNT:  %04x PSC:   %04x ARR:   %04x\n",
+  ainfo(" CCER: %04x CNT:  %04x PSC:   %04x ARR:   %04x\n",
         tim_getreg(priv, STM32_GTIM_CCER_OFFSET),
         tim_getreg(priv, STM32_GTIM_CNT_OFFSET),
         tim_getreg(priv, STM32_GTIM_PSC_OFFSET),
         tim_getreg(priv, STM32_GTIM_ARR_OFFSET));
-  avdbg(" CCR1: %04x CCR2: %04x CCR3:  %04x CCR4:  %04x\n",
+  ainfo(" CCR1: %04x CCR2: %04x CCR3:  %04x CCR4:  %04x\n",
         tim_getreg(priv, STM32_GTIM_CCR1_OFFSET),
         tim_getreg(priv, STM32_GTIM_CCR2_OFFSET),
         tim_getreg(priv, STM32_GTIM_CCR3_OFFSET),
         tim_getreg(priv, STM32_GTIM_CCR4_OFFSET));
   if (priv->tbase == STM32_TIM1_BASE || priv->tbase == STM32_TIM8_BASE)
     {
-      avdbg("  RCR: %04x BDTR: %04x DCR:   %04x DMAR:  %04x\n",
+      ainfo("  RCR: %04x BDTR: %04x DCR:   %04x DMAR:  %04x\n",
             tim_getreg(priv, STM32_ATIM_RCR_OFFSET),
             tim_getreg(priv, STM32_ATIM_BDTR_OFFSET),
             tim_getreg(priv, STM32_ATIM_DCR_OFFSET),
@@ -566,7 +599,7 @@ static void tim_dumpregs(FAR struct stm32_dev_s *priv, FAR const char *msg)
     }
   else
     {
-      avdbg("  DCR: %04x DMAR: %04x\n",
+      ainfo("  DCR: %04x DMAR: %04x\n",
             tim_getreg(priv, STM32_GTIM_DCR_OFFSET),
             tim_getreg(priv, STM32_GTIM_DMAR_OFFSET));
     }
@@ -590,7 +623,7 @@ static void tim_dumpregs(FAR struct stm32_dev_s *priv, FAR const char *msg)
 #ifdef ADC_HAVE_TIMER
 static void adc_timstart(FAR struct stm32_dev_s *priv, bool enable)
 {
-  avdbg("enable: %d\n", enable ? 1 : 0);
+  ainfo("enable: %d\n", enable ? 1 : 0);
 
   if (enable)
     {
@@ -659,7 +692,7 @@ static int adc_timinit(FAR struct stm32_dev_s *priv)
    *   position.
    */
 
-  avdbg("Initializing timers extsel = 0x%08x\n", priv->extsel);
+  ainfo("Initializing timers extsel = 0x%08x\n", priv->extsel);
 
   adc_modifyreg(priv, STM32_ADC_EXTREG_OFFSET,
                 ADC_EXTREG_EXTEN_MASK | ADC_EXTREG_EXTSEL_MASK,
@@ -692,7 +725,7 @@ static int adc_timinit(FAR struct stm32_dev_s *priv)
 
   if (prescaler < 1)
     {
-      adbg("WARNING: Prescaler underflowed.\n");
+      awarn("WARNING: Prescaler underflowed.\n");
       prescaler = 1;
     }
 
@@ -700,7 +733,7 @@ static int adc_timinit(FAR struct stm32_dev_s *priv)
 
   else if (prescaler > 65536)
     {
-      adbg("WARNING: Prescaler overflowed.\n");
+      awarn("WARNING: Prescaler overflowed.\n");
       prescaler = 65536;
     }
 
@@ -709,12 +742,12 @@ static int adc_timinit(FAR struct stm32_dev_s *priv)
   reload = timclk / priv->freq;
   if (reload < 1)
     {
-      adbg("WARNING: Reload value underflowed.\n");
+      awarn("WARNING: Reload value underflowed.\n");
       reload = 1;
     }
   else if (reload > 65535)
     {
-      adbg("WARNING: Reload value overflowed.\n");
+      awarn("WARNING: Reload value overflowed.\n");
       reload = 65535;
     }
 
@@ -854,7 +887,7 @@ static int adc_timinit(FAR struct stm32_dev_s *priv)
         break;
 
       default:
-        adbg("No such trigger: %d\n", priv->trigger);
+        aerr("ERROR: No such trigger: %d\n", priv->trigger);
         return -EINVAL;
     }
 
@@ -955,7 +988,7 @@ static int adc_timinit(FAR struct stm32_dev_s *priv)
 
 static void adc_startconv(FAR struct stm32_dev_s *priv, bool enable)
 {
-  avdbg("enable: %d\n", enable ? 1 : 0);
+  ainfo("enable: %d\n", enable ? 1 : 0);
 
   if (enable)
     {
@@ -1054,19 +1087,14 @@ static void adc_rccreset(FAR struct stm32_dev_s *priv, bool reset)
 
 static void adc_enable(FAR struct stm32_dev_s *priv, bool enable)
 {
-#ifdef ADC_SR_ADONS
-  bool enabled = (adc_getreg(priv, STM32_ADC_SR_OFFSET) & ADC_SR_ADONS) != 0;
-#else
-  bool enabled = false;
-#endif
 
-  avdbg("enable: %d\n", enable ? 1 : 0);
+  ainfo("enable: %d\n", enable ? 1 : 0);
 
-  if (!enabled && enable)
+  if (enable)
     {
       adc_modifyreg(priv, STM32_ADC_CR2_OFFSET, 0, ADC_CR2_ADON);
     }
-  else if (enabled && !enable)
+  else
     {
       adc_modifyreg(priv, STM32_ADC_CR2_OFFSET, ADC_CR2_ADON, 0);
     }
@@ -1096,18 +1124,24 @@ static void adc_dmaconvcallback(DMA_HANDLE handle, uint8_t isr, FAR void *arg)
   FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv;
   int i;
 
-  for (i = 0; i < priv->nchannels; i++)
-    {
-      adc_receive(dev, priv->current, priv->dmabuffer[priv->current]);
-      priv->current++;
-      if (priv->current >= priv->nchannels)
-        {
-          /* Restart the conversion sequence from the beginning */
+  /* Verify that the upper-half driver has bound its callback functions */
 
-          priv->current = 0;
+  if (priv->cb != NULL)
+    {
+      DEBUGASSERT(priv->cb->au_receive != NULL);
+
+      for (i = 0; i < priv->nchannels; i++)
+        {
+          priv->cb->au_receive(dev, priv->current, priv->dmabuffer[priv->current]);
+          priv->current++;
+          if (priv->current >= priv->nchannels)
+            {
+              /* Restart the conversion sequence from the beginning */
+
+              priv->current = 0;
+            }
         }
     }
-
   /* Restart DMA for the next conversion series */
 
   adc_modifyreg(priv, STM32_ADC_DMAREG_OFFSET, ADC_DMAREG_DMA, 0);
@@ -1115,6 +1149,25 @@ static void adc_dmaconvcallback(DMA_HANDLE handle, uint8_t isr, FAR void *arg)
 }
 #endif
 
+/****************************************************************************
+ * Name: adc_bind
+ *
+ * Description:
+ *   Bind the upper-half driver callbacks to the lower-half implementation.  This
+ *   must be called early in order to receive ADC event notifications.
+ *
+ ****************************************************************************/
+
+static int adc_bind(FAR struct adc_dev_s *dev,
+                    FAR const struct adc_callback_s *callback)
+{
+  FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv;
+
+  DEBUGASSERT(priv != NULL);
+  priv->cb = callback;
+  return OK;
+}
+
 /****************************************************************************
  * Name: adc_reset
  *
@@ -1138,7 +1191,7 @@ static void adc_reset(FAR struct adc_dev_s *dev)
   int ret;
 #endif
 
-  allvdbg("intf: %d\n", priv->intf);
+  ainfo("intf: %d\n", priv->intf);
   flags = enter_critical_section();
 
   /* Enable ADC reset state */
@@ -1218,7 +1271,12 @@ static void adc_reset(FAR struct adc_dev_s *dev)
   /* ADC CCR configuration */
 
   clrbits  = ADC_CCR_ADCPRE_MASK | ADC_CCR_TSVREFE;
-  setbits  = ADC_CCR_ADCPRE_DIV2;
+  setbits  = ADC_CCR_ADCPRE_DIV;
+
+  if (adc_internal(priv))
+    {
+      setbits  = ADC_CCR_TSVREFE;
+    }
 
   clrbits |= ADC_CCR_MULTI_MASK | ADC_CCR_DELAY_MASK | ADC_CCR_DDS |
              ADC_CCR_DMA_MASK | ADC_CCR_VBATE;
@@ -1263,7 +1321,7 @@ static void adc_reset(FAR struct adc_dev_s *dev)
       ret = adc_timinit(priv);
       if (ret < 0)
         {
-          adbg("adc_timinit failed: %d\n", ret);
+          aerr("ERROR: adc_timinit failed: %d\n", ret);
         }
     }
 #ifndef CONFIG_ADC_NO_STARTUP_CONV
@@ -1278,17 +1336,17 @@ static void adc_reset(FAR struct adc_dev_s *dev)
 
   leave_critical_section(flags);
 
-  avdbg("SR:   0x%08x CR1:  0x%08x CR2:  0x%08x\n",
+  ainfo("SR:   0x%08x CR1:  0x%08x CR2:  0x%08x\n",
         adc_getreg(priv, STM32_ADC_SR_OFFSET),
         adc_getreg(priv, STM32_ADC_CR1_OFFSET),
         adc_getreg(priv, STM32_ADC_CR2_OFFSET));
   
-  avdbg("SQR1: 0x%08x SQR2: 0x%08x SQR3: 0x%08x\n",
+  ainfo("SQR1: 0x%08x SQR2: 0x%08x SQR3: 0x%08x\n",
         adc_getreg(priv, STM32_ADC_SQR1_OFFSET),
         adc_getreg(priv, STM32_ADC_SQR2_OFFSET),
         adc_getreg(priv, STM32_ADC_SQR3_OFFSET));
 
-  avdbg("CCR:  0x%08x\n", getreg32(STM32_ADC_CCR));
+  ainfo("CCR:  0x%08x\n", getreg32(STM32_ADC_CCR));
 
 }
 
@@ -1317,7 +1375,7 @@ static int adc_setup(FAR struct adc_dev_s *dev)
   ret = irq_attach(priv->irq, priv->isr);
   if (ret < 0)
     {
-      avdbg("irq_attach failed: %d\n", ret);
+      ainfo("irq_attach failed: %d\n", ret);
       return ret;
     }
 
@@ -1327,7 +1385,7 @@ static int adc_setup(FAR struct adc_dev_s *dev)
 
   /* Enable the ADC interrupt */
 
-  avdbg("Enable the ADC interrupt: irq=%d\n", priv->irq);
+  ainfo("Enable the ADC interrupt: irq=%d\n", priv->irq);
   up_enable_irq(priv->irq);
 
   return ret;
@@ -1378,7 +1436,7 @@ static void adc_rxint(FAR struct adc_dev_s *dev, bool enable)
 {
   FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv;
 
-  avdbg("intf: %d enable: %d\n", priv->intf, enable ? 1 : 0);
+  ainfo("intf: %d enable: %d\n", priv->intf, enable ? 1 : 0);
 
   if (enable)
     {
@@ -1414,6 +1472,29 @@ static uint32_t adc_sqrbits(FAR struct stm32_dev_s *priv, int first, int last,
   return bits;
 }
 
+/****************************************************************************
+ * Name: adc_internal
+ ****************************************************************************/
+
+static bool adc_internal(FAR struct stm32_dev_s * priv)
+{
+  int i;
+
+  if (priv->intf == 1)
+    {
+      for (i  = 0; i < priv->nchannels; i++)
+        {
+          if (priv->chanlist[i] > ADC_LAST_EXTERNAL_CHAN)
+            {
+              return true;
+            }
+
+        }
+    }
+
+  return false;
+}
+
 /****************************************************************************
  * Name: adc_set_ch
  *
@@ -1453,16 +1534,6 @@ static int adc_set_ch(FAR struct adc_dev_s *dev, uint8_t ch)
       priv->nchannels = 1;
     }
 
-#ifdef STM32_ADC_SQR5_OFFSET
-  bits = adc_sqrbits(priv, ADC_SQR5_FIRST, ADC_SQR5_LAST, ADC_SQR5_SQ_OFFSET);
-  adc_modifyreg(priv, STM32_ADC_SQR5_OFFSET, ~ADC_SQR5_RESERVED, bits);
-#endif
-
-#ifdef STM32_ADC_SQR4_OFFSET
-  bits = adc_sqrbits(priv, ADC_SQR4_FIRST, ADC_SQR4_LAST, ADC_SQR4_SQ_OFFSET);
-  adc_modifyreg(priv, STM32_ADC_SQR4_OFFSET, ~ADC_SQR4_RESERVED, bits);
-#endif
-
   bits = adc_sqrbits(priv, ADC_SQR3_FIRST, ADC_SQR3_LAST, ADC_SQR3_SQ_OFFSET);
   adc_modifyreg(priv, STM32_ADC_SQR3_OFFSET, ~ADC_SQR3_RESERVED, bits);
 
@@ -1503,7 +1574,7 @@ static int adc_ioctl(FAR struct adc_dev_s *dev, int cmd, unsigned long arg)
         break;
 
       default:
-        adbg("ERROR: Unknown cmd: %d\n", cmd);
+        aerr("ERROR: Unknown cmd: %d\n", cmd);
         ret = -ENOTTY;
         break;
     }
@@ -1541,12 +1612,12 @@ static int adc_interrupt(FAR struct adc_dev_s *dev)
 
   if ((regval & ADC_ISR_AWD) != 0)
     {
-      alldbg("WARNING: Analog Watchdog, Value converted out of range!\n");
+      awarn("WARNING: Analog Watchdog, Value converted out of range!\n");
     }
 
   if ((regval & ADC_ISR_OVR) != 0)
     {
-      alldbg("WARNING: Overrun has occurred!\n");
+      awarn("WARNING: Overrun has occurred!\n");
     }
 
   /* EOC: End of conversion */
@@ -1559,15 +1630,21 @@ static int adc_interrupt(FAR struct adc_dev_s *dev)
 
       data = adc_getreg(priv, STM32_ADC_DR_OFFSET) & ADC_DR_RDATA_MASK;
 
-      /* Give the ADC data to the ADC driver.  adc_receive() accepts 3
-       * parameters:
-       *
-       * 1) The first is the ADC device instance for this ADC block.
-       * 2) The second is the channel number for the data, and
-       * 3) The third is the converted data for the channel.
-       */
+      /* Verify that the upper-half driver has bound its callback functions */
 
-      adc_receive(dev, priv->chanlist[priv->current], data);
+      if (priv->cb != NULL)
+        {
+          /* Give the ADC data to the ADC driver.  The ADC receive() method
+           * accepts 3 parameters:
+           *
+           * 1) The first is the ADC device instance for this ADC block.
+           * 2) The second is the channel number for the data, and
+           * 3) The third is the converted data for the channel.
+           */
+
+          DEBUGASSERT(priv->cb->au_receive != NULL);
+          priv->cb->au_receive(dev, priv->chanlist[priv->current], data);
+        }
 
       /* Set the channel number of the next channel that will complete
        * conversion.
@@ -1653,38 +1730,43 @@ struct adc_dev_s *stm32_adc_initialize(int intf, FAR const uint8_t *chanlist,
   FAR struct adc_dev_s   *dev;
   FAR struct stm32_dev_s *priv;
 
-  avdbg("intf: %d cchannels: %d\n", intf, cchannels);
+  ainfo("intf: %d cchannels: %d\n", intf, cchannels);
 
   switch (intf)
     {
 #ifdef CONFIG_STM32F7_ADC1
       case 1:
-        avdbg("ADC1 selected\n");
+        ainfo("ADC1 selected\n");
         dev = &g_adcdev1;
         break;
 #endif
 #ifdef CONFIG_STM32F7_ADC2
       case 2:
-        avdbg("ADC2 selected\n");
+        ainfo("ADC2 selected\n");
         dev = &g_adcdev2;
         break;
 #endif
 #ifdef CONFIG_STM32F7_ADC3
       case 3:
-        avdbg("ADC3 selected\n");
+        ainfo("ADC3 selected\n");
         dev = &g_adcdev3;
         break;
 #endif
       default:
-        adbg("No ADC interface defined\n");
+        aerr("ERROR: No ADC interface defined\n");
         return NULL;
     }
 
   /* Configure the selected ADC */
 
-  priv = (FAR struct stm32_dev_s *)dev->ad_priv;
+  priv     = (FAR struct stm32_dev_s *)dev->ad_priv;
+  priv->cb = NULL;
 
   DEBUGASSERT(cchannels <= ADC_MAX_SAMPLES);
+  if (cchannels > ADC_MAX_SAMPLES)
+    {
+      cchannels = ADC_MAX_SAMPLES;
+    }
 
   priv->cchannels = cchannels;
 
diff --git a/arch/arm/src/stm32f7/stm32_adc.h b/arch/arm/src/stm32f7/stm32_adc.h
index 89dd750d804..f07afe42db4 100644
--- a/arch/arm/src/stm32f7/stm32_adc.h
+++ b/arch/arm/src/stm32f7/stm32_adc.h
@@ -5,6 +5,7 @@
  *   Copyright (C) 2015 Omni Hoverboards Inc. All rights reserved.
  *   Authors: Gregory Nutt <gnutt@nuttx.org>
  *            Paul Alexander Patience <paul-a.patience@polymtl.ca>
+ *            David Sidrane <david_s5@nscdg.com>
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -103,19 +104,15 @@
 
 /* Up to 3 ADC interfaces are supported */
 
-#if STM32_NADC < 4
-#  undef CONFIG_STM32F7_ADC4
-#endif
-
-#if STM32_NADC < 3
+#if STM32F7_NADC < 3
 #  undef CONFIG_STM32F7_ADC3
 #endif
 
-#if STM32_NADC < 2
+#if STM32F7_NADC < 2
 #  undef CONFIG_STM32F7_ADC2
 #endif
 
-#if STM32_NADC < 1
+#if STM32F7_NADC < 1
 #  undef CONFIG_STM32F7_ADC1
 #endif
 
@@ -758,7 +755,7 @@ extern "C"
  ****************************************************************************/
 
 struct adc_dev_s;
-struct adc_dev_s *stm32_adc_initialiize(int intf,
+struct adc_dev_s *stm32_adc_initialize(int intf,
                                         FAR const uint8_t *chanlist,
                                         int nchannels);
 #undef EXTERN
diff --git a/arch/arm/src/stm32f7/stm32_ethernet.c b/arch/arm/src/stm32f7/stm32_ethernet.c
index 6129d3e75f4..74d7721ed60 100644
--- a/arch/arm/src/stm32f7/stm32_ethernet.c
+++ b/arch/arm/src/stm32f7/stm32_ethernet.c
@@ -1060,8 +1060,8 @@ static int stm32_transmit(struct stm32_ethmac_s *priv)
   txdesc  = priv->txhead;
   txfirst = txdesc;
 
-  nllinfo("d_len: %d d_buf: %p txhead: %p tdes0: %08x\n",
-          priv->dev.d_len, priv->dev.d_buf, txdesc, txdesc->tdes0);
+  ninfo("d_len: %d d_buf: %p txhead: %p tdes0: %08x\n",
+        priv->dev.d_len, priv->dev.d_buf, txdesc, txdesc->tdes0);
 
   DEBUGASSERT(txdesc && (txdesc->tdes0 & ETH_TDES0_OWN) == 0);
 
@@ -1082,7 +1082,7 @@ static int stm32_transmit(struct stm32_ethmac_s *priv)
       bufcount = (priv->dev.d_len + (ALIGNED_BUFSIZE-1)) / ALIGNED_BUFSIZE;
       lastsize = priv->dev.d_len - (bufcount - 1) * ALIGNED_BUFSIZE;
 
-      nllinfo("bufcount: %d lastsize: %d\n", bufcount, lastsize);
+      ninfo("bufcount: %d lastsize: %d\n", bufcount, lastsize);
 
       /* Set the first segment bit in the first TX descriptor */
 
@@ -1209,8 +1209,8 @@ static int stm32_transmit(struct stm32_ethmac_s *priv)
 
   priv->inflight++;
 
-  nllinfo("txhead: %p txtail: %p inflight: %d\n",
-          priv->txhead, priv->txtail, priv->inflight);
+  ninfo("txhead: %p txtail: %p inflight: %d\n",
+        priv->txhead, priv->txtail, priv->inflight);
 
   /* If all TX descriptors are in-flight, then we have to disable receive interrupts
    * too.  This is because receive events can trigger more un-stoppable transmit
@@ -1508,7 +1508,7 @@ static void stm32_freesegment(struct stm32_ethmac_s *priv,
   struct eth_rxdesc_s *rxdesc;
   int i;
 
-  nllinfo("rxfirst: %p segments: %d\n", rxfirst, segments);
+  ninfo("rxfirst: %p segments: %d\n", rxfirst, segments);
 
   /* Give the freed RX buffers back to the Ethernet MAC to be refilled */
 
@@ -1580,8 +1580,8 @@ static int stm32_recvframe(struct stm32_ethmac_s *priv)
   uint8_t *buffer;
   int i;
 
-  nllinfo("rxhead: %p rxcurr: %p segments: %d\n",
-          priv->rxhead, priv->rxcurr, priv->segments);
+  ninfo("rxhead: %p rxcurr: %p segments: %d\n",
+        priv->rxhead, priv->rxcurr, priv->segments);
 
   /* Check if there are free buffers.  We cannot receive new frames in this
    * design unless there is at least one free buffer.
@@ -1589,7 +1589,7 @@ static int stm32_recvframe(struct stm32_ethmac_s *priv)
 
   if (!stm32_isfreebuffer(priv))
     {
-      nllerr("ERROR: No free buffers\n");
+      nerr("ERROR: No free buffers\n");
       return -ENOMEM;
     }
 
@@ -1652,7 +1652,7 @@ static int stm32_recvframe(struct stm32_ethmac_s *priv)
               rxcurr = priv->rxcurr;
             }
 
-          nllinfo("rxhead: %p rxcurr: %p segments: %d\n",
+          ninfo("rxhead: %p rxcurr: %p segments: %d\n",
               priv->rxhead, priv->rxcurr, priv->segments);
 
           /* Check if any errors are reported in the frame */
@@ -1705,8 +1705,8 @@ static int stm32_recvframe(struct stm32_ethmac_s *priv)
               arch_invalidate_dcache((uintptr_t)dev->d_buf,
                                      (uintptr_t)dev->d_buf + dev->d_len);
 
-              nllinfo("rxhead: %p d_buf: %p d_len: %d\n",
-                      priv->rxhead, dev->d_buf, dev->d_len);
+              ninfo("rxhead: %p d_buf: %p d_len: %d\n",
+                    priv->rxhead, dev->d_buf, dev->d_len);
 
               /* Return success */
 
@@ -1718,7 +1718,7 @@ static int stm32_recvframe(struct stm32_ethmac_s *priv)
                * scanning logic, and continue scanning with the next frame.
                */
 
-              nllwarn("WARNING: DROPPED RX descriptor errors: %08x\n", rxdesc->rdes0);
+              nwarn("WARNING: DROPPED RX descriptor errors: %08x\n", rxdesc->rdes0);
               stm32_freesegment(priv, rxcurr, priv->segments);
             }
         }
@@ -1739,8 +1739,8 @@ static int stm32_recvframe(struct stm32_ethmac_s *priv)
 
   priv->rxhead = rxdesc;
 
-  nllinfo("rxhead: %p rxcurr: %p segments: %d\n",
-          priv->rxhead, priv->rxcurr, priv->segments);
+  ninfo("rxhead: %p rxcurr: %p segments: %d\n",
+        priv->rxhead, priv->rxcurr, priv->segments);
 
   return -EAGAIN;
 }
@@ -1784,7 +1784,7 @@ static void stm32_receive(struct stm32_ethmac_s *priv)
 
       if (dev->d_len > CONFIG_NET_ETH_MTU)
         {
-          nllwarn("WARNING: DROPPED Too big: %d\n", dev->d_len);
+          nwarn("WARNING: DROPPED Too big: %d\n", dev->d_len);
           continue;
         }
 
@@ -1799,7 +1799,7 @@ static void stm32_receive(struct stm32_ethmac_s *priv)
 #ifdef CONFIG_NET_IPv4
       if (BUF->type == HTONS(ETHTYPE_IP))
         {
-          nllinfo("IPv4 frame\n");
+          ninfo("IPv4 frame\n");
 
           /* Handle ARP on input then give the IPv4 packet to the network
            * layer
@@ -1839,7 +1839,7 @@ static void stm32_receive(struct stm32_ethmac_s *priv)
 #ifdef CONFIG_NET_IPv6
       if (BUF->type == HTONS(ETHTYPE_IP6))
         {
-          nllinfo("Iv6 frame\n");
+          ninfo("Iv6 frame\n");
 
           /* Give the IPv6 packet to the network layer */
 
@@ -1876,7 +1876,7 @@ static void stm32_receive(struct stm32_ethmac_s *priv)
 #ifdef CONFIG_NET_ARP
       if (BUF->type == htons(ETHTYPE_ARP))
         {
-          nllinfo("ARP frame\n");
+          ninfo("ARP frame\n");
 
           /* Handle ARP packet */
 
@@ -1894,7 +1894,7 @@ static void stm32_receive(struct stm32_ethmac_s *priv)
       else
 #endif
         {
-          nllwarn("WARNING: DROPPED Unknown type: %04x\n", BUF->type);
+          nwarn("WARNING: DROPPED Unknown type: %04x\n", BUF->type);
         }
 
       /* We are finished with the RX buffer.  NOTE:  If the buffer is
@@ -1935,8 +1935,8 @@ static void stm32_freeframe(struct stm32_ethmac_s *priv)
   struct eth_txdesc_s *txdesc;
   int i;
 
-  nllinfo("txhead: %p txtail: %p inflight: %d\n",
-          priv->txhead, priv->txtail, priv->inflight);
+  ninfo("txhead: %p txtail: %p inflight: %d\n",
+        priv->txhead, priv->txtail, priv->inflight);
 
   /* Scan for "in-flight" descriptors owned by the CPU */
 
@@ -1956,8 +1956,8 @@ static void stm32_freeframe(struct stm32_ethmac_s *priv)
            * TX descriptors.
            */
 
-          nllinfo("txtail: %p tdes0: %08x tdes2: %08x tdes3: %08x\n",
-                  txdesc, txdesc->tdes0, txdesc->tdes2, txdesc->tdes3);
+          ninfo("txtail: %p tdes0: %08x tdes2: %08x tdes3: %08x\n",
+                txdesc, txdesc->tdes0, txdesc->tdes2, txdesc->tdes3);
 
           DEBUGASSERT(txdesc->tdes2 != 0);
 
@@ -2021,8 +2021,8 @@ static void stm32_freeframe(struct stm32_ethmac_s *priv)
 
       priv->txtail = txdesc;
 
-      nllinfo("txhead: %p txtail: %p inflight: %d\n",
-              priv->txhead, priv->txtail, priv->inflight);
+      ninfo("txhead: %p txtail: %p inflight: %d\n",
+            priv->txhead, priv->txtail, priv->inflight);
     }
 }
 
@@ -2158,7 +2158,7 @@ static inline void stm32_interrupt_process(struct stm32_ethmac_s *priv)
     {
       /* Just let the user know what happened */
 
-      nllerr("ERROR: Abormal event(s): %08x\n", dmasr);
+      nerr("ERROR: Abormal event(s): %08x\n", dmasr);
 
       /* Clear all pending abnormal events */
 
@@ -2362,7 +2362,7 @@ static void stm32_txtimeout_expiry(int argc, uint32_t arg, ...)
 {
   struct stm32_ethmac_s *priv = (struct stm32_ethmac_s *)arg;
 
-  nllerr("ERROR: Timeout!\n");
+  nerr("ERROR: Timeout!\n");
 
 #ifdef CONFIG_NET_NOINTS
   /* Disable further Ethernet interrupts.  This will prevent some race
@@ -2829,8 +2829,8 @@ static int stm32_addmac(struct net_driver_s *dev, const uint8_t *mac)
   uint32_t temp;
   uint32_t registeraddress;
 
-  nllinfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
-          mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+  ninfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
+        mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
 
   /* Add the MAC address to the hardware multicast hash table */
 
@@ -2886,7 +2886,7 @@ static int stm32_rmmac(struct net_driver_s *dev, const uint8_t *mac)
   uint32_t temp;
   uint32_t registeraddress;
 
-  nllinfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
+  ninfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
           mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
 
   /* Remove the MAC address to the hardware multicast hash table */
@@ -3973,11 +3973,11 @@ static void stm32_macaddress(struct stm32_ethmac_s *priv)
   struct net_driver_s *dev = &priv->dev;
   uint32_t regval;
 
-  nllinfo("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
-          dev->d_ifname,
-          dev->d_mac.ether_addr_octet[0], dev->d_mac.ether_addr_octet[1],
-          dev->d_mac.ether_addr_octet[2], dev->d_mac.ether_addr_octet[3],
-          dev->d_mac.ether_addr_octet[4], dev->d_mac.ether_addr_octet[5]);
+  ninfo("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
+        dev->d_ifname,
+        dev->d_mac.ether_addr_octet[0], dev->d_mac.ether_addr_octet[1],
+        dev->d_mac.ether_addr_octet[2], dev->d_mac.ether_addr_octet[3],
+        dev->d_mac.ether_addr_octet[4], dev->d_mac.ether_addr_octet[5]);
 
   /* Set the MAC address high register */
 
@@ -4179,12 +4179,12 @@ static int stm32_ethconfig(struct stm32_ethmac_s *priv)
 
   /* Reset the Ethernet block */
 
-  nllinfo("Reset the Ethernet block\n");
+  ninfo("Reset the Ethernet block\n");
   stm32_ethreset(priv);
 
   /* Initialize the PHY */
 
-  nllinfo("Initialize the PHY\n");
+  ninfo("Initialize the PHY\n");
   ret = stm32_phyinit(priv);
   if (ret < 0)
     {
@@ -4193,7 +4193,7 @@ static int stm32_ethconfig(struct stm32_ethmac_s *priv)
 
   /* Initialize the MAC and DMA */
 
-  nllinfo("Initialize the MAC and DMA\n");
+  ninfo("Initialize the MAC and DMA\n");
   ret = stm32_macconfig(priv);
   if (ret < 0)
     {
@@ -4217,7 +4217,7 @@ static int stm32_ethconfig(struct stm32_ethmac_s *priv)
 
   /* Enable normal MAC operation */
 
-  nllinfo("Enable normal operation\n");
+  ninfo("Enable normal operation\n");
   return stm32_macenable(priv);
 }
 
diff --git a/arch/arm/src/stm32f7/stm32_gpio.c b/arch/arm/src/stm32f7/stm32_gpio.c
index 0cd386725ff..17e8b4c1082 100644
--- a/arch/arm/src/stm32f7/stm32_gpio.c
+++ b/arch/arm/src/stm32f7/stm32_gpio.c
@@ -182,6 +182,7 @@ int stm32_configgpio(uint32_t cfgset)
         break;
 
       case GPIO_OUTPUT:     /* General purpose output mode */
+        stm32_gpiowrite(cfgset, (cfgset & GPIO_OUTPUT_SET) != 0); /* Set the initial output value */
         pinmode = GPIO_MODER_OUTPUT;
         break;
 
@@ -311,17 +312,9 @@ int stm32_configgpio(uint32_t cfgset)
 
   putreg32(regval, base + STM32_GPIO_OTYPER_OFFSET);
 
-  /* If it is an output... set the pin to the correct initial state. */
-
-  if (pinmode == GPIO_MODER_OUTPUT)
-    {
-      bool value = ((cfgset & GPIO_OUTPUT_SET) != 0);
-      stm32_gpiowrite(cfgset, value);
-    }
-
   /* Otherwise, it is an input pin.  Should it configured as an EXTI interrupt? */
 
-  else if ((cfgset & GPIO_EXTI) != 0)
+  if (pinmode != GPIO_MODER_OUTPUT && (cfgset & GPIO_EXTI) != 0)
     {
       /* "In STM32 F1 the selection of the EXTI line source is performed through
        *  the EXTIx bits in the AFIO_EXTICRx registers, while in F2 series this
diff --git a/arch/arm/src/stm32f7/stm32_i2c.c b/arch/arm/src/stm32f7/stm32_i2c.c
index e6fa309cd74..3786e7d52c2 100644
--- a/arch/arm/src/stm32f7/stm32_i2c.c
+++ b/arch/arm/src/stm32f7/stm32_i2c.c
@@ -1,18 +1,16 @@
 /************************************************************************************
- * arch/arm/src/stm32/stm32f3xx_i2c.c
- * STM32 F3 I2C Hardware Layer - Device Driver
+ * arch/arm/src/stm32/stm32f7_i2c.c
+ * STM32 I2C Hardware Layer - Device Driver
  *
  *   Copyright (C) 2011 Uros Platise. All rights reserved.
  *   Author: Uros Platise <uros.platise@isotel.eu>
  *
  * With extensions and modifications for the F1, F2, and F4 by:
  *
- *   Copyright (C) 2011-2013 Gregory Nutt. All rights reserved.
- *   Author: Gregroy Nutt <gnutt@nuttx.org>
- *
- * And this version for the STM32 F3 by
- *
- *   Author: John Wharington
+ *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ *   Authors: Gregroy Nutt <gnutt@nuttx.org>
+ *            John Wharington
+ *            David Sidrane <david_s5@nscdg.com>
  *
  * Major rewrite of ISR and supporting methods, including support
  * for NACK and RELOAD by:
@@ -51,22 +49,25 @@
 
 /* ------------------------------------------------------------------------------
  *
- * STM32 F3 I2C Driver
+ * STM32 F7 I2C Driver
  *
  * Supports:
- *  - STM32 F30xxx
- *  - Internal Oscillator (HSI) running at 8 Mhz
- *  - Master operation at up to 400Khz (Fast Mode)
+ *  - Master operation:
+ *      Standard-mode (up to 100 kHz)
+ *      Fast-mode (up to 400 kHz)
+ *      Fast-mode Plus (up to 1 MHz)
+ *      fI2CCLK clock source selection is based on STM32_RCC_DCKCFGR2_I2CxSRC
+ *      being set to HSI and the calulations are based on STM32_HSI_FREQUENCY
+ *      of 16mHz
+ *
  *  - Multiple instances (shared bus)
  *  - Interrupt based operation
  *  - RELOAD support
  *
  * Unsupported, possible future work:
  *  - More effective error reporting to higher layers
- *  - Fast mode plus (1Mhz)
  *  - Slave operation
- *  - Peripheral clock source selection (SYSCLK vs HSI)
- *  - Support of SYSCLK frequencies other than 8Mhz
+ *  - Support of fI2CCLK frequencies other than 16Mhz
  *  - Polled operation (code present but untested)
  *  - SMBus support
  *  - Multi-master support
@@ -74,8 +75,7 @@
  *
  * Test Environment:
  *
- *  - STM32F303VC on ST F3 Discovery Board (ST Part STM32F3DISCOVERY)
- *    256K Flash, 40K SRAM available for all operations, 8K SRAM CCM
+ *  - STM32F7676ZI on ST Nucleo-144 Board (ST Part STM32F429ZIT6)
  *
  * Operational Status:
  *
@@ -87,18 +87,18 @@
  *  payloads has not been  tested as the author lacked access to a real
  *  device supporting these types of transfers.
  *
- * Performance Benchmarks:
+ * Performance Benchmarks: TBD
  *
  *  Time to transfer two messages, each a byte in length, in addition to the
  *  START condition, in interrupt mode:
  *
- *  DEBUG enabled (development): 80ms
+ *  DEBUG enabled (development): TBDms
  *      Excessive delay here is caused by printing to the console and
  *      is of no concern.
  *
- *  DEBUG disabled (production): 120us
- *      Between Messages: 38us
- *      Between Bytes: 7us
+ *  DEBUG disabled (production): TBSus
+ *      Between Messages: TBDus
+ *      Between Bytes: TBDus
  *
  * Implementation:
  *
@@ -157,48 +157,55 @@
  *
  *  To use this driver, enable the following configuration variable:
  *
- *    CONFIG_STM32F7_STM32F30XX
+ *  One of:
+ *
+ *    CONFIG_STM32F7_STM32F74XX
+ *    CONFIG_STM32F7_STM32F75XX
+ *    CONFIG_STM32F7_STM32F76XX
+ *    CONFIG_STM32F7_STM32F77XX
+ *
  *
  *  and one or more interfaces:
  *
  *    CONFIG_STM32F7_I2C1
  *    CONFIG_STM32F7_I2C2
  *    CONFIG_STM32F7_I2C3
+ *    CONFIG_STM32F7_I2C4
  *
- *  To configure the ISR timeout using fixed values (STM32_I2C_DYNTIMEO=n):
+ *  To configure the ISR timeout using fixed values (CONFIG_STM32F7_I2C_DYNTIMEO=n):
  *
- *    CONFIG_STM32F7_I2CTIMEOMS    (Timeout in milliseconds)
  *    CONFIG_STM32F7_I2CTIMEOSEC   (Timeout in seconds)
+ *    CONFIG_STM32F7_I2CTIMEOMS    (Timeout in milliseconds)
  *    CONFIG_STM32F7_I2CTIMEOTICKS (Timeout in ticks)
  *
- *  To configure the ISR timeout using dynamic values (STM32_I2C_DYNTIMEO=y):
+ *  To configure the ISR timeout using dynamic values (CONFIG_STM32F7_I2C_DYNTIMEO=y):
  *
- *    STM32_I2C_DYNTIMEO_USECPERBYTE  (Timeout in microseconds per byte)
- *    STM32_I2C_DYNTIMEO_STARTSTOP    (Timeout for start/stop in milliseconds)
+ *    CONFIG_STM32F7_I2C_DYNTIMEO_USECPERBYTE  (Timeout in microseconds per byte)
+ *    CONFIG_STM32F7_I2C_DYNTIMEO_STARTSTOP    (Timeout for start/stop in milliseconds)
  *
  *  Debugging output enabled with:
  *
- *    CONFIG_DEBUG_I2C_INFO
+ *    CONFIG_DEBUG_FEATURES and CONFIG_DEBUG_I2C_{ERROR|WARN|INFO}
  *
  *  ISR Debugging output may be enabled with:
  *
- *    CONFIG_DEBUG_VERBOSE
+ *    CONFIG_DEBUG_FEATURES and CONFIG_DEBUG_I2C_INFO
  *
  * ------------------------------------------------------------------------------
  *
  * References:
  *
  *  RM0316:
- *     ST STM32F303xB/C/D/E, etc. Reference Manual
- *     Document ID: DM00043574, Revision 6, August 2015.
+ *     ST STM32F76xxx and STM32F77xxx Reference Manual
+ *     Document ID: DocID028270 Revision 2, April 2016.
  *
  *  DATASHEET:
- *     ST STM32F303xB/STM32F303xC Datasheet
- *     Document ID: DM00058181, Revision 12, December 2015.
+ *     ST STM32F777xx/STM32F778Ax/STM32F779x Datasheet
+ *     Document ID: DocID028294, Revision 3, May 2016.
  *
- *  303ZYERRATA:
- *     STM32F303xB/C Rev Z and Y device limitations
- *     Document ID: DM00063985, Revision 7, September 2015.
+ *  ERRATA:
+ *     STM32F76xxx/STM32F77xxx Errata sheet Rev A device limitations
+ *     Document ID: DocID028806, Revision 2, April 2016.
  *
  *  I2CSPEC:
  *     I2C Bus Specification and User Manual
@@ -239,14 +246,40 @@
 
 /* At least one I2C peripheral must be enabled */
 
-#if defined(CONFIG_STM32F7_I2C1) || defined(CONFIG_STM32F7_I2C2) || defined(CONFIG_STM32F7_I2C3)
-/* This implementation is for the STM32 F1, F2, and F4 only */
-
+#if defined(CONFIG_STM32F7_I2C1) || defined(CONFIG_STM32F7_I2C2) || \
+    defined(CONFIG_STM32F7_I2C3) || defined(CONFIG_STM32F7_I2C4)
 
 /************************************************************************************
  * Pre-processor Definitions
  ************************************************************************************/
 
+#undef INVALID_CLOCK_SOURCE
+
+#ifdef CONFIG_STM32F7_I2C1
+#  if STM32_RCC_DCKCFGR2_I2C1SRC != RCC_DCKCFGR2_I2C1SEL_HSI
+#    warning "Clock Source STM32_RCC_DCKCFGR2_I2C1SRC must be HSI"
+#    define INVALID_CLOCK_SOURCE
+#  endif
+#endif
+#ifdef CONFIG_STM32F7_I2C1
+#  if STM32_RCC_DCKCFGR2_I2C2SRC != RCC_DCKCFGR2_I2C2SEL_HSI
+#    warning "Clock Source STM32_RCC_DCKCFGR2_I2C2SRC must be HSI"
+#    define INVALID_CLOCK_SOURCE
+#  endif
+#endif
+#ifdef CONFIG_STM32F7_I2C3
+#  if STM32_RCC_DCKCFGR2_I2C3SRC != RCC_DCKCFGR2_I2C3SEL_HSI
+#    warning "Clock Source STM32_RCC_DCKCFGR2_I2C3SRC must be HSI"
+#    define INVALID_CLOCK_SOURCE
+#  endif
+#endif
+#ifdef CONFIG_STM32F7_I2C4
+#  if STM32_RCC_DCKCFGR2_I2C4SRC != RCC_DCKCFGR2_I2C4SEL_HSI
+#    warning "Clock Source STM32_RCC_DCKCFGR2_I2C4SRC must be HSI"
+#    define INVALID_CLOCK_SOURCE
+#  endif
+#endif
+
 /* CONFIG_I2C_POLLED may be set so that I2C interrupts will not be used.  Instead,
  * CPU-intensive polling will be used.
  */
@@ -256,6 +289,7 @@
 #if !defined(CONFIG_STM32F7_I2CTIMEOSEC) && !defined(CONFIG_STM32F7_I2CTIMEOMS)
 #  define CONFIG_STM32F7_I2CTIMEOSEC 0
 #  define CONFIG_STM32F7_I2CTIMEOMS  500   /* Default is 500 milliseconds */
+#  warning "Using Defualt 500 Ms Timeout"
 #elif !defined(CONFIG_STM32F7_I2CTIMEOSEC)
 #  define CONFIG_STM32F7_I2CTIMEOSEC 0     /* User provided milliseconds */
 #elif !defined(CONFIG_STM32F7_I2CTIMEOMS)
@@ -280,12 +314,8 @@
 
 #define MKI2C_OUTPUT(p) (((p) & (GPIO_PORT_MASK | GPIO_PIN_MASK)) | I2C_OUTPUT)
 
-/* Register setting unique to the STM32F30xx */
-
-#define I2C_CR1_TXRX \
-  (I2C_CR1_RXIE | I2C_CR1_TXIE)
-#define I2C_CR1_ALLINTS \
-  (I2C_CR1_TXRX | I2C_CR1_TCIE | I2C_CR1_ERRIE)
+#define I2C_CR1_TXRX (I2C_CR1_RXIE | I2C_CR1_TXIE)
+#define I2C_CR1_ALLINTS (I2C_CR1_TXRX | I2C_CR1_TCIE | I2C_CR1_ERRIE)
 
 /* I2C event tracing
  *
@@ -455,15 +485,18 @@ static inline void stm32_i2c_sendstop(FAR struct stm32_i2c_priv_s *priv);
 static inline uint32_t stm32_i2c_getstatus(FAR struct stm32_i2c_priv_s *priv);
 static int stm32_i2c_isr(struct stm32_i2c_priv_s * priv);
 #ifndef CONFIG_I2C_POLLED
-#ifdef CONFIG_STM32F7_I2C1
+#  ifdef CONFIG_STM32F7_I2C1
 static int stm32_i2c1_isr(int irq, void *context);
-#endif
-#ifdef CONFIG_STM32F7_I2C2
+#  endif
+#  ifdef CONFIG_STM32F7_I2C2
 static int stm32_i2c2_isr(int irq, void *context);
-#endif
-#ifdef CONFIG_STM32F7_I2C3
+#  endif
+#  ifdef CONFIG_STM32F7_I2C3
 static int stm32_i2c3_isr(int irq, void *context);
-#endif
+#  endif
+#  ifdef CONFIG_STM32F7_I2C4
+static int stm32_i2c4_isr(int irq, void *context);
+#  endif
 #endif
 static int stm32_i2c_init(FAR struct stm32_i2c_priv_s *priv);
 static int stm32_i2c_deinit(FAR struct stm32_i2c_priv_s *priv);
@@ -570,6 +603,36 @@ struct stm32_i2c_priv_s stm32_i2c3_priv =
 };
 #endif
 
+#ifdef CONFIG_STM32F7_I2C4
+static const struct stm32_i2c_config_s stm32_i2c4_config =
+{
+  .base       = STM32_I2C4_BASE,
+  .clk_bit    = RCC_APB1ENR_I2C4EN,
+  .reset_bit  = RCC_APB1RSTR_I2C4RST,
+  .scl_pin    = GPIO_I2C4_SCL,
+  .sda_pin    = GPIO_I2C4_SDA,
+#ifndef CONFIG_I2C_POLLED
+  .isr        = stm32_i2c4_isr,
+  .ev_irq     = STM32_IRQ_I2C4EV,
+  .er_irq     = STM32_IRQ_I2C4ER
+#endif
+};
+
+struct stm32_i2c_priv_s stm32_i2c4_priv =
+{
+  .config     = &stm32_i2c4_config,
+  .refs       = 0,
+  .intstate   = INTSTATE_IDLE,
+  .msgc       = 0,
+  .msgv       = NULL,
+  .ptr        = NULL,
+  .frequency  = 0,
+  .dcnt       = 0,
+  .flags      = 0,
+  .status     = 0
+};
+#endif
+
 /* Device Structures, Instantiation */
 
 struct i2c_ops_s stm32_i2c_ops =
@@ -712,7 +775,7 @@ static useconds_t stm32_i2c_tousecs(int msgc, FAR struct i2c_msg_s *msgs)
 #ifndef CONFIG_I2C_POLLED
 static inline void stm32_i2c_enableinterrupts(struct stm32_i2c_priv_s *priv)
 {
-    stm32_i2c_modifyreg32(priv, STM32F7_I2C_CR1_OFFSET, 0, (I2C_CR1_TXRX | I2C_CR1_NACKIE));
+    stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, (I2C_CR1_TXRX | I2C_CR1_NACKIE));
 }
 #endif
 
@@ -742,7 +805,7 @@ static inline int stm32_i2c_sem_waitdone(FAR struct stm32_i2c_priv_s *priv)
    * The remainder of the interrupts, including error-related, are enabled here.
    */
 
-  stm32_i2c_modifyreg32(priv, STM32F7_I2C_CR1_OFFSET, 0,
+  stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0,
                         (I2C_CR1_ALLINTS & ~I2C_CR1_TXRX));
 
   /* Signal the interrupt handler that we are waiting */
@@ -802,7 +865,7 @@ static inline int stm32_i2c_sem_waitdone(FAR struct stm32_i2c_priv_s *priv)
 
   /* Disable I2C interrupts */
 
-  stm32_i2c_modifyreg32(priv, STM32F7_I2C_CR1_OFFSET, I2C_CR1_ALLINTS, 0);
+  stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_ALLINTS, 0);
 
   leave_critical_section(flags);
   return ret;
@@ -869,7 +932,7 @@ static inline int stm32_i2c_sem_waitdone(FAR struct stm32_i2c_priv_s *priv)
 static inline void
 stm32_i2c_set_7bit_address(FAR struct stm32_i2c_priv_s *priv)
 {
-  stm32_i2c_modifyreg32(priv, STM32F7_I2C_CR2_OFFSET, I2C_CR2_SADD7_MASK,
+  stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_SADD7_MASK,
                         ((priv->msgv->addr & 0x7F) << I2C_CR2_SADD7_SHIFT));
 }
 
@@ -884,7 +947,7 @@ static inline void
 stm32_i2c_set_bytes_to_transfer(FAR struct stm32_i2c_priv_s *priv,
                                uint8_t n_bytes)
 {
-  stm32_i2c_modifyreg32(priv, STM32F7_I2C_CR2_OFFSET, I2C_CR2_NBYTES_MASK,
+  stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_NBYTES_MASK,
                         (n_bytes << I2C_CR2_NBYTES_SHIFT));
 }
 
@@ -898,7 +961,7 @@ stm32_i2c_set_bytes_to_transfer(FAR struct stm32_i2c_priv_s *priv,
 static inline void
 stm32_i2c_set_write_transfer_dir(FAR struct stm32_i2c_priv_s *priv)
 {
-  stm32_i2c_modifyreg32(priv, STM32F7_I2C_CR2_OFFSET, I2C_CR2_RD_WRN, 0);
+  stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_RD_WRN, 0);
 }
 
 /************************************************************************************
@@ -911,7 +974,7 @@ stm32_i2c_set_write_transfer_dir(FAR struct stm32_i2c_priv_s *priv)
 static inline void
 stm32_i2c_set_read_transfer_dir(FAR struct stm32_i2c_priv_s *priv)
 {
-  stm32_i2c_modifyreg32(priv, STM32F7_I2C_CR2_OFFSET, 0, I2C_CR2_RD_WRN);
+  stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_RD_WRN);
 }
 
 /************************************************************************************
@@ -924,7 +987,7 @@ stm32_i2c_set_read_transfer_dir(FAR struct stm32_i2c_priv_s *priv)
 static inline void
 stm32_i2c_enable_reload(FAR struct stm32_i2c_priv_s *priv)
 {
-  stm32_i2c_modifyreg32(priv, STM32F7_I2C_CR2_OFFSET, 0, I2C_CR2_RELOAD);
+  stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_RELOAD);
 }
 
 /************************************************************************************
@@ -937,7 +1000,7 @@ stm32_i2c_enable_reload(FAR struct stm32_i2c_priv_s *priv)
 static inline void
 stm32_i2c_disable_reload(FAR struct stm32_i2c_priv_s *priv)
 {
-  stm32_i2c_modifyreg32(priv, STM32F7_I2C_CR2_OFFSET, I2C_CR2_RELOAD, 0);
+  stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_RELOAD, 0);
 }
 
 
@@ -972,7 +1035,7 @@ static inline void stm32_i2c_sem_waitstop(FAR struct stm32_i2c_priv_s *priv)
     {
       /* Check for STOP condition */
 
-      cr = stm32_i2c_getreg32(priv, STM32F7_I2C_CR2_OFFSET);
+      cr = stm32_i2c_getreg32(priv, STM32_I2C_CR2_OFFSET);
       if ((cr & I2C_CR2_STOP) == 0)
         {
           return;
@@ -980,7 +1043,7 @@ static inline void stm32_i2c_sem_waitstop(FAR struct stm32_i2c_priv_s *priv)
 
       /* Check for timeout error */
 
-      sr = stm32_i2c_getreg(priv, STM32F7_I2C_ISR_OFFSET);
+      sr = stm32_i2c_getreg(priv, STM32_I2C_ISR_OFFSET);
       if ((sr & I2C_INT_TIMEOUT) != 0)
         {
           return;
@@ -1171,10 +1234,10 @@ static void stm32_i2c_tracedump(FAR struct stm32_i2c_priv_s *priv)
  *
  *   This function supports bus clock frequencies of:
  *
- *      500Khz
- *      400Khz
- *      100Khz
- *       10Khz
+ *      1000Khz (Fast Mode+)
+ *      400Khz  (Fast Mode)
+ *      100Khz  (Standard Mode)
+ *      10Khz   (Standard Mode)
  *
  *   Attempts to set a different frequency will quietly provision the default
  *   of 10Khz.
@@ -1190,15 +1253,15 @@ static void stm32_i2c_tracedump(FAR struct stm32_i2c_priv_s *priv)
  *
  * Clock Selection:
  *
- *   The I2C peripheral clock can be provided by either SYSCLK or the HSI.
+ *   The I2C peripheral clock can be provided by either PCLK1, SYSCLK or the HSI.
  *
- *   SYSCLK >------|\   I2CCLK
- *                 | |--------->
+ *    PCLK1 >------|\   I2CCLK
+ *   SYSCLK >------| |--------->
  *      HSI >------|/
  *
- *   HSI is the default and is always 8Mhz.
+ *   HSI is the default and is always 16Mhz.
  *
- *   SYSCLK can, in turn, be derived from the HSI, PLL or HSE.
+ *   SYSCLK can, in turn, be derived from the HSI, HSE, PPLCLK.
  *
  *      HSI >------|\
  *                 | |  SYSCLK
@@ -1206,19 +1269,10 @@ static void stm32_i2c_tracedump(FAR struct stm32_i2c_priv_s *priv)
  *                 | |
  *      HSE >------|/
  *
- *   The ability to select the I2C peripheral clock source is not yet supported
- *   so all of this really only works at 8Mhz.  The values provided are copied
- *   directly from the 8Mhz example table in RM0316 (See References).
- *
- * TODO:
- *
- *  - Add support for peripheral clock source selection (SYSCLK vs HSI).
- *  - Calculate values for a given SYSCLK frequency.
- *  - Add support for Fast Mode Plus (up to 1Mhz)
  *
  * References:
  *
- *  RM0316: Section: 28.4.9: I2C_TIMINGR register configuration examples
+ *  App Note AN4235 and the associated software STSW-STM32126.
  *
  ************************************************************************************/
 
@@ -1235,39 +1289,52 @@ static void stm32_i2c_setclock(FAR struct stm32_i2c_priv_s *priv, uint32_t frequ
     {
       /* I2C peripheral must be disabled to update clocking configuration */
 
-      pe = (stm32_i2c_getreg32(priv, STM32F7_I2C_CR1_OFFSET) & I2C_CR1_PE);
+      pe = (stm32_i2c_getreg32(priv, STM32_I2C_CR1_OFFSET) & I2C_CR1_PE);
       if (pe)
         {
-          stm32_i2c_modifyreg32(priv, STM32F7_I2C_CR1_OFFSET, I2C_CR1_PE, 0);
+          stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_PE, 0);
         }
 
-      /* TODO: speed/timing calcs, at the moment 45Mhz = STM32_PCLK1_FREQUENCY, analog filter is on,
-          digital off from STM32F0-F3_AN4235_V1.0.1 */
+      /*  The Sppeed and timing calculation are based on the following
+       *  fI2CCLK = HSI and is 16Mhz
+       *  Analog filter is on,
+       *  Digital filter off
+       *  Rise Time is 120 ns and fall is 10ns
+       *  Mode is FastMode
+       */
 
         if (frequency == 100000)
           {
-            presc        = 0x06;
-            scl_delay    = 0x02;
-            sda_delay    = 0x00;
-            scl_h_period = 0x1e;
-            scl_l_period = 0x2b;
+            presc        = 0;
+            scl_delay    = 3;
+            sda_delay    = 0;
+            scl_h_period = 30;
+            scl_l_period = 120;
 
           }
-       else if (frequency == 400000)
-          {
-            presc        = 0x00;
-            scl_delay    = 0x0A;
-            sda_delay    = 0x00;
-            scl_h_period = 0x1b;
-            scl_l_period = 0x5b;
-          }
+        else if (frequency == 400000)
+           {
+             presc        = 0;
+             scl_delay    = 3;
+             sda_delay    = 9;
+             scl_h_period = 6;
+             scl_l_period = 24;
+           }
+         else if (frequency == 1000000)
+            {
+              presc        = 0;
+              scl_delay    = 2;
+              sda_delay    = 0;
+              scl_h_period = 1;
+              scl_l_period = 5;
+            }
         else
           {
-            presc        = 0x00;
-            scl_delay    = 0x08;
-            sda_delay    = 0x00;
-            scl_h_period = 0x09;
-            scl_l_period = 0x1c;
+            presc        = 7;
+            scl_delay    = 0;
+            sda_delay    = 0;
+            scl_h_period = 35;
+            scl_l_period = 162;
           }
 
       uint32_t timingr =
@@ -1277,11 +1344,11 @@ static void stm32_i2c_setclock(FAR struct stm32_i2c_priv_s *priv, uint32_t frequ
         (scl_h_period << I2C_TIMINGR_SCLH_SHIFT) |
         (scl_l_period << I2C_TIMINGR_SCLL_SHIFT);
 
-      stm32_i2c_putreg32(priv, STM32F7_I2C_TIMINGR_OFFSET, timingr);
+      stm32_i2c_putreg32(priv, STM32_I2C_TIMINGR_OFFSET, timingr);
 
       if (pe)
         {
-          stm32_i2c_modifyreg32(priv, STM32F7_I2C_CR1_OFFSET, 0, I2C_CR1_PE);
+          stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, I2C_CR1_PE);
         }
 
       priv->frequency = frequency;
@@ -1378,11 +1445,14 @@ static inline void stm32_i2c_sendstart(FAR struct stm32_i2c_priv_s *priv)
    * exceed the hardware maximum allowed.
    */
 
-  if (priv->dcnt > 255) {
+  if (priv->dcnt > 255)
+    {
       stm32_i2c_set_bytes_to_transfer(priv, 255);
-  } else {
+    }
+  else
+    {
       stm32_i2c_set_bytes_to_transfer(priv, priv->dcnt);
-  }
+    }
 
   /* Set the (7 bit) address.
    * 10 bit addressing is not yet supported.
@@ -1408,9 +1478,9 @@ static inline void stm32_i2c_sendstart(FAR struct stm32_i2c_priv_s *priv)
    */
 
   i2cinfo("Sending START: dcnt=%i msgc=%i flags=0x%04x\n",
-     priv->dcnt, priv->msgc, priv->flags);
+          priv->dcnt, priv->msgc, priv->flags);
 
-  stm32_i2c_modifyreg32(priv, STM32F7_I2C_CR2_OFFSET, 0, I2C_CR2_START);
+  stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_START);
 }
 
 /************************************************************************************
@@ -1430,7 +1500,7 @@ static inline void stm32_i2c_sendstop(FAR struct stm32_i2c_priv_s *priv)
   i2cinfo("Sending STOP\n");
   stm32_i2c_traceevent(priv, I2CEVENT_WRITE_STOP, 0);
 
-  stm32_i2c_modifyreg32(priv, STM32F7_I2C_CR2_OFFSET, 0, I2C_CR2_STOP);
+  stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_STOP);
 }
 
 /************************************************************************************
@@ -1443,7 +1513,7 @@ static inline void stm32_i2c_sendstop(FAR struct stm32_i2c_priv_s *priv)
 
 static inline uint32_t stm32_i2c_getstatus(FAR struct stm32_i2c_priv_s *priv)
 {
-  return getreg32(priv->config->base + STM32F7_I2C_ISR_OFFSET);
+  return getreg32(priv->config->base + STM32_I2C_ISR_OFFSET);
 }
 
 /************************************************************************************
@@ -1456,7 +1526,7 @@ static inline uint32_t stm32_i2c_getstatus(FAR struct stm32_i2c_priv_s *priv)
 
 static inline void stm32_i2c_clearinterrupts(struct stm32_i2c_priv_s *priv)
 {
-  stm32_i2c_modifyreg32(priv, STM32F7_I2C_ICR_OFFSET, 0, I2C_ICR_CLEARMASK);
+  stm32_i2c_modifyreg32(priv, STM32_I2C_ICR_OFFSET, 0, I2C_ICR_CLEARMASK);
 }
 
 /************************************************************************************
@@ -1483,7 +1553,7 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
 
   /* Get state of the I2C controller */
 
-  status = stm32_i2c_getreg32(priv, STM32F7_I2C_ISR_OFFSET);
+  status = stm32_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET);
 
   i2cinfo("ENTER: status = 0x%08x\n", status);
 
@@ -1645,7 +1715,7 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
 
           /* Transmit current byte */
 
-          stm32_i2c_putreg(priv, STM32F7_I2C_TXDR_OFFSET, *priv->ptr);
+          stm32_i2c_putreg(priv, STM32_I2C_TXDR_OFFSET, *priv->ptr);
 
           /* Advance to next byte */
 
@@ -1719,7 +1789,7 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
 #endif
           /* Receive a byte */
 
-          *priv->ptr = stm32_i2c_getreg(priv, STM32F7_I2C_RXDR_OFFSET);
+          *priv->ptr = stm32_i2c_getreg(priv, STM32_I2C_RXDR_OFFSET);
 
           i2cinfo("RXNE: Read Data 0x%02x\n", *priv->ptr);
 
@@ -1740,9 +1810,9 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
           /* Unsupported state */
 
           stm32_i2c_traceevent(priv, I2CEVENT_READ_ERROR, 0);
-          status = stm32_i2c_getreg(priv, STM32F7_I2C_ISR_OFFSET);
+          status = stm32_i2c_getreg(priv, STM32_I2C_ISR_OFFSET);
           i2cerr("ERROR: RXNE Unsupported state detected, dcnt=%i, status 0x%08x\n",
-          priv->dcnt, status);
+                 priv->dcnt, status);
 
           /* Set signals that will terminate ISR and wake waiting thread */
 
@@ -1952,7 +2022,7 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
                * we receive a TC event next time which will allow us to
                * either RESTART and continue sending the contents of the
                * next message or send a STOP condition and exit the ISR.
-              */
+               */
 
               i2cinfo("TCR: DISABLE RELOAD: NBYTES = dcnt = %i msgc = %i\n",
                       priv->dcnt, priv->msgc);
@@ -1975,7 +2045,7 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
 
   else if (priv->dcnt == -1 && priv->msgc == 0)
     {
-      status = stm32_i2c_getreg(priv, STM32F7_I2C_ISR_OFFSET);
+      status = stm32_i2c_getreg(priv, STM32_I2C_ISR_OFFSET);
       i2cwarn("WARNING: EMPTY CALL: Stopping ISR: status 0x%08x\n", status);
       stm32_i2c_traceevent(priv, I2CEVENT_ISR_EMPTY_CALL, 0);
     }
@@ -1990,14 +2060,14 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
    * in one of the supported states when polled.
    */
 
-   else
+  else
     {
 #ifdef CONFIG_I2C_POLLED
       stm32_i2c_traceevent(priv, I2CEVENT_POLL_DEV_NOT_RDY, 0);
 #else
       /* Read rest of the state */
 
-      status = stm32_i2c_getreg(priv, STM32F7_I2C_ISR_OFFSET);
+      status = stm32_i2c_getreg(priv, STM32_I2C_ISR_OFFSET);
 
       i2cerr("ERROR: Invalid state detected, status 0x%08x\n", status);
 
@@ -2033,20 +2103,21 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
       priv->intstate = INTSTATE_DONE;
 #else
 
-      status = stm32_i2c_getreg32(priv, STM32F7_I2C_ISR_OFFSET);
+      status = stm32_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET);
 
       /* Update private state to capture NACK which is used in combination
        * with the astart flag to report the type of NACK received (address
        * vs data) to the upper layers once we exit the ISR.
        *
        * Note: We do this prior to clearing interrupts because the NACKF
-       * flag will naturally be cleared by that process. */
+       * flag will naturally be cleared by that process.
+       */
 
       priv->status = status;
 
       /* Clear all interrupts */
 
-      stm32_i2c_modifyreg32(priv, STM32F7_I2C_ICR_OFFSET, 0, I2C_ICR_CLEARMASK);
+      stm32_i2c_modifyreg32(priv, STM32_I2C_ICR_OFFSET, 0, I2C_ICR_CLEARMASK);
 
       /* If a thread is waiting then inform it transfer is complete */
 
@@ -2058,7 +2129,7 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
 #endif
     }
 
-  status = stm32_i2c_getreg32(priv, STM32F7_I2C_ISR_OFFSET);
+  status = stm32_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET);
   i2cinfo("EXIT: status = 0x%08x\n", status);
 
   return OK;
@@ -2073,12 +2144,12 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
  ************************************************************************************/
 
 #ifndef CONFIG_I2C_POLLED
-#ifdef CONFIG_STM32F7_I2C1
+#  ifdef CONFIG_STM32F7_I2C1
 static int stm32_i2c1_isr(int irq, void *context)
 {
   return stm32_i2c_isr(&stm32_i2c1_priv);
 }
-#endif
+#  endif
 
 /************************************************************************************
  * Name: stm32_i2c2_isr
@@ -2088,12 +2159,12 @@ static int stm32_i2c1_isr(int irq, void *context)
  *
  ************************************************************************************/
 
-#ifdef CONFIG_STM32F7_I2C2
+# ifdef CONFIG_STM32F7_I2C2
 static int stm32_i2c2_isr(int irq, void *context)
 {
   return stm32_i2c_isr(&stm32_i2c2_priv);
 }
-#endif
+#  endif
 
 /************************************************************************************
  * Name: stm32_i2c3_isr
@@ -2103,12 +2174,27 @@ static int stm32_i2c2_isr(int irq, void *context)
  *
  ************************************************************************************/
 
-#ifdef CONFIG_STM32F7_I2C3
+#  ifdef CONFIG_STM32F7_I2C3
 static int stm32_i2c3_isr(int irq, void *context)
 {
   return stm32_i2c_isr(&stm32_i2c3_priv);
 }
-#endif
+#  endif
+
+/************************************************************************************
+ * Name: stm32_i2c4_isr
+ *
+ * Description:
+ *   I2C2 interrupt service routine
+ *
+ ************************************************************************************/
+
+#  ifdef CONFIG_STM32F7_I2C4
+static int stm32_i2c4_isr(int irq, void *context)
+{
+  return stm32_i2c_isr(&stm32_i2c4_priv);
+}
+#  endif
 #endif
 
 /************************************************************************************
@@ -2164,7 +2250,7 @@ static int stm32_i2c_init(FAR struct stm32_i2c_priv_s *priv)
 
   /* Enable I2C peripheral */
 
-  stm32_i2c_modifyreg32(priv, STM32F7_I2C_CR1_OFFSET, 0, I2C_CR1_PE);
+  stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, I2C_CR1_PE);
 
   return OK;
 }
@@ -2181,7 +2267,7 @@ static int stm32_i2c_deinit(FAR struct stm32_i2c_priv_s *priv)
 {
   /* Disable I2C */
 
-  stm32_i2c_putreg32(priv, STM32F7_I2C_CR1_OFFSET, 0);
+  stm32_i2c_putreg32(priv, STM32_I2C_CR1_OFFSET, 0);
 
   /* Unconfigure GPIO pins */
 
@@ -2221,8 +2307,8 @@ static int stm32_i2c_process(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s
   struct stm32_i2c_inst_s     *inst = (struct stm32_i2c_inst_s *)dev;
   FAR struct stm32_i2c_priv_s *priv = inst->priv;
   uint32_t    status = 0;
-  uint32_t    cr1 = 0;
-  uint32_t    cr2 = 0;
+  uint32_t    cr1;
+  uint32_t    cr2;
   int         errval = 0;
   int         waitrc = 0;
 
@@ -2279,8 +2365,12 @@ static int stm32_i2c_process(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s
 
   waitrc = stm32_i2c_sem_waitdone(priv);
 
-  cr1 = stm32_i2c_getreg32(priv, STM32F7_I2C_CR1_OFFSET);
-  cr2 = stm32_i2c_getreg32(priv, STM32F7_I2C_CR2_OFFSET);
+  cr1 = stm32_i2c_getreg32(priv, STM32_I2C_CR1_OFFSET);
+  cr2 = stm32_i2c_getreg32(priv, STM32_I2C_CR2_OFFSET);
+#if !defined(CONFIG_DEBUG_I2C)
+  UNUSED(cr1);
+  UNUSED(cr2);
+#endif
 
   /* Status after a normal / good exit is usually 0x00000001, meaning the TXE
    * bit is set.  That occurs as a result of the I2C_TXDR register being
@@ -2312,6 +2402,9 @@ static int stm32_i2c_process(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s
              cr1, cr2,status );
     }
 
+  UNUSED(cr1);
+  UNUSED(cr2);
+
   i2cinfo("priv->status: 0x%08x\n", priv->status);
 
   /* Check for error status conditions */
@@ -2463,13 +2556,9 @@ FAR struct i2c_master_s *stm32_i2cbus_initialize(int port)
   struct stm32_i2c_inst_s * inst = NULL;  /* device, single instance */
   int irqs;
 
-#if STM32_PCLK1_FREQUENCY < 4000000
-#   warning STM32_I2C_INIT: Peripheral clock must be at least 4 MHz to support 400 kHz operation.
-#endif
-
-#if STM32_PCLK1_FREQUENCY < 2000000
-#   warning STM32_I2C_INIT: Peripheral clock must be at least 2 MHz to support 100 kHz operation.
-  return NULL;
+#if STM32_HSI_FREQUENCY != 16000000 || defined(INVALID_CLOCK_SOURCE)
+#   warning STM32_I2C_INIT: Peripheral clock is HSI and it must be 16mHz or the speed/timing calculations need to be redone.
+    return NULL;
 #endif
 
   /* Get I2C private structure */
@@ -2490,6 +2579,11 @@ FAR struct i2c_master_s *stm32_i2cbus_initialize(int port)
       case 3:
         priv = (struct stm32_i2c_priv_s *)&stm32_i2c3_priv;
         break;
+#endif
+#ifdef CONFIG_STM32F7_I2C4
+      case 4:
+        priv = (struct stm32_i2c_priv_s *)&stm32_i2c4_priv;
+        break;
 #endif
       default:
         return NULL;
diff --git a/arch/arm/src/stm32f7/stm32_irq.c b/arch/arm/src/stm32f7/stm32_irq.c
index 62c4aee7aa7..eb7a8e1b868 100644
--- a/arch/arm/src/stm32f7/stm32_irq.c
+++ b/arch/arm/src/stm32f7/stm32_irq.c
@@ -175,7 +175,7 @@ static void stm32_dumpnvic(const char *msg, int irq)
 #endif
 
 /****************************************************************************
- * Name: stm32_nmi, stm32_busfault, stm32_usagefault, stm32_pendsv, stm32_errmonitor,
+ * Name: stm32_nmi, stm32_busfault, stm32_usagefault, stm32_pendsv, stm32_dbgmonitor,
  *       stm32_pendsv, stm32_reserved
  *
  * Description:
@@ -218,7 +218,7 @@ static int stm32_pendsv(int irq, FAR void *context)
   return 0;
 }
 
-static int stm32_errmonitor(int irq, FAR void *context)
+static int stm32_dbgmonitor(int irq, FAR void *context)
 {
   (void)up_irq_save();
   _err("PANIC!!! Debug Monitor received\n");
@@ -500,7 +500,7 @@ void up_irqinitialize(void)
   irq_attach(STM32_IRQ_BUSFAULT, stm32_busfault);
   irq_attach(STM32_IRQ_USAGEFAULT, stm32_usagefault);
   irq_attach(STM32_IRQ_PENDSV, stm32_pendsv);
-  irq_attach(STM32_IRQ_DBGMONITOR, stm32_errmonitor);
+  irq_attach(STM32_IRQ_DBGMONITOR, stm32_dbgmonitor);
   irq_attach(STM32_IRQ_RESERVED, stm32_reserved);
 #endif
 
diff --git a/arch/arm/src/stm32f7/stm32_tim.c b/arch/arm/src/stm32f7/stm32_tim.c
index 7605a14a7f6..84934db13dc 100644
--- a/arch/arm/src/stm32f7/stm32_tim.c
+++ b/arch/arm/src/stm32f7/stm32_tim.c
@@ -6,8 +6,9 @@
  *
  * With modifications and updates by:
  *
- *   Copyright (C) 2011-2012 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ *   Authors: Gregory Nutt <gnutt@nuttx.org>
+ *            David Sidrane <david_s5@nscdg.com>
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -144,56 +145,101 @@
 #  undef CONFIG_STM32F7_TIM14
 #endif
 
-#if defined(CONFIG_STM32F7_TIM1) 
+#if defined(CONFIG_STM32F7_TIM1)
 #  if defined(GPIO_TIM1_CH1OUT) ||defined(GPIO_TIM1_CH2OUT)||\
       defined(GPIO_TIM1_CH3OUT) ||defined(GPIO_TIM1_CH4OUT)
 #    define HAVE_TIM1_GPIOCONFIG 1
 #endif
 #endif
 
-#if defined(CONFIG_STM32F7_TIM2) 
+#if defined(CONFIG_STM32F7_TIM2)
 #  if defined(GPIO_TIM2_CH1OUT) ||defined(GPIO_TIM2_CH2OUT)||\
       defined(GPIO_TIM2_CH3OUT) ||defined(GPIO_TIM2_CH4OUT)
 #    define HAVE_TIM2_GPIOCONFIG 1
 #endif
 #endif
 
-#if defined(CONFIG_STM32F7_TIM3) 
+#if defined(CONFIG_STM32F7_TIM3)
 #  if defined(GPIO_TIM3_CH1OUT) ||defined(GPIO_TIM3_CH2OUT)||\
       defined(GPIO_TIM3_CH3OUT) ||defined(GPIO_TIM3_CH4OUT)
 #    define HAVE_TIM3_GPIOCONFIG 1
 #endif
 #endif
 
-#if defined(CONFIG_STM32F7_TIM4) 
+#if defined(CONFIG_STM32F7_TIM4)
 #  if defined(GPIO_TIM4_CH1OUT) ||defined(GPIO_TIM4_CH2OUT)||\
       defined(GPIO_TIM4_CH3OUT) ||defined(GPIO_TIM4_CH4OUT)
 #    define HAVE_TIM4_GPIOCONFIG 1
 #endif
 #endif
 
-#if defined(CONFIG_STM32F7_TIM5) 
+#if defined(CONFIG_STM32F7_TIM5)
 #  if defined(GPIO_TIM5_CH1OUT) ||defined(GPIO_TIM5_CH2OUT)||\
       defined(GPIO_TIM5_CH3OUT) ||defined(GPIO_TIM5_CH4OUT)
 #    define HAVE_TIM5_GPIOCONFIG 1
 #endif
 #endif
 
-#if defined(CONFIG_STM32F7_TIM8) 
+#if defined(CONFIG_STM32F7_TIM8)
 #  if defined(GPIO_TIM8_CH1OUT) ||defined(GPIO_TIM8_CH2OUT)||\
       defined(GPIO_TIM8_CH3OUT) ||defined(GPIO_TIM8_CH4OUT)
 #    define HAVE_TIM8_GPIOCONFIG 1
 #endif
 #endif
+#if defined(CONFIG_STM32F7_TIM9)
+#  if defined(GPIO_TIM9_CH1OUT) ||defined(GPIO_TIM9_CH2OUT)||\
+      defined(GPIO_TIM9_CH3OUT) ||defined(GPIO_TIM9_CH4OUT)
+#    define HAVE_TIM9_GPIOCONFIG 1
+#endif
+#endif
+
+#if defined(CONFIG_STM32F7_TIM10)
+#  if defined(GPIO_TIM10_CH1OUT) ||defined(GPIO_TIM10_CH2OUT)||\
+      defined(GPIO_TIM10_CH3OUT) ||defined(GPIO_TIM10_CH4OUT)
+#    define HAVE_TIM10_GPIOCONFIG 1
+#endif
+#endif
+
+#if defined(CONFIG_STM32F7_TIM11)
+#  if defined(GPIO_TIM11_CH1OUT) ||defined(GPIO_TIM11_CH2OUT)||\
+      defined(GPIO_TIM11_CH3OUT) ||defined(GPIO_TIM11_CH4OUT)
+#    define HAVE_TIM11_GPIOCONFIG 1
+#endif
+#endif
+
+#if defined(CONFIG_STM32F7_TIM12)
+#  if defined(GPIO_TIM12_CH1OUT) ||defined(GPIO_TIM12_CH2OUT)||\
+      defined(GPIO_TIM12_CH3OUT) ||defined(GPIO_TIM12_CH4OUT)
+#    define HAVE_TIM12_GPIOCONFIG 1
+#endif
+#endif
+
+#if defined(CONFIG_STM32F7_TIM13)
+#  if defined(GPIO_TIM13_CH1OUT) ||defined(GPIO_TIM13_CH2OUT)||\
+      defined(GPIO_TIM13_CH3OUT) ||defined(GPIO_TIM13_CH4OUT)
+#    define HAVE_TIM13_GPIOCONFIG 1
+#endif
+#endif
+
+#if defined(CONFIG_STM32F7_TIM14)
+#  if defined(GPIO_TIM14_CH1OUT) ||defined(GPIO_TIM14_CH2OUT)||\
+      defined(GPIO_TIM14_CH3OUT) ||defined(GPIO_TIM14_CH4OUT)
+#    define HAVE_TIM14_GPIOCONFIG 1
+#endif
+#endif
 
 
 /* This module then only compiles if there are enabled timers that are not intended for
  * some other purpose.
  */
 
-#if defined(CONFIG_STM32F7_TIM1) || defined(CONFIG_STM32F7_TIM2) || defined(CONFIG_STM32F7_TIM3) || \
-    defined(CONFIG_STM32F7_TIM4) || defined(CONFIG_STM32F7_TIM5) || defined(CONFIG_STM32F7_TIM6) || \
-    defined(CONFIG_STM32F7_TIM7) || defined(CONFIG_STM32F7_TIM8)
+#if defined(CONFIG_STM32F7_TIM1)  || defined(CONFIG_STM32F7_TIM2)  || \
+    defined(CONFIG_STM32F7_TIM3)  || defined(CONFIG_STM32F7_TIM4)  || \
+    defined(CONFIG_STM32F7_TIM5)  || defined(CONFIG_STM32F7_TIM6)  || \
+    defined(CONFIG_STM32F7_TIM7)  || defined(CONFIG_STM32F7_TIM8)  || \
+    defined(CONFIG_STM32F7_TIM9)  || defined(CONFIG_STM32F7_TIM10) || \
+    defined(CONFIG_STM32F7_TIM11) || defined(CONFIG_STM32F7_TIM12) || \
+    defined(CONFIG_STM32F7_TIM13) || defined(CONFIG_STM32F7_TIM14)
 
 /************************************************************************************
  * Private Types
@@ -311,9 +357,10 @@ static void stm32_tim_gpioconfig(uint32_t cfg, stm32_tim_channel_t mode)
 
 static int stm32_tim_setclock(FAR struct stm32_tim_dev_s *dev, uint32_t freq)
 {
+  uint32_t freqin;
   int prescaler;
 
-  ASSERT(dev);
+  DEBUGASSERT(dev != NULL);
 
   /* Disable Timer? */
 
@@ -323,20 +370,96 @@ static int stm32_tim_setclock(FAR struct stm32_tim_dev_s *dev, uint32_t freq)
       return 0;
     }
 
-#if STM32F7_NATIM > 0
-  if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM1_BASE ||
-      ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM8_BASE)
+  /* Get the input clock frequency for this timer.  These vary with
+   * different timer clock sources, MCU-specific timer configuration, and
+   * board-specific clock configuration.  The correct input clock frequency
+   * must be defined in the board.h header file.
+   */
+
+  switch (((struct stm32_tim_priv_s *)dev)->base)
     {
-      prescaler = STM32_TIM18_FREQUENCY / freq;
-    }
-  else
+#ifdef CONFIG_STM32F7_TIM1
+      case STM32_TIM1_BASE:
+        freqin = STM32_APB2_TIM1_CLKIN;
+        break;
 #endif
-    {
-      prescaler = STM32_TIM27_FREQUENCY / freq;
+#ifdef CONFIG_STM32F7_TIM2
+      case STM32_TIM2_BASE:
+        freqin = STM32_APB1_TIM2_CLKIN;
+        break;
+#endif
+#ifdef CONFIG_STM32F7_TIM3
+      case STM32_TIM3_BASE:
+        freqin = STM32_APB1_TIM3_CLKIN;
+        break;
+#endif
+#ifdef CONFIG_STM32F7_TIM4
+      case STM32_TIM4_BASE:
+        freqin = STM32_APB1_TIM4_CLKIN;
+        break;
+#endif
+#ifdef CONFIG_STM32F7_TIM5
+      case STM32_TIM5_BASE:
+        freqin = STM32_APB1_TIM5_CLKIN;
+        break;
+#endif
+#ifdef CONFIG_STM32F7_TIM6
+      case STM32_TIM6_BASE:
+        freqin = STM32_APB1_TIM6_CLKIN;
+        break;
+#endif
+#ifdef CONFIG_STM32F7_TIM7
+      case STM32_TIM7_BASE:
+        freqin = STM32_APB1_TIM7_CLKIN;
+        break;
+#endif
+#ifdef CONFIG_STM32F7_TIM8
+      case STM32_TIM8_BASE:
+        freqin = STM32_APB2_TIM8_CLKIN;
+        break;
+#endif
+#ifdef CONFIG_STM32F7_TIM9
+      case STM32_TIM9_BASE:
+        freqin = STM32_APB2_TIM9_CLKIN;
+        break;
+#endif
+#ifdef CONFIG_STM32F7_TIM10
+      case STM32_TIM10_BASE:
+        freqin = STM32_APB2_TIM10_CLKIN;
+        break;
+#endif
+#ifdef CONFIG_STM32F7_TIM11
+      case STM32_TIM11_BASE:
+        freqin = STM32_APB2_TIM11_CLKIN;
+        break;
+#endif
+#ifdef CONFIG_STM32F7_TIM12
+      case STM32_TIM12_BASE:
+        freqin = STM32_APB1_TIM12_CLKIN;
+        break;
+#endif
+#ifdef CONFIG_STM32F7_TIM13
+      case STM32_TIM13_BASE:
+        freqin = STM32_APB1_TIM13_CLKIN;
+        break;
+#endif
+#ifdef CONFIG_STM32F7_TIM14
+      case STM32_TIM14_BASE:
+        freqin = STM32_APB1_TIM14_CLKIN;
+        break;
+#endif
+      default:
+        return -EINVAL;
     }
 
-  /* We need to decrement value for '1', but only, if we are allowed to
-   * not to cause underflow. Check for overflow.
+  /* Select a pre-scaler value for this timer using the input clock
+   * frequency.
+   */
+
+  prescaler = freqin / freq;
+
+  /* We need to decrement value for '1', but only, if that will not to
+   * cause underflow.
    */
 
   if (prescaler > 0)
@@ -344,6 +467,8 @@ static int stm32_tim_setclock(FAR struct stm32_tim_dev_s *dev, uint32_t freq)
       prescaler--;
     }
 
+  /* Check for overflow as well. */
+
   if (prescaler > 0xffff)
     {
       prescaler = 0xffff;
@@ -358,7 +483,7 @@ static int stm32_tim_setclock(FAR struct stm32_tim_dev_s *dev, uint32_t freq)
 static void stm32_tim_setperiod(FAR struct stm32_tim_dev_s *dev,
                                 uint32_t period)
 {
-  ASSERT(dev);
+  DEBUGASSERT(dev != NULL);
   stm32_putreg32(dev, STM32_BTIM_ARR_OFFSET, period);
 }
 
@@ -368,11 +493,16 @@ static int stm32_tim_setisr(FAR struct stm32_tim_dev_s *dev,
 {
   int vectorno;
 
-  ASSERT(dev);
-  ASSERT(source == 0);
+  DEBUGASSERT(dev != NULL);
+  DEBUGASSERT(source == 0);
 
   switch (((struct stm32_tim_priv_s *)dev)->base)
     {
+#ifdef CONFIG_STM32F7_TIM1
+      case STM32_TIM1_BASE:
+        vectorno = STM32_IRQ_TIM1UP;
+        break;
+#endif
 #ifdef CONFIG_STM32F7_TIM2
       case STM32_TIM2_BASE:
         vectorno = STM32_IRQ_TIM2;
@@ -393,36 +523,54 @@ static int stm32_tim_setisr(FAR struct stm32_tim_dev_s *dev,
         vectorno = STM32_IRQ_TIM5;
         break;
 #endif
-#if STM32F7_NBTIM > 0
 #ifdef CONFIG_STM32F7_TIM6
       case STM32_TIM6_BASE:
         vectorno = STM32_IRQ_TIM6;
         break;
 #endif
-#endif
-#if STM32F7_NBTIM > 1
 #ifdef CONFIG_STM32F7_TIM7
       case STM32_TIM7_BASE:
         vectorno = STM32_IRQ_TIM7;
         break;
 #endif
-#endif
-#if STM32F7_NATIM > 0
-      /* TODO: add support for multiple sources and callbacks */
-
-#ifdef CONFIG_STM32F7_TIM1
-      case STM32_TIM1_BASE:
-        vectorno = STM32_IRQ_TIM1UP;
-        break;
-#endif
 #ifdef CONFIG_STM32F7_TIM8
       case STM32_TIM8_BASE:
         vectorno = STM32_IRQ_TIM8UP;
         break;
 #endif
+#ifdef CONFIG_STM32F7_TIM9
+      case STM32_TIM9_BASE:
+        vectorno = STM32_IRQ_TIM9;
+        break;
 #endif
+#ifdef CONFIG_STM32F7_TIM10
+      case STM32_TIM10_BASE:
+        vectorno = STM32_IRQ_TIM10;
+        break;
+#endif
+#ifdef CONFIG_STM32F7_TIM11
+      case STM32_TIM11_BASE:
+        vectorno = STM32_IRQ_TIM11;
+        break;
+#endif
+#ifdef CONFIG_STM32F7_TIM12
+      case STM32_TIM12_BASE:
+        vectorno = STM32_IRQ_TIM12;
+        break;
+#endif
+#ifdef CONFIG_STM32F7_TIM13
+      case STM32_TIM13_BASE:
+        vectorno = STM32_IRQ_TIM13;
+        break;
+#endif
+#ifdef CONFIG_STM32F7_TIM14
+      case STM32_TIM14_BASE:
+        vectorno = STM32_IRQ_TIM14;
+        break;
+#endif
+
       default:
-        return ERROR;
+        return -EINVAL;
     }
 
   /* Disable interrupt when callback is removed */
@@ -450,13 +598,13 @@ static int stm32_tim_setisr(FAR struct stm32_tim_dev_s *dev,
 
 static void stm32_tim_enableint(FAR struct stm32_tim_dev_s *dev, int source)
 {
-  ASSERT(dev);
+  DEBUGASSERT(dev != NULL);
   stm32_modifyreg16(dev, STM32_BTIM_DIER_OFFSET, 0, ATIM_DIER_UIE);
 }
 
 static void stm32_tim_disableint(FAR struct stm32_tim_dev_s *dev, int source)
 {
-  ASSERT(dev);
+  DEBUGASSERT(dev != NULL);
   stm32_modifyreg16(dev, STM32_BTIM_DIER_OFFSET, ATIM_DIER_UIE, 0);
 }
 
@@ -473,24 +621,17 @@ static int stm32_tim_setmode(FAR struct stm32_tim_dev_s *dev, stm32_tim_mode_t m
 {
   uint16_t val = ATIM_CR1_CEN | ATIM_CR1_ARPE;
 
-  ASSERT(dev);
+  DEBUGASSERT(dev != NULL);
 
   /* This function is not supported on basic timers. To enable or
    * disable it, simply set its clock to valid frequency or zero.
    */
 
-#if STM32F7_NBTIM > 0
-  if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE
-#endif
-#if STM32F7_NBTIM > 1
-      ||  ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE
-#endif
-#if STM32F7_NBTIM > 0
-  )
+  if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE || \
+      ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE)
     {
-      return ERROR;
+      return -EINVAL;
     }
-#endif
 
   /* Decode operational modes */
 
@@ -516,13 +657,12 @@ static int stm32_tim_setmode(FAR struct stm32_tim_dev_s *dev, stm32_tim_mode_t m
         break;
 
       default:
-        return ERROR;
+        return -EINVAL;
     }
 
   stm32_tim_reload_counter(dev);
   stm32_putreg16(dev, STM32_BTIM_CR1_OFFSET, val);
 
-#if STM32F7_NATIM > 0
   /* Advanced registers require Main Output Enable */
 
     if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM1_BASE ||
@@ -530,7 +670,6 @@ static int stm32_tim_setmode(FAR struct stm32_tim_dev_s *dev, stm32_tim_mode_t m
       {
         stm32_modifyreg16(dev, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE);
       }
-#endif
 
   return OK;
 }
@@ -544,13 +683,13 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint8_t channel
   uint16_t ccer_val    = stm32_getreg16(dev, STM32_GTIM_CCER_OFFSET);
   uint8_t  ccmr_offset = STM32_GTIM_CCMR1_OFFSET;
 
-  ASSERT(dev);
+  DEBUGASSERT(dev != NULL);
 
   /* Further we use range as 0..3; if channel=0 it will also overflow here */
 
   if (--channel > 4)
     {
-      return ERROR;
+      return -EINVAL;
     }
 
   /* Assume that channel is disabled and polarity is active high */
@@ -561,18 +700,12 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint8_t channel
    * disable it, simply set its clock to valid frequency or zero.
    */
 
-#if STM32F7_NBTIM > 0
-  if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE
-#endif
-#if STM32F7_NBTIM > 1
-      || ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE
-#endif
-#if STM32F7_NBTIM > 0
-  )
+  if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE || \
+      ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE)
     {
-      return ERROR;
+      return -EINVAL;
     }
-#endif
+
 
   /* Decode configuration */
 
@@ -587,7 +720,7 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint8_t channel
         break;
 
       default:
-        return ERROR;
+        return -EINVAL;
     }
 
   /* Set polarity */
@@ -620,32 +753,57 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint8_t channel
 
   switch (((struct stm32_tim_priv_s *)dev)->base)
     {
+#ifdef CONFIG_STM32F7_TIM1
+      case STM32_TIM1_BASE:
+        switch (channel)
+          {
+#  if defined(GPIO_TIM1_CH1OUT)
+            case 0:
+              stm32_tim_gpioconfig(GPIO_TIM1_CH1OUT, mode); break;
+#  endif
+#  if defined(GPIO_TIM1_CH2OUT)
+            case 1:
+              stm32_tim_gpioconfig(GPIO_TIM1_CH2OUT, mode); break;
+#  endif
+#  if defined(GPIO_TIM1_CH3OUT)
+            case 2:
+              stm32_tim_gpioconfig(GPIO_TIM1_CH3OUT, mode); break;
+#  endif
+#  if defined(GPIO_TIM1_CH4OUT)
+            case 3:
+              stm32_tim_gpioconfig(GPIO_TIM1_CH4OUT, mode); break;
+#  endif
+            default:
+              return -EINVAL;
+          }
+        break;
+#endif
 #ifdef CONFIG_STM32F7_TIM2
       case STM32_TIM2_BASE:
         switch (channel)
           {
-#if defined(GPIO_TIM2_CH1OUT)
+#  if defined(GPIO_TIM2_CH1OUT)
             case 0:
               stm32_tim_gpioconfig(GPIO_TIM2_CH1OUT, mode);
               break;
-#endif
-#if defined(GPIO_TIM2_CH2OUT)
+#  endif
+#  if defined(GPIO_TIM2_CH2OUT)
             case 1:
               stm32_tim_gpioconfig(GPIO_TIM2_CH2OUT, mode);
               break;
-#endif
-#if defined(GPIO_TIM2_CH3OUT)
+#  endif
+#  if defined(GPIO_TIM2_CH3OUT)
             case 2:
               stm32_tim_gpioconfig(GPIO_TIM2_CH3OUT, mode);
               break;
-#endif
-#if defined(GPIO_TIM2_CH4OUT)
+#  endif
+#  if defined(GPIO_TIM2_CH4OUT)
             case 3:
               stm32_tim_gpioconfig(GPIO_TIM2_CH4OUT, mode);
               break;
 #endif
             default:
-              return ERROR;
+              return -EINVAL;
           }
         break;
 #endif
@@ -653,28 +811,28 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint8_t channel
       case STM32_TIM3_BASE:
         switch (channel)
           {
-#if defined(GPIO_TIM3_CH1OUT)
+#  if defined(GPIO_TIM3_CH1OUT)
             case 0:
               stm32_tim_gpioconfig(GPIO_TIM3_CH1OUT, mode);
               break;
-#endif
-#if defined(GPIO_TIM3_CH2OUT)
+#  endif
+#  if defined(GPIO_TIM3_CH2OUT)
             case 1:
               stm32_tim_gpioconfig(GPIO_TIM3_CH2OUT, mode);
               break;
-#endif
-#if defined(GPIO_TIM3_CH3OUT)
+#  endif
+#  if defined(GPIO_TIM3_CH3OUT)
             case 2:
               stm32_tim_gpioconfig(GPIO_TIM3_CH3OUT, mode);
               break;
-#endif
-#if defined(GPIO_TIM3_CH4OUT)
+#  endif
+#  if defined(GPIO_TIM3_CH4OUT)
             case 3:
               stm32_tim_gpioconfig(GPIO_TIM3_CH4OUT, mode);
               break;
 #endif
             default:
-              return ERROR;
+              return -EINVAL;
           }
         break;
 #endif
@@ -682,28 +840,28 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint8_t channel
       case STM32_TIM4_BASE:
         switch (channel)
           {
-#if defined(GPIO_TIM4_CH1OUT)
+#  if defined(GPIO_TIM4_CH1OUT)
             case 0:
               stm32_tim_gpioconfig(GPIO_TIM4_CH1OUT, mode);
               break;
-#endif
-#if defined(GPIO_TIM4_CH2OUT)
+#  endif
+#  if defined(GPIO_TIM4_CH2OUT)
             case 1:
               stm32_tim_gpioconfig(GPIO_TIM4_CH2OUT, mode);
               break;
-#endif
-#if defined(GPIO_TIM4_CH3OUT)
+#  endif
+#  if defined(GPIO_TIM4_CH3OUT)
             case 2:
               stm32_tim_gpioconfig(GPIO_TIM4_CH3OUT, mode);
               break;
-#endif
-#if defined(GPIO_TIM4_CH4OUT)
+#  endif
+#  if defined(GPIO_TIM4_CH4OUT)
             case 3:
               stm32_tim_gpioconfig(GPIO_TIM4_CH4OUT, mode);
               break;
-#endif
+#  endif
             default:
-              return ERROR;
+              return -EINVAL;
           }
         break;
 #endif
@@ -711,55 +869,28 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint8_t channel
       case STM32_TIM5_BASE:
         switch (channel)
           {
-#if defined(GPIO_TIM5_CH1OUT)
+#  if defined(GPIO_TIM5_CH1OUT)
             case 0:
               stm32_tim_gpioconfig(GPIO_TIM5_CH1OUT, mode);
               break;
-#endif
-#if defined(GPIO_TIM5_CH2OUT)
+#  endif
+#  if defined(GPIO_TIM5_CH2OUT)
             case 1:
               stm32_tim_gpioconfig(GPIO_TIM5_CH2OUT, mode);
               break;
-#endif
-#if defined(GPIO_TIM5_CH3OUT)
+#  endif
+#  if defined(GPIO_TIM5_CH3OUT)
             case 2:
               stm32_tim_gpioconfig(GPIO_TIM5_CH3OUT, mode);
               break;
-#endif
-#if defined(GPIO_TIM5_CH4OUT)
+#  endif
+#  if defined(GPIO_TIM5_CH4OUT)
             case 3:
               stm32_tim_gpioconfig(GPIO_TIM5_CH4OUT, mode);
               break;
-#endif
+#  endif
             default:
-              return ERROR;
-          }
-        break;
-#endif
-
-#if STM32F7_NATIM > 0
-#ifdef CONFIG_STM32F7_TIM1
-      case STM32_TIM1_BASE:
-        switch (channel)
-          {
-#if defined(GPIO_TIM1_CH1OUT)
-            case 0:
-              stm32_tim_gpioconfig(GPIO_TIM1_CH1OUT, mode); break;
-#endif
-#if defined(GPIO_TIM1_CH2OUT)
-            case 1:
-              stm32_tim_gpioconfig(GPIO_TIM1_CH2OUT, mode); break;
-#endif
-#if defined(GPIO_TIM1_CH3OUT)
-            case 2:
-              stm32_tim_gpioconfig(GPIO_TIM1_CH3OUT, mode); break;
-#endif
-#if defined(GPIO_TIM1_CH4OUT)
-            case 3:
-              stm32_tim_gpioconfig(GPIO_TIM1_CH4OUT, mode); break;
-#endif
-            default:
-              return ERROR;
+              return -EINVAL;
           }
         break;
 #endif
@@ -767,39 +898,209 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint8_t channel
       case STM32_TIM8_BASE:
         switch (channel)
           {
-#if defined(GPIO_TIM8_CH1OUT)
+#  if defined(GPIO_TIM8_CH1OUT)
             case 0:
               stm32_tim_gpioconfig(GPIO_TIM8_CH1OUT, mode); break;
-#endif
-#if defined(GPIO_TIM8_CH2OUT)
+#  endif
+#  if defined(GPIO_TIM8_CH2OUT)
             case 1:
               stm32_tim_gpioconfig(GPIO_TIM8_CH2OUT, mode); break;
-#endif
-#if defined(GPIO_TIM8_CH3OUT)
+#  endif
+#  if defined(GPIO_TIM8_CH3OUT)
             case 2:
               stm32_tim_gpioconfig(GPIO_TIM8_CH3OUT, mode); break;
-#endif
-#if defined(GPIO_TIM8_CH4OUT)
+#  endif
+#  if defined(GPIO_TIM8_CH4OUT)
             case 3:
               stm32_tim_gpioconfig(GPIO_TIM8_CH4OUT, mode); break;
-#endif
+#  endif
             default:
-              return ERROR;
+              return -EINVAL;
           }
         break;
 #endif
-#endif
+#  ifdef CONFIG_STM32F7_TIM9
+      case STM32_TIM9_BASE:
+        switch (channel)
+          {
+#  if defined(GPIO_TIM9_CH1OUT)
+            case 0:
+              stm32_tim_gpioconfig(GPIO_TIM9_CH1OUT, mode);
+              break;
+#  endif
+#  if defined(GPIO_TIM9_CH2OUT)
+            case 1:
+              stm32_tim_gpioconfig(GPIO_TIM9_CH2OUT, mode);
+              break;
+#  endif
+#  if defined(GPIO_TIM9_CH3OUT)
+            case 2:
+              stm32_tim_gpioconfig(GPIO_TIM9_CH3OUT, mode);
+              break;
+# endif
+#  if defined(GPIO_TIM9_CH4OUT)
+            case 3:
+              stm32_tim_gpioconfig(GPIO_TIM9_CH4OUT, mode);
+              break;
+#  endif
       default:
-        return ERROR;
+              return -EINVAL;
+          }
+        break;
+#endif
+#ifdef CONFIG_STM32F7_TIM10
+      case STM32_TIM10_BASE:
+        switch (channel)
+          {
+#  if defined(GPIO_TIM10_CH1OUT)
+            case 0:
+              stm32_tim_gpioconfig(GPIO_TIM10_CH1OUT, mode);
+              break;
+#  endif
+#  if defined(GPIO_TIM10_CH2OUT)
+            case 1:
+              stm32_tim_gpioconfig(GPIO_TIM10_CH2OUT, mode);
+              break;
+#  endif
+#  if defined(GPIO_TIM10_CH3OUT)
+            case 2:
+              stm32_tim_gpioconfig(GPIO_TIM10_CH3OUT, mode);
+              break;
+#  endif
+#  if defined(GPIO_TIM10_CH4OUT)
+            case 3:
+              stm32_tim_gpioconfig(GPIO_TIM10_CH4OUT, mode);
+              break;
+#  endif
+            default:
+              return -EINVAL;
+          }
+        break;
+#endif
+#ifdef CONFIG_STM32F7_TIM11
+      case STM32_TIM11_BASE:
+        switch (channel)
+          {
+#  if defined(GPIO_TIM11_CH1OUT)
+            case 0:
+              stm32_tim_gpioconfig(GPIO_TIM11_CH1OUT, mode);
+              break;
+#  endif
+#  if defined(GPIO_TIM11_CH2OUT)
+            case 1:
+              stm32_tim_gpioconfig(GPIO_TIM11_CH2OUT, mode);
+              break;
+#  endif
+#  if defined(GPIO_TIM11_CH3OUT)
+            case 2:
+              stm32_tim_gpioconfig(GPIO_TIM11_CH3OUT, mode);
+              break;
+#  endif
+#  if defined(GPIO_TIM11_CH4OUT)
+            case 3:
+              stm32_tim_gpioconfig(GPIO_TIM11_CH4OUT, mode);
+              break;
+#  endif
+            default:
+              return -EINVAL;
+          }
+        break;
+#endif
+#ifdef CONFIG_STM32F7_TIM12
+      case STM32_TIM12_BASE:
+        switch (channel)
+          {
+#  if defined(GPIO_TIM12_CH1OUT)
+            case 0:
+              stm32_tim_gpioconfig(GPIO_TIM12_CH1OUT, mode);
+              break;
+#  endif
+#  if defined(GPIO_TIM12_CH2OUT)
+            case 1:
+              stm32_tim_gpioconfig(GPIO_TIM12_CH2OUT, mode);
+              break;
+#  endif
+#  if defined(GPIO_TIM12_CH3OUT)
+            case 2:
+              stm32_tim_gpioconfig(GPIO_TIM12_CH3OUT, mode);
+              break;
+#  endif
+#  if defined(GPIO_TIM12_CH4OUT)
+            case 3:
+              stm32_tim_gpioconfig(GPIO_TIM12_CH4OUT, mode);
+              break;
+#  endif
+            default:
+              return -EINVAL;
+          }
+        break;
+#endif
+#ifdef CONFIG_STM32F7_TIM13
+      case STM32_TIM13_BASE:
+        switch (channel)
+          {
+#  if defined(GPIO_TIM13_CH1OUT)
+            case 0:
+              stm32_tim_gpioconfig(GPIO_TIM13_CH1OUT, mode);
+              break;
+#  endif
+#  if defined(GPIO_TIM13_CH2OUT)
+            case 1:
+              stm32_tim_gpioconfig(GPIO_TIM13_CH2OUT, mode);
+              break;
+#  endif
+#  if defined(GPIO_TIM13_CH3OUT)
+            case 2:
+              stm32_tim_gpioconfig(GPIO_TIM13_CH3OUT, mode);
+              break;
+#  endif
+#  if defined(GPIO_TIM13_CH4OUT)
+            case 3:
+              stm32_tim_gpioconfig(GPIO_TIM13_CH4OUT, mode);
+              break;
+#  endif
+            default:
+              return -EINVAL;
+          }
+        break;
+#endif
+#ifdef CONFIG_STM32F7_TIM14
+      case STM32_TIM14_BASE:
+        switch (channel)
+          {
+#  if defined(GPIO_TIM14_CH1OUT)
+            case 0:
+              stm32_tim_gpioconfig(GPIO_TIM14_CH1OUT, mode);
+              break;
+#  endif
+#  if defined(GPIO_TIM14_CH2OUT)
+            case 1:
+              stm32_tim_gpioconfig(GPIO_TIM14_CH2OUT, mode);
+              break;
+#  endif
+#  if defined(GPIO_TIM14_CH3OUT)
+            case 2:
+              stm32_tim_gpioconfig(GPIO_TIM14_CH3OUT, mode);
+              break;
+#  endif
+#  if defined(GPIO_TIM14_CH4OUT)
+            case 3:
+              stm32_tim_gpioconfig(GPIO_TIM14_CH4OUT, mode);
+              break;
+#  endif
+            default:
+              return -EINVAL;
+          }
+        break;
+#endif
     }
-
   return OK;
 }
 
 static int stm32_tim_setcompare(FAR struct stm32_tim_dev_s *dev, uint8_t channel,
                                 uint32_t compare)
 {
-  ASSERT(dev);
+  DEBUGASSERT(dev != NULL);
 
   switch (channel)
     {
@@ -816,14 +1117,14 @@ static int stm32_tim_setcompare(FAR struct stm32_tim_dev_s *dev, uint8_t channel
         stm32_putreg32(dev, STM32_GTIM_CCR4_OFFSET, compare);
         break;
       default:
-        return ERROR;
+        return -EINVAL;
     }
   return OK;
 }
 
 static int stm32_tim_getcapture(FAR struct stm32_tim_dev_s *dev, uint8_t channel)
 {
-  ASSERT(dev);
+  DEBUGASSERT(dev != NULL);
 
   switch (channel)
     {
@@ -837,7 +1138,7 @@ static int stm32_tim_getcapture(FAR struct stm32_tim_dev_s *dev, uint8_t channel
         return stm32_getreg32(dev, STM32_GTIM_CCR4_OFFSET);
     }
 
-  return ERROR;
+  return -EINVAL;
 }
 
 /************************************************************************************
@@ -864,6 +1165,14 @@ struct stm32_tim_ops_s stm32_tim_ops =
   .ackint         = &stm32_tim_ackint
 };
 
+#ifdef CONFIG_STM32F7_TIM1
+struct stm32_tim_priv_s stm32_tim1_priv =
+{
+  .ops        = &stm32_tim_ops,
+  .mode       = STM32_TIM_MODE_UNUSED,
+  .base       = STM32_TIM1_BASE,
+};
+#endif
 #ifdef CONFIG_STM32F7_TIM2
 struct stm32_tim_priv_s stm32_tim2_priv =
 {
@@ -900,7 +1209,6 @@ struct stm32_tim_priv_s stm32_tim5_priv =
 };
 #endif
 
-#if STM32F7_NBTIM > 0
 #ifdef CONFIG_STM32F7_TIM6
 struct stm32_tim_priv_s stm32_tim6_priv =
 {
@@ -909,9 +1217,7 @@ struct stm32_tim_priv_s stm32_tim6_priv =
   .base       = STM32_TIM6_BASE,
 };
 #endif
-#endif
 
-#if STM32F7_NBTIM > 1
 #ifdef CONFIG_STM32F7_TIM7
 struct stm32_tim_priv_s stm32_tim7_priv =
 {
@@ -920,18 +1226,6 @@ struct stm32_tim_priv_s stm32_tim7_priv =
   .base       = STM32_TIM7_BASE,
 };
 #endif
-#endif
-
-#if STM32F7_NATIM > 0
-
-#ifdef CONFIG_STM32F7_TIM1
-struct stm32_tim_priv_s stm32_tim1_priv =
-{
-  .ops        = &stm32_tim_ops,
-  .mode       = STM32_TIM_MODE_UNUSED,
-  .base       = STM32_TIM1_BASE,
-};
-#endif
 
 #ifdef CONFIG_STM32F7_TIM8
 struct stm32_tim_priv_s stm32_tim8_priv =
@@ -942,8 +1236,61 @@ struct stm32_tim_priv_s stm32_tim8_priv =
 };
 #endif
 
+#ifdef CONFIG_STM32F7_TIM9
+struct stm32_tim_priv_s stm32_tim9_priv =
+{
+  .ops        = &stm32_tim_ops,
+  .mode       = STM32_TIM_MODE_UNUSED,
+  .base       = STM32_TIM9_BASE,
+};
 #endif
 
+#ifdef CONFIG_STM32F7_TIM10
+struct stm32_tim_priv_s stm32_tim10_priv =
+{
+  .ops        = &stm32_tim_ops,
+  .mode       = STM32_TIM_MODE_UNUSED,
+  .base       = STM32_TIM10_BASE,
+};
+#endif
+
+#ifdef CONFIG_STM32F7_TIM11
+struct stm32_tim_priv_s stm32_tim11_priv =
+{
+  .ops        = &stm32_tim_ops,
+  .mode       = STM32_TIM_MODE_UNUSED,
+  .base       = STM32_TIM11_BASE,
+};
+#endif
+
+#ifdef CONFIG_STM32F7_TIM12
+struct stm32_tim_priv_s stm32_tim12_priv =
+{
+  .ops        = &stm32_tim_ops,
+  .mode       = STM32_TIM_MODE_UNUSED,
+  .base       = STM32_TIM12_BASE,
+};
+#endif
+
+#ifdef CONFIG_STM32F7_TIM13
+struct stm32_tim_priv_s stm32_tim13_priv =
+{
+  .ops        = &stm32_tim_ops,
+  .mode       = STM32_TIM_MODE_UNUSED,
+  .base       = STM32_TIM13_BASE,
+};
+#endif
+
+#ifdef CONFIG_STM32F7_TIM14
+struct stm32_tim_priv_s stm32_tim14_priv =
+{
+  .ops        = &stm32_tim_ops,
+  .mode       = STM32_TIM_MODE_UNUSED,
+  .base       = STM32_TIM14_BASE,
+};
+#endif
+
+
 /************************************************************************************
  * Public Function - Initialization
  ************************************************************************************/
@@ -956,6 +1303,12 @@ FAR struct stm32_tim_dev_s *stm32_tim_init(int timer)
 
   switch (timer)
     {
+#ifdef CONFIG_STM32F7_TIM1
+      case 1:
+        dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv;
+        modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN);
+        break;
+#endif
 #ifdef CONFIG_STM32F7_TIM2
       case 2:
         dev = (struct stm32_tim_dev_s *)&stm32_tim2_priv;
@@ -980,37 +1333,59 @@ FAR struct stm32_tim_dev_s *stm32_tim_init(int timer)
         modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM5EN);
         break;
 #endif
-
-#if STM32F7_NBTIM > 0
 #ifdef CONFIG_STM32F7_TIM6
       case 6:
         dev = (struct stm32_tim_dev_s *)&stm32_tim6_priv;
         modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM6EN);
         break;
 #endif
-#endif
-#if STM32F7_NBTIM > 1
 #ifdef CONFIG_STM32F7_TIM7
       case 7:
         dev = (struct stm32_tim_dev_s *)&stm32_tim7_priv;
         modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM7EN);
         break;
 #endif
-#endif
-
-#if STM32F7_NATIM > 0
-#ifdef CONFIG_STM32F7_TIM1
-      case 1:
-        dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv;
-        modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN);
-        break;
-#endif
 #ifdef CONFIG_STM32F7_TIM8
       case 8:
         dev = (struct stm32_tim_dev_s *)&stm32_tim8_priv;
         modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN);
         break;
 #endif
+#ifdef CONFIG_STM32F7_TIM9
+      case 9:
+        dev = (struct stm32_tim_dev_s *)&stm32_tim9_priv;
+        modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM9EN);
+        break;
+#endif
+#ifdef CONFIG_STM32F7_TIM10
+      case 10:
+        dev = (struct stm32_tim_dev_s *)&stm32_tim10_priv;
+        modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM10EN);
+        break;
+#endif
+#ifdef CONFIG_STM32F7_TIM11
+      case 11:
+        dev = (struct stm32_tim_dev_s *)&stm32_tim11_priv;
+        modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM11EN);
+        break;
+#endif
+#ifdef CONFIG_STM32F7_TIM12
+      case 12:
+        dev = (struct stm32_tim_dev_s *)&stm32_tim12_priv;
+        modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM12EN);
+        break;
+#endif
+#ifdef CONFIG_STM32F7_TIM13
+      case 13:
+        dev = (struct stm32_tim_dev_s *)&stm32_tim13_priv;
+        modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM13EN);
+        break;
+#endif
+#ifdef CONFIG_STM32F7_TIM14
+      case 14:
+        dev = (struct stm32_tim_dev_s *)&stm32_tim14_priv;
+        modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM14EN);
+        break;
 #endif
       default:
         return NULL;
@@ -1032,12 +1407,17 @@ FAR struct stm32_tim_dev_s *stm32_tim_init(int timer)
 
 int stm32_tim_deinit(FAR struct stm32_tim_dev_s * dev)
 {
-  ASSERT(dev);
+  DEBUGASSERT(dev != NULL);
 
   /* Disable power */
 
   switch (((struct stm32_tim_priv_s *)dev)->base)
     {
+#ifdef CONFIG_STM32F7_TIM1
+      case STM32_TIM1_BASE:
+        modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0);
+        break;
+#endif
 #ifdef CONFIG_STM32F7_TIM2
       case STM32_TIM2_BASE:
         modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM2EN, 0);
@@ -1058,35 +1438,53 @@ int stm32_tim_deinit(FAR struct stm32_tim_dev_s * dev)
         modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM5EN, 0);
         break;
 #endif
-#if STM32F7_NBTIM > 0
 #ifdef CONFIG_STM32F7_TIM6
       case STM32_TIM6_BASE:
         modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM6EN, 0);
         break;
 #endif
-#endif
-#if STM32F7_NBTIM > 1
 #ifdef CONFIG_STM32F7_TIM7
       case STM32_TIM7_BASE:
         modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM7EN, 0);
         break;
 #endif
-#endif
-
-#if STM32F7_NATIM > 0
-#ifdef CONFIG_STM32F7_TIM1
-      case STM32_TIM1_BASE:
-        modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0);
-        break;
-#endif
 #ifdef CONFIG_STM32F7_TIM8
       case STM32_TIM8_BASE:
         modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0);
         break;
 #endif
+#ifdef CONFIG_STM32F7_TIM9
+      case STM32_TIM9_BASE:
+        modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM9EN, 0);
+        break;
+#endif
+#ifdef CONFIG_STM32F7_TIM10
+      case STM32_TIM10_BASE:
+        modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM10EN, 0);
+        break;
+#endif
+#ifdef CONFIG_STM32F7_TIM11
+      case STM32_TIM11_BASE:
+        modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM11EN, 0);
+        break;
+#endif
+#ifdef CONFIG_STM32F7_TIM12
+      case STM32_TIM12_BASE:
+        modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM12EN, 0);
+        break;
+#endif
+#ifdef CONFIG_STM32F7_TIM13
+      case STM32_TIM13_BASE:
+        modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM13EN, 0);
+        break;
+#endif
+#ifdef CONFIG_STM32F7_TIM14
+      case STM32_TIM14_BASE:
+        modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM14EN, 0);
+        break;
 #endif
       default:
-        return ERROR;
+        return -EINVAL;
     }
 
   /* Mark it as free */
diff --git a/arch/arm/src/stm32f7/stm32_uart.h b/arch/arm/src/stm32f7/stm32_uart.h
index 9b1bce0b4e6..d250eb77612 100644
--- a/arch/arm/src/stm32f7/stm32_uart.h
+++ b/arch/arm/src/stm32f7/stm32_uart.h
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_STC_STM32F7_STM32_UART_H
-#define __ARCH_ARM_STC_STM32F7_STM32_UART_H
+#ifndef __ARCH_ARM_SRC_STM32F7_STM32_UART_H
+#define __ARCH_ARM_SRC_STM32F7_STM32_UART_H
 
 /************************************************************************************
  * Included Files
@@ -342,4 +342,4 @@ void stm32_serial_dma_poll(void);
 #endif
 
 #endif /* __ASSEMBLY__ */
-#endif /* __ARCH_ARM_STC_STM32F7_STM32_UART_H */
+#endif /* __ARCH_ARM_SRC_STM32F7_STM32_UART_H */
diff --git a/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c b/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c
index 1db43d25513..7ae301548a0 100644
--- a/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c
+++ b/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c
@@ -1,8 +1,9 @@
 /****************************************************************************
  * arch/arm/src/stm32f7/stm32f74xxx75xx_rcc.c
  *
- *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ *   Authors: Gregory Nutt <gnutt@nuttx.org>
+ *            David Sidrane <david_s5@nscdg.com>
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -827,18 +828,38 @@ static void stm32_stdclockconfig(void)
         {
         }
 
-#ifdef CONFIG_STM32F7_LTDC
-      /* Configure PLLSAI */
+#if defined(CONFIG_STM32F7_LTDC) || defined(CONFIG_STM32F7_PLLSAI)
+
+       /* Configure PLLSAI */
 
       regval = getreg32(STM32_RCC_PLLSAICFGR);
+      regval &= ~(  RCC_PLLSAICFGR_PLLSAIN_MASK
+                  | RCC_PLLSAICFGR_PLLSAIP_MASK
+                  | RCC_PLLSAICFGR_PLLSAIQ_MASK
+                  | RCC_PLLSAICFGR_PLLSAIR_MASK);
       regval |= (STM32_RCC_PLLSAICFGR_PLLSAIN
-                | STM32_RCC_PLLSAICFGR_PLLSAIR
-                | STM32_RCC_PLLSAICFGR_PLLSAIQ);
+                 | STM32_RCC_PLLSAICFGR_PLLSAIP
+                 | STM32_RCC_PLLSAICFGR_PLLSAIQ
+                 | STM32_RCC_PLLSAICFGR_PLLSAIR);
       putreg32(regval, STM32_RCC_PLLSAICFGR);
 
-      regval = getreg32(STM32_RCC_DCKCFGR);
-      regval |= STM32_RCC_DCKCFGR_PLLSAIDIVR;
-      putreg32(regval, STM32_RCC_DCKCFGR);
+      regval  = getreg32(STM32_RCC_DCKCFGR1);
+      regval &= ~(RCC_DCKCFGR1_PLLI2SDIVQ_MASK
+                  | RCC_DCKCFGR1_PLLSAIDIVQ_MASK
+                  | RCC_DCKCFGR1_PLLSAIDIVR_MASK
+                  | RCC_DCKCFGR1_SAI1SEL_MASK
+                  | RCC_DCKCFGR1_SAI2SEL_MASK
+                  | RCC_DCKCFGR1_TIMPRESEL);
+
+      regval |= (STM32_RCC_DCKCFGR1_PLLI2SDIVQ
+                 | STM32_RCC_DCKCFGR1_PLLSAIDIVQ
+                 | STM32_RCC_DCKCFGR1_PLLSAIDIVR
+                 | STM32_RCC_DCKCFGR1_SAI1SRC
+                 | STM32_RCC_DCKCFGR1_SAI2SRC
+                 | STM32_RCC_DCKCFGR1_TIMPRESRC);
+
+      putreg32(regval, STM32_RCC_DCKCFGR1);
+
 
       /* Enable PLLSAI */
 
@@ -852,6 +873,68 @@ static void stm32_stdclockconfig(void)
         {
         }
 #endif
+#if defined(CONFIG_STM32F7_LTDC) || defined(CONFIG_STM32F7_PLLI2S)
+
+      /* Configure PLLI2S */
+
+      regval = getreg32(STM32_RCC_PLLI2SCFGR);
+      regval &= ~(  RCC_PLLI2SCFGR_PLLI2SN_MASK
+                  | RCC_PLLI2SCFGR_PLLI2SP_MASK
+                  | RCC_PLLI2SCFGR_PLLI2SQ_MASK
+                  | RCC_PLLI2SCFGR_PLLI2SR_MASK);
+      regval |= (STM32_RCC_PLLSAICFGR_PLLSAIN
+                 | STM32_RCC_PLLSAICFGR_PLLSAIP
+                 | STM32_RCC_PLLSAICFGR_PLLSAIQ
+                 | STM32_RCC_PLLSAICFGR_PLLSAIR);
+      putreg32(regval, STM32_RCC_PLLI2SCFGR);
+
+      regval  = getreg32(STM32_RCC_DCKCFGR2);
+      regval &= ~(  RCC_DCKCFGR2_USART1SEL_MASK
+                  | RCC_DCKCFGR2_USART2SEL_MASK
+                  | RCC_DCKCFGR2_UART4SEL_MASK
+                  | RCC_DCKCFGR2_UART5SEL_MASK
+                  | RCC_DCKCFGR2_USART6SEL_MASK
+                  | RCC_DCKCFGR2_UART7SEL_MASK
+                  | RCC_DCKCFGR2_UART8SEL_MASK
+                  | RCC_DCKCFGR2_I2C1SEL_MASK
+                  | RCC_DCKCFGR2_I2C2SEL_MASK
+                  | RCC_DCKCFGR2_I2C3SEL_MASK
+                  | RCC_DCKCFGR2_I2C4SEL_MASK
+                  | RCC_DCKCFGR2_LPTIM1SEL_MASK
+                  | RCC_DCKCFGR2_CECSEL_MASK
+                  | RCC_DCKCFGR2_CK48MSEL_MASK
+                  | RCC_DCKCFGR2_SDMMCSEL_MASK);
+
+      regval |= (  STM32_RCC_DCKCFGR2_USART1SRC
+                 | STM32_RCC_DCKCFGR2_USART2SRC
+                 | STM32_RCC_DCKCFGR2_UART4SRC
+                 | STM32_RCC_DCKCFGR2_UART5SRC
+                 | STM32_RCC_DCKCFGR2_USART6SRC
+                 | STM32_RCC_DCKCFGR2_UART7SRC
+                 | STM32_RCC_DCKCFGR2_UART8SRC
+                 | STM32_RCC_DCKCFGR2_I2C1SRC
+                 | STM32_RCC_DCKCFGR2_I2C2SRC
+                 | STM32_RCC_DCKCFGR2_I2C3SRC
+                 | STM32_RCC_DCKCFGR2_I2C4SRC
+                 | STM32_RCC_DCKCFGR2_LPTIM1SRC
+                 | STM32_RCC_DCKCFGR2_CECSRC
+                 | STM32_RCC_DCKCFGR2_CK48MSRC
+                 | STM32_RCC_DCKCFGR2_SDMMCSRC);
+
+      putreg32(regval, STM32_RCC_DCKCFGR2);
+
+      /* Enable PLLI2S */
+
+      regval = getreg32(STM32_RCC_CR);
+      regval |= RCC_CR_PLLI2SON;
+      putreg32(regval, STM32_RCC_CR);
+
+      /* Wait until the PLLI2S is ready */
+
+      while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLI2SRDY) == 0)
+        {
+        }
+#endif
 
 #if defined(CONFIG_STM32F7_IWDG) || defined(CONFIG_RTC_LSICLOCK)
       /* Low speed internal clock source LSI */
diff --git a/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c b/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c
index 74d58b52ade..d24705d5fd6 100644
--- a/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c
+++ b/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c
@@ -224,6 +224,7 @@ static inline void rcc_enableahb1(void)
   /* USB OTG HS */
 
   regval |= RCC_AHB1ENR_OTGHSEN;
+
 #endif  /* CONFIG_STM32F7_OTGHS */
 
   putreg32(regval, STM32_RCC_AHB1ENR);   /* Enable peripherals */
@@ -823,18 +824,41 @@ static void stm32_stdclockconfig(void)
         {
         }
 
-#ifdef CONFIG_STM32F7_LTDC
+#if defined(CONFIG_STM32F7_LTDC) || defined(CONFIG_STM32F7_PLLSAI)
+
       /* Configure PLLSAI */
 
       regval = getreg32(STM32_RCC_PLLSAICFGR);
+      regval &= ~(  RCC_PLLSAICFGR_PLLSAIN_MASK
+                  | RCC_PLLSAICFGR_PLLSAIP_MASK
+                  | RCC_PLLSAICFGR_PLLSAIQ_MASK
+                  | RCC_PLLSAICFGR_PLLSAIR_MASK);
       regval |= (STM32_RCC_PLLSAICFGR_PLLSAIN
-                | STM32_RCC_PLLSAICFGR_PLLSAIR
-                | STM32_RCC_PLLSAICFGR_PLLSAIQ);
+                 | STM32_RCC_PLLSAICFGR_PLLSAIP
+                 | STM32_RCC_PLLSAICFGR_PLLSAIQ
+                 | STM32_RCC_PLLSAICFGR_PLLSAIR);
       putreg32(regval, STM32_RCC_PLLSAICFGR);
 
-      regval = getreg32(STM32_RCC_DCKCFGR);
-      regval |= STM32_RCC_DCKCFGR_PLLSAIDIVR;
-      putreg32(regval, STM32_RCC_DCKCFGR);
+      regval  = getreg32(STM32_RCC_DCKCFGR1);
+      regval &= ~(RCC_DCKCFGR1_PLLI2SDIVQ_MASK
+                  | RCC_DCKCFGR1_PLLSAIDIVQ_MASK
+                  | RCC_DCKCFGR1_PLLSAIDIVR_MASK
+                  | RCC_DCKCFGR1_SAI1SEL_MASK
+                  | RCC_DCKCFGR1_SAI2SEL_MASK
+                  | RCC_DCKCFGR1_TIMPRESEL
+                  | RCC_DCKCFGR1_DFSDM1SEL
+                  | RCC_DCKCFGR1_ADFSDM1SEL);
+
+      regval |= (STM32_RCC_DCKCFGR1_PLLI2SDIVQ
+                 | STM32_RCC_DCKCFGR1_PLLSAIDIVQ
+                 | STM32_RCC_DCKCFGR1_PLLSAIDIVR
+                 | STM32_RCC_DCKCFGR1_SAI1SRC
+                 | STM32_RCC_DCKCFGR1_SAI2SRC
+                 | STM32_RCC_DCKCFGR1_TIMPRESRC
+                 | STM32_RCC_DCKCFGR1_DFSDM1SRC
+                 | STM32_RCC_DCKCFGR1_ADFSDM1SRC);
+
+      putreg32(regval, STM32_RCC_DCKCFGR1);
 
       /* Enable PLLSAI */
 
@@ -848,6 +872,72 @@ static void stm32_stdclockconfig(void)
         {
         }
 #endif
+#if defined(CONFIG_STM32F7_LTDC) || defined(CONFIG_STM32F7_PLLI2S)
+
+      /* Configure PLLI2S */
+
+      regval = getreg32(STM32_RCC_PLLI2SCFGR);
+      regval &= ~(  RCC_PLLI2SCFGR_PLLI2SN_MASK
+                  | RCC_PLLI2SCFGR_PLLI2SP_MASK
+                  | RCC_PLLI2SCFGR_PLLI2SQ_MASK
+                  | RCC_PLLI2SCFGR_PLLI2SR_MASK);
+      regval |= (STM32_RCC_PLLSAICFGR_PLLSAIN
+                 | STM32_RCC_PLLSAICFGR_PLLSAIP
+                 | STM32_RCC_PLLSAICFGR_PLLSAIQ
+                 | STM32_RCC_PLLSAICFGR_PLLSAIR);
+      putreg32(regval, STM32_RCC_PLLI2SCFGR);
+
+      regval  = getreg32(STM32_RCC_DCKCFGR2);
+      regval &= ~(  RCC_DCKCFGR2_USART1SEL_MASK
+                  | RCC_DCKCFGR2_USART2SEL_MASK
+                  | RCC_DCKCFGR2_UART4SEL_MASK
+                  | RCC_DCKCFGR2_UART5SEL_MASK
+                  | RCC_DCKCFGR2_USART6SEL_MASK
+                  | RCC_DCKCFGR2_UART7SEL_MASK
+                  | RCC_DCKCFGR2_UART8SEL_MASK
+                  | RCC_DCKCFGR2_I2C1SEL_MASK
+                  | RCC_DCKCFGR2_I2C2SEL_MASK
+                  | RCC_DCKCFGR2_I2C3SEL_MASK
+                  | RCC_DCKCFGR2_I2C4SEL_MASK
+                  | RCC_DCKCFGR2_LPTIM1SEL_MASK
+                  | RCC_DCKCFGR2_CECSEL_MASK
+                  | RCC_DCKCFGR2_CK48MSEL_MASK
+                  | RCC_DCKCFGR2_SDMMCSEL_MASK
+                  | RCC_DCKCFGR2_SDMMC2SEL_MASK
+                  | RCC_DCKCFGR2_DSISELL_MASK);
+
+      regval |= (  STM32_RCC_DCKCFGR2_USART1SRC
+                 | STM32_RCC_DCKCFGR2_USART2SRC
+                 | STM32_RCC_DCKCFGR2_UART4SRC
+                 | STM32_RCC_DCKCFGR2_UART5SRC
+                 | STM32_RCC_DCKCFGR2_USART6SRC
+                 | STM32_RCC_DCKCFGR2_UART7SRC
+                 | STM32_RCC_DCKCFGR2_UART8SRC
+                 | STM32_RCC_DCKCFGR2_I2C1SRC
+                 | STM32_RCC_DCKCFGR2_I2C2SRC
+                 | STM32_RCC_DCKCFGR2_I2C3SRC
+                 | STM32_RCC_DCKCFGR2_I2C4SRC
+                 | STM32_RCC_DCKCFGR2_LPTIM1SRC
+                 | STM32_RCC_DCKCFGR2_CECSRC
+                 | STM32_RCC_DCKCFGR2_CK48MSRC
+                 | STM32_RCC_DCKCFGR2_SDMMCSRC
+                 | STM32_RCC_DCKCFGR2_SDMMC2SRC
+                 | STM32_RCC_DCKCFGR2_DSISRC);
+
+      putreg32(regval, STM32_RCC_DCKCFGR2);
+
+      /* Enable PLLI2S */
+
+      regval = getreg32(STM32_RCC_CR);
+      regval |= RCC_CR_PLLI2SON;
+      putreg32(regval, STM32_RCC_CR);
+
+      /* Wait until the PLLI2S is ready */
+
+      while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLI2SRDY) == 0)
+        {
+        }
+#endif
 
 #if defined(CONFIG_STM32F7_IWDG) || defined(CONFIG_RTC_LSICLOCK)
       /* Low speed internal clock source LSI */
diff --git a/arch/arm/src/stm32l4/Kconfig b/arch/arm/src/stm32l4/Kconfig
index 1724fe81247..143230fa5b9 100644
--- a/arch/arm/src/stm32l4/Kconfig
+++ b/arch/arm/src/stm32l4/Kconfig
@@ -871,7 +871,7 @@ config CAN1_BAUD
 	default 250000
 	depends on STM32L4_CAN1
 	---help---
-		CAN1 BAUD rate.  Required if STM32L4_CAN1 is defined.
+		CAN1 BAUD rate.  Required if CONFIG_STM32L4_CAN1 is defined.
 
 config CAN_TSEG1
 	int "TSEG1 quanta"
@@ -884,6 +884,15 @@ config CAN_TSEG2
 	default 7
 	---help---
 		The number of CAN time quanta in segment 2. Default: 7
+
+config STM32L4_CAN_REGDEBUG
+	bool "CAN Register level debug"
+	depends on DEBUG_CAN_INFO
+	default n
+	---help---
+		Output detailed register-level CAN device debug information.
+		Requires also CONFIG_DEBUG_CAN_INFO.
+
 endmenu
 
 endif # ARCH_CHIP_STM32L4
diff --git a/arch/arm/src/stm32l4/stm32l4_can.c b/arch/arm/src/stm32l4/stm32l4_can.c
index cff88f9b934..4d239c2fc3e 100644
--- a/arch/arm/src/stm32l4/stm32l4_can.c
+++ b/arch/arm/src/stm32l4/stm32l4_can.c
@@ -83,7 +83,7 @@
 #define CAN_BIT_QUANTA (CONFIG_CAN_TSEG1 + CONFIG_CAN_TSEG2 + 1)
 
 #ifndef CONFIG_DEBUG_CAN_INFO
-#  undef CONFIG_STM32_CAN_REGDEBUG
+#  undef CONFIG_STM32L4_CAN_REGDEBUG
 #endif
 
 /****************************************************************************
@@ -107,14 +107,14 @@ struct stm32l4_can_s
 
 /* CAN Register access */
 
-static uint32_t can_getreg(struct stm32l4_can_s *priv, int offset);
-static uint32_t can_getfreg(struct stm32l4_can_s *priv, int offset);
-static void can_putreg(struct stm32l4_can_s *priv, int offset, uint32_t value);
-static void can_putfreg(struct stm32l4_can_s *priv, int offset, uint32_t value);
-#ifdef CONFIG_STM32_CAN_REGDEBUG
-static void can_dumpctrlregs(struct stm32l4_can_s *priv, FAR const char *msg);
-static void can_dumpmbregs(struct stm32l4_can_s *priv, FAR const char *msg);
-static void can_dumpfiltregs(struct stm32l4_can_s *priv, FAR const char *msg);
+static uint32_t can_getreg(FAR struct stm32l4_can_s *priv, int offset);
+static uint32_t can_getfreg(FAR struct stm32l4_can_s *priv, int offset);
+static void can_putreg(FAR struct stm32l4_can_s *priv, int offset, uint32_t value);
+static void can_putfreg(FAR struct stm32l4_can_s *priv, int offset, uint32_t value);
+#ifdef CONFIG_STM32L4_CAN_REGDEBUG
+static void can_dumpctrlregs(FAR struct stm32l4_can_s *priv, FAR const char *msg);
+static void can_dumpmbregs(FAR struct stm32l4_can_s *priv, FAR const char *msg);
+static void can_dumpfiltregs(FAR struct stm32l4_can_s *priv, FAR const char *msg);
 #else
 #  define can_dumpctrlregs(priv,msg)
 #  define can_dumpmbregs(priv,msg)
@@ -136,14 +136,23 @@ static bool can_txempty(FAR struct can_dev_s *dev);
 
 /* CAN interrupt handling */
 
-static int  can_rx0interrupt(int irq, void *context);
-static int  can_txinterrupt(int irq, void *context);
+static int  can_rx0interrupt(int irq, FAR void *context);
+static int  can_txinterrupt(int irq, FAR void *context);
 
 /* Initialization */
 
-static int  can_bittiming(struct stm32l4_can_s *priv);
-static int  can_cellinit(struct stm32l4_can_s *priv);
-static int  can_filterinit(struct stm32l4_can_s *priv);
+static int  can_enterinitmode(FAR struct stm32l4_can_s *priv);
+static int  can_exitinitmode(FAR struct stm32l4_can_s *priv);
+static int  can_bittiming(FAR struct stm32l4_can_s *priv);
+static int  can_cellinit(FAR struct stm32l4_can_s *priv);
+static int  can_filterinit(FAR struct stm32l4_can_s *priv);
+
+/* Filtering (todo) */
+
+static int  stm32l4_can_addextfilter(FAR struct stm32l4_can_s *priv, FAR struct canioc_extfilter_s *arg);
+static int  stm32l4_can_delextfilter(FAR struct stm32l4_can_s *priv, int arg);
+static int  stm32l4_can_addstdfilter(FAR struct stm32l4_can_s *priv, FAR struct canioc_stdfilter_s *arg);
+static int  stm32l4_can_delstdfilter(FAR struct stm32l4_can_s *priv, int arg);
 
 /****************************************************************************
  * Private Data
@@ -201,7 +210,7 @@ static struct can_dev_s g_can1dev =
  *
  ****************************************************************************/
 
-#ifdef CONFIG_STM32_CAN_REGDEBUG
+#ifdef CONFIG_STM32L4_CAN_REGDEBUG
 static uint32_t can_vgetreg(uint32_t addr)
 {
   static uint32_t prevaddr = 0;
@@ -255,23 +264,23 @@ static uint32_t can_vgetreg(uint32_t addr)
   return val;
 }
 
-static uint32_t can_getreg(struct stm32l4_can_s *priv, int offset)
+static uint32_t can_getreg(FAR struct stm32l4_can_s *priv, int offset)
 {
   return can_vgetreg(priv->base + offset);
 }
 
-static uint32_t can_getfreg(struct stm32l4_can_s *priv, int offset)
+static uint32_t can_getfreg(FAR struct stm32l4_can_s *priv, int offset)
 {
   return can_vgetreg(priv->fbase + offset);
 }
 
 #else
-static uint32_t can_getreg(struct stm32l4_can_s *priv, int offset)
+static uint32_t can_getreg(FAR struct stm32l4_can_s *priv, int offset)
 {
   return getreg32(priv->base + offset);
 }
 
-static uint32_t can_getfreg(struct stm32l4_can_s *priv, int offset)
+static uint32_t can_getfreg(FAR struct stm32l4_can_s *priv, int offset)
 {
   return getreg32(priv->fbase + offset);
 }
@@ -295,7 +304,7 @@ static uint32_t can_getfreg(struct stm32l4_can_s *priv, int offset)
  *
  ****************************************************************************/
 
-#ifdef CONFIG_STM32_CAN_REGDEBUG
+#ifdef CONFIG_STM32L4_CAN_REGDEBUG
 static void can_vputreg(uint32_t addr, uint32_t value)
 {
   /* Show the register value being written */
@@ -307,23 +316,23 @@ static void can_vputreg(uint32_t addr, uint32_t value)
   putreg32(value, addr);
 }
 
-static void can_putreg(struct stm32l4_can_s *priv, int offset, uint32_t value)
+static void can_putreg(FAR struct stm32l4_can_s *priv, int offset, uint32_t value)
 {
   can_vputreg(priv->base + offset, value);
 }
 
-static void can_putfreg(struct stm32l4_can_s *priv, int offset, uint32_t value)
+static void can_putfreg(FAR struct stm32l4_can_s *priv, int offset, uint32_t value)
 {
   can_vputreg(priv->fbase + offset, value);
 }
 
 #else
-static void can_putreg(struct stm32l4_can_s *priv, int offset, uint32_t value)
+static void can_putreg(FAR struct stm32l4_can_s *priv, int offset, uint32_t value)
 {
   putreg32(value, priv->base + offset);
 }
 
-static void can_putfreg(struct stm32l4_can_s *priv, int offset, uint32_t value)
+static void can_putfreg(FAR struct stm32l4_can_s *priv, int offset, uint32_t value)
 {
   putreg32(value, priv->fbase + offset);
 }
@@ -343,8 +352,8 @@ static void can_putfreg(struct stm32l4_can_s *priv, int offset, uint32_t value)
  *
  ****************************************************************************/
 
-#ifdef CONFIG_STM32_CAN_REGDEBUG
-static void can_dumpctrlregs(struct stm32l4_can_s *priv, FAR const char *msg)
+#ifdef CONFIG_STM32L4_CAN_REGDEBUG
+static void can_dumpctrlregs(FAR struct stm32l4_can_s *priv, FAR const char *msg)
 {
   if (msg)
     {
@@ -387,8 +396,8 @@ static void can_dumpctrlregs(struct stm32l4_can_s *priv, FAR const char *msg)
  *
  ****************************************************************************/
 
-#ifdef CONFIG_STM32_CAN_REGDEBUG
-static void can_dumpmbregs(struct stm32l4_can_s *priv, FAR const char *msg)
+#ifdef CONFIG_STM32L4_CAN_REGDEBUG
+static void can_dumpmbregs(FAR struct stm32l4_can_s *priv, FAR const char *msg)
 {
   if (msg)
     {
@@ -447,8 +456,8 @@ static void can_dumpmbregs(struct stm32l4_can_s *priv, FAR const char *msg)
  *
  ****************************************************************************/
 
-#ifdef CONFIG_STM32_CAN_REGDEBUG
-static void can_dumpfiltregs(struct stm32l4_can_s *priv, FAR const char *msg)
+#ifdef CONFIG_STM32L4_CAN_REGDEBUG
+static void can_dumpfiltregs(FAR struct stm32l4_can_s *priv, FAR const char *msg)
 {
   int i;
 
@@ -499,7 +508,7 @@ static void can_reset(FAR struct can_dev_s *dev)
   uint32_t regbit = 0;
   irqstate_t flags;
 
-  canllinfo("CAN%d\n", priv->port);
+  caninfo("CAN%d\n", priv->port);
 
   /* Get the bits in the AHB1RSTR1 register needed to reset this CAN device */
 
@@ -554,7 +563,7 @@ static int can_setup(FAR struct can_dev_s *dev)
   FAR struct stm32l4_can_s *priv = dev->cd_priv;
   int ret;
 
-  canllinfo("CAN%d RX0 irq: %d TX irq: %d\n", priv->port, priv->canrx0, priv->cantx);
+  caninfo("CAN%d RX0 irq: %d TX irq: %d\n", priv->port, priv->canrx0, priv->cantx);
 
   /* CAN cell initialization */
 
@@ -624,7 +633,7 @@ static void can_shutdown(FAR struct can_dev_s *dev)
 {
   FAR struct stm32l4_can_s *priv = dev->cd_priv;
 
-  canllinfo("CAN%d\n", priv->port);
+  caninfo("CAN%d\n", priv->port);
 
   /* Disable the RX FIFO 0 and TX interrupts */
 
@@ -660,7 +669,7 @@ static void can_rxint(FAR struct can_dev_s *dev, bool enable)
   FAR struct stm32l4_can_s *priv = dev->cd_priv;
   uint32_t regval;
 
-  canllinfo("CAN%d enable: %d\n", priv->port, enable);
+  caninfo("CAN%d enable: %d\n", priv->port, enable);
 
   /* Enable/disable the FIFO 0 message pending interrupt */
 
@@ -696,7 +705,7 @@ static void can_txint(FAR struct can_dev_s *dev, bool enable)
   FAR struct stm32l4_can_s *priv = dev->cd_priv;
   uint32_t regval;
 
-  canllinfo("CAN%d enable: %d\n", priv->port, enable);
+  caninfo("CAN%d enable: %d\n", priv->port, enable);
 
   /* Support only disabling the transmit mailbox interrupt */
 
@@ -724,9 +733,241 @@ static void can_txint(FAR struct can_dev_s *dev, bool enable)
 
 static int can_ioctl(FAR struct can_dev_s *dev, int cmd, unsigned long arg)
 {
-  /* No CAN ioctls are supported */
+  FAR struct stm32l4_can_s *priv;
+  int ret = -ENOTTY;
 
-  return -ENOTTY;
+  caninfo("cmd=%04x arg=%lu\n", cmd, arg);
+
+  DEBUGASSERT(dev && dev->cd_priv);
+  priv = dev->cd_priv;
+
+  /* Handle the command */
+
+  switch (cmd)
+    {
+      /* CANIOC_GET_BITTIMING:
+       *   Description:    Return the current bit timing settings
+       *   Argument:       A pointer to a write-able instance of struct
+       *                   canioc_bittiming_s in which current bit timing values
+       *                   will be returned.
+       *   Returned Value: Zero (OK) is returned on success.  Otherwise -1 (ERROR)
+       *                   is returned with the errno variable set to indicate the
+       *                   nature of the error.
+       *   Dependencies:   None
+       */
+
+      case CANIOC_GET_BITTIMING:
+        {
+          FAR struct canioc_bittiming_s *bt =
+            (FAR struct canioc_bittiming_s *)arg;
+          uint32_t regval;
+          uint32_t brp;
+
+          DEBUGASSERT(bt != NULL);
+          regval       = can_getreg(priv, STM32L4_CAN_BTR_OFFSET);
+          bt->bt_sjw   = ((regval & CAN_BTR_SJW_MASK) >> CAN_BTR_SJW_SHIFT) + 1;
+          bt->bt_tseg1 = ((regval & CAN_BTR_TS1_MASK) >> CAN_BTR_TS1_SHIFT) + 1;
+          bt->bt_tseg2 = ((regval & CAN_BTR_TS2_MASK) >> CAN_BTR_TS2_SHIFT) + 1;
+
+          brp          = ((regval & CAN_BTR_BRP_MASK) >> CAN_BTR_BRP_SHIFT) + 1;
+          bt->bt_baud  = STM32L4_PCLK1_FREQUENCY /
+                         (brp * (bt->bt_tseg1 + bt->bt_tseg2 + 1));
+          ret = OK;
+        }
+        break;
+
+      /* CANIOC_SET_BITTIMING:
+       *   Description:    Set new current bit timing values
+       *   Argument:       A pointer to a read-able instance of struct
+       *                   canioc_bittiming_s in which the new bit timing values
+       *                   are provided.
+       *   Returned Value: Zero (OK) is returned on success.  Otherwise -1 (ERROR)
+       *                   is returned with the errno variable set to indicate the
+       *                   nature of the error.
+       *   Dependencies:   None
+       *
+       * REVISIT: There is probably a limitation here:  If there are multiple
+       * threads trying to send CAN packets, when one of these threads reconfigures
+       * the bitrate, the MCAN hardware will be reset and the context of operation
+       * will be lost.  Hence, this IOCTL can only safely be executed in quiescent
+       * time periods.
+       */
+
+      case CANIOC_SET_BITTIMING:
+        {
+          FAR const struct canioc_bittiming_s *bt =
+            (FAR const struct canioc_bittiming_s *)arg;
+          uint32_t brp;
+          uint32_t can_bit_quanta;
+          uint32_t tmp;
+
+          DEBUGASSERT(bt != NULL);
+          DEBUGASSERT(bt->bt_baud < STM32L4_PCLK1_FREQUENCY);
+          DEBUGASSERT(bt->bt_sjw > 0 && bt->bt_sjw <= 4);
+          DEBUGASSERT(bt->bt_tseg1 > 0 && bt->bt_tseg1 <= 16);
+          DEBUGASSERT(bt->bt_tseg2 > 0 && bt->bt_tseg2 <=  8);
+
+          /* Extract bit timing data */
+          /* tmp is in clocks per bit time */
+
+          tmp = STM32L4_PCLK1_FREQUENCY / bt->bt_baud;
+
+          /* This value is dynamic as requested by user */
+
+          can_bit_quanta = bt->bt_tseg1 + bt->bt_tseg2 + 1;
+
+          if (tmp < can_bit_quanta)
+            {
+#if 0
+              /* At the smallest brp value (1), there are already too few
+               * bit times (PCLK1 / baud) to meet our goal.  brp must be one
+               * and we need make some reasonable guesses about ts1 and ts2.
+               */
+
+              brp = 1;
+
+              /* In this case, we have to guess a good value for ts1 and ts2 */
+
+              tseg1 = (tmp - 1) >> 1; /* cut available time in half */
+              tseg2 = tmp - tseg1 - 1; /* ts2 uses the rest minus one */
+
+              /* if we can, try to approximate the CAN requirements,
+               * which are not exactly "cut baud time in half"
+               */
+
+              if (tseg1 == tseg2 && tseg1 > 1 && tseg2 < CAN_BTR_TSEG2_MAX)
+                {
+                  tseg1--;
+                  tseg2++;
+                }
+#else
+              ret = -EINVAL;
+#endif
+            }
+
+          /* Otherwise, nquanta is can_bit_quanta, ts1 and ts2 are provided
+           * by the user and we calculate brp to achieve can_bit_quanta
+           * quanta in the bit time
+           */
+
+          else
+            {
+              brp = (tmp + (can_bit_quanta/2)) / can_bit_quanta;
+              DEBUGASSERT(brp >= 1 && brp <= CAN_BTR_BRP_MAX);
+            }
+
+          caninfo("TS1: %d TS2: %d BRP: %d\n", bt->bt_tseg1, bt->bt_tseg2, brp);
+
+          /* Configure bit timing.  This also does the following, less obvious
+           * things.  Unless loopback mode is enabled, it:
+           *
+           * - Disables silent mode.
+           * - Disables loopback mode.
+           *
+           */
+
+          tmp = ((brp          - 1) << CAN_BTR_BRP_SHIFT) |
+                ((bt->bt_tseg1 - 1) << CAN_BTR_TS1_SHIFT) |
+                ((bt->bt_tseg2 - 1) << CAN_BTR_TS2_SHIFT) |
+                ((bt->bt_sjw   - 1) << CAN_BTR_SJW_SHIFT);
+#ifdef CONFIG_CAN_LOOPBACK
+          tmp |= CAN_BTR_LBKM;
+#endif
+
+          /* Bit timing can only be configured in init mode.
+           * No registers are changed.
+           */
+
+          ret = can_enterinitmode(priv);
+          if (ret != 0)
+            {
+              break;
+            }
+
+          can_putreg(priv, STM32L4_CAN_BTR_OFFSET, tmp);
+          ret = can_exitinitmode(priv);
+
+          if (ret == 0)
+            {
+              priv->baud  = STM32L4_PCLK1_FREQUENCY / (brp * (bt->bt_tseg1 + bt->bt_tseg2 + 1));
+            }
+        }
+        break;
+
+#ifdef CONFIG_CAN_EXTID
+      /* CANIOC_ADD_EXTFILTER:
+       *   Description:    Add an address filter for a extended 29 bit
+       *                   address.
+       *   Argument:       A reference to struct canioc_extfilter_s
+       *   Returned Value: A non-negative filter ID is returned on success.
+       *                   Otherwise -1 (ERROR) is returned with the errno
+       *                   variable set to indicate the nature of the error.
+       */
+
+      case CANIOC_ADD_EXTFILTER:
+        {
+          DEBUGASSERT(arg != 0);
+          ret = stm32l4_can_addextfilter(priv, (FAR struct canioc_extfilter_s *)arg);
+        }
+        break;
+
+      /* CANIOC_DEL_EXTFILTER:
+       *   Description:    Remove an address filter for a standard 29 bit address.
+       *   Argument:       The filter index previously returned by the
+       *                   CANIOC_ADD_EXTFILTER command
+       *   Returned Value: Zero (OK) is returned on success.  Otherwise -1 (ERROR)
+       *                   is returned with the errno variable set to indicate the
+       *                   nature of the error.
+       */
+
+      case CANIOC_DEL_EXTFILTER:
+        {
+          DEBUGASSERT(arg <= priv->config->nextfilters);
+          ret = stm32l4_can_delextfilter(priv, (int)arg);
+        }
+        break;
+#endif
+
+      /* CANIOC_ADD_STDFILTER:
+       *   Description:    Add an address filter for a standard 11 bit
+       *                   address.
+       *   Argument:       A reference to struct canioc_stdfilter_s
+       *   Returned Value: A non-negative filter ID is returned on success.
+       *                   Otherwise -1 (ERROR) is returned with the errno
+       *                   variable set to indicate the nature of the error.
+       */
+
+      case CANIOC_ADD_STDFILTER:
+        {
+          DEBUGASSERT(arg != 0);
+          ret = stm32l4_can_addstdfilter(priv, (FAR struct canioc_stdfilter_s *)arg);
+        }
+        break;
+
+      /* CANIOC_DEL_STDFILTER:
+       *   Description:    Remove an address filter for a standard 11 bit address.
+       *   Argument:       The filter index previously returned by the
+       *                   CANIOC_ADD_STDFILTER command
+       *   Returned Value: Zero (OK) is returned on success.  Otherwise -1 (ERROR)
+       *                   is returned with the errno variable set to indicate the
+       *                   nature of the error.
+       */
+
+      case CANIOC_DEL_STDFILTER:
+        {
+          DEBUGASSERT(arg <= priv->config->nstdfilters);
+          ret = stm32l4_can_delstdfilter(priv, (int)arg);
+        }
+        break;
+
+      /* Unsupported/unrecognized command */
+
+      default:
+        canerr("ERROR: Unrecognized command: %04x\n", cmd);
+        break;
+    }
+
+  return ret;
 }
 
 /****************************************************************************
@@ -781,7 +1022,8 @@ static int can_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg)
   int dlc;
   int txmb;
 
-  canllinfo("CAN%d ID: %d DLC: %d\n", priv->port, msg->cm_hdr.ch_id, msg->cm_hdr.ch_dlc);
+  caninfo("CAN%d ID: %d DLC: %d\n",
+          priv->port, msg->cm_hdr.ch_id, msg->cm_hdr.ch_dlc);
 
   /* Select one empty transmit mailbox */
 
@@ -934,7 +1176,7 @@ static bool can_txready(FAR struct can_dev_s *dev)
   /* Return true if any mailbox is available */
 
   regval = can_getreg(priv, STM32L4_CAN_TSR_OFFSET);
-  canllinfo("CAN%d TSR: %08x\n", priv->port, regval);
+  caninfo("CAN%d TSR: %08x\n", priv->port, regval);
 
   if ((regval & CAN_ALL_MAILBOXES) != 0)
     {
@@ -970,7 +1212,7 @@ static bool can_txempty(FAR struct can_dev_s *dev)
   /* Return true if all mailboxes are available */
 
   regval = can_getreg(priv, STM32L4_CAN_TSR_OFFSET);
-  canllinfo("CAN%d TSR: %08x\n", priv->port, regval);
+  caninfo("CAN%d TSR: %08x\n", priv->port, regval);
 
   if ((regval & CAN_ALL_MAILBOXES) == CAN_ALL_MAILBOXES)
     {
@@ -995,7 +1237,7 @@ static bool can_txempty(FAR struct can_dev_s *dev)
  *
  ****************************************************************************/
 
-static int can_rx0interrupt(int irq, void *context)
+static int can_rx0interrupt(int irq, FAR void *context)
 {
   FAR struct can_dev_s *dev = NULL;
   FAR struct stm32l4_can_s *priv;
@@ -1106,7 +1348,7 @@ errout:
  *
  ****************************************************************************/
 
-static int can_txinterrupt(int irq, void *context)
+static int can_txinterrupt(int irq, FAR void *context)
 {
   FAR struct can_dev_s *dev = NULL;
   FAR struct stm32l4_can_s *priv;
@@ -1226,6 +1468,7 @@ static int can_txinterrupt(int irq, void *context)
  *   Tbs1 = Tq * ts1
  *   Tbs2 = Tq * ts2
  *   Tq = brp * Tpclk1
+ *   baud = Fpclk1 / (brp  * (1 + ts1 + ts2)))
  *
  * Where:
  *   Tpclk1 is the period of the APB1 clock (PCLK1).
@@ -1238,15 +1481,15 @@ static int can_txinterrupt(int irq, void *context)
  *
  ****************************************************************************/
 
-static int can_bittiming(struct stm32l4_can_s *priv)
+static int can_bittiming(FAR struct stm32l4_can_s *priv)
 {
   uint32_t tmp;
   uint32_t brp;
   uint32_t ts1;
   uint32_t ts2;
 
-  canllinfo("CAN%d PCLK1: %d baud: %d\n",
-            priv->port, STM32L4_PCLK1_FREQUENCY, priv->baud);
+  caninfo("CAN%d PCLK1: %d baud: %d\n",
+          priv->port, STM32L4_PCLK1_FREQUENCY, priv->baud);
 
   /* Try to get CAN_BIT_QUANTA quanta in one bit_time.
    *
@@ -1299,7 +1542,7 @@ static int can_bittiming(struct stm32l4_can_s *priv)
       DEBUGASSERT(brp >= 1 && brp <= CAN_BTR_BRP_MAX);
     }
 
-  canllinfo("TS1: %d TS2: %d BRP: %d\n", ts1, ts2, brp);
+  caninfo("TS1: %d TS2: %d BRP: %d\n", ts1, ts2, brp);
 
   /* Configure bit timing.  This also does the following, less obvious
    * things.  Unless loopback mode is enabled, it:
@@ -1323,10 +1566,12 @@ static int can_bittiming(struct stm32l4_can_s *priv)
 }
 
 /****************************************************************************
- * Name: can_cellinit
+ * Name: can_enterinitmode
  *
  * Description:
- *   CAN cell initialization
+ *   Put the CAN cell in Initialization mode. This only disconnects the CAN
+ *   peripheral, no registers are changed. The initialization mode is
+ *   required to change the baud rate.
  *
  * Input Parameter:
  *   priv - A pointer to the private data structure for this CAN block
@@ -1336,27 +1581,17 @@ static int can_bittiming(struct stm32l4_can_s *priv)
  *
  ****************************************************************************/
 
-static int can_cellinit(struct stm32l4_can_s *priv)
+static int can_enterinitmode(FAR struct stm32l4_can_s *priv)
 {
-  volatile uint32_t timeout;
   uint32_t regval;
+  volatile uint32_t timeout;
   int ret;
 
-  canllinfo("CAN%d\n", priv->port);
-
-  /* Exit from sleep mode */
-
-  regval  = can_getreg(priv, STM32L4_CAN_MCR_OFFSET);
-  regval &= ~CAN_MCR_SLEEP;
-  can_putreg(priv, STM32L4_CAN_MCR_OFFSET, regval);
-
-  /* Configure CAN behavior.  Priority driven request order, not message ID. */
-
-  regval |= CAN_MCR_TXFP;
-  can_putreg(priv, STM32L4_CAN_MCR_OFFSET, regval);
+  caninfo("CAN%d\n", priv->port);
 
   /* Enter initialization mode */
 
+  regval  = can_getreg(priv, STM32L4_CAN_MCR_OFFSET);
   regval |= CAN_MCR_INRQ;
   can_putreg(priv, STM32L4_CAN_MCR_OFFSET, regval);
 
@@ -1381,30 +1616,29 @@ static int can_cellinit(struct stm32l4_can_s *priv)
       return -ETIMEDOUT;
     }
 
-  /* Disable the following modes:
-   *
-   *  - Time triggered communication mode
-   *  - Automatic bus-off management
-   *  - Automatic wake-up mode
-   *  - No automatic retransmission
-   *  - Receive FIFO locked mode
-   *  - Transmit FIFO priority
-   */
+  return 0;
+}
 
-  regval   = can_getreg(priv, STM32L4_CAN_MCR_OFFSET);
-  regval &= ~(CAN_MCR_TXFP | CAN_MCR_RFLM | CAN_MCR_NART | CAN_MCR_AWUM | CAN_MCR_ABOM | CAN_MCR_TTCM);
-  can_putreg(priv, STM32L4_CAN_MCR_OFFSET, regval);
+/****************************************************************************
+ * Name: can_exitinitmode
+ *
+ * Description:
+ *   Put the CAN cell out of the Initialization mode (to Normal mode)
+ *
+ * Input Parameter:
+ *   priv - A pointer to the private data structure for this CAN block
+ *
+ * Returned Value:
+ *   Zero on success; a negated errno value on failure.
+ *
+ ****************************************************************************/
 
-  /* Configure bit timing. */
+static int can_exitinitmode(FAR struct stm32l4_can_s *priv)
+{
+  uint32_t regval;
+  volatile uint32_t timeout;
 
-  ret = can_bittiming(priv);
-  if (ret < 0)
-    {
-      canerr("ERROR: Failed to set bit timing: %d\n", ret);
-      return ret;
-    }
-
-  /* Exit initialization mode */
+  /* Exit Initialization mode, enter Normal mode */
 
   regval  = can_getreg(priv, STM32L4_CAN_MCR_OFFSET);
   regval &= ~CAN_MCR_INRQ;
@@ -1431,7 +1665,72 @@ static int can_cellinit(struct stm32l4_can_s *priv)
       return -ETIMEDOUT;
     }
 
-  return OK;
+  return 0;
+}
+
+/****************************************************************************
+ * Name: can_cellinit
+ *
+ * Description:
+ *   CAN cell initialization
+ *
+ * Input Parameter:
+ *   priv - A pointer to the private data structure for this CAN block
+ *
+ * Returned Value:
+ *   Zero on success; a negated errno value on failure.
+ *
+ ****************************************************************************/
+
+static int can_cellinit(FAR struct stm32l4_can_s *priv)
+{
+  uint32_t regval;
+  int ret;
+
+  caninfo("CAN%d\n", priv->port);
+
+  /* Exit from sleep mode */
+
+  regval  = can_getreg(priv, STM32L4_CAN_MCR_OFFSET);
+  regval &= ~CAN_MCR_SLEEP;
+  can_putreg(priv, STM32L4_CAN_MCR_OFFSET, regval);
+
+  /* Configure CAN behavior.  Priority driven request order, not message ID. */
+
+  regval |= CAN_MCR_TXFP;
+  can_putreg(priv, STM32L4_CAN_MCR_OFFSET, regval);
+
+  ret = can_enterinitmode(priv);
+  if(ret != 0)
+    {
+      return ret;
+    }
+
+  /* Disable the following modes:
+   *
+   *  - Time triggered communication mode
+   *  - Automatic bus-off management
+   *  - Automatic wake-up mode
+   *  - No automatic retransmission
+   *  - Receive FIFO locked mode
+   *  - Transmit FIFO priority
+   */
+
+  regval   = can_getreg(priv, STM32L4_CAN_MCR_OFFSET);
+  regval &= ~(CAN_MCR_TXFP | CAN_MCR_RFLM | CAN_MCR_NART | CAN_MCR_AWUM |
+              CAN_MCR_ABOM | CAN_MCR_TTCM);
+  can_putreg(priv, STM32L4_CAN_MCR_OFFSET, regval);
+
+  /* Configure bit timing. */
+
+  ret = can_bittiming(priv);
+  if (ret < 0)
+    {
+      canerr("ERROR: Failed to set bit timing: %d\n", ret);
+      return ret;
+    }
+
+  return can_exitinitmode(priv);
 }
 
 /****************************************************************************
@@ -1451,7 +1750,7 @@ static int can_cellinit(struct stm32l4_can_s *priv)
  *      finer control of the filtering.
  *
  *   There is no need to set up one filter for each CAN since STM32L4 only
- *   contains one CAN devices. If one day some STM32L4 has 2 CANs, then
+ *   contains one CAN device. If one day some STM32L4 has 2 CANs, then
  *   code will have to be imported from the STM32 port.
  *
  *   32-bit IdMask mode is configured.  However, both the ID and the MASK
@@ -1466,12 +1765,12 @@ static int can_cellinit(struct stm32l4_can_s *priv)
  *
  ****************************************************************************/
 
-static int can_filterinit(struct stm32l4_can_s *priv)
+static int can_filterinit(FAR struct stm32l4_can_s *priv)
 {
   uint32_t regval;
   uint32_t bitmask;
 
-  canllinfo("CAN%d filter: %d\n", priv->port, priv->filter);
+  caninfo("CAN%d filter: %d\n", priv->port, priv->filter);
 
   /* Get the bitmask associated with the filter used by this CAN block */
 
@@ -1528,6 +1827,98 @@ static int can_filterinit(struct stm32l4_can_s *priv)
   return OK;
 }
 
+/****************************************************************************
+ * Name: stm32l4_can_addextfilter
+ *
+ * Description:
+ *   Add a filter for extended CAN IDs
+ *
+ * Input Parameter:
+ *   priv - A pointer to the private data structure for this CAN block
+ *   arg  - A pointer to a structure describing the filter
+ *
+ * Returned Value:
+ *   A non-negative filter ID is returned on success.
+ *   Otherwise -1 (ERROR) is returned with the errno
+ *   set to indicate the nature of the error.
+ *
+ ****************************************************************************/
+
+static int  stm32l4_can_addextfilter(FAR struct stm32l4_can_s *priv,
+                                     FAR struct canioc_extfilter_s *arg)
+{
+  return -ENOTTY;
+}
+
+/****************************************************************************
+ * Name: stm32l4_can_delextfilter
+ *
+ * Description:
+ *   Remove a filter for extended CAN IDs
+ *
+ * Input Parameter:
+ *   priv - A pointer to the private data structure for this CAN block
+ *   arg  - The filter index previously returned by the
+ *            CANIOC_ADD_EXTFILTER command
+ *
+ * Returned Value:
+ *   Zero (OK) is returned on success.  Otherwise -1 (ERROR)
+ *   returned with the errno variable set to indicate the
+ *   of the error.
+ *
+ ****************************************************************************/
+
+static int  stm32l4_can_delextfilter(FAR struct stm32l4_can_s *priv, int arg)
+{
+  return -ENOTTY;
+}
+
+/****************************************************************************
+ * Name: stm32l4_can_addextfilter
+ *
+ * Description:
+ *   Add a filter for standard CAN IDs
+ *
+ * Input Parameter:
+ *   priv - A pointer to the private data structure for this CAN block
+ *   arg  - A pointer to a structure describing the filter
+ *
+ * Returned Value:
+ *   A non-negative filter ID is returned on success.
+ *   Otherwise -1 (ERROR) is returned with the errno
+ *   set to indicate the nature of the error.
+ *
+ ****************************************************************************/
+
+static int  stm32l4_can_addstdfilter(FAR struct stm32l4_can_s *priv,
+                                     FAR struct canioc_stdfilter_s *arg)
+{
+  return -ENOTTY;
+}
+
+/****************************************************************************
+ * Name: stm32l4_can_delstdfilter
+ *
+ * Description:
+ *   Remove a filter for standard CAN IDs
+ *
+ * Input Parameter:
+ *   priv - A pointer to the private data structure for this CAN block
+ *   arg  - The filter index previously returned by the
+ *            CANIOC_ADD_STDFILTER command
+ *
+ * Returned Value:
+ *   Zero (OK) is returned on success.  Otherwise -1 (ERROR)
+ *   returned with the errno variable set to indicate the
+ *   of the error.
+ *
+ ****************************************************************************/
+
+static int  stm32l4_can_delstdfilter(FAR struct stm32l4_can_s *priv, int arg)
+{
+  return -ENOTTY;
+}
+
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
@@ -1548,7 +1939,7 @@ static int can_filterinit(struct stm32l4_can_s *priv)
 
 FAR struct can_dev_s *stm32l4_caninitialize(int port)
 {
-  struct can_dev_s *dev = NULL;
+  FAR struct can_dev_s *dev = NULL;
 
   caninfo("CAN%d\n", port);
 
diff --git a/arch/arm/src/stm32l4/stm32l4_gpio.c b/arch/arm/src/stm32l4/stm32l4_gpio.c
index 8ae6efdb118..0c3432d6e47 100644
--- a/arch/arm/src/stm32l4/stm32l4_gpio.c
+++ b/arch/arm/src/stm32l4/stm32l4_gpio.c
@@ -176,6 +176,7 @@ int stm32l4_configgpio(uint32_t cfgset)
         break;
 
       case GPIO_OUTPUT:     /* General purpose output mode */
+        stm32l4_gpiowrite(cfgset, (cfgset & GPIO_OUTPUT_SET) != 0); /* Set the initial output value */
         pinmode = GPIO_MODER_OUTPUT;
         break;
 
@@ -305,17 +306,9 @@ int stm32l4_configgpio(uint32_t cfgset)
 
   putreg32(regval, base + STM32L4_GPIO_OTYPER_OFFSET);
 
-  /* If it is an output... set the pin to the correct initial state. */
-
-  if (pinmode == GPIO_MODER_OUTPUT)
-    {
-      bool value = ((cfgset & GPIO_OUTPUT_SET) != 0);
-      stm32l4_gpiowrite(cfgset, value);
-    }
-
   /* Otherwise, it is an input pin.  Should it configured as an EXTI interrupt? */
 
-  else if ((cfgset & GPIO_EXTI) != 0)
+  if ((cfgset & GPIO_EXTI) != 0)
     {
 #if 0
       /* "In STM32 F1 the selection of the EXTI line source is performed through
diff --git a/arch/arm/src/stm32l4/stm32l4_idle.c b/arch/arm/src/stm32l4/stm32l4_idle.c
index f17bd4d75e2..60dacd2928d 100644
--- a/arch/arm/src/stm32l4/stm32l4_idle.c
+++ b/arch/arm/src/stm32l4/stm32l4_idle.c
@@ -101,7 +101,7 @@ static void up_idlepm(void)
 
       /* Perform board-specific, state-dependent logic here */
 
-      _llinfo("newstate= %d oldstate=%d\n", newstate, oldstate);
+      _info("newstate= %d oldstate=%d\n", newstate, oldstate);
 
       /* Then force the global state change */
 
diff --git a/arch/arm/src/stm32l4/stm32l4_irq.c b/arch/arm/src/stm32l4/stm32l4_irq.c
index 7d5f948c81c..4742d5c95b5 100644
--- a/arch/arm/src/stm32l4/stm32l4_irq.c
+++ b/arch/arm/src/stm32l4/stm32l4_irq.c
@@ -150,7 +150,7 @@ static void stm32l4_dumpnvic(const char *msg, int irq)
 
 /****************************************************************************
  * Name: stm32l4_nmi, stm32l4_busfault, stm32l4_usagefault, stm32l4_pendsv,
- *       stm32l4_errmonitor, stm32l4_pendsv, stm32l4_reserved
+ *       stm32l4_dbgmonitor, stm32l4_pendsv, stm32l4_reserved
  *
  * Description:
  *   Handlers for various execptions.  None are handled and all are fatal
@@ -192,7 +192,7 @@ static int stm32l4_pendsv(int irq, FAR void *context)
   return 0;
 }
 
-static int stm32l4_errmonitor(int irq, FAR void *context)
+static int stm32l4_dbgmonitor(int irq, FAR void *context)
 {
   (void)up_irq_save();
   _err("PANIC!!! Debug Monitor received\n");
@@ -413,7 +413,7 @@ void up_irqinitialize(void)
   irq_attach(STM32L4_IRQ_BUSFAULT, stm32l4_busfault);
   irq_attach(STM32L4_IRQ_USAGEFAULT, stm32l4_usagefault);
   irq_attach(STM32L4_IRQ_PENDSV, stm32l4_pendsv);
-  irq_attach(STM32L4_IRQ_DBGMONITOR, stm32l4_errmonitor);
+  irq_attach(STM32L4_IRQ_DBGMONITOR, stm32l4_dbgmonitor);
   irq_attach(STM32L4_IRQ_RESERVED, stm32l4_reserved);
 #endif
 
diff --git a/arch/arm/src/stm32l4/stm32l4_qspi.c b/arch/arm/src/stm32l4/stm32l4_qspi.c
index 1fe106a083e..db01e22bba7 100644
--- a/arch/arm/src/stm32l4/stm32l4_qspi.c
+++ b/arch/arm/src/stm32l4/stm32l4_qspi.c
@@ -405,7 +405,7 @@ static bool qspi_checkreg(struct stm32l4_qspidev_s *priv, bool wr, uint32_t valu
         {
           /* Yes... show how many times we did it */
 
-          spillinfo("...[Repeats %d times]...\n", priv->ntimes);
+          spiinfo("...[Repeats %d times]...\n", priv->ntimes);
         }
 
       /* Save information about the new access */
@@ -439,7 +439,7 @@ static inline uint32_t qspi_getreg(struct stm32l4_qspidev_s *priv,
 #ifdef CONFIG_STM32L4_QSPI_REGDEBUG
   if (qspi_checkreg(priv, false, value, address))
     {
-      spillinfo("%08x->%08x\n", address, value);
+      spiinfo("%08x->%08x\n", address, value);
     }
 #endif
 
@@ -462,7 +462,7 @@ static inline void qspi_putreg(struct stm32l4_qspidev_s *priv, uint32_t value,
 #ifdef CONFIG_STM32L4_QSPI_REGDEBUG
   if (qspi_checkreg(priv, true, value, address))
     {
-      spillinfo("%08x<-%08x\n", address, value);
+      spiinfo("%08x<-%08x\n", address, value);
     }
 #endif
 
diff --git a/arch/arm/src/stm32l4/stm32l4_rtcc.c b/arch/arm/src/stm32l4/stm32l4_rtcc.c
index 830425e1a7c..390e104d726 100644
--- a/arch/arm/src/stm32l4/stm32l4_rtcc.c
+++ b/arch/arm/src/stm32l4/stm32l4_rtcc.c
@@ -1284,7 +1284,7 @@ int stm32l4_rtc_setalarm(FAR struct alm_setalarm_s *alminfo)
         break;
 
       default:
-        rtcinfo("ERROR: Invalid ALARM%d\n", alminfo->as_id);
+        rtcerr("ERROR: Invalid ALARM%d\n", alminfo->as_id);
         break;
     }
 
@@ -1384,7 +1384,7 @@ int stm32l4_rtc_cancelalarm(enum alm_id_e alarmid)
         break;
 
       default:
-        rtcinfo("ERROR: Invalid ALARM%d\n", alarmid);
+        rtcerr("ERROR: Invalid ALARM%d\n", alarmid);
         break;
     }
 
diff --git a/arch/arm/src/str71x/str71x_decodeirq.c b/arch/arm/src/str71x/str71x_decodeirq.c
index bdf8015e912..88751c80c14 100644
--- a/arch/arm/src/str71x/str71x_decodeirq.c
+++ b/arch/arm/src/str71x/str71x_decodeirq.c
@@ -91,8 +91,8 @@ void up_decodeirq(uint32_t *regs)
 {
 #ifdef CONFIG_SUPPRESS_INTERRUPTS
   board_autoled_on(LED_INIRQ);
-  lowsyslog(LOG_ERR, "Unexpected IRQ\n");
   CURRENT_REGS = regs;
+  err("ERROR: Unexpected IRQ\n");
   PANIC();
 #else
   unsigned int irq;
diff --git a/arch/arm/src/tiva/lm3s_ethernet.c b/arch/arm/src/tiva/lm3s_ethernet.c
index e5e242c624f..ab9bd289016 100644
--- a/arch/arm/src/tiva/lm3s_ethernet.c
+++ b/arch/arm/src/tiva/lm3s_ethernet.c
@@ -333,7 +333,7 @@ static void tiva_ethreset(struct tiva_driver_s *priv)
   regval  = getreg32(TIVA_SYSCON_RCGC2);
   regval |= (SYSCON_RCGC2_EMAC0 | SYSCON_RCGC2_EPHY0);
   putreg32(regval, TIVA_SYSCON_RCGC2);
-  nllinfo("RCGC2: %08x\n", regval);
+  ninfo("RCGC2: %08x\n", regval);
 
   /* Put the Ethernet controller into the reset state */
 
@@ -349,7 +349,7 @@ static void tiva_ethreset(struct tiva_driver_s *priv)
 
   regval &= ~(SYSCON_SRCR2_EMAC0 | SYSCON_SRCR2_EPHY0);
   putreg32(regval, TIVA_SYSCON_SRCR2);
-  nllinfo("SRCR2: %08x\n", regval);
+  ninfo("SRCR2: %08x\n", regval);
 
   /* Wait just a bit, again.  If we touch the ethernet too soon, we may busfault. */
 
@@ -495,7 +495,7 @@ static int tiva_transmit(struct tiva_driver_s *priv)
        */
 
       pktlen     = priv->ld_dev.d_len;
-      nllinfo("Sending packet, pktlen: %d\n", pktlen);
+      ninfo("Sending packet, pktlen: %d\n", pktlen);
       DEBUGASSERT(pktlen > ETH_HDRLEN);
 
       dbuf       = priv->ld_dev.d_buf;
@@ -584,7 +584,7 @@ static int tiva_txpoll(struct net_driver_s *dev)
    * the field d_len is set to a value > 0.
    */
 
-  nllinfo("Poll result: d_len=%d\n", priv->ld_dev.d_len);
+  ninfo("Poll result: d_len=%d\n", priv->ld_dev.d_len);
   if (priv->ld_dev.d_len > 0)
     {
       DEBUGASSERT((tiva_ethin(priv, TIVA_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0);
@@ -672,7 +672,7 @@ static void tiva_receive(struct tiva_driver_s *priv)
 
       regval = tiva_ethin(priv, TIVA_MAC_DATA_OFFSET);
       pktlen = (int)(regval & 0x0000ffff);
-      nllinfo("Receiving packet, pktlen: %d\n", pktlen);
+      ninfo("Receiving packet, pktlen: %d\n", pktlen);
 
       /* Check if the pktlen is valid.  It should be large enough to hold
        * an Ethernet header and small enough to fit entirely in the I/O
@@ -686,7 +686,7 @@ static void tiva_receive(struct tiva_driver_s *priv)
 
           /* We will have to drop this packet */
 
-          nllwarn("WARNING: "Bad packet size dropped (%d)\n", pktlen);
+          nwarn("WARNING: Bad packet size dropped (%d)\n", pktlen);
           NETDEV_RXERRORS(&priv->ld_dev);
 
           /* The number of bytes and words left to read is pktlen - 4 (including,
@@ -770,7 +770,7 @@ static void tiva_receive(struct tiva_driver_s *priv)
 #ifdef CONFIG_NET_IPv4
       if (ETHBUF->type == HTONS(ETHTYPE_IP))
         {
-          nllinfo("IPv4 frame\n");
+          ninfo("IPv4 frame\n");
           NETDEV_RXIPV4(&priv->ld_dev);
 
           /* Handle ARP on input then give the IPv4 packet to the network
@@ -811,7 +811,7 @@ static void tiva_receive(struct tiva_driver_s *priv)
 #ifdef CONFIG_NET_IPv6
       if (ETHBUF->type == HTONS(ETHTYPE_IP6))
         {
-          nllinfo("Iv6 frame\n");
+          ninfo("Iv6 frame\n");
           NETDEV_RXIPV6(&priv->ld_dev);
 
           /* Give the IPv6 packet to the network layer */
@@ -850,7 +850,7 @@ static void tiva_receive(struct tiva_driver_s *priv)
 #ifdef CONFIG_NET_ARP
       if (ETHBUF->type == htons(ETHTYPE_ARP))
         {
-          nllinfo("ARP packet received (%02x)\n", ETHBUF->type);
+          ninfo("ARP packet received (%02x)\n", ETHBUF->type);
           NETDEV_RXARP(&priv->ld_dev);
 
           arp_arpin(&priv->ld_dev);
@@ -867,7 +867,7 @@ static void tiva_receive(struct tiva_driver_s *priv)
       else
 #endif
         {
-          nllwarn("WARNING: Unsupported packet type dropped (%02x)\n",
+          nwarn("WARNING: Unsupported packet type dropped (%02x)\n",
                   htons(ETHBUF->type));
           NETDEV_RXDROPPED(&priv->ld_dev);
         }
@@ -1025,7 +1025,7 @@ static void tiva_txtimeout(int argc, uint32_t arg, ...)
 
   /* Increment statistics */
 
-  nllerr("ERROR: Tx timeout\n");
+  nerr("ERROR: Tx timeout\n");
   NETDEV_TXTIMEOUTS(&priv->ld_dev);
 
   /* Then reset the hardware */
@@ -1105,9 +1105,9 @@ static int tiva_ifup(struct net_driver_s *dev)
   uint32_t div;
   uint16_t phyreg;
 
-  nllinfo("Bringing up: %d.%d.%d.%d\n",
-          dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff,
-          (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24);
+  ninfo("Bringing up: %d.%d.%d.%d\n",
+        dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff,
+        (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24);
 
   /* Enable and reset the Ethernet controller */
 
@@ -1126,7 +1126,7 @@ static int tiva_ifup(struct net_driver_s *dev)
 
   div = SYSCLK_FREQUENCY / 2 / TIVA_MAX_MDCCLK;
   tiva_ethout(priv, TIVA_MAC_MDV_OFFSET, div);
-  nllinfo("MDV:   %08x\n", div);
+  ninfo("MDV:   %08x\n", div);
 
   /* Then configure the Ethernet Controller for normal operation
    *
@@ -1138,7 +1138,7 @@ static int tiva_ifup(struct net_driver_s *dev)
   regval &= ~TIVA_TCTCL_CLRBITS;
   regval |= TIVA_TCTCL_SETBITS;
   tiva_ethout(priv, TIVA_MAC_TCTL_OFFSET, regval);
-  nllinfo("TCTL:  %08x\n", regval);
+  ninfo("TCTL:  %08x\n", regval);
 
   /* Setup the receive control register (Disable multicast frames, disable
    * promiscuous mode, disable bad CRC rejection).
@@ -1148,7 +1148,7 @@ static int tiva_ifup(struct net_driver_s *dev)
   regval &= ~TIVA_RCTCL_CLRBITS;
   regval |= TIVA_RCTCL_SETBITS;
   tiva_ethout(priv, TIVA_MAC_RCTL_OFFSET, regval);
-  nllinfo("RCTL:  %08x\n", regval);
+  ninfo("RCTL:  %08x\n", regval);
 
   /* Setup the time stamp configuration register */
 
@@ -1160,7 +1160,7 @@ static int tiva_ifup(struct net_driver_s *dev)
   regval &= ~(MAC_TS_EN);
 #endif
   tiva_ethout(priv, TIVA_MAC_TS_OFFSET, regval);
-  nllinfo("TS:    %08x\n", regval);
+  ninfo("TS:    %08x\n", regval);
 #endif
 
   /* Wait for the link to come up.  This following is not very conservative
@@ -1169,13 +1169,13 @@ static int tiva_ifup(struct net_driver_s *dev)
    * set
    */
 
-  nllinfo("Waiting for link\n");
+  ninfo("Waiting for link\n");
   do
     {
       phyreg = tiva_phyread(priv, MII_MSR);
     }
   while ((phyreg & MII_MSR_LINKSTATUS) == 0);
-  nllinfo("Link established\n");
+  ninfo("Link established\n");
 
   /* Reset the receive FIFO */
 
@@ -1259,9 +1259,9 @@ static int tiva_ifdown(struct net_driver_s *dev)
   irqstate_t flags;
   uint32_t regval;
 
-  nllinfo("Taking down: %d.%d.%d.%d\n",
-          dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff,
-          (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24);
+  ninfo("Taking down: %d.%d.%d.%d\n",
+        dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff,
+        (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24);
 
   /* Cancel the TX poll timer and TX timeout timers */
 
diff --git a/arch/arm/src/tiva/tiva_adclow.c b/arch/arm/src/tiva/tiva_adclow.c
index e2e20b91965..6a89e62b577 100644
--- a/arch/arm/src/tiva/tiva_adclow.c
+++ b/arch/arm/src/tiva/tiva_adclow.c
@@ -686,7 +686,7 @@ static void tiva_adc_read(void *arg)
        * and should cause a full system stop.
        */
 
-      allerr("ERROR: Invalid ADC device number given %d\n", sse->adc);
+      aerr("ERROR: Invalid ADC device number given %d\n", sse->adc);
       PANIC();
       return;
     }
diff --git a/arch/arm/src/tiva/tiva_gpioirq.c b/arch/arm/src/tiva/tiva_gpioirq.c
index 8931988a937..1023dd7bc23 100644
--- a/arch/arm/src/tiva/tiva_gpioirq.c
+++ b/arch/arm/src/tiva/tiva_gpioirq.c
@@ -293,7 +293,7 @@ static int tiva_gpioporthandler(uint8_t port, void *context)
   uint8_t   pin;                                   /* Pin number */
 
   tiva_gpioirqclear(port, 0xff);
-  gpiollinfo("mis=0b%08b\n", mis & 0xff);
+  gpioinfo("mis=0b%08b\n", mis & 0xff);
 
   /* Now process each IRQ pending in the MIS */
 
@@ -303,10 +303,10 @@ static int tiva_gpioporthandler(uint8_t port, void *context)
         {
           if (((mis >> pin) & 1) != 0)
             {
-              gpiollinfo("port=%d pin=%d irq=%p index=%d\n",
-                         port, pin,
-                         g_gpioportirqvector[TIVA_GPIO_IRQ_IDX(port, pin)],
-                         TIVA_GPIO_IRQ_IDX(port, pin));
+              gpioinfo("port=%d pin=%d irq=%p index=%d\n",
+                       port, pin,
+                       g_gpioportirqvector[TIVA_GPIO_IRQ_IDX(port, pin)],
+                       TIVA_GPIO_IRQ_IDX(port, pin));
 
               g_gpioportirqvector[TIVA_GPIO_IRQ_IDX(port, pin)](irq, context);
             }
diff --git a/arch/arm/src/tiva/tiva_irq.c b/arch/arm/src/tiva/tiva_irq.c
index 8f95e071d9e..6771007d59e 100644
--- a/arch/arm/src/tiva/tiva_irq.c
+++ b/arch/arm/src/tiva/tiva_irq.c
@@ -186,7 +186,7 @@ static void tiva_dumpnvic(const char *msg, int irq)
 
 /****************************************************************************
  * Name: tiva_nmi, tiva_busfault, tiva_usagefault, tiva_pendsv,
- *       tiva_errmonitor, tiva_pendsv, tiva_reserved
+ *       tiva_dbgmonitor, tiva_pendsv, tiva_reserved
  *
  * Description:
  *   Handlers for various execptions.  None are handled and all are fatal
@@ -228,7 +228,7 @@ static int tiva_pendsv(int irq, FAR void *context)
   return 0;
 }
 
-static int tiva_errmonitor(int irq, FAR void *context)
+static int tiva_dbgmonitor(int irq, FAR void *context)
 {
   (void)up_irq_save();
   _err("PANIC!!! Debug Monitor received\n");
@@ -482,7 +482,7 @@ void up_irqinitialize(void)
   irq_attach(TIVA_IRQ_BUSFAULT, tiva_busfault);
   irq_attach(TIVA_IRQ_USAGEFAULT, tiva_usagefault);
   irq_attach(TIVA_IRQ_PENDSV, tiva_pendsv);
-  irq_attach(TIVA_IRQ_DBGMONITOR, tiva_errmonitor);
+  irq_attach(TIVA_IRQ_DBGMONITOR, tiva_dbgmonitor);
   irq_attach(TIVA_IRQ_RESERVED, tiva_reserved);
 #endif
 
diff --git a/arch/arm/src/tiva/tm4c_ethernet.c b/arch/arm/src/tiva/tm4c_ethernet.c
index 575f6b2edc4..37fcbc22677 100644
--- a/arch/arm/src/tiva/tm4c_ethernet.c
+++ b/arch/arm/src/tiva/tm4c_ethernet.c
@@ -808,7 +808,7 @@ static uint32_t tiva_getreg(uint32_t addr)
         {
           if (count == 4)
             {
-              _llinfo("...\n");
+              _info("...\n");
             }
 
           return val;
@@ -825,7 +825,7 @@ static uint32_t tiva_getreg(uint32_t addr)
         {
           /* Yes.. then show how many times the value repeated */
 
-          _llinfo("[repeats %d more times]\n", count-3);
+          _info("[repeats %d more times]\n", count-3);
         }
 
       /* Save the new address, value, and count */
@@ -837,7 +837,7 @@ static uint32_t tiva_getreg(uint32_t addr)
 
   /* Show the register value read */
 
-  _llinfo("%08x->%08x\n", addr, val);
+  _info("%08x->%08x\n", addr, val);
   return val;
 }
 #endif
@@ -864,7 +864,7 @@ static void tiva_putreg(uint32_t val, uint32_t addr)
 {
   /* Show the register value being written */
 
-  _llinfo("%08x<-%08x\n", addr, val);
+  _info("%08x<-%08x\n", addr, val);
 
   /* Write the value */
 
@@ -1544,7 +1544,7 @@ static int tiva_recvframe(FAR struct tiva_ethmac_s *priv)
 
   if (!tiva_isfreebuffer(priv))
     {
-      nllerr("ERROR: No free buffers\n");
+      nerr("ERROR: No free buffers\n");
       return -ENOMEM;
     }
 
@@ -1651,7 +1651,7 @@ static int tiva_recvframe(FAR struct tiva_ethmac_s *priv)
                * scanning logic, and continue scanning with the next frame.
                */
 
-              nllwarn("DROPPED: RX descriptor errors: %08x\n", rxdesc->rdes0);
+              nwarn("DROPPED: RX descriptor errors: %08x\n", rxdesc->rdes0);
               tiva_freesegment(priv, rxcurr, priv->segments);
             }
         }
@@ -1712,7 +1712,7 @@ static void tiva_receive(FAR struct tiva_ethmac_s *priv)
 
       if (dev->d_len > CONFIG_NET_ETH_MTU)
         {
-          nllwarn("DROPPED: Too big: %d\n", dev->d_len);
+          nwarn("DROPPED: Too big: %d\n", dev->d_len);
         }
       else
 
@@ -1721,7 +1721,7 @@ static void tiva_receive(FAR struct tiva_ethmac_s *priv)
 #ifdef CONFIG_NET_IPv4
       if (BUF->type == HTONS(ETHTYPE_IP))
         {
-          nllinfo("IPv4 frame\n");
+          ninfo("IPv4 frame\n");
 
           /* Handle ARP on input then give the IPv4 packet to the network
            * layer
@@ -1760,7 +1760,7 @@ static void tiva_receive(FAR struct tiva_ethmac_s *priv)
 #ifdef CONFIG_NET_IPv6
       if (BUF->type == HTONS(ETHTYPE_IP6))
         {
-          nllinfo("IPv6 frame\n");
+          ninfo("IPv6 frame\n");
 
           /* Give the IPv6 packet to the network layer */
 
@@ -1815,7 +1815,7 @@ static void tiva_receive(FAR struct tiva_ethmac_s *priv)
       else
 #endif
         {
-          nllwarn("DROPPED: Unknown type: %04x\n", BUF->type);
+          nwarn("DROPPED: Unknown type: %04x\n", BUF->type);
         }
 
       /* We are finished with the RX buffer.  NOTE:  If the buffer is
@@ -2067,7 +2067,7 @@ static inline void tiva_interrupt_process(FAR struct tiva_ethmac_s *priv)
     {
       /* Just let the user know what happened */
 
-      nllerr("ERROR: Abnormal event(s): %08x\n", dmaris);
+      nerr("ERROR: Abnormal event(s): %08x\n", dmaris);
 
       /* Clear all pending abnormal events */
 
@@ -2287,7 +2287,7 @@ static void tiva_txtimeout_expiry(int argc, uint32_t arg, ...)
 {
   FAR struct tiva_ethmac_s *priv = (FAR struct tiva_ethmac_s *)arg;
 
-  nllerr("ERROR: Timeout!\n");
+  nerr("ERROR: Timeout!\n");
 
 #ifdef CONFIG_NET_NOINTS
   /* Disable further Ethernet interrupts.  This will prevent some race
@@ -3599,7 +3599,7 @@ static inline void tiva_phy_initialize(FAR struct tiva_ethmac_s *priv)
 {
   /* Enable the clock to the PHY module */
 
-  nllinfo("Enable EPHY clocking\n");
+  ninfo("Enable EPHY clocking\n");
   tiva_ephy_enableclk();
 
   /* What until the PREPHY register indicates that the PHY is ready before
@@ -3611,7 +3611,7 @@ static inline void tiva_phy_initialize(FAR struct tiva_ethmac_s *priv)
 
   /* Enable power to the Ethernet PHY */
 
-  nllinfo("Enable EPHY power\n");
+  ninfo("Enable EPHY power\n");
   tiva_ephy_enablepwr();
 
   /* What until the PREPHY register indicates that the PHY registers are ready
@@ -3621,11 +3621,11 @@ static inline void tiva_phy_initialize(FAR struct tiva_ethmac_s *priv)
   while (!tiva_ephy_periphrdy());
   up_udelay(250);
 
-  nllinfo("RCGCEPHY: %08x PCEPHY: %08x PREPHY: %08x\n",
-          getreg32(TIVA_SYSCON_RCGCEPHY),
-          getreg32(TIVA_SYSCON_PCEPHY),
-          getreg32(TIVA_SYSCON_PREPHY));
-  nllinfo("Configure PHY GPIOs\n");
+  ninfo("RCGCEPHY: %08x PCEPHY: %08x PREPHY: %08x\n",
+        getreg32(TIVA_SYSCON_RCGCEPHY),
+        getreg32(TIVA_SYSCON_PCEPHY),
+        getreg32(TIVA_SYSCON_PREPHY));
+  ninfo("Configure PHY GPIOs\n");
 
 #ifdef CONFIG_TIVA_PHY_INTERNAL
   /* Integrated PHY:
@@ -4201,7 +4201,7 @@ int tiva_ethinitialize(int intf)
   struct tiva_ethmac_s *priv;
   uint32_t regval;
 
-  nllinfo("intf: %d\n", intf);
+  ninfo("intf: %d\n", intf);
 
   /* Get the interface structure associated with this interface number. */
 
@@ -4247,7 +4247,7 @@ int tiva_ethinitialize(int intf)
    *   bringing it a fully functional state.
    */
 
-  nllinfo("Enable EMAC clocking\n");
+  ninfo("Enable EMAC clocking\n");
   tiva_emac_enablepwr();   /* Ethernet MAC Power Control */
   tiva_emac_enableclk();   /* Ethernet MAC Run Mode Clock Gating Control */
 
@@ -4260,11 +4260,11 @@ int tiva_ethinitialize(int intf)
 
   /* Show all EMAC clocks */
 
-  nllinfo("RCGCEMAC: %08x PCEMAC: %08x PREMAC: %08x MOSCCTL: %08x\n",
-          getreg32(TIVA_SYSCON_RCGCEMAC),
-          getreg32(TIVA_SYSCON_PCEMAC),
-          getreg32(TIVA_SYSCON_PREMAC),
-          getreg32(TIVA_SYSCON_MOSCCTL));
+  ninfo("RCGCEMAC: %08x PCEMAC: %08x PREMAC: %08x MOSCCTL: %08x\n",
+        getreg32(TIVA_SYSCON_RCGCEMAC),
+        getreg32(TIVA_SYSCON_PCEMAC),
+        getreg32(TIVA_SYSCON_PREMAC),
+        getreg32(TIVA_SYSCON_MOSCCTL));
 
   /* Configure clocking and GPIOs to support the internal/eternal PHY */
 
@@ -4309,7 +4309,7 @@ int tiva_ethinitialize(int intf)
 
   /* Register the device with the OS so that socket IOCTLs can be performed */
 
-  nllinfo("Registering Ethernet device\n");
+  ninfo("Registering Ethernet device\n");
   return netdev_register(&priv->dev, NET_LL_ETHERNET);
 }
 
diff --git a/arch/arm/src/tms570/tms570_esm.c b/arch/arm/src/tms570/tms570_esm.c
index e6eec90c5f1..2019fac5065 100644
--- a/arch/arm/src/tms570/tms570_esm.c
+++ b/arch/arm/src/tms570/tms570_esm.c
@@ -155,7 +155,7 @@ int tms570_esm_interrupt(int irq, void *context)
 
   /* Crash -- possibly showing diagnostic debug information. */
 
-  _llerr("ERROR: ESM Interrupt. PC: %08x\n", CURRENT_REGS[REG_PC]);
+  _err("ERROR: ESM Interrupt. PC: %08x\n", CURRENT_REGS[REG_PC]);
   PANIC();
   return OK; /* To keep the compiler happy */
 }
diff --git a/arch/arm/src/tms570/tms570_gio.c b/arch/arm/src/tms570/tms570_gio.c
index 3a771ff1d8b..34ffb4cfd21 100644
--- a/arch/arm/src/tms570/tms570_gio.c
+++ b/arch/arm/src/tms570/tms570_gio.c
@@ -296,8 +296,8 @@ int tms570_dumpgio(uint32_t pinset, const char *msg)
   uintptr_t     base;
   unsigned int  port;
 
-  _llinfo("GIO%c pinset: %08x base: %08x -- %s\n",
-         g_portchar[port], pinset, base, msg);
+  _info("GIO%c pinset: %08x base: %08x -- %s\n",
+        g_portchar[port], pinset, base, msg);
 
   /* Get the base address associated with the GIO port */
 
@@ -310,20 +310,20 @@ int tms570_dumpgio(uint32_t pinset, const char *msg)
 
   /* Show global GIO registers */
 
-  _llinfo("   GCR0: %08x INTDET: %08x    POL: %08x   ENA: %08x\n",
-         getreg32(TMS570_GIO_GCR0), getreg32(TMS570_GIO_INTDET),
-         getreg32(TMS570_GIO_POL), getreg32(TMS570_GIO_ENASET));
-  _llinfo("    LVL: %08x    FLG: %08x   EMU1: %08x   EMU2: %08x\n",
-         getreg32(TMS570_GIO_LVLSET), getreg32(TMS570_GIO_FLG),
-         getreg32(TMS570_GIO_EMU1), getreg32(TMS570_GIO_EMU2));
+  _info("   GCR0: %08x INTDET: %08x    POL: %08x   ENA: %08x\n",
+        getreg32(TMS570_GIO_GCR0), getreg32(TMS570_GIO_INTDET),
+        getreg32(TMS570_GIO_POL), getreg32(TMS570_GIO_ENASET));
+  _info("    LVL: %08x    FLG: %08x   EMU1: %08x   EMU2: %08x\n",
+        getreg32(TMS570_GIO_LVLSET), getreg32(TMS570_GIO_FLG),
+        getreg32(TMS570_GIO_EMU1), getreg32(TMS570_GIO_EMU2));
 
   /* Port specific registers */
 
-  _llinfo("    DIR: %08x    DIN: %08x   DOUT: %08x    PDR: %08x\n",
-         getreg32(base + TMS570_GIO_DIR_OFFSET), getreg32(base + TMS570_GIO_DIN_OFFSET),
-         getreg32(base + TMS570_GIO_DOUT_OFFSET), getreg32(base + TMS570_GIO_PDR_OFFSET));
-  _llinfo(" PULDIS: %08x    PSL: %08x\n",
-         getreg32(base + TMS570_GIO_PULDIS_OFFSET), getreg32(base + TMS570_GIO_PSL_OFFSET));
+  _info("    DIR: %08x    DIN: %08x   DOUT: %08x    PDR: %08x\n",
+        getreg32(base + TMS570_GIO_DIR_OFFSET), getreg32(base + TMS570_GIO_DIN_OFFSET),
+        getreg32(base + TMS570_GIO_DOUT_OFFSET), getreg32(base + TMS570_GIO_PDR_OFFSET));
+  _info(" PULDIS: %08x    PSL: %08x\n",
+        getreg32(base + TMS570_GIO_PULDIS_OFFSET), getreg32(base + TMS570_GIO_PSL_OFFSET));
 
   leave_critical_section(flags);
   return OK;
diff --git a/arch/avr/include/debug.h b/arch/avr/include/debug.h
index b95e9b9322a..05116b4418a 100644
--- a/arch/avr/include/debug.h
+++ b/arch/avr/include/debug.h
@@ -72,19 +72,15 @@
     } \
   while(0)
 
-/* __arch_syslog() and __arch_lowsyslog() override behavior of NuttX
- * dbg macros. They put the format string into program memory and
- * utilize IPTR (__memx) parameter of syslog to take the format
- * directly from program memory.  This reduces amount of RAM held by
- * the format strings used in debug statements.
+/* __arch_syslog() overrides the behavior of NuttX debug macros. They put
+ * the format string into program memory and utilize IPTR (__memx) parameter
+ * of syslog to take the format directly from program memory.  This reduces
+ * amount of RAM held by the format strings used in debug statements.
  */
 
 #define __arch_syslog(...) \
    __dbg_expand(syslog, ##__VA_ARGS__)
 
-#define __arch_lowsyslog(...) \
-   __dbg_expand(lowsyslog, ##__VA_ARGS__)
-
 #endif /* CONFIG_AVR_HAS_MEMX_PTR */
 
 #endif /* __INCLUDE_ARCH_DEBUG_H */
diff --git a/arch/avr/src/at32uc3/at32uc3_config.h b/arch/avr/src/at32uc3/at32uc3_config.h
index 8867fae8694..9dd75a24f7e 100644
--- a/arch/avr/src/at32uc3/at32uc3_config.h
+++ b/arch/avr/src/at32uc3/at32uc3_config.h
@@ -181,13 +181,6 @@
 #  define USE_SERIALDRIVER 1
 #endif
 
-/* Determine which device to use as the system logging device */
-
-#ifndef CONFIG_SYSLOG
-#  undef CONFIG_SYSLOG_CHAR
-#  undef CONFIG_RAMLOG_SYSLOG
-#endif
-
 /* If GPIO IRQ support is defined, then a set of GPIOs must all be included */
 
 #if CONFIG_AVR32_GPIOIRQSETA == 0 && CONFIG_AVR32_GPIOIRQSETB == 0
diff --git a/arch/avr/src/at32uc3/at32uc3_gpioirq.c b/arch/avr/src/at32uc3/at32uc3_gpioirq.c
index a62dc41aa6a..171fa39f1f2 100644
--- a/arch/avr/src/at32uc3/at32uc3_gpioirq.c
+++ b/arch/avr/src/at32uc3/at32uc3_gpioirq.c
@@ -228,8 +228,8 @@ static void gpio_porthandler(uint32_t regbase, int irqbase, uint32_t irqset, voi
                 }
               else
                 {
-                  _llerr("ERROR: No handler: pin=%d ifr=%08x irqset=%08x",
-                        pin, ifr, irqset);
+                  _err("ERROR: No handler: pin=%d ifr=%08x irqset=%08x",
+                       pin, ifr, irqset);
                 }
             }
 
@@ -247,8 +247,8 @@ static void gpio_porthandler(uint32_t regbase, int irqbase, uint32_t irqset, voi
           putreg32(bit, regbase + AVR32_GPIO_IFRC_OFFSET);
           ifr &= ~bit;
 
-          _llwarn("WARNING: IRQ on unconfigured pin: pin=%d ifr=%08x irqset=%08x",
-                 pin, ifr, irqset);
+          warn("WARNING: IRQ on unconfigured pin: pin=%d ifr=%08x irqset=%08x",
+               pin, ifr, irqset);
         }
     }
 }
diff --git a/arch/avr/src/at32uc3/at32uc3_irq.c b/arch/avr/src/at32uc3/at32uc3_irq.c
index 1983e1f34f1..4474f9e5c18 100644
--- a/arch/avr/src/at32uc3/at32uc3_irq.c
+++ b/arch/avr/src/at32uc3/at32uc3_irq.c
@@ -321,11 +321,11 @@ unsigned int avr32_intirqno(unsigned int level)
           mask <<= 1;
         }
 
-       _llerr("ERROR: Spurious interrupt: group=%d IRR=%08x\n", group, irr);
+       _err("ERROR: Spurious interrupt: group=%d IRR=%08x\n", group, irr);
        return -ENODEV;
     }
 
-  _llerr("ERROR: Bad group: %d\n", group);
+  _err("ERROR: Bad group: %d\n", group);
   return AVR32_IRQ_BADVECTOR;
 }
 
diff --git a/arch/avr/src/at90usb/at90usb_config.h b/arch/avr/src/at90usb/at90usb_config.h
index 3f0d80a19d8..b00fd1e0ba8 100644
--- a/arch/avr/src/at90usb/at90usb_config.h
+++ b/arch/avr/src/at90usb/at90usb_config.h
@@ -100,13 +100,6 @@
 #  define USE_SERIALDRIVER 1
 #endif
 
-/* Determine which device to use as the system logging device */
-
-#ifndef CONFIG_SYSLOG
-#  undef CONFIG_SYSLOG_CHAR
-#  undef CONFIG_RAMLOG_SYSLOG
-#endif
-
 /************************************************************************************
  * Public Types
  ************************************************************************************/
diff --git a/arch/avr/src/at90usb/at90usb_usbdev.c b/arch/avr/src/at90usb/at90usb_usbdev.c
index 63b7fe95cd8..333037d2158 100644
--- a/arch/avr/src/at90usb/at90usb_usbdev.c
+++ b/arch/avr/src/at90usb/at90usb_usbdev.c
@@ -1399,8 +1399,8 @@ static inline void avr_ep0setup(void)
   index = GETUINT16(ctrl.index);
   len   = GETUINT16(ctrl.len);
 
-  ullinfo("type=%02x req=%02x value=%04x index=%04x len=%04x\n",
-          ctrl.type, ctrl.req, value, index, len);
+  uinfo("type=%02x req=%02x value=%04x index=%04x len=%04x\n",
+        ctrl.type, ctrl.req, value, index, len);
 
   /* Dispatch any non-standard requests */
 
@@ -1596,7 +1596,7 @@ static inline void avr_ep0setup(void)
 #ifdef CONFIG_USBDEV_SELFPOWERED
                 if (value == USB_FEATURE_TESTMODE)
                   {
-                    ullinfo("test mode: %d\n", index);
+                    uinfo("test mode: %d\n", index);
                   }
                 else if (value == USB_FEATURE_REMOTEWAKEUP)
                   {
@@ -2386,8 +2386,8 @@ static int avr_epsubmit(FAR struct usbdev_ep_s *ep,
   if (!req || !req->callback || !req->buf || !ep)
     {
       usbtrace(TRACE_DEVERROR(AVR_TRACEERR_INVALIDPARMS), 0);
-      ullinfo("req=%p callback=%p buf=%p ep=%p\n",
-              req, req->callback, req->buf, ep);
+      uinfo("req=%p callback=%p buf=%p ep=%p\n",
+            req, req->callback, req->buf, ep);
       return -EINVAL;
     }
 #endif
diff --git a/arch/avr/src/atmega/atmega_config.h b/arch/avr/src/atmega/atmega_config.h
index 0390f1c129f..3d21cd82a79 100644
--- a/arch/avr/src/atmega/atmega_config.h
+++ b/arch/avr/src/atmega/atmega_config.h
@@ -106,13 +106,6 @@
 #  define USE_SERIALDRIVER 1
 #endif
 
-/* Determine which device to use as the system logging device */
-
-#ifndef CONFIG_SYSLOG
-#  undef CONFIG_SYSLOG_CHAR
-#  undef CONFIG_RAMLOG_SYSLOG
-#endif
-
 /************************************************************************************
  * Public Types
  ************************************************************************************/
diff --git a/arch/avr/src/avr/up_releasepending.c b/arch/avr/src/avr/up_releasepending.c
index 2501d8340c4..5b9b05df2be 100644
--- a/arch/avr/src/avr/up_releasepending.c
+++ b/arch/avr/src/avr/up_releasepending.c
@@ -66,7 +66,7 @@ void up_release_pending(void)
 {
   struct tcb_s *rtcb = this_task();
 
-  sllinfo("From TCB=%p\n", rtcb);
+  sinfo("From TCB=%p\n", rtcb);
 
   /* Merge the g_pendingtasks list into the ready-to-run task list */
 
diff --git a/arch/avr/src/avr/up_reprioritizertr.c b/arch/avr/src/avr/up_reprioritizertr.c
index 24fdd401cd6..846b59becf6 100644
--- a/arch/avr/src/avr/up_reprioritizertr.c
+++ b/arch/avr/src/avr/up_reprioritizertr.c
@@ -94,7 +94,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority)
       struct tcb_s *rtcb = this_task();
       bool switch_needed;
 
-      sllinfo("TCB=%p PRI=%d\n", tcb, priority);
+      sinfo("TCB=%p PRI=%d\n", tcb, priority);
 
       /* Remove the tcb task from the ready-to-run list.
        * sched_removereadytorun will return true if we just
diff --git a/arch/avr/src/avr32/up_releasepending.c b/arch/avr/src/avr32/up_releasepending.c
index 29bc26dbf21..617c04cc3b9 100644
--- a/arch/avr/src/avr32/up_releasepending.c
+++ b/arch/avr/src/avr32/up_releasepending.c
@@ -67,7 +67,7 @@ void up_release_pending(void)
 {
   struct tcb_s *rtcb = this_task();
 
-  sllinfo("From TCB=%p\n", rtcb);
+  sinfo("From TCB=%p\n", rtcb);
 
   /* Merge the g_pendingtasks list into the ready-to-run task list */
 
diff --git a/arch/avr/src/avr32/up_reprioritizertr.c b/arch/avr/src/avr32/up_reprioritizertr.c
index bf60353cf1f..1ce7a4c406e 100644
--- a/arch/avr/src/avr32/up_reprioritizertr.c
+++ b/arch/avr/src/avr32/up_reprioritizertr.c
@@ -95,7 +95,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority)
       struct tcb_s *rtcb = this_task();
       bool switch_needed;
 
-      sllinfo("TCB=%p PRI=%d\n", tcb, priority);
+      sinfo("TCB=%p PRI=%d\n", tcb, priority);
 
       /* Remove the tcb task from the ready-to-run list.
        * sched_removereadytorun will return true if we just
diff --git a/arch/avr/src/common/up_assert.c b/arch/avr/src/common/up_assert.c
index a93187c5238..92c3bde0175 100644
--- a/arch/avr/src/common/up_assert.c
+++ b/arch/avr/src/common/up_assert.c
@@ -109,7 +109,7 @@ static int usbtrace_syslog(FAR const char *fmt, ...)
   /* Let vsyslog do the real work */
 
   va_start(ap, fmt);
-  ret = lowvsyslog(LOG_INFO, fmt, ap);
+  ret = vsyslog(LOG_EMERG, fmt, ap);
   va_end(ap);
   return ret;
 }
@@ -131,7 +131,7 @@ static int assert_tracecallback(FAR struct usbtrace_s *trace, FAR void *arg)
 
 void up_assert(const uint8_t *filename, int lineno)
 {
-#if CONFIG_TASK_NAME_SIZE > 0
+#if CONFIG_TASK_NAME_SIZE > 0 && defined(CONFIG_DEBUG_ALERT)
   struct tcb_s *rtcb = this_task();
 #endif
 
diff --git a/arch/avr/src/common/up_exit.c b/arch/avr/src/common/up_exit.c
index 73dd3bb353b..4b77c358b23 100644
--- a/arch/avr/src/common/up_exit.c
+++ b/arch/avr/src/common/up_exit.c
@@ -52,6 +52,14 @@
 #include "group/group.h"
 #include "up_internal.h"
 
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#ifndef CONFIG_DEBUG_SCHED_INFO
+#  undef CONFIG_DUMP_ON_EXIT
+#endif
+
 /****************************************************************************
  * Private Functions
  ****************************************************************************/
@@ -66,7 +74,7 @@
  *
  ****************************************************************************/
 
-#if defined(CONFIG_DUMP_ON_EXIT) && defined(CONFIG_DEBUG_FEATURES)
+#ifdef CONFIG_DUMP_ON_EXIT
 static void _up_dumponexit(FAR struct tcb_s *tcb, FAR void *arg)
 {
 #if CONFIG_NFILE_DESCRIPTORS > 0
@@ -138,10 +146,10 @@ void _exit(int status)
 
   (void)up_irq_save();
 
-  sllinfo("TCB=%p exiting\n", this_task());
+  sinfo("TCB=%p exiting\n", this_task());
 
-#if defined(CONFIG_DUMP_ON_EXIT) && defined(CONFIG_DEBUG_FEATURES)
-  sllinfo("Other tasks:\n");
+#ifdef CONFIG_DUMP_ON_EXIT
+  sinfo("Other tasks:\n");
   sched_foreach(_up_dumponexit, NULL);
 #endif
 
diff --git a/arch/avr/src/common/up_initialize.c b/arch/avr/src/common/up_initialize.c
index b79f95876cb..669821631c0 100644
--- a/arch/avr/src/common/up_initialize.c
+++ b/arch/avr/src/common/up_initialize.c
@@ -48,7 +48,7 @@
 #include <nuttx/net/loopback.h>
 #include <nuttx/net/tun.h>
 #include <nuttx/net/telnet.h>
-#include <nuttx/syslog/ramlog.h>
+#include <nuttx/syslog/syslog.h>
 #include <nuttx/syslog/syslog_console.h>
 
 #include <arch/board/board.h>
@@ -99,13 +99,6 @@
 #  define USE_SERIALDRIVER 1
 #endif
 
-/* Determine which device to use as the system logging device */
-
-#ifndef CONFIG_SYSLOG
-#  undef CONFIG_SYSLOG_CHAR
-#  undef CONFIG_RAMLOG_SYSLOG
-#endif
-
 /****************************************************************************
  * Private Functions
  ****************************************************************************/
@@ -125,13 +118,13 @@ static void up_calibratedelay(void)
 {
   int i;
 
-  _llwarn("Beginning 100s delay\n");
+  _warn("Beginning 100s delay\n");
   for (i = 0; i < 100; i++)
     {
       up_mdelay(1000);
     }
 
-  _llwarn("End 100s delay\n");
+  _warn("End 100s delay\n");
 }
 #else
 # define up_calibratedelay()
@@ -259,20 +252,18 @@ void up_initialize(void)
 
 #if defined(CONFIG_DEV_LOWCONSOLE)
   lowconsole_init();
-#elif defined(CONFIG_SYSLOG_CONSOLE)
+#elif defined(CONFIG_CONSOLE_SYSLOG)
   syslog_console_init();
 #elif defined(CONFIG_RAMLOG_CONSOLE)
   ramlog_consoleinit();
 #endif
 
-  /* Initialize the system logging device */
+  /* Early initialization of the system logging device.  Some SYSLOG channel
+   * can be initialized early in the initialization sequence because they
+   * depend on only minimal OS initialization.
+   */
 
-#ifdef CONFIG_SYSLOG_CHAR
-  syslog_initialize();
-#endif
-#ifdef CONFIG_RAMLOG_SYSLOG
-  ramlog_sysloginit();
-#endif
+  syslog_initialize(SYSLOG_INIT_EARLY);
 
 #ifndef CONFIG_NETDEV_LATEINIT
   /* Initialize the network */
diff --git a/arch/avr/src/common/up_internal.h b/arch/avr/src/common/up_internal.h
index 92a160ee90e..64eecb658ce 100644
--- a/arch/avr/src/common/up_internal.h
+++ b/arch/avr/src/common/up_internal.h
@@ -67,6 +67,10 @@
 #undef  CONFIG_SUPPRESS_UART_CONFIG   /* DEFINED: Do not reconfig UART */
 #undef  CONFIG_DUMP_ON_EXIT           /* DEFINED: Dump task state on exit */
 
+#ifndef CONFIG_DEBUG_SCHED_INFO
+#  undef CONFIG_DUMP_ON_EXIT          /* Needs CONFIG_DEBUG_SCHED_INFO */
+#endif
+
 /* Check if an interrupt stack size is configured */
 
 #ifndef CONFIG_ARCH_INTERRUPTSTACK
diff --git a/arch/hc/src/common/up_exit.c b/arch/hc/src/common/up_exit.c
index 251e91cefc4..098b8681dbb 100644
--- a/arch/hc/src/common/up_exit.c
+++ b/arch/hc/src/common/up_exit.c
@@ -56,9 +56,9 @@
  * Pre-processor Definitions
  ****************************************************************************/
 
-/****************************************************************************
- * Private Data
- ****************************************************************************/
+#ifndef CONFIG_DEBUG_SCHED_INFO
+#  undef CONFIG_DUMP_ON_EXIT
+#endif
 
 /****************************************************************************
  * Private Functions
@@ -74,7 +74,7 @@
  *
  ****************************************************************************/
 
-#if defined(CONFIG_DUMP_ON_EXIT) && defined(CONFIG_DEBUG_FEATURES)
+#ifdef CONFIG_DUMP_ON_EXIT
 static void _up_dumponexit(FAR struct tcb_s *tcb, FAR void *arg)
 {
 #if CONFIG_NFILE_DESCRIPTORS > 0
@@ -146,10 +146,10 @@ void _exit(int status)
 
   (void)up_irq_save();
 
-  sllinfo("TCB=%p exiting\n", this_task());
+  sinfo("TCB=%p exiting\n", this_task());
 
-#if defined(CONFIG_DUMP_ON_EXIT) && defined(CONFIG_DEBUG_FEATURES)
-  sllinfo("Other tasks:\n");
+#ifdef CONFIG_DUMP_ON_EXIT
+  sinfo("Other tasks:\n");
   sched_foreach(_up_dumponexit, NULL);
 #endif
 
diff --git a/arch/hc/src/common/up_initialize.c b/arch/hc/src/common/up_initialize.c
index 47c8abfe94a..c5b1149d04a 100644
--- a/arch/hc/src/common/up_initialize.c
+++ b/arch/hc/src/common/up_initialize.c
@@ -49,7 +49,7 @@
 #include <nuttx/net/loopback.h>
 #include <nuttx/net/tun.h>
 #include <nuttx/net/telnet.h>
-#include <nuttx/syslog/ramlog.h>
+#include <nuttx/syslog/syslog.h>
 #include <nuttx/syslog/syslog_console.h>
 
 #include "up_arch.h"
@@ -74,13 +74,13 @@ static void up_calibratedelay(void)
 {
   int i;
 
-  _llwarn("Beginning 100s delay\n");
+  _warn("Beginning 100s delay\n");
   for (i = 0; i < 100; i++)
     {
       up_mdelay(1000);
     }
 
-  _llwarn("End 100s delay\n");
+  _warn("End 100s delay\n");
 }
 #else
 # define up_calibratedelay()
@@ -178,20 +178,18 @@ void up_initialize(void)
 
 #if defined(CONFIG_DEV_LOWCONSOLE)
   lowconsole_init();
-#elif defined(CONFIG_SYSLOG_CONSOLE)
+#elif defined(CONFIG_CONSOLE_SYSLOG)
   syslog_console_init();
 #elif defined(CONFIG_RAMLOG_CONSOLE)
   ramlog_consoleinit();
 #endif
 
-  /* Initialize the system logging device */
+  /* Early initialization of the system logging device.  Some SYSLOG channel
+   * can be initialized early in the initialization sequence because they
+   * depend on only minimal OS initialization.
+   */
 
-#ifdef CONFIG_SYSLOG_CHAR
-  syslog_initialize();
-#endif
-#ifdef CONFIG_RAMLOG_SYSLOG
-  ramlog_sysloginit();
-#endif
+  syslog_initialize(SYSLOG_INIT_EARLY);
 
 #ifndef CONFIG_NETDEV_LATEINIT
   /* Initialize the network */
diff --git a/arch/hc/src/common/up_internal.h b/arch/hc/src/common/up_internal.h
index 1650711f3a6..ca582195fcf 100644
--- a/arch/hc/src/common/up_internal.h
+++ b/arch/hc/src/common/up_internal.h
@@ -62,6 +62,10 @@
 #undef  CONFIG_SUPPRESS_UART_CONFIG   /* DEFINED: Do not reconfig UART */
 #undef  CONFIG_DUMP_ON_EXIT           /* DEFINED: Dump task state on exit */
 
+#ifndef CONFIG_DEBUG_SCHED_INFO
+#  undef CONFIG_DUMP_ON_EXIT          /* Needs CONFIG_DEBUG_SCHED_INFO */
+#endif
+
 /* Determine which (if any) console driver to use.  If a console is enabled
  * and no other console device is specified, then a serial console is
  * assumed.
@@ -96,13 +100,6 @@
 #    define USE_SERIALDRIVER 1
 #endif
 
-/* Determine which device to use as the system logging device */
-
-#ifndef CONFIG_SYSLOG
-#  undef CONFIG_SYSLOG_CHAR
-#  undef CONFIG_RAMLOG_SYSLOG
-#endif
-
 /* Check if an interrupt stack size is configured */
 
 #ifndef CONFIG_ARCH_INTERRUPTSTACK
diff --git a/arch/hc/src/common/up_releasepending.c b/arch/hc/src/common/up_releasepending.c
index 5d237ac478f..f2afeabd794 100644
--- a/arch/hc/src/common/up_releasepending.c
+++ b/arch/hc/src/common/up_releasepending.c
@@ -66,7 +66,7 @@ void up_release_pending(void)
 {
   struct tcb_s *rtcb = this_task();
 
-  sllinfo("From TCB=%p\n", rtcb);
+  sinfo("From TCB=%p\n", rtcb);
 
   /* Merge the g_pendingtasks list into the ready-to-run task list */
 
diff --git a/arch/hc/src/common/up_reprioritizertr.c b/arch/hc/src/common/up_reprioritizertr.c
index 986b9ed3acf..0b0d400d9a5 100644
--- a/arch/hc/src/common/up_reprioritizertr.c
+++ b/arch/hc/src/common/up_reprioritizertr.c
@@ -95,7 +95,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority)
       struct tcb_s *rtcb = this_task();
       bool switch_needed;
 
-      sllinfo("TCB=%p PRI=%d\n", tcb, priority);
+      sinfo("TCB=%p PRI=%d\n", tcb, priority);
 
       /* Remove the tcb task from the ready-to-run list.
        * sched_removereadytorun will return true if we just
diff --git a/arch/hc/src/m9s12/m9s12_assert.c b/arch/hc/src/m9s12/m9s12_assert.c
index 2f859314f1d..496b3933a66 100644
--- a/arch/hc/src/m9s12/m9s12_assert.c
+++ b/arch/hc/src/m9s12/m9s12_assert.c
@@ -144,7 +144,7 @@ static int usbtrace_syslog(FAR const char *fmt, ...)
   /* Let vsyslog do the real work */
 
   va_start(ap, fmt);
-  ret = lowvsyslog(LOG_INFO, fmt, ap);
+  ret = vsyslog(LOG_EMERG, fmt, ap);
   va_end(ap);
   return ret;
 }
@@ -294,7 +294,7 @@ static void _up_assert(int errorcode)
 
 void up_assert(const uint8_t *filename, int lineno)
 {
-#if CONFIG_TASK_NAME_SIZE > 0
+#if CONFIG_TASK_NAME_SIZE > 0 && defined(CONFIG_DEBUG_ALERT)
   struct tcb_s *rtcb = this_task();
 #endif
 
diff --git a/arch/hc/src/m9s12/m9s12_ethernet.c b/arch/hc/src/m9s12/m9s12_ethernet.c
index 1dd9c6b4fc3..958a10affec 100644
--- a/arch/hc/src/m9s12/m9s12_ethernet.c
+++ b/arch/hc/src/m9s12/m9s12_ethernet.c
@@ -294,7 +294,7 @@ static void emac_receive(FAR struct emac_driver_s *priv)
 #ifdef CONFIG_NET_IPv4
       if (BUF->type == HTONS(ETHTYPE_IP))
         {
-          nllinfo("IPv4 frame\n");
+          ninfo("IPv4 frame\n");
 
           /* Handle ARP on input then give the IPv4 packet to the network
            * layer
@@ -334,7 +334,7 @@ static void emac_receive(FAR struct emac_driver_s *priv)
 #ifdef CONFIG_NET_IPv6
       if (BUF->type == HTONS(ETHTYPE_IP6))
         {
-          nllinfo("Iv6 frame\n");
+          ninfo("Iv6 frame\n");
 
           /* Give the IPv6 packet to the network layer */
 
diff --git a/arch/mips/src/common/up_exit.c b/arch/mips/src/common/up_exit.c
index d26de05841f..af9a79a0e75 100644
--- a/arch/mips/src/common/up_exit.c
+++ b/arch/mips/src/common/up_exit.c
@@ -58,9 +58,9 @@
  * Pre-processor Definitions
  ****************************************************************************/
 
-/****************************************************************************
- * Private Data
- ****************************************************************************/
+#ifndef CONFIG_DEBUG_SCHED_INFO
+#  undef CONFIG_DUMP_ON_EXIT
+#endif
 
 /****************************************************************************
  * Private Functions
@@ -76,7 +76,7 @@
  *
  ****************************************************************************/
 
-#if defined(CONFIG_DUMP_ON_EXIT) && defined(CONFIG_DEBUG_FEATURES)
+#ifdef CONFIG_DUMP_ON_EXIT
 static void _up_dumponexit(FAR struct tcb_s *tcb, FAR void *arg)
 {
 #if CONFIG_NFILE_DESCRIPTORS > 0
@@ -148,10 +148,10 @@ void _exit(int status)
 
   (void)up_irq_save();
 
-  sllinfo("TCB=%p exiting\n", this_task());
+  sinfo("TCB=%p exiting\n", this_task());
 
-#if defined(CONFIG_DUMP_ON_EXIT) && defined(CONFIG_DEBUG_FEATURES)
-  sllinfo("Other tasks:\n");
+#ifdef CONFIG_DUMP_ON_EXIT
+  sinfo("Other tasks:\n");
   sched_foreach(_up_dumponexit, NULL);
 #endif
 
diff --git a/arch/mips/src/common/up_initialize.c b/arch/mips/src/common/up_initialize.c
index dbb950424bb..d6d634c9bc7 100644
--- a/arch/mips/src/common/up_initialize.c
+++ b/arch/mips/src/common/up_initialize.c
@@ -49,7 +49,7 @@
 #include <nuttx/net/loopback.h>
 #include <nuttx/net/tun.h>
 #include <nuttx/net/telnet.h>
-#include <nuttx/syslog/ramlog.h>
+#include <nuttx/syslog/syslog.h>
 #include <nuttx/syslog/syslog_console.h>
 
 #include <arch/board/board.h>
@@ -76,13 +76,13 @@ static void up_calibratedelay(void)
 {
   int i;
 
-  _llwarn("Beginning 100s delay\n");
+  _warn("Beginning 100s delay\n");
   for (i = 0; i < 100; i++)
     {
       up_mdelay(1000);
     }
 
-  _llwarn("End 100s delay\n");
+  _warn("End 100s delay\n");
 }
 #else
 # define up_calibratedelay()
@@ -180,20 +180,18 @@ void up_initialize(void)
 
 #if defined(CONFIG_DEV_LOWCONSOLE)
   lowconsole_init();
-#elif defined(CONFIG_SYSLOG_CONSOLE)
+#elif defined(CONFIG_CONSOLE_SYSLOG)
   syslog_console_init();
 #elif defined(CONFIG_RAMLOG_CONSOLE)
   ramlog_consoleinit();
 #endif
 
-  /* Initialize the system logging device */
+  /* Early initialization of the system logging device.  Some SYSLOG channel
+   * can be initialized early in the initialization sequence because they
+   * depend on only minimal OS initialization.
+   */
 
-#ifdef CONFIG_SYSLOG_CHAR
-  syslog_initialize();
-#endif
-#ifdef CONFIG_RAMLOG_SYSLOG
-  ramlog_sysloginit();
-#endif
+  syslog_initialize(SYSLOG_INIT_EARLY);
 
 #ifndef CONFIG_NETDEV_LATEINIT
   /* Initialize the network */
diff --git a/arch/mips/src/common/up_internal.h b/arch/mips/src/common/up_internal.h
index 3b2ca4ccbc3..f14bc63b3c8 100644
--- a/arch/mips/src/common/up_internal.h
+++ b/arch/mips/src/common/up_internal.h
@@ -60,6 +60,10 @@
 #undef  CONFIG_SUPPRESS_UART_CONFIG   /* DEFINED: Do not reconfig UART */
 #undef  CONFIG_DUMP_ON_EXIT           /* DEFINED: Dump task state on exit */
 
+#ifndef CONFIG_DEBUG_SCHED_INFO
+#  undef CONFIG_DUMP_ON_EXIT          /* Needs CONFIG_DEBUG_SCHED_INFO */
+#endif
+
 /* Determine which (if any) console driver to use.  If a console is enabled
  * and no other console device is specified, then a serial console is
  * assumed.
@@ -94,13 +98,6 @@
 #  define USE_SERIALDRIVER 1
 #endif
 
-/* Determine which device to use as the system logging device */
-
-#ifndef CONFIG_SYSLOG
-#  undef CONFIG_SYSLOG_CHAR
-#  undef CONFIG_RAMLOG_SYSLOG
-#endif
-
 /* Check if an interrupt stack size is configured */
 
 #ifndef CONFIG_ARCH_INTERRUPTSTACK
diff --git a/arch/mips/src/mips32/up_assert.c b/arch/mips/src/mips32/up_assert.c
index 119844eb997..5723fe18405 100644
--- a/arch/mips/src/mips32/up_assert.c
+++ b/arch/mips/src/mips32/up_assert.c
@@ -109,7 +109,7 @@ static int usbtrace_syslog(FAR const char *fmt, ...)
   /* Let vsyslog do the real work */
 
   va_start(ap, fmt);
-  ret = lowvsyslog(LOG_INFO, fmt, ap);
+  ret = vsyslog(LOG_EMERG, fmt, ap);
   va_end(ap);
   return ret;
 }
@@ -131,7 +131,7 @@ static int assert_tracecallback(FAR struct usbtrace_s *trace, FAR void *arg)
 
 void up_assert(const uint8_t *filename, int lineno)
 {
-#if CONFIG_TASK_NAME_SIZE > 0
+#if CONFIG_TASK_NAME_SIZE > 0 && defined(CONFIG_DEBUG_ALERT)
   struct tcb_s *rtcb = this_task();
 #endif
 
diff --git a/arch/mips/src/mips32/up_releasepending.c b/arch/mips/src/mips32/up_releasepending.c
index 862f81ed75b..b7e1d8ce928 100644
--- a/arch/mips/src/mips32/up_releasepending.c
+++ b/arch/mips/src/mips32/up_releasepending.c
@@ -69,7 +69,7 @@ void up_release_pending(void)
 {
   struct tcb_s *rtcb = this_task();
 
-  sllinfo("From TCB=%p\n", rtcb);
+  sinfo("From TCB=%p\n", rtcb);
 
   /* Merge the g_pendingtasks list into the ready-to-run task list */
 
diff --git a/arch/mips/src/mips32/up_reprioritizertr.c b/arch/mips/src/mips32/up_reprioritizertr.c
index 7f80dd31fb8..22a204d58ba 100644
--- a/arch/mips/src/mips32/up_reprioritizertr.c
+++ b/arch/mips/src/mips32/up_reprioritizertr.c
@@ -97,7 +97,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority)
       struct tcb_s *rtcb = this_task();
       bool switch_needed;
 
-      sllinfo("TCB=%p PRI=%d\n", tcb, priority);
+      sinfo("TCB=%p PRI=%d\n", tcb, priority);
 
       /* Remove the tcb task from the ready-to-run list.
        * sched_removereadytorun will return true if we just
diff --git a/arch/mips/src/mips32/up_swint0.c b/arch/mips/src/mips32/up_swint0.c
index e7e5f21d853..95638c8c087 100644
--- a/arch/mips/src/mips32/up_swint0.c
+++ b/arch/mips/src/mips32/up_swint0.c
@@ -63,25 +63,25 @@
 #ifdef CONFIG_DEBUG_SYSCALL_INFO
 static void up_registerdump(const uint32_t *regs)
 {
-  svcllinfo("MFLO:%08x MFHI:%08x EPC:%08x STATUS:%08x\n",
-            regs[REG_MFLO], regs[REG_MFHI], regs[REG_EPC], regs[REG_STATUS]);
-  svcllinfo("AT:%08x V0:%08x V1:%08x A0:%08x A1:%08x A2:%08x A3:%08x\n",
-            regs[REG_AT], regs[REG_V0], regs[REG_V1], regs[REG_A0],
-            regs[REG_A1], regs[REG_A2], regs[REG_A3]);
-  svcllinfo("T0:%08x T1:%08x T2:%08x T3:%08x T4:%08x T5:%08x T6:%08x T7:%08x\n",
-            regs[REG_T0], regs[REG_T1], regs[REG_T2], regs[REG_T3],
-            regs[REG_T4], regs[REG_T5], regs[REG_T6], regs[REG_T7]);
-  svcllinfo("S0:%08x S1:%08x S2:%08x S3:%08x S4:%08x S5:%08x S6:%08x S7:%08x\n",
-            regs[REG_S0], regs[REG_S1], regs[REG_S2], regs[REG_S3],
-            regs[REG_S4], regs[REG_S5], regs[REG_S6], regs[REG_S7]);
+  svcinfo("MFLO:%08x MFHI:%08x EPC:%08x STATUS:%08x\n",
+          regs[REG_MFLO], regs[REG_MFHI], regs[REG_EPC], regs[REG_STATUS]);
+  svcinfo("AT:%08x V0:%08x V1:%08x A0:%08x A1:%08x A2:%08x A3:%08x\n",
+          regs[REG_AT], regs[REG_V0], regs[REG_V1], regs[REG_A0],
+          regs[REG_A1], regs[REG_A2], regs[REG_A3]);
+  svcinfo("T0:%08x T1:%08x T2:%08x T3:%08x T4:%08x T5:%08x T6:%08x T7:%08x\n",
+          regs[REG_T0], regs[REG_T1], regs[REG_T2], regs[REG_T3],
+          regs[REG_T4], regs[REG_T5], regs[REG_T6], regs[REG_T7]);
+  svcinfo("S0:%08x S1:%08x S2:%08x S3:%08x S4:%08x S5:%08x S6:%08x S7:%08x\n",
+          regs[REG_S0], regs[REG_S1], regs[REG_S2], regs[REG_S3],
+          regs[REG_S4], regs[REG_S5], regs[REG_S6], regs[REG_S7]);
 #ifdef MIPS32_SAVE_GP
-  svcllinfo("T8:%08x T9:%08x GP:%08x SP:%08x FP:%08x RA:%08x\n",
-            regs[REG_T8], regs[REG_T9], regs[REG_GP], regs[REG_SP],
-            regs[REG_FP], regs[REG_RA]);
+  svcinfo("T8:%08x T9:%08x GP:%08x SP:%08x FP:%08x RA:%08x\n",
+          regs[REG_T8], regs[REG_T9], regs[REG_GP], regs[REG_SP],
+          regs[REG_FP], regs[REG_RA]);
 #else
-  svcllinfo("T8:%08x T9:%08x SP:%08x FP:%08x RA:%08x\n",
-            regs[REG_T8], regs[REG_T9], regs[REG_SP], regs[REG_FP],
-            regs[REG_RA]);
+  svcinfo("T8:%08x T9:%08x SP:%08x FP:%08x RA:%08x\n",
+          regs[REG_T8], regs[REG_T9], regs[REG_SP], regs[REG_FP],
+          regs[REG_RA]);
 #endif
 }
 #else
@@ -142,7 +142,7 @@ int up_swint0(int irq, FAR void *context)
    */
 
 #ifdef CONFIG_DEBUG_SYSCALL_INFO
-  svcllinfo("Entry: regs: %p cmd: %d\n", regs, regs[REG_R4]);
+  svcinfo("Entry: regs: %p cmd: %d\n", regs, regs[REG_R4]);
   up_registerdump(regs);
 #endif
 
@@ -263,7 +263,7 @@ int up_swint0(int irq, FAR void *context)
 
           g_current_regs[REG_R0] -= CONFIG_SYS_RESERVED;
 #else
-          svcllerr("ERROR: Bad SYS call: %d\n", regs[REG_A0]);
+          svcerr("ERROR: Bad SYS call: %d\n", regs[REG_A0]);
 #endif
         }
         break;
@@ -274,12 +274,12 @@ int up_swint0(int irq, FAR void *context)
 #ifdef CONFIG_DEBUG_SYSCALL_INFO
   if (regs != g_current_regs)
     {
-      svcllinfo("SWInt Return: Context switch!\n");
+      svcinfo("SWInt Return: Context switch!\n");
       up_registerdump((const uint32_t *)g_current_regs);
     }
   else
     {
-      svcllinfo("SWInt Return: %d\n", regs[REG_V0]);
+      svcinfo("SWInt Return: %d\n", regs[REG_V0]);
     }
 #endif
 
diff --git a/arch/mips/src/pic32mx/pic32mx-ethernet.c b/arch/mips/src/pic32mx/pic32mx-ethernet.c
index 47cb807acf8..8578977b3b4 100644
--- a/arch/mips/src/pic32mx/pic32mx-ethernet.c
+++ b/arch/mips/src/pic32mx/pic32mx-ethernet.c
@@ -438,7 +438,7 @@ static void pic32mx_ethreset(struct pic32mx_driver_s *priv);
 #ifdef CONFIG_NET_REGDEBUG
 static void pic32mx_printreg(uint32_t addr, uint32_t val, bool iswrite)
 {
-  nllinfo("%08x%s%08x\n", addr, iswrite ? "<-" : "->", val);
+  ninfo("%08x%s%08x\n", addr, iswrite ? "<-" : "->", val);
 }
 #endif
 
@@ -488,7 +488,7 @@ static void pic32mx_checkreg(uint32_t addr, uint32_t val, bool iswrite)
             {
               /* No.. More than one. */
 
-              nllinfo("[repeats %d more times]\n", count);
+              ninfo("[repeats %d more times]\n", count);
             }
         }
 
@@ -567,12 +567,12 @@ static void pic32mx_putreg(uint32_t val, uint32_t addr)
 #ifdef CONFIG_NET_DESCDEBUG
 static void pic32mx_dumptxdesc(struct pic32mx_txdesc_s *txdesc, const char *msg)
 {
-  nllinfo("TX Descriptor [%p]: %s\n", txdesc, msg);
-  nllinfo("   status: %08x\n", txdesc->status);
-  nllinfo("  address: %08x [%08x]\n", txdesc->address, VIRT_ADDR(txdesc->address));
-  nllinfo("     tsv1: %08x\n", txdesc->tsv1);
-  nllinfo("     tsv2: %08x\n", txdesc->tsv2);
-  nllinfo("   nexted: %08x [%08x]\n", txdesc->nexted, VIRT_ADDR(txdesc->nexted));
+  ninfo("TX Descriptor [%p]: %s\n", txdesc, msg);
+  ninfo("   status: %08x\n", txdesc->status);
+  ninfo("  address: %08x [%08x]\n", txdesc->address, VIRT_ADDR(txdesc->address));
+  ninfo("     tsv1: %08x\n", txdesc->tsv1);
+  ninfo("     tsv2: %08x\n", txdesc->tsv2);
+  ninfo("   nexted: %08x [%08x]\n", txdesc->nexted, VIRT_ADDR(txdesc->nexted));
 }
 #endif
 
@@ -594,12 +594,12 @@ static void pic32mx_dumptxdesc(struct pic32mx_txdesc_s *txdesc, const char *msg)
 #ifdef CONFIG_NET_DESCDEBUG
 static void pic32mx_dumprxdesc(struct pic32mx_rxdesc_s *rxdesc, const char *msg)
 {
-  nllinfo("RX Descriptor [%p]: %s\n", rxdesc, msg);
-  nllinfo("   status: %08x\n", rxdesc->status);
-  nllinfo("  address: %08x [%08x]\n", rxdesc->address, VIRT_ADDR(rxdesc->address));
-  nllinfo("     rsv1: %08x\n", rxdesc->rsv1);
-  nllinfo("     rsv2: %08x\n", rxdesc->rsv2);
-  nllinfo("   nexted: %08x [%08x]\n", rxdesc->nexted, VIRT_ADDR(rxdesc->nexted));
+  ninfo("RX Descriptor [%p]: %s\n", rxdesc, msg);
+  ninfo("   status: %08x\n", rxdesc->status);
+  ninfo("  address: %08x [%08x]\n", rxdesc->address, VIRT_ADDR(rxdesc->address));
+  ninfo("     rsv1: %08x\n", rxdesc->rsv1);
+  ninfo("     rsv2: %08x\n", rxdesc->rsv2);
+  ninfo("   nexted: %08x [%08x]\n", rxdesc->nexted, VIRT_ADDR(rxdesc->nexted));
 }
 #endif
 
@@ -1357,8 +1357,8 @@ static void pic32mx_rxdone(struct pic32mx_driver_s *priv)
 
       if ((rxdesc->rsv2 & RXDESC_RSV2_OK) == 0)
         {
-          nllerr("ERROR. rsv1: %08x rsv2: %08x\n",
-                 rxdesc->rsv1, rxdesc->rsv2);
+          nerr("ERROR. rsv1: %08x rsv2: %08x\n",
+               rxdesc->rsv1, rxdesc->rsv2);
           NETDEV_RXERRORS(&priv->pd_dev);
           pic32mx_rxreturn(rxdesc);
         }
@@ -1371,8 +1371,8 @@ static void pic32mx_rxdone(struct pic32mx_driver_s *priv)
 
       else if (priv->pd_dev.d_len > CONFIG_NET_ETH_MTU)
         {
-          nllerr("ERROR: Too big. packet length: %d rxdesc: %08x\n",
-                 priv->pd_dev.d_len, rxdesc->status);
+          nerr("ERROR: Too big. packet length: %d rxdesc: %08x\n",
+               priv->pd_dev.d_len, rxdesc->status);
           NETDEV_RXERRORS(&priv->pd_dev);
           pic32mx_rxreturn(rxdesc);
         }
@@ -1382,8 +1382,8 @@ static void pic32mx_rxdone(struct pic32mx_driver_s *priv)
       else if ((rxdesc->status & (RXDESC_STATUS_EOP | RXDESC_STATUS_SOP)) !=
                (RXDESC_STATUS_EOP | RXDESC_STATUS_SOP))
         {
-          nllerr("ERROR: Fragment. packet length: %d rxdesc: %08x\n",
-                  priv->pd_dev.d_len, rxdesc->status);
+          nerr("ERROR: Fragment. packet length: %d rxdesc: %08x\n",
+               priv->pd_dev.d_len, rxdesc->status);
           NETDEV_RXFRAGMENTS(&priv->pd_dev);
           pic32mx_rxreturn(rxdesc);
         }
@@ -1421,7 +1421,7 @@ static void pic32mx_rxdone(struct pic32mx_driver_s *priv)
 #ifdef CONFIG_NET_IPv4
           if (BUF->type == HTONS(ETHTYPE_IP))
             {
-              nllinfo("IPv4 frame\n");
+              ninfo("IPv4 frame\n");
               NETDEV_RXIPV4(&priv->pd_dev);
 
               /* Handle ARP on input then give the IPv4 packet to the network
@@ -1463,7 +1463,7 @@ static void pic32mx_rxdone(struct pic32mx_driver_s *priv)
 #ifdef CONFIG_NET_IPv6
           if (BUF->type == HTONS(ETHTYPE_IP6))
             {
-              nllinfo("Iv6 frame\n");
+              ninfo("Iv6 frame\n");
               NETDEV_RXIPV6(&priv->pd_dev);
 
               /* Give the IPv6 packet to the network layer */
@@ -1522,8 +1522,8 @@ static void pic32mx_rxdone(struct pic32mx_driver_s *priv)
             {
               /* Unrecognized... drop it. */
 
-              nllerr("ERROR: Unrecognized packet type dropped: %04x\n",
-                     ntohs(BUF->type));
+              nerr("ERROR: Unrecognized packet type dropped: %04x\n",
+                   ntohs(BUF->type));
               NETDEV_RXDROPPED(&priv->pd_dev);
             }
 
@@ -1685,7 +1685,7 @@ static int pic32mx_interrupt(int irq, void *context)
 
       if ((status & ETH_INT_RXOVFLW) != 0)
         {
-          nllerr("ERROR: RX Overrun. status: %08x\n", status);
+          nerr("ERROR: RX Overrun. status: %08x\n", status);
           NETDEV_RXERRORS(&priv->pd_dev);
         }
 
@@ -1696,7 +1696,7 @@ static int pic32mx_interrupt(int irq, void *context)
 
       if ((status & ETH_INT_RXBUFNA) != 0)
         {
-          nllerr("ERROR: RX buffer descriptor overrun. status: %08x\n", status);
+          nerr("ERROR: RX buffer descriptor overrun. status: %08x\n", status);
           NETDEV_RXERRORS(&priv->pd_dev);
         }
 
@@ -1707,7 +1707,7 @@ static int pic32mx_interrupt(int irq, void *context)
 
       if ((status & ETH_INT_RXBUSE) != 0)
         {
-          nllerr("ERROR: RX BVCI bus error. status: %08x\n", status);
+          nerr("ERROR: RX BVCI bus error. status: %08x\n", status);
           NETDEV_RXERRORS(&priv->pd_dev);
         }
 
@@ -1750,7 +1750,7 @@ static int pic32mx_interrupt(int irq, void *context)
 
       if ((status & ETH_INT_TXABORT) != 0)
         {
-          nllerr("ERROR: TX abort. status: %08x\n", status);
+          nerr("ERROR: TX abort. status: %08x\n", status);
           NETDEV_TXERRORS(&priv->pd_dev);
         }
 
@@ -1761,7 +1761,7 @@ static int pic32mx_interrupt(int irq, void *context)
 
       if ((status & ETH_INT_TXBUSE) != 0)
         {
-          nllerr("ERROR: TX BVCI bus error. status: %08x\n", status);
+          nerr("ERROR: TX BVCI bus error. status: %08x\n", status);
           NETDEV_TXERRORS(&priv->pd_dev);
         }
 
@@ -2367,14 +2367,14 @@ static int pic32mx_rmmac(struct net_driver_s *dev, const uint8_t *mac)
 #if defined(CONFIG_NET_REGDEBUG) && defined(PIC32MX_HAVE_PHY)
 static void pic32mx_showmii(uint8_t phyaddr, const char *msg)
 {
-  nllinfo("PHY " PIC32MX_PHYNAME ": %s\n", msg);
-  nllinfo("  MCR:       %04x\n", pic32mx_phyread(phyaddr, MII_MCR));
-  nllinfo("  MSR:       %04x\n", pic32mx_phyread(phyaddr, MII_MSR));
-  nllinfo("  ADVERTISE: %04x\n", pic32mx_phyread(phyaddr, MII_ADVERTISE));
-  nllinfo("  LPA:       %04x\n", pic32mx_phyread(phyaddr, MII_LPA));
-  nllinfo("  EXPANSION: %04x\n", pic32mx_phyread(phyaddr, MII_EXPANSION));
+  ninfo("PHY " PIC32MX_PHYNAME ": %s\n", msg);
+  ninfo("  MCR:       %04x\n", pic32mx_phyread(phyaddr, MII_MCR));
+  ninfo("  MSR:       %04x\n", pic32mx_phyread(phyaddr, MII_MSR));
+  ninfo("  ADVERTISE: %04x\n", pic32mx_phyread(phyaddr, MII_ADVERTISE));
+  ninfo("  LPA:       %04x\n", pic32mx_phyread(phyaddr, MII_LPA));
+  ninfo("  EXPANSION: %04x\n", pic32mx_phyread(phyaddr, MII_EXPANSION));
 #ifdef CONFIG_ETH0_PHY_KS8721
-  nllinfo("  10BTCR:    %04x\n", pic32mx_phyread(phyaddr, MII_KS8721_10BTCR));
+  ninfo("  10BTCR:    %04x\n", pic32mx_phyread(phyaddr, MII_KS8721_10BTCR));
 #endif
 }
 #endif
diff --git a/arch/mips/src/pic32mx/pic32mx-serial.c b/arch/mips/src/pic32mx/pic32mx-serial.c
index 7617a8f3a0c..ebd20cdfdda 100644
--- a/arch/mips/src/pic32mx/pic32mx-serial.c
+++ b/arch/mips/src/pic32mx/pic32mx-serial.c
@@ -500,8 +500,8 @@ static int up_interrupt(int irq, void *context)
            /* Clear the pending error interrupt */
 
            up_clrpend_irq(priv->irqe);
-           _llerr("ERROR: interrupt STA: %08x\n",
-                 up_serialin(priv, PIC32MX_UART_STA_OFFSET));
+           _err("ERROR: interrupt STA: %08x\n",
+               up_serialin(priv, PIC32MX_UART_STA_OFFSET));
            handled = true;
         }
 #endif
diff --git a/arch/mips/src/pic32mx/pic32mx-spi.c b/arch/mips/src/pic32mx/pic32mx-spi.c
index c56ff271c3c..2489f671c45 100644
--- a/arch/mips/src/pic32mx/pic32mx-spi.c
+++ b/arch/mips/src/pic32mx/pic32mx-spi.c
@@ -315,7 +315,7 @@ static uint32_t spi_getreg(FAR struct pic32mx_dev_s *priv, unsigned int offset)
         {
            if (count == 4)
              {
-               _llinfo("...\n");
+               _info("...\n");
              }
           return value;
         }
@@ -331,7 +331,7 @@ static uint32_t spi_getreg(FAR struct pic32mx_dev_s *priv, unsigned int offset)
          {
            /* Yes.. then show how many times the value repeated */
 
-           _llinfo("[repeats %d more times]\n", count-3);
+           _info("[repeats %d more times]\n", count-3);
          }
 
        /* Save the new address, value, and count */
@@ -343,7 +343,7 @@ static uint32_t spi_getreg(FAR struct pic32mx_dev_s *priv, unsigned int offset)
 
   /* Show the register value read */
 
-  _llinfo("%08x->%08x\n", addr, value);
+  _info("%08x->%08x\n", addr, value);
   return value;
 }
 #else
@@ -381,7 +381,7 @@ static void spi_putreg(FAR struct pic32mx_dev_s *priv, unsigned int offset,
 
   /* Show the register value being written */
 
-  _llinfo("%08x<-%08x\n", addr, value);
+  _info("%08x<-%08x\n", addr, value);
 
   /* Then do the write */
 
diff --git a/arch/mips/src/pic32mx/pic32mx-usbdev.c b/arch/mips/src/pic32mx/pic32mx-usbdev.c
index 85d2705c70b..da5544580a9 100644
--- a/arch/mips/src/pic32mx/pic32mx-usbdev.c
+++ b/arch/mips/src/pic32mx/pic32mx-usbdev.c
@@ -280,9 +280,9 @@
 #  undef CONFIG_PIC32MX_USBDEV_BDTDEBUG
 #  define CONFIG_PIC32MX_USBDEV_BDTDEBUG 1
 
-#  define regerr  _llerr
-#  define regwarn _llwarn
-#  define reginfo _llinfo
+#  define regerr  _err
+#  define regwarn _warn
+#  define reginfo _info
 
 #else
 
@@ -298,9 +298,9 @@
 
 #ifdef CONFIG_PIC32MX_USBDEV_BDTDEBUG
 
-#  define bdterr  _llerr
-#  define bdtwarn _llwarn
-#  define bdtinfo _llinfo
+#  define bdterr  _err
+#  define bdtwarn _warn
+#  define bdtinfo _info
 
 #else
 
@@ -893,15 +893,15 @@ static void pic32mx_wrcomplete(struct pic32mx_usbdev_s *priv,
   epno   = USB_EPNO(privep->ep.eplog);
 
 #ifdef CONFIG_USBDEV_NOWRITEAHEAD
-  ullinfo("EP%d: len=%d xfrd=%d inflight=%d\n",
-          epno, privreq->req.len, privreq->req.xfrd, privreq->inflight[0]);
+  uinfo("EP%d: len=%d xfrd=%d inflight=%d\n",
+        epno, privreq->req.len, privreq->req.xfrd, privreq->inflight[0]);
 #else
-  ullinfo("EP%d: len=%d xfrd=%d inflight={%d, %d}\n",
-          epno, privreq->req.len, privreq->req.xfrd,
-          privreq->inflight[0], privreq->inflight[1]);
+  uinfo("EP%d: len=%d xfrd=%d inflight={%d, %d}\n",
+        epno, privreq->req.len, privreq->req.xfrd,
+        privreq->inflight[0], privreq->inflight[1]);
 #endif
   bdtinfo("EP%d BDT IN [%p] {%08x, %08x}\n",
-          epno, bdtin, bdtin->status, bdtin->addr);
+        epno, bdtin, bdtin->status, bdtin->addr);
 
   /* We should own the BDT that just completed. But NULLify the entire BDT IN.
    * Why?  So that we can tell later that the BDT available.  No, it is not
@@ -1209,8 +1209,8 @@ static int pic32mx_wrstart(struct pic32mx_usbdev_s *priv,
       bytesleft = privreq->req.len;
     }
 
-  ullinfo("epno=%d req=%p: len=%d xfrd=%d index=%d nullpkt=%d\n",
-          epno, privreq, privreq->req.len, xfrd, index, privep->txnullpkt);
+  uinfo("epno=%d req=%p: len=%d xfrd=%d index=%d nullpkt=%d\n",
+        epno, privreq, privreq->req.len, xfrd, index, privep->txnullpkt);
 
   /* Get the number of bytes left to be sent in the packet */
 
@@ -1323,10 +1323,10 @@ static int pic32mx_rdcomplete(struct pic32mx_usbdev_s *priv,
   bdtout = privep->bdtout;
   epno   = USB_EPNO(privep->ep.eplog);
 
-  ullinfo("EP%d: len=%d xfrd=%d\n",
-          epno, privreq->req.len, privreq->req.xfrd);
+  uinfo("EP%d: len=%d xfrd=%d\n",
+        epno, privreq->req.len, privreq->req.xfrd);
   bdtinfo("EP%d BDT OUT [%p] {%08x, %08x}\n",
-          epno, bdtout, bdtout->status, bdtout->addr);
+        epno, bdtout, bdtout->status, bdtout->addr);
 
   /* We should own the BDT that just completed */
 
@@ -1613,7 +1613,7 @@ static int pic32mx_rdrequest(struct pic32mx_usbdev_s *priv,
       return OK;
     }
 
-  ullinfo("EP%d: len=%d\n", USB_EPNO(privep->ep.eplog), privreq->req.len);
+  uinfo("EP%d: len=%d\n", USB_EPNO(privep->ep.eplog), privreq->req.len);
 
   /* Ignore any attempt to receive a zero length packet */
 
@@ -1902,8 +1902,8 @@ static void pic32mx_ep0setup(struct pic32mx_usbdev_s *priv)
   index.w = GETUINT16(priv->ctrl.index);
   len.w   = GETUINT16(priv->ctrl.len);
 
-  ullinfo("SETUP: type=%02x req=%02x value=%04x index=%04x len=%04x\n",
-          priv->ctrl.type, priv->ctrl.req, value.w, index.w, len.w);
+  uinfo("SETUP: type=%02x req=%02x value=%04x index=%04x len=%04x\n",
+        priv->ctrl.type, priv->ctrl.req, value.w, index.w, len.w);
 
   /* Dispatch any non-standard requests */
 
@@ -2146,7 +2146,7 @@ static void pic32mx_ep0setup(struct pic32mx_usbdev_s *priv)
               {
                 /* Special case recipient=device test mode */
 
-                ullinfo("test mode: %d\n", index.w);
+                uinfo("test mode: %d\n", index.w);
               }
             else
               {
@@ -2820,7 +2820,7 @@ static int pic32mx_interrupt(int irq, void *context)
   if ((usbir & USB_INT_UERR) != 0)
     {
       usbtrace(TRACE_INTDECODE(PIC32MX_TRACEINTID_UERR), usbir);
-      ullerr("ERROR: EIR=%04x\n", pic32mx_getreg(PIC32MX_USB_EIR));
+      uerr("ERROR: EIR=%04x\n", pic32mx_getreg(PIC32MX_USB_EIR));
 
       /* Clear all pending USB error interrupts */
 
@@ -3140,7 +3140,7 @@ static int pic32mx_epconfigure(struct usbdev_ep_s *ep,
   if (!ep || !desc)
     {
       usbtrace(TRACE_DEVERROR(PIC32MX_TRACEERR_INVALIDPARMS), 0);
-      ullerr("ERROR: ep=%p desc=%p\n");
+      uerr("ERROR: ep=%p desc=%p\n");
       return -EINVAL;
     }
 #endif
@@ -3271,7 +3271,7 @@ static int pic32mx_epdisable(struct usbdev_ep_s *ep)
   if (!ep)
     {
       usbtrace(TRACE_DEVERROR(PIC32MX_TRACEERR_INVALIDPARMS), 0);
-      ullerr("ERROR: ep=%p\n", ep);
+      uerr("ERROR: ep=%p\n", ep);
       return -EINVAL;
     }
 #endif
@@ -3368,8 +3368,8 @@ static int pic32mx_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req)
   if (!req || !req->callback || !req->buf || !ep)
     {
       usbtrace(TRACE_DEVERROR(PIC32MX_TRACEERR_INVALIDPARMS), 0);
-      ullerr("ERROR: req=%p callback=%p buf=%p ep=%p\n",
-             req, req->callback, req->buf, ep);
+      uerr("ERROR: req=%p callback=%p buf=%p ep=%p\n",
+           req, req->callback, req->buf, ep);
       return -EINVAL;
     }
 #endif
@@ -3381,7 +3381,7 @@ static int pic32mx_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req)
   if (!priv->driver)
     {
       usbtrace(TRACE_DEVERROR(PIC32MX_TRACEERR_NOTCONFIGURED), priv->usbdev.speed);
-      ullerr("ERROR: driver=%p\n", priv->driver);
+      uerr("ERROR: driver=%p\n", priv->driver);
       return -ESHUTDOWN;
     }
 #endif
diff --git a/arch/mips/src/pic32mz/pic32mz-ethernet.c b/arch/mips/src/pic32mz/pic32mz-ethernet.c
index c1e2671f927..87a91962d4e 100644
--- a/arch/mips/src/pic32mz/pic32mz-ethernet.c
+++ b/arch/mips/src/pic32mz/pic32mz-ethernet.c
@@ -465,7 +465,7 @@ static void pic32mz_ethreset(struct pic32mz_driver_s *priv);
 #ifdef CONFIG_NET_REGDEBUG
 static void pic32mz_printreg(uint32_t addr, uint32_t val, bool iswrite)
 {
-  nllinfo("%08x%s%08x\n", addr, iswrite ? "<-" : "->", val);
+  ninfo("%08x%s%08x\n", addr, iswrite ? "<-" : "->", val);
 }
 #endif
 
@@ -515,7 +515,7 @@ static void pic32mz_checkreg(uint32_t addr, uint32_t val, bool iswrite)
             {
               /* No.. More than one. */
 
-              nllinfo("[repeats %d more times]\n", count);
+              ninfo("[repeats %d more times]\n", count);
             }
         }
 
@@ -594,12 +594,12 @@ static void pic32mz_putreg(uint32_t val, uint32_t addr)
 #ifdef CONFIG_NET_DESCDEBUG
 static void pic32mz_dumptxdesc(struct pic32mz_txdesc_s *txdesc, const char *msg)
 {
-  nllinfo("TX Descriptor [%p]: %s\n", txdesc, msg);
-  nllinfo("   status: %08x\n", txdesc->status);
-  nllinfo("  address: %08x [%08x]\n", txdesc->address, VIRT_ADDR(txdesc->address));
-  nllinfo("     tsv1: %08x\n", txdesc->tsv1);
-  nllinfo("     tsv2: %08x\n", txdesc->tsv2);
-  nllinfo("   nexted: %08x [%08x]\n", txdesc->nexted, VIRT_ADDR(txdesc->nexted));
+  ninfo("TX Descriptor [%p]: %s\n", txdesc, msg);
+  ninfo("   status: %08x\n", txdesc->status);
+  ninfo("  address: %08x [%08x]\n", txdesc->address, VIRT_ADDR(txdesc->address));
+  ninfo("     tsv1: %08x\n", txdesc->tsv1);
+  ninfo("     tsv2: %08x\n", txdesc->tsv2);
+  ninfo("   nexted: %08x [%08x]\n", txdesc->nexted, VIRT_ADDR(txdesc->nexted));
 }
 #endif
 
@@ -621,12 +621,12 @@ static void pic32mz_dumptxdesc(struct pic32mz_txdesc_s *txdesc, const char *msg)
 #ifdef CONFIG_NET_DESCDEBUG
 static void pic32mz_dumprxdesc(struct pic32mz_rxdesc_s *rxdesc, const char *msg)
 {
-  nllinfo("RX Descriptor [%p]: %s\n", rxdesc, msg);
-  nllinfo("   status: %08x\n", rxdesc->status);
-  nllinfo("  address: %08x [%08x]\n", rxdesc->address, VIRT_ADDR(rxdesc->address));
-  nllinfo("     rsv1: %08x\n", rxdesc->rsv1);
-  nllinfo("     rsv2: %08x\n", rxdesc->rsv2);
-  nllinfo("   nexted: %08x [%08x]\n", rxdesc->nexted, VIRT_ADDR(rxdesc->nexted));
+  ninfo("RX Descriptor [%p]: %s\n", rxdesc, msg);
+  ninfo("   status: %08x\n", rxdesc->status);
+  ninfo("  address: %08x [%08x]\n", rxdesc->address, VIRT_ADDR(rxdesc->address));
+  ninfo("     rsv1: %08x\n", rxdesc->rsv1);
+  ninfo("     rsv2: %08x\n", rxdesc->rsv2);
+  ninfo("   nexted: %08x [%08x]\n", rxdesc->nexted, VIRT_ADDR(rxdesc->nexted));
 }
 #endif
 
@@ -1384,8 +1384,8 @@ static void pic32mz_rxdone(struct pic32mz_driver_s *priv)
 
       if ((rxdesc->rsv2 & RXDESC_RSV2_OK) == 0)
         {
-          nllwarn("WARNING. rsv1: %08x rsv2: %08x\n",
-                 rxdesc->rsv1, rxdesc->rsv2);
+          nwarn("WARNING. rsv1: %08x rsv2: %08x\n",
+                rxdesc->rsv1, rxdesc->rsv2);
           NETDEV_RXERRORS(&priv->pd_dev);
           pic32mz_rxreturn(rxdesc);
         }
@@ -1398,8 +1398,8 @@ static void pic32mz_rxdone(struct pic32mz_driver_s *priv)
 
       else if (priv->pd_dev.d_len > CONFIG_NET_ETH_MTU)
         {
-          nllwarn("WARNING: Too big. packet length: %d rxdesc: %08x\n",
-                  priv->pd_dev.d_len, rxdesc->status);
+          nwarn("WARNING: Too big. packet length: %d rxdesc: %08x\n",
+                priv->pd_dev.d_len, rxdesc->status);
           NETDEV_RXERRORS(&priv->pd_dev);
           pic32mz_rxreturn(rxdesc);
         }
@@ -1409,8 +1409,8 @@ static void pic32mz_rxdone(struct pic32mz_driver_s *priv)
       else if ((rxdesc->status & (RXDESC_STATUS_EOP | RXDESC_STATUS_SOP)) !=
                (RXDESC_STATUS_EOP | RXDESC_STATUS_SOP))
         {
-          nllwarn("WARNING: Fragment. packet length: %d rxdesc: %08x\n",
-                 priv->pd_dev.d_len, rxdesc->status);
+          nwarn("WARNING: Fragment. packet length: %d rxdesc: %08x\n",
+                priv->pd_dev.d_len, rxdesc->status);
           NETDEV_RXFRAGMENTS(&priv->pd_dev);
           pic32mz_rxreturn(rxdesc);
         }
@@ -1448,7 +1448,7 @@ static void pic32mz_rxdone(struct pic32mz_driver_s *priv)
 #ifdef CONFIG_NET_IPv4
           if (BUF->type == HTONS(ETHTYPE_IP))
             {
-              nllinfo("IPv4 frame\n");
+              ninfo("IPv4 frame\n");
               NETDEV_RXIPV4(&priv->pd_dev);
 
               /* Handle ARP on input then give the IPv4 packet to the network
@@ -1490,7 +1490,7 @@ static void pic32mz_rxdone(struct pic32mz_driver_s *priv)
 #ifdef CONFIG_NET_IPv6
           if (BUF->type == HTONS(ETHTYPE_IP6))
             {
-              nllinfo("Iv6 frame\n");
+              ninfo("Iv6 frame\n");
               NETDEV_RXIPV6(&priv->pd_dev);
 
               /* Give the IPv6 packet to the network layer */
@@ -1549,8 +1549,8 @@ static void pic32mz_rxdone(struct pic32mz_driver_s *priv)
             {
               /* Unrecognized... drop it. */
 
-              nllwarn("WARNING: Unrecognized packet type dropped: %04x\n",
-                      ntohs(BUF->type));
+              nwarn("WARNING: Unrecognized packet type dropped: %04x\n",
+                    ntohs(BUF->type));
               NETDEV_RXDROPPED(&priv->pd_dev);
             }
 
@@ -1712,7 +1712,7 @@ static int pic32mz_interrupt(int irq, void *context)
 
       if ((status & ETH_INT_RXOVFLW) != 0)
         {
-          nllerr("ERROR: RX Overrun. status: %08x\n", status);
+          nerr("ERROR: RX Overrun. status: %08x\n", status);
           NETDEV_RXERRORS(&priv->pd_dev);
         }
 
@@ -1723,7 +1723,7 @@ static int pic32mz_interrupt(int irq, void *context)
 
       if ((status & ETH_INT_RXBUFNA) != 0)
         {
-          nllerr("ERROR: RX buffer descriptor overrun. status: %08x\n", status);
+          nerr("ERROR: RX buffer descriptor overrun. status: %08x\n", status);
           NETDEV_RXERRORS(&priv->pd_dev);
         }
 
@@ -1734,7 +1734,7 @@ static int pic32mz_interrupt(int irq, void *context)
 
       if ((status & ETH_INT_RXBUSE) != 0)
         {
-          nllerr("ERROR: RX BVCI bus error. status: %08x\n", status);
+          nerr("ERROR: RX BVCI bus error. status: %08x\n", status);
           NETDEV_RXERRORS(&priv->pd_dev);
         }
 
@@ -1777,7 +1777,7 @@ static int pic32mz_interrupt(int irq, void *context)
 
       if ((status & ETH_INT_TXABORT) != 0)
         {
-          nllerr("ERROR: TX abort. status: %08x\n", status);
+          nerr("ERROR: TX abort. status: %08x\n", status);
           NETDEV_TXERRORS(&priv->pd_dev);
         }
 
@@ -1788,7 +1788,7 @@ static int pic32mz_interrupt(int irq, void *context)
 
       if ((status & ETH_INT_TXBUSE) != 0)
         {
-          nllerr("ERROR: TX BVCI bus error. status: %08x\n", status);
+          nerr("ERROR: TX BVCI bus error. status: %08x\n", status);
           NETDEV_TXERRORS(&priv->pd_dev);
         }
 
@@ -1942,7 +1942,7 @@ static int pic32mz_ifup(struct net_driver_s *dev)
   uint32_t regval;
   int ret;
 
-  nnllinfoBringing up: %d.%d.%d.%d\n",
+  ninfo("Bringing up: %d.%d.%d.%d\n",
         dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff,
         (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24);
 
@@ -2399,14 +2399,14 @@ static int pic32mz_rmmac(struct net_driver_s *dev, const uint8_t *mac)
 #if defined(CONFIG_NET_REGDEBUG) && defined(PIC32MZ_HAVE_PHY)
 static void pic32mz_showmii(uint8_t phyaddr, const char *msg)
 {
-  nllinfo("PHY " PIC32MZ_PHYNAME ": %s\n", msg);
-  nllinfo("  MCR:       %04x\n", pic32mz_phyread(phyaddr, MII_MCR));
-  nllinfo("  MSR:       %04x\n", pic32mz_phyread(phyaddr, MII_MSR));
-  nllinfo("  ADVERTISE: %04x\n", pic32mz_phyread(phyaddr, MII_ADVERTISE));
-  nllinfo("  LPA:       %04x\n", pic32mz_phyread(phyaddr, MII_LPA));
-  nllinfo("  EXPANSION: %04x\n", pic32mz_phyread(phyaddr, MII_EXPANSION));
+  ninfo("PHY " PIC32MZ_PHYNAME ": %s\n", msg);
+  ninfo("  MCR:       %04x\n", pic32mz_phyread(phyaddr, MII_MCR));
+  ninfo("  MSR:       %04x\n", pic32mz_phyread(phyaddr, MII_MSR));
+  ninfo("  ADVERTISE: %04x\n", pic32mz_phyread(phyaddr, MII_ADVERTISE));
+  ninfo("  LPA:       %04x\n", pic32mz_phyread(phyaddr, MII_LPA));
+  ninfo("  EXPANSION: %04x\n", pic32mz_phyread(phyaddr, MII_EXPANSION));
 #ifdef CONFIG_ETH0_PHY_KS8721
-  nllinfo("  10BTCR:    %04x\n", pic32mz_phyread(phyaddr, MII_KS8721_10BTCR));
+  ninfo("  10BTCR:    %04x\n", pic32mz_phyread(phyaddr, MII_KS8721_10BTCR));
 #endif
 }
 #endif
diff --git a/arch/mips/src/pic32mz/pic32mz-serial.c b/arch/mips/src/pic32mz/pic32mz-serial.c
index e14ab4472f1..fcdc0c1874d 100644
--- a/arch/mips/src/pic32mz/pic32mz-serial.c
+++ b/arch/mips/src/pic32mz/pic32mz-serial.c
@@ -752,14 +752,14 @@ static int  up_interrupt(struct uart_dev_s *dev)
        *  - Overflow condition for the receive buffer OERR (UxSTA bit 1) occurs
        */
 
-#ifdef CONFIG_DEBUG_FEATURES
+#ifdef CONFIG_DEBUG_ERROR
       if (up_pending_irq(priv->irqe))
         {
            /* Clear the pending error interrupt */
 
            up_clrpend_irq(priv->irqe);
-           _llerr("ERROR: interrupt STA: %08x\n",
-                 up_serialin(priv, PIC32MZ_UART_STA_OFFSET));
+           _err("ERROR: interrupt STA: %08x\n",
+                up_serialin(priv, PIC32MZ_UART_STA_OFFSET));
            handled = true;
         }
 #endif
@@ -1008,7 +1008,7 @@ static void up_rxint(struct uart_dev_s *dev, bool enable)
        */
 
 #ifndef CONFIG_SUPPRESS_SERIAL_INTS
-#ifdef CONFIG_DEBUG_FEATURES
+#ifdef CONFIG_DEBUG_ERROR
       up_enable_irq(priv->irqe);
 #endif
       up_enable_irq(priv->irqrx);
@@ -1017,7 +1017,7 @@ static void up_rxint(struct uart_dev_s *dev, bool enable)
     }
   else
     {
-#ifdef CONFIG_DEBUG_FEATURES
+#ifdef CONFIG_DEBUG_ERROR
       up_disable_irq(priv->irqe);
 #endif
       up_disable_irq(priv->irqrx);
diff --git a/arch/mips/src/pic32mz/pic32mz-spi.c b/arch/mips/src/pic32mz/pic32mz-spi.c
index b2ddd66d7c8..3eea799d10c 100644
--- a/arch/mips/src/pic32mz/pic32mz-spi.c
+++ b/arch/mips/src/pic32mz/pic32mz-spi.c
@@ -482,7 +482,7 @@ static bool spi_checkreg(struct pic32mz_dev_s *priv, uintptr_t regaddr,
         {
           /* Yes... show how many times we did it */
 
-          _llinfo("...[Repeats %d times]...\n", priv->ntimes);
+          _info("...[Repeats %d times]...\n", priv->ntimes);
         }
 
       /* Save information about the new access */
@@ -532,8 +532,8 @@ static uint32_t spi_getreg(FAR struct pic32mz_dev_s *priv,
     {
       /* Yes.. */
 
-      _llinfo("%08lx->%08lx\n",
-             (unsigned long)regaddr, (unsigned long)regval);
+      _info("%08lx->%08lx\n",
+           (unsigned long)regaddr, (unsigned long)regval);
     }
 
   /* Return the value read */
@@ -574,8 +574,8 @@ static void spi_putaddr(FAR struct pic32mz_dev_s *priv, uintptr_t regaddr,
     {
       /* Yes.. */
 
-      _llinfo("%08lx<-%08lx\n",
-             (unsigned long)regaddr, (unsigned long)regval);
+      _info("%08lx<-%08lx\n",
+           (unsigned long)regaddr, (unsigned long)regval);
     }
 
   /* Write the value to the register */
diff --git a/arch/sh/src/common/up_assert.c b/arch/sh/src/common/up_assert.c
index 95abc9b1903..ec02578cfd0 100644
--- a/arch/sh/src/common/up_assert.c
+++ b/arch/sh/src/common/up_assert.c
@@ -110,7 +110,7 @@ static int usbtrace_syslog(FAR const char *fmt, ...)
   /* Let vsyslog do the real work */
 
   va_start(ap, fmt);
-  ret = lowvsyslog(LOG_INFO, fmt, ap);
+  ret = vsyslog(LOG_EMERG, fmt, ap);
   va_end(ap);
   return ret;
 }
@@ -132,7 +132,7 @@ static int assert_tracecallback(FAR struct usbtrace_s *trace, FAR void *arg)
 
 void up_assert(const uint8_t *filename, int lineno)
 {
-#if CONFIG_TASK_NAME_SIZE > 0
+#if CONFIG_TASK_NAME_SIZE > 0 && defined(CONFIG_DEBUG_ALERT)
   struct tcb_s *rtcb = this_task();
 #endif
 
diff --git a/arch/sh/src/common/up_exit.c b/arch/sh/src/common/up_exit.c
index 4b4ba44337c..1aa9644dba9 100644
--- a/arch/sh/src/common/up_exit.c
+++ b/arch/sh/src/common/up_exit.c
@@ -57,9 +57,9 @@
  * Pre-processor Definitions
  ****************************************************************************/
 
-/****************************************************************************
- * Private Data
- ****************************************************************************/
+#ifndef CONFIG_DEBUG_SCHED_INFO
+#  undef CONFIG_DUMP_ON_EXIT
+#endif
 
 /****************************************************************************
  * Private Functions
@@ -75,7 +75,7 @@
  *
  ****************************************************************************/
 
-#if defined(CONFIG_DUMP_ON_EXIT) && defined(CONFIG_DEBUG_FEATURES)
+#ifdef CONFIG_DUMP_ON_EXIT
 static void _up_dumponexit(FAR struct tcb_s *tcb, FAR void *arg)
 {
 #if CONFIG_NFILE_DESCRIPTORS > 0
@@ -147,10 +147,10 @@ void _exit(int status)
 
   (void)up_irq_save();
 
-  sllinfo("TCB=%p exiting\n", this_task());
+  sinfo("TCB=%p exiting\n", this_task());
 
-#if defined(CONFIG_DUMP_ON_EXIT) && defined(CONFIG_DEBUG_FEATURES)
-  sllinfo("Other tasks:\n");
+#ifdef CONFIG_DUMP_ON_EXIT
+  sinfo("Other tasks:\n");
   sched_foreach(_up_dumponexit, NULL);
 #endif
 
diff --git a/arch/sh/src/common/up_initialize.c b/arch/sh/src/common/up_initialize.c
index 89fb6579c34..c333f4b9939 100644
--- a/arch/sh/src/common/up_initialize.c
+++ b/arch/sh/src/common/up_initialize.c
@@ -49,7 +49,7 @@
 #include <nuttx/net/loopback.h>
 #include <nuttx/net/tun.h>
 #include <nuttx/net/telnet.h>
-#include <nuttx/syslog/ramlog.h>
+#include <nuttx/syslog/syslog.h>
 #include <nuttx/syslog/syslog_console.h>
 
 #include "up_arch.h"
@@ -82,13 +82,13 @@ static void up_calibratedelay(void)
 {
   int i;
 
-  sllwarn("Beginning 100s delay\n");
+  swarn("Beginning 100s delay\n");
   for (i = 0; i < 100; i++)
     {
       up_mdelay(1000);
     }
 
-  sllwarn("End 100s delay\n");
+  swarn("End 100s delay\n");
 }
 #else
 # define up_calibratedelay()
@@ -172,20 +172,18 @@ void up_initialize(void)
 
 #if defined(CONFIG_DEV_LOWCONSOLE)
   lowconsole_init();
-#elif defined(CONFIG_SYSLOG_CONSOLE)
+#elif defined(CONFIG_CONSOLE_SYSLOG)
   syslog_console_init();
 #elif defined(CONFIG_RAMLOG_CONSOLE)
   ramlog_consoleinit();
 #endif
 
-  /* Initialize the system logging device */
+  /* Early initialization of the system logging device.  Some SYSLOG channel
+   * can be initialized early in the initialization sequence because they
+   * depend on only minimal OS initialization.
+   */
 
-#ifdef CONFIG_SYSLOG_CHAR
-  syslog_initialize();
-#endif
-#ifdef CONFIG_RAMLOG_SYSLOG
-  ramlog_sysloginit();
-#endif
+  syslog_initialize(SYSLOG_INIT_EARLY);
 
 #ifndef CONFIG_NETDEV_LATEINIT
   /* Initialize the network */
diff --git a/arch/sh/src/common/up_internal.h b/arch/sh/src/common/up_internal.h
index 5f1a54bb3ef..c055436edb6 100644
--- a/arch/sh/src/common/up_internal.h
+++ b/arch/sh/src/common/up_internal.h
@@ -101,13 +101,6 @@
 #  define USE_SERIALDRIVER 1
 #endif
 
-/* Determine which device to use as the system logging device */
-
-#ifndef CONFIG_SYSLOG
-#  undef CONFIG_SYSLOG_CHAR
-#  undef CONFIG_RAMLOG_SYSLOG
-#endif
-
 /* Check if an interrupt stack size is configured */
 
 #ifndef CONFIG_ARCH_INTERRUPTSTACK
diff --git a/arch/sh/src/common/up_releasepending.c b/arch/sh/src/common/up_releasepending.c
index 1f36fd752ba..195935ff458 100644
--- a/arch/sh/src/common/up_releasepending.c
+++ b/arch/sh/src/common/up_releasepending.c
@@ -67,7 +67,7 @@ void up_release_pending(void)
 {
   struct tcb_s *rtcb = this_task();
 
-  sllinfo("From TCB=%p\n", rtcb);
+  sinfo("From TCB=%p\n", rtcb);
 
   /* Merge the g_pendingtasks list into the ready-to-run task list */
 
diff --git a/arch/sh/src/common/up_reprioritizertr.c b/arch/sh/src/common/up_reprioritizertr.c
index bce7c4e144f..f2d0d1a2266 100644
--- a/arch/sh/src/common/up_reprioritizertr.c
+++ b/arch/sh/src/common/up_reprioritizertr.c
@@ -95,7 +95,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority)
       struct tcb_s *rtcb = this_task();
       bool switch_needed;
 
-      sllinfo("TCB=%p PRI=%d\n", tcb, priority);
+      sinfo("TCB=%p PRI=%d\n", tcb, priority);
 
       /* Remove the tcb task from the ready-to-run list.
        * sched_removereadytorun will return true if we just
diff --git a/arch/sim/src/up_blocktask.c b/arch/sim/src/up_blocktask.c
index 63749556c3b..27223b19c3b 100644
--- a/arch/sim/src/up_blocktask.c
+++ b/arch/sim/src/up_blocktask.c
@@ -83,7 +83,7 @@ void up_block_task(struct tcb_s *tcb, tstate_t task_state)
   ASSERT((tcb->task_state >= FIRST_READY_TO_RUN_STATE) &&
          (tcb->task_state <= LAST_READY_TO_RUN_STATE));
 
-  sinfo("Blocking TCB=%p\n", tcb);
+  //sinfo("Blocking TCB=%p\n", tcb);
 
   /* Remove the tcb task from the ready-to-run list.  If we
    * are blocking the task at the head of the task list (the
diff --git a/arch/sim/src/up_initialize.c b/arch/sim/src/up_initialize.c
index 7efcfb23738..cb07619eabd 100644
--- a/arch/sim/src/up_initialize.c
+++ b/arch/sim/src/up_initialize.c
@@ -50,7 +50,7 @@
 #include <nuttx/net/tun.h>
 #include <nuttx/net/telnet.h>
 #include <nuttx/mtd/mtd.h>
-#include <nuttx/syslog/ramlog.h>
+#include <nuttx/syslog/syslog.h>
 #include <nuttx/syslog/syslog_console.h>
 
 #include "up_internal.h"
@@ -162,18 +162,18 @@ void up_initialize(void)
   /* Register a console (or not) */
 
   up_devconsole();          /* Our private /dev/console */
-#elif defined(CONFIG_SYSLOG_CONSOLE)
+#elif defined(CONFIG_CONSOLE_SYSLOG)
   syslog_console_init();
 #elif defined(CONFIG_RAMLOG_CONSOLE)
   ramlog_consoleinit();
 #endif
 
-#ifdef CONFIG_SYSLOG_CHAR
-  syslog_initialize();
-#endif
-#ifdef CONFIG_RAMLOG_SYSLOG
-  ramlog_sysloginit();      /* System logging device */
-#endif
+  /* Early initialization of the system logging device.  Some SYSLOG channel
+   * can be initialized early in the initialization sequence because they
+   * depend on only minimal OS initialization.
+   */
+
+  syslog_initialize(SYSLOG_INIT_EARLY);
 
 #if defined(CONFIG_FS_FAT) && !defined(CONFIG_DISABLE_MOUNTPOINT)
   up_registerblockdevice(); /* Our FAT ramdisk at /dev/ram0 */
diff --git a/arch/sim/src/up_internal.h b/arch/sim/src/up_internal.h
index ddae194a6a1..f163e67a254 100644
--- a/arch/sim/src/up_internal.h
+++ b/arch/sim/src/up_internal.h
@@ -96,13 +96,6 @@
 #  endif
 #endif
 
-/* Determine which device to use as the system logging device */
-
-#ifndef CONFIG_SYSLOG
-#  undef CONFIG_SYSLOG_CHAR
-#  undef CONFIG_RAMLOG_SYSLOG
-#endif
-
 /* The design for how we signal UART data availability is up in the air */
 
 #undef CONFIG_SIM_UART_DATAPOST
diff --git a/arch/sim/src/up_netdriver.c b/arch/sim/src/up_netdriver.c
index 908cff3236c..1e7ef5345cf 100644
--- a/arch/sim/src/up_netdriver.c
+++ b/arch/sim/src/up_netdriver.c
@@ -213,7 +213,7 @@ void netdriver_loop(void)
 #ifdef CONFIG_NET_IPv4
           if (eth->type == HTONS(ETHTYPE_IP) && is_ours)
             {
-              nllinfo("IPv4 frame\n");
+              ninfo("IPv4 frame\n");
 
               /* Handle ARP on input then give the IPv4 packet to the network
                * layer
@@ -254,7 +254,7 @@ void netdriver_loop(void)
 #ifdef CONFIG_NET_IPv6
           if (eth->type == HTONS(ETHTYPE_IP6) && is_ours)
             {
-              nllinfo("Iv6 frame\n");
+              ninfo("Iv6 frame\n");
 
               /* Give the IPv6 packet to the network layer */
 
diff --git a/arch/sim/src/up_schednote.c b/arch/sim/src/up_schednote.c
index 41797969b2c..28e2fd8fbf0 100644
--- a/arch/sim/src/up_schednote.c
+++ b/arch/sim/src/up_schednote.c
@@ -68,19 +68,19 @@ void sched_note_start(FAR struct tcb_s *tcb)
 {
 #ifdef CONFIG_SMP
 #if CONFIG_TASK_NAME_SIZE > 0
-  lowsyslog(LOG_INFO, "CPU%d: Start %s, TCB@%p, state=%d\n",
-            tcb->cpu, tcb->name, tcb, tcb->task_state);
+  syslog(LOG_INFO, "CPU%d: Start %s, TCB@%p, state=%d\n",
+         tcb->cpu, tcb->name, tcb, tcb->task_state);
 #else
-  lowsyslog(LOG_INFO, "CPU%d: Start TCB@%p, state=%d\n"
-            tcb->cpu, tcb, tcb->task_state);
+  syslog(LOG_INFO, "CPU%d: Start TCB@%p, state=%d\n"
+         tcb->cpu, tcb, tcb->task_state);
 #endif
 #else
 #if CONFIG_TASK_NAME_SIZE > 0
-  lowsyslog(LOG_INFO, "Start %s, TCB@%p, state=%d\n",
-            tcb->name, tcb, tcb->task_state);
+  syslog(LOG_INFO, "Start %s, TCB@%p, state=%d\n",
+         tcb->name, tcb, tcb->task_state);
 #else
-  lowsyslog(LOG_INFO, "Start TCB@%p, state=%d\n",
-            tcb, tcb->task_state);
+  syslog(LOG_INFO, "Start TCB@%p, state=%d\n",
+         tcb, tcb->task_state);
 #endif
 #endif
 }
@@ -89,19 +89,19 @@ void sched_note_stop(FAR struct tcb_s *tcb)
 {
 #ifdef CONFIG_SMP
 #if CONFIG_TASK_NAME_SIZE > 0
-  lowsyslog(LOG_INFO, "CPU%d: Stop %s, TCB@%p, state=%d\n",
-            tcb->cpu, tcb->name, tcb, tcb->task_state);
+  syslog(LOG_INFO, "CPU%d: Stop %s, TCB@%p, state=%d\n",
+         tcb->cpu, tcb->name, tcb, tcb->task_state);
 #else
-  lowsyslog(LOG_INFO, "CPU%d: Stop TCB@%p, state=%d\n",
-            tcb->cpu, tcb, tcb->task_state);
+  syslog(LOG_INFO, "CPU%d: Stop TCB@%p, state=%d\n",
+         tcb->cpu, tcb, tcb->task_state);
 #endif
 #else
 #if CONFIG_TASK_NAME_SIZE > 0
-  lowsyslog(LOG_INFO, "Stop %s, TCB@%p, state=%d\n",
-            tcb->name, tcb, tcb->task_state);
+  syslog(LOG_INFO, "Stop %s, TCB@%p, state=%d\n",
+         tcb->name, tcb, tcb->task_state);
 #else
-  lowsyslog(LOG_INFO, "Stop TCB@%p, state=%d\n",
-            tcb, tcb->task_state);
+  syslog(LOG_INFO, "Stop TCB@%p, state=%d\n",
+         tcb, tcb->task_state);
 #endif
 #endif
 }
@@ -110,19 +110,19 @@ void sched_note_suspend(FAR struct tcb_s *tcb)
 {
 #ifdef CONFIG_SMP
 #if CONFIG_TASK_NAME_SIZE > 0
-  lowsyslog(LOG_INFO, "CPU%d: Suspend %s, TCB@%p, state=%d\n",
-            tcb->cpu, tcb->name, tcb, tcb->task_state);
+  syslog(LOG_INFO, "CPU%d: Suspend %s, TCB@%p, state=%d\n",
+         tcb->cpu, tcb->name, tcb, tcb->task_state);
 #else
-  lowsyslog(LOG_INFO, "CPU%d: Suspend TCB@%p, state=%d\n",
-            tcb->cpu, tcb, tcb->task_state);
+  syslog(LOG_INFO, "CPU%d: Suspend TCB@%p, state=%d\n",
+         tcb->cpu, tcb, tcb->task_state);
 #endif
 #else
 #if CONFIG_TASK_NAME_SIZE > 0
-  lowsyslog(LOG_INFO, "Suspend %s, TCB@%p, state=%d\n",
-            tcb->name, tcb, tcb->task_state);
+  syslog(LOG_INFO, "Suspend %s, TCB@%p, state=%d\n",
+         tcb->name, tcb, tcb->task_state);
 #else
-  lowsyslog(LOG_INFO, "Suspend TCB@%p, state=%d\n",
-            tcb, tcb->task_state);
+  syslog(LOG_INFO, "Suspend TCB@%p, state=%d\n",
+         tcb, tcb->task_state);
 #endif
 #endif
 }
@@ -131,19 +131,19 @@ void sched_note_resume(FAR struct tcb_s *tcb)
 {
 #ifdef CONFIG_SMP
 #if CONFIG_TASK_NAME_SIZE > 0
-  lowsyslog(LOG_INFO, "CPU%d: Resume %s, TCB@%p, state=%d\n",
-            tcb->cpu, tcb->name, tcb, tcb->task_state);
+  syslog(LOG_INFO, "CPU%d: Resume %s, TCB@%p, state=%d\n",
+         tcb->cpu, tcb->name, tcb, tcb->task_state);
 #else
-  lowsyslog(LOG_INFO, "CPU%d: Resume TCB@%p, state=%d\n",
-            tcb->cpu, tcb, tcb->task_state);
+  syslog(LOG_INFO, "CPU%d: Resume TCB@%p, state=%d\n",
+         tcb->cpu, tcb, tcb->task_state);
 #endif
 #else
 #if CONFIG_TASK_NAME_SIZE > 0
-  lowsyslog(LOG_INFO, "Resume %s, TCB@%p, state=%d\n",
-            tcb->name, tcb, tcb->task_state);
+  syslog(LOG_INFO, "Resume %s, TCB@%p, state=%d\n",
+         tcb->name, tcb, tcb->task_state);
 #else
-  lowsyslog(LOG_INFO, "Resume TCB@%p, state=%d\n",
-            tcb, tcb->task_state);
+  syslog(LOG_INFO, "Resume TCB@%p, state=%d\n",
+         tcb, tcb->task_state);
 #endif
 #endif
 }
@@ -160,19 +160,19 @@ void sched_note_premption(FAR struct tcb_s *tcb, bool locked)
 {
 #ifdef CONFIG_SMP
 #if CONFIG_TASK_NAME_SIZE > 0
-  lowsyslog(LOG_INFO, "CPU%d: Task %s TCB@%p preemption %s\n",
-            tcb->cpu, tcb->name, tcb, locked ? "LOCKED" : "UNLOCKED");
+  syslog(LOG_INFO, "CPU%d: Task %s TCB@%p preemption %s\n",
+         tcb->cpu, tcb->name, tcb, locked ? "LOCKED" : "UNLOCKED");
 #else
-  lowsyslog(LOG_INFO, "CPU%d: TCB@%p preemption %s\n",
-            tcb->cpu, tcb, locked ? "LOCKED" : "UNLOCKED");
+  syslog(LOG_INFO, "CPU%d: TCB@%p preemption %s\n",
+         tcb->cpu, tcb, locked ? "LOCKED" : "UNLOCKED");
 #endif
 #else
 #if CONFIG_TASK_NAME_SIZE > 0
-  lowsyslog(LOG_INFO, "Task %s, TCB@%p preemption %s\n",
-            tcb->name, tcb, locked ? "LOCKED" : "UNLOCKED");
+  syslog(LOG_INFO, "Task %s, TCB@%p preemption %s\n",
+         tcb->name, tcb, locked ? "LOCKED" : "UNLOCKED");
 #else
-  lowsyslog(LOG_INFO, "TCB@%p preemption %s\n",
-            tcb, locked ? "LOCKED" : "UNLOCKED");
+  syslog(LOG_INFO, "TCB@%p preemption %s\n",
+         tcb, locked ? "LOCKED" : "UNLOCKED");
 #endif
 #endif
 }
@@ -190,19 +190,19 @@ void sched_note_csection(FAR struct tcb_s *tcb, bool enter)
 {
 #ifdef CONFIG_SMP
 #if CONFIG_TASK_NAME_SIZE > 0
-  lowsyslog(LOG_INFO, "CPU%d: Task %s TCB@%p critical section %s\n",
-            tcb->cpu, tcb->name, tcb, enter ? "ENTER" : "LEAVE");
+  syslog(LOG_INFO, "CPU%d: Task %s TCB@%p critical section %s\n",
+         tcb->cpu, tcb->name, tcb, enter ? "ENTER" : "LEAVE");
 #else
-  lowsyslog(LOG_INFO, "CPU%d: TCB@%p critical section %s\n",
-            tcb->cpu, tcb, enter ? "ENTER" : "LEAVE");
+  syslog(LOG_INFO, "CPU%d: TCB@%p critical section %s\n",
+         tcb->cpu, tcb, enter ? "ENTER" : "LEAVE");
 #endif
 #else
 #if CONFIG_TASK_NAME_SIZE > 0
-  lowsyslog(LOG_INFO, "Task %s, TCB@%p critical section %s\n",
-            tcb->name, tcb, enter ? "ENTER" : "LEAVE");
+  syslog(LOG_INFO, "Task %s, TCB@%p critical section %s\n",
+         tcb->name, tcb, enter ? "ENTER" : "LEAVE");
 #else
-  lowsyslog(LOG_INFO, "TCB@%p critical section %s\n",
-            tcb, enter ? "ENTER" : "LEAVE");
+  syslog(LOG_INFO, "TCB@%p critical section %s\n",
+         tcb, enter ? "ENTER" : "LEAVE");
 #endif
 #endif
 }
diff --git a/arch/x86/src/common/up_assert.c b/arch/x86/src/common/up_assert.c
index 3b6caececce..7afec4e4bec 100644
--- a/arch/x86/src/common/up_assert.c
+++ b/arch/x86/src/common/up_assert.c
@@ -103,7 +103,7 @@ static int usbtrace_syslog(FAR const char *fmt, ...)
   /* Let vsyslog do the real work */
 
   va_start(ap, fmt);
-  ret = lowvsyslog(LOG_INFO, fmt, ap);
+  ret = vsyslog(LOG_EMERG, fmt, ap);
   va_end(ap);
   return ret;
 }
@@ -256,7 +256,7 @@ static void _up_assert(int errorcode)
 
 void up_assert(const uint8_t *filename, int lineno)
 {
-#if CONFIG_TASK_NAME_SIZE > 0
+#if CONFIG_TASK_NAME_SIZE > 0 && defined(CONFIG_DEBUG_ALERT)
   struct tcb_s *rtcb = this_task();
 #endif
 
diff --git a/arch/x86/src/common/up_exit.c b/arch/x86/src/common/up_exit.c
index 7e96c48e882..5ebeba07c3b 100644
--- a/arch/x86/src/common/up_exit.c
+++ b/arch/x86/src/common/up_exit.c
@@ -56,9 +56,9 @@
  * Pre-processor Definitions
  ****************************************************************************/
 
-/****************************************************************************
- * Private Data
- ****************************************************************************/
+#ifndef CONFIG_DEBUG_SCHED_INFO
+#  undef CONFIG_DUMP_ON_EXIT
+#endif
 
 /****************************************************************************
  * Private Functions
@@ -74,7 +74,7 @@
  *
  ****************************************************************************/
 
-#if defined(CONFIG_DUMP_ON_EXIT) && defined(CONFIG_DEBUG_FEATURES)
+#ifdef CONFIG_DUMP_ON_EXIT
 static void _up_dumponexit(FAR struct tcb_s *tcb, FAR void *arg)
 {
 #if CONFIG_NFILE_DESCRIPTORS > 0
@@ -146,10 +146,10 @@ void _exit(int status)
 
   (void)up_irq_save();
 
-  sllinfo("TCB=%p exiting\n", this_task());
+  sinfo("TCB=%p exiting\n", this_task());
 
-#if defined(CONFIG_DUMP_ON_EXIT) && defined(CONFIG_DEBUG_FEATURES)
-  sllinfo("Other tasks:\n");
+#ifdef CONFIG_DUMP_ON_EXIT
+  sinfo("Other tasks:\n");
   sched_foreach(_up_dumponexit, NULL);
 #endif
 
diff --git a/arch/x86/src/common/up_initialize.c b/arch/x86/src/common/up_initialize.c
index 15197e93a5f..853304038bd 100644
--- a/arch/x86/src/common/up_initialize.c
+++ b/arch/x86/src/common/up_initialize.c
@@ -49,7 +49,7 @@
 #include <nuttx/net/loopback.h>
 #include <nuttx/net/tun.h>
 #include <nuttx/net/telnet.h>
-#include <nuttx/syslog/ramlog.h>
+#include <nuttx/syslog/syslog.h>
 #include <nuttx/syslog/syslog_console.h>
 
 #include <arch/board/board.h>
@@ -76,13 +76,13 @@ static void up_calibratedelay(void)
 {
   int i;
 
-  _llwarn("Beginning 100s delay\n");
+  _warn("Beginning 100s delay\n");
   for (i = 0; i < 100; i++)
     {
       up_mdelay(1000);
     }
 
-  _llwarn("End 100s delay\n");
+  _warn("End 100s delay\n");
 }
 #else
 # define up_calibratedelay()
@@ -180,20 +180,18 @@ void up_initialize(void)
 
 #if defined(CONFIG_DEV_LOWCONSOLE)
   lowconsole_init();
-#elif defined(CONFIG_SYSLOG_CONSOLE)
+#elif defined(CONFIG_CONSOLE_SYSLOG)
   syslog_console_init();
 #elif defined(CONFIG_RAMLOG_CONSOLE)
   ramlog_consoleinit();
 #endif
 
-  /* Initialize the system logging device */
+  /* Early initialization of the system logging device.  Some SYSLOG channel
+   * can be initialized early in the initialization sequence because they
+   * depend on only minimal OS initialization.
+   */
 
-#ifdef CONFIG_SYSLOG_CHAR
-  syslog_initialize();
-#endif
-#ifdef CONFIG_RAMLOG_SYSLOG
-  ramlog_sysloginit();
-#endif
+  syslog_initialize(SYSLOG_INIT_EARLY);
 
 #ifndef CONFIG_NETDEV_LATEINIT
   /* Initialize the network */
diff --git a/arch/x86/src/common/up_internal.h b/arch/x86/src/common/up_internal.h
index d0eb1570c36..810bece03a4 100644
--- a/arch/x86/src/common/up_internal.h
+++ b/arch/x86/src/common/up_internal.h
@@ -62,6 +62,10 @@
 #undef  CONFIG_SUPPRESS_UART_CONFIG   /* DEFINED: Do not reconfig UART */
 #undef  CONFIG_DUMP_ON_EXIT           /* DEFINED: Dump task state on exit */
 
+#ifndef CONFIG_DEBUG_SCHED_INFO
+#  undef CONFIG_DUMP_ON_EXIT          /* Needs CONFIG_DEBUG_SCHED_INFO */
+#endif
+
 /* Determine which (if any) console driver to use.  If a console is enabled
  * and no other console device is specified, then a serial console is
  * assumed.
@@ -96,13 +100,6 @@
 #  define USE_SERIALDRIVER 1
 #endif
 
-/* Determine which device to use as the system logging device */
-
-#ifndef CONFIG_SYSLOG
-#  undef CONFIG_SYSLOG_CHAR
-#  undef CONFIG_RAMLOG_SYSLOG
-#endif
-
 /* Check if an interrupt stack size is configured */
 
 #ifndef CONFIG_ARCH_INTERRUPTSTACK
diff --git a/arch/x86/src/common/up_releasepending.c b/arch/x86/src/common/up_releasepending.c
index 9271d8e4042..b0e8890db3a 100644
--- a/arch/x86/src/common/up_releasepending.c
+++ b/arch/x86/src/common/up_releasepending.c
@@ -67,7 +67,7 @@ void up_release_pending(void)
 {
   struct tcb_s *rtcb = this_task();
 
-  sllinfo("From TCB=%p\n", rtcb);
+  sinfo("From TCB=%p\n", rtcb);
 
   /* Merge the g_pendingtasks list into the ready-to-run task list */
 
diff --git a/arch/x86/src/common/up_reprioritizertr.c b/arch/x86/src/common/up_reprioritizertr.c
index e78cdf04bd7..110d26a6717 100644
--- a/arch/x86/src/common/up_reprioritizertr.c
+++ b/arch/x86/src/common/up_reprioritizertr.c
@@ -95,7 +95,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority)
       struct tcb_s *rtcb = this_task();
       bool switch_needed;
 
-      sllinfo("TCB=%p PRI=%d\n", tcb, priority);
+      sinfo("TCB=%p PRI=%d\n", tcb, priority);
 
       /* Remove the tcb task from the ready-to-run list.
        * sched_removereadytorun will return true if we just
diff --git a/arch/z16/src/common/up_assert.c b/arch/z16/src/common/up_assert.c
index 628c34f1faa..5346e9d48c9 100644
--- a/arch/z16/src/common/up_assert.c
+++ b/arch/z16/src/common/up_assert.c
@@ -109,7 +109,7 @@ static int usbtrace_syslog(FAR const char *fmt, ...)
   /* Let vsyslog do the real work */
 
   va_start(ap, fmt);
-  ret = lowvsyslog(LOG_INFO, fmt, ap);
+  ret = vsyslog(LOG_EMERG, fmt, ap);
   va_end(ap);
   return ret;
 }
@@ -135,7 +135,7 @@ void up_assert(const uint8_t *filename, int lineno)
 void up_assert(void)
 #endif
 {
-#if CONFIG_TASK_NAME_SIZE > 0
+#if CONFIG_TASK_NAME_SIZE > 0 && defined(CONFIG_DEBUG_ALERT)
   struct tcb_s *rtcb = this_task();
 #endif
 
@@ -150,7 +150,7 @@ void up_assert(void)
         filename, lineno);
 #endif
 #else
-#if CONFIG_TASK_NAME_SIZE > 0
+#if CONFIG_TASK_NAME_SIZE > 0 && defined(CONFIG_DEBUG_ALERT)
   _alert("Assertion failed: task: %s\n", rtcb->name);
 #else
   _alert("Assertion failed\n");
diff --git a/arch/z16/src/common/up_exit.c b/arch/z16/src/common/up_exit.c
index df4d62c3818..a47e042b38c 100644
--- a/arch/z16/src/common/up_exit.c
+++ b/arch/z16/src/common/up_exit.c
@@ -53,6 +53,14 @@
 #include "sched/sched.h"
 #include "up_internal.h"
 
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#ifndef CONFIG_DEBUG_SCHED_INFO
+#  undef CONFIG_DUMP_ON_EXIT
+#endif
+
 /****************************************************************************
  * Private Functions
  ****************************************************************************/
@@ -67,7 +75,7 @@
  *
  ****************************************************************************/
 
-#if defined(CONFIG_DUMP_ON_EXIT) && defined(CONFIG_DEBUG_FEATURES)
+#ifdef CONFIG_DUMP_ON_EXIT
 static void _up_dumponexit(FAR struct tcb_s *tcb, FAR void *arg)
 {
 #if CONFIG_NFILE_DESCRIPTORS > 0
@@ -78,8 +86,8 @@ static void _up_dumponexit(FAR struct tcb_s *tcb, FAR void *arg)
   int i;
 #endif
 
-  sllinfo("  TCB=%p name=%s\n", tcb, tcb->argv[0]);
-  sllinfo("    priority=%d state=%d\n", tcb->sched_priority, tcb->task_state);
+  sinfo("  TCB=%p name=%s\n", tcb, tcb->argv[0]);
+  sinfo("    priority=%d state=%d\n", tcb->sched_priority, tcb->task_state);
 
 #if CONFIG_NFILE_DESCRIPTORS > 0
   filelist = tcb->group->tg_filelist;
@@ -88,8 +96,8 @@ static void _up_dumponexit(FAR struct tcb_s *tcb, FAR void *arg)
       struct inode *inode = filelist->fl_files[i].f_inode;
       if (inode)
         {
-          sllinfo("      fd=%d refcount=%d\n",
-                  i, inode->i_crefs);
+          sinfo("      fd=%d refcount=%d\n",
+                i, inode->i_crefs);
         }
     }
 #endif
@@ -102,11 +110,11 @@ static void _up_dumponexit(FAR struct tcb_s *tcb, FAR void *arg)
       if (filep->fs_fd >= 0)
         {
 #if CONFIG_STDIO_BUFFER_SIZE > 0
-          sllinfo("      fd=%d nbytes=%d\n",
-                  filep->fs_fd,
-                  filep->fs_bufpos - filep->fs_bufstart);
+          sinfo("      fd=%d nbytes=%d\n",
+                filep->fs_fd,
+                filep->fs_bufpos - filep->fs_bufstart);
 #else
-          sllinfo("      fd=%d\n", filep->fs_fd);
+          sinfo("      fd=%d\n", filep->fs_fd);
 #endif
         }
     }
@@ -139,10 +147,10 @@ void _exit(int status)
 
   (void)up_irq_save();
 
-  sllinfo("TCB=%p exiting\n", tcb);
+  sinfo("TCB=%p exiting\n", tcb);
 
-#if defined(CONFIG_DUMP_ON_EXIT) && defined(CONFIG_DEBUG_FEATURES)
-  sllinfo("Other tasks:\n");
+#ifdef CONFIG_DUMP_ON_EXIT
+  sinfo("Other tasks:\n");
   sched_foreach(_up_dumponexit, NULL);
 #endif
 
@@ -155,7 +163,7 @@ void _exit(int status)
    */
 
   tcb = this_task();
-  sllinfo("New Active Task TCB=%p\n", tcb);
+  sinfo("New Active Task TCB=%p\n", tcb);
 
   /* Then switch contexts */
 
diff --git a/arch/z16/src/common/up_initialize.c b/arch/z16/src/common/up_initialize.c
index 853ae0ce7a8..f6a020203aa 100644
--- a/arch/z16/src/common/up_initialize.c
+++ b/arch/z16/src/common/up_initialize.c
@@ -49,7 +49,7 @@
 #include <nuttx/net/loopback.h>
 #include <nuttx/net/tun.h>
 #include <nuttx/net/telnet.h>
-#include <nuttx/syslog/ramlog.h>
+#include <nuttx/syslog/syslog.h>
 #include <nuttx/syslog/syslog_console.h>
 
 #include <arch/board/board.h>
@@ -87,13 +87,13 @@ static void up_calibratedelay(void)
 {
   int i;
 
-  _llwarn("Beginning 100s delay\n");
+  _warn("Beginning 100s delay\n");
   for (i = 0; i < 100; i++)
     {
       up_mdelay(1000);
     }
 
-  _llwarn("End 100s delay\n");
+  _warn("End 100s delay\n");
 }
 #else
 # define up_calibratedelay()
@@ -180,20 +180,18 @@ void up_initialize(void)
 
 #if defined(CONFIG_DEV_LOWCONSOLE)
   lowconsole_init();
-#elif defined(CONFIG_SYSLOG_CONSOLE)
+#elif defined(CONFIG_CONSOLE_SYSLOG)
   syslog_console_init();
 #elif defined(CONFIG_RAMLOG_CONSOLE)
   ramlog_consoleinit();
 #endif
 
-  /* Initialize the system logging device */
+  /* Early initialization of the system logging device.  Some SYSLOG channel
+   * can be initialized early in the initialization sequence because they
+   * depend on only minimal OS initialization.
+   */
 
-#ifdef CONFIG_SYSLOG_CHAR
-  syslog_initialize();
-#endif
-#ifdef CONFIG_RAMLOG_SYSLOG
-  ramlog_sysloginit();
-#endif
+  syslog_initialize(SYSLOG_INIT_EARLY);
 
 #ifndef CONFIG_NETDEV_LATEINIT
   /* Initialize the network */
diff --git a/arch/z16/src/common/up_internal.h b/arch/z16/src/common/up_internal.h
index 64a5302a420..c959bb09562 100644
--- a/arch/z16/src/common/up_internal.h
+++ b/arch/z16/src/common/up_internal.h
@@ -60,6 +60,10 @@
 #undef  CONFIG_Z16_LOWPUTC            /* Support up_lowputc for debug */
 #undef  CONFIG_Z16_LOWGETC            /* support z16_lowgetc for debug */
 
+#ifndef CONFIG_DEBUG_SCHED_INFO
+#  undef CONFIG_DUMP_ON_EXIT          /* Needs CONFIG_DEBUG_SCHED_INFO */
+#endif
+
 /* Determine which (if any) console driver to use.  If a console is enabled
  * and no other console device is specified, then a serial console is
  * assumed.
@@ -98,13 +102,6 @@
 #  define USE_SERIALDRIVER 1
 #endif
 
-/* Determine which device to use as the system logging device */
-
-#ifndef CONFIG_SYSLOG
-#  undef CONFIG_SYSLOG_CHAR
-#  undef CONFIG_RAMLOG_SYSLOG
-#endif
-
 /* Macros for portability */
 
 #define IN_INTERRUPT             (g_current_regs != NULL)
diff --git a/arch/z16/src/common/up_releasepending.c b/arch/z16/src/common/up_releasepending.c
index ff6d24f4fb0..ddac88d6c4c 100644
--- a/arch/z16/src/common/up_releasepending.c
+++ b/arch/z16/src/common/up_releasepending.c
@@ -68,7 +68,7 @@ void up_release_pending(void)
 {
   FAR struct tcb_s *rtcb = this_task();
 
-  sllinfo("From TCB=%p\n", rtcb);
+  sinfo("From TCB=%p\n", rtcb);
 
   /* Merge the g_pendingtasks list into the ready-to-run task list */
 
diff --git a/arch/z16/src/common/up_reprioritizertr.c b/arch/z16/src/common/up_reprioritizertr.c
index 8af6cc003b9..4724fc2f294 100644
--- a/arch/z16/src/common/up_reprioritizertr.c
+++ b/arch/z16/src/common/up_reprioritizertr.c
@@ -96,7 +96,7 @@ void up_reprioritize_rtr(FAR struct tcb_s *tcb, uint8_t priority)
       FAR struct tcb_s *rtcb = this_task();
       bool switch_needed;
 
-      sllinfo("TCB=%p PRI=%d\n", tcb, priority);
+      sinfo("TCB=%p PRI=%d\n", tcb, priority);
 
       /* Remove the tcb task from the ready-to-run list.
        * sched_removereadytorun will return true if we just
diff --git a/arch/z16/src/common/up_stackdump.c b/arch/z16/src/common/up_stackdump.c
index 0abb3a33aea..3dc17151dd1 100644
--- a/arch/z16/src/common/up_stackdump.c
+++ b/arch/z16/src/common/up_stackdump.c
@@ -73,7 +73,7 @@ static void up_stackdump(void)
 
   if (sp >= stack_base || sp < stack_base - stack_size)
     {
-      _llerr("ERROR: Stack pointer is not within allocated stack\n");
+      _err("ERROR: Stack pointer is not within allocated stack\n");
       return;
     }
   else
diff --git a/arch/z16/src/z16f/z16f_sysexec.c b/arch/z16/src/z16f/z16f_sysexec.c
index d7ac6317513..7c3eafa0ab6 100644
--- a/arch/z16/src/z16f/z16f_sysexec.c
+++ b/arch/z16/src/z16f/z16f_sysexec.c
@@ -88,42 +88,42 @@ void z16f_sysexec(FAR chipreg_t *regs)
   excp = getreg16(Z16F_SYSEXCP);
   if ((excp & Z16F_SYSEXCP_SPOVF) != 0)
     {
-      lowsyslog(LOG_ERR, "SP OVERFLOW\n");
+      err("ERROR: SP OVERFLOW\n");
     }
 
   if ((excp & Z16F_SYSEXCP_PCOVF) != 0)
     {
-      lowsyslog(LOG_ERR, "PC OVERFLOW\n");
+      err("ERROR: PC OVERFLOW\n");
     }
 
   if ((excp & Z16F_SYSEXCP_DIV0) != 0)
     {
-      lowsyslog(LOG_ERR, "Divide by zero\n");
+      err("ERROR: Divide by zero\n");
     }
 
   if ((excp & Z16F_SYSEXCP_DIVOVF) != 0)
     {
-      lowsyslog(LOG_ERR, "Divide overflow\n");
+      err("ERROR: Divide overflow\n");
     }
 
   if ((excp & Z16F_SYSEXCP_ILL) != 0)
     {
-      lowsyslog(LOG_ERR, "Illegal instruction\n");
+      err("ERROR: Illegal instruction\n");
     }
 
   if ((excp & Z16F_SYSEXCP_WDTOSC) != 0)
     {
-      lowsyslog(LOG_ERR, "WDT oscillator failure\n");
+      err("ERROR: WDT oscillator failure\n");
     }
 
   if ((excp & Z16F_SYSEXCP_PRIOSC) != 0)
     {
-      lowsyslog(LOG_ERR, "Primary Oscillator Failure\n");
+      err("ERROR: Primary Oscillator Failure\n");
     }
 
   if ((excp & Z16F_SYSEXCP_WDT) != 0)
     {
-      lowsyslog(LOG_ERR, "Watchdog timeout\n");
+      err("ERROR: Watchdog timeout\n");
       z16f_reset();
     }
 
diff --git a/arch/z80/src/common/up_assert.c b/arch/z80/src/common/up_assert.c
index 49b72409289..da899feb6f4 100644
--- a/arch/z80/src/common/up_assert.c
+++ b/arch/z80/src/common/up_assert.c
@@ -108,7 +108,7 @@ static int usbtrace_syslog(FAR const char *fmt, ...)
   /* Let vsyslog do the real work */
 
   va_start(ap, fmt);
-  ret = lowvsyslog(LOG_INFO, fmt, ap);
+  ret = vsyslog(LOG_EMERG, fmt, ap);
   va_end(ap);
   return ret;
 }
@@ -134,7 +134,7 @@ void up_assert(const uint8_t *filename, int lineno)
 void up_assert(void)
 #endif
 {
-#if CONFIG_TASK_NAME_SIZE > 0
+#if CONFIG_TASK_NAME_SIZE > 0 && defined(CONFIG_DEBUG_ALERT)
   struct tcb_s *rtcb = this_task();
 #endif
 
diff --git a/arch/z80/src/common/up_doirq.c b/arch/z80/src/common/up_doirq.c
index 30e2caf9fd1..878594a126c 100644
--- a/arch/z80/src/common/up_doirq.c
+++ b/arch/z80/src/common/up_doirq.c
@@ -78,8 +78,8 @@ FAR chipreg_t *up_doirq(uint8_t irq, FAR chipreg_t *regs)
 
 #ifdef CONFIG_SUPPRESS_INTERRUPTS
 
-  lowsyslog(LOG_ERR, "Unexpected IRQ\n");
   IRQ_ENTER(regs);
+  err("ERROR: Unexpected IRQ\n");
   PANIC();
   return NULL; /* Won't get here */
 
diff --git a/arch/z80/src/common/up_exit.c b/arch/z80/src/common/up_exit.c
index a5e98321334..29860f7d296 100644
--- a/arch/z80/src/common/up_exit.c
+++ b/arch/z80/src/common/up_exit.c
@@ -59,9 +59,9 @@
  * Pre-processor Definitions
  ****************************************************************************/
 
-/****************************************************************************
- * Private Data
- ****************************************************************************/
+#ifndef CONFIG_DEBUG_SCHED_INFO
+#  undef CONFIG_DUMP_ON_EXIT
+#endif
 
 /****************************************************************************
  * Private Functions
@@ -77,7 +77,7 @@
  *
  ****************************************************************************/
 
-#if defined(CONFIG_DUMP_ON_EXIT) && defined(CONFIG_DEBUG_FEATURES)
+#ifdef CONFIG_DUMP_ON_EXIT
 static void _up_dumponexit(FAR struct tcb_s *tcb, FAR void *arg)
 {
 #if CONFIG_NFILE_DESCRIPTORS > 0
@@ -88,8 +88,8 @@ static void _up_dumponexit(FAR struct tcb_s *tcb, FAR void *arg)
   int i;
 #endif
 
-  _llinfo("  TCB=%p name=%s\n", tcb, tcb->argv[0]);
-  _llinfo("    priority=%d state=%d\n", tcb->sched_priority, tcb->task_state);
+  sinfo("  TCB=%p name=%s\n", tcb, tcb->argv[0]);
+  sinfo("    priority=%d state=%d\n", tcb->sched_priority, tcb->task_state);
 
 #if CONFIG_NFILE_DESCRIPTORS > 0
   filelist = tcb->group->tg_filelist;
@@ -98,8 +98,8 @@ static void _up_dumponexit(FAR struct tcb_s *tcb, FAR void *arg)
       struct inode *inode = filelist->fl_files[i].f_inode;
       if (inode)
         {
-          _llinfo("      fd=%d refcount=%d\n",
-                 i, inode->i_crefs);
+          sinfo("      fd=%d refcount=%d\n",
+                i, inode->i_crefs);
         }
     }
 #endif
@@ -112,11 +112,11 @@ static void _up_dumponexit(FAR struct tcb_s *tcb, FAR void *arg)
       if (filep->fs_fd >= 0)
         {
 #if CONFIG_STDIO_BUFFER_SIZE > 0
-          _llinfo("      fd=%d nbytes=%d\n",
-                 filep->fs_fd,
-                 filep->fs_bufpos - filep->fs_bufstart);
+          sinfo("      fd=%d nbytes=%d\n",
+                filep->fs_fd,
+                filep->fs_bufpos - filep->fs_bufstart);
 #else
-          _llinfo("      fd=%d\n", filep->fs_fd);
+          sinfo("      fd=%d\n", filep->fs_fd);
 #endif
         }
     }
@@ -149,10 +149,10 @@ void _exit(int status)
 
   (void)up_irq_save();
 
-  sllinfo("TCB=%p exiting\n", tcb);
+  sinfo("TCB=%p exiting\n", tcb);
 
-#if defined(CONFIG_DUMP_ON_EXIT) && defined(CONFIG_DEBUG_FEATURES)
-  _llinfo("Other tasks:\n");
+#ifdef CONFIG_DUMP_ON_EXIT
+  sinfo("Other tasks:\n");
   sched_foreach(_up_dumponexit, NULL);
 #endif
 
@@ -165,7 +165,7 @@ void _exit(int status)
    */
 
   tcb = this_task();
-  sllinfo("New Active Task TCB=%p\n", tcb);
+  sinfo("New Active Task TCB=%p\n", tcb);
 
 #ifdef CONFIG_ARCH_ADDRENV
   /* Make sure that the address environment for the previously running
diff --git a/arch/z80/src/common/up_initialize.c b/arch/z80/src/common/up_initialize.c
index b773d958925..9684998ff36 100644
--- a/arch/z80/src/common/up_initialize.c
+++ b/arch/z80/src/common/up_initialize.c
@@ -48,7 +48,8 @@
 #include <nuttx/fs/loop.h>
 #include <nuttx/net/loopback.h>
 #include <nuttx/net/tun.h>
-#include <nuttx/net/telnet.h>
+#include <nuttx/syslog/syslog.h>
+#include <nuttx/syslog/syslog_console.h>
 
 #include <arch/board/board.h>
 
@@ -75,13 +76,13 @@ static void up_calibratedelay(void)
 {
   int i;
 
-  _llwarn("Beginning 100s delay\n");
+  _warn("Beginning 100s delay\n");
   for (i = 0; i < 100; i++)
     {
       up_mdelay(1000);
     }
 
-  _llwarn("End 100s delay\n");
+  _warn("End 100s delay\n");
 }
 #else
 # define up_calibratedelay()
@@ -176,12 +177,19 @@ void up_initialize(void)
 
 #if defined(CONFIG_DEV_LOWCONSOLE)
   lowconsole_init();
-#elif defined(CONFIG_SYSLOG_CONSOLE)
+#elif defined(CONFIG_CONSOLE_SYSLOG)
   syslog_console_init();
 #elif defined(CONFIG_RAMLOG_CONSOLE)
   ramlog_consoleinit();
 #endif
 
+  /* Early initialization of the system logging device.  Some SYSLOG channel
+   * can be initialized early in the initialization sequence because they
+   * depend on minimal OS initialization.
+   */
+
+  syslog_initialize(SYSLOG_INIT_EARLY);
+
 #ifndef CONFIG_NETDEV_LATEINIT
   /* Initialize the network */
 
diff --git a/arch/z80/src/common/up_internal.h b/arch/z80/src/common/up_internal.h
index 76deaa34b7b..2f1436967de 100644
--- a/arch/z80/src/common/up_internal.h
+++ b/arch/z80/src/common/up_internal.h
@@ -51,6 +51,10 @@
 #undef  CONFIG_SUPPRESS_UART_CONFIG   /* Do not reconfig UART */
 #undef  CONFIG_DUMP_ON_EXIT           /* Dump task state on exit */
 
+#ifndef CONFIG_DEBUG_SCHED_INFO
+#  undef CONFIG_DUMP_ON_EXIT          /* Needs CONFIG_DEBUG_SCHED_INFO */
+#endif
+
 /****************************************************************************
  * Included Files
  ****************************************************************************/
@@ -88,7 +92,7 @@
 #  if defined(CONFIG_RAMLOG_CONSOLE)
 #    undef  USE_SERIALDRIVER
 #    undef  CONFIG_DEV_LOWCONSOLE
-#  elif defined(CONFIG_SYSLOG_CONSOLE)
+#  elif defined(CONFIG_CONSOLE_SYSLOG)
 #    undef  USE_SERIALDRIVER
 #    undef  CONFIG_DEV_LOWCONSOLE
 #  elif defined(CONFIG_DEV_LOWCONSOLE)
@@ -173,7 +177,7 @@ void lowconsole_init(void);
 
 /* Defined in drivers/syslog_console.c */
 
-#ifdef CONFIG_SYSLOG_CONSOLE
+#ifdef CONFIG_CONSOLE_SYSLOG
 void syslog_console_init();
 #else
 # define syslog_console_init()
diff --git a/arch/z80/src/common/up_releasepending.c b/arch/z80/src/common/up_releasepending.c
index bf824018ccf..3a3974863f7 100644
--- a/arch/z80/src/common/up_releasepending.c
+++ b/arch/z80/src/common/up_releasepending.c
@@ -70,7 +70,7 @@ void up_release_pending(void)
 {
   FAR struct tcb_s *rtcb = this_task();
 
-  sllinfo("From TCB=%p\n", rtcb);
+  sinfo("From TCB=%p\n", rtcb);
 
   /* Merge the g_pendingtasks list into the ready-to-run task list */
 
diff --git a/arch/z80/src/common/up_reprioritizertr.c b/arch/z80/src/common/up_reprioritizertr.c
index 4e3a74157dc..12c4bcef99c 100644
--- a/arch/z80/src/common/up_reprioritizertr.c
+++ b/arch/z80/src/common/up_reprioritizertr.c
@@ -98,7 +98,7 @@ void up_reprioritize_rtr(FAR struct tcb_s *tcb, uint8_t priority)
       FAR struct tcb_s *rtcb = this_task();
       bool switch_needed;
 
-      sllinfo("TCB=%p PRI=%d\n", tcb, priority);
+      sinfo("TCB=%p PRI=%d\n", tcb, priority);
 
       /* Remove the tcb task from the ready-to-run list.
        * sched_removereadytorun will return true if we just
diff --git a/arch/z80/src/ez80/ez80_emac.c b/arch/z80/src/ez80/ez80_emac.c
index 0080cb388d4..640c1d3fc21 100644
--- a/arch/z80/src/ez80/ez80_emac.c
+++ b/arch/z80/src/ez80/ez80_emac.c
@@ -960,9 +960,9 @@ static int ez80emac_transmit(struct ez80emac_driver_s *priv)
    * handler and, therefore, may be suspended when debug output is generated!
    */
 
-  nllinfo("txnext=%p {%06x, %u, %04x} trp=%02x%02x\n",
-          priv->txnext, priv->txnext->np, priv->txnext->pktsize, priv->txnext->stat,
-          inp(EZ80_EMAC_TRP_H), inp(EZ80_EMAC_TRP_L));
+  ninfo("txnext=%p {%06x, %u, %04x} trp=%02x%02x\n",
+        priv->txnext, priv->txnext->np, priv->txnext->pktsize, priv->txnext->stat,
+        inp(EZ80_EMAC_TRP_H), inp(EZ80_EMAC_TRP_L));
 
   /* Increment statistics */
 
@@ -1039,11 +1039,11 @@ static int ez80emac_transmit(struct ez80emac_driver_s *priv)
   outp(EZ80_EMAC_PTMR, EMAC_PTMR);
   leave_critical_section(flags);
 
-  nllinfo("txdesc=%p {%06x, %u, %04x}\n",
-          txdesc, txdesc->np, txdesc->pktsize, txdesc->stat);
-  nllinfo("txnext=%p {%06x, %u, %04x} trp=%02x%02x\n",
-          txnext, txnext->np, txnext->pktsize, txnext->stat,
-          inp(EZ80_EMAC_TRP_H), inp(EZ80_EMAC_TRP_L));
+  ninfo("txdesc=%p {%06x, %u, %04x}\n",
+        txdesc, txdesc->np, txdesc->pktsize, txdesc->stat);
+  ninfo("txnext=%p {%06x, %u, %04x} trp=%02x%02x\n",
+        txnext, txnext->np, txnext->pktsize, txnext->stat,
+        inp(EZ80_EMAC_TRP_H), inp(EZ80_EMAC_TRP_L));
 
   /* Setup the TX timeout watchdog (perhaps restarting the timer) */
 
@@ -1304,7 +1304,7 @@ static int ez80emac_receive(struct ez80emac_driver_s *priv)
 #ifdef CONFIG_NET_IPv4
       if (ETHBUF->type == HTONS(ETHTYPE_IP))
         {
-          nllinfo("IPv4 frame\n");
+          ninfo("IPv4 frame\n");
 
           /* Handle ARP on input then give the IPv4 packet to the network
            * layer
@@ -1345,7 +1345,7 @@ static int ez80emac_receive(struct ez80emac_driver_s *priv)
 #ifdef CONFIG_NET_IPv6
       if (ETHBUF->type == HTONS(ETHTYPE_IP6))
         {
-          nllinfo("Iv6 frame\n");
+          ninfo("Iv6 frame\n");
 
           /* Give the IPv6 packet to the network layer */
 
@@ -2200,7 +2200,7 @@ int up_netinitialize(void)
   ret = irq_attach(EZ80_EMACSYS_IRQ, ez80emac_sysinterrupt);
   if (ret < 0)
     {
-      nllerr("ERROR: Unable to attach IRQ %d\n", EZ80_EMACSYS_IRQ);
+      nerr("ERROR: Unable to attach IRQ %d\n", EZ80_EMACSYS_IRQ);
       ret = -EAGAIN;
       goto errout;
     }
@@ -2208,7 +2208,7 @@ int up_netinitialize(void)
   ret = irq_attach(EZ80_EMACRX_IRQ, ez80emac_rxinterrupt);
   if (ret < 0)
     {
-      nllerr("ERROR: Unable to attach IRQ %d\n", EZ80_EMACRX_IRQ);
+      nerr("ERROR: Unable to attach IRQ %d\n", EZ80_EMACRX_IRQ);
       ret = -EAGAIN;
       goto errout;
     }
@@ -2216,7 +2216,7 @@ int up_netinitialize(void)
   ret = irq_attach(EZ80_EMACTX_IRQ, ez80emac_txinterrupt);
   if (ret < 0)
     {
-      nllerr("ERROR: Unable to attach IRQ %d\n", EZ80_EMACTX_IRQ);
+      nerr("ERROR: Unable to attach IRQ %d\n", EZ80_EMACTX_IRQ);
       ret = -EAGAIN;
       goto errout;
     }
diff --git a/audio/audio.c b/audio/audio.c
index 184ef74a6f7..b8194908ab9 100644
--- a/audio/audio.c
+++ b/audio/audio.c
@@ -704,7 +704,7 @@ static inline void audio_dequeuebuffer(FAR struct audio_upperhalf_s *upper,
 {
   struct audio_msg_s    msg;
 
-  audllinfo("Entry\n");
+  audinfo("Entry\n");
 
   /* Send a dequeue message to the user if a message queue is registered */
 
@@ -742,7 +742,7 @@ static inline void audio_complete(FAR struct audio_upperhalf_s *upper,
 {
   struct audio_msg_s    msg;
 
-  audllinfo("Entry\n");
+  audinfo("Entry\n");
 
   /* Send a dequeue message to the user if a message queue is registered */
 
@@ -791,7 +791,7 @@ static void audio_callback(FAR void *handle, uint16_t reason,
 {
   FAR struct audio_upperhalf_s *upper = (FAR struct audio_upperhalf_s *)handle;
 
-  audllinfo("Entry\n");
+  audinfo("Entry\n");
 
   /* Perform operation based on reason code */
 
diff --git a/binfmt/binfmt_schedunload.c b/binfmt/binfmt_schedunload.c
index 1347262ff49..5121e975eac 100644
--- a/binfmt/binfmt_schedunload.c
+++ b/binfmt/binfmt_schedunload.c
@@ -209,7 +209,7 @@ static void unload_callback(int signo, siginfo_t *info, void *ucontext)
 
   if (!info || signo != SIGCHLD)
     {
-      bllerr("ERROR:Bad signal callback: signo=%d info=%p\n", signo, info);
+      berr("ERROR:Bad signal callback: signo=%d info=%p\n", signo, info);
       return;
     }
 
@@ -218,7 +218,7 @@ static void unload_callback(int signo, siginfo_t *info, void *ucontext)
   bin = unload_list_remove(info->si_pid);
   if (!bin)
     {
-      bllerr("ERROR: Could not find load info for PID=%d\n", info->si_pid);
+      berr("ERROR: Could not find load info for PID=%d\n", info->si_pid);
       return;
     }
 
@@ -227,7 +227,7 @@ static void unload_callback(int signo, siginfo_t *info, void *ucontext)
   ret = unload_module(bin);
   if (ret < 0)
     {
-      bllerr("ERROR: unload_module failed: %d\n", get_errno());
+      berr("ERROR: unload_module failed: %d\n", get_errno());
     }
 
   /* Free the load structure */
@@ -284,7 +284,7 @@ int schedule_unload(pid_t pid, FAR struct binary_s *bin)
       /* The errno value will get trashed by the following debug output */
 
       errorcode = get_errno();
-      binfo("ERROR: sigprocmask failed: %d\n", ret);
+      berr("ERROR: sigprocmask failed: %d\n", ret);
       goto errout;
     }
 
@@ -310,14 +310,14 @@ int schedule_unload(pid_t pid, FAR struct binary_s *bin)
       /* The errno value will get trashed by the following debug output */
 
       errorcode = get_errno();
-      binfo("ERROR: sigaction failed: %d\n" , ret);
+      berr("ERROR: sigaction failed: %d\n" , ret);
 
       /* Emergency removal from the list */
 
       flags = enter_critical_section();
       if (unload_list_remove(pid) != bin)
         {
-          bllerr("ERROR: Failed to remove structure\n");
+          berr("ERROR: Failed to remove structure\n");
         }
 
       leave_critical_section(flags);
diff --git a/binfmt/libelf/Kconfig b/binfmt/libelf/Kconfig
index 684eaba8bef..5580a70a475 100644
--- a/binfmt/libelf/Kconfig
+++ b/binfmt/libelf/Kconfig
@@ -35,7 +35,7 @@ config ELF_BUFFERINCR
 config ELF_DUMPBUFFER
 	bool "Dump ELF buffers"
 	default n
-	depends on DEBUG_FEATURES && CONFIG_DEBUG_INFO
+	depends on DEBUG_INFO
 	---help---
 		Dump various ELF buffers for debug purposes
 
diff --git a/binfmt/libnxflat/Kconfig b/binfmt/libnxflat/Kconfig
index 6929b04296c..66c0031528e 100644
--- a/binfmt/libnxflat/Kconfig
+++ b/binfmt/libnxflat/Kconfig
@@ -6,4 +6,4 @@
 config NXFLAT_DUMPBUFFER
 	bool "Dump NXFLAT buffers"
 	default n
-	depends on DEBUG_FEATURES && CONFIG_DEBUG_INFO
+	depends on DEBUG_INFO
diff --git a/binfmt/libpcode/Kconfig b/binfmt/libpcode/Kconfig
index c767aca7907..046dc71c55b 100644
--- a/binfmt/libpcode/Kconfig
+++ b/binfmt/libpcode/Kconfig
@@ -64,6 +64,6 @@ endif # PCODE_TEST_FS
 config PCODE_DUMPBUFFER
 	bool "Dump P-code buffers"
 	default n
-	depends on DEBUG_FEATURES && CONFIG_DEBUG_INFO
+	depends on DEBUG_INFO
 	---help---
 		Dump various P-code buffers for debug purposes
diff --git a/configs/Kconfig b/configs/Kconfig
index 98d4b30b2d9..75014db5fd4 100644
--- a/configs/Kconfig
+++ b/configs/Kconfig
@@ -997,7 +997,7 @@ config ARCH_BOARD_STM32F429I_DISCO
 
 config ARCH_BOARD_STM32F746G_DISCO
 	bool "STMicro STM32F746G-Discovery board"
-	depends on ARCH_CHIP_STM32F746
+	depends on ARCH_CHIP_STM32F746NG
 	select ARCH_HAVE_LEDS
 	select ARCH_HAVE_BUTTONS
 	select ARCH_HAVE_IRQBUTTONS
@@ -1006,8 +1006,14 @@ config ARCH_BOARD_STM32F746G_DISCO
 		MCU. The STM32F746NGH6  is a 216MHz Cortex-M7 operation with 1024Kb Flash
 		memory and 320Kb SRAM.
 
+config ARCH_BOARD_STM32F746_WS
+	bool "Waveshare STM32F746 board"
+	depends on ARCH_CHIP_STM32F746IG
+	---help---
+		Waveshare STM32F746 development board featuring the STM32F746IG MCU.
+
 config ARCH_BOARD_STM32L476VG_DISCO
-	bool "STMicro STM32F746VG-Discovery board"
+	bool "STMicro STM32L476VG -Discovery board"
 	depends on ARCH_CHIP_STM32L476RG
 	select ARCH_HAVE_LEDS
 	select ARCH_HAVE_BUTTONS
@@ -1438,6 +1444,7 @@ config ARCH_BOARD
 	default "stm32f411e-disco"         if ARCH_BOARD_STM32F411E_DISCO
 	default "stm32f429i-disco"         if ARCH_BOARD_STM32F429I_DISCO
 	default "stm32f746g-disco"         if ARCH_BOARD_STM32F746G_DISCO
+	default "stm32f746-ws"             if ARCH_BOARD_STM32F746_WS
 	default "stm32l476vg-disco"        if ARCH_BOARD_STM32L476VG_DISCO
 	default "stm32ldiscovery"          if ARCH_BOARD_STM32L_DISCOVERY
 	default "stm32vldiscovery"         if ARCH_BOARD_STM32VL_DISCOVERY
@@ -1812,6 +1819,9 @@ endif
 if ARCH_BOARD_STM32F746G_DISCO
 source "configs/stm32f746g-disco/Kconfig"
 endif
+if ARCH_BOARD_STM32F746_WS
+source "configs/stm32f746-ws/Kconfig"
+endif
 if ARCH_BOARD_STM32L476VG_DISCO
 source "configs/stm32l476vg-disco/Kconfig"
 endif
diff --git a/configs/README.txt b/configs/README.txt
index 3e44ef649c5..2e4c4aad958 100644
--- a/configs/README.txt
+++ b/configs/README.txt
@@ -658,6 +658,9 @@ configs/stm32f746g-disco
   MCU. The STM32F746NGH6  is a 216MHz Cortex-M7 operation with 1024Kb Flash
   memory and 300Kb SRAM.
 
+configs/stm32f746g-ws
+  Waveshare STM32F746 development board featuring the STM32F746IG MCU.
+
 configs/stm32l476vg-disco
   STMicro STM32L476VG_DISCO development board featuring the STM32L476VG
   MCU. The STM32L476VG  is a Cortex-M4 optimised for low-power operation
diff --git a/configs/amber/hello/defconfig b/configs/amber/hello/defconfig
index f7862235e30..506a83f03ec 100644
--- a/configs/amber/hello/defconfig
+++ b/configs/amber/hello/defconfig
@@ -298,7 +298,6 @@ CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y
 # System Logging
 #
 
-# CONFIG_SYSLOG is not set
 
 #
 # Graphics Support
diff --git a/configs/arduino-due/nsh/defconfig b/configs/arduino-due/nsh/defconfig
index ed94d781749..a14caa24fc2 100644
--- a/configs/arduino-due/nsh/defconfig
+++ b/configs/arduino-due/nsh/defconfig
@@ -553,7 +553,7 @@ CONFIG_UART0_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -588,7 +588,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/arduino-mega2560/hello/defconfig b/configs/arduino-mega2560/hello/defconfig
index d710f55debb..fe1eb43cfc0 100644
--- a/configs/arduino-mega2560/hello/defconfig
+++ b/configs/arduino-mega2560/hello/defconfig
@@ -360,7 +360,7 @@ CONFIG_USART0_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -393,7 +393,6 @@ CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/arduino-mega2560/nsh/defconfig b/configs/arduino-mega2560/nsh/defconfig
index d9eca795de8..5c561848996 100644
--- a/configs/arduino-mega2560/nsh/defconfig
+++ b/configs/arduino-mega2560/nsh/defconfig
@@ -369,7 +369,7 @@ CONFIG_USART0_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -402,7 +402,6 @@ CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/avr32dev1/nsh/defconfig b/configs/avr32dev1/nsh/defconfig
index a0846beb460..2b4bbaf59fa 100644
--- a/configs/avr32dev1/nsh/defconfig
+++ b/configs/avr32dev1/nsh/defconfig
@@ -345,7 +345,6 @@ CONFIG_FS_FAT=y
 # System Logging
 #
 
-# CONFIG_SYSLOG is not set
 
 #
 # Graphics Support
diff --git a/configs/avr32dev1/ostest/defconfig b/configs/avr32dev1/ostest/defconfig
index 1342e4c2e7c..0576325bf00 100644
--- a/configs/avr32dev1/ostest/defconfig
+++ b/configs/avr32dev1/ostest/defconfig
@@ -335,7 +335,6 @@ CONFIG_DISABLE_MOUNTPOINT=y
 # System Logging
 #
 
-# CONFIG_SYSLOG is not set
 
 #
 # Graphics Support
diff --git a/configs/c5471evm/httpd/defconfig b/configs/c5471evm/httpd/defconfig
index 5f0118087a3..faa36b27052 100644
--- a/configs/c5471evm/httpd/defconfig
+++ b/configs/c5471evm/httpd/defconfig
@@ -514,7 +514,6 @@ CONFIG_DISABLE_MOUNTPOINT=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/c5471evm/nettest/defconfig b/configs/c5471evm/nettest/defconfig
index ba47f3e2669..3e8e22c61a9 100644
--- a/configs/c5471evm/nettest/defconfig
+++ b/configs/c5471evm/nettest/defconfig
@@ -403,7 +403,7 @@ CONFIG_OTHER_SERIAL_CONSOLE=y
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -539,7 +539,6 @@ CONFIG_DISABLE_MOUNTPOINT=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/c5471evm/nsh/defconfig b/configs/c5471evm/nsh/defconfig
index 90dba4e681f..01b1ff19f51 100644
--- a/configs/c5471evm/nsh/defconfig
+++ b/configs/c5471evm/nsh/defconfig
@@ -440,7 +440,7 @@ CONFIG_OTHER_SERIAL_CONSOLE=y
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -581,7 +581,6 @@ CONFIG_DISABLE_MOUNTPOINT=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/cc3200-launchpad/nsh/defconfig b/configs/cc3200-launchpad/nsh/defconfig
index df8dc6ecb96..8c019e37767 100644
--- a/configs/cc3200-launchpad/nsh/defconfig
+++ b/configs/cc3200-launchpad/nsh/defconfig
@@ -453,7 +453,6 @@ CONFIG_FS_PROCFS=y
 # System Logging
 #
 
-# CONFIG_SYSLOG is not set
 
 #
 # Graphics Support
diff --git a/configs/cloudctrl/nsh/defconfig b/configs/cloudctrl/nsh/defconfig
index 2b6591e0ebc..523c5c2e597 100644
--- a/configs/cloudctrl/nsh/defconfig
+++ b/configs/cloudctrl/nsh/defconfig
@@ -872,7 +872,7 @@ CONFIG_USART2_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -1029,7 +1029,6 @@ CONFIG_FAT_MAXFNAME=32
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/cloudctrl/src/stm32_usb.c b/configs/cloudctrl/src/stm32_usb.c
index 9af1565f91f..a1e889feb15 100644
--- a/configs/cloudctrl/src/stm32_usb.c
+++ b/configs/cloudctrl/src/stm32_usb.c
@@ -301,7 +301,7 @@ xcpt_t stm32_setup_overcurrent(xcpt_t handler)
 #ifdef CONFIG_USBDEV
 void stm32_usbsuspend(FAR struct usbdev_s *dev, bool resume)
 {
-  ullinfo("resume: %d\n", resume);
+  uinfo("resume: %d\n", resume);
 }
 #endif
 
diff --git a/configs/compal_e86/nsh_highram/defconfig b/configs/compal_e86/nsh_highram/defconfig
index 29d7ceb2879..5bfe73a0ad9 100644
--- a/configs/compal_e86/nsh_highram/defconfig
+++ b/configs/compal_e86/nsh_highram/defconfig
@@ -413,7 +413,7 @@ CONFIG_OTHER_SERIAL_CONSOLE=y
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -452,7 +452,6 @@ CONFIG_OTHER_SERIAL_CONSOLE=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/compal_e88/nsh_highram/defconfig b/configs/compal_e88/nsh_highram/defconfig
index 66ca0db0ea5..042107a1009 100644
--- a/configs/compal_e88/nsh_highram/defconfig
+++ b/configs/compal_e88/nsh_highram/defconfig
@@ -413,7 +413,7 @@ CONFIG_OTHER_SERIAL_CONSOLE=y
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -452,7 +452,6 @@ CONFIG_OTHER_SERIAL_CONSOLE=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/compal_e99/nsh_compalram/defconfig b/configs/compal_e99/nsh_compalram/defconfig
index 77d140a6fe5..103c7e34696 100644
--- a/configs/compal_e99/nsh_compalram/defconfig
+++ b/configs/compal_e99/nsh_compalram/defconfig
@@ -450,7 +450,7 @@ CONFIG_OTHER_SERIAL_CONSOLE=y
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -489,7 +489,6 @@ CONFIG_OTHER_SERIAL_CONSOLE=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/compal_e99/nsh_highram/defconfig b/configs/compal_e99/nsh_highram/defconfig
index 3f18883c1d1..afd0172efb6 100644
--- a/configs/compal_e99/nsh_highram/defconfig
+++ b/configs/compal_e99/nsh_highram/defconfig
@@ -449,7 +449,7 @@ CONFIG_OTHER_SERIAL_CONSOLE=y
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -488,7 +488,6 @@ CONFIG_OTHER_SERIAL_CONSOLE=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/demo9s12ne64/ostest/defconfig b/configs/demo9s12ne64/ostest/defconfig
index dc2009b5d20..f9ee45ac71c 100644
--- a/configs/demo9s12ne64/ostest/defconfig
+++ b/configs/demo9s12ne64/ostest/defconfig
@@ -292,7 +292,6 @@ CONFIG_DISABLE_MOUNTPOINT=y
 # System Logging
 #
 
-# CONFIG_SYSLOG is not set
 
 #
 # Graphics Support
diff --git a/configs/dk-tm4c129x/ipv6/defconfig b/configs/dk-tm4c129x/ipv6/defconfig
index fc1e30d8165..06a79772796 100644
--- a/configs/dk-tm4c129x/ipv6/defconfig
+++ b/configs/dk-tm4c129x/ipv6/defconfig
@@ -637,7 +637,7 @@ CONFIG_UART0_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -788,7 +788,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/dk-tm4c129x/nsh/defconfig b/configs/dk-tm4c129x/nsh/defconfig
index a2d60ace10c..c01c46126a9 100644
--- a/configs/dk-tm4c129x/nsh/defconfig
+++ b/configs/dk-tm4c129x/nsh/defconfig
@@ -639,7 +639,7 @@ CONFIG_UART0_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -792,7 +792,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/dk-tm4c129x/src/tm4c_ethernet.c b/configs/dk-tm4c129x/src/tm4c_ethernet.c
index 927757e16d1..dbf31f08969 100644
--- a/configs/dk-tm4c129x/src/tm4c_ethernet.c
+++ b/configs/dk-tm4c129x/src/tm4c_ethernet.c
@@ -84,7 +84,7 @@ void tiva_ethernetmac(struct ether_addr *ethaddr)
   user0 = getreg32(TIVA_FLASH_USERREG0);
   user1 = getreg32(TIVA_FLASH_USERREG1);
 
-  nllinfo("user: %06x:%06x\n", user1 & 0x00ffffff, user0 & 0x00ffffff);
+  ninfo("user: %06x:%06x\n", user1 & 0x00ffffff, user0 & 0x00ffffff);
   DEBUGASSERT(user0 != 0xffffffff && user1 != 0xffffffff);
 
   /* Re-format that MAC address the way that the network expects to see it */
diff --git a/configs/ea3131/nsh/defconfig b/configs/ea3131/nsh/defconfig
index 7db317ab9fe..8b5c909d713 100644
--- a/configs/ea3131/nsh/defconfig
+++ b/configs/ea3131/nsh/defconfig
@@ -453,7 +453,6 @@ CONFIG_FS_FAT=y
 # System Logging
 #
 
-# CONFIG_SYSLOG is not set
 
 #
 # Graphics Support
diff --git a/configs/ea3131/pgnsh/defconfig b/configs/ea3131/pgnsh/defconfig
index e56fb71d68c..abb4c19f046 100644
--- a/configs/ea3131/pgnsh/defconfig
+++ b/configs/ea3131/pgnsh/defconfig
@@ -509,7 +509,7 @@ CONFIG_UART_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -552,7 +552,6 @@ CONFIG_FS_FAT=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/ea3131/src/lpc31_fillpage.c b/configs/ea3131/src/lpc31_fillpage.c
index 2020c844d92..56834721586 100644
--- a/configs/ea3131/src/lpc31_fillpage.c
+++ b/configs/ea3131/src/lpc31_fillpage.c
@@ -244,7 +244,7 @@ static inline void lpc31_initsrc(void)
       char devname[16];
 #endif
 
-      pgllinfo("Initializing %s\n", CONFIG_PAGING_BINPATH);
+      pginfo("Initializing %s\n", CONFIG_PAGING_BINPATH);
 
       /* No, do we need to mount an SD device? */
 
@@ -300,7 +300,7 @@ static inline void lpc31_initsrc(void)
     {
       /* No... the initialize now */
 
-      pgllinfo("Initializing\n");
+      pginfo("Initializing\n");
 
       /* First get an instance of the SPI device interface */
 
@@ -327,7 +327,7 @@ static inline void lpc31_initsrc(void)
       ret = MTD_IOCTL(g_pgsrc.mtd, MTDIOC_GEOMETRY, (unsigned long)&g_pgsrc.geo);
       DEBUGASSERT(ret >= 0);
       capacity = g_pgsrc.geo.erasesize*g_pgsrc.geo.neraseblocks;
-      pgllinfo("capacity: %d\n", capacity);
+      pginfo("capacity: %d\n", capacity);
       DEBUGASSERT(capacity >= (CONFIG_EA3131_PAGING_BINOFFSET + PG_TEXT_VSIZE));
 #endif
 
@@ -412,7 +412,7 @@ int up_fillpage(FAR struct tcb_s *tcb, FAR void *vpage)
   off_t   offset;
 #endif
 
-  pgllinfo("TCB: %p vpage: %p far: %08x\n", tcb, vpage, tcb->xcp.far);
+  pginfo("TCB: %p vpage: %p far: %08x\n", tcb, vpage, tcb->xcp.far);
   DEBUGASSERT(tcb->xcp.far >= PG_PAGED_VBASE && tcb->xcp.far < PG_PAGED_VEND);
 
   /* If BINPATH is defined, then it is the full path to a file on a mounted file
@@ -475,7 +475,7 @@ int up_fillpage(FAR struct tcb_s *tcb, FAR void *vpage)
 
 int up_fillpage(FAR struct tcb_s *tcb, FAR void *vpage, up_pgcallback_t pg_callback)
 {
-  pgllinfo("TCB: %p vpage: %d far: %08x\n", tcb, vpage, tcb->xcp.far);
+  pginfo("TCB: %p vpage: %d far: %08x\n", tcb, vpage, tcb->xcp.far);
   DEBUGASSERT(tcb->xcp.far >= PG_PAGED_VBASE && tcb->xcp.far < PG_PAGED_VEND);
 
 #if defined(CONFIG_PAGING_BINPATH)
diff --git a/configs/ea3131/src/lpc31_usbmsc.c b/configs/ea3131/src/lpc31_usbmsc.c
index f55bdc8e10f..0d9736d4d6b 100644
--- a/configs/ea3131/src/lpc31_usbmsc.c
+++ b/configs/ea3131/src/lpc31_usbmsc.c
@@ -93,8 +93,7 @@ int board_usbmsc_initialize(int port)
   pbuffer = (uint8_t *)kmm_malloc(BUFFER_SIZE);
   if (!pbuffer)
     {
-      lowsyslog(LOG_ERR, "ERROR: Failed to allocate ramdisk of size %d\n",
-                BUFFER_SIZE);
+      err("ERROR: Failed to allocate ramdisk of size %d\n", BUFFER_SIZE);
       return -ENOMEM;
     }
 
@@ -107,9 +106,8 @@ int board_usbmsc_initialize(int port)
                          RDFLAG_WRENABLED | RDFLAG_FUNLINK);
   if (ret < 0)
     {
-      syslog(LOG_ERR,
-             "ERROR: create_ramdisk: Failed to register ramdisk at %s: %d\n",
-             g_source, -ret);
+      err("ERROR: create_ramdisk: Failed to register ramdisk at %s: %d\n",
+          g_source, -ret);
       kmm_free(pbuffer);
       return ret;
     }
@@ -119,9 +117,8 @@ int board_usbmsc_initialize(int port)
   ret = mkfatfs(g_source, &g_fmt);
   if (ret < 0)
     {
-      syslog(LOG_ERR,
-             "ERROR: create_ramdisk: Failed to create FAT filesystem on ramdisk at %s\n",
-             g_source);
+      err("ERROR: create_ramdisk: Failed to create FAT filesystem on ramdisk at %s\n",
+          g_source);
       /* kmm_free(pbuffer); -- RAM disk is registered */
       return ret;
     }
diff --git a/configs/ea3131/usbserial/defconfig b/configs/ea3131/usbserial/defconfig
index 6d68bedc94f..cdab4df4bf5 100644
--- a/configs/ea3131/usbserial/defconfig
+++ b/configs/ea3131/usbserial/defconfig
@@ -527,7 +527,7 @@ CONFIG_USBHOST_HAVE_ASYNCH=y
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -567,7 +567,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/ea3152/ostest/defconfig b/configs/ea3152/ostest/defconfig
index 49dda7cc91a..2aa4bcbbb2a 100644
--- a/configs/ea3152/ostest/defconfig
+++ b/configs/ea3152/ostest/defconfig
@@ -442,7 +442,6 @@ CONFIG_DISABLE_MOUNTPOINT=y
 # System Logging
 #
 
-# CONFIG_SYSLOG is not set
 
 #
 # Graphics Support
diff --git a/configs/ea3152/src/lpc31_fillpage.c b/configs/ea3152/src/lpc31_fillpage.c
index 33dd4dc08af..51ad18749e4 100644
--- a/configs/ea3152/src/lpc31_fillpage.c
+++ b/configs/ea3152/src/lpc31_fillpage.c
@@ -244,7 +244,7 @@ static inline void lpc31_initsrc(void)
       char devname[16];
 #endif
 
-      pgllinfo("Initializing %s\n", CONFIG_PAGING_BINPATH);
+      pginfo("Initializing %s\n", CONFIG_PAGING_BINPATH);
 
       /* No, do we need to mount an SD device? */
 
@@ -300,7 +300,7 @@ static inline void lpc31_initsrc(void)
     {
       /* No... the initialize now */
 
-      pgllinfo("Initializing\n");
+      pginfo("Initializing\n");
 
       /* First get an instance of the SPI device interface */
 
@@ -327,7 +327,7 @@ static inline void lpc31_initsrc(void)
       ret = MTD_IOCTL(g_pgsrc.mtd, MTDIOC_GEOMETRY, (unsigned long)&g_pgsrc.geo);
       DEBUGASSERT(ret >= 0);
       capacity = g_pgsrc.geo.erasesize*g_pgsrc.geo.neraseblocks;
-      pgllinfo("capacity: %d\n", capacity);
+      pginfo("capacity: %d\n", capacity);
       DEBUGASSERT(capacity >= (CONFIG_EA3152_PAGING_BINOFFSET + PG_TEXT_VSIZE));
 #endif
 
@@ -412,7 +412,7 @@ int up_fillpage(FAR struct tcb_s *tcb, FAR void *vpage)
   off_t   offset;
 #endif
 
-  pgllinfo("TCB: %p vpage: %p far: %08x\n", tcb, vpage, tcb->xcp.far);
+  pginfo("TCB: %p vpage: %p far: %08x\n", tcb, vpage, tcb->xcp.far);
   DEBUGASSERT(tcb->xcp.far >= PG_PAGED_VBASE && tcb->xcp.far < PG_PAGED_VEND);
 
   /* If BINPATH is defined, then it is the full path to a file on a mounted file
@@ -475,7 +475,7 @@ int up_fillpage(FAR struct tcb_s *tcb, FAR void *vpage)
 
 int up_fillpage(FAR struct tcb_s *tcb, FAR void *vpage, up_pgcallback_t pg_callback)
 {
-  pgllinfo("TCB: %p vpage: %d far: %08x\n", tcb, vpage, tcb->xcp.far);
+  pginfo("TCB: %p vpage: %d far: %08x\n", tcb, vpage, tcb->xcp.far);
   DEBUGASSERT(tcb->xcp.far >= PG_PAGED_VBASE && tcb->xcp.far < PG_PAGED_VEND);
 
 #if defined(CONFIG_PAGING_BINPATH)
diff --git a/configs/ea3152/src/lpc31_usbmsc.c b/configs/ea3152/src/lpc31_usbmsc.c
index e251d5cbc02..b3e431eeba8 100644
--- a/configs/ea3152/src/lpc31_usbmsc.c
+++ b/configs/ea3152/src/lpc31_usbmsc.c
@@ -93,8 +93,8 @@ int board_usbmsc_initialize(int port)
   pbuffer = (uint8_t *)kmm_malloc(BUFFER_SIZE);
   if (!pbuffer)
     {
-      lowsyslog("board_usbmsc_initialize: Failed to allocate ramdisk of size %d\n",
-                BUFFER_SIZE);
+      err("ERROR: board_usbmsc_initialize: Failed to allocate ramdisk of size %d\n",
+          BUFFER_SIZE);
       return -ENOMEM;
     }
 
@@ -107,8 +107,8 @@ int board_usbmsc_initialize(int port)
                          RDFLAG_WRENABLED | RDFLAG_FUNLINK);
   if (ret < 0)
     {
-      printf("create_ramdisk: Failed to register ramdisk at %s: %d\n",
-             g_source, -ret);
+      err("ERROR: create_ramdisk: Failed to register ramdisk at %s: %d\n",
+          g_source, -ret);
       kmm_free(pbuffer);
       return ret;
     }
@@ -118,8 +118,8 @@ int board_usbmsc_initialize(int port)
   ret = mkfatfs(g_source, &g_fmt);
   if (ret < 0)
     {
-      printf("create_ramdisk: Failed to create FAT filesystem on ramdisk at %s\n",
-             g_source);
+      err("ERROR: create_ramdisk: Failed to create FAT filesystem on ramdisk at %s\n",
+          g_source);
       /* kmm_free(pbuffer); -- RAM disk is registered */
       return ret;
     }
diff --git a/configs/eagle100/httpd/defconfig b/configs/eagle100/httpd/defconfig
index b7920a1123b..e3f52f0a1ac 100644
--- a/configs/eagle100/httpd/defconfig
+++ b/configs/eagle100/httpd/defconfig
@@ -458,7 +458,6 @@ CONFIG_DISABLE_MOUNTPOINT=y
 # System Logging
 #
 
-# CONFIG_SYSLOG is not set
 
 #
 # Graphics Support
diff --git a/configs/eagle100/nettest/defconfig b/configs/eagle100/nettest/defconfig
index 3488e2b471b..6d40060e9e1 100644
--- a/configs/eagle100/nettest/defconfig
+++ b/configs/eagle100/nettest/defconfig
@@ -532,7 +532,7 @@ CONFIG_UART0_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -668,7 +668,6 @@ CONFIG_DISABLE_MOUNTPOINT=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/eagle100/nsh/defconfig b/configs/eagle100/nsh/defconfig
index 96471a6dcfa..96ac8e5c58d 100644
--- a/configs/eagle100/nsh/defconfig
+++ b/configs/eagle100/nsh/defconfig
@@ -608,7 +608,7 @@ CONFIG_UART0_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -763,7 +763,6 @@ CONFIG_FS_FAT=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/eagle100/nxflat/defconfig b/configs/eagle100/nxflat/defconfig
index 364634f48e7..81ac4c90461 100644
--- a/configs/eagle100/nxflat/defconfig
+++ b/configs/eagle100/nxflat/defconfig
@@ -409,7 +409,6 @@ CONFIG_FS_ROMFS=y
 # System Logging
 #
 
-# CONFIG_SYSLOG is not set
 
 #
 # Graphics Support
diff --git a/configs/eagle100/src/lm_ethernet.c b/configs/eagle100/src/lm_ethernet.c
index cc81b1667e3..69c6e6c8f48 100644
--- a/configs/eagle100/src/lm_ethernet.c
+++ b/configs/eagle100/src/lm_ethernet.c
@@ -83,7 +83,7 @@ void tiva_ethernetmac(struct ether_addr *ethaddr)
   user0 = getreg32(TIVA_FLASH_USERREG0);
   user1 = getreg32(TIVA_FLASH_USERREG1);
 
-  nllinfo("user: %06x:%06x\n", user1 & 0x00ffffff, user0 & 0x00ffffff);
+  ninfo("user: %06x:%06x\n", user1 & 0x00ffffff, user0 & 0x00ffffff);
   DEBUGASSERT(user0 != 0xffffffff && user1 != 0xffffffff);
 
   /* Re-format that MAC address the way that the network expects to see it */
diff --git a/configs/eagle100/thttpd/defconfig b/configs/eagle100/thttpd/defconfig
index ae3c7d6e275..a542cf2b7c9 100644
--- a/configs/eagle100/thttpd/defconfig
+++ b/configs/eagle100/thttpd/defconfig
@@ -516,7 +516,7 @@ CONFIG_UART0_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -654,7 +654,6 @@ CONFIG_FS_ROMFS=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/efm32-g8xx-stk/nsh/defconfig b/configs/efm32-g8xx-stk/nsh/defconfig
index d99809600d1..def34126e9d 100644
--- a/configs/efm32-g8xx-stk/nsh/defconfig
+++ b/configs/efm32-g8xx-stk/nsh/defconfig
@@ -462,7 +462,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 
 #
 # Graphics Support
diff --git a/configs/efm32gg-stk3700/nsh/defconfig b/configs/efm32gg-stk3700/nsh/defconfig
index d78466e83cf..c8fb8784654 100644
--- a/configs/efm32gg-stk3700/nsh/defconfig
+++ b/configs/efm32gg-stk3700/nsh/defconfig
@@ -456,7 +456,7 @@ CONFIG_OTHER_SERIAL_CONSOLE=y
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -489,7 +489,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/ekk-lm3s9b96/nsh/defconfig b/configs/ekk-lm3s9b96/nsh/defconfig
index c4c1ca9db1f..2b146ff6f76 100644
--- a/configs/ekk-lm3s9b96/nsh/defconfig
+++ b/configs/ekk-lm3s9b96/nsh/defconfig
@@ -597,7 +597,7 @@ CONFIG_UART0_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -753,7 +753,6 @@ CONFIG_NFS=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/ekk-lm3s9b96/src/lm_ethernet.c b/configs/ekk-lm3s9b96/src/lm_ethernet.c
index 16156f0d930..3c9cca9d6e4 100644
--- a/configs/ekk-lm3s9b96/src/lm_ethernet.c
+++ b/configs/ekk-lm3s9b96/src/lm_ethernet.c
@@ -84,7 +84,7 @@ void tiva_ethernetmac(struct ether_addr *ethaddr)
   user0 = getreg32(TIVA_FLASH_USERREG0);
   user1 = getreg32(TIVA_FLASH_USERREG1);
 
-  nllinfo("user: %06x:%06x\n", user1 & 0x00ffffff, user0 & 0x00ffffff);
+  ninfo("user: %06x:%06x\n", user1 & 0x00ffffff, user0 & 0x00ffffff);
   DEBUGASSERT(user0 != 0xffffffff && user1 != 0xffffffff);
 
   /* Re-format that MAC address the way that the network expects to see it */
diff --git a/configs/ez80f910200kitg/ostest/defconfig b/configs/ez80f910200kitg/ostest/defconfig
index 5ad96bd9153..cdd48e8e119 100644
--- a/configs/ez80f910200kitg/ostest/defconfig
+++ b/configs/ez80f910200kitg/ostest/defconfig
@@ -441,7 +441,7 @@ CONFIG_UART0_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -474,7 +474,6 @@ CONFIG_DISABLE_MOUNTPOINT=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/ez80f910200zco/dhcpd/defconfig b/configs/ez80f910200zco/dhcpd/defconfig
index 19f54e3feb8..a46d8181611 100644
--- a/configs/ez80f910200zco/dhcpd/defconfig
+++ b/configs/ez80f910200zco/dhcpd/defconfig
@@ -487,7 +487,7 @@ CONFIG_UART0_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -620,7 +620,6 @@ CONFIG_DISABLE_MOUNTPOINT=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/ez80f910200zco/httpd/defconfig b/configs/ez80f910200zco/httpd/defconfig
index c34eb7aff51..1d8f5613c88 100644
--- a/configs/ez80f910200zco/httpd/defconfig
+++ b/configs/ez80f910200zco/httpd/defconfig
@@ -496,7 +496,7 @@ CONFIG_UART0_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -634,7 +634,6 @@ CONFIG_DISABLE_MOUNTPOINT=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/ez80f910200zco/nettest/defconfig b/configs/ez80f910200zco/nettest/defconfig
index 9e0180deaf1..0975adabd05 100644
--- a/configs/ez80f910200zco/nettest/defconfig
+++ b/configs/ez80f910200zco/nettest/defconfig
@@ -488,7 +488,7 @@ CONFIG_UART0_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -626,7 +626,6 @@ CONFIG_DISABLE_MOUNTPOINT=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/ez80f910200zco/nsh/defconfig b/configs/ez80f910200zco/nsh/defconfig
index f431c18dad1..241877ecd1b 100644
--- a/configs/ez80f910200zco/nsh/defconfig
+++ b/configs/ez80f910200zco/nsh/defconfig
@@ -504,7 +504,7 @@ CONFIG_UART0_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -654,7 +654,6 @@ CONFIG_NET_HOSTNAME=""
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/ez80f910200zco/poll/defconfig b/configs/ez80f910200zco/poll/defconfig
index ca969eee985..f24325f5771 100644
--- a/configs/ez80f910200zco/poll/defconfig
+++ b/configs/ez80f910200zco/poll/defconfig
@@ -495,7 +495,7 @@ CONFIG_UART0_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -633,7 +633,6 @@ CONFIG_DISABLE_MOUNTPOINT=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/fire-stm32v2/nsh/defconfig b/configs/fire-stm32v2/nsh/defconfig
index 72a8e7e4a1a..a4ed137681d 100644
--- a/configs/fire-stm32v2/nsh/defconfig
+++ b/configs/fire-stm32v2/nsh/defconfig
@@ -928,7 +928,7 @@ CONFIG_USBMSC_SCSI_STACKSIZE=2048
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -1085,7 +1085,6 @@ CONFIG_FAT_MAXFNAME=32
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/fire-stm32v2/src/stm32_enc28j60.c b/configs/fire-stm32v2/src/stm32_enc28j60.c
index 41565d288f7..cd5ee2c6b31 100644
--- a/configs/fire-stm32v2/src/stm32_enc28j60.c
+++ b/configs/fire-stm32v2/src/stm32_enc28j60.c
@@ -188,7 +188,7 @@ void up_netinitialize(void)
   spi = stm32_spibus_initialize(ENC28J60_SPI_PORTNO);
   if (!spi)
     {
-      nllerr("ERROR: Failed to initialize SPI port %d\n", ENC28J60_SPI_PORTNO);
+      nerr("ERROR: Failed to initialize SPI port %d\n", ENC28J60_SPI_PORTNO);
       return;
     }
 
@@ -201,12 +201,12 @@ void up_netinitialize(void)
   ret = enc_initialize(spi, &g_enclower.lower, ENC28J60_DEVNO);
   if (ret < 0)
     {
-      nllerr("ERROR: Failed to bind SPI port %d ENC28J60 device %d: %d\n",
-             ENC28J60_SPI_PORTNO, ENC28J60_DEVNO, ret);
+      nerr("ERROR: Failed to bind SPI port %d ENC28J60 device %d: %d\n",
+           ENC28J60_SPI_PORTNO, ENC28J60_DEVNO, ret);
       return;
     }
 
-  nllinfo("Bound SPI port %d to ENC28J60 device %d\n",
+  ninfo("Bound SPI port %d to ENC28J60 device %d\n",
         ENC28J60_SPI_PORTNO, ENC28J60_DEVNO);
 }
 
diff --git a/configs/fire-stm32v2/src/stm32_usbdev.c b/configs/fire-stm32v2/src/stm32_usbdev.c
index ca46743f73c..ea3ee830545 100644
--- a/configs/fire-stm32v2/src/stm32_usbdev.c
+++ b/configs/fire-stm32v2/src/stm32_usbdev.c
@@ -114,5 +114,5 @@ int stm32_usbpullup(FAR struct usbdev_s *dev, bool enable)
 
 void stm32_usbsuspend(FAR struct usbdev_s *dev, bool resume)
 {
-  ullinfo("resume: %d\n", resume);
+  uinfo("resume: %d\n", resume);
 }
diff --git a/configs/freedom-kl25z/README.txt b/configs/freedom-kl25z/README.txt
index f2cc8e0c027..a4a806dd482 100644
--- a/configs/freedom-kl25z/README.txt
+++ b/configs/freedom-kl25z/README.txt
@@ -301,6 +301,11 @@ Where <subdir> is one of the following:
     configuration.  This configuration has far fewer features than the nsh
     configuration but is also a fraction of the size.
 
+    2016-06-21:
+    $ arm-none-eabi-size nuttx
+       text    data     bss     dec     hex filename
+      12282     196     736   13214    339e nuttx
+
     This minnsh configuration is a "proof-of-concept" and not very usable in
     its current state.  This configuration was created by disabling
     everything possible INCLUDING file system support.  Without file system
diff --git a/configs/freedom-kl25z/minnsh/defconfig b/configs/freedom-kl25z/minnsh/defconfig
index c2ccfaf0a66..4e2ba76061f 100644
--- a/configs/freedom-kl25z/minnsh/defconfig
+++ b/configs/freedom-kl25z/minnsh/defconfig
@@ -442,7 +442,6 @@ CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/freedom-kl25z/nsh/defconfig b/configs/freedom-kl25z/nsh/defconfig
index 285f30c8b38..debb15644d5 100644
--- a/configs/freedom-kl25z/nsh/defconfig
+++ b/configs/freedom-kl25z/nsh/defconfig
@@ -443,7 +443,7 @@ CONFIG_UART0_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -476,7 +476,6 @@ CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/freedom-kl26z/minnsh/defconfig b/configs/freedom-kl26z/minnsh/defconfig
index b21dd2b7102..12666fa8a73 100644
--- a/configs/freedom-kl26z/minnsh/defconfig
+++ b/configs/freedom-kl26z/minnsh/defconfig
@@ -445,7 +445,6 @@ CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/freedom-kl26z/nsh/defconfig b/configs/freedom-kl26z/nsh/defconfig
index af85a35e635..d22fc5bf084 100644
--- a/configs/freedom-kl26z/nsh/defconfig
+++ b/configs/freedom-kl26z/nsh/defconfig
@@ -443,7 +443,7 @@ CONFIG_UART0_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -476,7 +476,6 @@ CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/hymini-stm32v/README.txt b/configs/hymini-stm32v/README.txt
index 1afd69b08c0..2ec1c043535 100644
--- a/configs/hymini-stm32v/README.txt
+++ b/configs/hymini-stm32v/README.txt
@@ -650,7 +650,6 @@ Where <subdir> is one of the following:
     1. This configuration does have UART2 output enabled and set up as
        the system logging device:
 
-       CONFIG_SYSLOG=y                    : Enable output to syslog, not console
        CONFIG_SYSLOG_CHAR=y               : Use a character device for system logging
        CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" : UART2 will be /dev/ttyS0
 
diff --git a/configs/hymini-stm32v/buttons/defconfig b/configs/hymini-stm32v/buttons/defconfig
index bc42209cf81..84cf57940c9 100644
--- a/configs/hymini-stm32v/buttons/defconfig
+++ b/configs/hymini-stm32v/buttons/defconfig
@@ -743,7 +743,7 @@ CONFIG_USART1_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -783,7 +783,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/hymini-stm32v/nsh/defconfig b/configs/hymini-stm32v/nsh/defconfig
index d572218f049..1749a0acd02 100644
--- a/configs/hymini-stm32v/nsh/defconfig
+++ b/configs/hymini-stm32v/nsh/defconfig
@@ -772,7 +772,7 @@ CONFIG_USART1_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -818,7 +818,6 @@ CONFIG_FAT_LCNAMES=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/hymini-stm32v/nsh2/defconfig b/configs/hymini-stm32v/nsh2/defconfig
index 4e191fbbbf2..9458de82acb 100644
--- a/configs/hymini-stm32v/nsh2/defconfig
+++ b/configs/hymini-stm32v/nsh2/defconfig
@@ -897,7 +897,7 @@ CONFIG_USBMSC_SCSI_STACKSIZE=2048
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -945,7 +945,6 @@ CONFIG_FS_ROMFS=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/hymini-stm32v/src/stm32_ts.c b/configs/hymini-stm32v/src/stm32_ts.c
index 678dba89a24..16f91c3fd0e 100644
--- a/configs/hymini-stm32v/src/stm32_ts.c
+++ b/configs/hymini-stm32v/src/stm32_ts.c
@@ -106,7 +106,7 @@ static int hymini_ts_irq_attach(FAR struct ads7843e_config_s *state, xcpt_t isr)
 static void hymini_ts_irq_enable(FAR struct ads7843e_config_s *state,
     bool enable)
 {
-  illinfo("%d\n", enable);
+  iinfo("%d\n", enable);
 
   stm32_gpiosetevent(GPIO_TS_IRQ, true, true, true, enable? tc_isr:NULL);
 }
diff --git a/configs/hymini-stm32v/src/stm32_usbdev.c b/configs/hymini-stm32v/src/stm32_usbdev.c
index c1a21be6240..4a60528b42a 100644
--- a/configs/hymini-stm32v/src/stm32_usbdev.c
+++ b/configs/hymini-stm32v/src/stm32_usbdev.c
@@ -73,7 +73,7 @@
 
 void stm32_usbinitialize(void)
 {
-  ullinfo("called\n");
+  uinfo("called\n");
 
   /* USB Soft Connect Pullup */
   stm32_configgpio(GPIO_USB_PULLUP);
@@ -111,5 +111,5 @@ int stm32_usbpullup(FAR struct usbdev_s *dev, bool enable)
 
 void stm32_usbsuspend(FAR struct usbdev_s *dev, bool resume)
 {
-  ullinfo("resume: %d\n", resume);
+  uinfo("resume: %d\n", resume);
 }
diff --git a/configs/hymini-stm32v/usbmsc/defconfig b/configs/hymini-stm32v/usbmsc/defconfig
index a84c37fb42b..6af83e6dc57 100644
--- a/configs/hymini-stm32v/usbmsc/defconfig
+++ b/configs/hymini-stm32v/usbmsc/defconfig
@@ -825,7 +825,7 @@ CONFIG_USBMSC_SCSI_STACKSIZE=2048
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -865,7 +865,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/hymini-stm32v/usbnsh/defconfig b/configs/hymini-stm32v/usbnsh/defconfig
index 200447a70d3..d44ec35f6cc 100644
--- a/configs/hymini-stm32v/usbnsh/defconfig
+++ b/configs/hymini-stm32v/usbnsh/defconfig
@@ -793,7 +793,7 @@ CONFIG_CDCACM_PRODUCTSTR="CDC/ACM Serial"
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -833,7 +833,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-CONFIG_SYSLOG=y
 # CONFIG_SYSLOG_TIMESTAMP is not set
 CONFIG_SYSLOG_CHAR=y
 CONFIG_SYSLOG_DEVPATH="/dev/ttyS0"
diff --git a/configs/hymini-stm32v/usbserial/defconfig b/configs/hymini-stm32v/usbserial/defconfig
index aefb46b0480..45d53256452 100644
--- a/configs/hymini-stm32v/usbserial/defconfig
+++ b/configs/hymini-stm32v/usbserial/defconfig
@@ -799,7 +799,7 @@ CONFIG_PL2303_PRODUCTSTR="USBdev Serial"
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -833,7 +833,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/kwikstik-k40/ostest/defconfig b/configs/kwikstik-k40/ostest/defconfig
index 60166ea794c..094b28af90b 100644
--- a/configs/kwikstik-k40/ostest/defconfig
+++ b/configs/kwikstik-k40/ostest/defconfig
@@ -477,7 +477,7 @@ CONFIG_UART5_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -511,7 +511,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/kwikstik-k40/src/k40_usbdev.c b/configs/kwikstik-k40/src/k40_usbdev.c
index f4e206578c4..d21bd39adea 100644
--- a/configs/kwikstik-k40/src/k40_usbdev.c
+++ b/configs/kwikstik-k40/src/k40_usbdev.c
@@ -108,6 +108,6 @@ int kinetis_usbpullup(FAR struct usbdev_s *dev, bool enable)
 
 void kinetis_usbsuspend(FAR struct usbdev_s *dev, bool resume)
 {
-  ullinfo("resume: %d\n", resume);
+  uinfo("resume: %d\n", resume);
 #warning "Missing logic"
 }
diff --git a/configs/launchxl-tms57004/nsh/defconfig b/configs/launchxl-tms57004/nsh/defconfig
index cae356b118c..ed6cee7d90b 100644
--- a/configs/launchxl-tms57004/nsh/defconfig
+++ b/configs/launchxl-tms57004/nsh/defconfig
@@ -481,7 +481,7 @@ CONFIG_SCI1_2STOP=1
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -535,7 +535,6 @@ CONFIG_FS_PROCFS=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/lincoln60/netnsh/defconfig b/configs/lincoln60/netnsh/defconfig
index 38c6cb0587d..2a824c20adf 100644
--- a/configs/lincoln60/netnsh/defconfig
+++ b/configs/lincoln60/netnsh/defconfig
@@ -591,7 +591,7 @@ CONFIG_UART0_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -749,7 +749,6 @@ CONFIG_FS_FAT=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/lincoln60/nsh/defconfig b/configs/lincoln60/nsh/defconfig
index 609322785bf..e940e1f9d8f 100644
--- a/configs/lincoln60/nsh/defconfig
+++ b/configs/lincoln60/nsh/defconfig
@@ -486,7 +486,7 @@ CONFIG_UART0_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -528,7 +528,6 @@ CONFIG_FS_FAT=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/lincoln60/thttpd-binfs/defconfig b/configs/lincoln60/thttpd-binfs/defconfig
index 1cbd3aeb336..85d237e6dcd 100644
--- a/configs/lincoln60/thttpd-binfs/defconfig
+++ b/configs/lincoln60/thttpd-binfs/defconfig
@@ -523,7 +523,7 @@ CONFIG_UART0_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -666,7 +666,6 @@ CONFIG_FS_UNIONFS=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/lm3s6432-s2e/nsh/defconfig b/configs/lm3s6432-s2e/nsh/defconfig
index 618b1a5be18..14e14ef254f 100644
--- a/configs/lm3s6432-s2e/nsh/defconfig
+++ b/configs/lm3s6432-s2e/nsh/defconfig
@@ -587,7 +587,7 @@ CONFIG_UART1_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -736,7 +736,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/lm3s6432-s2e/src/lm_ethernet.c b/configs/lm3s6432-s2e/src/lm_ethernet.c
index 2d7f2c64148..6aeb02b3fc0 100644
--- a/configs/lm3s6432-s2e/src/lm_ethernet.c
+++ b/configs/lm3s6432-s2e/src/lm_ethernet.c
@@ -83,7 +83,7 @@ void tiva_ethernetmac(struct ether_addr *ethaddr)
   user0 = getreg32(TIVA_FLASH_USERREG0);
   user1 = getreg32(TIVA_FLASH_USERREG1);
 
-  nllinfo("user: %06x:%06x\n", user1 & 0x00ffffff, user0 & 0x00ffffff);
+  ninfo("user: %06x:%06x\n", user1 & 0x00ffffff, user0 & 0x00ffffff);
   DEBUGASSERT(user0 != 0xffffffff && user1 != 0xffffffff);
 
   /* Re-format that MAC address the way that the network expects to see it */
diff --git a/configs/lm3s6965-ek/discover/defconfig b/configs/lm3s6965-ek/discover/defconfig
index 1ede54c185d..f8a687f604f 100644
--- a/configs/lm3s6965-ek/discover/defconfig
+++ b/configs/lm3s6965-ek/discover/defconfig
@@ -602,7 +602,7 @@ CONFIG_UART0_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -757,7 +757,6 @@ CONFIG_FS_FAT=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/lm3s6965-ek/nsh/defconfig b/configs/lm3s6965-ek/nsh/defconfig
index 1ede54c185d..f8a687f604f 100644
--- a/configs/lm3s6965-ek/nsh/defconfig
+++ b/configs/lm3s6965-ek/nsh/defconfig
@@ -602,7 +602,7 @@ CONFIG_UART0_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -757,7 +757,6 @@ CONFIG_FS_FAT=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/lm3s6965-ek/nx/defconfig b/configs/lm3s6965-ek/nx/defconfig
index 0753cc248fa..eaccaa9a27e 100644
--- a/configs/lm3s6965-ek/nx/defconfig
+++ b/configs/lm3s6965-ek/nx/defconfig
@@ -549,7 +549,7 @@ CONFIG_UART0_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -583,7 +583,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/lm3s6965-ek/src/lm_ethernet.c b/configs/lm3s6965-ek/src/lm_ethernet.c
index bc26a77ef58..882c18c8811 100644
--- a/configs/lm3s6965-ek/src/lm_ethernet.c
+++ b/configs/lm3s6965-ek/src/lm_ethernet.c
@@ -83,7 +83,7 @@ void tiva_ethernetmac(struct ether_addr *ethaddr)
   user0 = getreg32(TIVA_FLASH_USERREG0);
   user1 = getreg32(TIVA_FLASH_USERREG1);
 
-  nllinfo("user: %06x:%06x\n", user1 & 0x00ffffff, user0 & 0x00ffffff);
+  ninfo("user: %06x:%06x\n", user1 & 0x00ffffff, user0 & 0x00ffffff);
   DEBUGASSERT(user0 != 0xffffffff && user1 != 0xffffffff);
 
   /* Re-format that MAC address the way that the network expects to see it */
diff --git a/configs/lm3s6965-ek/src/lm_oled.c b/configs/lm3s6965-ek/src/lm_oled.c
index bc28b2ac79d..2d72db7c1ea 100644
--- a/configs/lm3s6965-ek/src/lm_oled.c
+++ b/configs/lm3s6965-ek/src/lm_oled.c
@@ -114,7 +114,7 @@ FAR struct lcd_dev_s *board_graphics_setup(unsigned int devno)
   spi = tiva_ssibus_initialize(0);
   if (!spi)
     {
-      gllerr("ERROR: Failed to initialize SSI port 0\n");
+      gerr("ERROR: Failed to initialize SSI port 0\n");
     }
   else
     {
@@ -123,11 +123,11 @@ FAR struct lcd_dev_s *board_graphics_setup(unsigned int devno)
       dev = rit_initialize(spi, devno);
       if (!dev)
         {
-          gllerr("ERROR: Failed to bind SSI port 0 to OLED %d: %d\n", devno);
+          gerr("ERROR: Failed to bind SSI port 0 to OLED %d: %d\n", devno);
         }
      else
         {
-          gllinfo("Bound SSI port 0 to OLED %d\n", devno);
+          ginfo("Bound SSI port 0 to OLED %d\n", devno);
 
           /* And turn the OLED on (CONFIG_LCD_MAXPOWER should be 1) */
 
diff --git a/configs/lm3s6965-ek/tcpecho/defconfig b/configs/lm3s6965-ek/tcpecho/defconfig
index d4282f16fb1..b9ba2269e96 100644
--- a/configs/lm3s6965-ek/tcpecho/defconfig
+++ b/configs/lm3s6965-ek/tcpecho/defconfig
@@ -542,7 +542,7 @@ CONFIG_UART0_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -695,7 +695,6 @@ CONFIG_FS_FAT=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/lm3s8962-ek/nsh/defconfig b/configs/lm3s8962-ek/nsh/defconfig
index 067dad9f116..a751de477d3 100644
--- a/configs/lm3s8962-ek/nsh/defconfig
+++ b/configs/lm3s8962-ek/nsh/defconfig
@@ -612,7 +612,7 @@ CONFIG_UART0_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -767,7 +767,6 @@ CONFIG_FS_FAT=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/lm3s8962-ek/nx/defconfig b/configs/lm3s8962-ek/nx/defconfig
index ab03e9edc65..3726d932ee9 100644
--- a/configs/lm3s8962-ek/nx/defconfig
+++ b/configs/lm3s8962-ek/nx/defconfig
@@ -559,7 +559,7 @@ CONFIG_UART0_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -593,7 +593,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/lm3s8962-ek/src/lm_ethernet.c b/configs/lm3s8962-ek/src/lm_ethernet.c
index d93810f066b..1c337358899 100644
--- a/configs/lm3s8962-ek/src/lm_ethernet.c
+++ b/configs/lm3s8962-ek/src/lm_ethernet.c
@@ -83,7 +83,7 @@ void tiva_ethernetmac(struct ether_addr *ethaddr)
   user0 = getreg32(TIVA_FLASH_USERREG0);
   user1 = getreg32(TIVA_FLASH_USERREG1);
 
-  nllinfo("user: %06x:%06x\n", user1 & 0x00ffffff, user0 & 0x00ffffff);
+  ninfo("user: %06x:%06x\n", user1 & 0x00ffffff, user0 & 0x00ffffff);
   DEBUGASSERT(user0 != 0xffffffff && user1 != 0xffffffff);
 
   /* Re-format that MAC address the way that the network expects to see it */
diff --git a/configs/lm3s8962-ek/src/lm_oled.c b/configs/lm3s8962-ek/src/lm_oled.c
index 0be8eaf8743..6e557a12208 100644
--- a/configs/lm3s8962-ek/src/lm_oled.c
+++ b/configs/lm3s8962-ek/src/lm_oled.c
@@ -113,7 +113,7 @@ FAR struct lcd_dev_s *board_graphics_setup(unsigned int devno)
   spi = tiva_ssibus_initialize(0);
   if (!spi)
     {
-      gllerr("ERROR: Failed to initialize SSI port 0\n");
+      gerr("ERROR: Failed to initialize SSI port 0\n");
     }
   else
     {
@@ -122,11 +122,11 @@ FAR struct lcd_dev_s *board_graphics_setup(unsigned int devno)
       dev = rit_initialize(spi, devno);
       if (!dev)
         {
-          gllerr("ERROR: Failed to bind SSI port 0 to OLED %d: %d\n", devno);
+          gerr("ERROR: Failed to bind SSI port 0 to OLED %d: %d\n", devno);
         }
      else
         {
-          gllinfo("Bound SSI port 0 to OLED %d\n", devno);
+          ginfo("Bound SSI port 0 to OLED %d\n", devno);
 
           /* And turn the OLED on (CONFIG_LCD_MAXPOWER should be 1) */
 
diff --git a/configs/lm4f120-launchpad/nsh/defconfig b/configs/lm4f120-launchpad/nsh/defconfig
index d87cc7cf0dc..52b8f0257ce 100644
--- a/configs/lm4f120-launchpad/nsh/defconfig
+++ b/configs/lm4f120-launchpad/nsh/defconfig
@@ -413,7 +413,6 @@ CONFIG_UART0_2STOP=0
 # System Logging
 #
 
-# CONFIG_SYSLOG is not set
 
 #
 # Graphics Support
diff --git a/configs/lpc4330-xplorer/nsh/defconfig b/configs/lpc4330-xplorer/nsh/defconfig
index 13c015c5c41..d27d7cd0a34 100644
--- a/configs/lpc4330-xplorer/nsh/defconfig
+++ b/configs/lpc4330-xplorer/nsh/defconfig
@@ -532,7 +532,7 @@ CONFIG_USART0_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -577,7 +577,6 @@ CONFIG_FAT_MAXFNAME=32
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/lpc4337-ws/nsh/defconfig b/configs/lpc4337-ws/nsh/defconfig
index 11e1e3062f5..c11c4afae07 100644
--- a/configs/lpc4337-ws/nsh/defconfig
+++ b/configs/lpc4337-ws/nsh/defconfig
@@ -569,7 +569,7 @@ CONFIG_CDCACM_PRODUCTSTR="lpc4337-ws"
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -615,7 +615,6 @@ CONFIG_FAT_MAXFNAME=32
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/lpc4357-evb/nsh/defconfig b/configs/lpc4357-evb/nsh/defconfig
index 37601e039c0..fabc0b794d8 100644
--- a/configs/lpc4357-evb/nsh/defconfig
+++ b/configs/lpc4357-evb/nsh/defconfig
@@ -505,7 +505,6 @@ CONFIG_FAT_MAXFNAME=32
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/lpc4370-link2/nsh/defconfig b/configs/lpc4370-link2/nsh/defconfig
index 82d3fdea904..34ae243ed8d 100644
--- a/configs/lpc4370-link2/nsh/defconfig
+++ b/configs/lpc4370-link2/nsh/defconfig
@@ -567,7 +567,7 @@ CONFIG_CDCACM_PRODUCTSTR="lpc4370-link2"
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -613,7 +613,6 @@ CONFIG_FAT_MAXFNAME=32
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/lpcxpresso-lpc1115/minnsh/defconfig b/configs/lpcxpresso-lpc1115/minnsh/defconfig
index 4b7a2748e95..43b4aa9e6ae 100644
--- a/configs/lpcxpresso-lpc1115/minnsh/defconfig
+++ b/configs/lpcxpresso-lpc1115/minnsh/defconfig
@@ -459,7 +459,6 @@ CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/lpcxpresso-lpc1115/nsh/defconfig b/configs/lpcxpresso-lpc1115/nsh/defconfig
index 17f1bfde042..b684acd7796 100644
--- a/configs/lpcxpresso-lpc1115/nsh/defconfig
+++ b/configs/lpcxpresso-lpc1115/nsh/defconfig
@@ -445,7 +445,7 @@ CONFIG_UART0_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -479,7 +479,6 @@ CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/lpcxpresso-lpc1768/dhcpd/defconfig b/configs/lpcxpresso-lpc1768/dhcpd/defconfig
index 9e7037cf026..f88c0eaa4fd 100644
--- a/configs/lpcxpresso-lpc1768/dhcpd/defconfig
+++ b/configs/lpcxpresso-lpc1768/dhcpd/defconfig
@@ -515,7 +515,7 @@ CONFIG_UART3_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -644,7 +644,6 @@ CONFIG_DISABLE_MOUNTPOINT=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/lpcxpresso-lpc1768/nsh/defconfig b/configs/lpcxpresso-lpc1768/nsh/defconfig
index e548bd2b89c..345c2275b8b 100644
--- a/configs/lpcxpresso-lpc1768/nsh/defconfig
+++ b/configs/lpcxpresso-lpc1768/nsh/defconfig
@@ -631,7 +631,7 @@ CONFIG_UART3_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -786,7 +786,6 @@ CONFIG_FS_FAT=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/lpcxpresso-lpc1768/nx/defconfig b/configs/lpcxpresso-lpc1768/nx/defconfig
index 2473e7e4b33..6036f0b1aec 100644
--- a/configs/lpcxpresso-lpc1768/nx/defconfig
+++ b/configs/lpcxpresso-lpc1768/nx/defconfig
@@ -527,7 +527,7 @@ CONFIG_UART3_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -561,7 +561,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/lpcxpresso-lpc1768/src/lpc17_oled.c b/configs/lpcxpresso-lpc1768/src/lpc17_oled.c
index b759aa7f0c3..063af42b2dc 100644
--- a/configs/lpcxpresso-lpc1768/src/lpc17_oled.c
+++ b/configs/lpcxpresso-lpc1768/src/lpc17_oled.c
@@ -112,7 +112,7 @@ FAR struct lcd_dev_s *board_graphics_setup(unsigned int devno)
   spi = lpc17_sspbus_initialize(1);
   if (!spi)
     {
-      gllerr("ERROR: Failed to initialize SPI port 1\n");
+      gerr("ERROR: Failed to initialize SPI port 1\n");
     }
   else
     {
@@ -121,11 +121,11 @@ FAR struct lcd_dev_s *board_graphics_setup(unsigned int devno)
       dev = ug_initialize(spi, devno);
       if (!dev)
         {
-          gllerr("ERROR: Failed to bind SPI port 1 to OLED %d: %d\n", devno);
+          gerr("ERROR: Failed to bind SPI port 1 to OLED %d: %d\n", devno);
         }
      else
         {
-          gllinfo("Bound SPI port 1 to OLED %d\n", devno);
+          ginfo("Bound SPI port 1 to OLED %d\n", devno);
 
           /* And turn the OLED on (dim) */
 
@@ -193,7 +193,7 @@ int lpc17_ssp1cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd)
 #ifdef CONFIG_UG9664HSWAG01_POWER
 void ug_power(unsigned int devno, bool on)
 {
-  gllinfo("power %s\n", on ? "ON" : "OFF");
+  ginfo("power %s\n", on ? "ON" : "OFF");
   (void)lpc17_gpiowrite(LPCXPRESSO_OLED_POWER, on);
 }
 #endif
diff --git a/configs/lpcxpresso-lpc1768/thttpd/defconfig b/configs/lpcxpresso-lpc1768/thttpd/defconfig
index e203df5654c..dfe3556a78f 100644
--- a/configs/lpcxpresso-lpc1768/thttpd/defconfig
+++ b/configs/lpcxpresso-lpc1768/thttpd/defconfig
@@ -514,7 +514,7 @@ CONFIG_UART3_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -653,7 +653,6 @@ CONFIG_FS_ROMFS=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/lpcxpresso-lpc1768/usbmsc/defconfig b/configs/lpcxpresso-lpc1768/usbmsc/defconfig
index fe6c95bf21c..0e18fd3a3ed 100644
--- a/configs/lpcxpresso-lpc1768/usbmsc/defconfig
+++ b/configs/lpcxpresso-lpc1768/usbmsc/defconfig
@@ -540,7 +540,7 @@ CONFIG_USBMSC_SCSI_STACKSIZE=2048
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -579,7 +579,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/maple/nsh/defconfig b/configs/maple/nsh/defconfig
index fd555b7de2c..b348746c157 100644
--- a/configs/maple/nsh/defconfig
+++ b/configs/maple/nsh/defconfig
@@ -755,7 +755,7 @@ CONFIG_USBDEV_TRACE_NRECORDS=32
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -796,7 +796,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/maple/nx/defconfig b/configs/maple/nx/defconfig
index 686663cfa82..ab045784c67 100644
--- a/configs/maple/nx/defconfig
+++ b/configs/maple/nx/defconfig
@@ -903,7 +903,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/maple/src/stm32_usbdev.c b/configs/maple/src/stm32_usbdev.c
index d27177a2409..104624d6450 100644
--- a/configs/maple/src/stm32_usbdev.c
+++ b/configs/maple/src/stm32_usbdev.c
@@ -74,7 +74,7 @@
 
 void stm32_usbinitialize(void)
 {
-  ullinfo("called\n");
+  uinfo("called\n");
 
   /* USB Soft Connect Pullup */
 
@@ -113,5 +113,5 @@ int stm32_usbpullup(FAR struct usbdev_s *dev, bool enable)
 
 void stm32_usbsuspend(FAR struct usbdev_s *dev, bool resume)
 {
-  ullinfo("resume: %d\n", resume);
+  uinfo("resume: %d\n", resume);
 }
diff --git a/configs/maple/usbnsh/defconfig b/configs/maple/usbnsh/defconfig
index 58380687fa0..bea93df83dd 100644
--- a/configs/maple/usbnsh/defconfig
+++ b/configs/maple/usbnsh/defconfig
@@ -829,7 +829,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/mbed/hidkbd/defconfig b/configs/mbed/hidkbd/defconfig
index aec81d64449..0a185161614 100644
--- a/configs/mbed/hidkbd/defconfig
+++ b/configs/mbed/hidkbd/defconfig
@@ -438,7 +438,6 @@ CONFIG_HIDKBD_NPOLLWAITERS=2
 # System Logging
 #
 
-# CONFIG_SYSLOG is not set
 
 #
 # Graphics Support
diff --git a/configs/mbed/nsh/defconfig b/configs/mbed/nsh/defconfig
index 6596091fc86..a94ba59b538 100644
--- a/configs/mbed/nsh/defconfig
+++ b/configs/mbed/nsh/defconfig
@@ -553,7 +553,6 @@ CONFIG_FS_FAT=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/mcu123-lpc214x/composite/defconfig b/configs/mcu123-lpc214x/composite/defconfig
index eda130109f5..bba97d42c17 100644
--- a/configs/mcu123-lpc214x/composite/defconfig
+++ b/configs/mcu123-lpc214x/composite/defconfig
@@ -531,7 +531,7 @@ CONFIG_USBMSC_SCSI_STACKSIZE=2048
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -570,7 +570,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/mcu123-lpc214x/nsh/defconfig b/configs/mcu123-lpc214x/nsh/defconfig
index ef656130501..128167e6871 100644
--- a/configs/mcu123-lpc214x/nsh/defconfig
+++ b/configs/mcu123-lpc214x/nsh/defconfig
@@ -456,7 +456,7 @@ CONFIG_UART1_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -500,7 +500,6 @@ CONFIG_FAT_MAXFNAME=32
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/mcu123-lpc214x/usbmsc/defconfig b/configs/mcu123-lpc214x/usbmsc/defconfig
index 3fba717eafc..8a6ea1a428c 100644
--- a/configs/mcu123-lpc214x/usbmsc/defconfig
+++ b/configs/mcu123-lpc214x/usbmsc/defconfig
@@ -495,7 +495,7 @@ CONFIG_USBMSC_SCSI_STACKSIZE=2048
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -534,7 +534,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/mcu123-lpc214x/usbserial/defconfig b/configs/mcu123-lpc214x/usbserial/defconfig
index 4c01c08a481..b445b24704b 100644
--- a/configs/mcu123-lpc214x/usbserial/defconfig
+++ b/configs/mcu123-lpc214x/usbserial/defconfig
@@ -517,7 +517,7 @@ CONFIG_PL2303_PRODUCTSTR="USBdev Serial"
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -551,7 +551,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/micropendous3/hello/defconfig b/configs/micropendous3/hello/defconfig
index b843bb70a70..a1de9375e28 100644
--- a/configs/micropendous3/hello/defconfig
+++ b/configs/micropendous3/hello/defconfig
@@ -306,7 +306,6 @@ CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y
 # System Logging
 #
 
-# CONFIG_SYSLOG is not set
 
 #
 # Graphics Support
diff --git a/configs/mikroe-stm32f4/README.txt b/configs/mikroe-stm32f4/README.txt
index 667761ba247..ace80f20fbd 100644
--- a/configs/mikroe-stm32f4/README.txt
+++ b/configs/mikroe-stm32f4/README.txt
@@ -908,7 +908,6 @@ Where <subdir> is one of the following:
     3. This configuration does have UART2 output enabled and set up as
        the system logging device:
 
-       CONFIG_SYSLOG=y                    : Enable output to syslog, not console
        CONFIG_SYSLOG_CHAR=y               : Use a character device for system logging
        CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" : UART2 will be /dev/ttyS0
 
diff --git a/configs/mikroe-stm32f4/fulldemo/defconfig b/configs/mikroe-stm32f4/fulldemo/defconfig
index d2855b82194..6d2cd51f370 100644
--- a/configs/mikroe-stm32f4/fulldemo/defconfig
+++ b/configs/mikroe-stm32f4/fulldemo/defconfig
@@ -1020,7 +1020,6 @@ CONFIG_FS_BINFS=y
 #
 # System Logging
 #
-CONFIG_SYSLOG=y
 # CONFIG_SYSLOG_TIMESTAMP is not set
 CONFIG_SYSLOG_CHAR=y
 CONFIG_SYSLOG_DEVPATH="/dev/ttyS0"
diff --git a/configs/mikroe-stm32f4/kostest/defconfig b/configs/mikroe-stm32f4/kostest/defconfig
index 541bf36f6d2..c28a02bc75a 100644
--- a/configs/mikroe-stm32f4/kostest/defconfig
+++ b/configs/mikroe-stm32f4/kostest/defconfig
@@ -962,7 +962,6 @@ CONFIG_SMARTFS_MAXNAMLEN=16
 #
 # System Logging
 #
-CONFIG_SYSLOG=y
 # CONFIG_SYSLOG_TIMESTAMP is not set
 CONFIG_SYSLOG_CHAR=y
 CONFIG_SYSLOG_DEVPATH="/dev/ttyS0"
diff --git a/configs/mikroe-stm32f4/nsh/defconfig b/configs/mikroe-stm32f4/nsh/defconfig
index b70544ce971..596b4b78a0b 100644
--- a/configs/mikroe-stm32f4/nsh/defconfig
+++ b/configs/mikroe-stm32f4/nsh/defconfig
@@ -902,7 +902,6 @@ CONFIG_SMARTFS_MAXNAMLEN=16
 #
 # System Logging
 #
-CONFIG_SYSLOG=y
 # CONFIG_SYSLOG_TIMESTAMP is not set
 CONFIG_SYSLOG_CHAR=y
 CONFIG_SYSLOG_DEVPATH="/dev/ttyS0"
diff --git a/configs/mikroe-stm32f4/nx/defconfig b/configs/mikroe-stm32f4/nx/defconfig
index f15e9f29d5f..1d29349a7e9 100644
--- a/configs/mikroe-stm32f4/nx/defconfig
+++ b/configs/mikroe-stm32f4/nx/defconfig
@@ -783,7 +783,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-CONFIG_SYSLOG=y
 # CONFIG_SYSLOG_TIMESTAMP is not set
 CONFIG_SYSLOG_CHAR=y
 CONFIG_SYSLOG_DEVPATH="/dev/ttyS0"
diff --git a/configs/mikroe-stm32f4/nxlines/defconfig b/configs/mikroe-stm32f4/nxlines/defconfig
index 6d6e72883b6..e910925c583 100644
--- a/configs/mikroe-stm32f4/nxlines/defconfig
+++ b/configs/mikroe-stm32f4/nxlines/defconfig
@@ -783,7 +783,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-CONFIG_SYSLOG=y
 # CONFIG_SYSLOG_TIMESTAMP is not set
 CONFIG_SYSLOG_CHAR=y
 CONFIG_SYSLOG_DEVPATH="/dev/ttyS0"
diff --git a/configs/mikroe-stm32f4/nxtext/defconfig b/configs/mikroe-stm32f4/nxtext/defconfig
index efe5b4720f4..fa83fa73d4a 100644
--- a/configs/mikroe-stm32f4/nxtext/defconfig
+++ b/configs/mikroe-stm32f4/nxtext/defconfig
@@ -783,7 +783,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-CONFIG_SYSLOG=y
 # CONFIG_SYSLOG_TIMESTAMP is not set
 CONFIG_SYSLOG_CHAR=y
 CONFIG_SYSLOG_DEVPATH="/dev/ttyS0"
diff --git a/configs/mikroe-stm32f4/src/stm32_idle.c b/configs/mikroe-stm32f4/src/stm32_idle.c
index 54265e8a47a..140de1b15f0 100644
--- a/configs/mikroe-stm32f4/src/stm32_idle.c
+++ b/configs/mikroe-stm32f4/src/stm32_idle.c
@@ -125,7 +125,7 @@ static void up_idlepm(void)
 
   if (newstate != oldstate)
     {
-      _llinfo("newstate= %d oldstate=%d\n", newstate, oldstate);
+      _info("newstate= %d oldstate=%d\n", newstate, oldstate);
 
       flags = enter_critical_section();
 
diff --git a/configs/mikroe-stm32f4/src/stm32_usb.c b/configs/mikroe-stm32f4/src/stm32_usb.c
index c8b819fea30..001d6e0930a 100644
--- a/configs/mikroe-stm32f4/src/stm32_usb.c
+++ b/configs/mikroe-stm32f4/src/stm32_usb.c
@@ -300,7 +300,7 @@ xcpt_t stm32_setup_overcurrent(xcpt_t handler)
 #ifdef CONFIG_USBDEV
 void stm32_usbsuspend(FAR struct usbdev_s *dev, bool resume)
 {
-  ullinfo("resume: %d\n", resume);
+  uinfo("resume: %d\n", resume);
 }
 #endif
 
diff --git a/configs/mikroe-stm32f4/src/stm32_vs1053.c b/configs/mikroe-stm32f4/src/stm32_vs1053.c
index 98b8aeddcc3..74e7d4310c1 100644
--- a/configs/mikroe-stm32f4/src/stm32_vs1053.c
+++ b/configs/mikroe-stm32f4/src/stm32_vs1053.c
@@ -187,7 +187,7 @@ void up_vs1053initialize(FAR struct spi_dev_s* spi)
   pVs1053 = vs1053_initialize(spi, &g_vs1053lower.lower, VS1053_DEVNO);
   if (pVs1053 == NULL)
     {
-      audllerr("ERROR: Failed to bind SPI port %d VS1053 device\n", VS1053_DEVNO);
+      auderr("ERROR: Failed to bind SPI port %d VS1053 device\n", VS1053_DEVNO);
       return;
     }
 
@@ -200,7 +200,7 @@ void up_vs1053initialize(FAR struct spi_dev_s* spi)
       auderr("ERROR: Failed to register VS1053 Audio device\n");
     }
 
-  audllinfo("Bound SPI port to VS1053 device %s\n", name);
+  audinfo("Bound SPI port to VS1053 device %s\n", name);
 }
 
 #endif /* CONFIG_VS1053 */
diff --git a/configs/mikroe-stm32f4/usbnsh/defconfig b/configs/mikroe-stm32f4/usbnsh/defconfig
index af0fd609fbd..771a1c9fce0 100644
--- a/configs/mikroe-stm32f4/usbnsh/defconfig
+++ b/configs/mikroe-stm32f4/usbnsh/defconfig
@@ -951,7 +951,6 @@ CONFIG_SMARTFS_MAXNAMLEN=16
 #
 # System Logging
 #
-CONFIG_SYSLOG=y
 # CONFIG_SYSLOG_TIMESTAMP is not set
 CONFIG_SYSLOG_CHAR=y
 CONFIG_SYSLOG_DEVPATH="/dev/ttyS0"
diff --git a/configs/mirtoo/nsh/defconfig b/configs/mirtoo/nsh/defconfig
index faf80c044b3..53c083284ac 100644
--- a/configs/mirtoo/nsh/defconfig
+++ b/configs/mirtoo/nsh/defconfig
@@ -533,7 +533,7 @@ CONFIG_UART1_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -567,7 +567,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/mirtoo/nxffs/defconfig b/configs/mirtoo/nxffs/defconfig
index 5a9b691c1b6..0c240a27549 100644
--- a/configs/mirtoo/nxffs/defconfig
+++ b/configs/mirtoo/nxffs/defconfig
@@ -564,7 +564,7 @@ CONFIG_UART1_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -608,7 +608,6 @@ CONFIG_NXFFS_TAILTHRESHOLD=8192
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/moteino-mega/hello/defconfig b/configs/moteino-mega/hello/defconfig
index c2cf278267b..ddc57e49e37 100644
--- a/configs/moteino-mega/hello/defconfig
+++ b/configs/moteino-mega/hello/defconfig
@@ -362,7 +362,6 @@ CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/moteino-mega/nsh/defconfig b/configs/moteino-mega/nsh/defconfig
index 36156b8a292..f2590d782dd 100644
--- a/configs/moteino-mega/nsh/defconfig
+++ b/configs/moteino-mega/nsh/defconfig
@@ -371,7 +371,6 @@ CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/moxa/nsh/defconfig b/configs/moxa/nsh/defconfig
index a46d5327131..1ad986a2c89 100644
--- a/configs/moxa/nsh/defconfig
+++ b/configs/moxa/nsh/defconfig
@@ -482,7 +482,7 @@ CONFIG_ARCH_HAVE_SERIAL_TERMIOS=y
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -632,7 +632,6 @@ CONFIG_FS_UNIONFS=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/mx1ads/ostest/defconfig b/configs/mx1ads/ostest/defconfig
index b9442ef16f4..6e555f7cdda 100644
--- a/configs/mx1ads/ostest/defconfig
+++ b/configs/mx1ads/ostest/defconfig
@@ -406,7 +406,6 @@ CONFIG_DISABLE_MOUNTPOINT=y
 # System Logging
 #
 
-# CONFIG_SYSLOG is not set
 
 #
 # Graphics Support
diff --git a/configs/ne64badge/ostest/defconfig b/configs/ne64badge/ostest/defconfig
index 52e1afd874d..8566d4ab1fa 100644
--- a/configs/ne64badge/ostest/defconfig
+++ b/configs/ne64badge/ostest/defconfig
@@ -292,7 +292,6 @@ CONFIG_DISABLE_MOUNTPOINT=y
 # System Logging
 #
 
-# CONFIG_SYSLOG is not set
 
 #
 # Graphics Support
diff --git a/configs/ne64badge/src/m9s12_buttons.c b/configs/ne64badge/src/m9s12_buttons.c
index dc67eeec6a4..522d402c491 100644
--- a/configs/ne64badge/src/m9s12_buttons.c
+++ b/configs/ne64badge/src/m9s12_buttons.c
@@ -53,42 +53,23 @@
  * Pre-processor Definitions
  ****************************************************************************/
 
-/* Enables debug output from this file (needs CONFIG_DEBUG_FEATURES with
- * CONFIG_DEBUG_INFO too)
- */
-
-#undef BUTTON_DEBUG   /* Define to enable debug */
-#undef BUTTON_VERBOSE /* Define to enable verbose debug */
-
-#ifdef BUTTON_DEBUG
-#  define btnerr  _llerr
-#  ifdef BUTTON_VERBOSE
-#    define btninfo  _llerr
-#  else
-#    define btninfo(x...)
+#ifdef CONFIG_DEBUG_INPUT
+#  define btnerr        _err
+#  define btninfo(x...) _info
 #  endif
 #else
-#  undef BUTTON_VERBOSE
 #  define btnerr(x...)
 #  define btninfo(x...)
 #endif
 
 /* Dump GPIO registers */
 
-#ifdef BUTTON_VERBOSE
+#ifdef CONFIG_DEBUG_INPUT
 #  define btn_dumpgpio(m) m9s12_dumpgpio(m)
 #else
 #  define btn_dumpgpio(m)
 #endif
 
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
diff --git a/configs/ntosd-dm320/nettest/defconfig b/configs/ntosd-dm320/nettest/defconfig
index d5e1e4c25c9..66a56c48d7a 100644
--- a/configs/ntosd-dm320/nettest/defconfig
+++ b/configs/ntosd-dm320/nettest/defconfig
@@ -441,7 +441,7 @@ CONFIG_UART1_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -577,7 +577,6 @@ CONFIG_DISABLE_MOUNTPOINT=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/ntosd-dm320/nsh/defconfig b/configs/ntosd-dm320/nsh/defconfig
index 253a848408c..19b759f998d 100644
--- a/configs/ntosd-dm320/nsh/defconfig
+++ b/configs/ntosd-dm320/nsh/defconfig
@@ -490,7 +490,7 @@ CONFIG_UART1_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -644,7 +644,6 @@ CONFIG_FS_ROMFS=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/ntosd-dm320/poll/defconfig b/configs/ntosd-dm320/poll/defconfig
index 19312449ba2..ca965d06f47 100644
--- a/configs/ntosd-dm320/poll/defconfig
+++ b/configs/ntosd-dm320/poll/defconfig
@@ -440,7 +440,7 @@ CONFIG_UART1_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -574,7 +574,6 @@ CONFIG_DISABLE_MOUNTPOINT=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/ntosd-dm320/src/dm320_network.c b/configs/ntosd-dm320/src/dm320_network.c
index fc8e1592d94..80911ff5fe1 100644
--- a/configs/ntosd-dm320/src/dm320_network.c
+++ b/configs/ntosd-dm320/src/dm320_network.c
@@ -52,18 +52,6 @@
 
 extern void dm9x_initialize(void);
 
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
@@ -79,8 +67,8 @@ void up_netinitialize(void)
    * width is 16-bits.
    */
 
-  nllinfo("CS4CTRL1=%04x CS4CTRL2=%04x\n",
-          getreg16(DM320_EMIF_CS4CTRL1), getreg16(DM320_EMIF_CS4CTRL2));
+  ninfo("CS4CTRL1=%04x CS4CTRL2=%04x\n",
+        getreg16(DM320_EMIF_CS4CTRL1), getreg16(DM320_EMIF_CS4CTRL2));
 
   /* It is assumed that bootloader has already configured CS4.  Here,
    * we will only make certain that the GIO is properly configured
@@ -91,9 +79,9 @@ void up_netinitialize(void)
   GIO_INTERRUPT(GIO_DM9000A_INT);
   GIO_RISINGEDGE(GIO_DM9000A_INT);
 
-  nllinfo("GIO DIR0=%04x INV0=%04x IRQPORT=%04x IRQEDGE=%04x\n",
-          getreg16(DM320_GIO_DIR0), getreg16(DM320_GIO_INV0),
-          getreg16(DM320_GIO_IRQPORT), getreg16(DM320_GIO_IRQEDGE));
+  ninfo("GIO DIR0=%04x INV0=%04x IRQPORT=%04x IRQEDGE=%04x\n",
+        getreg16(DM320_GIO_DIR0), getreg16(DM320_GIO_INV0),
+        getreg16(DM320_GIO_IRQPORT), getreg16(DM320_GIO_IRQEDGE));
 
   /* Then initialize the driver */
 
diff --git a/configs/ntosd-dm320/thttpd/defconfig b/configs/ntosd-dm320/thttpd/defconfig
index 189372f25ac..bec6c696fcf 100644
--- a/configs/ntosd-dm320/thttpd/defconfig
+++ b/configs/ntosd-dm320/thttpd/defconfig
@@ -433,7 +433,7 @@ CONFIG_UART1_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -571,7 +571,6 @@ CONFIG_FS_ROMFS=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/ntosd-dm320/udp/defconfig b/configs/ntosd-dm320/udp/defconfig
index 976f7018242..44a24d42089 100644
--- a/configs/ntosd-dm320/udp/defconfig
+++ b/configs/ntosd-dm320/udp/defconfig
@@ -513,7 +513,6 @@ CONFIG_DISABLE_MOUNTPOINT=y
 # System Logging
 #
 
-# CONFIG_SYSLOG is not set
 
 #
 # Graphics Support
diff --git a/configs/ntosd-dm320/webserver/defconfig b/configs/ntosd-dm320/webserver/defconfig
index 0c1575922bf..ef35dd42fca 100644
--- a/configs/ntosd-dm320/webserver/defconfig
+++ b/configs/ntosd-dm320/webserver/defconfig
@@ -446,7 +446,7 @@ CONFIG_UART1_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -580,7 +580,6 @@ CONFIG_DISABLE_MOUNTPOINT=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/nucleo-144/f746-evalos/defconfig b/configs/nucleo-144/f746-evalos/defconfig
index 06fc415c041..f8c9ad88688 100644
--- a/configs/nucleo-144/f746-evalos/defconfig
+++ b/configs/nucleo-144/f746-evalos/defconfig
@@ -665,7 +665,7 @@ CONFIG_USART3_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -707,7 +707,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/nucleo-144/f746-nsh/defconfig b/configs/nucleo-144/f746-nsh/defconfig
index 68451cbb1b7..7cbeb670936 100644
--- a/configs/nucleo-144/f746-nsh/defconfig
+++ b/configs/nucleo-144/f746-nsh/defconfig
@@ -651,7 +651,7 @@ CONFIG_USART6_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -692,7 +692,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/nucleo-144/f767-evalos/defconfig b/configs/nucleo-144/f767-evalos/defconfig
index 5e15aafa6b1..d1b95c6d2b8 100644
--- a/configs/nucleo-144/f767-evalos/defconfig
+++ b/configs/nucleo-144/f767-evalos/defconfig
@@ -670,7 +670,7 @@ CONFIG_USART3_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -712,7 +712,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/nucleo-144/f767-nsh/defconfig b/configs/nucleo-144/f767-nsh/defconfig
index d939a39556e..8b1e83fad49 100644
--- a/configs/nucleo-144/f767-nsh/defconfig
+++ b/configs/nucleo-144/f767-nsh/defconfig
@@ -656,7 +656,7 @@ CONFIG_USART6_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -697,7 +697,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/nucleo-144/include/board.h b/configs/nucleo-144/include/board.h
index ea4e2efbe2d..1561ad8cc68 100644
--- a/configs/nucleo-144/include/board.h
+++ b/configs/nucleo-144/include/board.h
@@ -111,7 +111,7 @@
  *
  * PLL_VCO = (8,000,000 / 4) * 216 = 432 MHz
  * SYSCLK  = 432 MHz / 2 = 216 MHz
- * USB OTG FS, SDMMC and RNG Clock = 432 MHz / 9 = 48MHz
+ * USB OTG FS, SDMMC and RNG Clock = 432 MHz / 9 = 48 MHz
  */
 
 #define STM32_PLLCFG_PLLM       RCC_PLLCFG_PLLM(4)
@@ -125,6 +125,7 @@
 
 /* Configure factors for  PLLSAI clock */
 
+#define CONFIG_STM32F7_PLLSAI 1
 #define STM32_RCC_PLLSAICFGR_PLLSAIN    RCC_PLLSAICFGR_PLLSAIN(192)
 #define STM32_RCC_PLLSAICFGR_PLLSAIP    RCC_PLLSAICFGR_PLLSAIP(2)
 #define STM32_RCC_PLLSAICFGR_PLLSAIQ    RCC_PLLSAICFGR_PLLSAIQ(2)
@@ -132,16 +133,20 @@
 
 /* Configure Dedicated Clock Configuration Register */
 
-#define STM32_RCC_DCKCFGR_PLLI2SDIVQ RCC_DCKCFGR_PLLI2SDIVQ(1)
-#define STM32_RCC_DCKCFGR_PLLSAIDIVQ RCC_DCKCFGR_PLLSAIDIVQ(1)
-#define STM32_RCC_DCKCFGR_SAI1SRC       RCC_DCKCFGR_SAI1SRC_PLLSAI
-#define STM32_RCC_DCKCFGR_SAI2SRC       RCC_DCKCFGR_SAI2SRC_PLLSAI
-#define STM32_RCC_DCKCFGR_TIMPRE        0
-#define STM32_RCC_DCKCFGR_I2S1SRC       RCC_DCKCFGR_SAI1SRC_PLL
-#define STM32_RCC_DCKCFGR_I2S2SRC       RCC_DCKCFGR_SAI2SRC_PLL
+#define STM32_RCC_DCKCFGR1_PLLI2SDIVQ  RCC_DCKCFGR1_PLLI2SDIVQ(1)
+#define STM32_RCC_DCKCFGR1_PLLSAIDIVQ  RCC_DCKCFGR1_PLLSAIDIVQ(1)
+#define STM32_RCC_DCKCFGR1_PLLSAIDIVR  RCC_DCKCFGR1_PLLSAIDIVR(0)
+#define STM32_RCC_DCKCFGR1_SAI1SRC     RCC_DCKCFGR1_SAI1SEL(0)
+#define STM32_RCC_DCKCFGR1_SAI2SRC     RCC_DCKCFGR1_SAI2SEL(0)
+#define STM32_RCC_DCKCFGR1_TIMPRESRC   0
+#define STM32_RCC_DCKCFGR1_DFSDM1SRC   0
+#define STM32_RCC_DCKCFGR1_ADFSDM1SRC  0
+
+
 
 /* Configure factors for  PLLI2S clock */
 
+#define CONFIG_STM32F7_PLLI2S 1
 #define STM32_RCC_PLLI2SCFGR_PLLI2SN   RCC_PLLI2SCFGR_PLLI2SN(192)
 #define STM32_RCC_PLLI2SCFGR_PLLI2SP   RCC_PLLI2SCFGR_PLLI2SP(2)
 #define STM32_RCC_PLLI2SCFGR_PLLI2SQ   RCC_PLLI2SCFGR_PLLI2SQ(2)
@@ -149,11 +154,24 @@
 
 /* Configure Dedicated Clock Configuration Register 2 */
 
-#define STM32_RCC_DCKCFGR2_FMPI2C1SEL RCC_DCKCFGR2_FMPI2C1SEL_APB
-#define STM32_RCC_DCKCFGR2_CECSEL     RCC_DCKCFGR2_CECSEL_HSI
-#define STM32_RCC_DCKCFGR2_CK48MSEL   RCC_DCKCFGR2_CK48MSEL_PLLSAI
-#define STM32_RCC_DCKCFGR2_SDIOSEL    RCC_DCKCFGR2_SDIOSEL_48MHZ
-#define STM32_RCC_DCKCFGR2_SPDIFRXSEL RCC_DCKCFGR2_SPDIFRXSEL_PLL
+#define STM32_RCC_DCKCFGR2_USART1SRC  RCC_DCKCFGR2_USART1SEL_APB
+#define STM32_RCC_DCKCFGR2_USART2SRC  RCC_DCKCFGR2_USART2SEL_APB
+#define STM32_RCC_DCKCFGR2_UART4SRC   RCC_DCKCFGR2_UART4SEL_APB
+#define STM32_RCC_DCKCFGR2_UART5SRC   RCC_DCKCFGR2_UART5SEL_APB
+#define STM32_RCC_DCKCFGR2_USART6SRC  RCC_DCKCFGR2_USART6SEL_APB
+#define STM32_RCC_DCKCFGR2_UART7SRC   RCC_DCKCFGR2_UART7SEL_APB
+#define STM32_RCC_DCKCFGR2_UART8SRC   RCC_DCKCFGR2_UART8SEL_APB
+#define STM32_RCC_DCKCFGR2_I2C1SRC    RCC_DCKCFGR2_I2C1SEL_HSI
+#define STM32_RCC_DCKCFGR2_I2C2SRC    RCC_DCKCFGR2_I2C2SEL_HSI
+#define STM32_RCC_DCKCFGR2_I2C3SRC    RCC_DCKCFGR2_I2C3SEL_HSI
+#define STM32_RCC_DCKCFGR2_I2C4SRC    RCC_DCKCFGR2_I2C4SEL_HSI
+#define STM32_RCC_DCKCFGR2_LPTIM1SRC  RCC_DCKCFGR2_LPTIM1SEL_APB
+#define STM32_RCC_DCKCFGR2_CECSRC     RCC_DCKCFGR2_CECSEL_HSI
+#define STM32_RCC_DCKCFGR2_CK48MSRC   RCC_DCKCFGR2_CK48MSEL_PLLSAI
+#define STM32_RCC_DCKCFGR2_SDMMCSRC   RCC_DCKCFGR2_SDMMCSEL_48MHZ
+#define STM32_RCC_DCKCFGR2_SDMMC2SRC  RCC_DCKCFGR2_SDMMC2SEL_48MHZ
+#define STM32_RCC_DCKCFGR2_DSISRC     RCC_DCKCFGR2_DSISEL_48MHZ
+
 
 /* Several prescalers allow the configuration of the two AHB buses, the
  * high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum
@@ -311,20 +329,27 @@
  * USART8: has no remap
  */
 
+/* DMA channels *************************************************************/
+/* ADC */
+
+#define ADC1_DMA_CHAN DMAMAP_ADC1_1
+#define ADC2_DMA_CHAN DMAMAP_ADC2_1
+#define ADC3_DMA_CHAN DMAMAP_ADC3_1
+
 /* SPI
  *
  *
- *  PA6   MISO CN12-13
- *  PA7   MOSI CN12-15
- *  PA5   SCK  CN12-11
+ *  PA6   SPI1_MISO CN12-13
+ *  PA7   SPI1_MOSI CN12-15
+ *  PA5   SPI1_SCK  CN12-11
  *
- *  PB14  MISO CN12-28
- *  PB15  MOSI CN12-26
- *  PB10  SCK  CN12-25
+ *  PB14  SPI2_MISO CN12-28
+ *  PB15  SPI2_MOSI CN12-26
+ *  PB13  SPI2_SCK  CN12-30
  *
- *  PB4   MISO CN12-27
- *  PB5   MOSI CN12-29
- *  PB3   SCK  CN12-31
+ *  PB4   SPI3_MISO CN12-27
+ *  PB5   SPI3_MOSI CN12-29
+ *  PB3   SPI3_SCK  CN12-31
  */
 
 #define GPIO_SPI1_MISO   GPIO_SPI1_MISO_1
@@ -333,11 +358,34 @@
 
 #define GPIO_SPI2_MISO   GPIO_SPI2_MISO_1
 #define GPIO_SPI2_MOSI   GPIO_SPI2_MOSI_1
-#define GPIO_SPI2_SCK    GPIO_SPI2_SCK_2
+#define GPIO_SPI2_SCK    GPIO_SPI2_SCK_3
 
-#define GPIO_SPI3_MISO  GPIO_SPI3_MISO_1
-#define GPIO_SPI3_MOSI  GPIO_SPI3_MOSI_2
-#define GPIO_SPI3_SCK   GPIO_SPI3_SCK_1
+#define GPIO_SPI3_MISO   GPIO_SPI3_MISO_1
+#define GPIO_SPI3_MOSI   GPIO_SPI3_MOSI_2
+#define GPIO_SPI3_SCK    GPIO_SPI3_SCK_1
+
+/* I2C
+ *
+ *
+ *  PB8   I2C1_SCL CN12-3
+ *  PB9   I2C1_SDA CN12-5
+
+ *  PB10   I2C2_SCL CN11-51
+ *  PB11 I2C2_SDA CN12-18
+ *
+ *  PA8   I2C3_SCL CN12-23
+ *  PC9   I2C3_SDA CN12-1
+ *
+ */
+
+#define GPIO_I2C1_SCL GPIO_I2C1_SCL_2
+#define GPIO_I2C1_SDA GPIO_I2C1_SDA_2
+
+#define GPIO_I2C2_SCL GPIO_I2C2_SCL_1
+#define GPIO_I2C2_SDA GPIO_I2C2_SDA_1
+
+#define GPIO_I2C3_SCL GPIO_I2C3_SCL_1
+#define GPIO_I2C3_SDA GPIO_I2C3_SDA_1
 
 /* The STM32 F7 connects to a SMSC LAN8742A PHY using these pins:
  *
diff --git a/configs/nucleo-144/src/Makefile b/configs/nucleo-144/src/Makefile
index e179c34a7b8..e4e02750bd4 100644
--- a/configs/nucleo-144/src/Makefile
+++ b/configs/nucleo-144/src/Makefile
@@ -56,6 +56,9 @@ endif
 ifeq ($(CONFIG_SPI),y)
 CSRCS += stm32_spi.c
 endif
+ifeq ($(CONFIG_ADC),y)
+CSRCS += stm32_adc.c
+endif
 
 ifeq ($(HAVE_SDIO),y)
 CSRCS += stm32_sdio.c
diff --git a/configs/nucleo-144/src/nucleo-144.h b/configs/nucleo-144/src/nucleo-144.h
index 8737deee611..48a6f9f11a3 100644
--- a/configs/nucleo-144/src/nucleo-144.h
+++ b/configs/nucleo-144/src/nucleo-144.h
@@ -95,9 +95,8 @@
 
 #define GPIO_BTN_USER  (GPIO_INPUT | GPIO_FLOAT | GPIO_EXTI | GPIO_PORTC | GPIO_PIN13)
 
-/* SPI ***************************************************************************
- *
- */
+/* SPI ***************************************************************************/
+
 #define GPIO_SPI_CS    (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | \
                         GPIO_OUTPUT_SET)
 
@@ -185,5 +184,17 @@ void stm32_dma_alloc_init(void);
 int stm32_dma_alloc_init(void);
 #endif
 
+/****************************************************************************
+ * Name: stm32_adc_initialize
+ *
+ * Description:
+ *   Called at application startup time to initialize the ADC functionality.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_ADC
+int board_adc_initialize(void);
+#endif
+
 #endif /* __ASSEMBLY__ */
 #endif /* __CONFIGS_NUCLEO_144_SRC_NUCLEO_144_H */
diff --git a/configs/nucleo-144/src/stm32_adc.c b/configs/nucleo-144/src/stm32_adc.c
new file mode 100644
index 00000000000..f185335a7a1
--- /dev/null
+++ b/configs/nucleo-144/src/stm32_adc.c
@@ -0,0 +1,188 @@
+/************************************************************************************
+ * configs/nucleo-144/src/stm32_adc.c
+ *
+ *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <errno.h>
+#include <debug.h>
+
+#include <nuttx/board.h>
+#include <nuttx/analog/adc.h>
+#include <arch/board/board.h>
+
+#include "chip.h"
+#include "stm32_gpio.h"
+#include "stm32_adc.h"
+#include "nucleo-144.h"
+
+#ifdef CONFIG_ADC
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Configuration ********************************************************************/
+/* Up to 3 ADC interfaces are supported */
+
+#if STM32F7_NADC < 3
+#  undef CONFIG_STM32F7_ADC3
+#endif
+
+#if STM32F7_NADC < 2
+#  undef CONFIG_STM32F7_ADC2
+#endif
+
+#if STM32F7_NADC < 1
+#  undef CONFIG_STM32F7_ADC1
+#endif
+
+#if defined(CONFIG_STM32F7_ADC1) || defined(CONFIG_STM32F7_ADC2) || defined(CONFIG_STM32F7_ADC3)
+#ifndef CONFIG_STM32F7_ADC1
+#  warning "Channel information only available for ADC1"
+#endif
+
+/* The number of ADC channels in the conversion list */
+
+#define ADC1_NCHANNELS 1
+
+/************************************************************************************
+ * Private Data
+ ************************************************************************************/
+
+/* Identifying number of each ADC channel: Variable Resistor.
+ *
+ * {1,  2,  3, 4,  5,  6, 7,  8,  9, 10, 11, 12, 13, 15};
+ */
+
+#ifdef CONFIG_STM32F7_ADC1
+static const uint8_t  g_chanlist[ADC1_NCHANNELS] = {3};
+
+/* Configurations of pins used byte each ADC channels
+ *
+ * {GPIO_ADC1_IN1,  GPIO_ADC1_IN2,  GPIO_ADC1_IN3, GPIO_ADC1_IN4,  GPIO_ADC1_IN5, 
+ *  GPIO_ADC1_IN6,  GPIO_ADC1_IN7,  GPIO_ADC1_IN8,  GPIO_ADC1_IN9, GPIO_ADC1_IN10,
+ *  GPIO_ADC1_IN11, GPIO_ADC1_IN12, GPIO_ADC1_IN13, GPIO_ADC1_IN15};
+ */
+
+static const uint32_t g_pinlist[ADC1_NCHANNELS] = {GPIO_ADC1_IN3};
+#endif
+
+/************************************************************************************
+ * Private Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Name: board_adc_setup
+ *
+ * Description:
+ *   All STM32 architectures must provide the following interface to work with
+ *   examples/adc.
+ *
+ ************************************************************************************/
+
+int board_adc_setup(void)
+{
+  return board_adc_initialize();
+}
+
+/************************************************************************************
+ * Name: stm32_adc_initialize
+ *
+ * Description:
+ *   Called at application startup time to initialize the ADC functionality.
+ *
+ ************************************************************************************/
+
+int board_adc_initialize(void)
+{
+#ifdef CONFIG_STM32F7_ADC1
+  static bool initialized = false;
+  struct adc_dev_s *adc;
+  int ret;
+  int i;
+
+  /* Check if we have already initialized */
+
+  if (!initialized)
+    {
+      /* Configure the pins as analog inputs for the selected channels */
+
+      for (i = 0; i < ADC1_NCHANNELS; i++)
+        {
+          if (g_pinlist[i] != 0)
+            {
+              stm32_configgpio(g_pinlist[i]);
+            }
+        }
+
+      /* Call stm32_adcinitialize() to get an instance of the ADC interface */
+
+      adc = stm32_adc_initialize(1, g_chanlist, ADC1_NCHANNELS);
+      if (adc == NULL)
+        {
+          aerr("ERROR: Failed to get ADC interface\n");
+          return -ENODEV;
+        }
+
+      /* Register the ADC driver at "/dev/adc0" */
+
+      ret = adc_register("/dev/adc0", adc);
+      if (ret < 0)
+        {
+          aerr("ERROR: adc_register failed: %d\n", ret);
+          return ret;
+        }
+
+      /* Now we are initialized */
+
+      initialized = true;
+    }
+
+  return OK;
+#else
+  return -ENOSYS;
+#endif
+}
+
+#endif /* CONFIG_STM32F7_ADC1 || CONFIG_STM32F7_ADC2 || CONFIG_STM32F7_ADC3 */
+#endif /* CONFIG_ADC */
diff --git a/configs/nucleo-f303re/adc/defconfig b/configs/nucleo-f303re/adc/defconfig
index c7f0d633787..372d8112240 100644
--- a/configs/nucleo-f303re/adc/defconfig
+++ b/configs/nucleo-f303re/adc/defconfig
@@ -743,7 +743,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/nucleo-f303re/can/defconfig b/configs/nucleo-f303re/can/defconfig
index 3a3c06931ae..9d8f635d967 100644
--- a/configs/nucleo-f303re/can/defconfig
+++ b/configs/nucleo-f303re/can/defconfig
@@ -745,7 +745,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/nucleo-f303re/nxlines/defconfig b/configs/nucleo-f303re/nxlines/defconfig
index 868dff9a652..265a518bbc7 100644
--- a/configs/nucleo-f303re/nxlines/defconfig
+++ b/configs/nucleo-f303re/nxlines/defconfig
@@ -815,7 +815,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-CONFIG_SYSLOG=y
 # CONFIG_SYSLOG_TIMESTAMP is not set
 # CONFIG_SYSLOG_CHAR is not set
 
diff --git a/configs/nucleo-f303re/pwm/defconfig b/configs/nucleo-f303re/pwm/defconfig
index e794d3b47c4..18a81bc3776 100644
--- a/configs/nucleo-f303re/pwm/defconfig
+++ b/configs/nucleo-f303re/pwm/defconfig
@@ -749,7 +749,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-CONFIG_SYSLOG=y
 # CONFIG_SYSLOG_TIMESTAMP is not set
 # CONFIG_SYSLOG_CHAR is not set
 
diff --git a/configs/nucleo-f303re/serialrx/defconfig b/configs/nucleo-f303re/serialrx/defconfig
index 760b77e3479..34450260056 100644
--- a/configs/nucleo-f303re/serialrx/defconfig
+++ b/configs/nucleo-f303re/serialrx/defconfig
@@ -795,7 +795,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/nucleo-f303re/uavcan/defconfig b/configs/nucleo-f303re/uavcan/defconfig
index 6473097cf39..4f53df45553 100644
--- a/configs/nucleo-f303re/uavcan/defconfig
+++ b/configs/nucleo-f303re/uavcan/defconfig
@@ -722,7 +722,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/nucleo-f4x1re/f401-nsh/defconfig b/configs/nucleo-f4x1re/f401-nsh/defconfig
index 164422be804..6f84c5fa5bd 100644
--- a/configs/nucleo-f4x1re/f401-nsh/defconfig
+++ b/configs/nucleo-f4x1re/f401-nsh/defconfig
@@ -748,7 +748,7 @@ CONFIG_USART2_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -789,7 +789,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/nucleo-f4x1re/f411-nsh/defconfig b/configs/nucleo-f4x1re/f411-nsh/defconfig
index 5f353390328..e30e31814c5 100644
--- a/configs/nucleo-f4x1re/f411-nsh/defconfig
+++ b/configs/nucleo-f4x1re/f411-nsh/defconfig
@@ -750,7 +750,7 @@ CONFIG_USART2_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -791,7 +791,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/nucleo-f4x1re/src/stm32_ajoystick.c b/configs/nucleo-f4x1re/src/stm32_ajoystick.c
index d4cb9d374eb..432d91667b4 100644
--- a/configs/nucleo-f4x1re/src/stm32_ajoystick.c
+++ b/configs/nucleo-f4x1re/src/stm32_ajoystick.c
@@ -340,8 +340,8 @@ static void ajoy_enable(FAR const struct ajoy_lowerhalf_s *lower,
   flags = enter_critical_section();
   ajoy_disable();
 
-  illinfo("press: %02x release: %02x handler: %p arg: %p\n",
-          press, release, handler, arg);
+  iinfo("press: %02x release: %02x handler: %p arg: %p\n",
+        press, release, handler, arg);
 
   /* If no events are indicated or if no handler is provided, then this
    * must really be a request to disable interrupts.
@@ -372,8 +372,8 @@ static void ajoy_enable(FAR const struct ajoy_lowerhalf_s *lower,
                falling = ((press & bit) != 0);
                rising  = ((release & bit) != 0);
 
-               illinfo("GPIO %d: rising: %d falling: %d\n",
-                        i, rising, falling);
+               iinfo("GPIO %d: rising: %d falling: %d\n",
+                      i, rising, falling);
 
                (void)stm32_gpiosetevent(g_joygpio[i], rising, falling,
                                         true, ajoy_interrupt);
diff --git a/configs/nucleo-l476rg/nsh/defconfig b/configs/nucleo-l476rg/nsh/defconfig
index a79d8198373..b512cf5fe2a 100644
--- a/configs/nucleo-l476rg/nsh/defconfig
+++ b/configs/nucleo-l476rg/nsh/defconfig
@@ -620,7 +620,7 @@ CONFIG_USART2_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -661,7 +661,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/nucleo-l476rg/src/stm32_ajoystick.c b/configs/nucleo-l476rg/src/stm32_ajoystick.c
index 1eaf3db609b..6f49fd9823d 100644
--- a/configs/nucleo-l476rg/src/stm32_ajoystick.c
+++ b/configs/nucleo-l476rg/src/stm32_ajoystick.c
@@ -339,8 +339,8 @@ static void ajoy_enable(FAR const struct ajoy_lowerhalf_s *lower,
   flags = enter_critical_section();
   ajoy_disable();
 
-  illinfo("press: %02x release: %02x handler: %p arg: %p\n",
-          press, release, handler, arg);
+  iinfo("press: %02x release: %02x handler: %p arg: %p\n",
+        press, release, handler, arg);
 
   /* If no events are indicated or if no handler is provided, then this
    * must really be a request to disable interrupts.
@@ -371,8 +371,8 @@ static void ajoy_enable(FAR const struct ajoy_lowerhalf_s *lower,
                falling = ((press & bit) != 0);
                rising  = ((release & bit) != 0);
 
-               illinfo("GPIO %d: rising: %d falling: %d\n",
-                        i, rising, falling);
+               iinfo("GPIO %d: rising: %d falling: %d\n",
+                      i, rising, falling);
 
                (void)stm32_gpiosetevent(g_joygpio[i], rising, falling,
                                         true, ajoy_interrupt);
diff --git a/configs/nutiny-nuc120/nsh/defconfig b/configs/nutiny-nuc120/nsh/defconfig
index 25df02b98de..2091e561dc7 100644
--- a/configs/nutiny-nuc120/nsh/defconfig
+++ b/configs/nutiny-nuc120/nsh/defconfig
@@ -363,7 +363,6 @@ CONFIG_DISABLE_MOUNTPOINT=y
 # System Logging
 #
 
-# CONFIG_SYSLOG is not set
 
 #
 # Graphics Support
diff --git a/configs/olimex-efm32g880f128-stk/nsh/defconfig b/configs/olimex-efm32g880f128-stk/nsh/defconfig
index 2437444121d..c91ce75524e 100644
--- a/configs/olimex-efm32g880f128-stk/nsh/defconfig
+++ b/configs/olimex-efm32g880f128-stk/nsh/defconfig
@@ -451,7 +451,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 
 #
 # Graphics Support
diff --git a/configs/olimex-lpc-h3131/nsh/defconfig b/configs/olimex-lpc-h3131/nsh/defconfig
index 84f2cbd171b..071fc460955 100644
--- a/configs/olimex-lpc-h3131/nsh/defconfig
+++ b/configs/olimex-lpc-h3131/nsh/defconfig
@@ -440,7 +440,7 @@ CONFIG_UART_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -483,7 +483,6 @@ CONFIG_FAT_MAXFNAME=32
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/olimex-lpc1766stk/ftpc/defconfig b/configs/olimex-lpc1766stk/ftpc/defconfig
index b6d71ebeb14..4d497428175 100644
--- a/configs/olimex-lpc1766stk/ftpc/defconfig
+++ b/configs/olimex-lpc1766stk/ftpc/defconfig
@@ -600,7 +600,7 @@ CONFIG_UART0_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -757,7 +757,6 @@ CONFIG_FAT_MAXFNAME=32
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/olimex-lpc1766stk/hidkbd/defconfig b/configs/olimex-lpc1766stk/hidkbd/defconfig
index 56b10fb30f9..184f698cf5a 100644
--- a/configs/olimex-lpc1766stk/hidkbd/defconfig
+++ b/configs/olimex-lpc1766stk/hidkbd/defconfig
@@ -536,7 +536,7 @@ CONFIG_HIDKBD_ENCODED=y
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -574,7 +574,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/olimex-lpc1766stk/hidmouse/defconfig b/configs/olimex-lpc1766stk/hidmouse/defconfig
index 8a34f1b45a2..caf3e88bb3e 100644
--- a/configs/olimex-lpc1766stk/hidmouse/defconfig
+++ b/configs/olimex-lpc1766stk/hidmouse/defconfig
@@ -587,7 +587,7 @@ CONFIG_HIDMOUSE_THRESHY=12
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -745,7 +745,6 @@ CONFIG_FAT_MAXFNAME=32
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/olimex-lpc1766stk/nettest/defconfig b/configs/olimex-lpc1766stk/nettest/defconfig
index 3ea457fd886..a28a7732907 100644
--- a/configs/olimex-lpc1766stk/nettest/defconfig
+++ b/configs/olimex-lpc1766stk/nettest/defconfig
@@ -526,7 +526,7 @@ CONFIG_UART0_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -662,7 +662,6 @@ CONFIG_DISABLE_MOUNTPOINT=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/olimex-lpc1766stk/nsh/defconfig b/configs/olimex-lpc1766stk/nsh/defconfig
index 73b936fecaa..0d4bd8ed6b5 100644
--- a/configs/olimex-lpc1766stk/nsh/defconfig
+++ b/configs/olimex-lpc1766stk/nsh/defconfig
@@ -602,7 +602,7 @@ CONFIG_UART0_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -760,7 +760,6 @@ CONFIG_FAT_MAXFNAME=32
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/olimex-lpc1766stk/nx/defconfig b/configs/olimex-lpc1766stk/nx/defconfig
index 897a1b3dd4a..e4e545d18d7 100644
--- a/configs/olimex-lpc1766stk/nx/defconfig
+++ b/configs/olimex-lpc1766stk/nx/defconfig
@@ -539,7 +539,7 @@ CONFIG_UART0_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -573,7 +573,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/olimex-lpc1766stk/slip-httpd/defconfig b/configs/olimex-lpc1766stk/slip-httpd/defconfig
index a965a598b06..74d36bad226 100644
--- a/configs/olimex-lpc1766stk/slip-httpd/defconfig
+++ b/configs/olimex-lpc1766stk/slip-httpd/defconfig
@@ -486,7 +486,7 @@ CONFIG_UART1_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -622,7 +622,6 @@ CONFIG_FS_ROMFS=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/olimex-lpc1766stk/src/lpc17_hidmouse.c b/configs/olimex-lpc1766stk/src/lpc17_hidmouse.c
index 28df025df12..f583d526792 100644
--- a/configs/olimex-lpc1766stk/src/lpc17_hidmouse.c
+++ b/configs/olimex-lpc1766stk/src/lpc17_hidmouse.c
@@ -62,30 +62,10 @@
 #ifndef CONFIG_DEBUG_INPUT
 #  undef  ierr
 #  define ierr    uerr
-#  undef  illerr
-#  define illerr  ullerr
 #  undef  iinfo
 #  define iinfo   uinfo
-#  undef  illinfo
-#  define illinfo ullinfo
 #endif
 
-/****************************************************************************
- * Private Types
- ****************************************************************************/
-
-/****************************************************************************
- * Private Function Prototypes
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
diff --git a/configs/olimex-lpc1766stk/src/lpc17_lcd.c b/configs/olimex-lpc1766stk/src/lpc17_lcd.c
index d1bfc3481ba..2bde4f2ddf6 100644
--- a/configs/olimex-lpc1766stk/src/lpc17_lcd.c
+++ b/configs/olimex-lpc1766stk/src/lpc17_lcd.c
@@ -205,7 +205,7 @@ FAR struct lcd_dev_s *board_graphics_setup(unsigned int devno)
   spi = lpc17_sspbus_initialize(0);
   if (!spi)
     {
-      gllerr("ERROR: Failed to initialize SSP port 0\n");
+      gerr("ERROR: Failed to initialize SSP port 0\n");
     }
   else
     {
@@ -214,11 +214,11 @@ FAR struct lcd_dev_s *board_graphics_setup(unsigned int devno)
       dev = nokia_lcdinitialize(spi, devno);
       if (!dev)
         {
-          gllerr("ERROR: Failed to bind SSP port 0 to LCD %d: %d\n", devno);
+          gerr("ERROR: Failed to bind SSP port 0 to LCD %d: %d\n", devno);
         }
      else
         {
-          gllinfo("Bound SSP port 0 to LCD %d\n", devno);
+          ginfo("Bound SSP port 0 to LCD %d\n", devno);
 
           /* And turn the LCD on (CONFIG_LCD_MAXPOWER should be 1) */
 
diff --git a/configs/olimex-lpc1766stk/thttpd-binfs/defconfig b/configs/olimex-lpc1766stk/thttpd-binfs/defconfig
index d3cdafdb9d9..657ee240754 100644
--- a/configs/olimex-lpc1766stk/thttpd-binfs/defconfig
+++ b/configs/olimex-lpc1766stk/thttpd-binfs/defconfig
@@ -523,7 +523,7 @@ CONFIG_UART0_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -663,7 +663,6 @@ CONFIG_FS_UNIONFS=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/olimex-lpc1766stk/thttpd-nxflat/defconfig b/configs/olimex-lpc1766stk/thttpd-nxflat/defconfig
index 505ddb9bdb5..b917444cef7 100644
--- a/configs/olimex-lpc1766stk/thttpd-nxflat/defconfig
+++ b/configs/olimex-lpc1766stk/thttpd-nxflat/defconfig
@@ -515,7 +515,7 @@ CONFIG_UART0_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -653,7 +653,6 @@ CONFIG_FS_ROMFS=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/olimex-lpc1766stk/usbmsc/defconfig b/configs/olimex-lpc1766stk/usbmsc/defconfig
index 35d7141e1a1..946feef1a29 100644
--- a/configs/olimex-lpc1766stk/usbmsc/defconfig
+++ b/configs/olimex-lpc1766stk/usbmsc/defconfig
@@ -542,7 +542,7 @@ CONFIG_USBMSC_SCSI_STACKSIZE=2048
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -581,7 +581,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/olimex-lpc1766stk/usbserial/defconfig b/configs/olimex-lpc1766stk/usbserial/defconfig
index 8a2e409f588..a2ce7be2d38 100644
--- a/configs/olimex-lpc1766stk/usbserial/defconfig
+++ b/configs/olimex-lpc1766stk/usbserial/defconfig
@@ -567,7 +567,7 @@ CONFIG_PL2303_PRODUCTSTR="USBdev Serial"
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -601,7 +601,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/olimex-lpc1766stk/zmodem/defconfig b/configs/olimex-lpc1766stk/zmodem/defconfig
index 093cef7b7a1..676ad0c00e0 100644
--- a/configs/olimex-lpc1766stk/zmodem/defconfig
+++ b/configs/olimex-lpc1766stk/zmodem/defconfig
@@ -617,7 +617,7 @@ CONFIG_UART1_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -775,7 +775,6 @@ CONFIG_FAT_MAXFNAME=32
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/olimex-lpc2378/nsh/defconfig b/configs/olimex-lpc2378/nsh/defconfig
index 2670bc4dc06..772fd0cf022 100644
--- a/configs/olimex-lpc2378/nsh/defconfig
+++ b/configs/olimex-lpc2378/nsh/defconfig
@@ -453,7 +453,7 @@ CONFIG_UART2_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -493,7 +493,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/olimex-stm32-h405/src/stm32_usb.c b/configs/olimex-stm32-h405/src/stm32_usb.c
index d35c6aef3a6..7680452af07 100644
--- a/configs/olimex-stm32-h405/src/stm32_usb.c
+++ b/configs/olimex-stm32-h405/src/stm32_usb.c
@@ -110,7 +110,7 @@ void stm32_usbinitialize(void)
 #ifdef CONFIG_USBDEV
 void stm32_usbsuspend(FAR struct usbdev_s *dev, bool resume)
 {
-  ullinfo("resume: %d\n", resume);
+  uinfo("resume: %d\n", resume);
 }
 #endif
 
diff --git a/configs/olimex-stm32-h405/usbnsh/defconfig b/configs/olimex-stm32-h405/usbnsh/defconfig
index 33a729cbde8..7d516942327 100644
--- a/configs/olimex-stm32-h405/usbnsh/defconfig
+++ b/configs/olimex-stm32-h405/usbnsh/defconfig
@@ -892,7 +892,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/olimex-stm32-h407/nsh/defconfig b/configs/olimex-stm32-h407/nsh/defconfig
index 17aafd0c0b5..5bee1687107 100644
--- a/configs/olimex-stm32-h407/nsh/defconfig
+++ b/configs/olimex-stm32-h407/nsh/defconfig
@@ -772,7 +772,7 @@ CONFIG_USART2_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -821,7 +821,6 @@ CONFIG_FS_PROCFS=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/olimex-stm32-h407/src/stm32_usb.c b/configs/olimex-stm32-h407/src/stm32_usb.c
index 549820309c5..d948604a3b2 100644
--- a/configs/olimex-stm32-h407/src/stm32_usb.c
+++ b/configs/olimex-stm32-h407/src/stm32_usb.c
@@ -307,7 +307,7 @@ xcpt_t stm32_setup_overcurrent(xcpt_t handler)
 #ifdef CONFIG_USBDEV
 void stm32_usbsuspend(FAR struct usbdev_s *dev, bool resume)
 {
-  ullinfo("resume: %d\n", resume);
+  uinfo("resume: %d\n", resume);
 }
 #endif
 
diff --git a/configs/olimex-stm32-p107/nsh/defconfig b/configs/olimex-stm32-p107/nsh/defconfig
index 5f103a6e7e8..cbffc5aebbf 100644
--- a/configs/olimex-stm32-p107/nsh/defconfig
+++ b/configs/olimex-stm32-p107/nsh/defconfig
@@ -860,7 +860,7 @@ CONFIG_USART2_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -1010,7 +1010,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/olimex-stm32-p107/src/stm32_encx24j600.c b/configs/olimex-stm32-p107/src/stm32_encx24j600.c
index 37c46548b5f..c5ec3b96636 100644
--- a/configs/olimex-stm32-p107/src/stm32_encx24j600.c
+++ b/configs/olimex-stm32-p107/src/stm32_encx24j600.c
@@ -180,7 +180,7 @@ void up_netinitialize(void)
   spi = stm32_spibus_initialize(ENCX24J600_SPI_PORTNO);
   if (!spi)
     {
-      nllerr("ERROR: Failed to initialize SPI port %d\n", ENCX24J600_SPI_PORTNO);
+      nerr("ERROR: Failed to initialize SPI port %d\n", ENCX24J600_SPI_PORTNO);
       return;
     }
 
@@ -190,13 +190,13 @@ void up_netinitialize(void)
 
   if (ret < 0)
     {
-      nllerr("ERROR: Failed to bind SPI port %d ENCX24J600 device %d: %d\n",
-             ENCX24J600_SPI_PORTNO, ENCX24J600_DEVNO, ret);
+      nerr("ERROR: Failed to bind SPI port %d ENCX24J600 device %d: %d\n",
+           ENCX24J600_SPI_PORTNO, ENCX24J600_DEVNO, ret);
       return;
     }
 
-  nllinfo("Bound SPI port %d to ENCX24J600 device %d\n",
-          ENCX24J600_SPI_PORTNO, ENCX24J600_DEVNO);
+  ninfo("Bound SPI port %d to ENCX24J600 device %d\n",
+        ENCX24J600_SPI_PORTNO, ENCX24J600_DEVNO);
 }
 
 #endif /* CONFIG_ENCX24J600 */
diff --git a/configs/olimex-stm32-p207/nsh/defconfig b/configs/olimex-stm32-p207/nsh/defconfig
index 3ccfd8bfee1..e7daab78ec7 100644
--- a/configs/olimex-stm32-p207/nsh/defconfig
+++ b/configs/olimex-stm32-p207/nsh/defconfig
@@ -907,7 +907,7 @@ CONFIG_USBHOST_HAVE_ASYNCH=y
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -1057,7 +1057,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/olimex-stm32-p207/src/stm32_usb.c b/configs/olimex-stm32-p207/src/stm32_usb.c
index 492c7d26e8c..65198bf0041 100644
--- a/configs/olimex-stm32-p207/src/stm32_usb.c
+++ b/configs/olimex-stm32-p207/src/stm32_usb.c
@@ -311,7 +311,7 @@ void stm32_usbhost_vbusdrive(int iface, bool enable)
 #ifdef CONFIG_USBDEV
 void stm32_usbsuspend(FAR struct usbdev_s *dev, bool resume)
 {
-  ullinfo("resume: %d\n", resume);
+  uinfo("resume: %d\n", resume);
 }
 #endif
 
diff --git a/configs/olimex-strp711/nettest/defconfig b/configs/olimex-strp711/nettest/defconfig
index 07d292a7a9e..6ceeed73742 100644
--- a/configs/olimex-strp711/nettest/defconfig
+++ b/configs/olimex-strp711/nettest/defconfig
@@ -483,7 +483,7 @@ CONFIG_UART1_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -620,7 +620,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/olimex-strp711/nsh/defconfig b/configs/olimex-strp711/nsh/defconfig
index b6454a797fc..574f15003be 100644
--- a/configs/olimex-strp711/nsh/defconfig
+++ b/configs/olimex-strp711/nsh/defconfig
@@ -407,7 +407,6 @@ CONFIG_FS_FAT=y
 # System Logging
 #
 
-# CONFIG_SYSLOG is not set
 
 #
 # Graphics Support
diff --git a/configs/olimex-strp711/src/str71_enc28j60.c b/configs/olimex-strp711/src/str71_enc28j60.c
index ab49dc72b1d..73d16f1eadc 100644
--- a/configs/olimex-strp711/src/str71_enc28j60.c
+++ b/configs/olimex-strp711/src/str71_enc28j60.c
@@ -216,7 +216,7 @@ void up_netinitialize(void)
   spi = str71_spibus_initialize(ENC28J60_SPI_PORTNO);
   if (!spi)
     {
-      nllerr("ERROR: Failed to initialize SPI port %d\n", ENC28J60_SPI_PORTNO);
+      nerr("ERROR: Failed to initialize SPI port %d\n", ENC28J60_SPI_PORTNO);
       return;
     }
 
@@ -225,7 +225,7 @@ void up_netinitialize(void)
   ret = str71x_xticonfig(ENC28J60_IRQ, false);
   if (ret < 0)
     {
-      nllerr("ERROR: Failed configure interrupt for IRQ %d: %d\n", ENC28J60_IRQ, ret);
+      nerr("ERROR: Failed configure interrupt for IRQ %d: %d\n", ENC28J60_IRQ, ret);
       return;
     }
 
@@ -240,12 +240,12 @@ void up_netinitialize(void)
   ret = enc_initialize(spi, &g_enclower, ENC28J60_DEVNO);
   if (ret < 0)
     {
-      nllerr("ERROR: Failed to bind SPI port %d ENC28J60 device %d: %d\n",
-             ENC28J60_SPI_PORTNO, ENC28J60_DEVNO, ret);
+      nerr("ERROR: Failed to bind SPI port %d ENC28J60 device %d: %d\n",
+           ENC28J60_SPI_PORTNO, ENC28J60_DEVNO, ret);
       return;
     }
 
-  nllinfo("Bound SPI port %d to ENC28J60 device %d\n",
+  ninfo("Bound SPI port %d to ENC28J60 device %d\n",
         ENC28J60_SPI_PORTNO, ENC28J60_DEVNO);
 }
 #endif /* CONFIG_ENC28J60 */
diff --git a/configs/olimexino-stm32/can/defconfig b/configs/olimexino-stm32/can/defconfig
index 284fc55b6d3..e9b76b079ab 100644
--- a/configs/olimexino-stm32/can/defconfig
+++ b/configs/olimexino-stm32/can/defconfig
@@ -810,7 +810,7 @@ CONFIG_USART1_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -859,7 +859,6 @@ CONFIG_FS_FATTIME=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/olimexino-stm32/composite/defconfig b/configs/olimexino-stm32/composite/defconfig
index 4db6ca49fb5..7152e530fc0 100644
--- a/configs/olimexino-stm32/composite/defconfig
+++ b/configs/olimexino-stm32/composite/defconfig
@@ -898,7 +898,7 @@ CONFIG_USBMSC_SCSI_STACKSIZE=340
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -947,7 +947,6 @@ CONFIG_FS_FATTIME=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/olimexino-stm32/nsh/defconfig b/configs/olimexino-stm32/nsh/defconfig
index a5d78472372..096fdb9fc69 100644
--- a/configs/olimexino-stm32/nsh/defconfig
+++ b/configs/olimexino-stm32/nsh/defconfig
@@ -826,7 +826,7 @@ CONFIG_USART2_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -875,7 +875,6 @@ CONFIG_FS_FATTIME=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/olimexino-stm32/smallnsh/defconfig b/configs/olimexino-stm32/smallnsh/defconfig
index efcbbe0a484..0612dbbeed6 100644
--- a/configs/olimexino-stm32/smallnsh/defconfig
+++ b/configs/olimexino-stm32/smallnsh/defconfig
@@ -788,7 +788,7 @@ CONFIG_USART1_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -829,7 +829,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/olimexino-stm32/src/stm32_usbdev.c b/configs/olimexino-stm32/src/stm32_usbdev.c
index d810a55365b..dd0846ae48c 100644
--- a/configs/olimexino-stm32/src/stm32_usbdev.c
+++ b/configs/olimexino-stm32/src/stm32_usbdev.c
@@ -90,7 +90,7 @@ void stm32_usb_set_pwr_callback(xcpt_t pwr_changed_handler)
 
 void stm32_usbinitialize(void)
 {
-  ullinfo("called\n");
+  uinfo("called\n");
 
   /* USB Soft Connect Pullup */
 
@@ -129,5 +129,5 @@ int stm32_usbpullup(FAR struct usbdev_s *dev, bool enable)
 
 void stm32_usbsuspend(FAR struct usbdev_s *dev, bool resume)
 {
-  ullinfo("resume: %d\n", resume);
+  uinfo("resume: %d\n", resume);
 }
diff --git a/configs/olimexino-stm32/tiny/defconfig b/configs/olimexino-stm32/tiny/defconfig
index 6a8fbe3cf60..ffd31cfd9f5 100644
--- a/configs/olimexino-stm32/tiny/defconfig
+++ b/configs/olimexino-stm32/tiny/defconfig
@@ -790,7 +790,7 @@ CONFIG_USART1_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -826,7 +826,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/open1788/knsh/defconfig b/configs/open1788/knsh/defconfig
index b28e4e87bf9..bfb8b877005 100644
--- a/configs/open1788/knsh/defconfig
+++ b/configs/open1788/knsh/defconfig
@@ -522,7 +522,6 @@ CONFIG_FS_ROMFS=y
 # System Logging
 #
 
-# CONFIG_SYSLOG is not set
 
 #
 # Graphics Support
diff --git a/configs/open1788/nsh/defconfig b/configs/open1788/nsh/defconfig
index 00a7dd67111..aa96bf089c4 100644
--- a/configs/open1788/nsh/defconfig
+++ b/configs/open1788/nsh/defconfig
@@ -524,7 +524,7 @@ CONFIG_UART0_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -570,7 +570,6 @@ CONFIG_FS_ROMFS=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/open1788/nxlines/defconfig b/configs/open1788/nxlines/defconfig
index 22e10f17cda..4ebc2d874ed 100644
--- a/configs/open1788/nxlines/defconfig
+++ b/configs/open1788/nxlines/defconfig
@@ -424,7 +424,6 @@ CONFIG_FS_ROMFS=y
 # System Logging
 #
 
-# CONFIG_SYSLOG is not set
 
 #
 # Graphics Support
diff --git a/configs/p112/ostest/defconfig b/configs/p112/ostest/defconfig
index 12359147a4d..21e30346746 100644
--- a/configs/p112/ostest/defconfig
+++ b/configs/p112/ostest/defconfig
@@ -306,7 +306,6 @@ CONFIG_DEV_LOWCONSOLE=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 
 #
 # Graphics Support
diff --git a/configs/pcblogic-pic32mx/nsh/defconfig b/configs/pcblogic-pic32mx/nsh/defconfig
index 3585765cbef..78547b01121 100644
--- a/configs/pcblogic-pic32mx/nsh/defconfig
+++ b/configs/pcblogic-pic32mx/nsh/defconfig
@@ -530,7 +530,7 @@ CONFIG_UART1_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -570,7 +570,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/pcduino-a10/nsh/defconfig b/configs/pcduino-a10/nsh/defconfig
index 0d5c40af7a7..158c989a87a 100644
--- a/configs/pcduino-a10/nsh/defconfig
+++ b/configs/pcduino-a10/nsh/defconfig
@@ -513,7 +513,6 @@ CONFIG_FAT_MAXFNAME=32
 # System Logging
 #
 
-# CONFIG_SYSLOG is not set
 
 #
 # Graphics Support
diff --git a/configs/pcduino-a10/nsh/pcduino-140107.patch b/configs/pcduino-a10/nsh/pcduino-140107.patch
index 1d0b6651844..2dcd324a7d8 100644
--- a/configs/pcduino-a10/nsh/pcduino-140107.patch
+++ b/configs/pcduino-a10/nsh/pcduino-140107.patch
@@ -6,14 +6,14 @@ index 3cc6323..ad42790 100644
     * for all IO regions (Including the vector region).
     */
  
-+lowsyslog(LOG_INFO, "Calling a1x_setupmappings\n"); // REMOVE ME
++syslog(LOG_INFO, "Calling a1x_setupmappings\n"); // REMOVE ME
    a1x_setupmappings();
  
    /* Provide a special mapping for the IRAM interrupt vector positioned in
     * high memory.
     */
  
-+lowsyslog(LOG_INFO, "Calling a1x_vectormapping\n"); // REMOVE ME
++syslog(LOG_INFO, "Calling a1x_vectormapping\n"); // REMOVE ME
    a1x_vectormapping();
  
  #endif /* CONFIG_ARCH_ROMPGTABLE */
@@ -21,19 +21,19 @@ index 3cc6323..ad42790 100644
     * arm_vector.S
     */
  
-+lowsyslog(LOG_INFO, "Calling a1x_copyvectorblock\n"); // REMOVE ME
++syslog(LOG_INFO, "Calling a1x_copyvectorblock\n"); // REMOVE ME
    a1x_copyvectorblock();
  
    /* Initialize the FPU */
  
  #ifdef CONFIG_ARCH_FPU
-+lowsyslog(LOG_INFO, "Calling arm_fpuconfig\n"); // REMOVE ME
++syslog(LOG_INFO, "Calling arm_fpuconfig\n"); // REMOVE ME
    arm_fpuconfig();
  #endif
  
    /* Perform common, low-level chip initialization (might do nothing) */
  
-+lowsyslog(LOG_INFO, "Calling a1x_lowsetup\n"); // REMOVE ME
++syslog(LOG_INFO, "Calling a1x_lowsetup\n"); // REMOVE ME
    a1x_lowsetup();
  
    /* Perform early serial initialization if we are going to use the serial
@@ -41,7 +41,7 @@ index 3cc6323..ad42790 100644
     */
  
  #ifdef USE_EARLYSERIALINIT
-+lowsyslog(LOG_INFO, "Calling up_earlyserialinit\n"); // REMOVE ME
++syslog(LOG_INFO, "Calling up_earlyserialinit\n"); // REMOVE ME
    up_earlyserialinit();
  #endif
  
@@ -49,7 +49,7 @@ index 3cc6323..ad42790 100644
     */
  
  #ifdef CONFIG_BUILD_PROTECTED
-+lowsyslog(LOG_INFO, "Calling a1x_userspace\n"); // REMOVE ME
++syslog(LOG_INFO, "Calling a1x_userspace\n"); // REMOVE ME
    a1x_userspace();
  #endif
  
@@ -57,9 +57,9 @@ index 3cc6323..ad42790 100644
     * - Configuration of board specific resources (PIOs, LEDs, etc).
     */
  
-+lowsyslog(LOG_INFO, "Calling a1x_boardinitialize\n"); // REMOVE ME
++syslog(LOG_INFO, "Calling a1x_boardinitialize\n"); // REMOVE ME
    a1x_boardinitialize();
-+lowsyslog(LOG_INFO, "Returning\n"); // REMOVE ME
++syslog(LOG_INFO, "Returning\n"); // REMOVE ME
  }
 diff --git a/nuttx/arch/arm/src/armv7-a/arm_head.S b/nuttx/arch/arm/src/armv7-a/arm_head.S
 index bce82d5..924bd24 100644
diff --git a/configs/pic32mx-starterkit/README.txt b/configs/pic32mx-starterkit/README.txt
index 196efadda95..62f1309a62e 100644
--- a/configs/pic32mx-starterkit/README.txt
+++ b/configs/pic32mx-starterkit/README.txt
@@ -1137,7 +1137,6 @@ Where <subdir> is one of the following:
 
     3. The RAM log is enabled"
 
-      CONFIG_SYSLOG=y             : Enables the System Logging feature.
       CONFIG_RAMLOG=y             : Enable the RAM-based logging feature.
       CONFIG_RAMLOG_CONSOLE=n     : (there is no default console device)
       CONFIG_RAMLOG_SYSLOG=y      : This enables the RAM-based logger as the
diff --git a/configs/pic32mx-starterkit/nsh/defconfig b/configs/pic32mx-starterkit/nsh/defconfig
index 9d95806d46d..c31f98bf9bd 100644
--- a/configs/pic32mx-starterkit/nsh/defconfig
+++ b/configs/pic32mx-starterkit/nsh/defconfig
@@ -569,7 +569,7 @@ CONFIG_UART1_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -614,7 +614,6 @@ CONFIG_FAT_MAXFNAME=32
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/pic32mx-starterkit/nsh2/defconfig b/configs/pic32mx-starterkit/nsh2/defconfig
index 168b1157b54..e0d59d64c8d 100644
--- a/configs/pic32mx-starterkit/nsh2/defconfig
+++ b/configs/pic32mx-starterkit/nsh2/defconfig
@@ -635,7 +635,7 @@ CONFIG_RAMLOG_BUFSIZE=16384
 # CONFIG_RAMLOG_CRLF is not set
 CONFIG_RAMLOG_NONBLOCKING=y
 CONFIG_RAMLOG_NPOLLWAITERS=4
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -792,7 +792,6 @@ CONFIG_FAT_MAXFNAME=32
 #
 # System Logging
 #
-CONFIG_SYSLOG=y
 # CONFIG_SYSLOG_TIMESTAMP is not set
 # CONFIG_SYSLOG_CHAR is not set
 
diff --git a/configs/pic32mx7mmb/nsh/defconfig b/configs/pic32mx7mmb/nsh/defconfig
index fd10897fb83..0e50acd4deb 100644
--- a/configs/pic32mx7mmb/nsh/defconfig
+++ b/configs/pic32mx7mmb/nsh/defconfig
@@ -700,7 +700,7 @@ CONFIG_USBMSC_SCSI_STACKSIZE=2048
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -857,7 +857,6 @@ CONFIG_FAT_MAXFNAME=32
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/pic32mz-starterkit/nsh/defconfig b/configs/pic32mz-starterkit/nsh/defconfig
index 3662e48eeb2..957e7a04fd4 100644
--- a/configs/pic32mz-starterkit/nsh/defconfig
+++ b/configs/pic32mz-starterkit/nsh/defconfig
@@ -496,7 +496,7 @@ CONFIG_UART1_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -541,7 +541,6 @@ CONFIG_FAT_MAXFNAME=32
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/pirelli_dpl10/nsh_highram/defconfig b/configs/pirelli_dpl10/nsh_highram/defconfig
index ad786886a86..d538ebe7f3e 100644
--- a/configs/pirelli_dpl10/nsh_highram/defconfig
+++ b/configs/pirelli_dpl10/nsh_highram/defconfig
@@ -414,7 +414,7 @@ CONFIG_OTHER_SERIAL_CONSOLE=y
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -453,7 +453,6 @@ CONFIG_OTHER_SERIAL_CONSOLE=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/qemu-i486/nsh/defconfig b/configs/qemu-i486/nsh/defconfig
index 7f88c5286b0..a7c7b5d4e52 100644
--- a/configs/qemu-i486/nsh/defconfig
+++ b/configs/qemu-i486/nsh/defconfig
@@ -339,7 +339,6 @@ CONFIG_FS_ROMFS=y
 # System Logging
 #
 
-# CONFIG_SYSLOG is not set
 
 #
 # Graphics Support
diff --git a/configs/qemu-i486/ostest/defconfig b/configs/qemu-i486/ostest/defconfig
index 9ada6498abf..5e8d9f74c1f 100644
--- a/configs/qemu-i486/ostest/defconfig
+++ b/configs/qemu-i486/ostest/defconfig
@@ -316,7 +316,6 @@ CONFIG_FS_FAT=y
 # System Logging
 #
 
-# CONFIG_SYSLOG is not set
 
 #
 # Graphics Support
diff --git a/configs/rgmp/arm/default/defconfig b/configs/rgmp/arm/default/defconfig
index 8495938b1b7..6e6f76deeb9 100644
--- a/configs/rgmp/arm/default/defconfig
+++ b/configs/rgmp/arm/default/defconfig
@@ -365,7 +365,6 @@ CONFIG_NET_ETHERNET=y
 # System Logging
 #
 
-# CONFIG_SYSLOG is not set
 
 #
 # Graphics Support
diff --git a/configs/rgmp/arm/nsh/defconfig b/configs/rgmp/arm/nsh/defconfig
index 90f20031956..c6466fabca1 100644
--- a/configs/rgmp/arm/nsh/defconfig
+++ b/configs/rgmp/arm/nsh/defconfig
@@ -387,7 +387,6 @@ CONFIG_NET_ETHERNET=y
 # System Logging
 #
 
-# CONFIG_SYSLOG is not set
 
 #
 # Graphics Support
diff --git a/configs/rgmp/x86/cxxtest/defconfig b/configs/rgmp/x86/cxxtest/defconfig
index d9ba51f827d..ddda0c478c2 100644
--- a/configs/rgmp/x86/cxxtest/defconfig
+++ b/configs/rgmp/x86/cxxtest/defconfig
@@ -394,7 +394,6 @@ CONFIG_NET_ETHERNET=y
 # System Logging
 #
 
-# CONFIG_SYSLOG is not set
 
 #
 # Graphics Support
diff --git a/configs/rgmp/x86/default/defconfig b/configs/rgmp/x86/default/defconfig
index 5d6cb9c5f0c..1416b238937 100644
--- a/configs/rgmp/x86/default/defconfig
+++ b/configs/rgmp/x86/default/defconfig
@@ -373,7 +373,6 @@ CONFIG_NET_ETHERNET=y
 # System Logging
 #
 
-# CONFIG_SYSLOG is not set
 
 #
 # Graphics Support
diff --git a/configs/rgmp/x86/helloxx/defconfig b/configs/rgmp/x86/helloxx/defconfig
index bc8d365d29d..b581016e8c0 100644
--- a/configs/rgmp/x86/helloxx/defconfig
+++ b/configs/rgmp/x86/helloxx/defconfig
@@ -394,7 +394,6 @@ CONFIG_NET_ETHERNET=y
 # System Logging
 #
 
-# CONFIG_SYSLOG is not set
 
 #
 # Graphics Support
diff --git a/configs/rgmp/x86/nsh/defconfig b/configs/rgmp/x86/nsh/defconfig
index 7bd35b1c0d6..4df54001cb7 100644
--- a/configs/rgmp/x86/nsh/defconfig
+++ b/configs/rgmp/x86/nsh/defconfig
@@ -395,7 +395,6 @@ CONFIG_NET_ETHERNET=y
 # System Logging
 #
 
-# CONFIG_SYSLOG is not set
 
 #
 # Graphics Support
diff --git a/configs/sabre-6quad/README.txt b/configs/sabre-6quad/README.txt
index 965d2d908e4..f94614ae63d 100644
--- a/configs/sabre-6quad/README.txt
+++ b/configs/sabre-6quad/README.txt
@@ -95,34 +95,11 @@ Status
     -CONFIG_RAMLOG_BUFSIZE=16384
     -CONFIG_RAMLOG_NONBLOCKING=y
     -CONFIG_RAMLOG_NPOLLWAITERS=4
-    -CONFIG_SYSLOG=y
 
   I would also disable debug output from CPU0 so that I could better see the
-  debug output from CPU1:
+  debug output from CPU1.  In drivers/syslog/vsyslog.c:
 
-    $ diff -u libc/syslog/lib_lowsyslog.c libc/syslog/lib_lowsyslog.c.SAVE
-    --- libc/syslog/lib_lowsyslog.c 2016-05-22 14:56:35.130096500 -0600
-    +++ libc/syslog/lib_lowsyslog.c.SAVE    2016-05-20 13:36:22.588330100 -0600
-    @@ -126,7 +126,0 @@
-     {
-       va_list ap;
-       int ret;
     +if (up_cpu_index() == 0) return 17; // REMOVE ME
-      
-       /* Let lowvsyslog do the work */
-    
-       va_start(ap, fmt);
-  
-    $ diff -u libc/syslog/lib_syslog.c libc/syslog/lib_syslog.c.SAVE
-    --- libc/syslog/lib_syslog.c    2016-05-22 14:56:35.156098100 -0600
-    +++ libc/syslog/lib_syslog.c.SAVE       2016-05-20 13:36:15.331284000 -0600
-    @@ -192,6 +192,7 @@
-     {
-       va_list ap;
-       int ret;
-    +if (up_cpu_index() == 0) return 17; // REMOVE ME
-    
-       /* Let vsyslog do the work */
 
 Platform Features
 =================
@@ -653,7 +630,6 @@ Configuration sub-directories
        RAMLOG and will not be visible unless you use the nsh 'dmesg'
        command.  To disable this RAMLOG feature, disable the following:
 
-       File Systems:    CONFIG_SYSLOG
        Device Drivers:  CONFIG_RAMLOG
 
 
diff --git a/configs/sabre-6quad/nsh/defconfig b/configs/sabre-6quad/nsh/defconfig
index 5d95de0c179..ad80c2600a6 100644
--- a/configs/sabre-6quad/nsh/defconfig
+++ b/configs/sabre-6quad/nsh/defconfig
@@ -495,7 +495,7 @@ CONFIG_RAMLOG_BUFSIZE=16384
 # CONFIG_RAMLOG_CRLF is not set
 CONFIG_RAMLOG_NONBLOCKING=y
 CONFIG_RAMLOG_NPOLLWAITERS=4
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -544,7 +544,6 @@ CONFIG_FS_PROCFS=y
 #
 # System Logging
 #
-CONFIG_SYSLOG=y
 # CONFIG_SYSLOG_TIMESTAMP is not set
 # CONFIG_SYSLOG_CHAR is not set
 
diff --git a/configs/sabre-6quad/smp/defconfig b/configs/sabre-6quad/smp/defconfig
index 5e8afbadb13..22281fb345f 100644
--- a/configs/sabre-6quad/smp/defconfig
+++ b/configs/sabre-6quad/smp/defconfig
@@ -502,7 +502,7 @@ CONFIG_RAMLOG_BUFSIZE=16384
 # CONFIG_RAMLOG_CRLF is not set
 CONFIG_RAMLOG_NONBLOCKING=y
 CONFIG_RAMLOG_NPOLLWAITERS=4
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -551,7 +551,6 @@ CONFIG_FS_PROCFS=y
 #
 # System Logging
 #
-CONFIG_SYSLOG=y
 # CONFIG_SYSLOG_TIMESTAMP is not set
 # CONFIG_SYSLOG_CHAR is not set
 
diff --git a/configs/sabre-6quad/src/imx_bringup.c b/configs/sabre-6quad/src/imx_bringup.c
index 5bb167a90b4..13f1742c154 100644
--- a/configs/sabre-6quad/src/imx_bringup.c
+++ b/configs/sabre-6quad/src/imx_bringup.c
@@ -44,22 +44,6 @@
 
 #include "sabre-6quad.h"
 
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/* Debug ********************************************************************/
-
-#ifdef CONFIG_BOARD_INITIALIZE
-#  define SYSLOG  _llerr
-#else
-#  define SYSLOG  _err
-#endif
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
diff --git a/configs/sam3u-ek/knsh/defconfig b/configs/sam3u-ek/knsh/defconfig
index 9a56064aa0f..561c67f6d8c 100644
--- a/configs/sam3u-ek/knsh/defconfig
+++ b/configs/sam3u-ek/knsh/defconfig
@@ -564,7 +564,7 @@ CONFIG_UART0_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -610,7 +610,6 @@ CONFIG_FS_FAT=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/sam3u-ek/nsh/defconfig b/configs/sam3u-ek/nsh/defconfig
index 0f23cf44ca3..14d7c69f169 100644
--- a/configs/sam3u-ek/nsh/defconfig
+++ b/configs/sam3u-ek/nsh/defconfig
@@ -551,7 +551,7 @@ CONFIG_UART0_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -598,7 +598,6 @@ CONFIG_FS_FAT=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/sam3u-ek/nx/defconfig b/configs/sam3u-ek/nx/defconfig
index f8f9a7ffe84..e9161d210ed 100644
--- a/configs/sam3u-ek/nx/defconfig
+++ b/configs/sam3u-ek/nx/defconfig
@@ -578,7 +578,7 @@ CONFIG_UART0_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -612,7 +612,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/sam3u-ek/nxwm/defconfig b/configs/sam3u-ek/nxwm/defconfig
index da3c51728a4..1a34f4d18e8 100644
--- a/configs/sam3u-ek/nxwm/defconfig
+++ b/configs/sam3u-ek/nxwm/defconfig
@@ -626,7 +626,7 @@ CONFIG_UART0_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -666,7 +666,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/sam3u-ek/src/sam_usbdev.c b/configs/sam3u-ek/src/sam_usbdev.c
index ae3d3ba68e3..08a6c57bc86 100644
--- a/configs/sam3u-ek/src/sam_usbdev.c
+++ b/configs/sam3u-ek/src/sam_usbdev.c
@@ -75,5 +75,5 @@
 
 void sam_usbsuspend(FAR struct usbdev_s *dev, bool resume)
 {
-  ullinfo("resume: %d\n", resume);
+  uinfo("resume: %d\n", resume);
 }
diff --git a/configs/sam4e-ek/README.txt b/configs/sam4e-ek/README.txt
index 41694bc2750..6de1817b015 100644
--- a/configs/sam4e-ek/README.txt
+++ b/configs/sam4e-ek/README.txt
@@ -1554,7 +1554,6 @@ Configurations
        the system logging device:
 
            File Systems -> Advanced SYSLOG Features
-             CONFIG_SYSLOG=y               : Enable output to syslog, not console
              CONFIG_SYSLOG_CHAR=y          : Use a character device for system logging
              CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" : UART0 will be /dev/ttyS0
 
diff --git a/configs/sam4e-ek/nsh/defconfig b/configs/sam4e-ek/nsh/defconfig
index e6d405873f8..aa801205f42 100644
--- a/configs/sam4e-ek/nsh/defconfig
+++ b/configs/sam4e-ek/nsh/defconfig
@@ -701,7 +701,7 @@ CONFIG_USART1_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -861,7 +861,6 @@ CONFIG_FAT_MAXFNAME=32
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/sam4e-ek/nxwm/defconfig b/configs/sam4e-ek/nxwm/defconfig
index 2ef7b2a98f7..e6b54f6b127 100644
--- a/configs/sam4e-ek/nxwm/defconfig
+++ b/configs/sam4e-ek/nxwm/defconfig
@@ -759,7 +759,7 @@ CONFIG_USART1_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -918,7 +918,6 @@ CONFIG_FAT_MAXFNAME=32
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/sam4e-ek/src/sam_ethernet.c b/configs/sam4e-ek/src/sam_ethernet.c
index 1e2948da575..b15cf06107a 100644
--- a/configs/sam4e-ek/src/sam_ethernet.c
+++ b/configs/sam4e-ek/src/sam_ethernet.c
@@ -77,16 +77,10 @@
 #  define phyerr    _err
 #  define phywarn   _warn
 #  define phyinfo   _info
-#  define phyllerr  _llerr
-#  define phyllwarn _llwarn
-#  define phyllinfo _llinfo
 #else
 #  define phyerr(x...)
 #  define phywarn(x...)
 #  define phyinfo(x...)
-#  define phyllerr(x...)
-#  define phyllwarn(x...)
-#  define phyllinfo(x...)
 #endif
 
 /************************************************************************************
diff --git a/configs/sam4e-ek/src/sam_hsmci.c b/configs/sam4e-ek/src/sam_hsmci.c
index b10dc5c2fc6..e799cf0d1b9 100644
--- a/configs/sam4e-ek/src/sam_hsmci.c
+++ b/configs/sam4e-ek/src/sam_hsmci.c
@@ -194,7 +194,7 @@ bool sam_cardinserted(int slotno)
   /* Get the state of the GPIO pin */
 
   removed = sam_gpioread(GPIO_MCI_CD);
-  fllinfo("Slot %d inserted: %s\n", slotno, removed ? "NO" : "YES");
+  finfo("Slot %d inserted: %s\n", slotno, removed ? "NO" : "YES");
 
   return !removed;
 }
diff --git a/configs/sam4e-ek/src/sam_udp.c b/configs/sam4e-ek/src/sam_udp.c
index d275ffef740..8a2213f9d2a 100644
--- a/configs/sam4e-ek/src/sam_udp.c
+++ b/configs/sam4e-ek/src/sam_udp.c
@@ -83,5 +83,5 @@
 
 void sam_udp_suspend(FAR struct usbdev_s *dev, bool resume)
 {
-  ullinfo("resume: %d\n", resume);
+  uinfo("resume: %d\n", resume);
 }
diff --git a/configs/sam4e-ek/usbnsh/defconfig b/configs/sam4e-ek/usbnsh/defconfig
index 80736c4caab..fe7aa0f9a3f 100644
--- a/configs/sam4e-ek/usbnsh/defconfig
+++ b/configs/sam4e-ek/usbnsh/defconfig
@@ -898,7 +898,6 @@ CONFIG_FAT_MAXFNAME=32
 #
 # System Logging
 #
-CONFIG_SYSLOG=y
 # CONFIG_SYSLOG_TIMESTAMP is not set
 CONFIG_SYSLOG_CHAR=y
 CONFIG_SYSLOG_DEVPATH="/dev/ttyS0"
diff --git a/configs/sam4l-xplained/nsh/defconfig b/configs/sam4l-xplained/nsh/defconfig
index 60170ad2aa3..5857be09958 100644
--- a/configs/sam4l-xplained/nsh/defconfig
+++ b/configs/sam4l-xplained/nsh/defconfig
@@ -567,7 +567,7 @@ CONFIG_USART0_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -608,7 +608,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/sam4s-xplained-pro/nsh/defconfig b/configs/sam4s-xplained-pro/nsh/defconfig
index e796be0db2a..1758207123a 100644
--- a/configs/sam4s-xplained-pro/nsh/defconfig
+++ b/configs/sam4s-xplained-pro/nsh/defconfig
@@ -687,7 +687,7 @@ CONFIG_CDCACM_PRODUCTSTR="CDC/ACM Serial"
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -743,7 +743,6 @@ CONFIG_FS_PROCFS=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/sam4s-xplained-pro/src/sam_hsmci.c b/configs/sam4s-xplained-pro/src/sam_hsmci.c
index d01a199815a..e71e948de82 100644
--- a/configs/sam4s-xplained-pro/src/sam_hsmci.c
+++ b/configs/sam4s-xplained-pro/src/sam_hsmci.c
@@ -207,7 +207,7 @@ bool sam_cardinserted(int slotno)
   /* Get the state of the GPIO pin */
 
   removed = sam_gpioread(GPIO_MCI_CD);
-  fllinfo("Slot %d inserted: %s\n", slotno, removed ? "NO" : "YES");
+  finfo("Slot %d inserted: %s\n", slotno, removed ? "NO" : "YES");
 
   return !removed;
 }
diff --git a/configs/sam4s-xplained-pro/src/sam_udp.c b/configs/sam4s-xplained-pro/src/sam_udp.c
index 2f83c9d12fe..13c1f72e02f 100644
--- a/configs/sam4s-xplained-pro/src/sam_udp.c
+++ b/configs/sam4s-xplained-pro/src/sam_udp.c
@@ -84,5 +84,5 @@
 
 void sam_udp_suspend(FAR struct usbdev_s *dev, bool resume)
 {
-  ullinfo("resume: %d\n", resume);
+  uinfo("resume: %d\n", resume);
 }
diff --git a/configs/sam4s-xplained/nsh/defconfig b/configs/sam4s-xplained/nsh/defconfig
index 18055fb1196..1442a817eb3 100644
--- a/configs/sam4s-xplained/nsh/defconfig
+++ b/configs/sam4s-xplained/nsh/defconfig
@@ -547,7 +547,7 @@ CONFIG_UART1_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -582,7 +582,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/sama5d2-xult/README.txt b/configs/sama5d2-xult/README.txt
index 9af903ada86..8f11cc1db50 100644
--- a/configs/sama5d2-xult/README.txt
+++ b/configs/sama5d2-xult/README.txt
@@ -1032,7 +1032,6 @@ Configurations
        configuration settings are summarized below:
 
        File System:
-       CONFIG_SYSLOG=y             : Enables the System Logging feature.
 
        Device Drivers:
        CONFIG_RAMLOG=y             : Enable the RAM-based logging feature.
diff --git a/configs/sama5d2-xult/nsh/defconfig b/configs/sama5d2-xult/nsh/defconfig
index dcd38abd685..b1d1190fc0a 100644
--- a/configs/sama5d2-xult/nsh/defconfig
+++ b/configs/sama5d2-xult/nsh/defconfig
@@ -655,7 +655,7 @@ CONFIG_RAMLOG_BUFSIZE=16384
 # CONFIG_RAMLOG_CRLF is not set
 CONFIG_RAMLOG_NONBLOCKING=y
 CONFIG_RAMLOG_NPOLLWAITERS=4
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -711,7 +711,6 @@ CONFIG_FS_PROCFS=y
 #
 # System Logging
 #
-CONFIG_SYSLOG=y
 # CONFIG_SYSLOG_TIMESTAMP is not set
 # CONFIG_SYSLOG_CHAR is not set
 
diff --git a/configs/sama5d2-xult/src/sam_bringup.c b/configs/sama5d2-xult/src/sam_bringup.c
index eb026524411..6d758e5f8ad 100644
--- a/configs/sama5d2-xult/src/sam_bringup.c
+++ b/configs/sama5d2-xult/src/sam_bringup.c
@@ -45,16 +45,6 @@
 
 #include "sama5d2-xult.h"
 
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-#ifdef CONFIG_BOARD_INITIALIZE
-#  define SYSLOG  _llerr
-#else
-#  define SYSLOG  _err
-#endif
-
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
@@ -77,8 +67,8 @@ int sam_bringup(void)
   ret = mount(NULL, SAMA5_PROCFS_MOUNTPOINT, "procfs", 0, NULL);
   if (ret < 0)
     {
-      syslog(LOG_ERR, "ERROR: Failed to mount procfs at %s: %d\n",
-             SAMA5_PROCFS_MOUNTPOINT, ret);
+      _err("ERROR: Failed to mount procfs at %s: %d\n",
+           SAMA5_PROCFS_MOUNTPOINT, ret);
     }
 #endif
 
diff --git a/configs/sama5d3-xplained/bridge/defconfig b/configs/sama5d3-xplained/bridge/defconfig
index 21cbf729dec..53e4a4acef2 100644
--- a/configs/sama5d3-xplained/bridge/defconfig
+++ b/configs/sama5d3-xplained/bridge/defconfig
@@ -653,7 +653,7 @@ CONFIG_OTHER_SERIAL_CONSOLE=y
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -799,7 +799,6 @@ CONFIG_FAT_MAXFNAME=32
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/sama5d3-xplained/nsh/defconfig b/configs/sama5d3-xplained/nsh/defconfig
index b096817b15e..56c0bf48e8f 100644
--- a/configs/sama5d3-xplained/nsh/defconfig
+++ b/configs/sama5d3-xplained/nsh/defconfig
@@ -571,7 +571,7 @@ CONFIG_OTHER_SERIAL_CONSOLE=y
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -627,7 +627,6 @@ CONFIG_FS_PROCFS=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/sama5d3-xplained/src/sam_ajoystick.c b/configs/sama5d3-xplained/src/sam_ajoystick.c
index f068cf2ef95..15b53d3f70d 100644
--- a/configs/sama5d3-xplained/src/sam_ajoystick.c
+++ b/configs/sama5d3-xplained/src/sam_ajoystick.c
@@ -301,8 +301,8 @@ static void ajoy_enable(FAR const struct ajoy_lowerhalf_s *lower,
   flags = enter_critical_section();
   ajoy_disable();
 
-  illinfo("press: %02x release: %02x handler: %p arg: %p\n",
-          press, release, handler, arg);
+  iinfo("press: %02x release: %02x handler: %p arg: %p\n",
+        press, release, handler, arg);
 
   /* If no events are indicated or if no handler is provided, then this
    * must really be a request to disable interrupts.
diff --git a/configs/sama5d3-xplained/src/sam_ethernet.c b/configs/sama5d3-xplained/src/sam_ethernet.c
index 5f38d395b1f..8505711302a 100644
--- a/configs/sama5d3-xplained/src/sam_ethernet.c
+++ b/configs/sama5d3-xplained/src/sam_ethernet.c
@@ -87,16 +87,10 @@
 #  define phyerr    _err
 #  define phywarn   _warn
 #  define phyinfo   _info
-#  define phyllerr  _llerr
-#  define phyllwarn _llwarn
-#  define phyllinfo _llinfo
 #else
 #  define phyerr(x...)
 #  define phywarn(x...)
 #  define phyinfo(x...)
-#  define phyllerr(x...)
-#  define phyllwarn(x...)
-#  define phyllinfo(x...)
 #endif
 
 /************************************************************************************
diff --git a/configs/sama5d3-xplained/src/sam_hsmci.c b/configs/sama5d3-xplained/src/sam_hsmci.c
index cbb8e3b654c..27db3addacf 100644
--- a/configs/sama5d3-xplained/src/sam_hsmci.c
+++ b/configs/sama5d3-xplained/src/sam_hsmci.c
@@ -154,7 +154,7 @@ bool sam_cardinserted_internal(struct sam_hsmci_state_s *state)
   /* Get the state of the PIO pin */
 
   inserted = sam_pioread(state->pincfg);
-  fllinfo("Slot %d inserted: %s\n", state->slotno, inserted ? "NO" : "YES");
+  finfo("Slot %d inserted: %s\n", state->slotno, inserted ? "NO" : "YES");
   return !inserted;
 }
 
diff --git a/configs/sama5d3-xplained/src/sam_usb.c b/configs/sama5d3-xplained/src/sam_usb.c
index 98aafc0dbb3..b04c4eeb2ee 100644
--- a/configs/sama5d3-xplained/src/sam_usb.c
+++ b/configs/sama5d3-xplained/src/sam_usb.c
@@ -546,7 +546,7 @@ xcpt_t sam_setup_overcurrent(xcpt_t handler)
 #ifdef CONFIG_USBDEV
 void sam_usbsuspend(FAR struct usbdev_s *dev, bool resume)
 {
-  ullinfo("resume: %d\n", resume);
+  uinfo("resume: %d\n", resume);
 }
 #endif
 
diff --git a/configs/sama5d3x-ek/demo/defconfig b/configs/sama5d3x-ek/demo/defconfig
index a25290cbec5..405ad536c46 100644
--- a/configs/sama5d3x-ek/demo/defconfig
+++ b/configs/sama5d3x-ek/demo/defconfig
@@ -760,7 +760,7 @@ CONFIG_HIDKBD_BUFSIZE=64
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -817,7 +817,6 @@ CONFIG_FS_PROCFS=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/sama5d3x-ek/hello/defconfig b/configs/sama5d3x-ek/hello/defconfig
index e1677b94440..d51c6393db0 100644
--- a/configs/sama5d3x-ek/hello/defconfig
+++ b/configs/sama5d3x-ek/hello/defconfig
@@ -565,7 +565,7 @@ CONFIG_USART1_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -599,7 +599,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/sama5d3x-ek/norboot/defconfig b/configs/sama5d3x-ek/norboot/defconfig
index f6888c8649c..18868fd3135 100644
--- a/configs/sama5d3x-ek/norboot/defconfig
+++ b/configs/sama5d3x-ek/norboot/defconfig
@@ -579,7 +579,7 @@ CONFIG_USART1_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -613,7 +613,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/sama5d3x-ek/nsh/defconfig b/configs/sama5d3x-ek/nsh/defconfig
index cd3c6e0256a..34bd0f3f84f 100644
--- a/configs/sama5d3x-ek/nsh/defconfig
+++ b/configs/sama5d3x-ek/nsh/defconfig
@@ -584,7 +584,7 @@ CONFIG_USART1_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -640,7 +640,6 @@ CONFIG_FS_PROCFS=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/sama5d3x-ek/nx/defconfig b/configs/sama5d3x-ek/nx/defconfig
index 5bd9fd49e17..8934b36bd1a 100644
--- a/configs/sama5d3x-ek/nx/defconfig
+++ b/configs/sama5d3x-ek/nx/defconfig
@@ -625,7 +625,7 @@ CONFIG_USART1_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -666,7 +666,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/sama5d3x-ek/nxplayer/defconfig b/configs/sama5d3x-ek/nxplayer/defconfig
index 51feda7a001..f7317e9e8c6 100644
--- a/configs/sama5d3x-ek/nxplayer/defconfig
+++ b/configs/sama5d3x-ek/nxplayer/defconfig
@@ -683,7 +683,7 @@ CONFIG_USART1_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -739,7 +739,6 @@ CONFIG_FS_PROCFS=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/sama5d3x-ek/nxwm/defconfig b/configs/sama5d3x-ek/nxwm/defconfig
index 11e9a854417..9fcf1bfdcee 100644
--- a/configs/sama5d3x-ek/nxwm/defconfig
+++ b/configs/sama5d3x-ek/nxwm/defconfig
@@ -690,7 +690,7 @@ CONFIG_USART1_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -739,7 +739,6 @@ CONFIG_FS_PROCFS=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/sama5d3x-ek/ov2640/defconfig b/configs/sama5d3x-ek/ov2640/defconfig
index 1529474d0a4..55dfeef0008 100644
--- a/configs/sama5d3x-ek/ov2640/defconfig
+++ b/configs/sama5d3x-ek/ov2640/defconfig
@@ -650,7 +650,7 @@ CONFIG_USART1_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -684,7 +684,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/sama5d3x-ek/src/sam_ethernet.c b/configs/sama5d3x-ek/src/sam_ethernet.c
index b4d0d31c0bf..87ee620ba7b 100644
--- a/configs/sama5d3x-ek/src/sam_ethernet.c
+++ b/configs/sama5d3x-ek/src/sam_ethernet.c
@@ -87,16 +87,10 @@
 #  define phyerr    _err
 #  define phywarn   _warn
 #  define phyinfo   _info
-#  define phyllerr  _llerr
-#  define phyllwarn _llwarn
-#  define phyllinfo _llinfo
 #else
 #  define phyerr(x...)
 #  define phywarn(x...)
 #  define phyinfo(x...)
-#  define phyllerr(x...)
-#  define phyllwarn(x...)
-#  define phyllinfo(x...)
 #endif
 
 /************************************************************************************
diff --git a/configs/sama5d3x-ek/src/sam_hsmci.c b/configs/sama5d3x-ek/src/sam_hsmci.c
index 8cbcfa4e406..89a0307d890 100644
--- a/configs/sama5d3x-ek/src/sam_hsmci.c
+++ b/configs/sama5d3x-ek/src/sam_hsmci.c
@@ -154,7 +154,7 @@ bool sam_cardinserted_internal(struct sam_hsmci_state_s *state)
   /* Get the state of the PIO pin */
 
   inserted = sam_pioread(state->pincfg);
-  fllinfo("Slot %d inserted: %s\n", state->slotno, inserted ? "NO" : "YES");
+  finfo("Slot %d inserted: %s\n", state->slotno, inserted ? "NO" : "YES");
   return !inserted;
 }
 
diff --git a/configs/sama5d3x-ek/src/sam_usb.c b/configs/sama5d3x-ek/src/sam_usb.c
index e8d7c5c705b..93fec362310 100644
--- a/configs/sama5d3x-ek/src/sam_usb.c
+++ b/configs/sama5d3x-ek/src/sam_usb.c
@@ -538,7 +538,7 @@ xcpt_t sam_setup_overcurrent(xcpt_t handler)
 #ifdef CONFIG_USBDEV
 void sam_usbsuspend(FAR struct usbdev_s *dev, bool resume)
 {
-  ullinfo("resume: %d\n", resume);
+  uinfo("resume: %d\n", resume);
 }
 #endif
 
diff --git a/configs/sama5d4-ek/README.txt b/configs/sama5d4-ek/README.txt
index 2120739e5b3..ee5408b0d0f 100644
--- a/configs/sama5d4-ek/README.txt
+++ b/configs/sama5d4-ek/README.txt
@@ -4272,7 +4272,6 @@ Configurations
        configuration settings are summarized below:
 
        File System:
-       CONFIG_SYSLOG=y             : Enables the System Logging feature.
 
        Device Drivers:
        CONFIG_RAMLOG=y             : Enable the RAM-based logging feature.
diff --git a/configs/sama5d4-ek/at25boot/defconfig b/configs/sama5d4-ek/at25boot/defconfig
index cd7c46ca7bc..1ef4c31c3b9 100644
--- a/configs/sama5d4-ek/at25boot/defconfig
+++ b/configs/sama5d4-ek/at25boot/defconfig
@@ -644,7 +644,7 @@ CONFIG_USART3_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -692,7 +692,6 @@ CONFIG_FAT_MAXFNAME=32
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/sama5d4-ek/bridge/defconfig b/configs/sama5d4-ek/bridge/defconfig
index b90ca57f517..c7f5e3cca97 100644
--- a/configs/sama5d4-ek/bridge/defconfig
+++ b/configs/sama5d4-ek/bridge/defconfig
@@ -685,7 +685,7 @@ CONFIG_USART3_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -831,7 +831,6 @@ CONFIG_FAT_MAXFNAME=32
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/sama5d4-ek/dramboot/defconfig b/configs/sama5d4-ek/dramboot/defconfig
index 9d8209403d2..064b7a25217 100644
--- a/configs/sama5d4-ek/dramboot/defconfig
+++ b/configs/sama5d4-ek/dramboot/defconfig
@@ -601,7 +601,7 @@ CONFIG_USART3_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -649,7 +649,6 @@ CONFIG_FAT_MAXFNAME=32
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/sama5d4-ek/elf/defconfig b/configs/sama5d4-ek/elf/defconfig
index 5e871507ae8..c42a5fb4129 100644
--- a/configs/sama5d4-ek/elf/defconfig
+++ b/configs/sama5d4-ek/elf/defconfig
@@ -642,7 +642,7 @@ CONFIG_USART4_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -683,7 +683,6 @@ CONFIG_FS_ROMFS=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/sama5d4-ek/ipv6/defconfig b/configs/sama5d4-ek/ipv6/defconfig
index ba5f8eaa162..c316af858a5 100644
--- a/configs/sama5d4-ek/ipv6/defconfig
+++ b/configs/sama5d4-ek/ipv6/defconfig
@@ -875,7 +875,7 @@ CONFIG_RAMLOG_BUFSIZE=16384
 # CONFIG_RAMLOG_CRLF is not set
 CONFIG_RAMLOG_NONBLOCKING=y
 CONFIG_RAMLOG_NPOLLWAITERS=4
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -1042,7 +1042,6 @@ CONFIG_FS_PROCFS=y
 #
 # System Logging
 #
-CONFIG_SYSLOG=y
 # CONFIG_SYSLOG_TIMESTAMP is not set
 # CONFIG_SYSLOG_CHAR is not set
 
diff --git a/configs/sama5d4-ek/knsh/defconfig b/configs/sama5d4-ek/knsh/defconfig
index 87b85e3ae60..8d9f0691a3d 100644
--- a/configs/sama5d4-ek/knsh/defconfig
+++ b/configs/sama5d4-ek/knsh/defconfig
@@ -671,7 +671,7 @@ CONFIG_USART4_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -728,7 +728,6 @@ CONFIG_FS_PROCFS=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/sama5d4-ek/knsh/defconfig.ROMFS b/configs/sama5d4-ek/knsh/defconfig.ROMFS
index eeb8acc422f..38e1643c966 100644
--- a/configs/sama5d4-ek/knsh/defconfig.ROMFS
+++ b/configs/sama5d4-ek/knsh/defconfig.ROMFS
@@ -596,7 +596,6 @@ CONFIG_FS_ROMFS=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 
 #
 # Graphics Support
diff --git a/configs/sama5d4-ek/nsh/defconfig b/configs/sama5d4-ek/nsh/defconfig
index d8ef00a4d50..60cfb5bc741 100644
--- a/configs/sama5d4-ek/nsh/defconfig
+++ b/configs/sama5d4-ek/nsh/defconfig
@@ -877,7 +877,7 @@ CONFIG_RAMLOG_BUFSIZE=16384
 # CONFIG_RAMLOG_CRLF is not set
 CONFIG_RAMLOG_NONBLOCKING=y
 CONFIG_RAMLOG_NPOLLWAITERS=4
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -1046,7 +1046,6 @@ CONFIG_FS_PROCFS=y
 #
 # System Logging
 #
-CONFIG_SYSLOG=y
 # CONFIG_SYSLOG_TIMESTAMP is not set
 # CONFIG_SYSLOG_CHAR is not set
 
diff --git a/configs/sama5d4-ek/nxwm/defconfig b/configs/sama5d4-ek/nxwm/defconfig
index 814542201dc..f1ba6ebe4b0 100644
--- a/configs/sama5d4-ek/nxwm/defconfig
+++ b/configs/sama5d4-ek/nxwm/defconfig
@@ -846,7 +846,7 @@ CONFIG_RAMLOG_BUFSIZE=16384
 # CONFIG_RAMLOG_CRLF is not set
 CONFIG_RAMLOG_NONBLOCKING=y
 CONFIG_RAMLOG_NPOLLWAITERS=4
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -1013,7 +1013,6 @@ CONFIG_FS_PROCFS=y
 #
 # System Logging
 #
-CONFIG_SYSLOG=y
 # CONFIG_SYSLOG_TIMESTAMP is not set
 # CONFIG_SYSLOG_CHAR is not set
 
diff --git a/configs/sama5d4-ek/ramtest/defconfig b/configs/sama5d4-ek/ramtest/defconfig
index a8bb0dc5f77..2ab5988a757 100644
--- a/configs/sama5d4-ek/ramtest/defconfig
+++ b/configs/sama5d4-ek/ramtest/defconfig
@@ -601,7 +601,7 @@ CONFIG_USART3_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -657,7 +657,6 @@ CONFIG_FS_PROCFS=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/sama5d4-ek/src/sam_bringup.c b/configs/sama5d4-ek/src/sam_bringup.c
index 953a40b4986..bc32caa2105 100644
--- a/configs/sama5d4-ek/src/sam_bringup.c
+++ b/configs/sama5d4-ek/src/sam_bringup.c
@@ -69,14 +69,6 @@
   (((n)+CONFIG_SAMA5D4EK_ROMFS_ROMDISK_SECTSIZE-1) / \
    CONFIG_SAMA5D4EK_ROMFS_ROMDISK_SECTSIZE)
 
-/* Debug ********************************************************************/
-
-#ifdef CONFIG_BOARD_INITIALIZE
-#  define SYSLOG  _llerr
-#else
-#  define SYSLOG  _err
-#endif
-
 /****************************************************************************
  * Private Functions
  ****************************************************************************/
@@ -171,7 +163,7 @@ int sam_bringup(void)
   ret = sam_nand_automount(NAND_MINOR);
   if (ret < 0)
     {
-      SYSLOG("ERROR: sam_nand_automount failed: %d\n", ret);
+      _err("ERROR: sam_nand_automount failed: %d\n", ret);
     }
 #endif
 
@@ -181,7 +173,7 @@ int sam_bringup(void)
   ret = sam_at25_automount(AT25_MINOR);
   if (ret < 0)
     {
-      SYSLOG("ERROR: sam_at25_automount failed: %d\n", ret);
+      _err("ERROR: sam_at25_automount failed: %d\n", ret);
     }
 #endif
 
@@ -192,8 +184,8 @@ int sam_bringup(void)
   ret = sam_hsmci_initialize(HSMCI0_SLOTNO, HSMCI0_MINOR);
   if (ret < 0)
     {
-      SYSLOG("ERROR: sam_hsmci_initialize(%d,%d) failed: %d\n",
-             HSMCI0_SLOTNO, HSMCI0_MINOR, ret);
+      _err("ERROR: sam_hsmci_initialize(%d,%d) failed: %d\n",
+           HSMCI0_SLOTNO, HSMCI0_MINOR, ret);
     }
 
 #ifdef CONFIG_SAMA5D4EK_HSMCI0_MOUNT
@@ -209,8 +201,8 @@ int sam_bringup(void)
 
       if (ret < 0)
         {
-          SYSLOG("ERROR: Failed to mount %s: %d\n",
-                 CONFIG_SAMA5D4EK_HSMCI0_MOUNT_MOUNTPOINT, errno);
+          _err("ERROR: Failed to mount %s: %d\n",
+               CONFIG_SAMA5D4EK_HSMCI0_MOUNT_MOUNTPOINT, errno);
         }
     }
 #endif
@@ -222,8 +214,8 @@ int sam_bringup(void)
   ret = sam_hsmci_initialize(HSMCI1_SLOTNO, HSMCI1_MINOR);
   if (ret < 0)
     {
-      SYSLOG("ERROR: sam_hsmci_initialize(%d,%d) failed: %d\n",
-             HSMCI1_SLOTNO, HSMCI1_MINOR, ret);
+      _err("ERROR: sam_hsmci_initialize(%d,%d) failed: %d\n",
+           HSMCI1_SLOTNO, HSMCI1_MINOR, ret);
     }
 
 #ifdef CONFIG_SAMA5D4EK_HSMCI1_MOUNT
@@ -239,8 +231,8 @@ int sam_bringup(void)
 
       if (ret < 0)
         {
-          SYSLOG("ERROR: Failed to mount %s: %d\n",
-                 CONFIG_SAMA5D4EK_HSMCI1_MOUNT_MOUNTPOINT, errno);
+          _err("ERROR: Failed to mount %s: %d\n",
+               CONFIG_SAMA5D4EK_HSMCI1_MOUNT_MOUNTPOINT, errno);
         }
     }
 #endif
@@ -261,7 +253,7 @@ int sam_bringup(void)
                          CONFIG_SAMA5D4EK_ROMFS_ROMDISK_SECTSIZE);
   if (ret < 0)
     {
-      SYSLOG("ERROR: romdisk_register failed: %d\n", -ret);
+      _err("ERROR: romdisk_register failed: %d\n", -ret);
     }
   else
     {
@@ -272,9 +264,9 @@ int sam_bringup(void)
                   "romfs", MS_RDONLY, NULL);
       if (ret < 0)
         {
-          SYSLOG("ERROR: mount(%s,%s,romfs) failed: %d\n",
-                 CONFIG_SAMA5D4EK_ROMFS_ROMDISK_DEVNAME,
-                 CONFIG_SAMA5D4EK_ROMFS_MOUNT_MOUNTPOINT, errno);
+          _err("ERROR: mount(%s,%s,romfs) failed: %d\n",
+               CONFIG_SAMA5D4EK_ROMFS_ROMDISK_DEVNAME,
+               CONFIG_SAMA5D4EK_ROMFS_MOUNT_MOUNTPOINT, errno);
         }
     }
 #endif
@@ -287,7 +279,7 @@ int sam_bringup(void)
   ret = sam_usbhost_initialize();
   if (ret != OK)
     {
-      SYSLOG("ERROR: Failed to initialize USB host: %d\n", ret);
+      _err("ERROR: Failed to initialize USB host: %d\n", ret);
     }
 #endif
 
@@ -297,7 +289,7 @@ int sam_bringup(void)
   ret = usbmonitor_start(0, NULL);
   if (ret != OK)
     {
-      SYSLOG("ERROR: Failed to start the USB monitor: %d\n", ret);
+      _err("ERROR: Failed to start the USB monitor: %d\n", ret);
     }
 #endif
 
@@ -307,7 +299,7 @@ int sam_bringup(void)
   ret = sam_wm8904_initialize(0);
   if (ret != OK)
     {
-      SYSLOG("ERROR: Failed to initialize WM8904 audio: %d\n", ret);
+      _err("ERROR: Failed to initialize WM8904 audio: %d\n", ret);
     }
 #endif
 
@@ -317,18 +309,18 @@ int sam_bringup(void)
   ret = sam_audio_null_initialize(0);
   if (ret != OK)
     {
-      SYSLOG("ERROR: Failed to initialize the NULL audio device: %d\n", ret);
+      _err("ERROR: Failed to initialize the NULL audio device: %d\n", ret);
     }
 #endif
 
 #ifdef HAVE_ELF
   /* Initialize the ELF binary loader */
 
-  SYSLOG("Initializing the ELF binary loader\n");
+  _err("Initializing the ELF binary loader\n");
   ret = elf_initialize();
   if (ret < 0)
     {
-      SYSLOG("ERROR: Initialization of the ELF loader failed: %d\n", ret);
+      _err("ERROR: Initialization of the ELF loader failed: %d\n", ret);
     }
 #endif
 
@@ -338,8 +330,8 @@ int sam_bringup(void)
   ret = mount(NULL, SAMA5_PROCFS_MOUNTPOINT, "procfs", 0, NULL);
   if (ret < 0)
     {
-      SYSLOG("ERROR: Failed to mount procfs at %s: %d\n",
-             SAMA5_PROCFS_MOUNTPOINT, ret);
+      _err("ERROR: Failed to mount procfs at %s: %d\n",
+           SAMA5_PROCFS_MOUNTPOINT, ret);
     }
 #endif
 
diff --git a/configs/sama5d4-ek/src/sam_ethernet.c b/configs/sama5d4-ek/src/sam_ethernet.c
index 30fd1e61243..edda5f686a2 100644
--- a/configs/sama5d4-ek/src/sam_ethernet.c
+++ b/configs/sama5d4-ek/src/sam_ethernet.c
@@ -87,16 +87,10 @@
 #  define phyerr    _err
 #  define phywarn   _warn
 #  define phyinfo   _info
-#  define phyllerr  _llerr
-#  define phyllwarn _llwarn
-#  define phyllinfo _llinfo
 #else
 #  define phyerr(x...)
 #  define phywarn(x...)
 #  define phyinfo(x...)
-#  define phyllerr(x...)
-#  define phyllwarn(x...)
-#  define phyllinfo(x...)
 #endif
 
 /************************************************************************************
diff --git a/configs/sama5d4-ek/src/sam_hsmci.c b/configs/sama5d4-ek/src/sam_hsmci.c
index f719c5ae813..5af7468a5ec 100644
--- a/configs/sama5d4-ek/src/sam_hsmci.c
+++ b/configs/sama5d4-ek/src/sam_hsmci.c
@@ -167,7 +167,7 @@ bool sam_cardinserted_internal(struct sam_hsmci_state_s *state)
   /* Get the state of the PIO pin */
 
   inserted = sam_pioread(state->cdcfg);
-  fllinfo("Slot %d inserted: %s\n", state->slotno, inserted ? "NO" : "YES");
+  finfo("Slot %d inserted: %s\n", state->slotno, inserted ? "NO" : "YES");
   return !inserted;
 }
 
diff --git a/configs/sama5d4-ek/src/sam_usb.c b/configs/sama5d4-ek/src/sam_usb.c
index 3b9bbc407c8..1f4d3aff62a 100644
--- a/configs/sama5d4-ek/src/sam_usb.c
+++ b/configs/sama5d4-ek/src/sam_usb.c
@@ -539,7 +539,7 @@ xcpt_t sam_setup_overcurrent(xcpt_t handler)
 #ifdef CONFIG_USBDEV
 void sam_usbsuspend(FAR struct usbdev_s *dev, bool resume)
 {
-  ullinfo("resume: %d\n", resume);
+  uinfo("resume: %d\n", resume);
 }
 #endif
 
diff --git a/configs/samd20-xplained/nsh/defconfig b/configs/samd20-xplained/nsh/defconfig
index 87edc245bfb..c5e67c41c82 100644
--- a/configs/samd20-xplained/nsh/defconfig
+++ b/configs/samd20-xplained/nsh/defconfig
@@ -544,7 +544,7 @@ CONFIG_USART4_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -585,7 +585,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/samd21-xplained/nsh/defconfig b/configs/samd21-xplained/nsh/defconfig
index 83cfab46246..a4c76dda60f 100644
--- a/configs/samd21-xplained/nsh/defconfig
+++ b/configs/samd21-xplained/nsh/defconfig
@@ -542,7 +542,7 @@ CONFIG_USART4_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -583,7 +583,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/same70-xplained/netnsh/defconfig b/configs/same70-xplained/netnsh/defconfig
index 80e6323f2d4..c4421983e7c 100644
--- a/configs/same70-xplained/netnsh/defconfig
+++ b/configs/same70-xplained/netnsh/defconfig
@@ -731,7 +731,7 @@ CONFIG_USART1_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -901,7 +901,6 @@ CONFIG_FS_PROCFS=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/same70-xplained/nsh/defconfig b/configs/same70-xplained/nsh/defconfig
index 0a77aaefd59..e1c9fb23db9 100644
--- a/configs/same70-xplained/nsh/defconfig
+++ b/configs/same70-xplained/nsh/defconfig
@@ -657,7 +657,7 @@ CONFIG_USART1_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -714,7 +714,6 @@ CONFIG_FS_PROCFS=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/same70-xplained/src/sam_bringup.c b/configs/same70-xplained/src/sam_bringup.c
index 814953748ef..759811328e6 100644
--- a/configs/same70-xplained/src/sam_bringup.c
+++ b/configs/same70-xplained/src/sam_bringup.c
@@ -76,14 +76,6 @@
   (((n)+CONFIG_SAME70XPLAINED_ROMFS_ROMDISK_SECTSIZE-1) / \
    CONFIG_SAME70XPLAINED_ROMFS_ROMDISK_SECTSIZE)
 
-/* Debug ********************************************************************/
-
-#ifdef CONFIG_BOARD_INITIALIZE
-#  define SYSLOG  _llerr
-#else
-#  define SYSLOG  _err
-#endif
-
 /****************************************************************************
  * Private Functions
  ****************************************************************************/
@@ -177,7 +169,7 @@ int sam_bringup(void)
   ret = sam_emac0_setmac();
   if (ret < 0)
     {
-      SYSLOG("ERROR: sam_emac0_setmac() failed: %d\n", ret);
+      _err("ERROR: sam_emac0_setmac() failed: %d\n", ret);
     }
 #endif
 
@@ -187,8 +179,8 @@ int sam_bringup(void)
   ret = mount(NULL, SAME70_PROCFS_MOUNTPOINT, "procfs", 0, NULL);
   if (ret < 0)
     {
-      SYSLOG("ERROR: Failed to mount procfs at %s: %d\n",
-             SAME70_PROCFS_MOUNTPOINT, ret);
+      _err("ERROR: Failed to mount procfs at %s: %d\n",
+           SAME70_PROCFS_MOUNTPOINT, ret);
     }
 #endif
 
@@ -200,7 +192,7 @@ int sam_bringup(void)
   ret = sam_at24config();
   if (ret < 0)
     {
-      SYSLOG("ERROR: sam_at24config() failed: %d\n", ret);
+      _err("ERROR: sam_at24config() failed: %d\n", ret);
     }
 #endif
 
@@ -210,8 +202,8 @@ int sam_bringup(void)
   ret = sam_hsmci_initialize(HSMCI0_SLOTNO, HSMCI0_MINOR);
   if (ret < 0)
     {
-      SYSLOG("ERROR: sam_hsmci_initialize(%d,%d) failed: %d\n",
-             HSMCI0_SLOTNO, HSMCI0_MINOR, ret);
+      _err("ERROR: sam_hsmci_initialize(%d,%d) failed: %d\n",
+           HSMCI0_SLOTNO, HSMCI0_MINOR, ret);
     }
 
 #ifdef CONFIG_SAME70XPLAINED_HSMCI0_MOUNT
@@ -227,8 +219,8 @@ int sam_bringup(void)
 
       if (ret < 0)
         {
-          SYSLOG("ERROR: Failed to mount %s: %d\n",
-                 CONFIG_SAME70XPLAINED_HSMCI0_MOUNT_MOUNTPOINT, errno);
+          _err("ERROR: Failed to mount %s: %d\n",
+               CONFIG_SAME70XPLAINED_HSMCI0_MOUNT_MOUNTPOINT, errno);
         }
     }
 
@@ -249,7 +241,7 @@ int sam_bringup(void)
                          CONFIG_SAME70XPLAINED_ROMFS_ROMDISK_SECTSIZE);
   if (ret < 0)
     {
-      SYSLOG("ERROR: romdisk_register failed: %d\n", -ret);
+      _err("ERROR: romdisk_register failed: %d\n", -ret);
     }
   else
     {
@@ -260,9 +252,9 @@ int sam_bringup(void)
                   "romfs", MS_RDONLY, NULL);
       if (ret < 0)
         {
-          SYSLOG("ERROR: mount(%s,%s,romfs) failed: %d\n",
-                 CONFIG_SAME70XPLAINED_ROMFS_ROMDISK_DEVNAME,
-                 CONFIG_SAME70XPLAINED_ROMFS_MOUNT_MOUNTPOINT, errno);
+          _err("ERROR: mount(%s,%s,romfs) failed: %d\n",
+               CONFIG_SAME70XPLAINED_ROMFS_ROMDISK_DEVNAME,
+               CONFIG_SAME70XPLAINED_ROMFS_MOUNT_MOUNTPOINT, errno);
         }
     }
 #endif
@@ -277,7 +269,7 @@ int sam_bringup(void)
   mtd = progmem_initialize();
   if (!mtd)
     {
-      SYSLOG("ERROR: progmem_initialize failed\n");
+      _err("ERROR: progmem_initialize failed\n");
     }
 
   /* Use the FTL layer to wrap the MTD driver as a block driver */
@@ -285,7 +277,7 @@ int sam_bringup(void)
   ret = ftl_initialize(PROGMEM_MTD_MINOR, mtd);
   if (ret < 0)
     {
-      SYSLOG("ERROR: Failed to initialize the FTL layer: %d\n", ret);
+      _err("ERROR: Failed to initialize the FTL layer: %d\n", ret);
       return ret;
     }
 
@@ -299,7 +291,7 @@ int sam_bringup(void)
   ret = bchdev_register(blockdev, chardev, false);
   if (ret < 0)
     {
-      SYSLOG("ERROR: bchdev_register %s failed: %d\n", chardev, ret);
+      _err("ERROR: bchdev_register %s failed: %d\n", chardev, ret);
       return ret;
     }
 #endif
@@ -312,7 +304,7 @@ int sam_bringup(void)
   ret = sam_usbhost_initialize();
   if (ret != OK)
     {
-      SYSLOG("ERROR: Failed to initialize USB host: %d\n", ret);
+      _err("ERROR: Failed to initialize USB host: %d\n", ret);
     }
 #endif
 
@@ -322,18 +314,18 @@ int sam_bringup(void)
   ret = usbmonitor_start(0, NULL);
   if (ret != OK)
     {
-      SYSLOG("ERROR: Failed to start the USB monitor: %d\n", ret);
+      _err("ERROR: Failed to start the USB monitor: %d\n", ret);
     }
 #endif
 
 #ifdef HAVE_ELF
   /* Initialize the ELF binary loader */
 
-  SYSLOG("Initializing the ELF binary loader\n");
+  _err("Initializing the ELF binary loader\n");
   ret = elf_initialize();
   if (ret < 0)
     {
-      SYSLOG("ERROR: Initialization of the ELF loader failed: %d\n", ret);
+      _err("ERROR: Initialization of the ELF loader failed: %d\n", ret);
     }
 #endif
 
diff --git a/configs/same70-xplained/src/sam_ethernet.c b/configs/same70-xplained/src/sam_ethernet.c
index f7a2d9113cb..8f427e8c97a 100644
--- a/configs/same70-xplained/src/sam_ethernet.c
+++ b/configs/same70-xplained/src/sam_ethernet.c
@@ -83,16 +83,10 @@
 #  define phyerr    _err
 #  define phywarn   _warn
 #  define phyinfo   _info
-#  define phyllerr  _llerr
-#  define phyllwarn _llwarn
-#  define phyllinfo _llinfo
 #else
 #  define phyerr(x...)
 #  define phywarn(x...)
 #  define phyinfo(x...)
-#  define phyllerr(x...)
-#  define phyllwarn(x...)
-#  define phyllinfo(x...)
 #endif
 
 /************************************************************************************
diff --git a/configs/same70-xplained/src/sam_hsmci.c b/configs/same70-xplained/src/sam_hsmci.c
index ba9e33871d2..56df5830bd9 100644
--- a/configs/same70-xplained/src/sam_hsmci.c
+++ b/configs/same70-xplained/src/sam_hsmci.c
@@ -129,7 +129,7 @@ bool sam_cardinserted_internal(struct sam_hsmci_state_s *state)
   /* Get the state of the PIO pin */
 
   inserted = sam_gpioread(state->cdcfg);
-  fllinfo("Slot %d inserted: %s\n", state->slotno, inserted ? "NO" : "YES");
+  finfo("Slot %d inserted: %s\n", state->slotno, inserted ? "NO" : "YES");
   return !inserted;
 }
 
diff --git a/configs/same70-xplained/src/sam_usbdev.c b/configs/same70-xplained/src/sam_usbdev.c
index e4be8a893a5..ae0f54f3e0e 100644
--- a/configs/same70-xplained/src/sam_usbdev.c
+++ b/configs/same70-xplained/src/sam_usbdev.c
@@ -94,5 +94,5 @@ void sam_usbinitialize(void)
 
 void sam_usbsuspend(FAR struct usbdev_s *dev, bool resume)
 {
-  ullinfo("resume: %d\n", resume);
+  uinfo("resume: %d\n", resume);
 }
diff --git a/configs/saml21-xplained/nsh/defconfig b/configs/saml21-xplained/nsh/defconfig
index 0501ee95b44..17e0f2f5889 100644
--- a/configs/saml21-xplained/nsh/defconfig
+++ b/configs/saml21-xplained/nsh/defconfig
@@ -530,7 +530,7 @@ CONFIG_USART4_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -571,7 +571,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/samv71-xult/knsh/defconfig b/configs/samv71-xult/knsh/defconfig
index 6339428989f..9e6c0996087 100644
--- a/configs/samv71-xult/knsh/defconfig
+++ b/configs/samv71-xult/knsh/defconfig
@@ -672,7 +672,7 @@ CONFIG_UART3_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -729,7 +729,6 @@ CONFIG_FS_PROCFS=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/samv71-xult/module/defconfig b/configs/samv71-xult/module/defconfig
index 1d484f8f603..fc642b19b5c 100644
--- a/configs/samv71-xult/module/defconfig
+++ b/configs/samv71-xult/module/defconfig
@@ -588,7 +588,7 @@ CONFIG_UART3_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -645,7 +645,6 @@ CONFIG_FS_PROCFS=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/samv71-xult/mxtxplnd/defconfig b/configs/samv71-xult/mxtxplnd/defconfig
index 3909c4bb409..0c62c6a03a8 100644
--- a/configs/samv71-xult/mxtxplnd/defconfig
+++ b/configs/samv71-xult/mxtxplnd/defconfig
@@ -705,7 +705,7 @@ CONFIG_USART0_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -762,7 +762,6 @@ CONFIG_FS_PROCFS=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/samv71-xult/netnsh/defconfig b/configs/samv71-xult/netnsh/defconfig
index 28f69354aca..0fdfc08e770 100644
--- a/configs/samv71-xult/netnsh/defconfig
+++ b/configs/samv71-xult/netnsh/defconfig
@@ -734,7 +734,7 @@ CONFIG_UART3_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -904,7 +904,6 @@ CONFIG_FS_PROCFS=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/samv71-xult/nsh/defconfig b/configs/samv71-xult/nsh/defconfig
index 66eef8cec94..123b0db98e3 100644
--- a/configs/samv71-xult/nsh/defconfig
+++ b/configs/samv71-xult/nsh/defconfig
@@ -665,7 +665,7 @@ CONFIG_UART3_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -722,7 +722,6 @@ CONFIG_FS_PROCFS=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/samv71-xult/nxwm/defconfig b/configs/samv71-xult/nxwm/defconfig
index f4315ad71ad..ba5ff815e6e 100644
--- a/configs/samv71-xult/nxwm/defconfig
+++ b/configs/samv71-xult/nxwm/defconfig
@@ -719,7 +719,7 @@ CONFIG_USART0_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -767,7 +767,6 @@ CONFIG_FAT_MAXFNAME=32
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/samv71-xult/src/sam_bringup.c b/configs/samv71-xult/src/sam_bringup.c
index 85dca370574..b6a33379722 100644
--- a/configs/samv71-xult/src/sam_bringup.c
+++ b/configs/samv71-xult/src/sam_bringup.c
@@ -99,14 +99,6 @@
   (((n)+CONFIG_SAMV71XULT_ROMFS_ROMDISK_SECTSIZE-1) / \
    CONFIG_SAMV71XULT_ROMFS_ROMDISK_SECTSIZE)
 
-/* Debug ********************************************************************/
-
-#ifdef CONFIG_BOARD_INITIALIZE
-#  define SYSLOG  _llerr
-#else
-#  define SYSLOG  _err
-#endif
-
 /****************************************************************************
  * Private Functions
  ****************************************************************************/
@@ -206,7 +198,7 @@ int sam_bringup(void)
   ret = userled_lower_initialize(LED_DRIVER_PATH);
   if (ret < 0)
     {
-      SYSLOG("ERROR: userled_lower_initialize() failed: %d\n", ret);
+      _err("ERROR: userled_lower_initialize() failed: %d\n", ret);
     }
 #endif
 
@@ -216,7 +208,7 @@ int sam_bringup(void)
   i2c = sam_i2cbus_initialize(PCF85263_TWI_BUS);
   if (i2c == NULL)
     {
-      SYSLOG("ERROR: sam_i2cbus_initialize(%d) failed\n", PCF85263_TWI_BUS);
+      _err("ERROR: sam_i2cbus_initialize(%d) failed\n", PCF85263_TWI_BUS);
     }
   else
     {
@@ -225,7 +217,7 @@ int sam_bringup(void)
       ret = pcf85263_rtc_initialize(i2c);
       if (ret < 0)
         {
-          SYSLOG("ERROR: pcf85263_rtc_initialize() failed: %d\n", ret);
+          _err("ERROR: pcf85263_rtc_initialize() failed: %d\n", ret);
         }
       else
         {
@@ -241,7 +233,7 @@ int sam_bringup(void)
   i2c = sam_i2cbus_initialize(DSXXXX_TWI_BUS);
   if (i2c == NULL)
     {
-      SYSLOG("ERROR: sam_i2cbus_initialize(%d) failed\n", DSXXXX_TWI_BUS);
+      _err("ERROR: sam_i2cbus_initialize(%d) failed\n", DSXXXX_TWI_BUS);
     }
   else
     {
@@ -250,7 +242,7 @@ int sam_bringup(void)
       ret = dsxxxx_rtc_initialize(i2c);
       if (ret < 0)
         {
-          SYSLOG("ERROR: dsxxxx_rtc_initialize() failed: %d\n", ret);
+          _err("ERROR: dsxxxx_rtc_initialize() failed: %d\n", ret);
         }
       else
         {
@@ -269,7 +261,7 @@ int sam_bringup(void)
   ret = sam_emac0_setmac();
   if (ret < 0)
     {
-      SYSLOG("ERROR: sam_emac0_setmac() failed: %d\n", ret);
+      _err("ERROR: sam_emac0_setmac() failed: %d\n", ret);
     }
 #endif
 
@@ -279,8 +271,8 @@ int sam_bringup(void)
   ret = mount(NULL, SAMV71_PROCFS_MOUNTPOINT, "procfs", 0, NULL);
   if (ret < 0)
     {
-      SYSLOG("ERROR: Failed to mount procfs at %s: %d\n",
-             SAMV71_PROCFS_MOUNTPOINT, ret);
+      _err("ERROR: Failed to mount procfs at %s: %d\n",
+           SAMV71_PROCFS_MOUNTPOINT, ret);
     }
 #endif
 
@@ -292,7 +284,7 @@ int sam_bringup(void)
   ret = sam_at24config();
   if (ret < 0)
     {
-      SYSLOG("ERROR: sam_at24config() failed: %d\n", ret);
+      _err("ERROR: sam_at24config() failed: %d\n", ret);
     }
 #endif
 
@@ -302,8 +294,8 @@ int sam_bringup(void)
   ret = sam_hsmci_initialize(HSMCI0_SLOTNO, HSMCI0_MINOR);
   if (ret < 0)
     {
-      SYSLOG("ERROR: sam_hsmci_initialize(%d,%d) failed: %d\n",
-             HSMCI0_SLOTNO, HSMCI0_MINOR, ret);
+      _err("ERROR: sam_hsmci_initialize(%d,%d) failed: %d\n",
+           HSMCI0_SLOTNO, HSMCI0_MINOR, ret);
     }
 
 #ifdef CONFIG_SAMV71XULT_HSMCI0_MOUNT
@@ -319,8 +311,8 @@ int sam_bringup(void)
 
       if (ret < 0)
         {
-          SYSLOG("ERROR: Failed to mount %s: %d\n",
-                 CONFIG_SAMV71XULT_HSMCI0_MOUNT_MOUNTPOINT, errno);
+          _err("ERROR: Failed to mount %s: %d\n",
+               CONFIG_SAMV71XULT_HSMCI0_MOUNT_MOUNTPOINT, errno);
         }
     }
 
@@ -341,7 +333,7 @@ int sam_bringup(void)
                          CONFIG_SAMV71XULT_ROMFS_ROMDISK_SECTSIZE);
   if (ret < 0)
     {
-      SYSLOG("ERROR: romdisk_register failed: %d\n", -ret);
+      _err("ERROR: romdisk_register failed: %d\n", -ret);
     }
   else
     {
@@ -352,9 +344,9 @@ int sam_bringup(void)
                   "romfs", MS_RDONLY, NULL);
       if (ret < 0)
         {
-          SYSLOG("ERROR: mount(%s,%s,romfs) failed: %d\n",
-                 CONFIG_SAMV71XULT_ROMFS_ROMDISK_DEVNAME,
-                 CONFIG_SAMV71XULT_ROMFS_MOUNT_MOUNTPOINT, errno);
+          _err("ERROR: mount(%s,%s,romfs) failed: %d\n",
+               CONFIG_SAMV71XULT_ROMFS_ROMDISK_DEVNAME,
+               CONFIG_SAMV71XULT_ROMFS_MOUNT_MOUNTPOINT, errno);
         }
     }
 #endif
@@ -365,7 +357,7 @@ int sam_bringup(void)
   qspi = sam_qspi_initialize(0);
   if (!qspi)
     {
-      SYSLOG("ERROR: sam_qspi_initialize failed\n");
+      _err("ERROR: sam_qspi_initialize failed\n");
     }
   else
     {
@@ -376,7 +368,7 @@ int sam_bringup(void)
       mtd = s25fl1_initialize(qspi, true);
       if (!mtd)
         {
-          SYSLOG("ERROR: s25fl1_initialize failed\n");
+          _err("ERROR: s25fl1_initialize failed\n");
         }
 
 #ifdef HAVE_S25FL1_SMARTFS
@@ -385,7 +377,7 @@ int sam_bringup(void)
       ret = smart_initialize(S25FL1_SMART_MINOR, mtd, NULL);
       if (ret != OK)
         {
-          SYSLOG("ERROR: Failed to initialize SmartFS: %d\n", ret);
+          _err("ERROR: Failed to initialize SmartFS: %d\n", ret);
         }
 
 #elif defined(HAVE_S25FL1_NXFFS)
@@ -394,7 +386,7 @@ int sam_bringup(void)
       ret = nxffs_initialize(mtd);
       if (ret < 0)
         {
-         SYSLOG("ERROR: NXFFS initialization failed: %d\n", ret);
+         _err("ERROR: NXFFS initialization failed: %d\n", ret);
         }
 
       /* Mount the file system at /mnt/s25fl1 */
@@ -402,7 +394,7 @@ int sam_bringup(void)
       ret = mount(NULL, "/mnt/s25fl1", "nxffs", 0, NULL);
       if (ret < 0)
         {
-          SYSLOG("ERROR: Failed to mount the NXFFS volume: %d\n", errno);
+          _err("ERROR: Failed to mount the NXFFS volume: %d\n", errno);
           return ret;
         }
 
@@ -412,7 +404,7 @@ int sam_bringup(void)
       ret = ftl_initialize(S25FL1_MTD_MINOR, mtd);
       if (ret < 0)
         {
-          SYSLOG("ERROR: Failed to initialize the FTL layer: %d\n", ret);
+          _err("ERROR: Failed to initialize the FTL layer: %d\n", ret);
           return ret;
         }
 
@@ -426,7 +418,7 @@ int sam_bringup(void)
       ret = bchdev_register(blockdev, chardev, false);
       if (ret < 0)
         {
-          SYSLOG("ERROR: bchdev_register %s failed: %d\n", chardev, ret);
+          _err("ERROR: bchdev_register %s failed: %d\n", chardev, ret);
           return ret;
         }
 #endif
@@ -443,7 +435,7 @@ int sam_bringup(void)
   mtd = progmem_initialize();
   if (!mtd)
     {
-      SYSLOG("ERROR: progmem_initialize failed\n");
+      _err("ERROR: progmem_initialize failed\n");
     }
 
   /* Use the FTL layer to wrap the MTD driver as a block driver */
@@ -451,7 +443,7 @@ int sam_bringup(void)
   ret = ftl_initialize(PROGMEM_MTD_MINOR, mtd);
   if (ret < 0)
     {
-      SYSLOG("ERROR: Failed to initialize the FTL layer: %d\n", ret);
+      _err("ERROR: Failed to initialize the FTL layer: %d\n", ret);
       return ret;
     }
 
@@ -465,7 +457,7 @@ int sam_bringup(void)
   ret = bchdev_register(blockdev, chardev, false);
   if (ret < 0)
     {
-      SYSLOG("ERROR: bchdev_register %s failed: %d\n", chardev, ret);
+      _err("ERROR: bchdev_register %s failed: %d\n", chardev, ret);
       return ret;
     }
 #endif
@@ -478,7 +470,7 @@ int sam_bringup(void)
   ret = sam_usbhost_initialize();
   if (ret != OK)
     {
-      SYSLOG("ERROR: Failed to initialize USB host: %d\n", ret);
+      _err("ERROR: Failed to initialize USB host: %d\n", ret);
     }
 #endif
 
@@ -488,7 +480,7 @@ int sam_bringup(void)
   ret = usbmonitor_start(0, NULL);
   if (ret != OK)
     {
-      SYSLOG("ERROR: Failed to start the USB monitor: %d\n", ret);
+      _err("ERROR: Failed to start the USB monitor: %d\n", ret);
     }
 #endif
 
@@ -498,7 +490,7 @@ int sam_bringup(void)
   ret = sam_wm8904_initialize(0);
   if (ret != OK)
     {
-      SYSLOG("ERROR: Failed to initialize WM8904 audio: %d\n", ret);
+      _err("ERROR: Failed to initialize WM8904 audio: %d\n", ret);
     }
 #endif
 
@@ -508,18 +500,18 @@ int sam_bringup(void)
   ret = sam_audio_null_initialize(0);
   if (ret != OK)
     {
-      SYSLOG("ERROR: Failed to initialize the NULL audio device: %d\n", ret);
+      _err("ERROR: Failed to initialize the NULL audio device: %d\n", ret);
     }
 #endif
 
 #ifdef HAVE_ELF
   /* Initialize the ELF binary loader */
 
-  SYSLOG("Initializing the ELF binary loader\n");
+  _err("Initializing the ELF binary loader\n");
   ret = elf_initialize();
   if (ret < 0)
     {
-      SYSLOG("ERROR: Initialization of the ELF loader failed: %d\n", ret);
+      _err("ERROR: Initialization of the ELF loader failed: %d\n", ret);
     }
 #endif
 
diff --git a/configs/samv71-xult/src/sam_ethernet.c b/configs/samv71-xult/src/sam_ethernet.c
index 00d91314a02..2714eab3beb 100644
--- a/configs/samv71-xult/src/sam_ethernet.c
+++ b/configs/samv71-xult/src/sam_ethernet.c
@@ -83,16 +83,10 @@
 #  define phyerr    _err
 #  define phywarn   _warn
 #  define phyinfo   _info
-#  define phyllerr  _llerr
-#  define phyllwarn _llwarn
-#  define phyllinfo _llinfo
 #else
 #  define phyerr(x...)
 #  define phywarn(x...)
 #  define phyinfo(x...)
-#  define phyllerr(x...)
-#  define phyllwarn(x...)
-#  define phyllinfo(x...)
 #endif
 
 /************************************************************************************
diff --git a/configs/samv71-xult/src/sam_hsmci.c b/configs/samv71-xult/src/sam_hsmci.c
index 1e0eb3670ed..85e66b048d5 100644
--- a/configs/samv71-xult/src/sam_hsmci.c
+++ b/configs/samv71-xult/src/sam_hsmci.c
@@ -129,7 +129,7 @@ bool sam_cardinserted_internal(struct sam_hsmci_state_s *state)
   /* Get the state of the PIO pin */
 
   inserted = sam_gpioread(state->cdcfg);
-  fllinfo("Slot %d inserted: %s\n", state->slotno, inserted ? "NO" : "YES");
+  finfo("Slot %d inserted: %s\n", state->slotno, inserted ? "NO" : "YES");
   return !inserted;
 }
 
diff --git a/configs/samv71-xult/src/sam_usbdev.c b/configs/samv71-xult/src/sam_usbdev.c
index 39e39a1997b..9dec1511034 100644
--- a/configs/samv71-xult/src/sam_usbdev.c
+++ b/configs/samv71-xult/src/sam_usbdev.c
@@ -94,5 +94,5 @@ void sam_usbinitialize(void)
 
 void sam_usbsuspend(FAR struct usbdev_s *dev, bool resume)
 {
-  ullinfo("resume: %d\n", resume);
+  uinfo("resume: %d\n", resume);
 }
diff --git a/configs/samv71-xult/vnc/defconfig b/configs/samv71-xult/vnc/defconfig
index 6e472ce90b2..bf5f14f78d8 100644
--- a/configs/samv71-xult/vnc/defconfig
+++ b/configs/samv71-xult/vnc/defconfig
@@ -735,7 +735,7 @@ CONFIG_UART3_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -901,7 +901,6 @@ CONFIG_FS_PROCFS=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/samv71-xult/vnxwm/defconfig b/configs/samv71-xult/vnxwm/defconfig
index 30c3346129d..9a8d768422d 100644
--- a/configs/samv71-xult/vnxwm/defconfig
+++ b/configs/samv71-xult/vnxwm/defconfig
@@ -738,7 +738,7 @@ CONFIG_UART3_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -904,7 +904,6 @@ CONFIG_FS_PROCFS=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/shenzhou/nsh/defconfig b/configs/shenzhou/nsh/defconfig
index 6d7451accf2..67d1dfa0781 100644
--- a/configs/shenzhou/nsh/defconfig
+++ b/configs/shenzhou/nsh/defconfig
@@ -858,7 +858,7 @@ CONFIG_USART2_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -1015,7 +1015,6 @@ CONFIG_FAT_MAXFNAME=32
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/shenzhou/nxwm/defconfig b/configs/shenzhou/nxwm/defconfig
index cd4f922de24..ca29ac7cd29 100644
--- a/configs/shenzhou/nxwm/defconfig
+++ b/configs/shenzhou/nxwm/defconfig
@@ -922,7 +922,7 @@ CONFIG_USART2_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -1071,7 +1071,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/shenzhou/src/stm32_usb.c b/configs/shenzhou/src/stm32_usb.c
index 35c2ff422bc..ce32772207b 100644
--- a/configs/shenzhou/src/stm32_usb.c
+++ b/configs/shenzhou/src/stm32_usb.c
@@ -300,7 +300,7 @@ xcpt_t stm32_setup_overcurrent(xcpt_t handler)
 #ifdef CONFIG_USBDEV
 void stm32_usbsuspend(FAR struct usbdev_s *dev, bool resume)
 {
-  ullinfo("resume: %d\n", resume);
+  uinfo("resume: %d\n", resume);
 }
 #endif
 
diff --git a/configs/shenzhou/thttpd/defconfig b/configs/shenzhou/thttpd/defconfig
index b6a706238d5..dc34d9d5817 100644
--- a/configs/shenzhou/thttpd/defconfig
+++ b/configs/shenzhou/thttpd/defconfig
@@ -914,7 +914,7 @@ CONFIG_USART2_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -1072,7 +1072,6 @@ CONFIG_FS_ROMFS=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/sim/bas/defconfig b/configs/sim/bas/defconfig
index 263a99090e6..0045828f2e9 100644
--- a/configs/sim/bas/defconfig
+++ b/configs/sim/bas/defconfig
@@ -349,7 +349,7 @@ CONFIG_SERIAL=y
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -403,7 +403,6 @@ CONFIG_FS_PROCFS=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/sim/configdata/defconfig b/configs/sim/configdata/defconfig
index f4233e53604..1f8af42edf5 100644
--- a/configs/sim/configdata/defconfig
+++ b/configs/sim/configdata/defconfig
@@ -370,7 +370,7 @@ CONFIG_SERIAL=y
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -420,7 +420,6 @@ CONFIG_NXFFS_TAILTHRESHOLD=8192
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/sim/cxxtest/defconfig b/configs/sim/cxxtest/defconfig
index 6c81c365be4..aceb1fc38d8 100644
--- a/configs/sim/cxxtest/defconfig
+++ b/configs/sim/cxxtest/defconfig
@@ -361,7 +361,7 @@ CONFIG_SERIAL=y
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -402,7 +402,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/sim/mount/defconfig b/configs/sim/mount/defconfig
index 05e0718ce7c..60d8ee2f281 100644
--- a/configs/sim/mount/defconfig
+++ b/configs/sim/mount/defconfig
@@ -360,7 +360,7 @@ CONFIG_SERIAL=y
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -405,7 +405,6 @@ CONFIG_FS_FAT=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/sim/mtdpart/defconfig b/configs/sim/mtdpart/defconfig
index a91df0a3d2b..df0f7c19a46 100644
--- a/configs/sim/mtdpart/defconfig
+++ b/configs/sim/mtdpart/defconfig
@@ -368,7 +368,7 @@ CONFIG_SERIAL=y
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -412,7 +412,6 @@ CONFIG_FS_FAT=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/sim/mtdrwb/defconfig b/configs/sim/mtdrwb/defconfig
index 4eb9ea87808..f7da4507c06 100644
--- a/configs/sim/mtdrwb/defconfig
+++ b/configs/sim/mtdrwb/defconfig
@@ -399,7 +399,7 @@ CONFIG_SERIAL=y
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -443,7 +443,6 @@ CONFIG_FS_FAT=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/sim/nettest/defconfig b/configs/sim/nettest/defconfig
index da4d1d71408..a5124f251aa 100644
--- a/configs/sim/nettest/defconfig
+++ b/configs/sim/nettest/defconfig
@@ -352,7 +352,7 @@ CONFIG_SERIAL=y
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -502,7 +502,6 @@ CONFIG_FS_FAT=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/sim/nsh/defconfig b/configs/sim/nsh/defconfig
index 48223bb14a8..b0eb7f0c9fb 100644
--- a/configs/sim/nsh/defconfig
+++ b/configs/sim/nsh/defconfig
@@ -363,7 +363,7 @@ CONFIG_SERIAL=y
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -420,7 +420,6 @@ CONFIG_FS_PROCFS=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/sim/nsh2/defconfig b/configs/sim/nsh2/defconfig
index ea53866275f..bc6571c458a 100644
--- a/configs/sim/nsh2/defconfig
+++ b/configs/sim/nsh2/defconfig
@@ -358,7 +358,7 @@ CONFIG_SERIAL=y
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -411,7 +411,6 @@ CONFIG_FS_PROCFS=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/sim/nx/defconfig b/configs/sim/nx/defconfig
index 5d816932c73..688161175d9 100644
--- a/configs/sim/nx/defconfig
+++ b/configs/sim/nx/defconfig
@@ -364,7 +364,7 @@ CONFIG_SERIAL=y
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -398,7 +398,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/sim/nx11/defconfig b/configs/sim/nx11/defconfig
index 05d2ac83cb2..d1987dc8aba 100644
--- a/configs/sim/nx11/defconfig
+++ b/configs/sim/nx11/defconfig
@@ -365,7 +365,7 @@ CONFIG_SERIAL=y
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -399,7 +399,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/sim/nxffs/defconfig b/configs/sim/nxffs/defconfig
index 2f17fed0b85..1cd792167e3 100644
--- a/configs/sim/nxffs/defconfig
+++ b/configs/sim/nxffs/defconfig
@@ -345,7 +345,7 @@ CONFIG_SERIAL=y
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -396,7 +396,6 @@ CONFIG_NXFFS_TAILTHRESHOLD=8192
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/sim/nxlines/defconfig b/configs/sim/nxlines/defconfig
index c2c38d6215a..28f3880aedb 100644
--- a/configs/sim/nxlines/defconfig
+++ b/configs/sim/nxlines/defconfig
@@ -356,7 +356,7 @@ CONFIG_SERIAL=y
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -409,7 +409,6 @@ CONFIG_FS_PROCFS=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/sim/nxwm/defconfig b/configs/sim/nxwm/defconfig
index 3baa4ef65dc..9287f229bd6 100644
--- a/configs/sim/nxwm/defconfig
+++ b/configs/sim/nxwm/defconfig
@@ -355,7 +355,7 @@ CONFIG_SERIAL=y
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -408,7 +408,6 @@ CONFIG_FS_PROCFS=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/sim/ostest/defconfig b/configs/sim/ostest/defconfig
index 62666d3d3aa..8928a46a2e7 100644
--- a/configs/sim/ostest/defconfig
+++ b/configs/sim/ostest/defconfig
@@ -372,7 +372,7 @@ CONFIG_SERIAL=y
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -414,7 +414,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/sim/pashello/defconfig b/configs/sim/pashello/defconfig
index 1ffde388e08..c82757a6aa8 100644
--- a/configs/sim/pashello/defconfig
+++ b/configs/sim/pashello/defconfig
@@ -337,7 +337,7 @@ CONFIG_SERIAL=y
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -382,7 +382,6 @@ CONFIG_FS_FAT=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/sim/src/sim_bringup.c b/configs/sim/src/sim_bringup.c
index 28b4c8fdcbe..d65d99edb3b 100644
--- a/configs/sim/src/sim_bringup.c
+++ b/configs/sim/src/sim_bringup.c
@@ -53,18 +53,6 @@
 int trv_mount_world(int minor, FAR const char *mountpoint);
 #endif
 
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/* Debug ********************************************************************/
-
-#ifdef CONFIG_BOARD_INITIALIZE
-#  define SYSLOG  _llerr
-#else
-#  define SYSLOG  _err
-#endif
-
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
@@ -107,8 +95,8 @@ int sim_bringup(void)
   ret = mount(NULL, SIM_PROCFS_MOUNTPOINT, "procfs", 0, NULL);
   if (ret < 0)
     {
-      SYSLOG("ERROR: Failed to mount procfs at %s: %d\n",
-             SIM_PROCFS_MOUNTPOINT, ret);
+      _err("ERROR: Failed to mount procfs at %s: %d\n",
+           SIM_PROCFS_MOUNTPOINT, ret);
     }
 #endif
 
diff --git a/configs/sim/touchscreen/defconfig b/configs/sim/touchscreen/defconfig
index 3cb463d85c8..01012d9eed0 100644
--- a/configs/sim/touchscreen/defconfig
+++ b/configs/sim/touchscreen/defconfig
@@ -387,7 +387,7 @@ CONFIG_SERIAL=y
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -421,7 +421,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/sim/traveler/defconfig b/configs/sim/traveler/defconfig
index b9854ec3f27..4c260ef8943 100644
--- a/configs/sim/traveler/defconfig
+++ b/configs/sim/traveler/defconfig
@@ -379,7 +379,7 @@ CONFIG_SERIAL=y
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -420,7 +420,6 @@ CONFIG_FS_ROMFS=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/sim/udgram/defconfig b/configs/sim/udgram/defconfig
index 5db261aa15f..2c747306d89 100644
--- a/configs/sim/udgram/defconfig
+++ b/configs/sim/udgram/defconfig
@@ -365,7 +365,7 @@ CONFIG_SERIAL=y
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -502,7 +502,6 @@ CONFIG_FS_PROCFS=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/sim/unionfs/defconfig b/configs/sim/unionfs/defconfig
index f634b8bf10d..7bfe0b1ec3b 100644
--- a/configs/sim/unionfs/defconfig
+++ b/configs/sim/unionfs/defconfig
@@ -349,7 +349,7 @@ CONFIG_SERIAL=y
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -403,7 +403,6 @@ CONFIG_FS_UNIONFS=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/sim/ustream/defconfig b/configs/sim/ustream/defconfig
index 53879abb9fd..54a65071316 100644
--- a/configs/sim/ustream/defconfig
+++ b/configs/sim/ustream/defconfig
@@ -365,7 +365,7 @@ CONFIG_SERIAL=y
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -502,7 +502,6 @@ CONFIG_FS_PROCFS=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/skp16c26/ostest/defconfig b/configs/skp16c26/ostest/defconfig
index afa72d9af41..cf950449245 100644
--- a/configs/skp16c26/ostest/defconfig
+++ b/configs/skp16c26/ostest/defconfig
@@ -302,7 +302,6 @@ CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y
 # System Logging
 #
 
-# CONFIG_SYSLOG is not set
 
 #
 # Graphics Support
diff --git a/configs/spark/composite/defconfig b/configs/spark/composite/defconfig
index c0713e16b1b..310439b7628 100644
--- a/configs/spark/composite/defconfig
+++ b/configs/spark/composite/defconfig
@@ -885,7 +885,7 @@ CONFIG_CC3000_UNSOLICED_STACKSIZE=264
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -938,7 +938,6 @@ CONFIG_FS_FATTIME=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/spark/nsh/defconfig b/configs/spark/nsh/defconfig
index a18bcd21cbf..037990ab7c3 100644
--- a/configs/spark/nsh/defconfig
+++ b/configs/spark/nsh/defconfig
@@ -885,7 +885,7 @@ CONFIG_CC3000_UNSOLICED_STACKSIZE=264
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -938,7 +938,6 @@ CONFIG_FS_FATTIME=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/spark/src/stm32_usbdev.c b/configs/spark/src/stm32_usbdev.c
index 47f8d558ed8..ef59cef0c65 100644
--- a/configs/spark/src/stm32_usbdev.c
+++ b/configs/spark/src/stm32_usbdev.c
@@ -74,7 +74,7 @@
 
 void stm32_usbinitialize(void)
 {
-  ullinfo("called\n");
+  uinfo("called\n");
 
   /* USB Soft Connect Pullup */
 
@@ -113,5 +113,5 @@ int stm32_usbpullup(FAR struct usbdev_s *dev, bool enable)
 
 void stm32_usbsuspend(FAR struct usbdev_s *dev, bool resume)
 {
-  ullinfo("resume: %d\n", resume);
+  uinfo("resume: %d\n", resume);
 }
diff --git a/configs/spark/usbmsc/defconfig b/configs/spark/usbmsc/defconfig
index 8e945a51d2d..121e10b5b98 100644
--- a/configs/spark/usbmsc/defconfig
+++ b/configs/spark/usbmsc/defconfig
@@ -849,7 +849,7 @@ CONFIG_CC3000_UNSOLICED_STACKSIZE=264
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -902,7 +902,6 @@ CONFIG_FS_FATTIME=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/spark/usbnsh/defconfig b/configs/spark/usbnsh/defconfig
index 0069b99f042..2d4a963b664 100644
--- a/configs/spark/usbnsh/defconfig
+++ b/configs/spark/usbnsh/defconfig
@@ -888,7 +888,6 @@ CONFIG_FS_FAT=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/spark/usbserial/defconfig b/configs/spark/usbserial/defconfig
index dcc83462a09..35279b3dbc7 100644
--- a/configs/spark/usbserial/defconfig
+++ b/configs/spark/usbserial/defconfig
@@ -859,7 +859,7 @@ CONFIG_CC3000_PROBES=y
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -912,7 +912,6 @@ CONFIG_FS_FATTIME=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/stm3210e-eval/buttons/defconfig b/configs/stm3210e-eval/buttons/defconfig
index 9760c7596ad..afc30ec09be 100644
--- a/configs/stm3210e-eval/buttons/defconfig
+++ b/configs/stm3210e-eval/buttons/defconfig
@@ -756,7 +756,7 @@ CONFIG_USART2_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -789,7 +789,6 @@ CONFIG_DISABLE_MOUNTPOINT=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/stm3210e-eval/composite/defconfig b/configs/stm3210e-eval/composite/defconfig
index 42564278212..4062ccbfff6 100644
--- a/configs/stm3210e-eval/composite/defconfig
+++ b/configs/stm3210e-eval/composite/defconfig
@@ -902,7 +902,7 @@ CONFIG_USBMSC_SCSI_STACKSIZE=2048
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -942,7 +942,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/stm3210e-eval/nsh/defconfig b/configs/stm3210e-eval/nsh/defconfig
index 3e4babf3c4e..c3526b15ff0 100644
--- a/configs/stm3210e-eval/nsh/defconfig
+++ b/configs/stm3210e-eval/nsh/defconfig
@@ -854,7 +854,7 @@ CONFIG_USBDEV_MAXPOWER=100
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -900,7 +900,6 @@ CONFIG_FAT_LCNAMES=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/stm3210e-eval/nsh2/defconfig b/configs/stm3210e-eval/nsh2/defconfig
index 6495ae0b4f0..94d06efad54 100644
--- a/configs/stm3210e-eval/nsh2/defconfig
+++ b/configs/stm3210e-eval/nsh2/defconfig
@@ -927,7 +927,7 @@ CONFIG_USBMSC_SCSI_STACKSIZE=2048
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -975,7 +975,6 @@ CONFIG_FAT_MAXFNAME=32
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/stm3210e-eval/nx/defconfig b/configs/stm3210e-eval/nx/defconfig
index 4eab3a9dedc..d4283c715ab 100644
--- a/configs/stm3210e-eval/nx/defconfig
+++ b/configs/stm3210e-eval/nx/defconfig
@@ -846,7 +846,7 @@ CONFIG_USBDEV_MAXPOWER=100
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -880,7 +880,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/stm3210e-eval/nxterm/defconfig b/configs/stm3210e-eval/nxterm/defconfig
index da99ecd650f..9c371098f4c 100644
--- a/configs/stm3210e-eval/nxterm/defconfig
+++ b/configs/stm3210e-eval/nxterm/defconfig
@@ -823,7 +823,7 @@ CONFIG_USART2_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -864,7 +864,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/stm3210e-eval/pm/defconfig b/configs/stm3210e-eval/pm/defconfig
index 570954ff632..c09cc4ccffd 100644
--- a/configs/stm3210e-eval/pm/defconfig
+++ b/configs/stm3210e-eval/pm/defconfig
@@ -865,7 +865,7 @@ CONFIG_USART2_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -906,7 +906,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/stm3210e-eval/src/stm32_djoystick.c b/configs/stm3210e-eval/src/stm32_djoystick.c
index 8e367c5e3a7..72d5009e705 100644
--- a/configs/stm3210e-eval/src/stm32_djoystick.c
+++ b/configs/stm3210e-eval/src/stm32_djoystick.c
@@ -177,8 +177,8 @@ static void djoy_enable(FAR const struct djoy_lowerhalf_s *lower,
   flags = enter_critical_section();
   djoy_disable();
 
-  illinfo("press: %02x release: %02x handler: %p arg: %p\n",
-          press, release, handler, arg);
+  iinfo("press: %02x release: %02x handler: %p arg: %p\n",
+        press, release, handler, arg);
 
   /* If no events are indicated or if no handler is provided, then this
    * must really be a request to disable interrupts.
@@ -209,8 +209,8 @@ static void djoy_enable(FAR const struct djoy_lowerhalf_s *lower,
                falling = ((press & bit) != 0);
                rising  = ((release & bit) != 0);
 
-               illinfo("GPIO %d: rising: %d falling: %d\n",
-                        i, rising, falling);
+               iinfo("GPIO %d: rising: %d falling: %d\n",
+                      i, rising, falling);
 
                (void)stm32_gpiosetevent(g_joygpio[i], rising, falling,
                                         true, djoy_interrupt);
diff --git a/configs/stm3210e-eval/src/stm32_idle.c b/configs/stm3210e-eval/src/stm32_idle.c
index 5dc94ece4ec..e50aac3c854 100644
--- a/configs/stm3210e-eval/src/stm32_idle.c
+++ b/configs/stm3210e-eval/src/stm32_idle.c
@@ -229,7 +229,7 @@ static int stm32_rtc_alarm(time_t tv_sec, time_t tv_nsec, bool exti)
   ret = stm32_rtc_setalarm(&alarmtime, stm32_alarmcb);
   if (ret < 0)
     {
-      sllerr("ERROR: Warning: The alarm is already set\n");
+      serr("ERROR: Warning: The alarm is already set\n");
     }
 
   return ret;
@@ -290,7 +290,7 @@ static void stm32_idlepm(void)
 
   if (newstate != oldstate)
     {
-      _llinfo("newstate= %d oldstate=%d\n", newstate, oldstate);
+      _info("newstate= %d oldstate=%d\n", newstate, oldstate);
 
       sched_lock();
 
@@ -366,7 +366,7 @@ static void stm32_idlepm(void)
             ret = stm32_rtc_cancelalarm();
             if (ret < 0)
               {
-                sllwarn("WARNING: Cancel alarm failed\n");
+                swarn("WARNING: Cancel alarm failed\n");
               }
 #endif
             /* Note:  See the additional PM_STANDBY related logic at the
diff --git a/configs/stm3210e-eval/src/stm32_pmbuttons.c b/configs/stm3210e-eval/src/stm32_pmbuttons.c
index 49be1db7e22..3e723af37fb 100644
--- a/configs/stm3210e-eval/src/stm32_pmbuttons.c
+++ b/configs/stm3210e-eval/src/stm32_pmbuttons.c
@@ -318,9 +318,9 @@ void stm32_pmbuttons(void)
 
       if (oldhandler != NULL)
         {
-          lowsyslog(LOG_WARNING, "WARNING: oldhandler:%p is not NULL!  "
-                    "Button events may be lost or aliased!\n",
-                    oldhandler);
+          warn("WARNING: oldhandler:%p is not NULL!  "
+               "Button events may be lost or aliased!\n",
+               oldhandler);
         }
     }
 #endif
diff --git a/configs/stm3210e-eval/src/stm32_usbdev.c b/configs/stm3210e-eval/src/stm32_usbdev.c
index 143c938af15..89eed63bc9e 100644
--- a/configs/stm3210e-eval/src/stm32_usbdev.c
+++ b/configs/stm3210e-eval/src/stm32_usbdev.c
@@ -110,5 +110,5 @@ int stm32_usbpullup(FAR struct usbdev_s *dev, bool enable)
 
 void stm32_usbsuspend(FAR struct usbdev_s *dev, bool resume)
 {
-  ullinfo("resume: %d\n", resume);
+  uinfo("resume: %d\n", resume);
 }
diff --git a/configs/stm3210e-eval/usbmsc/defconfig b/configs/stm3210e-eval/usbmsc/defconfig
index 8548824a957..9896e045195 100644
--- a/configs/stm3210e-eval/usbmsc/defconfig
+++ b/configs/stm3210e-eval/usbmsc/defconfig
@@ -830,7 +830,7 @@ CONFIG_USBMSC_SCSI_STACKSIZE=2048
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -870,7 +870,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/stm3210e-eval/usbserial/defconfig b/configs/stm3210e-eval/usbserial/defconfig
index 7a54c3a789c..6e817633973 100644
--- a/configs/stm3210e-eval/usbserial/defconfig
+++ b/configs/stm3210e-eval/usbserial/defconfig
@@ -805,7 +805,7 @@ CONFIG_PL2303_PRODUCTSTR="USBdev Serial"
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -839,7 +839,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/stm3220g-eval/README.txt b/configs/stm3220g-eval/README.txt
index 07c61bc6d50..2ffb33194da 100644
--- a/configs/stm3220g-eval/README.txt
+++ b/configs/stm3220g-eval/README.txt
@@ -1087,7 +1087,6 @@ Where <subdir> is one of the following:
 
     There are some special settings to make life with only a Telnet
 
-    CONFIG_SYSLOG=y - Enables the System Logging feature.
     CONFIG_RAMLOG=y - Enable the RAM-based logging feature.
     CONFIG_RAMLOG_CONSOLE=y - Use the RAM logger as the default console.
       This means that any console output from non-Telnet threads will
diff --git a/configs/stm3220g-eval/dhcpd/defconfig b/configs/stm3220g-eval/dhcpd/defconfig
index 25432aea872..805beb41727 100644
--- a/configs/stm3220g-eval/dhcpd/defconfig
+++ b/configs/stm3220g-eval/dhcpd/defconfig
@@ -811,7 +811,7 @@ CONFIG_USART3_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -942,7 +942,6 @@ CONFIG_DISABLE_MOUNTPOINT=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/stm3220g-eval/ide/nsh/iar/libc.ewp b/configs/stm3220g-eval/ide/nsh/iar/libc.ewp
index 8804fd90438..db57f8d8b93 100644
--- a/configs/stm3220g-eval/ide/nsh/iar/libc.ewp
+++ b/configs/stm3220g-eval/ide/nsh/iar/libc.ewp
@@ -2631,9 +2631,6 @@
     <file>
       <name>$PROJ_DIR$/../../../../../libc/syslog/lib_syslog.c</name>
     </file>
-    <file>
-      <name>$PROJ_DIR$/../../../../../libc/syslog/lib_lowsyslog.c</name>
-    </file>
     <file>
       <name>$PROJ_DIR$/../../../../../libc/syslog/lib_setlogmask.c</name>
     </file>
diff --git a/configs/stm3220g-eval/ide/nsh/uvision/libc.uvproj b/configs/stm3220g-eval/ide/nsh/uvision/libc.uvproj
index 5baf501cd84..31ee6e86a52 100644
--- a/configs/stm3220g-eval/ide/nsh/uvision/libc.uvproj
+++ b/configs/stm3220g-eval/ide/nsh/uvision/libc.uvproj
@@ -1478,16 +1478,6 @@
               <FileType>1</FileType>
               <FilePath>../../../../../libc/symtab/symtab_findorderedbyvalue.c</FilePath>
             </File>
-            <File>
-              <FileName>lib_syslog.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>../../../../../libc/syslog/lib_syslog.c</FilePath>
-            </File>
-            <File>
-              <FileName>lib_lowsyslog.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>../../../../../libc/syslog/lib_lowsyslog.c</FilePath>
-            </File>
             <File>
               <FileName>lib_setlogmask.c</FileName>
               <FileType>1</FileType>
diff --git a/configs/stm3220g-eval/nettest/defconfig b/configs/stm3220g-eval/nettest/defconfig
index bd6d76b0327..17436141d62 100644
--- a/configs/stm3220g-eval/nettest/defconfig
+++ b/configs/stm3220g-eval/nettest/defconfig
@@ -811,7 +811,7 @@ CONFIG_USART3_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -947,7 +947,6 @@ CONFIG_DISABLE_MOUNTPOINT=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/stm3220g-eval/nsh/defconfig b/configs/stm3220g-eval/nsh/defconfig
index 55eb89cda4e..001e8d6d008 100644
--- a/configs/stm3220g-eval/nsh/defconfig
+++ b/configs/stm3220g-eval/nsh/defconfig
@@ -896,7 +896,7 @@ CONFIG_USART3_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -1053,7 +1053,6 @@ CONFIG_FAT_MAXFNAME=32
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/stm3220g-eval/nsh2/defconfig b/configs/stm3220g-eval/nsh2/defconfig
index 99b7a1f652b..997630da9e6 100644
--- a/configs/stm3220g-eval/nsh2/defconfig
+++ b/configs/stm3220g-eval/nsh2/defconfig
@@ -1053,7 +1053,6 @@ CONFIG_FAT_MAXFNAME=32
 #
 # System Logging
 #
-CONFIG_SYSLOG=y
 # CONFIG_SYSLOG_TIMESTAMP is not set
 # CONFIG_SYSLOG_CHAR is not set
 
diff --git a/configs/stm3220g-eval/nxwm/defconfig b/configs/stm3220g-eval/nxwm/defconfig
index 10dd97c8c92..7e3f42c3baa 100644
--- a/configs/stm3220g-eval/nxwm/defconfig
+++ b/configs/stm3220g-eval/nxwm/defconfig
@@ -946,7 +946,7 @@ CONFIG_USART3_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -1102,7 +1102,6 @@ CONFIG_FAT_MAXFNAME=32
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/stm3220g-eval/src/stm32_usb.c b/configs/stm3220g-eval/src/stm32_usb.c
index 36b48c2c70c..adecafb76df 100644
--- a/configs/stm3220g-eval/src/stm32_usb.c
+++ b/configs/stm3220g-eval/src/stm32_usb.c
@@ -300,7 +300,7 @@ xcpt_t stm32_setup_overcurrent(xcpt_t handler)
 #ifdef CONFIG_USBDEV
 void stm32_usbsuspend(FAR struct usbdev_s *dev, bool resume)
 {
-  ullinfo("resume: %d\n", resume);
+  uinfo("resume: %d\n", resume);
 }
 #endif
 
diff --git a/configs/stm3220g-eval/telnetd/defconfig b/configs/stm3220g-eval/telnetd/defconfig
index 456ec61e190..47f800f3191 100644
--- a/configs/stm3220g-eval/telnetd/defconfig
+++ b/configs/stm3220g-eval/telnetd/defconfig
@@ -813,7 +813,7 @@ CONFIG_USART3_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -949,7 +949,6 @@ CONFIG_DISABLE_MOUNTPOINT=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/stm3240g-eval/README.txt b/configs/stm3240g-eval/README.txt
index ce2d8a21222..9b2e6b97cc8 100644
--- a/configs/stm3240g-eval/README.txt
+++ b/configs/stm3240g-eval/README.txt
@@ -1327,7 +1327,6 @@ Where <subdir> is one of the following:
 
     There are some special settings to make life with only a Telnet
 
-    CONFIG_SYSLOG=y - Enables the System Logging feature.
     CONFIG_RAMLOG=y - Enable the RAM-based logging feature.
     CONFIG_RAMLOG_CONSOLE=y - Use the RAM logger as the default console.
       This means that any console output from non-Telnet threads will
diff --git a/configs/stm3240g-eval/dhcpd/defconfig b/configs/stm3240g-eval/dhcpd/defconfig
index 8aede9c9e36..34dae8ea1db 100644
--- a/configs/stm3240g-eval/dhcpd/defconfig
+++ b/configs/stm3240g-eval/dhcpd/defconfig
@@ -815,7 +815,7 @@ CONFIG_USART3_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -946,7 +946,6 @@ CONFIG_DISABLE_MOUNTPOINT=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/stm3240g-eval/discover/defconfig b/configs/stm3240g-eval/discover/defconfig
index a6556e8be1d..bb3e492924c 100644
--- a/configs/stm3240g-eval/discover/defconfig
+++ b/configs/stm3240g-eval/discover/defconfig
@@ -838,7 +838,7 @@ CONFIG_USART3_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -994,7 +994,6 @@ CONFIG_FAT_MAXFNAME=32
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/stm3240g-eval/knxwm/defconfig b/configs/stm3240g-eval/knxwm/defconfig
index 895218c6f40..1a350e3b676 100644
--- a/configs/stm3240g-eval/knxwm/defconfig
+++ b/configs/stm3240g-eval/knxwm/defconfig
@@ -891,7 +891,7 @@ CONFIG_USART3_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -938,7 +938,6 @@ CONFIG_FAT_MAXFNAME=32
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/stm3240g-eval/nettest/defconfig b/configs/stm3240g-eval/nettest/defconfig
index 7ff0a9859f3..3c2dd7b6b03 100644
--- a/configs/stm3240g-eval/nettest/defconfig
+++ b/configs/stm3240g-eval/nettest/defconfig
@@ -815,7 +815,7 @@ CONFIG_USART3_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -951,7 +951,6 @@ CONFIG_DISABLE_MOUNTPOINT=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/stm3240g-eval/nsh/defconfig b/configs/stm3240g-eval/nsh/defconfig
index e11d8b48ad1..b46e539a5a8 100644
--- a/configs/stm3240g-eval/nsh/defconfig
+++ b/configs/stm3240g-eval/nsh/defconfig
@@ -875,7 +875,7 @@ CONFIG_USART3_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -1032,7 +1032,6 @@ CONFIG_FAT_MAXFNAME=32
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/stm3240g-eval/nsh2/defconfig b/configs/stm3240g-eval/nsh2/defconfig
index f413fb97d98..6903c6cbd45 100644
--- a/configs/stm3240g-eval/nsh2/defconfig
+++ b/configs/stm3240g-eval/nsh2/defconfig
@@ -1057,7 +1057,6 @@ CONFIG_FAT_MAXFNAME=32
 #
 # System Logging
 #
-CONFIG_SYSLOG=y
 # CONFIG_SYSLOG_TIMESTAMP is not set
 # CONFIG_SYSLOG_CHAR is not set
 
diff --git a/configs/stm3240g-eval/nxterm/defconfig b/configs/stm3240g-eval/nxterm/defconfig
index c50998d6989..291340b2a32 100644
--- a/configs/stm3240g-eval/nxterm/defconfig
+++ b/configs/stm3240g-eval/nxterm/defconfig
@@ -908,7 +908,7 @@ CONFIG_USART3_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -1058,7 +1058,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/stm3240g-eval/nxwm/defconfig b/configs/stm3240g-eval/nxwm/defconfig
index cfc9df8f9b2..c2729b1ea0d 100644
--- a/configs/stm3240g-eval/nxwm/defconfig
+++ b/configs/stm3240g-eval/nxwm/defconfig
@@ -942,7 +942,7 @@ CONFIG_USART3_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -1098,7 +1098,6 @@ CONFIG_FAT_MAXFNAME=32
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/stm3240g-eval/src/stm32_usb.c b/configs/stm3240g-eval/src/stm32_usb.c
index e289ad19e86..71d51ce9ed4 100644
--- a/configs/stm3240g-eval/src/stm32_usb.c
+++ b/configs/stm3240g-eval/src/stm32_usb.c
@@ -300,7 +300,7 @@ xcpt_t stm32_setup_overcurrent(xcpt_t handler)
 #ifdef CONFIG_USBDEV
 void stm32_usbsuspend(FAR struct usbdev_s *dev, bool resume)
 {
-  ullinfo("resume: %d\n", resume);
+  uinfo("resume: %d\n", resume);
 }
 #endif
 
diff --git a/configs/stm3240g-eval/telnetd/defconfig b/configs/stm3240g-eval/telnetd/defconfig
index 6d37c628d55..f2895a91e3c 100644
--- a/configs/stm3240g-eval/telnetd/defconfig
+++ b/configs/stm3240g-eval/telnetd/defconfig
@@ -817,7 +817,7 @@ CONFIG_USART3_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -953,7 +953,6 @@ CONFIG_DISABLE_MOUNTPOINT=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/stm3240g-eval/webserver/defconfig b/configs/stm3240g-eval/webserver/defconfig
index d624ed0102f..b16ae73145b 100644
--- a/configs/stm3240g-eval/webserver/defconfig
+++ b/configs/stm3240g-eval/webserver/defconfig
@@ -894,7 +894,7 @@ CONFIG_USART3_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -1050,7 +1050,6 @@ CONFIG_FAT_MAXFNAME=32
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/stm3240g-eval/xmlrpc/defconfig b/configs/stm3240g-eval/xmlrpc/defconfig
index ef3897d0fcf..e802595fe0e 100644
--- a/configs/stm3240g-eval/xmlrpc/defconfig
+++ b/configs/stm3240g-eval/xmlrpc/defconfig
@@ -834,7 +834,7 @@ CONFIG_USART3_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -990,7 +990,6 @@ CONFIG_FAT_MAXFNAME=32
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/stm32_tiny/README.txt b/configs/stm32_tiny/README.txt
index 74552767236..29a8cbb43ff 100644
--- a/configs/stm32_tiny/README.txt
+++ b/configs/stm32_tiny/README.txt
@@ -617,7 +617,7 @@ Where <subdir> is one of the following:
 
         - /dev/console still exists and still refers to the serial port. So
           you can still use certain kinds of debug output (see include/debug.h, all
-          of the interfaces based on lowsyslog will work in this configuration).
+          of the debug output from interrupt handlers will be lost.
 
         - But don't enable USB debug output!  Since USB is console is used for
           USB debug output and you are using a USB console, there will be
@@ -657,7 +657,6 @@ Where <subdir> is one of the following:
     3. This configuration does have UART2 output enabled and set up as
        the system logging device:
 
-       CONFIG_SYSLOG=y                    : Enable output to syslog, not console
        CONFIG_SYSLOG_CHAR=y               : Use a character device for system logging
        CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" : UART2 will be /dev/ttyS0
 
diff --git a/configs/stm32_tiny/nsh/defconfig b/configs/stm32_tiny/nsh/defconfig
index 9314ce10dab..7ba4ffc1ece 100644
--- a/configs/stm32_tiny/nsh/defconfig
+++ b/configs/stm32_tiny/nsh/defconfig
@@ -764,7 +764,7 @@ CONFIG_WL_NRF24L01_RXFIFO_LEN=128
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -805,7 +805,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/stm32_tiny/src/stm32_usbdev.c b/configs/stm32_tiny/src/stm32_usbdev.c
index 5331dd7fffa..e9e76b4c2e2 100644
--- a/configs/stm32_tiny/src/stm32_usbdev.c
+++ b/configs/stm32_tiny/src/stm32_usbdev.c
@@ -74,7 +74,7 @@
 
 void stm32_usbinitialize(void)
 {
-  ullinfo("called\n");
+  uinfo("called\n");
 
   /* USB Soft Connect Pullup */
   stm32_configgpio(GPIO_USB_PULLUP);
@@ -112,5 +112,5 @@ int stm32_usbpullup(FAR struct usbdev_s *dev, bool enable)
 
 void stm32_usbsuspend(FAR struct usbdev_s *dev, bool resume)
 {
-  ullinfo("resume: %d\n", resume);
+  uinfo("resume: %d\n", resume);
 }
diff --git a/configs/stm32_tiny/usbnsh/defconfig b/configs/stm32_tiny/usbnsh/defconfig
index dee2bffc0ca..e42722af42b 100644
--- a/configs/stm32_tiny/usbnsh/defconfig
+++ b/configs/stm32_tiny/usbnsh/defconfig
@@ -819,7 +819,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/stm32f103-minimum/README.txt b/configs/stm32f103-minimum/README.txt
index 908a02bc88d..edd0fc92e1a 100644
--- a/configs/stm32f103-minimum/README.txt
+++ b/configs/stm32f103-minimum/README.txt
@@ -548,6 +548,13 @@ Where <subdir> is one of the following:
     console device was about 5 KB (primarily OS support) and the cost of
     the NSH 'ls' command (including OS support) is about 2KB.
 
+    2016-06-21:  Just checking the size after some big system changes:  The
+    size of the base configuration has actually dropped by a few bytes:
+
+     $ arm-none-eabi-size nuttx
+        text    data     bss     dec     hex filename
+      12526       4     816   13346    3422 nuttx
+
   nsh:
   ---
     Configures the NuttShell (nsh) located at apps/examples/nsh. This
@@ -583,7 +590,6 @@ Where <subdir> is one of the following:
     3. This configuration does have UART2 output enabled and set up as
        the system logging device:
 
-       CONFIG_SYSLOG=y                    : Enable output to syslog, not console
        CONFIG_SYSLOG_CHAR=y               : Use a character device for system logging
        CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" : UART2 will be /dev/ttyS0
 
diff --git a/configs/stm32f103-minimum/minnsh/defconfig b/configs/stm32f103-minimum/minnsh/defconfig
index f82d32cdaab..ce656ae2c6b 100644
--- a/configs/stm32f103-minimum/minnsh/defconfig
+++ b/configs/stm32f103-minimum/minnsh/defconfig
@@ -754,7 +754,6 @@ CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/stm32f103-minimum/nsh/defconfig b/configs/stm32f103-minimum/nsh/defconfig
index 6a74e8d4db0..9837d73ae16 100644
--- a/configs/stm32f103-minimum/nsh/defconfig
+++ b/configs/stm32f103-minimum/nsh/defconfig
@@ -741,7 +741,7 @@ CONFIG_USART1_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -782,7 +782,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/stm32f103-minimum/src/stm32_usbdev.c b/configs/stm32f103-minimum/src/stm32_usbdev.c
index 753d292dcd8..ecbd707fb76 100644
--- a/configs/stm32f103-minimum/src/stm32_usbdev.c
+++ b/configs/stm32f103-minimum/src/stm32_usbdev.c
@@ -103,5 +103,5 @@ int stm32_usbpullup(FAR struct usbdev_s *dev, bool enable)
 
 void stm32_usbsuspend(FAR struct usbdev_s *dev, bool resume)
 {
-  ullinfo("resume: %d\n", resume);
+  uinfo("resume: %d\n", resume);
 }
diff --git a/configs/stm32f103-minimum/usbnsh/defconfig b/configs/stm32f103-minimum/usbnsh/defconfig
index b1804dc70b4..cbdc654d597 100644
--- a/configs/stm32f103-minimum/usbnsh/defconfig
+++ b/configs/stm32f103-minimum/usbnsh/defconfig
@@ -819,7 +819,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/stm32f3discovery/README.txt b/configs/stm32f3discovery/README.txt
index 7917da3773c..64eb13ba18b 100644
--- a/configs/stm32f3discovery/README.txt
+++ b/configs/stm32f3discovery/README.txt
@@ -778,7 +778,6 @@ Where <subdir> is one of the following:
        the system logging device:
 
        Device Drivers -> System Logging Device Options:
-         CONFIG_SYSLOG=y                    : Enable output to syslog, not console
          CONFIG_SYSLOG_CHAR=y               : Use a character device for system logging
          CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" : USART2 will be /dev/ttyS0
 
diff --git a/configs/stm32f3discovery/nsh/defconfig b/configs/stm32f3discovery/nsh/defconfig
index ea746def107..269761d1321 100644
--- a/configs/stm32f3discovery/nsh/defconfig
+++ b/configs/stm32f3discovery/nsh/defconfig
@@ -799,7 +799,7 @@ CONFIG_CDCACM_PRODUCTSTR="CDC/ACM Serial"
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -840,7 +840,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/stm32f3discovery/src/stm32_usb.c b/configs/stm32f3discovery/src/stm32_usb.c
index 658e796c2be..d824090bad3 100644
--- a/configs/stm32f3discovery/src/stm32_usb.c
+++ b/configs/stm32f3discovery/src/stm32_usb.c
@@ -121,7 +121,7 @@ int stm32_usbpullup(FAR struct usbdev_s *dev, bool enable)
 
 void stm32_usbsuspend(FAR struct usbdev_s *dev, bool resume)
 {
-  ullinfo("Resume: %d\n", resume);
+  uinfo("Resume: %d\n", resume);
 }
 
 #endif /* CONFIG_STM32_USB */
diff --git a/configs/stm32f3discovery/usbnsh/defconfig b/configs/stm32f3discovery/usbnsh/defconfig
index 1b60a529e12..50e9dd3435f 100644
--- a/configs/stm32f3discovery/usbnsh/defconfig
+++ b/configs/stm32f3discovery/usbnsh/defconfig
@@ -852,7 +852,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-CONFIG_SYSLOG=y
 # CONFIG_SYSLOG_TIMESTAMP is not set
 CONFIG_SYSLOG_CHAR=y
 CONFIG_SYSLOG_DEVPATH="/dev/ttyS0"
diff --git a/configs/stm32f411e-disco/nsh/defconfig b/configs/stm32f411e-disco/nsh/defconfig
index 16f23c50485..282476a13d8 100644
--- a/configs/stm32f411e-disco/nsh/defconfig
+++ b/configs/stm32f411e-disco/nsh/defconfig
@@ -737,7 +737,7 @@ CONFIG_USART2_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -778,7 +778,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/stm32f429i-disco/README.txt b/configs/stm32f429i-disco/README.txt
index c803960bf5a..d14134e0680 100644
--- a/configs/stm32f429i-disco/README.txt
+++ b/configs/stm32f429i-disco/README.txt
@@ -726,7 +726,7 @@ Where <subdir> is one of the following:
 
         - /dev/console still exists and still refers to the serial port. So
           you can still use certain kinds of debug output (see include/debug.h, all
-          of the interfaces based on lowsyslog will work in this configuration).
+          debug output from interrupt handlers will be lost.
 
         - But don't enable USB debug output!  Since USB is console is used for
           USB debug output and you are using a USB console, there will be
diff --git a/configs/stm32f429i-disco/extflash/defconfig b/configs/stm32f429i-disco/extflash/defconfig
index ca991936890..06dd83e1ea1 100644
--- a/configs/stm32f429i-disco/extflash/defconfig
+++ b/configs/stm32f429i-disco/extflash/defconfig
@@ -865,7 +865,7 @@ CONFIG_USART1_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -921,7 +921,6 @@ CONFIG_FS_PROCFS=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/stm32f429i-disco/ide/ltcd/uvision/libc.uvproj b/configs/stm32f429i-disco/ide/ltcd/uvision/libc.uvproj
index 9a501a0b517..f7340f2ce7f 100644
--- a/configs/stm32f429i-disco/ide/ltcd/uvision/libc.uvproj
+++ b/configs/stm32f429i-disco/ide/ltcd/uvision/libc.uvproj
@@ -1425,11 +1425,6 @@
               <FileType>1</FileType>
               <FilePath>../../../../../libc/syslog/lib_syslog.c</FilePath>
             </File>
-            <File>
-              <FileName>lib_lowsyslog.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>../../../../../libc/syslog/lib_lowsyslog.c</FilePath>
-            </File>
             <File>
               <FileName>lib_setlogmask.c</FileName>
               <FileType>1</FileType>
diff --git a/configs/stm32f429i-disco/lcd/defconfig b/configs/stm32f429i-disco/lcd/defconfig
index bc0a882e2c4..32d0d306d7e 100644
--- a/configs/stm32f429i-disco/lcd/defconfig
+++ b/configs/stm32f429i-disco/lcd/defconfig
@@ -822,7 +822,7 @@ CONFIG_USART1_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -863,7 +863,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/stm32f429i-disco/ltdc/defconfig b/configs/stm32f429i-disco/ltdc/defconfig
index cea3ab6a9ab..6504e4e3eee 100644
--- a/configs/stm32f429i-disco/ltdc/defconfig
+++ b/configs/stm32f429i-disco/ltdc/defconfig
@@ -865,7 +865,7 @@ CONFIG_USART1_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -914,7 +914,6 @@ CONFIG_FS_PROCFS_REGISTER=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/stm32f429i-disco/nsh/defconfig b/configs/stm32f429i-disco/nsh/defconfig
index c54c4bd5b69..df6fe33ebd3 100644
--- a/configs/stm32f429i-disco/nsh/defconfig
+++ b/configs/stm32f429i-disco/nsh/defconfig
@@ -780,7 +780,7 @@ CONFIG_USART1_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -821,7 +821,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/stm32f429i-disco/src/stm32_idle.c b/configs/stm32f429i-disco/src/stm32_idle.c
index bb23e39065a..03bf79db1a5 100644
--- a/configs/stm32f429i-disco/src/stm32_idle.c
+++ b/configs/stm32f429i-disco/src/stm32_idle.c
@@ -125,7 +125,7 @@ static void stm32_idlepm(void)
 
   if (newstate != oldstate)
     {
-      sllinfo("newstate= %d oldstate=%d\n", newstate, oldstate);
+      sinfo("newstate= %d oldstate=%d\n", newstate, oldstate);
 
       flags = enter_critical_section();
 
diff --git a/configs/stm32f429i-disco/src/stm32_usb.c b/configs/stm32f429i-disco/src/stm32_usb.c
index 6d6da4d9312..011726a69b1 100644
--- a/configs/stm32f429i-disco/src/stm32_usb.c
+++ b/configs/stm32f429i-disco/src/stm32_usb.c
@@ -306,7 +306,7 @@ xcpt_t stm32_setup_overcurrent(xcpt_t handler)
 #ifdef CONFIG_USBDEV
 void stm32_usbsuspend(FAR struct usbdev_s *dev, bool resume)
 {
-  ullinfo("resume: %d\n", resume);
+  uinfo("resume: %d\n", resume);
 }
 #endif
 
diff --git a/configs/stm32f429i-disco/usbmsc/defconfig b/configs/stm32f429i-disco/usbmsc/defconfig
index 5f34604f72d..a010d81bdb5 100644
--- a/configs/stm32f429i-disco/usbmsc/defconfig
+++ b/configs/stm32f429i-disco/usbmsc/defconfig
@@ -813,7 +813,7 @@ CONFIG_USBHOST_MSC=y
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -860,7 +860,6 @@ CONFIG_FS_FAT=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/stm32f429i-disco/usbnsh/defconfig b/configs/stm32f429i-disco/usbnsh/defconfig
index 2189ee2ebfc..e5a5394c154 100644
--- a/configs/stm32f429i-disco/usbnsh/defconfig
+++ b/configs/stm32f429i-disco/usbnsh/defconfig
@@ -874,7 +874,6 @@ CONFIG_FS_FAT=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/stm32f4discovery/README.txt b/configs/stm32f4discovery/README.txt
index 9dc0ceb95c0..e0c912d1648 100644
--- a/configs/stm32f4discovery/README.txt
+++ b/configs/stm32f4discovery/README.txt
@@ -1652,7 +1652,7 @@ Where <subdir> is one of the following:
 
         - /dev/console still exists and still refers to the serial port. So
           you can still use certain kinds of debug output (see include/debug.h, all
-          of the interfaces based on lowsyslog will work in this configuration).
+          of the debug output from interrupt handlers will be lost.
 
         - But don't enable USB debug output!  Since USB is console is used for
           USB debug output and you are using a USB console, there will be
@@ -1979,7 +1979,6 @@ Where <subdir> is one of the following:
     3. This configuration does have UART2 output enabled and set up as
        the system logging device:
 
-       CONFIG_SYSLOG=y                    : Enable output to syslog, not console
        CONFIG_SYSLOG_CHAR=y               : Use a character device for system logging
        CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" : UART2 will be /dev/ttyS0
 
diff --git a/configs/stm32f4discovery/cxxtest/defconfig b/configs/stm32f4discovery/cxxtest/defconfig
index df571f322af..00e1029dc5b 100644
--- a/configs/stm32f4discovery/cxxtest/defconfig
+++ b/configs/stm32f4discovery/cxxtest/defconfig
@@ -774,7 +774,7 @@ CONFIG_USART2_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -808,7 +808,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/stm32f4discovery/elf/defconfig b/configs/stm32f4discovery/elf/defconfig
index 82c8b86c0a6..1cff39814bb 100644
--- a/configs/stm32f4discovery/elf/defconfig
+++ b/configs/stm32f4discovery/elf/defconfig
@@ -773,7 +773,7 @@ CONFIG_USART2_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -813,7 +813,6 @@ CONFIG_FS_ROMFS=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/stm32f4discovery/ipv6/defconfig b/configs/stm32f4discovery/ipv6/defconfig
index 9cf8c1ee699..c74e1fe5f00 100644
--- a/configs/stm32f4discovery/ipv6/defconfig
+++ b/configs/stm32f4discovery/ipv6/defconfig
@@ -902,7 +902,7 @@ CONFIG_USART6_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -1069,7 +1069,6 @@ CONFIG_FS_PROCFS=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/stm32f4discovery/kostest/defconfig b/configs/stm32f4discovery/kostest/defconfig
index 00e1ff529f0..57c52c32604 100644
--- a/configs/stm32f4discovery/kostest/defconfig
+++ b/configs/stm32f4discovery/kostest/defconfig
@@ -781,7 +781,7 @@ CONFIG_USART2_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -815,7 +815,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/stm32f4discovery/netnsh/defconfig b/configs/stm32f4discovery/netnsh/defconfig
index 5a83e7bdbdd..262ed58a5b1 100644
--- a/configs/stm32f4discovery/netnsh/defconfig
+++ b/configs/stm32f4discovery/netnsh/defconfig
@@ -904,7 +904,7 @@ CONFIG_USART6_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -1073,7 +1073,6 @@ CONFIG_FS_PROCFS=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/stm32f4discovery/nsh/defconfig b/configs/stm32f4discovery/nsh/defconfig
index 7a8b1a8b58f..b49e862c0ba 100644
--- a/configs/stm32f4discovery/nsh/defconfig
+++ b/configs/stm32f4discovery/nsh/defconfig
@@ -789,7 +789,7 @@ CONFIG_USART2_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -838,7 +838,6 @@ CONFIG_FS_PROCFS=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/stm32f4discovery/nxlines/defconfig b/configs/stm32f4discovery/nxlines/defconfig
index fccdcbc179c..05dda537a97 100644
--- a/configs/stm32f4discovery/nxlines/defconfig
+++ b/configs/stm32f4discovery/nxlines/defconfig
@@ -829,7 +829,7 @@ CONFIG_USART2_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -877,7 +877,6 @@ CONFIG_FS_PROCFS=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/stm32f4discovery/pm/defconfig b/configs/stm32f4discovery/pm/defconfig
index 383a96f6444..fd0fc976b8e 100644
--- a/configs/stm32f4discovery/pm/defconfig
+++ b/configs/stm32f4discovery/pm/defconfig
@@ -814,7 +814,7 @@ CONFIG_USART2_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -863,7 +863,6 @@ CONFIG_FS_PROCFS=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/stm32f4discovery/posix_spawn/defconfig b/configs/stm32f4discovery/posix_spawn/defconfig
index 3e58869dd11..96467039657 100644
--- a/configs/stm32f4discovery/posix_spawn/defconfig
+++ b/configs/stm32f4discovery/posix_spawn/defconfig
@@ -773,7 +773,7 @@ CONFIG_USART2_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -813,7 +813,6 @@ CONFIG_FS_ROMFS=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/stm32f4discovery/rgbled/defconfig b/configs/stm32f4discovery/rgbled/defconfig
index d01e11f1097..bc51c7fb53f 100644
--- a/configs/stm32f4discovery/rgbled/defconfig
+++ b/configs/stm32f4discovery/rgbled/defconfig
@@ -824,7 +824,7 @@ CONFIG_USART2_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -873,7 +873,6 @@ CONFIG_FS_PROCFS=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/stm32f4discovery/src/stm32_ethernet.c b/configs/stm32f4discovery/src/stm32_ethernet.c
index e8418d41f7a..67b7b9e95e3 100644
--- a/configs/stm32f4discovery/src/stm32_ethernet.c
+++ b/configs/stm32f4discovery/src/stm32_ethernet.c
@@ -82,16 +82,10 @@
 #  define phyerr    _err
 #  define phywarn   _warn
 #  define phyinfo   _info
-#  define phyllerr  _llerr
-#  define phyllwarn _llwarn
-#  define phyllinfo _llinfo
 #else
 #  define phyerr(x...)
 #  define phywarn(x...)
 #  define phyinfo(x...)
-#  define phyllerr(x...)
-#  define phyllwarn(x...)
-#  define phyllinfo(x...)
 #endif
 
 /************************************************************************************
diff --git a/configs/stm32f4discovery/src/stm32_idle.c b/configs/stm32f4discovery/src/stm32_idle.c
index 4fb9a0d0f72..a73ee49ba83 100644
--- a/configs/stm32f4discovery/src/stm32_idle.c
+++ b/configs/stm32f4discovery/src/stm32_idle.c
@@ -122,7 +122,7 @@ static void stm32_idlepm(void)
 
   if (newstate != oldstate)
     {
-      sllinfo("newstate= %d oldstate=%d\n", newstate, oldstate);
+      sinfo("newstate= %d oldstate=%d\n", newstate, oldstate);
 
       flags = enter_critical_section();
 
diff --git a/configs/stm32f4discovery/src/stm32_pmbuttons.c b/configs/stm32f4discovery/src/stm32_pmbuttons.c
index 0ca71c9dcde..750eaadbbe1 100644
--- a/configs/stm32f4discovery/src/stm32_pmbuttons.c
+++ b/configs/stm32f4discovery/src/stm32_pmbuttons.c
@@ -41,13 +41,13 @@
 #include <arch/board/board.h>
 #include <nuttx/config.h>
 
+#include <stdbool.h>
+#include <debug.h>
+
 #include <nuttx/board.h>
 #include <nuttx/power/pm.h>
 #include <arch/irq.h>
 
-#include <stdbool.h>
-#include <debug.h>
-
 #include "up_arch.h"
 #include "nvic.h"
 #include "stm32_pwr.h"
@@ -75,10 +75,6 @@
 
 #define PM_IDLE_DOMAIN  0 /* Revisit */
 
-/****************************************************************************
- * Private Types
- ****************************************************************************/
-
 /****************************************************************************
  * Private Function Prototypes
  ****************************************************************************/
@@ -87,10 +83,6 @@
 static int button_handler(int irq, FAR void *context);
 #endif /* CONFIG_ARCH_IRQBUTTONS */
 
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
 /****************************************************************************
  * Private Functions
  ****************************************************************************/
@@ -142,9 +134,9 @@ void stm32_pm_buttons(void)
 
       if (oldhandler != NULL)
         {
-          lowsyslog(LOG_WARNING, "WARNING: oldhandler:%p is not NULL!  "
-                   "Button events may be lost or aliased!\n",
-                   oldhandler);
+          _warn("WARNING: oldhandler:%p is not NULL!  "
+                "Button events may be lost or aliased!\n",
+                oldhandler);
         }
 #endif
 }
diff --git a/configs/stm32f4discovery/src/stm32_usb.c b/configs/stm32f4discovery/src/stm32_usb.c
index b77b34c72e3..397aaff76df 100644
--- a/configs/stm32f4discovery/src/stm32_usb.c
+++ b/configs/stm32f4discovery/src/stm32_usb.c
@@ -329,7 +329,7 @@ xcpt_t stm32_setup_overcurrent(xcpt_t handler)
 #ifdef CONFIG_USBDEV
 void stm32_usbsuspend(FAR struct usbdev_s *dev, bool resume)
 {
-  ullinfo("resume: %d\n", resume);
+  uinfo("resume: %d\n", resume);
 }
 #endif
 
diff --git a/configs/stm32f4discovery/src/stm32_zerocross.c b/configs/stm32f4discovery/src/stm32_zerocross.c
index e31ebbd066f..af0b99b860a 100644
--- a/configs/stm32f4discovery/src/stm32_zerocross.c
+++ b/configs/stm32f4discovery/src/stm32_zerocross.c
@@ -111,7 +111,7 @@ static void zcross_enable(FAR const struct zc_lowerhalf_s *lower,
   flags = enter_critical_section();
   zcross_disable();
 
-  snllinfo("handler: %p arg: %p\n", handler, arg);
+  sninfo("handler: %p arg: %p\n", handler, arg);
 
   if (handler)
     {
diff --git a/configs/stm32f4discovery/uavcan/defconfig b/configs/stm32f4discovery/uavcan/defconfig
index de306262859..7718d6329fb 100644
--- a/configs/stm32f4discovery/uavcan/defconfig
+++ b/configs/stm32f4discovery/uavcan/defconfig
@@ -750,7 +750,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-CONFIG_SYSLOG=y
 # CONFIG_SYSLOG_TIMESTAMP is not set
 # CONFIG_SYSLOG_CHAR is not set
 
diff --git a/configs/stm32f4discovery/usbnsh/defconfig b/configs/stm32f4discovery/usbnsh/defconfig
index 16c569baf46..86d93e72137 100644
--- a/configs/stm32f4discovery/usbnsh/defconfig
+++ b/configs/stm32f4discovery/usbnsh/defconfig
@@ -885,7 +885,6 @@ CONFIG_FS_PROCFS=y
 #
 # System Logging
 #
-CONFIG_SYSLOG=y
 # CONFIG_SYSLOG_TIMESTAMP is not set
 CONFIG_SYSLOG_CHAR=y
 CONFIG_SYSLOG_DEVPATH="/dev/ttyS0"
diff --git a/configs/stm32f4discovery/winbuild/defconfig b/configs/stm32f4discovery/winbuild/defconfig
index fa2cc94cab5..e52bc101ae3 100644
--- a/configs/stm32f4discovery/winbuild/defconfig
+++ b/configs/stm32f4discovery/winbuild/defconfig
@@ -715,7 +715,7 @@ CONFIG_USART2_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -749,7 +749,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/stm32f746-ws/include/board.h b/configs/stm32f746-ws/include/board.h
index 1f5e3f030cf..2a64e967fec 100644
--- a/configs/stm32f746-ws/include/board.h
+++ b/configs/stm32f746-ws/include/board.h
@@ -122,6 +122,55 @@
 #define STM32_SYSCLK_FREQUENCY  (STM32_VCO_FREQUENCY / 2)
 #define STM32_OTGFS_FREQUENCY   (STM32_VCO_FREQUENCY / 9)
 
+/* Configure factors for  PLLSAI clock */
+
+
+#define STM32_RCC_PLLSAICFGR_PLLSAIN    RCC_PLLSAICFGR_PLLSAIN(192)
+#define STM32_RCC_PLLSAICFGR_PLLSAIP    RCC_PLLSAICFGR_PLLSAIP(2)
+#define STM32_RCC_PLLSAICFGR_PLLSAIQ    RCC_PLLSAICFGR_PLLSAIQ(2)
+#define STM32_RCC_PLLSAICFGR_PLLSAIR    RCC_PLLSAICFGR_PLLSAIR(2)
+
+/* Configure Dedicated Clock Configuration Register */
+
+#define STM32_RCC_DCKCFGR1_PLLI2SDIVQ  RCC_DCKCFGR1_PLLI2SDIVQ(1)
+#define STM32_RCC_DCKCFGR1_PLLSAIDIVQ  RCC_DCKCFGR1_PLLSAIDIVQ(1)
+#define STM32_RCC_DCKCFGR1_PLLSAIDIVR  RCC_DCKCFGR1_PLLSAIDIVR(0)
+#define STM32_RCC_DCKCFGR1_SAI1SRC     RCC_DCKCFGR1_SAI1SEL(0)
+#define STM32_RCC_DCKCFGR1_SAI2SRC     RCC_DCKCFGR1_SAI2SEL(0)
+#define STM32_RCC_DCKCFGR1_TIMPRESRC   0
+#define STM32_RCC_DCKCFGR1_DFSDM1SRC   0
+#define STM32_RCC_DCKCFGR1_ADFSDM1SRC  0
+
+
+
+/* Configure factors for  PLLI2S clock */
+
+#define STM32_RCC_PLLI2SCFGR_PLLI2SN   RCC_PLLI2SCFGR_PLLI2SN(192)
+#define STM32_RCC_PLLI2SCFGR_PLLI2SP   RCC_PLLI2SCFGR_PLLI2SP(2)
+#define STM32_RCC_PLLI2SCFGR_PLLI2SQ   RCC_PLLI2SCFGR_PLLI2SQ(2)
+#define STM32_RCC_PLLI2SCFGR_PLLI2SR   RCC_PLLI2SCFGR_PLLI2SR(2)
+
+/* Configure Dedicated Clock Configuration Register 2 */
+
+#define STM32_RCC_DCKCFGR2_USART1SRC  RCC_DCKCFGR2_USART1SEL_APB
+#define STM32_RCC_DCKCFGR2_USART2SRC  RCC_DCKCFGR2_USART2SEL_APB
+#define STM32_RCC_DCKCFGR2_UART4SRC   RCC_DCKCFGR2_UART4SEL_APB
+#define STM32_RCC_DCKCFGR2_UART5SRC   RCC_DCKCFGR2_UART5SEL_APB
+#define STM32_RCC_DCKCFGR2_USART6SRC  RCC_DCKCFGR2_USART6SEL_APB
+#define STM32_RCC_DCKCFGR2_UART7SRC   RCC_DCKCFGR2_UART7SEL_APB
+#define STM32_RCC_DCKCFGR2_UART8SRC   RCC_DCKCFGR2_UART8SEL_APB
+#define STM32_RCC_DCKCFGR2_I2C1SRC    RCC_DCKCFGR2_I2C1SEL_HSI
+#define STM32_RCC_DCKCFGR2_I2C2SRC    RCC_DCKCFGR2_I2C2SEL_HSI
+#define STM32_RCC_DCKCFGR2_I2C3SRC    RCC_DCKCFGR2_I2C3SEL_HSI
+#define STM32_RCC_DCKCFGR2_I2C4SRC    RCC_DCKCFGR2_I2C4SEL_HSI
+#define STM32_RCC_DCKCFGR2_LPTIM1SRC  RCC_DCKCFGR2_LPTIM1SEL_APB
+#define STM32_RCC_DCKCFGR2_CECSRC     RCC_DCKCFGR2_CECSEL_HSI
+#define STM32_RCC_DCKCFGR2_CK48MSRC   RCC_DCKCFGR2_CK48MSEL_PLLSAI
+#define STM32_RCC_DCKCFGR2_SDMMCSRC   RCC_DCKCFGR2_SDMMCSEL_48MHZ
+#define STM32_RCC_DCKCFGR2_SDMMC2SRC  RCC_DCKCFGR2_SDMMC2SEL_48MHZ
+#define STM32_RCC_DCKCFGR2_DSISRC     RCC_DCKCFGR2_DSISEL_48MHZ
+
+
 /* Several prescalers allow the configuration of the two AHB buses, the
  * high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum
  * frequency of the two AHB buses is 216 MHz while the maximum frequency of
@@ -165,14 +214,6 @@
 #define STM32_APB2_TIM10_CLKIN  (2*STM32_PCLK2_FREQUENCY)
 #define STM32_APB2_TIM11_CLKIN  (2*STM32_PCLK2_FREQUENCY)
 
-/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx
- * otherwise frequency is 2xAPBx.
- * Note: TIM1,8 are on APB2, others on APB1
- */
-
-#define STM32_TIM18_FREQUENCY   (2*STM32_PCLK2_FREQUENCY)
-#define STM32_TIM27_FREQUENCY   (2*STM32_PCLK1_FREQUENCY)
-
 /* FLASH wait states
  *
  *  --------- ---------- -----------
@@ -210,12 +251,13 @@
 #define GPIO_SPI1_MISO GPIO_SPI1_MISO_1
 #define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_1
 
-#define GPIO_I2C1_SCL GPIO_I2C1_SCL_1
-#define GPIO_I2C1_SDA GPIO_I2C1_SDA_1
+#define GPIO_I2C1_SCL  GPIO_I2C1_SCL_1
+#define GPIO_I2C1_SDA  GPIO_I2C1_SDA_1
 
 /************************************************************************************
  * Public Data
  ************************************************************************************/
+
 #ifndef __ASSEMBLY__
 
 #undef EXTERN
diff --git a/configs/stm32f746-ws/nsh/defconfig b/configs/stm32f746-ws/nsh/defconfig
index df3654343f0..a45d8a824a5 100644
--- a/configs/stm32f746-ws/nsh/defconfig
+++ b/configs/stm32f746-ws/nsh/defconfig
@@ -16,7 +16,7 @@ CONFIG_HOST_LINUX=y
 #
 # Build Configuration
 #
-CONFIG_APPS_DIR="../apps"
+# CONFIG_APPS_DIR="../apps"
 CONFIG_BUILD_FLAT=y
 # CONFIG_BUILD_2PASS is not set
 
@@ -43,9 +43,10 @@ CONFIG_ARCH_STDARG_H=y
 # Debug Options
 #
 # CONFIG_DEBUG_FEATURES is not set
-CONFIG_ARCH_HAVE_HEAPCHECK=y
 CONFIG_ARCH_HAVE_STACKCHECK=y
 CONFIG_STACK_COLORATION=y
+CONFIG_ARCH_HAVE_HEAPCHECK=y
+# CONFIG_HEAP_COLORATION is not set
 CONFIG_DEBUG_SYMBOLS=y
 CONFIG_ARCH_HAVE_CUSTOMOPT=y
 CONFIG_DEBUG_NOOPT=y
@@ -124,7 +125,7 @@ CONFIG_ARCH_HAVE_CMNVECTOR=y
 CONFIG_ARMV7M_CMNVECTOR=y
 # CONFIG_ARMV7M_LAZYFPU is not set
 CONFIG_ARCH_HAVE_FPU=y
-CONFIG_ARCH_HAVE_DPFPU=y
+# CONFIG_ARCH_HAVE_DPFPU is not set
 CONFIG_ARCH_FPU=y
 # CONFIG_ARCH_HAVE_TRUSTZONE is not set
 CONFIG_ARM_HAVE_MPU_UNIFIED=y
@@ -151,29 +152,126 @@ CONFIG_ARMV7M_HAVE_STACKCHECK=y
 # CONFIG_ARMV7M_STACKCHECK is not set
 # CONFIG_ARMV7M_ITMSYSLOG is not set
 # CONFIG_SERIAL_TERMIOS is not set
+# CONFIG_USART6_RS485 is not set
+# CONFIG_SERIAL_DISABLE_REORDERING is not set
 
 #
 # STM32 F7 Configuration Options
 #
-
+# CONFIG_ARCH_CHIP_STM32F745VG is not set
+# CONFIG_ARCH_CHIP_STM32F745VE is not set
+# CONFIG_ARCH_CHIP_STM32F745IG is not set
+# CONFIG_ARCH_CHIP_STM32F745IE is not set
+# CONFIG_ARCH_CHIP_STM32F745ZE is not set
+# CONFIG_ARCH_CHIP_STM32F745ZG is not set
+# CONFIG_ARCH_CHIP_STM32F746BG is not set
+# CONFIG_ARCH_CHIP_STM32F746VG is not set
+# CONFIG_ARCH_CHIP_STM32F746VE is not set
+# CONFIG_ARCH_CHIP_STM32F746BE is not set
+# CONFIG_ARCH_CHIP_STM32F746ZG is not set
+# CONFIG_ARCH_CHIP_STM32F746IE is not set
+# CONFIG_ARCH_CHIP_STM32F746NG is not set
+# CONFIG_ARCH_CHIP_STM32F746NE is not set
+# CONFIG_ARCH_CHIP_STM32F746ZE is not set
 CONFIG_ARCH_CHIP_STM32F746IG=y
-# CONFIG_ARCH_CHIP_STM32F756 is not set
+# CONFIG_ARCH_CHIP_STM32F756NG is not set
+# CONFIG_ARCH_CHIP_STM32F756BG is not set
+# CONFIG_ARCH_CHIP_STM32F756IG is not set
+# CONFIG_ARCH_CHIP_STM32F756VG is not set
+# CONFIG_ARCH_CHIP_STM32F756ZG is not set
+# CONFIG_ARCH_CHIP_STM32F765NI is not set
+# CONFIG_ARCH_CHIP_STM32F765VI is not set
+# CONFIG_ARCH_CHIP_STM32F765VG is not set
+# CONFIG_ARCH_CHIP_STM32F765BI is not set
+# CONFIG_ARCH_CHIP_STM32F765NG is not set
+# CONFIG_ARCH_CHIP_STM32F765ZG is not set
+# CONFIG_ARCH_CHIP_STM32F765ZI is not set
+# CONFIG_ARCH_CHIP_STM32F765IG is not set
+# CONFIG_ARCH_CHIP_STM32F765BG is not set
+# CONFIG_ARCH_CHIP_STM32F765II is not set
+# CONFIG_ARCH_CHIP_STM32F767NG is not set
+# CONFIG_ARCH_CHIP_STM32F767IG is not set
+# CONFIG_ARCH_CHIP_STM32F767VG is not set
+# CONFIG_ARCH_CHIP_STM32F767ZG is not set
+# CONFIG_ARCH_CHIP_STM32F767NI is not set
+# CONFIG_ARCH_CHIP_STM32F767VI is not set
+# CONFIG_ARCH_CHIP_STM32F767BG is not set
+# CONFIG_ARCH_CHIP_STM32F767ZI is not set
+# CONFIG_ARCH_CHIP_STM32F767II is not set
+# CONFIG_ARCH_CHIP_STM32F769BI is not set
+# CONFIG_ARCH_CHIP_STM32F769II is not set
+# CONFIG_ARCH_CHIP_STM32F769BG is not set
+# CONFIG_ARCH_CHIP_STM32F769NI is not set
+# CONFIG_ARCH_CHIP_STM32F769AI is not set
+# CONFIG_ARCH_CHIP_STM32F769NG is not set
+# CONFIG_ARCH_CHIP_STM32F769IG is not set
+# CONFIG_ARCH_CHIP_STM32F777ZI is not set
+# CONFIG_ARCH_CHIP_STM32F777VI is not set
+# CONFIG_ARCH_CHIP_STM32F777NI is not set
+# CONFIG_ARCH_CHIP_STM32F777BI is not set
+# CONFIG_ARCH_CHIP_STM32F777II is not set
+# CONFIG_ARCH_CHIP_STM32F778AI is not set
+# CONFIG_ARCH_CHIP_STM32F779II is not set
+# CONFIG_ARCH_CHIP_STM32F779NI is not set
+# CONFIG_ARCH_CHIP_STM32F779BI is not set
+# CONFIG_ARCH_CHIP_STM32F779AI is not set
 CONFIG_STM32F7_STM32F74XX=y
 # CONFIG_STM32F7_STM32F75XX is not set
-# CONFIG_STM32F7_FLASH_512KB is not set
-CONFIG_STM32F7_FLASH_1024KB=y
+# CONFIG_STM32F7_STM32F76XX is not set
+# CONFIG_STM32F7_STM32F77XX is not set
+# CONFIG_STM32F7_IO_CONFIG_V is not set
+CONFIG_STM32F7_IO_CONFIG_I=y
+# CONFIG_STM32F7_IO_CONFIG_Z is not set
+# CONFIG_STM32F7_IO_CONFIG_N is not set
+# CONFIG_STM32F7_IO_CONFIG_B is not set
+# CONFIG_STM32F7_IO_CONFIG_A is not set
+# CONFIG_STM32F7_STM32F745XX is not set
+CONFIG_STM32F7_STM32F746XX=y
+# CONFIG_STM32F7_STM32F756XX is not set
+# CONFIG_STM32F7_STM32F765XX is not set
+# CONFIG_STM32F7_STM32F767XX is not set
+# CONFIG_STM32F7_STM32F768XX is not set
+# CONFIG_STM32F7_STM32F768AX is not set
+# CONFIG_STM32F7_STM32F769XX is not set
+# CONFIG_STM32F7_STM32F769AX is not set
+# CONFIG_STM32F7_STM32F777XX is not set
+# CONFIG_STM32F7_STM32F778XX is not set
+# CONFIG_STM32F7_STM32F778AX is not set
+# CONFIG_STM32F7_STM32F779XX is not set
+# CONFIG_STM32F7_STM32F779AX is not set
+# CONFIG_STM32F7_FLASH_CONFIG_E is not set
+# CONFIG_STM32F7_FLASH_CONFIG_I is not set
+CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT=y
+# CONFIG_STM32F7_FLASH_OVERRIDE_E is not set
+# CONFIG_STM32F7_FLASH_OVERRIDE_G is not set
+# CONFIG_STM32F7_FLASH_OVERRIDE_I is not set
 
 #
 # STM32 Peripheral Support
 #
 CONFIG_STM32F7_HAVE_LTDC=y
-# CONFIG_STM32F7_ADC is not set
+CONFIG_STM32F7_HAVE_FSMC=y
+CONFIG_STM32F7_HAVE_ETHRNET=y
+CONFIG_STM32F7_HAVE_RNG=y
+CONFIG_STM32F7_HAVE_SPI5=y
+CONFIG_STM32F7_HAVE_SPI6=y
+# CONFIG_STM32F7_HAVE_SDMMC2 is not set
+# CONFIG_STM32F7_HAVE_CAN3 is not set
+CONFIG_STM32F7_HAVE_DCMI=y
+# CONFIG_STM32F7_HAVE_DSIHOST is not set
+CONFIG_STM32F7_HAVE_DMA2D=y
+# CONFIG_STM32F7_HAVE_JPEG is not set
+# CONFIG_STM32F7_HAVE_CRYP is not set
+# CONFIG_STM32F7_HAVE_HASH is not set
+# CONFIG_STM32F7_HAVE_DFSDM1 is not set
+CONFIG_STM32F7_ADC=y
 # CONFIG_STM32F7_CAN is not set
 # CONFIG_STM32F7_DAC is not set
 # CONFIG_STM32F7_DMA is not set
 CONFIG_STM32F7_I2C=y
 # CONFIG_STM32F7_SAI is not set
 CONFIG_STM32F7_SPI=y
+# CONFIG_STM32F7_TIM is not set
 CONFIG_STM32F7_USART=y
 CONFIG_STM32F7_ADC1=y
 # CONFIG_STM32F7_ADC2 is not set
@@ -183,12 +281,12 @@ CONFIG_STM32F7_ADC1=y
 # CONFIG_STM32F7_CAN2 is not set
 # CONFIG_STM32F7_CEC is not set
 # CONFIG_STM32F7_CRC is not set
-# CONFIG_STM32F7_CRYP is not set
 # CONFIG_STM32F7_DMA1 is not set
 # CONFIG_STM32F7_DMA2 is not set
 # CONFIG_STM32F7_DAC1 is not set
 # CONFIG_STM32F7_DAC2 is not set
 # CONFIG_STM32F7_DCMI is not set
+# CONFIG_STM32F7_DMA2D is not set
 # CONFIG_STM32F7_ETHMAC is not set
 # CONFIG_STM32F7_FSMC is not set
 CONFIG_STM32F7_I2C1=y
@@ -196,12 +294,11 @@ CONFIG_STM32F7_I2C1=y
 # CONFIG_STM32F7_I2C3 is not set
 # CONFIG_STM32F7_LPTIM1 is not set
 # CONFIG_STM32F7_LTDC is not set
-# CONFIG_STM32F7_DMA2D is not set
 # CONFIG_STM32F7_OTGFS is not set
 # CONFIG_STM32F7_OTGHS is not set
 # CONFIG_STM32F7_QUADSPI is not set
-# CONFIG_STM32F7_SAI1 is not set
 # CONFIG_STM32F7_RNG is not set
+# CONFIG_STM32F7_SAI1 is not set
 # CONFIG_STM32F7_SAI2 is not set
 # CONFIG_STM32F7_SDMMC1 is not set
 # CONFIG_STM32F7_SPDIFRX is not set
@@ -236,6 +333,18 @@ CONFIG_STM32F7_USART6=y
 # CONFIG_STM32F7_UART8 is not set
 # CONFIG_STM32F7_IWDG is not set
 # CONFIG_STM32F7_WWDG is not set
+
+#
+# U[S]ART Configuration
+#
+# CONFIG_STM32F7_FLOWCONTROL_BROKEN is not set
+# CONFIG_STM32F7_USART_BREAKS is not set
+
+#
+# SPI Configuration
+#
+# CONFIG_STM32F7_SPI_INTERRUPTS is not set
+# CONFIG_STM32F7_SPI_DMA is not set
 # CONFIG_STM32F7_CUSTOM_CLOCKCONFIG is not set
 
 #
@@ -299,7 +408,6 @@ CONFIG_RAM_SIZE=245760
 #
 # Board Selection
 #
-# CONFIG_ARCH_BOARD_STM32F746G_DISCO is not set
 CONFIG_ARCH_BOARD_STM32F746_WS=y
 # CONFIG_ARCH_BOARD_CUSTOM is not set
 CONFIG_ARCH_BOARD="stm32f746-ws"
@@ -307,18 +415,18 @@ CONFIG_ARCH_BOARD="stm32f746-ws"
 #
 # Common Board Options
 #
-# CONFIG_ARCH_HAVE_LEDS  is not set
-# CONFIG_ARCH_LEDS  is not set
-# CONFIG_ARCH_HAVE_BUTTONS  is not set
-# CONFIG_ARCH_BUTTONS  is not set
-# CONFIG_ARCH_HAVE_IRQBUTTONS  is not set
-# CONFIG_ARCH_IRQBUTTONS is not set
 CONFIG_NSH_MMCSDMINOR=0
 
 #
 # Board-Specific Options
 #
 CONFIG_LIB_BOARDCTL=y
+# CONFIG_BOARDCTL_UNIQUEID is not set
+# CONFIG_BOARDCTL_TSCTEST is not set
+# CONFIG_BOARDCTL_ADCTEST is not set
+# CONFIG_BOARDCTL_PWMTEST is not set
+# CONFIG_BOARDCTL_GRAPHICS is not set
+# CONFIG_BOARDCTL_IOCTL is not set
 
 #
 # RTOS Features
@@ -370,6 +478,7 @@ CONFIG_NPTHREAD_KEYS=4
 #
 # CONFIG_SCHED_CPULOAD is not set
 CONFIG_SCHED_INSTRUMENTATION=y
+# CONFIG_SCHED_INSTRUMENTATION_PREEMPTION is not set
 CONFIG_SCHED_INSTRUMENTATION_BUFFER=y
 CONFIG_SCHED_NOTE_BUFSIZE=512
 
@@ -392,6 +501,7 @@ CONFIG_NAME_MAX=32
 # CONFIG_SCHED_STARTHOOK is not set
 # CONFIG_SCHED_ATEXIT is not set
 # CONFIG_SCHED_ONEXIT is not set
+# CONFIG_SIG_EVTHREAD is not set
 
 #
 # Signal Numbers
@@ -420,7 +530,6 @@ CONFIG_SCHED_HPWORKSTACKSIZE=1800
 CONFIG_SCHED_LPWORK=y
 CONFIG_SCHED_LPNTHREADS=1
 CONFIG_SCHED_LPWORKPRIORITY=50
-CONFIG_SCHED_LPWORKPRIOMAX=176
 CONFIG_SCHED_LPWORKPERIOD=50000
 CONFIG_SCHED_LPWORKSTACKSIZE=1800
 
@@ -436,7 +545,7 @@ CONFIG_PTHREAD_STACK_DEFAULT=2048
 #
 # Device Drivers
 #
-#CONFIG_DISABLE_POLL is not set
+# CONFIG_DISABLE_POLL is not set
 CONFIG_DEV_NULL=y
 # CONFIG_DEV_ZERO is not set
 # CONFIG_DEV_LOOP is not set
@@ -453,7 +562,11 @@ CONFIG_DEV_NULL=y
 # CONFIG_PWM is not set
 CONFIG_ARCH_HAVE_I2CRESET=y
 CONFIG_I2C=y
+# CONFIG_I2C_SLAVE is not set
+# CONFIG_I2C_POLLED is not set
 CONFIG_I2C_RESET=y
+# CONFIG_I2C_TRACE is not set
+CONFIG_I2C_DRIVER=y
 CONFIG_SPI=y
 # CONFIG_SPI_SLAVE is not set
 CONFIG_SPI_EXCHANGE=y
@@ -462,29 +575,43 @@ CONFIG_SPI_EXCHANGE=y
 # CONFIG_SPI_BITBANG is not set
 # CONFIG_SPI_HWFEATURES is not set
 # CONFIG_SPI_CRCGENERATION is not set
+# CONFIG_SPI_CS_CONTROL is not set
+# CONFIG_SPI_CS_DELAY_CONTROL is not set
 # CONFIG_I2S is not set
-CONFIG_ADC=y
 
 #
 # Timer Driver Support
 #
 # CONFIG_TIMER is not set
+# CONFIG_RTC is not set
 CONFIG_WATCHDOG=y
 CONFIG_WATCHDOG_DEVPATH="/dev/watchdog0"
-# CONFIG_ANALOG is not set
+# CONFIG_TIMERS_CS2100CP is not set
+CONFIG_ANALOG=y
+CONFIG_ADC=y
+CONFIG_ADC_FIFOSIZE=8
+# CONFIG_ADC_ADS1242 is not set
+# CONFIG_ADC_ADS125X is not set
+# CONFIG_ADC_PGA11X is not set
+# CONFIG_DAC is not set
 # CONFIG_AUDIO_DEVICES is not set
 # CONFIG_VIDEO_DEVICES is not set
 # CONFIG_BCH is not set
 # CONFIG_INPUT is not set
 # CONFIG_IOEXPANDER is not set
+
+#
+# LCD Driver Support
+#
 # CONFIG_LCD is not set
+# CONFIG_SLCD is not set
 
 #
 # LED Support
 #
-# CONFIG_USERLED is not set
 # CONFIG_RGBLED is not set
 # CONFIG_PCA9635PW is not set
+# CONFIG_NCP5623C is not set
 # CONFIG_MMCSD is not set
 # CONFIG_MODEM is not set
 # CONFIG_MTD is not set
@@ -502,7 +629,7 @@ CONFIG_SERIAL=y
 # CONFIG_UART1_SERIALDRIVER is not set
 # CONFIG_UART2_SERIALDRIVER is not set
 # CONFIG_UART3_SERIALDRIVER is not set
-# CONFIG_UART4_SERIALDRIVER is not set 
+# CONFIG_UART4_SERIALDRIVER is not set
 # CONFIG_UART5_SERIALDRIVER is not set
 # CONFIG_UART6_SERIALDRIVER is not set
 # CONFIG_UART7_SERIALDRIVER is not set
@@ -515,13 +642,13 @@ CONFIG_SERIAL=y
 # CONFIG_USART3_SERIALDRIVER is not set
 # CONFIG_USART4_SERIALDRIVER is not set
 # CONFIG_USART5_SERIALDRIVER is not set
-
-#
-# USART Configuration
-#
 CONFIG_USART6_SERIALDRIVER=y
+# CONFIG_USART7_SERIALDRIVER is not set
+# CONFIG_USART8_SERIALDRIVER is not set
+# CONFIG_OTHER_UART_SERIALDRIVER is not set
 CONFIG_MCU_SERIAL=y
 CONFIG_STANDARD_SERIAL=y
+CONFIG_SERIAL_NPOLLWAITERS=2
 # CONFIG_SERIAL_IFLOWCONTROL is not set
 # CONFIG_SERIAL_OFLOWCONTROL is not set
 # CONFIG_SERIAL_DMA is not set
@@ -554,7 +681,8 @@ CONFIG_USART6_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
+# CONFIG_DRIVER_NOTE is not set
 
 #
 # Networking Support
@@ -580,6 +708,7 @@ CONFIG_USART6_2STOP=0
 # CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set
 # CONFIG_FS_READABLE is not set
 # CONFIG_FS_WRITABLE is not set
+# CONFIG_FS_AIO is not set
 # CONFIG_FS_NAMED_SEMAPHORES is not set
 CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 # CONFIG_FS_RAMMAP is not set
@@ -595,7 +724,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
@@ -658,6 +786,7 @@ CONFIG_EOL_IS_EITHER_CRLF=y
 CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=1024
 CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=2048
 CONFIG_LIBC_STRERROR=y
+# CONFIG_LIBC_STRERROR_SHORT is not set
 # CONFIG_LIBC_PERROR_STDOUT is not set
 CONFIG_ARCH_LOWPUTC=y
 # CONFIG_LIBC_LOCALTIME is not set
@@ -672,6 +801,7 @@ CONFIG_ARCH_HAVE_TLS=y
 #
 # Non-standard Library Support
 #
+# CONFIG_LIB_CRC64_FAST is not set
 # CONFIG_LIB_KBDCODEC is not set
 # CONFIG_LIB_SLCDCODEC is not set
 
@@ -704,7 +834,7 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024
 #
 # Examples
 #
-# CONFIG_EXAMPLES_BUTTONS is not set
+# CONFIG_EXAMPLES_ADC is not set
 # CONFIG_EXAMPLES_CHAT is not set
 # CONFIG_EXAMPLES_CONFIGDATA is not set
 # CONFIG_EXAMPLES_CPUHOG is not set
@@ -715,10 +845,10 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024
 # CONFIG_EXAMPLES_FTPD is not set
 # CONFIG_EXAMPLES_HELLO is not set
 # CONFIG_EXAMPLES_HELLOXX is not set
-# CONFIG_EXAMPLES_JSON is not set
 # CONFIG_EXAMPLES_HIDKBD is not set
-# CONFIG_EXAMPLES_KEYPADTEST is not set
 # CONFIG_EXAMPLES_IGMP is not set
+# CONFIG_EXAMPLES_JSON is not set
+# CONFIG_EXAMPLES_KEYPADTEST is not set
 # CONFIG_EXAMPLES_MEDIA is not set
 # CONFIG_EXAMPLES_MM is not set
 # CONFIG_EXAMPLES_MODBUS is not set
@@ -728,17 +858,17 @@ CONFIG_EXAMPLES_NSH=y
 # CONFIG_EXAMPLES_NSH_CXXINITIALIZE is not set
 # CONFIG_EXAMPLES_NULL is not set
 # CONFIG_EXAMPLES_NX is not set
-# CONFIG_EXAMPLES_NXTERM is not set
 # CONFIG_EXAMPLES_NXFFS is not set
 # CONFIG_EXAMPLES_NXHELLO is not set
 # CONFIG_EXAMPLES_NXIMAGE is not set
 # CONFIG_EXAMPLES_NXLINES is not set
+# CONFIG_EXAMPLES_NXTERM is not set
 # CONFIG_EXAMPLES_NXTEXT is not set
 # CONFIG_EXAMPLES_OSTEST is not set
 # CONFIG_EXAMPLES_PCA9635 is not set
 # CONFIG_EXAMPLES_PIPE is not set
-# CONFIG_EXAMPLES_PPPD is not set
 # CONFIG_EXAMPLES_POSIXSPAWN is not set
+# CONFIG_EXAMPLES_PPPD is not set
 # CONFIG_EXAMPLES_RGBLED is not set
 # CONFIG_EXAMPLES_RGMP is not set
 # CONFIG_EXAMPLES_SENDMAIL is not set
@@ -746,16 +876,17 @@ CONFIG_EXAMPLES_NSH=y
 # CONFIG_EXAMPLES_SERIALRX is not set
 # CONFIG_EXAMPLES_SERLOOP is not set
 # CONFIG_EXAMPLES_SLCD is not set
-# CONFIG_EXAMPLES_SMART_TEST is not set
 # CONFIG_EXAMPLES_SMART is not set
+# CONFIG_EXAMPLES_SMART_TEST is not set
 # CONFIG_EXAMPLES_SMP is not set
 # CONFIG_EXAMPLES_TCPECHO is not set
 # CONFIG_EXAMPLES_TELNETD is not set
 # CONFIG_EXAMPLES_TIFF is not set
 # CONFIG_EXAMPLES_TOUCHSCREEN is not set
-# CONFIG_EXAMPLES_WEBSERVER is not set
+# CONFIG_EXAMPLES_USBSERIAL is not set
 # CONFIG_EXAMPLES_USBTERM is not set
 # CONFIG_EXAMPLES_WATCHDOG is not set
+# CONFIG_EXAMPLES_WEBSERVER is not set
 
 #
 # File System Utilities
@@ -777,8 +908,8 @@ CONFIG_EXAMPLES_NSH=y
 # Interpreters
 #
 # CONFIG_INTERPRETERS_FICL is not set
-# CONFIG_INTERPRETERS_PCODE is not set
 # CONFIG_INTERPRETERS_MICROPYTHON is not set
+# CONFIG_INTERPRETERS_PCODE is not set
 
 #
 # FreeModBus
@@ -788,7 +919,9 @@ CONFIG_EXAMPLES_NSH=y
 #
 # Network Utilities
 #
+# CONFIG_NETUTILS_CHAT is not set
 # CONFIG_NETUTILS_CODECS is not set
+# CONFIG_NETUTILS_ESP8266 is not set
 # CONFIG_NETUTILS_FTPC is not set
 # CONFIG_NETUTILS_JSON is not set
 # CONFIG_NETUTILS_SMTP is not set
@@ -872,6 +1005,7 @@ CONFIG_NSH_CMDOPT_DF_H=y
 CONFIG_NSH_CODECS_BUFSIZE=128
 CONFIG_NSH_CMDOPT_HEXDUMP=y
 CONFIG_NSH_FILEIOSIZE=512
+# CONFIG_NSH_STRERROR is not set
 
 #
 # Scripting Support
@@ -901,25 +1035,11 @@ CONFIG_NSH_ARCHINIT=y
 #
 # System Libraries and NSH Add-Ons
 #
-# CONFIG_SYSTEM_FREE is not set
 # CONFIG_SYSTEM_CLE is not set
 # CONFIG_SYSTEM_CUTERM is not set
-# CONFIG_SYSTEM_INSTALL is not set
+# CONFIG_SYSTEM_FREE is not set
 # CONFIG_SYSTEM_HEX2BIN is not set
 # CONFIG_SYSTEM_HEXED is not set
-# CONFIG_SYSTEM_RAMTEST is not set
-CONFIG_READLINE_HAVE_EXTMATCH=y
-CONFIG_SYSTEM_READLINE=y
-CONFIG_READLINE_ECHO=y
-# CONFIG_READLINE_TABCOMPLETION is not set
-# CONFIG_READLINE_CMD_HISTORY is not set
-# CONFIG_SYSTEM_SUDOKU is not set
-# CONFIG_SYSTEM_VI is not set
-# CONFIG_SYSTEM_UBLOXMODEM is not set
-# CONFIG_SYSTEM_ZMODEM is not set
-
-CONFIG_I2C_DRIVER=y
-
 CONFIG_SYSTEM_I2CTOOL=y
 CONFIG_I2CTOOL_MINBUS=1
 CONFIG_I2CTOOL_MAXBUS=1
@@ -927,4 +1047,15 @@ CONFIG_I2CTOOL_MINADDR=0x03
 CONFIG_I2CTOOL_MAXADDR=0x77
 CONFIG_I2CTOOL_MAXREGADDR=0xff
 CONFIG_I2CTOOL_DEFFREQ=100000
-
+# CONFIG_SYSTEM_INSTALL is not set
+# CONFIG_SYSTEM_RAMTEST is not set
+CONFIG_READLINE_HAVE_EXTMATCH=y
+CONFIG_SYSTEM_READLINE=y
+CONFIG_READLINE_ECHO=y
+# CONFIG_READLINE_TABCOMPLETION is not set
+# CONFIG_READLINE_CMD_HISTORY is not set
+# CONFIG_SYSTEM_STACKMONITOR is not set
+# CONFIG_SYSTEM_SUDOKU is not set
+# CONFIG_SYSTEM_UBLOXMODEM is not set
+# CONFIG_SYSTEM_VI is not set
+# CONFIG_SYSTEM_ZMODEM is not set
diff --git a/configs/stm32f746-ws/src/stm32_spi.c b/configs/stm32f746-ws/src/stm32_spi.c
index e973ca9b82b..517ea3761b2 100644
--- a/configs/stm32f746-ws/src/stm32_spi.c
+++ b/configs/stm32f746-ws/src/stm32_spi.c
@@ -101,7 +101,7 @@ void weak_function stm32_spidev_initialize(void)
 #ifdef CONFIG_STM32F7_SPI1
 void stm32_spi1select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected)
 {
-  spidbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert");
+  spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert");
 }
 
 uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
@@ -113,7 +113,7 @@ uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
 #ifdef CONFIG_STM32F7_SPI2
 void stm32_spi2select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected)
 {
-  spidbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert");
+  spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert");
 }
 
 uint8_t stm32_spi2status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
@@ -125,7 +125,7 @@ uint8_t stm32_spi2status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
 #ifdef CONFIG_STM32F7_SPI3
 void stm32_spi3select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected)
 {
-  spidbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert");
+  spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert");
 }
 
 uint8_t stm32_spi3status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
@@ -137,7 +137,7 @@ uint8_t stm32_spi3status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
 #ifdef CONFIG_STM32F7_SPI4
 void stm32_spi4select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected)
 {
-  spidbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert");
+  spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert");
 }
 
 uint8_t stm32_spi4status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
@@ -149,7 +149,7 @@ uint8_t stm32_spi4status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
 #ifdef CONFIG_STM32F7_SPI5
 void stm32_spi5select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected)
 {
-  spidbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert");
+  spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert");
 }
 
 uint8_t stm32_spi5status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
@@ -161,7 +161,7 @@ uint8_t stm32_spi5status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
 #ifdef CONFIG_STM32F7_SPI6
 void stm32_spi6select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected)
 {
-  spidbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert");
+  spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert");
 }
 
 uint8_t stm32_spi6status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
diff --git a/configs/stm32f746g-disco/include/board.h b/configs/stm32f746g-disco/include/board.h
index 6e9da62de0b..94823714990 100644
--- a/configs/stm32f746g-disco/include/board.h
+++ b/configs/stm32f746g-disco/include/board.h
@@ -154,6 +154,53 @@
 #define STM32_OTGFS_FREQUENCY   (STM32_VCO_FREQUENCY / 10)
 #endif
 
+/* Configure factors for  PLLSAI clock */
+
+#define STM32_RCC_PLLSAICFGR_PLLSAIN    RCC_PLLSAICFGR_PLLSAIN(192)
+#define STM32_RCC_PLLSAICFGR_PLLSAIP    RCC_PLLSAICFGR_PLLSAIP(2)
+#define STM32_RCC_PLLSAICFGR_PLLSAIQ    RCC_PLLSAICFGR_PLLSAIQ(2)
+#define STM32_RCC_PLLSAICFGR_PLLSAIR    RCC_PLLSAICFGR_PLLSAIR(2)
+
+/* Configure Dedicated Clock Configuration Register */
+
+#define STM32_RCC_DCKCFGR1_PLLI2SDIVQ  RCC_DCKCFGR1_PLLI2SDIVQ(1)
+#define STM32_RCC_DCKCFGR1_PLLSAIDIVQ  RCC_DCKCFGR1_PLLSAIDIVQ(1)
+#define STM32_RCC_DCKCFGR1_PLLSAIDIVR  RCC_DCKCFGR1_PLLSAIDIVR(0)
+#define STM32_RCC_DCKCFGR1_SAI1SRC     RCC_DCKCFGR1_SAI1SEL(0)
+#define STM32_RCC_DCKCFGR1_SAI2SRC     RCC_DCKCFGR1_SAI2SEL(0)
+#define STM32_RCC_DCKCFGR1_TIMPRESRC   0
+#define STM32_RCC_DCKCFGR1_DFSDM1SRC   0
+#define STM32_RCC_DCKCFGR1_ADFSDM1SRC  0
+
+
+
+/* Configure factors for  PLLI2S clock */
+
+#define STM32_RCC_PLLI2SCFGR_PLLI2SN   RCC_PLLI2SCFGR_PLLI2SN(192)
+#define STM32_RCC_PLLI2SCFGR_PLLI2SP   RCC_PLLI2SCFGR_PLLI2SP(2)
+#define STM32_RCC_PLLI2SCFGR_PLLI2SQ   RCC_PLLI2SCFGR_PLLI2SQ(2)
+#define STM32_RCC_PLLI2SCFGR_PLLI2SR   RCC_PLLI2SCFGR_PLLI2SR(2)
+
+/* Configure Dedicated Clock Configuration Register 2 */
+
+#define STM32_RCC_DCKCFGR2_USART1SRC  RCC_DCKCFGR2_USART1SEL_APB
+#define STM32_RCC_DCKCFGR2_USART2SRC  RCC_DCKCFGR2_USART2SEL_APB
+#define STM32_RCC_DCKCFGR2_UART4SRC   RCC_DCKCFGR2_UART4SEL_APB
+#define STM32_RCC_DCKCFGR2_UART5SRC   RCC_DCKCFGR2_UART5SEL_APB
+#define STM32_RCC_DCKCFGR2_USART6SRC  RCC_DCKCFGR2_USART6SEL_APB
+#define STM32_RCC_DCKCFGR2_UART7SRC   RCC_DCKCFGR2_UART7SEL_APB
+#define STM32_RCC_DCKCFGR2_UART8SRC   RCC_DCKCFGR2_UART8SEL_APB
+#define STM32_RCC_DCKCFGR2_I2C1SRC    RCC_DCKCFGR2_I2C1SEL_HSI
+#define STM32_RCC_DCKCFGR2_I2C2SRC    RCC_DCKCFGR2_I2C2SEL_HSI
+#define STM32_RCC_DCKCFGR2_I2C3SRC    RCC_DCKCFGR2_I2C3SEL_HSI
+#define STM32_RCC_DCKCFGR2_I2C4SRC    RCC_DCKCFGR2_I2C4SEL_HSI
+#define STM32_RCC_DCKCFGR2_LPTIM1SRC  RCC_DCKCFGR2_LPTIM1SEL_APB
+#define STM32_RCC_DCKCFGR2_CECSRC     RCC_DCKCFGR2_CECSEL_HSI
+#define STM32_RCC_DCKCFGR2_CK48MSRC   RCC_DCKCFGR2_CK48MSEL_PLLSAI
+#define STM32_RCC_DCKCFGR2_SDMMCSRC   RCC_DCKCFGR2_SDMMCSEL_48MHZ
+#define STM32_RCC_DCKCFGR2_SDMMC2SRC  RCC_DCKCFGR2_SDMMC2SEL_48MHZ
+#define STM32_RCC_DCKCFGR2_DSISRC     RCC_DCKCFGR2_DSISEL_48MHZ
+
 /* Several prescalers allow the configuration of the two AHB buses, the
  * high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum
  * frequency of the two AHB buses is 216 MHz while the maximum frequency of
diff --git a/configs/stm32f746g-disco/knsh/defconfig b/configs/stm32f746g-disco/knsh/defconfig
index 0d53e8c3f6d..d4d654a7953 100644
--- a/configs/stm32f746g-disco/knsh/defconfig
+++ b/configs/stm32f746g-disco/knsh/defconfig
@@ -554,7 +554,7 @@ CONFIG_USART6_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -594,7 +594,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/stm32f746g-disco/netnsh/defconfig b/configs/stm32f746g-disco/netnsh/defconfig
index ba5526141ba..f39e13dee5b 100644
--- a/configs/stm32f746g-disco/netnsh/defconfig
+++ b/configs/stm32f746g-disco/netnsh/defconfig
@@ -719,7 +719,7 @@ CONFIG_USART6_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -883,7 +883,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/stm32f746g-disco/nsh/defconfig b/configs/stm32f746g-disco/nsh/defconfig
index 564d647ad2c..03cd1f7505b 100644
--- a/configs/stm32f746g-disco/nsh/defconfig
+++ b/configs/stm32f746g-disco/nsh/defconfig
@@ -80,6 +80,7 @@ CONFIG_ARCH="arm"
 # CONFIG_ARCH_CHIP_DM320 is not set
 # CONFIG_ARCH_CHIP_EFM32 is not set
 # CONFIG_ARCH_CHIP_IMX1 is not set
+# CONFIG_ARCH_CHIP_IMX6 is not set
 # CONFIG_ARCH_CHIP_KINETIS is not set
 # CONFIG_ARCH_CHIP_KL is not set
 # CONFIG_ARCH_CHIP_LM is not set
@@ -98,6 +99,7 @@ CONFIG_ARCH="arm"
 # CONFIG_ARCH_CHIP_SAMV7 is not set
 # CONFIG_ARCH_CHIP_STM32 is not set
 CONFIG_ARCH_CHIP_STM32F7=y
+# CONFIG_ARCH_CHIP_STM32L4 is not set
 # CONFIG_ARCH_CHIP_STR71X is not set
 # CONFIG_ARCH_CHIP_TMS570 is not set
 # CONFIG_ARCH_CHIP_MOXART is not set
@@ -119,14 +121,16 @@ CONFIG_ARCH_CORTEXM7=y
 # CONFIG_ARCH_CORTEXR7F is not set
 CONFIG_ARCH_FAMILY="armv7-m"
 CONFIG_ARCH_CHIP="stm32f7"
+# CONFIG_ARM_TOOLCHAIN_IAR is not set
 CONFIG_ARM_TOOLCHAIN_GNU=y
 # CONFIG_ARMV7M_USEBASEPRI is not set
 CONFIG_ARCH_HAVE_CMNVECTOR=y
 CONFIG_ARMV7M_CMNVECTOR=y
 # CONFIG_ARMV7M_LAZYFPU is not set
 CONFIG_ARCH_HAVE_FPU=y
-CONFIG_ARCH_HAVE_DPFPU=y
+# CONFIG_ARCH_HAVE_DPFPU is not set
 # CONFIG_ARCH_FPU is not set
+# CONFIG_ARCH_HAVE_TRUSTZONE is not set
 CONFIG_ARM_HAVE_MPU_UNIFIED=y
 # CONFIG_ARM_MPU is not set
 
@@ -142,34 +146,134 @@ CONFIG_ARMV7M_HAVE_ITCM=y
 CONFIG_ARMV7M_HAVE_DTCM=y
 # CONFIG_ARMV7M_ITCM is not set
 CONFIG_ARMV7M_DTCM=y
+# CONFIG_ARMV7M_TOOLCHAIN_IARW is not set
 # CONFIG_ARMV7M_TOOLCHAIN_ATOLLIC is not set
 # CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT is not set
 # CONFIG_ARMV7M_TOOLCHAIN_CODEREDW is not set
 # CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW is not set
 # CONFIG_ARMV7M_TOOLCHAIN_DEVKITARM is not set
-# CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL is not set
-CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIW=y
+CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL=y
+# CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIW is not set
 # CONFIG_ARMV7M_TOOLCHAIN_RAISONANCE is not set
 CONFIG_ARMV7M_HAVE_STACKCHECK=y
 # CONFIG_ARMV7M_STACKCHECK is not set
 # CONFIG_ARMV7M_ITMSYSLOG is not set
 # CONFIG_SERIAL_TERMIOS is not set
+# CONFIG_USART6_RS485 is not set
+# CONFIG_SERIAL_DISABLE_REORDERING is not set
 
 #
 # STM32 F7 Configuration Options
 #
-# CONFIG_ARCH_CHIP_STM32F745 is not set
-CONFIG_ARCH_CHIP_STM32F746=y
-# CONFIG_ARCH_CHIP_STM32F756 is not set
+# CONFIG_ARCH_CHIP_STM32F745VG is not set
+# CONFIG_ARCH_CHIP_STM32F745VE is not set
+# CONFIG_ARCH_CHIP_STM32F745IG is not set
+# CONFIG_ARCH_CHIP_STM32F745IE is not set
+# CONFIG_ARCH_CHIP_STM32F745ZE is not set
+# CONFIG_ARCH_CHIP_STM32F745ZG is not set
+# CONFIG_ARCH_CHIP_STM32F746BG is not set
+# CONFIG_ARCH_CHIP_STM32F746VG is not set
+# CONFIG_ARCH_CHIP_STM32F746VE is not set
+# CONFIG_ARCH_CHIP_STM32F746BE is not set
+# CONFIG_ARCH_CHIP_STM32F746ZG is not set
+# CONFIG_ARCH_CHIP_STM32F746IE is not set
+CONFIG_ARCH_CHIP_STM32F746NG=y
+# CONFIG_ARCH_CHIP_STM32F746NE is not set
+# CONFIG_ARCH_CHIP_STM32F746ZE is not set
+# CONFIG_ARCH_CHIP_STM32F746IG is not set
+# CONFIG_ARCH_CHIP_STM32F756NG is not set
+# CONFIG_ARCH_CHIP_STM32F756BG is not set
+# CONFIG_ARCH_CHIP_STM32F756IG is not set
+# CONFIG_ARCH_CHIP_STM32F756VG is not set
+# CONFIG_ARCH_CHIP_STM32F756ZG is not set
+# CONFIG_ARCH_CHIP_STM32F765NI is not set
+# CONFIG_ARCH_CHIP_STM32F765VI is not set
+# CONFIG_ARCH_CHIP_STM32F765VG is not set
+# CONFIG_ARCH_CHIP_STM32F765BI is not set
+# CONFIG_ARCH_CHIP_STM32F765NG is not set
+# CONFIG_ARCH_CHIP_STM32F765ZG is not set
+# CONFIG_ARCH_CHIP_STM32F765ZI is not set
+# CONFIG_ARCH_CHIP_STM32F765IG is not set
+# CONFIG_ARCH_CHIP_STM32F765BG is not set
+# CONFIG_ARCH_CHIP_STM32F765II is not set
+# CONFIG_ARCH_CHIP_STM32F767NG is not set
+# CONFIG_ARCH_CHIP_STM32F767IG is not set
+# CONFIG_ARCH_CHIP_STM32F767VG is not set
+# CONFIG_ARCH_CHIP_STM32F767ZG is not set
+# CONFIG_ARCH_CHIP_STM32F767NI is not set
+# CONFIG_ARCH_CHIP_STM32F767VI is not set
+# CONFIG_ARCH_CHIP_STM32F767BG is not set
+# CONFIG_ARCH_CHIP_STM32F767ZI is not set
+# CONFIG_ARCH_CHIP_STM32F767II is not set
+# CONFIG_ARCH_CHIP_STM32F769BI is not set
+# CONFIG_ARCH_CHIP_STM32F769II is not set
+# CONFIG_ARCH_CHIP_STM32F769BG is not set
+# CONFIG_ARCH_CHIP_STM32F769NI is not set
+# CONFIG_ARCH_CHIP_STM32F769AI is not set
+# CONFIG_ARCH_CHIP_STM32F769NG is not set
+# CONFIG_ARCH_CHIP_STM32F769IG is not set
+# CONFIG_ARCH_CHIP_STM32F777ZI is not set
+# CONFIG_ARCH_CHIP_STM32F777VI is not set
+# CONFIG_ARCH_CHIP_STM32F777NI is not set
+# CONFIG_ARCH_CHIP_STM32F777BI is not set
+# CONFIG_ARCH_CHIP_STM32F777II is not set
+# CONFIG_ARCH_CHIP_STM32F778AI is not set
+# CONFIG_ARCH_CHIP_STM32F779II is not set
+# CONFIG_ARCH_CHIP_STM32F779NI is not set
+# CONFIG_ARCH_CHIP_STM32F779BI is not set
+# CONFIG_ARCH_CHIP_STM32F779AI is not set
 CONFIG_STM32F7_STM32F74XX=y
 # CONFIG_STM32F7_STM32F75XX is not set
-# CONFIG_STM32F7_FLASH_512KB is not set
-CONFIG_STM32F7_FLASH_1024KB=y
+# CONFIG_STM32F7_STM32F76XX is not set
+# CONFIG_STM32F7_STM32F77XX is not set
+# CONFIG_STM32F7_IO_CONFIG_V is not set
+# CONFIG_STM32F7_IO_CONFIG_I is not set
+# CONFIG_STM32F7_IO_CONFIG_Z is not set
+CONFIG_STM32F7_IO_CONFIG_N=y
+# CONFIG_STM32F7_IO_CONFIG_B is not set
+# CONFIG_STM32F7_IO_CONFIG_A is not set
+# CONFIG_STM32F7_STM32F745XX is not set
+CONFIG_STM32F7_STM32F746XX=y
+# CONFIG_STM32F7_STM32F756XX is not set
+# CONFIG_STM32F7_STM32F765XX is not set
+# CONFIG_STM32F7_STM32F767XX is not set
+# CONFIG_STM32F7_STM32F768XX is not set
+# CONFIG_STM32F7_STM32F768AX is not set
+# CONFIG_STM32F7_STM32F769XX is not set
+# CONFIG_STM32F7_STM32F769AX is not set
+# CONFIG_STM32F7_STM32F777XX is not set
+# CONFIG_STM32F7_STM32F778XX is not set
+# CONFIG_STM32F7_STM32F778AX is not set
+# CONFIG_STM32F7_STM32F779XX is not set
+# CONFIG_STM32F7_STM32F779AX is not set
+# CONFIG_STM32F7_FLASH_CONFIG_E is not set
+# CONFIG_STM32F7_FLASH_CONFIG_I is not set
+CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT=y
+# CONFIG_STM32F7_FLASH_OVERRIDE_E is not set
+# CONFIG_STM32F7_FLASH_OVERRIDE_G is not set
+# CONFIG_STM32F7_FLASH_OVERRIDE_I is not set
 
 #
 # STM32 Peripheral Support
 #
 CONFIG_STM32F7_HAVE_LTDC=y
+CONFIG_STM32F7_HAVE_FSMC=y
+CONFIG_STM32F7_HAVE_ETHRNET=y
+CONFIG_STM32F7_HAVE_RNG=y
+CONFIG_STM32F7_HAVE_SPI5=y
+CONFIG_STM32F7_HAVE_SPI6=y
+# CONFIG_STM32F7_HAVE_SDMMC2 is not set
+# CONFIG_STM32F7_HAVE_ADC1_DMA is not set
+# CONFIG_STM32F7_HAVE_ADC2_DMA is not set
+# CONFIG_STM32F7_HAVE_ADC3_DMA is not set
+# CONFIG_STM32F7_HAVE_CAN3 is not set
+CONFIG_STM32F7_HAVE_DCMI=y
+# CONFIG_STM32F7_HAVE_DSIHOST is not set
+CONFIG_STM32F7_HAVE_DMA2D=y
+# CONFIG_STM32F7_HAVE_JPEG is not set
+# CONFIG_STM32F7_HAVE_CRYP is not set
+# CONFIG_STM32F7_HAVE_HASH is not set
+# CONFIG_STM32F7_HAVE_DFSDM1 is not set
 # CONFIG_STM32F7_ADC is not set
 # CONFIG_STM32F7_CAN is not set
 # CONFIG_STM32F7_DAC is not set
@@ -177,34 +281,34 @@ CONFIG_STM32F7_HAVE_LTDC=y
 # CONFIG_STM32F7_I2C is not set
 # CONFIG_STM32F7_SAI is not set
 # CONFIG_STM32F7_SPI is not set
+# CONFIG_STM32F7_TIM is not set
 CONFIG_STM32F7_USART=y
 # CONFIG_STM32F7_ADC1 is not set
-# CONFIG_STM32F7_ADC2 is not set
 # CONFIG_STM32F7_ADC3 is not set
 # CONFIG_STM32F7_BKPSRAM is not set
 # CONFIG_STM32F7_CAN1 is not set
 # CONFIG_STM32F7_CAN2 is not set
 # CONFIG_STM32F7_CEC is not set
 # CONFIG_STM32F7_CRC is not set
-# CONFIG_STM32F7_CRYP is not set
 # CONFIG_STM32F7_DMA1 is not set
 # CONFIG_STM32F7_DMA2 is not set
 # CONFIG_STM32F7_DAC1 is not set
 # CONFIG_STM32F7_DAC2 is not set
 # CONFIG_STM32F7_DCMI is not set
+# CONFIG_STM32F7_DMA2D is not set
 # CONFIG_STM32F7_ETHMAC is not set
 # CONFIG_STM32F7_FSMC is not set
 # CONFIG_STM32F7_I2C1 is not set
 # CONFIG_STM32F7_I2C2 is not set
 # CONFIG_STM32F7_I2C3 is not set
+# CONFIG_STM32F7_I2C4 is not set
 # CONFIG_STM32F7_LPTIM1 is not set
 # CONFIG_STM32F7_LTDC is not set
-# CONFIG_STM32F7_DMA2D is not set
 # CONFIG_STM32F7_OTGFS is not set
 # CONFIG_STM32F7_OTGHS is not set
 # CONFIG_STM32F7_QUADSPI is not set
-# CONFIG_STM32F7_SAI1 is not set
 # CONFIG_STM32F7_RNG is not set
+# CONFIG_STM32F7_SAI1 is not set
 # CONFIG_STM32F7_SAI2 is not set
 # CONFIG_STM32F7_SDMMC1 is not set
 # CONFIG_STM32F7_SPDIFRX is not set
@@ -228,7 +332,6 @@ CONFIG_STM32F7_USART=y
 # CONFIG_STM32F7_TIM12 is not set
 # CONFIG_STM32F7_TIM13 is not set
 # CONFIG_STM32F7_TIM14 is not set
-# CONFIG_STM32F7_TIM15 is not set
 # CONFIG_STM32F7_USART1 is not set
 # CONFIG_STM32F7_USART2 is not set
 # CONFIG_STM32F7_USART3 is not set
@@ -239,8 +342,18 @@ CONFIG_STM32F7_USART6=y
 # CONFIG_STM32F7_UART8 is not set
 # CONFIG_STM32F7_IWDG is not set
 # CONFIG_STM32F7_WWDG is not set
+
+#
+# U[S]ART Configuration
+#
+# CONFIG_STM32F7_FLOWCONTROL_BROKEN is not set
+# CONFIG_STM32F7_USART_BREAKS is not set
 # CONFIG_STM32F7_CUSTOM_CLOCKCONFIG is not set
 
+#
+# Timer Configuration
+#
+
 #
 # Architecture Options
 #
@@ -452,6 +565,8 @@ CONFIG_SPI_EXCHANGE=y
 # CONFIG_SPI_BITBANG is not set
 # CONFIG_SPI_HWFEATURES is not set
 # CONFIG_SPI_CRCGENERATION is not set
+# CONFIG_SPI_CS_CONTROL is not set
+# CONFIG_SPI_CS_DELAY_CONTROL is not set
 # CONFIG_I2S is not set
 
 #
@@ -466,7 +581,12 @@ CONFIG_SPI_EXCHANGE=y
 # CONFIG_BCH is not set
 # CONFIG_INPUT is not set
 # CONFIG_IOEXPANDER is not set
+
+#
+# LCD Driver Support
+#
 # CONFIG_LCD is not set
+# CONFIG_SLCD is not set
 
 #
 # LED Support
@@ -474,6 +594,7 @@ CONFIG_SPI_EXCHANGE=y
 # CONFIG_USERLED is not set
 # CONFIG_RGBLED is not set
 # CONFIG_PCA9635PW is not set
+# CONFIG_NCP5623C is not set
 # CONFIG_MMCSD is not set
 # CONFIG_MODEM is not set
 # CONFIG_MTD is not set
@@ -508,10 +629,6 @@ CONFIG_USART6_SERIALDRIVER=y
 # CONFIG_USART7_SERIALDRIVER is not set
 # CONFIG_USART8_SERIALDRIVER is not set
 # CONFIG_OTHER_UART_SERIALDRIVER is not set
-
-#
-# USART Configuration
-#
 CONFIG_MCU_SERIAL=y
 CONFIG_STANDARD_SERIAL=y
 # CONFIG_SERIAL_IFLOWCONTROL is not set
@@ -546,7 +663,7 @@ CONFIG_USART6_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -587,7 +704,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
@@ -655,11 +771,14 @@ CONFIG_ARCH_LOWPUTC=y
 CONFIG_LIB_SENDFILE_BUFSIZE=512
 # CONFIG_ARCH_ROMGETC is not set
 # CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set
+CONFIG_ARCH_HAVE_TLS=y
+# CONFIG_TLS is not set
 # CONFIG_LIBC_NETDB is not set
 
 #
 # Non-standard Library Support
 #
+# CONFIG_LIB_CRC64_FAST is not set
 # CONFIG_LIB_KBDCODEC is not set
 # CONFIG_LIB_SLCDCODEC is not set
 
@@ -703,10 +822,10 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024
 # CONFIG_EXAMPLES_FTPD is not set
 # CONFIG_EXAMPLES_HELLO is not set
 # CONFIG_EXAMPLES_HELLOXX is not set
-# CONFIG_EXAMPLES_JSON is not set
 # CONFIG_EXAMPLES_HIDKBD is not set
-# CONFIG_EXAMPLES_KEYPADTEST is not set
 # CONFIG_EXAMPLES_IGMP is not set
+# CONFIG_EXAMPLES_JSON is not set
+# CONFIG_EXAMPLES_KEYPADTEST is not set
 # CONFIG_EXAMPLES_MEDIA is not set
 # CONFIG_EXAMPLES_MM is not set
 # CONFIG_EXAMPLES_MODBUS is not set
@@ -715,18 +834,18 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024
 CONFIG_EXAMPLES_NSH=y
 CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y
 # CONFIG_EXAMPLES_NULL is not set
-# CONFIG_EXAMPLES_NX is not set
-# CONFIG_EXAMPLES_NXTERM is not set
 # CONFIG_EXAMPLES_NXFFS is not set
 # CONFIG_EXAMPLES_NXHELLO is not set
 # CONFIG_EXAMPLES_NXIMAGE is not set
+# CONFIG_EXAMPLES_NX is not set
 # CONFIG_EXAMPLES_NXLINES is not set
+# CONFIG_EXAMPLES_NXTERM is not set
 # CONFIG_EXAMPLES_NXTEXT is not set
 # CONFIG_EXAMPLES_OSTEST is not set
 # CONFIG_EXAMPLES_PCA9635 is not set
 # CONFIG_EXAMPLES_PIPE is not set
-# CONFIG_EXAMPLES_PPPD is not set
 # CONFIG_EXAMPLES_POSIXSPAWN is not set
+# CONFIG_EXAMPLES_PPPD is not set
 # CONFIG_EXAMPLES_RGBLED is not set
 # CONFIG_EXAMPLES_RGMP is not set
 # CONFIG_EXAMPLES_SENDMAIL is not set
@@ -734,17 +853,16 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y
 # CONFIG_EXAMPLES_SERIALRX is not set
 # CONFIG_EXAMPLES_SERLOOP is not set
 # CONFIG_EXAMPLES_SLCD is not set
-# CONFIG_EXAMPLES_SMART_TEST is not set
 # CONFIG_EXAMPLES_SMART is not set
+# CONFIG_EXAMPLES_SMART_TEST is not set
 # CONFIG_EXAMPLES_SMP is not set
 # CONFIG_EXAMPLES_TCPECHO is not set
 # CONFIG_EXAMPLES_TELNETD is not set
 # CONFIG_EXAMPLES_TIFF is not set
 # CONFIG_EXAMPLES_TOUCHSCREEN is not set
-# CONFIG_EXAMPLES_WEBSERVER is not set
-# CONFIG_EXAMPLES_USBSERIAL is not set
 # CONFIG_EXAMPLES_USBTERM is not set
 # CONFIG_EXAMPLES_WATCHDOG is not set
+# CONFIG_EXAMPLES_WEBSERVER is not set
 
 #
 # File System Utilities
@@ -766,8 +884,8 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y
 # Interpreters
 #
 # CONFIG_INTERPRETERS_FICL is not set
-# CONFIG_INTERPRETERS_PCODE is not set
 # CONFIG_INTERPRETERS_MICROPYTHON is not set
+# CONFIG_INTERPRETERS_PCODE is not set
 
 #
 # FreeModBus
@@ -778,6 +896,7 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y
 # Network Utilities
 #
 # CONFIG_NETUTILS_CODECS is not set
+# CONFIG_NETUTILS_ESP8266 is not set
 # CONFIG_NETUTILS_FTPC is not set
 # CONFIG_NETUTILS_JSON is not set
 # CONFIG_NETUTILS_SMTP is not set
@@ -890,12 +1009,12 @@ CONFIG_NSH_CONSOLE=y
 #
 # System Libraries and NSH Add-Ons
 #
-# CONFIG_SYSTEM_FREE is not set
 # CONFIG_SYSTEM_CLE is not set
 # CONFIG_SYSTEM_CUTERM is not set
-# CONFIG_SYSTEM_INSTALL is not set
+# CONFIG_SYSTEM_FREE is not set
 # CONFIG_SYSTEM_HEX2BIN is not set
 # CONFIG_SYSTEM_HEXED is not set
+# CONFIG_SYSTEM_INSTALL is not set
 # CONFIG_SYSTEM_RAMTEST is not set
 CONFIG_READLINE_HAVE_EXTMATCH=y
 CONFIG_SYSTEM_READLINE=y
@@ -903,6 +1022,6 @@ CONFIG_READLINE_ECHO=y
 # CONFIG_READLINE_TABCOMPLETION is not set
 # CONFIG_READLINE_CMD_HISTORY is not set
 # CONFIG_SYSTEM_SUDOKU is not set
-# CONFIG_SYSTEM_VI is not set
 # CONFIG_SYSTEM_UBLOXMODEM is not set
+# CONFIG_SYSTEM_VI is not set
 # CONFIG_SYSTEM_ZMODEM is not set
diff --git a/configs/stm32l476vg-disco/nsh/defconfig b/configs/stm32l476vg-disco/nsh/defconfig
index 3d27e736d2b..b8202466cd2 100644
--- a/configs/stm32l476vg-disco/nsh/defconfig
+++ b/configs/stm32l476vg-disco/nsh/defconfig
@@ -668,7 +668,7 @@ CONFIG_USART2_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -724,7 +724,6 @@ CONFIG_FS_PROCFS_REGISTER=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/stm32l476vg-disco/src/stm32_appinit.c b/configs/stm32l476vg-disco/src/stm32_appinit.c
index 3d3cf8a76b7..d530dae0b5c 100644
--- a/configs/stm32l476vg-disco/src/stm32_appinit.c
+++ b/configs/stm32l476vg-disco/src/stm32_appinit.c
@@ -86,18 +86,6 @@
 #  include "stm32l4_qspi.h"
 #endif
 
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/* Debug ********************************************************************/
-
-#ifdef CONFIG_BOARD_INITIALIZE
-#  define SYSLOG  _llerr
-#else
-#  define SYSLOG  _err
-#endif
-
 /****************************************************************************
  * Private Data
  ****************************************************************************/
@@ -204,7 +192,7 @@ FAR struct mtd_dev_s *mtd_temp;
   g_qspi = stm32l4_qspi_initialize(0);
   if (!g_qspi)
     {
-      SYSLOG("ERROR: stm32l4_qspi_initialize failed\n");
+      _err("ERROR: stm32l4_qspi_initialize failed\n");
       return ret;
     }
   else
@@ -216,7 +204,7 @@ FAR struct mtd_dev_s *mtd_temp;
       mtd_temp = n25qxxx_initialize(g_qspi, true);
       if (!mtd_temp)
         {
-          SYSLOG("ERROR: n25qxxx_initialize failed\n");
+          _err("ERROR: n25qxxx_initialize failed\n");
           return ret;
         }
       g_mtd_fs = mtd_temp;
@@ -231,7 +219,7 @@ FAR struct mtd_dev_s *mtd_temp;
 #endif
       if (!g_mtd_fs)
         {
-          SYSLOG("ERROR: mtd_partition failed\n");
+          _err("ERROR: mtd_partition failed\n");
           return ret;
         }
 
@@ -243,7 +231,7 @@ FAR struct mtd_dev_s *mtd_temp;
       ret = ftl_initialize(N25QXXX_MTD_MINOR, g_mtd_fs);
       if (ret < 0)
         {
-          SYSLOG("ERROR: Failed to initialize the FTL layer: %d\n", ret);
+          _err("ERROR: Failed to initialize the FTL layer: %d\n", ret);
           return ret;
         }
 
@@ -265,7 +253,7 @@ FAR struct mtd_dev_s *mtd_temp;
       ret = bchdev_register(blockdev, chardev, false);
       if (ret < 0)
         {
-          SYSLOG("ERROR: bchdev_register %s failed: %d\n", chardev, ret);
+          _err("ERROR: bchdev_register %s failed: %d\n", chardev, ret);
           return ret;
         }
     }
diff --git a/configs/stm32l476vg-disco/src/stm32_buttons.c b/configs/stm32l476vg-disco/src/stm32_buttons.c
index 6a49927e802..b113718c9a1 100644
--- a/configs/stm32l476vg-disco/src/stm32_buttons.c
+++ b/configs/stm32l476vg-disco/src/stm32_buttons.c
@@ -253,9 +253,9 @@ void board_button_initialize(void)
       xcpt_t oldhandler = board_button_irq(i, button_handler);
       if (oldhandler != NULL)
         {
-          lowsyslog(LOG_WARNING, "WARNING: oldhandler:%p is not NULL!  "
-                   "Button events may be lost or aliased!\n",
-                   oldhandler);
+          warn("WARNING: oldhandler:%p is not NULL!  "
+               "Button events may be lost or aliased!\n",
+               oldhandler);
         }
 #endif
 #endif
diff --git a/configs/stm32ldiscovery/nsh/defconfig b/configs/stm32ldiscovery/nsh/defconfig
index ae2c63ff12f..b7593a5be00 100644
--- a/configs/stm32ldiscovery/nsh/defconfig
+++ b/configs/stm32ldiscovery/nsh/defconfig
@@ -735,7 +735,7 @@ CONFIG_USART1_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -768,7 +768,6 @@ CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/stm32vldiscovery/nsh/defconfig b/configs/stm32vldiscovery/nsh/defconfig
index 36cbe839703..818ad684ae2 100644
--- a/configs/stm32vldiscovery/nsh/defconfig
+++ b/configs/stm32vldiscovery/nsh/defconfig
@@ -754,7 +754,7 @@ CONFIG_USART1_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -802,7 +802,6 @@ CONFIG_FAT_MAXFNAME=32
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/sure-pic32mx/README.txt b/configs/sure-pic32mx/README.txt
index 0f59eccba3c..da415a98055 100644
--- a/configs/sure-pic32mx/README.txt
+++ b/configs/sure-pic32mx/README.txt
@@ -847,7 +847,6 @@ Where <subdir> is one of the following:
        settings do nothing until you enable debug ouput.
 
         Device Drivers -> System Logging Device Options:
-          CONFIG_SYSLOG=y             : Configure SYSLOG output
           CONFIG_SYSLOG_CHAR=y
           CONFIG_SYSLOG_DEVPATH="/dev/ttyS0"
 
@@ -913,16 +912,12 @@ Where <subdir> is one of the following:
         output will come the USB console, and 2) all debug output prior
         to connecting the USB console will be lost:
 
-        Device Drivers -> System Logging Device Options:
-           CONFIG_SYSLOG=n            : Disable SYSLOG output
-
         The second options is to configure a RAM SYLOG device.  This is
         a circular buffer that accumulated debug output in memory.  The
         contents of the circular buffer can be dumped from the NSH command
         line using the 'dmesg' command.
 
         Device Drivers -> System Logging Device Options:
-          CONFIG_SYSLOG=y             : Enables the System Logging feature.
           CONFIG_RAMLOG=y             : Enable the RAM-based logging feature.
           CONFIG_RAMLOG_CONSOLE=n     : (there is no default console device)
           CONFIG_RAMLOG_SYSLOG=y      : This enables the RAM-based logger as the
diff --git a/configs/sure-pic32mx/nsh/defconfig b/configs/sure-pic32mx/nsh/defconfig
index 586054fd480..ac04ca6b59a 100644
--- a/configs/sure-pic32mx/nsh/defconfig
+++ b/configs/sure-pic32mx/nsh/defconfig
@@ -541,7 +541,7 @@ CONFIG_UART2_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -581,7 +581,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/sure-pic32mx/usbnsh/defconfig b/configs/sure-pic32mx/usbnsh/defconfig
index cf8c9003bd1..4f11af19f0b 100644
--- a/configs/sure-pic32mx/usbnsh/defconfig
+++ b/configs/sure-pic32mx/usbnsh/defconfig
@@ -622,7 +622,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-CONFIG_SYSLOG=y
 # CONFIG_SYSLOG_TIMESTAMP is not set
 CONFIG_SYSLOG_CHAR=y
 CONFIG_SYSLOG_DEVPATH="/dev/ttyS0"
diff --git a/configs/teensy-2.0/hello/defconfig b/configs/teensy-2.0/hello/defconfig
index 7b0cb5f914f..01eeae917e3 100644
--- a/configs/teensy-2.0/hello/defconfig
+++ b/configs/teensy-2.0/hello/defconfig
@@ -364,7 +364,7 @@ CONFIG_USART1_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -397,7 +397,6 @@ CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/teensy-2.0/nsh/defconfig b/configs/teensy-2.0/nsh/defconfig
index be4d9acb2df..b1bbef77028 100644
--- a/configs/teensy-2.0/nsh/defconfig
+++ b/configs/teensy-2.0/nsh/defconfig
@@ -376,7 +376,7 @@ CONFIG_USART1_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -409,7 +409,6 @@ CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/teensy-2.0/usbmsc/defconfig b/configs/teensy-2.0/usbmsc/defconfig
index 99f4422eca2..5facac91d5c 100644
--- a/configs/teensy-2.0/usbmsc/defconfig
+++ b/configs/teensy-2.0/usbmsc/defconfig
@@ -432,7 +432,7 @@ CONFIG_USBMSC_SCSI_STACKSIZE=512
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -471,7 +471,6 @@ CONFIG_FS_WRITABLE=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/teensy-3.x/nsh/defconfig b/configs/teensy-3.x/nsh/defconfig
index b1c743c446e..d1d1c6acf09 100644
--- a/configs/teensy-3.x/nsh/defconfig
+++ b/configs/teensy-3.x/nsh/defconfig
@@ -496,7 +496,7 @@ CONFIG_UART0_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -536,7 +536,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/teensy-3.x/src/k20_usbdev.c b/configs/teensy-3.x/src/k20_usbdev.c
index ae8e2976d6b..5b593378896 100644
--- a/configs/teensy-3.x/src/k20_usbdev.c
+++ b/configs/teensy-3.x/src/k20_usbdev.c
@@ -136,6 +136,6 @@ int kinetis_usbpullup(FAR struct usbdev_s *dev, bool enable)
 
 void kinetis_usbsuspend(FAR struct usbdev_s *dev, bool resume)
 {
-  ullinfo("resume: %d\n", resume);
+  uinfo("resume: %d\n", resume);
 #warning "Missing logic"
 }
diff --git a/configs/teensy-3.x/usbnsh/defconfig b/configs/teensy-3.x/usbnsh/defconfig
index 28941b695d8..c1038bed80f 100644
--- a/configs/teensy-3.x/usbnsh/defconfig
+++ b/configs/teensy-3.x/usbnsh/defconfig
@@ -582,7 +582,7 @@ CONFIG_CDCACM_PRODUCTSTR="CDC/ACM Serial"
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -623,7 +623,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/teensy-lc/nsh/defconfig b/configs/teensy-lc/nsh/defconfig
index 6473aa8b658..a397ec07680 100644
--- a/configs/teensy-lc/nsh/defconfig
+++ b/configs/teensy-lc/nsh/defconfig
@@ -480,7 +480,7 @@ CONFIG_UART0_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -513,7 +513,6 @@ CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/tm4c123g-launchpad/nsh/defconfig b/configs/tm4c123g-launchpad/nsh/defconfig
index 2b6387edeea..2e6208a3e35 100644
--- a/configs/tm4c123g-launchpad/nsh/defconfig
+++ b/configs/tm4c123g-launchpad/nsh/defconfig
@@ -511,7 +511,7 @@ CONFIG_UART0_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -550,7 +550,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/tm4c1294-launchpad/ipv6/defconfig b/configs/tm4c1294-launchpad/ipv6/defconfig
index 0e28f5a84d5..a51d473b00b 100644
--- a/configs/tm4c1294-launchpad/ipv6/defconfig
+++ b/configs/tm4c1294-launchpad/ipv6/defconfig
@@ -608,7 +608,7 @@ CONFIG_UART0_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -757,7 +757,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/tm4c1294-launchpad/nsh/defconfig b/configs/tm4c1294-launchpad/nsh/defconfig
index 683294364a3..ef2b756981a 100644
--- a/configs/tm4c1294-launchpad/nsh/defconfig
+++ b/configs/tm4c1294-launchpad/nsh/defconfig
@@ -610,7 +610,7 @@ CONFIG_UART0_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -763,7 +763,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/tm4c1294-launchpad/src/tm4c_ethernet.c b/configs/tm4c1294-launchpad/src/tm4c_ethernet.c
index 2460d0f04e0..c62d0fc0123 100644
--- a/configs/tm4c1294-launchpad/src/tm4c_ethernet.c
+++ b/configs/tm4c1294-launchpad/src/tm4c_ethernet.c
@@ -84,7 +84,7 @@ void tiva_ethernetmac(struct ether_addr *ethaddr)
   user0 = getreg32(TIVA_FLASH_USERREG0);
   user1 = getreg32(TIVA_FLASH_USERREG1);
 
-  nllinfo("user: %06x:%06x\n", user1 & 0x00ffffff, user0 & 0x00ffffff);
+  ninfo("user: %06x:%06x\n", user1 & 0x00ffffff, user0 & 0x00ffffff);
   DEBUGASSERT(user0 != 0xffffffff && user1 != 0xffffffff);
 
   /* Re-format that MAC address the way that the network expects to see it */
diff --git a/configs/twr-k60n512/nsh/defconfig b/configs/twr-k60n512/nsh/defconfig
index 87448694e11..120f1f778b2 100644
--- a/configs/twr-k60n512/nsh/defconfig
+++ b/configs/twr-k60n512/nsh/defconfig
@@ -480,7 +480,7 @@ CONFIG_UART3_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -523,7 +523,6 @@ CONFIG_FS_FAT=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/twr-k60n512/src/k60_usbdev.c b/configs/twr-k60n512/src/k60_usbdev.c
index 7944ccdbc62..23c43088665 100644
--- a/configs/twr-k60n512/src/k60_usbdev.c
+++ b/configs/twr-k60n512/src/k60_usbdev.c
@@ -108,6 +108,6 @@ int kinetis_usbpullup(FAR struct usbdev_s *dev, bool enable)
 
 void kinetis_usbsuspend(FAR struct usbdev_s *dev, bool resume)
 {
-  ullinfo("resume: %d\n", resume);
+  uinfo("resume: %d\n", resume);
 #warning "Missing logic"
 }
diff --git a/configs/u-blox-c027/nsh/defconfig b/configs/u-blox-c027/nsh/defconfig
index 2e9d8ebe10c..07bca63b713 100644
--- a/configs/u-blox-c027/nsh/defconfig
+++ b/configs/u-blox-c027/nsh/defconfig
@@ -676,7 +676,7 @@ CONFIG_UART3_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -851,7 +851,6 @@ CONFIG_FS_PROCFS=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/u-blox-c027/src/lpc17_ubxmdm.c b/configs/u-blox-c027/src/lpc17_ubxmdm.c
index f926026eba3..183e076ec40 100644
--- a/configs/u-blox-c027/src/lpc17_ubxmdm.c
+++ b/configs/u-blox-c027/src/lpc17_ubxmdm.c
@@ -64,13 +64,9 @@
 #ifdef CONFIG_MODEM_U_BLOX_DEBUG
 #  define m_err     _err
 #  define m_info    _info
-#  define m_vllerr  _llerr
-#  define m_vllinfo _llinfo
 #else
 #  define m_err(x...)
 #  define m_info(x...)
-#  define m_llerr(x...)
-#  define m_llinfo(x...)
 #endif
 
 #define UBXMDM_REGISTER_COUNT                           \
diff --git a/configs/ubw32/nsh/defconfig b/configs/ubw32/nsh/defconfig
index 0061bd3fca8..6592e260a27 100644
--- a/configs/ubw32/nsh/defconfig
+++ b/configs/ubw32/nsh/defconfig
@@ -548,7 +548,7 @@ CONFIG_UART1_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -593,7 +593,6 @@ CONFIG_FAT_MAXFNAME=32
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/us7032evb1/nsh/defconfig b/configs/us7032evb1/nsh/defconfig
index df2d6ced1d3..e87a5da115d 100644
--- a/configs/us7032evb1/nsh/defconfig
+++ b/configs/us7032evb1/nsh/defconfig
@@ -322,7 +322,6 @@ CONFIG_DISABLE_MOUNTPOINT=y
 # System Logging
 #
 
-# CONFIG_SYSLOG is not set
 
 #
 # Graphics Support
diff --git a/configs/us7032evb1/ostest/defconfig b/configs/us7032evb1/ostest/defconfig
index c5e816c47af..0c8a86314e2 100644
--- a/configs/us7032evb1/ostest/defconfig
+++ b/configs/us7032evb1/ostest/defconfig
@@ -320,7 +320,6 @@ CONFIG_DISABLE_MOUNTPOINT=y
 # System Logging
 #
 
-# CONFIG_SYSLOG is not set
 
 #
 # Graphics Support
diff --git a/configs/viewtool-stm32f107/highpri/defconfig b/configs/viewtool-stm32f107/highpri/defconfig
index 0fd667d8dbf..c7b9fdb0402 100644
--- a/configs/viewtool-stm32f107/highpri/defconfig
+++ b/configs/viewtool-stm32f107/highpri/defconfig
@@ -754,7 +754,7 @@ CONFIG_USART1_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -794,7 +794,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/viewtool-stm32f107/netnsh/defconfig b/configs/viewtool-stm32f107/netnsh/defconfig
index 678c3c0d85f..a7ef0e16bab 100644
--- a/configs/viewtool-stm32f107/netnsh/defconfig
+++ b/configs/viewtool-stm32f107/netnsh/defconfig
@@ -831,7 +831,7 @@ CONFIG_USART1_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -984,7 +984,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/viewtool-stm32f107/nsh/defconfig b/configs/viewtool-stm32f107/nsh/defconfig
index a3c40e589ad..57540eba2d1 100644
--- a/configs/viewtool-stm32f107/nsh/defconfig
+++ b/configs/viewtool-stm32f107/nsh/defconfig
@@ -752,7 +752,7 @@ CONFIG_USART1_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -793,7 +793,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/viewtool-stm32f107/src/stm32_usbdev.c b/configs/viewtool-stm32f107/src/stm32_usbdev.c
index 05d91fb36c5..cd7b9acaab0 100644
--- a/configs/viewtool-stm32f107/src/stm32_usbdev.c
+++ b/configs/viewtool-stm32f107/src/stm32_usbdev.c
@@ -118,7 +118,7 @@ int stm32_usbpullup(FAR struct usbdev_s *dev, bool enable)
 
 void stm32_usbsuspend(FAR struct usbdev_s *dev, bool resume)
 {
-  ullinfo("resume: %d\n", resume);
+  uinfo("resume: %d\n", resume);
 }
 
 #endif /* CONFIG_STM32_OTGFS || CONFIG_STM32_USB*/
diff --git a/configs/xtrs/nsh/defconfig b/configs/xtrs/nsh/defconfig
index b9eb07b695e..13aa287939f 100644
--- a/configs/xtrs/nsh/defconfig
+++ b/configs/xtrs/nsh/defconfig
@@ -242,7 +242,6 @@ CONFIG_UART_2STOP=0
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 
 #
 # Graphics Support
diff --git a/configs/xtrs/ostest/defconfig b/configs/xtrs/ostest/defconfig
index e7a9ae6755a..c20eb517ce6 100644
--- a/configs/xtrs/ostest/defconfig
+++ b/configs/xtrs/ostest/defconfig
@@ -241,7 +241,6 @@ CONFIG_UART_2STOP=0
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 
 #
 # Graphics Support
diff --git a/configs/xtrs/pashello/defconfig b/configs/xtrs/pashello/defconfig
index 77e8550bc19..b3fd7fdd938 100644
--- a/configs/xtrs/pashello/defconfig
+++ b/configs/xtrs/pashello/defconfig
@@ -241,7 +241,6 @@ CONFIG_UART_2STOP=0
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 
 #
 # Graphics Support
diff --git a/configs/z16f2800100zcog/nsh/defconfig b/configs/z16f2800100zcog/nsh/defconfig
index a9b333f3f91..3066f732cb8 100644
--- a/configs/z16f2800100zcog/nsh/defconfig
+++ b/configs/z16f2800100zcog/nsh/defconfig
@@ -399,7 +399,6 @@ CONFIG_UART1_2STOP=0
 # System Logging
 #
 
-# CONFIG_SYSLOG is not set
 
 #
 # Graphics Support
diff --git a/configs/z16f2800100zcog/ostest/defconfig b/configs/z16f2800100zcog/ostest/defconfig
index c02658bcd5d..9f93e39aef6 100644
--- a/configs/z16f2800100zcog/ostest/defconfig
+++ b/configs/z16f2800100zcog/ostest/defconfig
@@ -335,7 +335,6 @@ CONFIG_UART1_2STOP=0
 # System Logging
 #
 
-# CONFIG_SYSLOG is not set
 
 #
 # Graphics Support
diff --git a/configs/z16f2800100zcog/pashello/defconfig b/configs/z16f2800100zcog/pashello/defconfig
index 18023c6270e..f5429183781 100644
--- a/configs/z16f2800100zcog/pashello/defconfig
+++ b/configs/z16f2800100zcog/pashello/defconfig
@@ -280,7 +280,6 @@ CONFIG_UART1_2STOP=0
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 
 #
 # Graphics Support
diff --git a/configs/z80sim/nsh/defconfig b/configs/z80sim/nsh/defconfig
index ece521d8f1e..97413cca42c 100644
--- a/configs/z80sim/nsh/defconfig
+++ b/configs/z80sim/nsh/defconfig
@@ -242,7 +242,6 @@ CONFIG_UART_2STOP=0
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 
 #
 # Graphics Support
diff --git a/configs/z80sim/ostest/defconfig b/configs/z80sim/ostest/defconfig
index 5a7eb1de7f3..1e9c2f2185f 100644
--- a/configs/z80sim/ostest/defconfig
+++ b/configs/z80sim/ostest/defconfig
@@ -241,7 +241,6 @@ CONFIG_UART_2STOP=0
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 
 #
 # Graphics Support
diff --git a/configs/z80sim/pashello/defconfig b/configs/z80sim/pashello/defconfig
index f2ee7176d45..5215e22846a 100644
--- a/configs/z80sim/pashello/defconfig
+++ b/configs/z80sim/pashello/defconfig
@@ -240,7 +240,6 @@ CONFIG_UART_2STOP=0
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 
 #
 # Graphics Support
diff --git a/configs/z8encore000zco/ostest/defconfig b/configs/z8encore000zco/ostest/defconfig
index 2a4dfbbd380..499f1d6ea85 100644
--- a/configs/z8encore000zco/ostest/defconfig
+++ b/configs/z8encore000zco/ostest/defconfig
@@ -433,7 +433,7 @@ CONFIG_UART1_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -466,7 +466,6 @@ CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/z8f64200100kit/ostest/defconfig b/configs/z8f64200100kit/ostest/defconfig
index b6a7427380b..0d9e7ba4e7e 100644
--- a/configs/z8f64200100kit/ostest/defconfig
+++ b/configs/z8f64200100kit/ostest/defconfig
@@ -434,7 +434,7 @@ CONFIG_UART1_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -467,7 +467,6 @@ CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/zkit-arm-1769/hello/defconfig b/configs/zkit-arm-1769/hello/defconfig
index ee52a97f0cb..3b3c51a7e57 100644
--- a/configs/zkit-arm-1769/hello/defconfig
+++ b/configs/zkit-arm-1769/hello/defconfig
@@ -515,7 +515,7 @@ CONFIG_UART0_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -654,7 +654,6 @@ CONFIG_FS_ROMFS=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/zkit-arm-1769/nsh/defconfig b/configs/zkit-arm-1769/nsh/defconfig
index 2ea0ad42a24..723ad671842 100644
--- a/configs/zkit-arm-1769/nsh/defconfig
+++ b/configs/zkit-arm-1769/nsh/defconfig
@@ -602,7 +602,7 @@ CONFIG_UART0_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -759,7 +759,6 @@ CONFIG_FAT_MAXFNAME=32
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/zkit-arm-1769/nxhello/defconfig b/configs/zkit-arm-1769/nxhello/defconfig
index 0b785d75fe0..c2248afe137 100644
--- a/configs/zkit-arm-1769/nxhello/defconfig
+++ b/configs/zkit-arm-1769/nxhello/defconfig
@@ -639,7 +639,7 @@ CONFIG_UART0_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -789,7 +789,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/zkit-arm-1769/src/lpc17_appinit.c b/configs/zkit-arm-1769/src/lpc17_appinit.c
index 9cc219af0a5..3854e0d1c46 100644
--- a/configs/zkit-arm-1769/src/lpc17_appinit.c
+++ b/configs/zkit-arm-1769/src/lpc17_appinit.c
@@ -117,13 +117,13 @@
 
 #ifdef CONFIG_CPP_HAVE_VARARGS
 #  ifdef CONFIG_DEBUG_INFO
-#    define message(...) _llinfo(__VA_ARGS__)
+#    define message(...) _info(__VA_ARGS__)
 #  else
 #    define message(...) printf(__VA_ARGS__)
 #  endif
 #else
-#  ifdef CONFIG_DEBUG_FEATURES
-#    define message _llinfo
+#  ifdef CONFIG_DEBUG_INFO
+#    define message _info
 #  else
 #    define message printf
 #  endif
diff --git a/configs/zkit-arm-1769/src/lpc17_lcd.c b/configs/zkit-arm-1769/src/lpc17_lcd.c
index 95602fa36e0..f0297731698 100644
--- a/configs/zkit-arm-1769/src/lpc17_lcd.c
+++ b/configs/zkit-arm-1769/src/lpc17_lcd.c
@@ -90,7 +90,7 @@ int board_lcd_initialize(void)
   g_spidev = lpc17_sspbus_initialize(0);
   if (!g_spidev)
     {
-      lcdllerr("ERROR: Failed to initialize SSP port 0\n");
+      lcderr("ERROR: Failed to initialize SSP port 0\n");
       return 0;
     }
 
@@ -109,11 +109,11 @@ FAR struct lcd_dev_s *board_lcd_getdev(int lcddev)
   g_lcddev = st7567_initialize(g_spidev, lcddev);
   if (!g_lcddev)
     {
-      lcdllerr("ERROR: Failed to bind SSI port 0 to OLCD %d: %d\n", lcddev);
+      lcderr("ERROR: Failed to bind SSI port 0 to OLCD %d: %d\n", lcddev);
     }
   else
     {
-      lcdllinfo("Bound SSI port 0 to OLCD %d\n", lcddev);
+      lcdinfo("Bound SSI port 0 to OLCD %d\n", lcddev);
 
       /* And turn the OLCD on (CONFIG_LCD_MAXPOWER should be 1) */
 
diff --git a/configs/zkit-arm-1769/thttpd/defconfig b/configs/zkit-arm-1769/thttpd/defconfig
index ec26a6cdf4f..6029f85b550 100644
--- a/configs/zkit-arm-1769/thttpd/defconfig
+++ b/configs/zkit-arm-1769/thttpd/defconfig
@@ -514,7 +514,7 @@ CONFIG_UART0_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -652,7 +652,6 @@ CONFIG_FS_ROMFS=y
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/zp214xpa/nsh/defconfig b/configs/zp214xpa/nsh/defconfig
index 01389b37f18..8535cf24f26 100644
--- a/configs/zp214xpa/nsh/defconfig
+++ b/configs/zp214xpa/nsh/defconfig
@@ -435,7 +435,7 @@ CONFIG_UART1_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -474,7 +474,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/configs/zp214xpa/nxlines/defconfig b/configs/zp214xpa/nxlines/defconfig
index 5a285c01f40..ca43f21181e 100644
--- a/configs/zp214xpa/nxlines/defconfig
+++ b/configs/zp214xpa/nxlines/defconfig
@@ -473,7 +473,7 @@ CONFIG_UART1_2STOP=0
 # System Logging
 #
 # CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
 
 #
 # Networking Support
@@ -511,7 +511,6 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
 # CONFIG_SYSLOG_TIMESTAMP is not set
 
 #
diff --git a/crypto/crypto.c b/crypto/crypto.c
index fef0a918971..57839fa0fef 100644
--- a/crypto/crypto.c
+++ b/crypto/crypto.c
@@ -81,11 +81,11 @@ int up_cryptoinitialize(void)
   res = crypto_test();
   if (res)
     {
-      cryptllerr("ERROR: crypto test failed\n");
+      crypterr("ERROR: crypto test failed\n");
     }
   else
     {
-      cryptllinfo("crypto test OK\n");
+      cryptinfo("crypto test OK\n");
     }
 #endif
 
diff --git a/crypto/testmngr.c b/crypto/testmngr.c
index 12db7541a3b..1554e1e3017 100644
--- a/crypto/testmngr.c
+++ b/crypto/testmngr.c
@@ -86,7 +86,7 @@ static int do_test_aes(FAR struct cipher_testvec *test, int mode, int encrypt)
 #define AES_CYPHER_TEST_ENCRYPT(mode, mode_str, count, template) \
   for (i = 0; i < count; i++) { \
     if (do_test_aes(template + i, mode, CYPHER_ENCRYPT)) { \
-      cryptllerr("ERROR: Failed " mode_str " encrypt test #%i\n", i); \
+      crypterr("ERROR: Failed " mode_str " encrypt test #%i\n", i); \
       return -1; \
     } \
   }
@@ -94,7 +94,7 @@ static int do_test_aes(FAR struct cipher_testvec *test, int mode, int encrypt)
 #define AES_CYPHER_TEST_DECRYPT(mode, mode_str, count, template) \
   for (i = 0; i < count; i++) { \
     if (do_test_aes(template + i, mode, CYPHER_DECRYPT)) { \
-      cryptllerr("ERROR: Failed " mode_str " decrypt test #%i\n", i); \
+      crypterr("ERROR: Failed " mode_str " decrypt test #%i\n", i); \
       return -1; \
     } \
   }
diff --git a/drivers/Kconfig b/drivers/Kconfig
index df45c0d1722..fbb5f5942fe 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -208,6 +208,14 @@ config CAN_LOOPBACK
 		driver does support loopback mode, the setting will enable it. (If the
 		driver does not, this setting will have no effect).
 
+config CAN_NPOLLWAITERS
+	int "Number of poll waiters"
+	default 2
+	depends on !DISABLE_POLL
+	---help---
+		The maximum number of threads that may be waiting on the
+		poll method.
+
 endif # CAN
 
 config ARCH_HAVE_PWM_PULSECOUNT
@@ -524,7 +532,4 @@ menuconfig DRIVERS_WIRELESS
 		Drivers for various wireless devices.
 
 source drivers/wireless/Kconfig
-
-comment "System Logging Device Options"
-
 source drivers/syslog/Kconfig
diff --git a/drivers/audio/wm8904.c b/drivers/audio/wm8904.c
index 07f87741cef..2bd2502b8df 100644
--- a/drivers/audio/wm8904.c
+++ b/drivers/audio/wm8904.c
@@ -1345,7 +1345,7 @@ static void  wm8904_senddone(FAR struct i2s_dev_s *i2s,
                 CONFIG_WM8904_MSG_PRIO);
   if (ret < 0)
     {
-      audllerr("ERROR: mq_send failed: %d\n", errno);
+      auderr("ERROR: mq_send failed: %d\n", errno);
     }
 }
 
@@ -1971,7 +1971,7 @@ static int wm8904_interrupt(FAR const struct wm8904_lower_s *lower,
   ret = work_queue(LPWORK, &priv->work, wm8904_interrupt_work, priv, 0);
   if (ret < 0)
     {
-      audllerr("ERROR: Failed to schedule work\n");
+      auderr("ERROR: Failed to schedule work\n");
     }
 
   return OK;
diff --git a/drivers/can.c b/drivers/can.c
index bb1eae795cd..8dc67601a7e 100644
--- a/drivers/can.c
+++ b/drivers/can.c
@@ -4,6 +4,9 @@
  *   Copyright (C) 2008-2009, 2011-2012, 2014-2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
+ *   Copyright (C) 2016 Omni Hoverboards Inc. All rights reserved.
+ *   Author: Paul Alexander Patience <paul-a.patience@polymtl.ca>
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
@@ -47,6 +50,7 @@
 #include <semaphore.h>
 #include <fcntl.h>
 #include <assert.h>
+#include <poll.h>
 #include <errno.h>
 #include <debug.h>
 
@@ -105,6 +109,17 @@
  * Private Function Prototypes
  ****************************************************************************/
 
+/* Semaphore helpers */
+
+static int            can_takesem(FAR sem_t *sem);
+
+/* Poll helpers */
+
+#ifndef CONFIG_DISABLE_POLL
+static void           can_pollnotify(FAR struct can_dev_s *dev,
+                                     pollevent_t eventset);
+#endif
+
 /* CAN helpers */
 
 static uint8_t        can_dlc2bytes(uint8_t dlc);
@@ -120,14 +135,18 @@ static void           can_txready_work(FAR void *arg);
 static int            can_open(FAR struct file *filep);
 static int            can_close(FAR struct file *filep);
 static ssize_t        can_read(FAR struct file *filep, FAR char *buffer,
-                         size_t buflen);
+                               size_t buflen);
 static int            can_xmit(FAR struct can_dev_s *dev);
 static ssize_t        can_write(FAR struct file *filep,
-                         FAR const char *buffer, size_t buflen);
+                                FAR const char *buffer, size_t buflen);
 static inline ssize_t can_rtrread(FAR struct can_dev_s *dev,
-                         FAR struct canioc_rtr_s *rtr);
+                                  FAR struct canioc_rtr_s *rtr);
 static int            can_ioctl(FAR struct file *filep, int cmd,
-                         unsigned long arg);
+                                unsigned long arg);
+#ifndef CONFIG_DISABLE_POLL
+static int            can_poll(FAR struct file *filep, FAR struct pollfd *fds,
+                               bool setup);
+#endif
 
 /****************************************************************************
  * Private Data
@@ -139,13 +158,13 @@ static const struct file_operations g_canops =
   can_close, /* close */
   can_read,  /* read */
   can_write, /* write */
-  0,         /* seek */
+  NULL,      /* seek */
   can_ioctl  /* ioctl */
 #ifndef CONFIG_DISABLE_POLL
-  , 0        /* poll */
+  , can_poll /* poll */
 #endif
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
-  , 0        /* unlink */
+  , NULL     /* unlink */
 #endif
 };
 
@@ -153,6 +172,64 @@ static const struct file_operations g_canops =
  * Private Functions
  ****************************************************************************/
 
+/****************************************************************************
+ * Name: can_takesem
+ ****************************************************************************/
+
+static int can_takesem(FAR sem_t *sem)
+{
+  int errcode;
+
+  /* Take a count from the semaphore, possibly waiting */
+
+  if (sem_wait(sem) < 0)
+    {
+      /* The only case that an error should occur here is if the wait
+       * was awakened by a signal
+       */
+
+      errcode = get_errno();
+      DEBUGASSERT(errcode == EINTR);
+      return -errcode;
+    }
+
+  return OK;
+}
+
+/****************************************************************************
+ * Name: can_givesem
+ ****************************************************************************/
+
+#define can_givesem(sem) sem_post(sem)
+
+/****************************************************************************
+ * Name: can_pollnotify
+ ****************************************************************************/
+
+#ifndef CONFIG_DISABLE_POLL
+static void can_pollnotify(FAR struct can_dev_s *dev, pollevent_t eventset)
+{
+  FAR struct pollfd *fds;
+  int i;
+
+  for (i = 0; i < CONFIG_CAN_NPOLLWAITERS; i++)
+    {
+      fds = dev->cd_fds[i];
+      if (fds != NULL)
+        {
+          fds->revents |= fds->events & eventset;
+          if (fds->revents != 0)
+            {
+              caninfo("Report events: %02x\n", fds->revents);
+              sem_post(fds->sem);
+            }
+        }
+    }
+}
+#else
+#  define can_pollnotify(dev, eventset)
+#endif
+
 /****************************************************************************
  * Name: can_dlc2bytes
  *
@@ -281,9 +358,9 @@ static void can_txready_work(FAR void *arg)
   irqstate_t flags;
   int ret;
 
-  canllinfo("xmit head: %d queue: %d tail: %d\n",
-            dev->cd_xmit.tx_head, dev->cd_xmit.tx_queue,
-            dev->cd_xmit.tx_tail);
+  caninfo("xmit head: %d queue: %d tail: %d\n",
+          dev->cd_xmit.tx_head, dev->cd_xmit.tx_queue,
+          dev->cd_xmit.tx_tail);
 
   /* Verify that the xmit FIFO is not empty.  The following operations must
    * be performed with interrupt disabled.
@@ -309,7 +386,7 @@ static void can_txready_work(FAR void *arg)
             {
               /* Yes.. Inform them that new xmit space is available */
 
-              (void)sem_post(&dev->cd_xmit.tx_sem);
+              can_givesem(&dev->cd_xmit.tx_sem);
             }
         }
     }
@@ -331,72 +408,70 @@ static int can_open(FAR struct file *filep)
   FAR struct inode     *inode = filep->f_inode;
   FAR struct can_dev_s *dev   = inode->i_private;
   uint8_t               tmp;
-  int                   ret   = OK;
+  int                   ret;
 
   caninfo("ocount: %d\n", dev->cd_ocount);
 
   /* If the port is the middle of closing, wait until the close is finished */
 
-  if (sem_wait(&dev->cd_closesem) != OK)
+  ret = can_takesem(&dev->cd_closesem);
+  if (ret < 0)
     {
-      ret = -get_errno();
+      return ret;
+    }
+
+  /* Increment the count of references to the device.  If this is the first
+   * time that the driver has been opened for this device, then initialize
+   * the device.
+   */
+
+  tmp = dev->cd_ocount + 1;
+  if (tmp == 0)
+    {
+      /* More than 255 opens; uint8_t overflows to zero */
+
+      ret = -EMFILE;
     }
   else
     {
-      /* Increment the count of references to the device.  If this is the first
-       * time that the driver has been opened for this device, then initialize
-       * the device.
-       */
+      /* Check if this is the first time that the driver has been opened. */
 
-      tmp = dev->cd_ocount + 1;
-      if (tmp == 0)
+      if (tmp == 1)
         {
-          /* More than 255 opens; uint8_t overflows to zero */
+          /* Yes.. perform one time hardware initialization. */
 
-          ret = -EMFILE;
+          irqstate_t flags = enter_critical_section();
+          ret = dev_setup(dev);
+          if (ret >= 0)
+            {
+              /* Mark the FIFOs empty */
+
+              dev->cd_xmit.tx_head  = 0;
+              dev->cd_xmit.tx_queue = 0;
+              dev->cd_xmit.tx_tail  = 0;
+              dev->cd_recv.rx_head  = 0;
+              dev->cd_recv.rx_tail  = 0;
+
+              /* Finally, Enable the CAN RX interrupt */
+
+              dev_rxint(dev, true);
+
+              /* Save the new open count only on success */
+
+              dev->cd_ocount = 1;
+            }
+
+          leave_critical_section(flags);
         }
       else
         {
-          /* Check if this is the first time that the driver has been opened. */
+          /* Save the incremented open count */
 
-          if (tmp == 1)
-            {
-              /* Yes.. perform one time hardware initialization. */
-
-              irqstate_t flags = enter_critical_section();
-              ret = dev_setup(dev);
-              if (ret == OK)
-                {
-                  /* Mark the FIFOs empty */
-
-                  dev->cd_xmit.tx_head  = 0;
-                  dev->cd_xmit.tx_queue = 0;
-                  dev->cd_xmit.tx_tail  = 0;
-                  dev->cd_recv.rx_head  = 0;
-                  dev->cd_recv.rx_tail  = 0;
-
-                  /* Finally, Enable the CAN RX interrupt */
-
-                  dev_rxint(dev, true);
-
-                  /* Save the new open count only on success */
-
-                  dev->cd_ocount = 1;
-                }
-
-              leave_critical_section(flags);
-            }
-          else
-            {
-              /* Save the incremented open count */
-
-              dev->cd_ocount = tmp;
-            }
+          dev->cd_ocount = tmp;
         }
-
-      sem_post(&dev->cd_closesem);
     }
 
+  can_givesem(&dev->cd_closesem);
   return ret;
 }
 
@@ -414,67 +489,64 @@ static int can_close(FAR struct file *filep)
   FAR struct inode     *inode = filep->f_inode;
   FAR struct can_dev_s *dev   = inode->i_private;
   irqstate_t            flags;
-  int                   ret = OK;
+  int                   ret;
 
   caninfo("ocount: %d\n", dev->cd_ocount);
 
-  if (sem_wait(&dev->cd_closesem) != OK)
+  ret = can_takesem(&dev->cd_closesem);
+  if (ret < 0)
     {
-      ret = -get_errno();
-    }
-  else
-    {
-      /* Decrement the references to the driver.  If the reference count will
-       * decrement to 0, then uninitialize the driver.
-       */
-
-      if (dev->cd_ocount > 1)
-        {
-          dev->cd_ocount--;
-          sem_post(&dev->cd_closesem);
-        }
-      else
-        {
-          /* There are no more references to the port */
-
-          dev->cd_ocount = 0;
-
-          /* Stop accepting input */
-
-          dev_rxint(dev, false);
-
-          /* Now we wait for the transmit FIFO to clear */
-
-          while (dev->cd_xmit.tx_head != dev->cd_xmit.tx_tail)
-            {
-#ifndef CONFIG_DISABLE_SIGNALS
-               usleep(HALF_SECOND_USEC);
-#else
-               up_mdelay(HALF_SECOND_MSEC);
-#endif
-            }
-
-          /* And wait for the TX hardware FIFO to drain */
-
-          while (!dev_txempty(dev))
-            {
-#ifndef CONFIG_DISABLE_SIGNALS
-              usleep(HALF_SECOND_USEC);
-#else
-              up_mdelay(HALF_SECOND_MSEC);
-#endif
-            }
-
-          /* Free the IRQ and disable the CAN device */
-
-          flags = enter_critical_section();       /* Disable interrupts */
-          dev_shutdown(dev);       /* Disable the CAN */
-          leave_critical_section(flags);
-
-          sem_post(&dev->cd_closesem);
-        }
+      return ret;
     }
 
+  /* Decrement the references to the driver.  If the reference count will
+   * decrement to 0, then uninitialize the driver.
+   */
+
+  if (dev->cd_ocount > 1)
+    {
+      dev->cd_ocount--;
+      goto errout;
+    }
+
+  /* There are no more references to the port */
+
+  dev->cd_ocount = 0;
+
+  /* Stop accepting input */
+
+  dev_rxint(dev, false);
+
+  /* Now we wait for the transmit FIFO to clear */
+
+  while (dev->cd_xmit.tx_head != dev->cd_xmit.tx_tail)
+    {
+#ifndef CONFIG_DISABLE_SIGNALS
+       usleep(HALF_SECOND_USEC);
+#else
+       up_mdelay(HALF_SECOND_MSEC);
+#endif
+    }
+
+  /* And wait for the TX hardware FIFO to drain */
+
+  while (!dev_txempty(dev))
+    {
+#ifndef CONFIG_DISABLE_SIGNALS
+      usleep(HALF_SECOND_USEC);
+#else
+      up_mdelay(HALF_SECOND_MSEC);
+#endif
+    }
+
+  /* Free the IRQ and disable the CAN device */
+
+  flags = enter_critical_section(); /* Disable interrupts */
+  dev_shutdown(dev);                /* Disable the CAN */
+  leave_critical_section(flags);
+
+errout:
+  can_givesem(&dev->cd_closesem);
   return ret;
 }
 
@@ -557,18 +629,12 @@ static ssize_t can_read(FAR struct file *filep, FAR char *buffer,
 
           /* Wait for a message to be received */
 
+          DEBUGASSERT(dev->cd_nrxwaiters < 255);
           dev->cd_nrxwaiters++;
-          do
-            {
-              ret = sem_wait(&dev->cd_recv.rx_sem);
-            }
-          while (ret >= 0 && dev->cd_recv.rx_head == dev->cd_recv.rx_tail);
-
+          ret = can_takesem(&dev->cd_recv.rx_sem);
           dev->cd_nrxwaiters--;
-
           if (ret < 0)
             {
-              ret = -get_errno();
               goto return_with_irqdisabled;
             }
         }
@@ -634,8 +700,8 @@ static int can_xmit(FAR struct can_dev_s *dev)
   int tmpndx;
   int ret = -EBUSY;
 
-  canllinfo("xmit head: %d queue: %d tail: %d\n",
-            dev->cd_xmit.tx_head, dev->cd_xmit.tx_queue, dev->cd_xmit.tx_tail);
+  caninfo("xmit head: %d queue: %d tail: %d\n",
+          dev->cd_xmit.tx_head, dev->cd_xmit.tx_queue, dev->cd_xmit.tx_tail);
 
   /* If there is nothing to send, then just disable interrupts and return */
 
@@ -685,7 +751,7 @@ static int can_xmit(FAR struct can_dev_s *dev)
       /* Send the next message at the FIFO queue index */
 
       ret = dev_send(dev, &dev->cd_xmit.tx_buffer[tmpndx]);
-      if (ret != OK)
+      if (ret < 0)
         {
           canerr("dev_send failed: %d\n", ret);
           break;
@@ -779,20 +845,14 @@ static ssize_t can_write(FAR struct file *filep, FAR const char *buffer,
 
           /* Wait for a message to be sent */
 
-          do
+          DEBUGASSERT(dev->cd_ntxwaiters < 255);
+          dev->cd_ntxwaiters++;
+          ret = can_takesem(&fifo->tx_sem);
+          dev->cd_ntxwaiters--;
+          if (ret < 0)
             {
-              DEBUGASSERT(dev->cd_ntxwaiters < 255);
-              dev->cd_ntxwaiters++;
-              ret = sem_wait(&fifo->tx_sem);
-              dev->cd_ntxwaiters--;
-
-              if (ret < 0 && get_errno() != EINTR)
-                {
-                  ret = -get_errno();
-                  goto return_with_irqdisabled;
-                }
+              goto return_with_irqdisabled;
             }
-          while (ret < 0);
 
           /* Re-check the FIFO state */
 
@@ -818,7 +878,7 @@ static ssize_t can_write(FAR struct file *filep, FAR const char *buffer,
     }
 
   /* We get here after all messages have been added to the FIFO.  Check if
-   * we need to kick of the XMIT sequence.
+   * we need to kick off the XMIT sequence.
    */
 
   if (inactive)
@@ -878,11 +938,11 @@ static inline ssize_t can_rtrread(FAR struct can_dev_s *dev,
       /* Send the remote transmission request */
 
       ret = dev_remoterequest(dev, wait->cr_id);
-      if (ret == OK)
+      if (ret >= 0)
         {
           /* Then wait for the response */
 
-          ret = sem_wait(&wait->cr_sem);
+          ret = can_takesem(&wait->cr_sem);
         }
     }
 
@@ -929,6 +989,157 @@ static int can_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
   return ret;
 }
 
+/****************************************************************************
+ * Name: can_poll
+ ****************************************************************************/
+
+#ifndef CONFIG_DISABLE_POLL
+static int can_poll(FAR struct file *filep, FAR struct pollfd *fds,
+                    bool setup)
+{
+  FAR struct inode     *inode = (FAR struct inode *)filep->f_inode;
+  FAR struct can_dev_s *dev   = (FAR struct can_dev_s *)inode->i_private;
+  pollevent_t eventset;
+  int ndx;
+  int ret;
+  int i;
+
+  /* Some sanity checking */
+
+#ifdef CONFIG_DEBUG_FEATURES
+  if (dev == NULL || fds == NULL)
+    {
+      return -ENODEV;
+    }
+#endif
+
+  /* Get exclusive access to the poll structures */
+
+  ret = can_takesem(&dev->cd_pollsem);
+  if (ret < 0)
+    {
+      /* A signal received while waiting for access to the poll data
+       * will abort the operation
+       */
+
+      return ret;
+    }
+
+  /* Are we setting up the poll?  Or tearing it down? */
+
+  if (setup)
+    {
+      /* This is a request to set up the poll.  Find an available
+       * slot for the poll structure reference.
+       */
+
+      for (i = 0; i < CONFIG_CAN_NPOLLWAITERS; i++)
+        {
+          /* Find an available slot */
+
+          if (dev->cd_fds[i] == NULL)
+            {
+              /* Bind the poll structure and this slot */
+
+              dev->cd_fds[i] = fds;
+              fds->priv       = &dev->cd_fds[i];
+              break;
+            }
+        }
+
+      if (i >= CONFIG_CAN_NPOLLWAITERS)
+        {
+          fds->priv = NULL;
+          ret       = -EBUSY;
+          goto errout;
+        }
+
+      /* Should we immediately notify on any of the requested events?
+       * First, check if the xmit buffer is full.
+       *
+       * Get exclusive access to the cd_xmit buffer indices.  NOTE: that
+       * we do not let this wait be interrupted by a signal (we probably
+       * should, but that would be a little awkward).
+       */
+
+      eventset = 0;
+
+      DEBUGASSERT(dev->cd_ntxwaiters < 255);
+      dev->cd_ntxwaiters++;
+      do
+        {
+          ret = can_takesem(&dev->cd_xmit.tx_sem);
+        }
+      while (ret < 0);
+      dev->cd_ntxwaiters--;
+
+      ndx = dev->cd_xmit.tx_head + 1;
+      if (ndx >= CONFIG_CAN_FIFOSIZE)
+        {
+          ndx = 0;
+        }
+
+      if (ndx != dev->cd_xmit.tx_tail)
+        {
+          eventset |= fds->events & POLLOUT;
+        }
+
+      can_givesem(&dev->cd_xmit.tx_sem);
+
+      /* Check if the receive buffer is empty.
+       *
+       * Get exclusive access to the cd_recv buffer indices.  NOTE: that
+       * we do not let this wait be interrupted by a signal (we probably
+       * should, but that would be a little awkward).
+       */
+
+      DEBUGASSERT(dev->cd_nrxwaiters < 255);
+      dev->cd_nrxwaiters++;
+      do
+        {
+          ret = can_takesem(&dev->cd_recv.rx_sem);
+        }
+      while (ret < 0);
+      dev->cd_nrxwaiters--;
+
+      if (dev->cd_recv.rx_head != dev->cd_recv.rx_tail)
+        {
+          eventset |= fds->events & POLLIN;
+        }
+
+      can_givesem(&dev->cd_recv.rx_sem);
+
+      if (eventset != 0)
+        {
+          can_pollnotify(dev, eventset);
+        }
+    }
+  else if (fds->priv != NULL)
+    {
+      /* This is a request to tear down the poll */
+
+      struct pollfd **slot = (struct pollfd **)fds->priv;
+
+#ifdef CONFIG_DEBUG_FEATURES
+      if (slot == NULL)
+        {
+          ret = -EIO;
+          goto errout;
+        }
+#endif
+
+      /* Remove all memory of the poll setup */
+
+      *slot     = NULL;
+      fds->priv = NULL;
+    }
+
+errout:
+  can_givesem(&dev->cd_pollsem);
+  return ret;
+}
+#endif
+
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
@@ -955,9 +1166,12 @@ int can_register(FAR const char *path, FAR struct can_dev_s *dev)
   dev->cd_error      = 0;
 #endif
 
-  sem_init(&dev->cd_xmit.tx_sem, 0, 0);
-  sem_init(&dev->cd_recv.rx_sem, 0, 0);
-  sem_init(&dev->cd_closesem, 0, 1);
+  sem_init(&dev->cd_xmit.tx_sem, 0, 1);
+  sem_init(&dev->cd_recv.rx_sem, 0, 1);
+  sem_init(&dev->cd_closesem,    0, 1);
+#ifndef CONFIG_DISABLE_POLL
+  sem_init(&dev->cd_pollsem,     0, 1);
+#endif
 
   for (i = 0; i < CONFIG_CAN_NPENDINGRTR; i++)
     {
@@ -1003,7 +1217,7 @@ int can_receive(FAR struct can_dev_s *dev, FAR struct can_hdr_s *hdr,
   int                      errcode = -ENOMEM;
   int                      i;
 
-  canllinfo("ID: %d DLC: %d\n", hdr->ch_id, hdr->ch_dlc);
+  caninfo("ID: %d DLC: %d\n", hdr->ch_id, hdr->ch_dlc);
 
   /* Check if adding this new message would over-run the drivers ability to
    * enqueue read data.
@@ -1055,7 +1269,7 @@ int can_receive(FAR struct can_dev_s *dev, FAR struct can_hdr_s *hdr,
 
               /* And restart the waiting thread */
 
-              sem_post(&rtr->cr_sem);
+              can_givesem(&rtr->cr_sem);
             }
         }
     }
@@ -1095,10 +1309,16 @@ int can_receive(FAR struct can_dev_s *dev, FAR struct can_hdr_s *hdr,
 
       if (dev->cd_nrxwaiters > 0)
         {
-          sem_post(&fifo->rx_sem);
+          can_givesem(&fifo->rx_sem);
         }
 
       errcode = OK;
+
+      /* Notify all poll/select waiters that they can read from the
+       * cd_recv buffer
+       */
+
+      can_pollnotify(dev, POLLIN);
     }
 #ifdef CONFIG_CAN_ERRORS
   else
@@ -1188,8 +1408,8 @@ int can_txdone(FAR struct can_dev_s *dev)
 {
   int ret = -ENOENT;
 
-  canllinfo("xmit head: %d queue: %d tail: %d\n",
-            dev->cd_xmit.tx_head, dev->cd_xmit.tx_queue, dev->cd_xmit.tx_tail);
+  caninfo("xmit head: %d queue: %d tail: %d\n",
+          dev->cd_xmit.tx_head, dev->cd_xmit.tx_queue, dev->cd_xmit.tx_tail);
 
   /* Verify that the xmit FIFO is not empty */
 
@@ -1220,7 +1440,7 @@ int can_txdone(FAR struct can_dev_s *dev)
         {
           /* Yes.. Inform them that new xmit space is available */
 
-          ret = sem_post(&dev->cd_xmit.tx_sem);
+          ret = can_givesem(&dev->cd_xmit.tx_sem);
         }
       else
         {
@@ -1228,6 +1448,12 @@ int can_txdone(FAR struct can_dev_s *dev)
         }
     }
 
+  /* Notify all poll/select waiters that they can write to the cd_xmit
+   * buffer
+   */
+
+  can_pollnotify(dev, POLLOUT);
+
   return ret;
 }
 
@@ -1292,9 +1518,9 @@ int can_txready(FAR struct can_dev_s *dev)
 {
   int ret = -ENOENT;
 
-  canllinfo("xmit head: %d queue: %d tail: %d waiters: %d\n",
-            dev->cd_xmit.tx_head, dev->cd_xmit.tx_queue, dev->cd_xmit.tx_tail,
-            dev->cd_ntxwaiters);
+  caninfo("xmit head: %d queue: %d tail: %d waiters: %d\n",
+          dev->cd_xmit.tx_head, dev->cd_xmit.tx_queue, dev->cd_xmit.tx_tail,
+          dev->cd_ntxwaiters);
 
   /* Verify that the xmit FIFO is not empty.  This is safe because interrupts
    * are always disabled when calling into can_xmit(); this cannot collide
diff --git a/drivers/eeprom/spi_xx25xx.c b/drivers/eeprom/spi_xx25xx.c
index 67a38b97843..437dfbea854 100644
--- a/drivers/eeprom/spi_xx25xx.c
+++ b/drivers/eeprom/spi_xx25xx.c
@@ -387,8 +387,6 @@ static void ee25xx_waitwritecomplete(struct ee25xx_dev_s *priv)
         }
     }
   while ((status & EE25XX_SR_WIP) != 0);
-
-  finfo("Complete\n");
 }
 
 /****************************************************************************
@@ -815,9 +813,8 @@ int ee25xx_initialize(FAR struct spi_dev_s *dev, FAR char *devname,
 
   eedev->readonly = !!readonly;
 
-  lowsyslog(LOG_NOTICE,
-            "EEPROM device %s, %d bytes, %d per page, addrlen %d, readonly %d\n",
-            devname, eedev->size, eedev->pgsize, eedev->addrlen, eedev->readonly);
+  finfo("EEPROM device %s, %d bytes, %d per page, addrlen %d, readonly %d\n",
+       devname, eedev->size, eedev->pgsize, eedev->addrlen, eedev->readonly);
 
   return register_driver(devname, &ee25xx_fops, 0666, eedev);
 }
diff --git a/drivers/input/Kconfig b/drivers/input/Kconfig
index e28d053af7b..0fc96d6c918 100644
--- a/drivers/input/Kconfig
+++ b/drivers/input/Kconfig
@@ -179,7 +179,7 @@ config MXT_NPOLLWAITERS
 config MXT_DISABLE_CONFIG_DEBUG_INFO
 	bool "Disable verbose debug output"
 	default y
-	depends on CONFIG_DEBUG_INFO && DEBUG_INPUT
+	depends on DEBUG_INPUT_INFO
 	---help---
 		The maXTouch tends to generate interrupts at a high rate during the
 		contact.  If verbose debug is enabled in this driver, you may not
diff --git a/drivers/input/ads7843e.c b/drivers/input/ads7843e.c
index 0ce1f897cb5..5f4c159a9f8 100644
--- a/drivers/input/ads7843e.c
+++ b/drivers/input/ads7843e.c
@@ -498,7 +498,7 @@ static int ads7843e_schedule(FAR struct ads7843e_dev_s *priv)
   ret = work_queue(HPWORK, &priv->work, ads7843e_worker, priv, 0);
   if (ret != 0)
     {
-      illerr("ERROR: Failed to queue work: %d\n", ret);
+      ierr("ERROR: Failed to queue work: %d\n", ret);
     }
 
   return OK;
diff --git a/drivers/input/ajoystick.c b/drivers/input/ajoystick.c
index af938ae1573..aaba021b95b 100644
--- a/drivers/input/ajoystick.c
+++ b/drivers/input/ajoystick.c
@@ -414,7 +414,7 @@ static int ajoy_open(FAR struct file *filep)
   ret = ajoy_takesem(&priv->au_exclsem);
   if (ret < 0)
     {
-      iinfo("ERROR: ajoy_takesem failed: %d\n", ret);
+      ierr("ERROR: ajoy_takesem failed: %d\n", ret);
       return ret;
     }
 
@@ -423,7 +423,7 @@ static int ajoy_open(FAR struct file *filep)
   opriv = (FAR struct ajoy_open_s *)kmm_zalloc(sizeof(struct ajoy_open_s));
   if (!opriv)
     {
-      iinfo("ERROR: Failled to allocate open structure\n");
+      ierr("ERROR: Failled to allocate open structure\n");
       ret = -ENOMEM;
       goto errout_with_sem;
     }
@@ -502,7 +502,7 @@ static int ajoy_close(FAR struct file *filep)
   ret = ajoy_takesem(&priv->au_exclsem);
   if (ret < 0)
     {
-      iinfo("ERROR: ajoy_takesem failed: %d\n", ret);
+      ierr("ERROR: ajoy_takesem failed: %d\n", ret);
       return ret;
     }
 
@@ -515,7 +515,7 @@ static int ajoy_close(FAR struct file *filep)
   DEBUGASSERT(curr);
   if (!curr)
     {
-      iinfo("ERROR: Failed to find open entry\n");
+      ierr("ERROR: Failed to find open entry\n");
       ret = -ENOENT;
       goto errout_with_exclsem;
     }
@@ -570,7 +570,7 @@ static ssize_t ajoy_read(FAR struct file *filep, FAR char *buffer,
 
   if (len < sizeof(struct ajoy_sample_s))
     {
-      iinfo("ERROR: buffer too small: %lu\n", (unsigned long)len);
+      ierr("ERROR: buffer too small: %lu\n", (unsigned long)len);
       return -EINVAL;
     }
 
@@ -579,7 +579,7 @@ static ssize_t ajoy_read(FAR struct file *filep, FAR char *buffer,
   ret = ajoy_takesem(&priv->au_exclsem);
   if (ret < 0)
     {
-      iinfo("ERROR: ajoy_takesem failed: %d\n", ret);
+      ierr("ERROR: ajoy_takesem failed: %d\n", ret);
       return ret;
     }
 
@@ -620,7 +620,7 @@ static int ajoy_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
   ret = ajoy_takesem(&priv->au_exclsem);
   if (ret < 0)
     {
-      iinfo("ERROR: ajoy_takesem failed: %d\n", ret);
+      ierr("ERROR: ajoy_takesem failed: %d\n", ret);
       return ret;
     }
 
@@ -720,7 +720,7 @@ static int ajoy_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
 #endif
 
     default:
-      iinfo("ERROR: Unrecognized command: %ld\n", cmd);
+      ierr("ERROR: Unrecognized command: %ld\n", cmd);
       ret = -ENOTTY;
       break;
     }
@@ -754,7 +754,7 @@ static int ajoy_poll(FAR struct file *filep, FAR struct pollfd *fds,
   ret = ajoy_takesem(&priv->au_exclsem);
   if (ret < 0)
     {
-      iinfo("ERROR: ajoy_takesem failed: %d\n", ret);
+      ierr("ERROR: ajoy_takesem failed: %d\n", ret);
       return ret;
     }
 
@@ -782,7 +782,7 @@ static int ajoy_poll(FAR struct file *filep, FAR struct pollfd *fds,
 
       if (i >= CONFIG_AJOYSTICK_NPOLLWAITERS)
         {
-          iinfo("ERROR: Too man poll waiters\n");
+          ierr("ERROR: Too man poll waiters\n");
           fds->priv    = NULL;
           ret          = -EBUSY;
           goto errout_with_dusem;
@@ -797,7 +797,7 @@ static int ajoy_poll(FAR struct file *filep, FAR struct pollfd *fds,
 #ifdef CONFIG_DEBUG_FEATURES
       if (!slot)
         {
-          iinfo("ERROR: Poll slot not found\n");
+          ierr("ERROR: Poll slot not found\n");
           ret = -EIO;
           goto errout_with_dusem;
         }
@@ -856,7 +856,7 @@ int ajoy_register(FAR const char *devname,
 
   if (!priv)
     {
-      iinfo("ERROR: Failed to allocate device structure\n");
+      ierr("ERROR: Failed to allocate device structure\n");
       return -ENOMEM;
     }
 
@@ -878,7 +878,7 @@ int ajoy_register(FAR const char *devname,
   ret = register_driver(devname, &ajoy_fops, 0666, priv);
   if (ret < 0)
     {
-      iinfo("ERROR: register_driver failed: %d\n", ret);
+      ierr("ERROR: register_driver failed: %d\n", ret);
       goto errout_with_priv;
     }
 
diff --git a/drivers/input/button_lower.c b/drivers/input/button_lower.c
index ae338d542dc..9be0b4a35f7 100644
--- a/drivers/input/button_lower.c
+++ b/drivers/input/button_lower.c
@@ -138,8 +138,8 @@ static void btn_enable(FAR const struct btn_lowerhalf_s *lower,
   flags = enter_critical_section();
   btn_disable();
 
-  illinfo("press: %02x release: %02x handler: %p arg: %p\n",
-          press, release, handler, arg);
+  iinfo("press: %02x release: %02x handler: %p arg: %p\n",
+        press, release, handler, arg);
 
   /* If no events are indicated or if no handler is provided, then this
    * must really be a request to disable interrupts.
diff --git a/drivers/input/button_upper.c b/drivers/input/button_upper.c
index b56afeccb76..2c03d3de3e0 100644
--- a/drivers/input/button_upper.c
+++ b/drivers/input/button_upper.c
@@ -410,7 +410,7 @@ static int btn_open(FAR struct file *filep)
   ret = btn_takesem(&priv->bu_exclsem);
   if (ret < 0)
     {
-      iinfo("ERROR: btn_takesem failed: %d\n", ret);
+      ierr("ERROR: btn_takesem failed: %d\n", ret);
       return ret;
     }
 
@@ -419,7 +419,7 @@ static int btn_open(FAR struct file *filep)
   opriv = (FAR struct btn_open_s *)kmm_zalloc(sizeof(struct btn_open_s));
   if (!opriv)
     {
-      iinfo("ERROR: Failled to allocate open structure\n");
+      ierr("ERROR: Failled to allocate open structure\n");
       ret = -ENOMEM;
       goto errout_with_sem;
     }
@@ -498,7 +498,7 @@ static int btn_close(FAR struct file *filep)
   ret = btn_takesem(&priv->bu_exclsem);
   if (ret < 0)
     {
-      iinfo("ERROR: btn_takesem failed: %d\n", ret);
+      ierr("ERROR: btn_takesem failed: %d\n", ret);
       return ret;
     }
 
@@ -511,7 +511,7 @@ static int btn_close(FAR struct file *filep)
   DEBUGASSERT(curr);
   if (!curr)
     {
-      iinfo("ERROR: Failed to find open entry\n");
+      ierr("ERROR: Failed to find open entry\n");
       ret = -ENOENT;
       goto errout_with_exclsem;
     }
@@ -566,7 +566,7 @@ static ssize_t btn_read(FAR struct file *filep, FAR char *buffer,
 
   if (len < sizeof(btn_buttonset_t))
     {
-      iinfo("ERROR: buffer too small: %lu\n", (unsigned long)len);
+      ierr("ERROR: buffer too small: %lu\n", (unsigned long)len);
       return -EINVAL;
     }
 
@@ -575,7 +575,7 @@ static ssize_t btn_read(FAR struct file *filep, FAR char *buffer,
   ret = btn_takesem(&priv->bu_exclsem);
   if (ret < 0)
     {
-      iinfo("ERROR: btn_takesem failed: %d\n", ret);
+      ierr("ERROR: btn_takesem failed: %d\n", ret);
       return ret;
     }
 
@@ -612,7 +612,7 @@ static int btn_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
   ret = btn_takesem(&priv->bu_exclsem);
   if (ret < 0)
     {
-      iinfo("ERROR: btn_takesem failed: %d\n", ret);
+      ierr("ERROR: btn_takesem failed: %d\n", ret);
       return ret;
     }
 
@@ -712,7 +712,7 @@ static int btn_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
 #endif
 
     default:
-      iinfo("ERROR: Unrecognized command: %ld\n", cmd);
+      ierr("ERROR: Unrecognized command: %ld\n", cmd);
       ret = -ENOTTY;
       break;
     }
@@ -746,7 +746,7 @@ static int btn_poll(FAR struct file *filep, FAR struct pollfd *fds,
   ret = btn_takesem(&priv->bu_exclsem);
   if (ret < 0)
     {
-      iinfo("ERROR: btn_takesem failed: %d\n", ret);
+      ierr("ERROR: btn_takesem failed: %d\n", ret);
       return ret;
     }
 
@@ -774,7 +774,7 @@ static int btn_poll(FAR struct file *filep, FAR struct pollfd *fds,
 
       if (i >= CONFIG_BUTTONS_NPOLLWAITERS)
         {
-          iinfo("ERROR: Too man poll waiters\n");
+          ierr("ERROR: Too man poll waiters\n");
           fds->priv    = NULL;
           ret          = -EBUSY;
           goto errout_with_dusem;
@@ -789,7 +789,7 @@ static int btn_poll(FAR struct file *filep, FAR struct pollfd *fds,
 #ifdef CONFIG_DEBUG_FEATURES
       if (!slot)
         {
-          iinfo("ERROR: Poll slot not found\n");
+          ierr("ERROR: Poll slot not found\n");
           ret = -EIO;
           goto errout_with_dusem;
         }
@@ -847,7 +847,7 @@ int btn_register(FAR const char *devname,
 
   if (!priv)
     {
-      iinfo("ERROR: Failed to allocate device structure\n");
+      ierr("ERROR: Failed to allocate device structure\n");
       return -ENOMEM;
     }
 
@@ -869,7 +869,7 @@ int btn_register(FAR const char *devname,
   ret = register_driver(devname, &btn_fops, 0666, priv);
   if (ret < 0)
     {
-      iinfo("ERROR: register_driver failed: %d\n", ret);
+      ierr("ERROR: register_driver failed: %d\n", ret);
       goto errout_with_priv;
     }
 
diff --git a/drivers/input/djoystick.c b/drivers/input/djoystick.c
index b1b7522eb81..1cc1b540045 100644
--- a/drivers/input/djoystick.c
+++ b/drivers/input/djoystick.c
@@ -352,7 +352,7 @@ static void djoy_sample(FAR struct djoy_upperhalf_s *priv)
                   fds->revents |= (fds->events & POLLIN);
                   if (fds->revents != 0)
                     {
-                      illinfo("Report events: %02x\n", fds->revents);
+                      iinfo("Report events: %02x\n", fds->revents);
                       sem_post(fds->sem);
                     }
                 }
@@ -414,7 +414,7 @@ static int djoy_open(FAR struct file *filep)
   ret = djoy_takesem(&priv->du_exclsem);
   if (ret < 0)
     {
-      iinfo("ERROR: djoy_takesem failed: %d\n", ret);
+      ierr("ERROR: djoy_takesem failed: %d\n", ret);
       return ret;
     }
 
@@ -423,7 +423,7 @@ static int djoy_open(FAR struct file *filep)
   opriv = (FAR struct djoy_open_s *)kmm_zalloc(sizeof(struct djoy_open_s));
   if (!opriv)
     {
-      iinfo("ERROR: Failled to allocate open structure\n");
+      ierr("ERROR: Failled to allocate open structure\n");
       ret = -ENOMEM;
       goto errout_with_sem;
     }
@@ -502,7 +502,7 @@ static int djoy_close(FAR struct file *filep)
   ret = djoy_takesem(&priv->du_exclsem);
   if (ret < 0)
     {
-      iinfo("ERROR: djoy_takesem failed: %d\n", ret);
+      ierr("ERROR: djoy_takesem failed: %d\n", ret);
       return ret;
     }
 
@@ -515,7 +515,7 @@ static int djoy_close(FAR struct file *filep)
   DEBUGASSERT(curr);
   if (!curr)
     {
-      iinfo("ERROR: Failed to find open entry\n");
+      ierr("ERROR: Failed to find open entry\n");
       ret = -ENOENT;
       goto errout_with_exclsem;
     }
@@ -568,7 +568,7 @@ static ssize_t djoy_read(FAR struct file *filep, FAR char *buffer,
 
   if (len < sizeof(djoy_buttonset_t))
     {
-      iinfo("ERROR: buffer too small: %lu\n", (unsigned long)len);
+      ierr("ERROR: buffer too small: %lu\n", (unsigned long)len);
       return -EINVAL;
     }
 
@@ -577,7 +577,7 @@ static ssize_t djoy_read(FAR struct file *filep, FAR char *buffer,
   ret = djoy_takesem(&priv->du_exclsem);
   if (ret < 0)
     {
-      iinfo("ERROR: djoy_takesem failed: %d\n", ret);
+      ierr("ERROR: djoy_takesem failed: %d\n", ret);
       return ret;
     }
 
@@ -616,7 +616,7 @@ static int djoy_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
   ret = djoy_takesem(&priv->du_exclsem);
   if (ret < 0)
     {
-      iinfo("ERROR: djoy_takesem failed: %d\n", ret);
+      ierr("ERROR: djoy_takesem failed: %d\n", ret);
       return ret;
     }
 
@@ -716,7 +716,7 @@ static int djoy_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
 #endif
 
     default:
-      iinfo("ERROR: Unrecognized command: %ld\n", cmd);
+      ierr("ERROR: Unrecognized command: %ld\n", cmd);
       ret = -ENOTTY;
       break;
     }
@@ -750,7 +750,7 @@ static int djoy_poll(FAR struct file *filep, FAR struct pollfd *fds,
   ret = djoy_takesem(&priv->du_exclsem);
   if (ret < 0)
     {
-      iinfo("ERROR: djoy_takesem failed: %d\n", ret);
+      ierr("ERROR: djoy_takesem failed: %d\n", ret);
       return ret;
     }
 
@@ -778,7 +778,7 @@ static int djoy_poll(FAR struct file *filep, FAR struct pollfd *fds,
 
       if (i >= CONFIG_DJOYSTICK_NPOLLWAITERS)
         {
-          iinfo("ERROR: Too man poll waiters\n");
+          ierr("ERROR: Too man poll waiters\n");
           fds->priv    = NULL;
           ret          = -EBUSY;
           goto errout_with_dusem;
@@ -793,7 +793,7 @@ static int djoy_poll(FAR struct file *filep, FAR struct pollfd *fds,
 #ifdef CONFIG_DEBUG_FEATURES
       if (!slot)
         {
-          iinfo("ERROR: Poll slot not found\n");
+          ierr("ERROR: Poll slot not found\n");
           ret = -EIO;
           goto errout_with_dusem;
         }
@@ -852,7 +852,7 @@ int djoy_register(FAR const char *devname,
 
   if (!priv)
     {
-      iinfo("ERROR: Failed to allocate device structure\n");
+      ierr("ERROR: Failed to allocate device structure\n");
       return -ENOMEM;
     }
 
@@ -874,7 +874,7 @@ int djoy_register(FAR const char *devname,
   ret = register_driver(devname, &djoy_fops, 0666, priv);
   if (ret < 0)
     {
-      iinfo("ERROR: register_driver failed: %d\n", ret);
+      ierr("ERROR: register_driver failed: %d\n", ret);
       sem_destroy(&priv->du_exclsem);
       kmm_free(priv);
     }
diff --git a/drivers/input/max11802.c b/drivers/input/max11802.c
index ca460861421..2394cd2e5ea 100644
--- a/drivers/input/max11802.c
+++ b/drivers/input/max11802.c
@@ -463,7 +463,7 @@ static int max11802_schedule(FAR struct max11802_dev_s *priv)
   ret = work_queue(HPWORK, &priv->work, max11802_worker, priv, 0);
   if (ret != 0)
     {
-      illerr("ERROR: Failed to queue work: %d\n", ret);
+      ierr("ERROR: Failed to queue work: %d\n", ret);
     }
 
   return OK;
diff --git a/drivers/input/mxt.c b/drivers/input/mxt.c
index 48c3dd33aae..891f7811209 100644
--- a/drivers/input/mxt.c
+++ b/drivers/input/mxt.c
@@ -1097,7 +1097,7 @@ static int mxt_interrupt(FAR const struct mxt_lower_s *lower, FAR void *arg)
   ret = work_queue(HPWORK, &priv->work, mxt_worker, priv, 0);
   if (ret != 0)
     {
-      illerr("ERROR: Failed to queue work: %d\n", ret);
+      ierr("ERROR: Failed to queue work: %d\n", ret);
     }
 
   /* Clear any pending interrupts and return success */
diff --git a/drivers/input/stmpe811_base.c b/drivers/input/stmpe811_base.c
index 3cfb7ad0994..dca84ae76a8 100644
--- a/drivers/input/stmpe811_base.c
+++ b/drivers/input/stmpe811_base.c
@@ -199,7 +199,7 @@ static int stmpe811_interrupt(int irq, FAR void *context)
       ret = work_queue(HPWORK, &priv->work, stmpe811_worker, priv, 0);
       if (ret != 0)
         {
-          illerr("ERROR: Failed to queue work: %d\n", ret);
+          ierr("ERROR: Failed to queue work: %d\n", ret);
         }
     }
 
diff --git a/drivers/input/stmpe811_gpio.c b/drivers/input/stmpe811_gpio.c
index 1af52ad1d73..c9933df718b 100644
--- a/drivers/input/stmpe811_gpio.c
+++ b/drivers/input/stmpe811_gpio.c
@@ -438,7 +438,7 @@ void stmpe811_gpioworker(FAR struct stmpe811_dev_s *priv)
             }
           else
             {
-              illerr("ERROR: No handler for PIN%d, GPIO_INTSTA: %02x\n", pin, regval);
+              ierr("ERROR: No handler for PIN%d, GPIO_INTSTA: %02x\n", pin, regval);
             }
 
           /* Clear the pending GPIO interrupt by writing a '1' to the
diff --git a/drivers/input/stmpe811_tsc.c b/drivers/input/stmpe811_tsc.c
index 83068d8011a..b58e9feebd1 100644
--- a/drivers/input/stmpe811_tsc.c
+++ b/drivers/input/stmpe811_tsc.c
@@ -786,7 +786,7 @@ static void stmpe811_timeout(int argc, uint32_t arg1, ...)
           ret = work_queue(HPWORK, &priv->timeout, stmpe811_timeoutworker, priv, 0);
           if (ret != 0)
             {
-              illerr("ERROR: Failed to queue work: %d\n", ret);
+              ierr("ERROR: Failed to queue work: %d\n", ret);
             }
         }
     }
diff --git a/drivers/input/tsc2007.c b/drivers/input/tsc2007.c
index 7b2e90b104f..8d49a2e0705 100644
--- a/drivers/input/tsc2007.c
+++ b/drivers/input/tsc2007.c
@@ -783,7 +783,7 @@ static int tsc2007_interrupt(int irq, FAR void *context)
   ret = work_queue(HPWORK, &priv->work, tsc2007_worker, priv, 0);
   if (ret != 0)
     {
-      illerr("ERROR: Failed to queue work: %d\n", ret);
+      ierr("ERROR: Failed to queue work: %d\n", ret);
     }
 
   /* Clear any pending interrupts and return success */
diff --git a/drivers/lcd/ssd1306_i2c.c b/drivers/lcd/ssd1306_i2c.c
index 969eec4769e..d6de937e35c 100644
--- a/drivers/lcd/ssd1306_i2c.c
+++ b/drivers/lcd/ssd1306_i2c.c
@@ -71,7 +71,7 @@ void ssd1306_sendbyte(FAR struct ssd1306_dev_s *priv, uint8_t regval)
   int ret;
 
 #ifdef CONFIG_LCD_SSD1306_REGDEBUG
-  _llerr("-> 0x%02x\n", regval);
+  _err("-> 0x%02x\n", regval);
 #endif
 
   /* Setup to the data to be transferred.  Two bytes:  The SSD1306 register
diff --git a/drivers/lcd/ssd1306_spi.c b/drivers/lcd/ssd1306_spi.c
index c53faf15d4c..9f3817a7b64 100644
--- a/drivers/lcd/ssd1306_spi.c
+++ b/drivers/lcd/ssd1306_spi.c
@@ -89,7 +89,7 @@ static inline void ssd1306_configspi(FAR struct spi_dev_s *spi)
 void ssd1306_sendbyte(FAR struct ssd1306_dev_s *priv, uint8_t regval)
 {
 #ifdef CONFIG_LCD_SSD1306_REGDEBUG
-  _llerr("->0x%02x\n", regval);
+  _err("->0x%02x\n", regval);
 #endif
 
   /* Send byte value to display */
diff --git a/drivers/leds/pca9635pw.c b/drivers/leds/pca9635pw.c
index 87f18bd288b..8d703982968 100644
--- a/drivers/leds/pca9635pw.c
+++ b/drivers/leds/pca9635pw.c
@@ -121,8 +121,8 @@ static int pca9635pw_i2c_write_byte(FAR struct pca9635pw_dev_s *priv,
 
   /* Write the register address followed by the data (no RESTART) */
 
-  lcdllinfo("i2c addr: 0x%02X reg addr: 0x%02X value: 0x%02X\n", priv->i2c_addr,
-        buffer[0], buffer[1]);
+  lcdinfo("i2c addr: 0x%02X reg addr: 0x%02X value: 0x%02X\n", priv->i2c_addr,
+          buffer[0], buffer[1]);
 
   ret = i2c_write(priv->i2c, &config, buffer, BUFFER_SIZE);
   if (ret != OK)
@@ -280,7 +280,7 @@ static int pca9635pw_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
   FAR struct pca9635pw_dev_s *priv = inode->i_private;
   int ret = OK;
 
-  lcdllinfo("cmd: %d arg: %ld\n", cmd, arg);
+  lcdinfo("cmd: %d arg: %ld\n", cmd, arg);
 
   switch (cmd)
     {
diff --git a/drivers/leds/userled_upper.c b/drivers/leds/userled_upper.c
index 964665d1876..abf7cc719e3 100644
--- a/drivers/leds/userled_upper.c
+++ b/drivers/leds/userled_upper.c
@@ -176,7 +176,7 @@ static int userled_open(FAR struct file *filep)
   ret = userled_takesem(&priv->lu_exclsem);
   if (ret < 0)
     {
-      lcdinfo("ERROR: userled_takesem failed: %d\n", ret);
+      lcderr("ERROR: userled_takesem failed: %d\n", ret);
       return ret;
     }
 
@@ -185,7 +185,7 @@ static int userled_open(FAR struct file *filep)
   opriv = (FAR struct userled_open_s *)kmm_zalloc(sizeof(struct userled_open_s));
   if (!opriv)
     {
-      lcdinfo("ERROR: Failled to allocate open structure\n");
+      lcderr("ERROR: Failled to allocate open structure\n");
       ret = -ENOMEM;
       goto errout_with_sem;
     }
@@ -253,7 +253,7 @@ static int userled_close(FAR struct file *filep)
   ret = userled_takesem(&priv->lu_exclsem);
   if (ret < 0)
     {
-      lcdinfo("ERROR: userled_takesem failed: %d\n", ret);
+      lcderr("ERROR: userled_takesem failed: %d\n", ret);
       return ret;
     }
 
@@ -266,7 +266,7 @@ static int userled_close(FAR struct file *filep)
   DEBUGASSERT(curr);
   if (!curr)
     {
-      lcdinfo("ERROR: Failed to find open entry\n");
+      lcderr("ERROR: Failed to find open entry\n");
       ret = -ENOENT;
       goto errout_with_exclsem;
     }
@@ -318,7 +318,7 @@ static ssize_t userled_write(FAR struct file *filep, FAR const char *buffer,
 
   if (len < sizeof(userled_set_t))
     {
-      lcdinfo("ERROR: buffer too small: %lu\n", (unsigned long)len);
+      lcderr("ERROR: buffer too small: %lu\n", (unsigned long)len);
       return -EINVAL;
     }
 
@@ -335,7 +335,7 @@ static ssize_t userled_write(FAR struct file *filep, FAR const char *buffer,
   ret = userled_takesem(&priv->lu_exclsem);
   if (ret < 0)
     {
-      lcdinfo("ERROR: userled_takesem failed: %d\n", ret);
+      lcderr("ERROR: userled_takesem failed: %d\n", ret);
       return ret;
     }
 
@@ -370,7 +370,7 @@ static int userled_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
   ret = userled_takesem(&priv->lu_exclsem);
   if (ret < 0)
     {
-      lcdinfo("ERROR: userled_takesem failed: %d\n", ret);
+      lcderr("ERROR: userled_takesem failed: %d\n", ret);
       return ret;
     }
 
@@ -500,7 +500,7 @@ static int userled_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
       break;
 
     default:
-      lcdinfo("ERROR: Unrecognized command: %ld\n", cmd);
+      lcderr("ERROR: Unrecognized command: %ld\n", cmd);
       ret = -ENOTTY;
       break;
     }
@@ -548,7 +548,7 @@ int userled_register(FAR const char *devname,
 
   if (!priv)
     {
-      lcdinfo("ERROR: Failed to allocate device structure\n");
+      lcderr("ERROR: Failed to allocate device structure\n");
       return -ENOMEM;
     }
 
@@ -569,7 +569,7 @@ int userled_register(FAR const char *devname,
   ret = register_driver(devname, &userled_fops, 0666, priv);
   if (ret < 0)
     {
-      lcdinfo("ERROR: register_driver failed: %d\n", ret);
+      lcderr("ERROR: register_driver failed: %d\n", ret);
       goto errout_with_priv;
     }
 
diff --git a/drivers/mmcsd/mmcsd_sdio.c b/drivers/mmcsd/mmcsd_sdio.c
index eddf12cb4de..be934950b9e 100644
--- a/drivers/mmcsd/mmcsd_sdio.c
+++ b/drivers/mmcsd/mmcsd_sdio.c
@@ -413,7 +413,7 @@ static int mmcsd_recvR1(FAR struct mmcsd_state_s *priv, uint32_t cmd)
            * indication for later use.
            */
 
-          finfo("ERROR: R1=%08x\n", r1);
+          ferr("ERROR: R1=%08x\n", r1);
           priv->locked = ((r1 & MMCSD_R1_CARDISLOCKED) != 0);
           ret = -EIO;
         }
diff --git a/drivers/modem/u-blox.c b/drivers/modem/u-blox.c
index f3cf094ebe3..b44b4aea5b0 100644
--- a/drivers/modem/u-blox.c
+++ b/drivers/modem/u-blox.c
@@ -60,13 +60,9 @@
 #ifdef CONFIG_MODEM_U_BLOX_DEBUG
 #  define m_err     _err
 #  define m_info    _info
-#  define m_vllerr  _llerr
-#  define m_vllinfo _llinfo
 #else
 #  define m_err(x...)
 #  define m_info(x...)
-#  define m_llerr(x...)
-#  define m_llinfo(x...)
 #endif
 
 /****************************************************************************
diff --git a/drivers/mtd/smart.c b/drivers/mtd/smart.c
index 52676e7ea71..e763e6bcba3 100644
--- a/drivers/mtd/smart.c
+++ b/drivers/mtd/smart.c
@@ -4678,7 +4678,7 @@ static int smart_readsector(FAR struct smart_struct_s *dev,
           sizeof(struct smart_sect_header_s), (FAR uint8_t *) &header);
   if (ret != sizeof(struct smart_sect_header_s))
     {
-      finfo("ERROR: Error reading sector %d header\n", physsector);
+      ferr("ERROR: Error reading sector %d header\n", physsector);
       ret = -EIO;
       goto errout;
     }
diff --git a/drivers/mtd/sst26.c b/drivers/mtd/sst26.c
index 016d72b5b47..91eb045fcf4 100644
--- a/drivers/mtd/sst26.c
+++ b/drivers/mtd/sst26.c
@@ -209,14 +209,10 @@
 
 #ifdef CONFIG_SST26_DEBUG
 # define ssterr(format, ...)    _err(format, ##__VA_ARGS__)
-# define sstllerr(format, ...)  _llerr(format, ##__VA_ARGS__)
 # define sstinfo(format, ...)   _info(format, ##__VA_ARGS__)
-# define sstllinfo(format, ...) _llinfo(format, ##__VA_ARGS__)
 #else
 # define ssterr(x...)
-# define sstllerr(x...)
 # define sstinfo(x...)
-# define sstllinfo(x...)
 #endif
 
 /************************************************************************************
@@ -340,8 +336,8 @@ static inline int sst26_readid(struct sst26_dev_s *priv)
   SPI_SELECT(priv->dev, SPIDEV_FLASH, false);
   sst26_unlock(priv->dev);
 
-  _llinfo("manufacturer: %02x memory: %02x capacity: %02x\n",
-         manufacturer, memory, capacity);
+  _info("manufacturer: %02x memory: %02x capacity: %02x\n",
+        manufacturer, memory, capacity);
 
   /* Check for a valid manufacturer and memory type */
 
diff --git a/drivers/net/cs89x0.c b/drivers/net/cs89x0.c
index 59df81c60f0..dd2af6658bf 100644
--- a/drivers/net/cs89x0.c
+++ b/drivers/net/cs89x0.c
@@ -467,7 +467,7 @@ static void cs89x0_receive(FAR struct cs89x0_driver_s *cs89x0, uint16_t isq)
 #ifdef CONFIG_NET_IPv4
   if (BUF->type == HTONS(ETHTYPE_IP))
     {
-      nllinfo("IPv4 frame\n");
+      ninfo("IPv4 frame\n");
       NETDEV_RXIPV4(&priv->cs_dev);
 
       /* Handle ARP on input then give the IPv4 packet to the network
@@ -508,7 +508,7 @@ static void cs89x0_receive(FAR struct cs89x0_driver_s *cs89x0, uint16_t isq)
 #ifdef CONFIG_NET_IPv6
   if (BUF->type == HTONS(ETHTYPE_IP6))
     {
-      nllinfo("Iv6 frame\n");
+      ninfo("Iv6 frame\n");
       NETDEV_RXIPV6(&priv->cs_dev);
 
       /* Give the IPv6 packet to the network layer */
@@ -561,7 +561,7 @@ static void cs89x0_receive(FAR struct cs89x0_driver_s *cs89x0, uint16_t isq)
   else
 #endif
     {
-      nllinfo("Unrecognized packet type %02x\n", BUF->type);
+      ninfo("Unrecognized packet type %02x\n", BUF->type);
       NETDEV_RXDROPPED(&priv->cs_dev);
     }
 }
diff --git a/drivers/net/dm90x0.c b/drivers/net/dm90x0.c
index f4b98bdc4a8..ddc809f4c50 100644
--- a/drivers/net/dm90x0.c
+++ b/drivers/net/dm90x0.c
@@ -902,7 +902,7 @@ static void dm9x_receive(FAR struct dm9x_driver_s *dm9x)
 #ifdef CONFIG_NET_IPv4
           if (BUF->type == HTONS(ETHTYPE_IP))
             {
-              nllinfo("IPv4 frame\n");
+              ninfo("IPv4 frame\n");
               NETDEV_RXIPV4(&priv->dm_dev);
 
               /* Handle ARP on input then give the IPv4 packet to the network
@@ -943,7 +943,7 @@ static void dm9x_receive(FAR struct dm9x_driver_s *dm9x)
 #ifdef CONFIG_NET_IPv6
           if (BUF->type == HTONS(ETHTYPE_IP6))
             {
-              nllinfo("Iv6 frame\n");
+              ninfo("Iv6 frame\n");
               NETDEV_RXIPV6(&priv->dm_dev);
 
               /* Give the IPv6 packet to the network layer */
@@ -1723,13 +1723,13 @@ int dm9x_initialize(void)
 
   vid = (((uint16_t)getreg(DM9X_VIDH)) << 8) | (uint16_t)getreg(DM9X_VIDL);
   pid = (((uint16_t)getreg(DM9X_PIDH)) << 8) | (uint16_t)getreg(DM9X_PIDL);
-  nllinfo("I/O base: %08x VID: %04x PID: %04x\n", CONFIG_DM9X_BASE, vid, pid);
+  ninfo("I/O base: %08x VID: %04x PID: %04x\n", CONFIG_DM9X_BASE, vid, pid);
 
   /* Check if a DM90x0 chip is recognized at this I/O base */
 
   if (vid != DM9X_DAVICOMVID || (pid != DM9X_DM9000PID && pid != DM9X_DM9010PID))
     {
-      nllerr("ERROR: DM90x0 vendor/product ID not found at this base address\n");
+      nerr("ERROR: DM90x0 vendor/product ID not found at this base address\n");
       return -ENODEV;
     }
 
@@ -1739,7 +1739,7 @@ int dm9x_initialize(void)
     {
       /* We could not attach the ISR to the ISR */
 
-      nllerr("ERROR: irq_attach() failed\n");
+      nerr("ERROR: irq_attach() failed\n");
       return -EAGAIN;
     }
 
@@ -1768,8 +1768,8 @@ int dm9x_initialize(void)
       mptr[i] = getreg(j);
     }
 
-  nllinfo("MAC: %0x:%0x:%0x:%0x:%0x:%0x\n",
-         mptr[0], mptr[1], mptr[2], mptr[3], mptr[4], mptr[5]);
+  ninfo("MAC: %0x:%0x:%0x:%0x:%0x:%0x\n",
+       mptr[0], mptr[1], mptr[2], mptr[3], mptr[4], mptr[5]);
 
   /* Register the device with the OS so that socket IOCTLs can be performed */
 
diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c
index ed9033ed2fb..6d5d5dc4f50 100644
--- a/drivers/net/e1000.c
+++ b/drivers/net/e1000.c
@@ -602,7 +602,7 @@ static void e1000_receive(struct e1000_dev *e1000)
 #ifdef CONFIG_NET_IPv4
       if (BUF->type == HTONS(ETHTYPE_IP))
         {
-          nllinfo("IPv4 frame\n");
+          ninfo("IPv4 frame\n");
 
           /* Handle ARP on input then give the IPv4 packet to the network
            * layer
@@ -642,7 +642,7 @@ static void e1000_receive(struct e1000_dev *e1000)
 #ifdef CONFIG_NET_IPv6
       if (BUF->type == HTONS(ETHTYPE_IP6))
         {
-          nllinfo("Iv6 frame\n");
+          ninfo("Iv6 frame\n");
 
           /* Give the IPv6 packet to the network layer */
 
diff --git a/drivers/net/enc28j60.c b/drivers/net/enc28j60.c
index bdb1b9d3547..98edc13417d 100644
--- a/drivers/net/enc28j60.c
+++ b/drivers/net/enc28j60.c
@@ -195,13 +195,13 @@
 
 #ifdef CONFIG_ENC28J60_REGDEBUG
 #  define enc_wrdump(a,v) \
-   lowsyslog(LOG_DEBUG, "ENC28J60: %02x<-%02x\n", a, v);
+   syslog(LOG_DEBUG, "ENC28J60: %02x<-%02x\n", a, v);
 #  define enc_rddump(a,v) \
-   lowsyslog(LOG_DEBUG, "ENC28J60: %02x->%02x\n", a, v);
+   syslog(LOG_DEBUG, "ENC28J60: %02x->%02x\n", a, v);
 #  define enc_cmddump(c) \
-   lowsyslog(LOG_DEBUG, "ENC28J60: CMD: %02x\n", c);
+   syslog(LOG_DEBUG, "ENC28J60: CMD: %02x\n", c);
 #  define enc_bmdump(c,b,s) \
-   lowsyslog(LOG_DEBUG, "ENC28J60: CMD: %02x buffer: %p length: %d\n", c, b, s);
+   syslog(LOG_DEBUG, "ENC28J60: CMD: %02x buffer: %p length: %d\n", c, b, s);
 #else
 #  define enc_wrdump(a,v)
 #  define enc_rddump(a,v)
@@ -774,56 +774,56 @@ static int enc_waitbreg(FAR struct enc_driver_s *priv, uint8_t ctrlreg,
 #if 0 /* Sometimes useful */
 static void enc_rxdump(FAR struct enc_driver_s *priv)
 {
-  lowsyslog(LOG_DEBUG, "Rx Registers:\n");
-  lowsyslog(LOG_DEBUG, "  EIE:      %02x EIR:      %02x\n",
-            enc_rdgreg(priv, ENC_EIE), enc_rdgreg(priv, ENC_EIR));
-  lowsyslog(LOG_DEBUG, "  ESTAT:    %02x ECON1:    %02x ECON2:    %02x\n",
-            enc_rdgreg(priv, ENC_ESTAT), enc_rdgreg(priv, ENC_ECON1),
-            enc_rdgreg(priv, ENC_ECON2));
-  lowsyslog(LOG_DEBUG, "  ERXST:    %02x %02x\n",
-            enc_rdbreg(priv, ENC_ERXSTH), enc_rdbreg(priv, ENC_ERXSTL));
-  lowsyslog(LOG_DEBUG, "  ERXND:    %02x %02x\n",
-            enc_rdbreg(priv, ENC_ERXNDH), enc_rdbreg(priv, ENC_ERXNDL));
-  lowsyslog(LOG_DEBUG, "  ERXRDPT:  %02x %02x\n",
-            enc_rdbreg(priv, ENC_ERXRDPTH), enc_rdbreg(priv, ENC_ERXRDPTL));
-  lowsyslog(LOG_DEBUG, "  ERXFCON:  %02x EPKTCNT:  %02x\n",
-            enc_rdbreg(priv, ENC_ERXFCON), enc_rdbreg(priv, ENC_EPKTCNT));
-  lowsyslog(LOG_DEBUG, "  MACON1:   %02x MACON3:   %02x\n",
-            enc_rdbreg(priv, ENC_MACON1), enc_rdbreg(priv, ENC_MACON3));
-  lowsyslog(LOG_DEBUG, "  MAMXFL:   %02x %02x\n",
-            enc_rdbreg(priv, ENC_MAMXFLH), enc_rdbreg(priv, ENC_MAMXFLL));
-  lowsyslog(LOG_DEBUG, "  MAADR:    %02x:%02x:%02x:%02x:%02x:%02x\n",
-            enc_rdbreg(priv, ENC_MAADR1), enc_rdbreg(priv, ENC_MAADR2),
-            enc_rdbreg(priv, ENC_MAADR3), enc_rdbreg(priv, ENC_MAADR4),
-            enc_rdbreg(priv, ENC_MAADR5), enc_rdbreg(priv, ENC_MAADR6));
+  syslog(LOG_DEBUG, "Rx Registers:\n");
+  syslog(LOG_DEBUG, "  EIE:      %02x EIR:      %02x\n",
+         enc_rdgreg(priv, ENC_EIE), enc_rdgreg(priv, ENC_EIR));
+  syslog(LOG_DEBUG, "  ESTAT:    %02x ECON1:    %02x ECON2:    %02x\n",
+         enc_rdgreg(priv, ENC_ESTAT), enc_rdgreg(priv, ENC_ECON1),
+         enc_rdgreg(priv, ENC_ECON2));
+  syslog(LOG_DEBUG, "  ERXST:    %02x %02x\n",
+         enc_rdbreg(priv, ENC_ERXSTH), enc_rdbreg(priv, ENC_ERXSTL));
+  syslog(LOG_DEBUG, "  ERXND:    %02x %02x\n",
+         enc_rdbreg(priv, ENC_ERXNDH), enc_rdbreg(priv, ENC_ERXNDL));
+  syslog(LOG_DEBUG, "  ERXRDPT:  %02x %02x\n",
+         enc_rdbreg(priv, ENC_ERXRDPTH), enc_rdbreg(priv, ENC_ERXRDPTL));
+  syslog(LOG_DEBUG, "  ERXFCON:  %02x EPKTCNT:  %02x\n",
+         enc_rdbreg(priv, ENC_ERXFCON), enc_rdbreg(priv, ENC_EPKTCNT));
+  syslog(LOG_DEBUG, "  MACON1:   %02x MACON3:   %02x\n",
+         enc_rdbreg(priv, ENC_MACON1), enc_rdbreg(priv, ENC_MACON3));
+  syslog(LOG_DEBUG, "  MAMXFL:   %02x %02x\n",
+         enc_rdbreg(priv, ENC_MAMXFLH), enc_rdbreg(priv, ENC_MAMXFLL));
+  syslog(LOG_DEBUG, "  MAADR:    %02x:%02x:%02x:%02x:%02x:%02x\n",
+         enc_rdbreg(priv, ENC_MAADR1), enc_rdbreg(priv, ENC_MAADR2),
+         enc_rdbreg(priv, ENC_MAADR3), enc_rdbreg(priv, ENC_MAADR4),
+         enc_rdbreg(priv, ENC_MAADR5), enc_rdbreg(priv, ENC_MAADR6));
 }
 #endif
 
 #if 0 /* Sometimes useful */
 static void enc_txdump(FAR struct enc_driver_s *priv)
 {
-  lowsyslog(LOG_DEBUG, "Tx Registers:\n");
-  lowsyslog(LOG_DEBUG, "  EIE:      %02x EIR:      %02x\n",
-            enc_rdgreg(priv, ENC_EIE), enc_rdgreg(priv, ENC_EIR));
-  lowsyslog(LOG_DEBUG, "  ESTAT:    %02x ECON1:    %02x\n",
-            enc_rdgreg(priv, ENC_ESTAT), enc_rdgreg(priv, ENC_ECON1));
-  lowsyslog(LOG_DEBUG, "  ETXST:    %02x %02x\n",
-            enc_rdbreg(priv, ENC_ETXSTH), enc_rdbreg(priv, ENC_ETXSTL));
-  lowsyslog(LOG_DEBUG, "  ETXND:    %02x %02x\n",
-            enc_rdbreg(priv, ENC_ETXNDH), enc_rdbreg(priv, ENC_ETXNDL));
-  lowsyslog(LOG_DEBUG, "  MACON1:   %02x MACON3:   %02x MACON4:   %02x\n",
-            enc_rdbreg(priv, ENC_MACON1), enc_rdbreg(priv, ENC_MACON3),
-            enc_rdbreg(priv, ENC_MACON4));
-  lowsyslog(LOG_DEBUG, "  MACON1:   %02x MACON3:   %02x MACON4:   %02x\n",
-            enc_rdbreg(priv, ENC_MACON1), enc_rdbreg(priv, ENC_MACON3),
-            enc_rdbreg(priv, ENC_MACON4));
-  lowsyslog(LOG_DEBUG, "  MABBIPG:  %02x MAIPG %02x %02x\n",
-            enc_rdbreg(priv, ENC_MABBIPG), enc_rdbreg(priv, ENC_MAIPGH),
-            enc_rdbreg(priv, ENC_MAIPGL));
-  lowsyslog(LOG_DEBUG, "  MACLCON1: %02x MACLCON2:   %02x\n",
-            enc_rdbreg(priv, ENC_MACLCON1), enc_rdbreg(priv, ENC_MACLCON2));
-  lowsyslog(LOG_DEBUG, "  MAMXFL:   %02x %02x\n",
-            enc_rdbreg(priv, ENC_MAMXFLH), enc_rdbreg(priv, ENC_MAMXFLL));
+  syslog(LOG_DEBUG, "Tx Registers:\n");
+  syslog(LOG_DEBUG, "  EIE:      %02x EIR:      %02x\n",
+         enc_rdgreg(priv, ENC_EIE), enc_rdgreg(priv, ENC_EIR));
+  syslog(LOG_DEBUG, "  ESTAT:    %02x ECON1:    %02x\n",
+         enc_rdgreg(priv, ENC_ESTAT), enc_rdgreg(priv, ENC_ECON1));
+  syslog(LOG_DEBUG, "  ETXST:    %02x %02x\n",
+         enc_rdbreg(priv, ENC_ETXSTH), enc_rdbreg(priv, ENC_ETXSTL));
+  syslog(LOG_DEBUG, "  ETXND:    %02x %02x\n",
+         enc_rdbreg(priv, ENC_ETXNDH), enc_rdbreg(priv, ENC_ETXNDL));
+  syslog(LOG_DEBUG, "  MACON1:   %02x MACON3:   %02x MACON4:   %02x\n",
+         enc_rdbreg(priv, ENC_MACON1), enc_rdbreg(priv, ENC_MACON3),
+         enc_rdbreg(priv, ENC_MACON4));
+  syslog(LOG_DEBUG, "  MACON1:   %02x MACON3:   %02x MACON4:   %02x\n",
+         enc_rdbreg(priv, ENC_MACON1), enc_rdbreg(priv, ENC_MACON3),
+         enc_rdbreg(priv, ENC_MACON4));
+  syslog(LOG_DEBUG, "  MABBIPG:  %02x MAIPG %02x %02x\n",
+         enc_rdbreg(priv, ENC_MABBIPG), enc_rdbreg(priv, ENC_MAIPGH),
+         enc_rdbreg(priv, ENC_MAIPGL));
+  syslog(LOG_DEBUG, "  MACLCON1: %02x MACLCON2:   %02x\n",
+         enc_rdbreg(priv, ENC_MACLCON1), enc_rdbreg(priv, ENC_MACLCON2));
+  syslog(LOG_DEBUG, "  MAMXFL:   %02x %02x\n",
+         enc_rdbreg(priv, ENC_MAMXFLH), enc_rdbreg(priv, ENC_MAMXFLL));
 }
 #endif
 
@@ -1092,7 +1092,7 @@ static int enc_transmit(FAR struct enc_driver_s *priv)
 
   /* Increment statistics */
 
-  nllinfo("Sending packet, pktlen: %d\n", priv->dev.d_len);
+  ninfo("Sending packet, pktlen: %d\n", priv->dev.d_len);
   NETDEV_TXPACKETS(&priv->dev);
 
   /* Verify that the hardware is ready to send another packet.  The driver
@@ -1180,7 +1180,7 @@ static int enc_txpoll(struct net_driver_s *dev)
    * the field d_len is set to a value > 0.
    */
 
-  nllinfo("Poll result: d_len=%d\n", priv->dev.d_len);
+  ninfo("Poll result: d_len=%d\n", priv->dev.d_len);
   if (priv->dev.d_len > 0)
     {
       /* Look up the destination MAC address and add it to the Ethernet
@@ -1388,7 +1388,7 @@ static void enc_rxdispatch(FAR struct enc_driver_s *priv)
 #ifdef CONFIG_NET_IPv4
   if (BUF->type == HTONS(ETHTYPE_IP))
     {
-      nllinfo("IPv4 frame\n");
+      ninfo("IPv4 frame\n");
       NETDEV_RXIPV4(&priv->dev);
 
       /* Handle ARP on input then give the IPv4 packet to the network
@@ -1429,7 +1429,7 @@ static void enc_rxdispatch(FAR struct enc_driver_s *priv)
 #ifdef CONFIG_NET_IPv6
   if (BUF->type == HTONS(ETHTYPE_IP6))
     {
-      nllinfo("Iv6 frame\n");
+      ninfo("Iv6 frame\n");
       NETDEV_RXIPV6(&priv->dev);
 
       /* Give the IPv6 packet to the network layer */
@@ -1467,7 +1467,7 @@ static void enc_rxdispatch(FAR struct enc_driver_s *priv)
 #ifdef CONFIG_NET_ARP
   if (BUF->type == htons(ETHTYPE_ARP))
     {
-      nllinfo("ARP packet received (%02x)\n", BUF->type);
+      ninfo("ARP packet received (%02x)\n", BUF->type);
       NETDEV_RXARP(&priv->dev);
 
       arp_arpin(&priv->dev);
@@ -1484,7 +1484,7 @@ static void enc_rxdispatch(FAR struct enc_driver_s *priv)
   else
 #endif
     {
-      nllerr("ERROR: Unsupported packet type dropped (%02x)\n", htons(BUF->type));
+      nerr("ERROR: Unsupported packet type dropped (%02x)\n", htons(BUF->type));
       NETDEV_RXDROPPED(&priv->dev);
     }
 }
@@ -1543,14 +1543,14 @@ static void enc_pktif(FAR struct enc_driver_s *priv)
   pktlen        = (uint16_t)rsv[3] << 8 | (uint16_t)rsv[2];
   rxstat        = (uint16_t)rsv[5] << 8 | (uint16_t)rsv[4];
 
-  nllinfo("Receiving packet, nextpkt: %04x pktlen: %d rxstat: %04x\n",
-          priv->nextpkt, pktlen, rxstat);
+  ninfo("Receiving packet, nextpkt: %04x pktlen: %d rxstat: %04x\n",
+        priv->nextpkt, pktlen, rxstat);
 
   /* Check if the packet was received OK */
 
   if ((rxstat & RXSTAT_OK) == 0)
     {
-      nllerr("ERROR: RXSTAT: %04x\n", rxstat);
+      nerr("ERROR: RXSTAT: %04x\n", rxstat);
       NETDEV_RXERRORS(&priv->dev);
     }
 
@@ -1558,7 +1558,7 @@ static void enc_pktif(FAR struct enc_driver_s *priv)
 
   else if (pktlen > (CONFIG_NET_ETH_MTU + 4) || pktlen <= (ETH_HDRLEN + 4))
     {
-      nllerr("ERROR: Bad packet size dropped (%d)\n", pktlen);
+      nerr("ERROR: Bad packet size dropped (%d)\n", pktlen);
       NETDEV_RXERRORS(&priv->dev);
     }
 
@@ -1647,7 +1647,7 @@ static void enc_irqworker(FAR void *arg)
        * settings.
        */
 
-      nllinfo("EIR: %02x\n", eir);
+      ninfo("EIR: %02x\n", eir);
 
       /* DMAIF: The DMA interrupt indicates that the DMA module has completed
        * its memory copy or checksum calculation. Additionally, this interrupt
@@ -1767,7 +1767,7 @@ static void enc_irqworker(FAR void *arg)
           uint8_t pktcnt = enc_rdbreg(priv, ENC_EPKTCNT);
           if (pktcnt > 0)
             {
-              nllinfo("EPKTCNT: %02x\n", pktcnt);
+              nerr("EPKTCNT: %02x\n", pktcnt);
 
               /* Handle packet receipt */
 
@@ -1878,7 +1878,7 @@ static void enc_toworker(FAR void *arg)
   net_lock_t lock;
   int ret;
 
-  nllerr("ERROR: Tx timeout\n");
+  nerr("ERROR: Tx timeout\n");
   DEBUGASSERT(priv);
 
   /* Get exclusive access to the network */
@@ -2067,9 +2067,9 @@ static int enc_ifup(struct net_driver_s *dev)
   FAR struct enc_driver_s *priv = (FAR struct enc_driver_s *)dev->d_private;
   int ret;
 
-  nllinfo("Bringing up: %d.%d.%d.%d\n",
-          dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff,
-          (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24);
+  ninfo("Bringing up: %d.%d.%d.%d\n",
+        dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff,
+        (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24);
 
   /* Lock the SPI bus so that we have exclusive access */
 
@@ -2139,9 +2139,9 @@ static int enc_ifdown(struct net_driver_s *dev)
   irqstate_t flags;
   int ret;
 
-  nllinfo("Taking down: %d.%d.%d.%d\n",
-          dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff,
-          (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24);
+  ninfo("Taking down: %d.%d.%d.%d\n",
+        dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff,
+        (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24);
 
   /* Lock the SPI bus so that we have exclusive access */
 
@@ -2336,7 +2336,7 @@ static int enc_rmmac(struct net_driver_s *dev, FAR const uint8_t *mac)
 
 static void enc_pwrsave(FAR struct enc_driver_s *priv)
 {
-  nllinfo("Set PWRSV\n");
+  ninfo("Set PWRSV\n");
 
   /* 1. Turn off packet reception by clearing ECON1.RXEN. */
 
@@ -2396,7 +2396,7 @@ static void enc_pwrsave(FAR struct enc_driver_s *priv)
 
 static void enc_pwrfull(FAR struct enc_driver_s *priv)
 {
-  nllinfo("Clear PWRSV\n");
+  ninfo("Clear PWRSV\n");
 
   /* 1. Wake-up by clearing ECON2.PWRSV. */
 
@@ -2473,7 +2473,7 @@ static int enc_reset(FAR struct enc_driver_s *priv)
 {
   uint8_t regval;
 
-  nllwarn("WARNING: Reset\n");
+  nwarn("WARNING: Reset\n");
 
   /* Configure SPI for the ENC28J60 */
 
@@ -2524,11 +2524,11 @@ static int enc_reset(FAR struct enc_driver_s *priv)
   regval = enc_rdbreg(priv, ENC_EREVID);
   if (regval == 0x00 || regval == 0xff)
     {
-      nllerr("ERROR: Bad Rev ID: %02x\n", regval);
+      nerr("ERROR: Bad Rev ID: %02x\n", regval);
       return -ENODEV;
     }
 
-  nllinfo("Rev ID: %02x\n", regval);
+  ninfo("Rev ID: %02x\n", regval);
 
   /* Set filter mode: unicast OR broadcast AND crc valid */
 
diff --git a/drivers/net/encx24j600.c b/drivers/net/encx24j600.c
index 02a24919018..b829d9cd97e 100644
--- a/drivers/net/encx24j600.c
+++ b/drivers/net/encx24j600.c
@@ -187,17 +187,17 @@
 
 #ifdef CONFIG_ENCX24J600_REGDEBUG
 #  define enc_wrdump(a,v) \
-   lowsyslog(LOG_DEBUG, "ENCX24J600: %02x<-%04x\n", a, v);
+   syslog(LOG_DEBUG, "ENCX24J600: %02x<-%04x\n", a, v);
 #  define enc_rddump(a,v) \
-   lowsyslog(LOG_DEBUG, "ENCX24J600: %02x->%04x\n", a, v);
+   syslog(LOG_DEBUG, "ENCX24J600: %02x->%04x\n", a, v);
 #  define enc_bfsdump(a,m) \
-   lowsyslog(LOG_DEBUG, "ENCX24J600: %02x|=%04x\n", a, m);
+   syslog(LOG_DEBUG, "ENCX24J600: %02x|=%04x\n", a, m);
 #  define enc_bfcdump(a,m) \
-   lowsyslog(LOG_DEBUG, "ENCX24J600: %02x&=~%04x\n", a, m);
+   syslog(LOG_DEBUG, "ENCX24J600: %02x&=~%04x\n", a, m);
 #  define enc_cmddump(c) \
-   lowsyslog(LOG_DEBUG, "ENCX24J600: CMD: %02x\n", c);
+   syslog(LOG_DEBUG, "ENCX24J600: CMD: %02x\n", c);
 #  define enc_bmdump(c,b,s) \
-   lowsyslog(LOG_DEBUG, "ENCX24J600: CMD: %02x buffer: %p length: %d\n", c, b, s);
+   syslog(LOG_DEBUG, "ENCX24J600: CMD: %02x buffer: %p length: %d\n", c, b, s);
 #else
 #  define enc_wrdump(a,v)
 #  define enc_rddump(a,v)
@@ -764,56 +764,56 @@ static void enc_bfc(FAR struct enc_driver_s *priv, uint16_t ctrlreg,
 #if 0 /* Sometimes useful */
 static void enc_rxdump(FAR struct enc_driver_s *priv)
 {
-  lowsyslog(LOG_DEBUG, "Rx Registers:\n");
-  lowsyslog(LOG_DEBUG, "  EIE:      %02x EIR:      %02x\n",
-            enc_rdgreg(priv, ENC_EIE), enc_rdgreg(priv, ENC_EIR));
-  lowsyslog(LOG_DEBUG, "  ESTAT:    %02x ECON1:    %02x ECON2:    %02x\n",
-            enc_rdgreg(priv, ENC_ESTAT), enc_rdgreg(priv, ENC_ECON1),
-            enc_rdgreg(priv, ENC_ECON2));
-  lowsyslog(LOG_DEBUG, "  ERXST:    %02x %02x\n",
-            enc_rdbreg(priv, ENC_ERXSTH), enc_rdbreg(priv, ENC_ERXSTL));
-  lowsyslog(LOG_DEBUG, "  ERXND:    %02x %02x\n",
-            enc_rdbreg(priv, ENC_ERXNDH), enc_rdbreg(priv, ENC_ERXNDL));
-  lowsyslog(LOG_DEBUG, "  ERXRDPT:  %02x %02x\n",
-            enc_rdbreg(priv, ENC_ERXRDPTH), enc_rdbreg(priv, ENC_ERXRDPTL));
-  lowsyslog(LOG_DEBUG, "  ERXFCON:  %02x EPKTCNT:  %02x\n",
-            enc_rdbreg(priv, ENC_ERXFCON), enc_rdbreg(priv, ENC_EPKTCNT));
-  lowsyslog(LOG_DEBUG, "  MACON1:   %02x MACON3:   %02x\n",
-            enc_rdbreg(priv, ENC_MACON1), enc_rdbreg(priv, ENC_MACON3));
-  lowsyslog(LOG_DEBUG, "  MAMXFL:   %02x %02x\n",
-            enc_rdbreg(priv, ENC_MAMXFLH), enc_rdbreg(priv, ENC_MAMXFLL));
-  lowsyslog(LOG_DEBUG, "  MAADR:    %02x:%02x:%02x:%02x:%02x:%02x\n",
-            enc_rdbreg(priv, ENC_MAADR1), enc_rdbreg(priv, ENC_MAADR2),
-            enc_rdbreg(priv, ENC_MAADR3), enc_rdbreg(priv, ENC_MAADR4),
-            enc_rdbreg(priv, ENC_MAADR5), enc_rdbreg(priv, ENC_MAADR6));
+  syslog(LOG_DEBUG, "Rx Registers:\n");
+  syslog(LOG_DEBUG, "  EIE:      %02x EIR:      %02x\n",
+         enc_rdgreg(priv, ENC_EIE), enc_rdgreg(priv, ENC_EIR));
+  syslog(LOG_DEBUG, "  ESTAT:    %02x ECON1:    %02x ECON2:    %02x\n",
+         enc_rdgreg(priv, ENC_ESTAT), enc_rdgreg(priv, ENC_ECON1),
+         enc_rdgreg(priv, ENC_ECON2));
+  syslog(LOG_DEBUG, "  ERXST:    %02x %02x\n",
+         enc_rdbreg(priv, ENC_ERXSTH), enc_rdbreg(priv, ENC_ERXSTL));
+  syslog(LOG_DEBUG, "  ERXND:    %02x %02x\n",
+         enc_rdbreg(priv, ENC_ERXNDH), enc_rdbreg(priv, ENC_ERXNDL));
+  syslog(LOG_DEBUG, "  ERXRDPT:  %02x %02x\n",
+         enc_rdbreg(priv, ENC_ERXRDPTH), enc_rdbreg(priv, ENC_ERXRDPTL));
+  syslog(LOG_DEBUG, "  ERXFCON:  %02x EPKTCNT:  %02x\n",
+         enc_rdbreg(priv, ENC_ERXFCON), enc_rdbreg(priv, ENC_EPKTCNT));
+  syslog(LOG_DEBUG, "  MACON1:   %02x MACON3:   %02x\n",
+         enc_rdbreg(priv, ENC_MACON1), enc_rdbreg(priv, ENC_MACON3));
+  syslog(LOG_DEBUG, "  MAMXFL:   %02x %02x\n",
+         enc_rdbreg(priv, ENC_MAMXFLH), enc_rdbreg(priv, ENC_MAMXFLL));
+  syslog(LOG_DEBUG, "  MAADR:    %02x:%02x:%02x:%02x:%02x:%02x\n",
+         enc_rdbreg(priv, ENC_MAADR1), enc_rdbreg(priv, ENC_MAADR2),
+         enc_rdbreg(priv, ENC_MAADR3), enc_rdbreg(priv, ENC_MAADR4),
+         enc_rdbreg(priv, ENC_MAADR5), enc_rdbreg(priv, ENC_MAADR6));
 }
 #endif
 
 #if 0 /* Sometimes useful */
 static void enc_txdump(FAR struct enc_driver_s *priv)
 {
-  lowsyslog(LOG_DEBUG, "Tx Registers:\n");
-  lowsyslog(LOG_DEBUG, "  EIE:      %02x EIR:      %02x\n",
-            enc_rdgreg(priv, ENC_EIE), enc_rdgreg(priv, ENC_EIR));
-  lowsyslog(LOG_DEBUG, "  ESTAT:    %02x ECON1:    %02x\n",
-            enc_rdgreg(priv, ENC_ESTAT), enc_rdgreg(priv, ENC_ECON1));
-  lowsyslog(LOG_DEBUG, "  ETXST:    %02x %02x\n",
-            enc_rdbreg(priv, ENC_ETXSTH), enc_rdbreg(priv, ENC_ETXSTL));
-  lowsyslog(LOG_DEBUG, "  ETXND:    %02x %02x\n",
-            enc_rdbreg(priv, ENC_ETXNDH), enc_rdbreg(priv, ENC_ETXNDL));
-  lowsyslog(LOG_DEBUG, "  MACON1:   %02x MACON3:   %02x MACON4:   %02x\n",
-            enc_rdbreg(priv, ENC_MACON1), enc_rdbreg(priv, ENC_MACON3),
-            enc_rdbreg(priv, ENC_MACON4));
-  lowsyslog(LOG_DEBUG, "  MACON1:   %02x MACON3:   %02x MACON4:   %02x\n",
-            enc_rdbreg(priv, ENC_MACON1), enc_rdbreg(priv, ENC_MACON3),
-            enc_rdbreg(priv, ENC_MACON4));
-  lowsyslog(LOG_DEBUG, "  MABBIPG:  %02x MAIPG %02x %02x\n",
-            enc_rdbreg(priv, ENC_MABBIPG), enc_rdbreg(priv, ENC_MAIPGH),
-            enc_rdbreg(priv, ENC_MAIPGL));
-  lowsyslog(LOG_DEBUG, "  MACLCON1: %02x MACLCON2:   %02x\n",
-            enc_rdbreg(priv, ENC_MACLCON1), enc_rdbreg(priv, ENC_MACLCON2));
-  lowsyslog(LOG_DEBUG, "  MAMXFL:   %02x %02x\n",
-            enc_rdbreg(priv, ENC_MAMXFLH), enc_rdbreg(priv, ENC_MAMXFLL));
+  syslog(LOG_DEBUG, "Tx Registers:\n");
+  syslog(LOG_DEBUG, "  EIE:      %02x EIR:      %02x\n",
+         enc_rdgreg(priv, ENC_EIE), enc_rdgreg(priv, ENC_EIR));
+  syslog(LOG_DEBUG, "  ESTAT:    %02x ECON1:    %02x\n",
+         enc_rdgreg(priv, ENC_ESTAT), enc_rdgreg(priv, ENC_ECON1));
+  syslog(LOG_DEBUG, "  ETXST:    %02x %02x\n",
+         enc_rdbreg(priv, ENC_ETXSTH), enc_rdbreg(priv, ENC_ETXSTL));
+  syslog(LOG_DEBUG, "  ETXND:    %02x %02x\n",
+         enc_rdbreg(priv, ENC_ETXNDH), enc_rdbreg(priv, ENC_ETXNDL));
+  syslog(LOG_DEBUG, "  MACON1:   %02x MACON3:   %02x MACON4:   %02x\n",
+         enc_rdbreg(priv, ENC_MACON1), enc_rdbreg(priv, ENC_MACON3),
+         enc_rdbreg(priv, ENC_MACON4));
+  syslog(LOG_DEBUG, "  MACON1:   %02x MACON3:   %02x MACON4:   %02x\n",
+         enc_rdbreg(priv, ENC_MACON1), enc_rdbreg(priv, ENC_MACON3),
+         enc_rdbreg(priv, ENC_MACON4));
+  syslog(LOG_DEBUG, "  MABBIPG:  %02x MAIPG %02x %02x\n",
+         enc_rdbreg(priv, ENC_MABBIPG), enc_rdbreg(priv, ENC_MAIPGH),
+         enc_rdbreg(priv, ENC_MAIPGL));
+  syslog(LOG_DEBUG, "  MACLCON1: %02x MACLCON2:   %02x\n",
+         enc_rdbreg(priv, ENC_MACLCON1), enc_rdbreg(priv, ENC_MACLCON2));
+  syslog(LOG_DEBUG, "  MAMXFL:   %02x %02x\n",
+         enc_rdbreg(priv, ENC_MAMXFLH), enc_rdbreg(priv, ENC_MAMXFLL));
 }
 #endif
 
@@ -1127,7 +1127,7 @@ static int enc_txenqueue(FAR struct enc_driver_s *priv)
     }
   else
     {
-      nllerr("ERROR: no free descriptors\n");
+      nerr("ERROR: no free descriptors\n");
       ret = -ENOMEM;
     }
 
@@ -1165,7 +1165,7 @@ static int enc_txpoll(struct net_driver_s *dev)
    * the field d_len is set to a value > 0.
    */
 
-  nllinfo("Poll result: d_len=%d\n", priv->dev.d_len);
+  ninfo("Poll result: d_len=%d\n", priv->dev.d_len);
 
   if (priv->dev.d_len > 0)
     {
@@ -1331,7 +1331,7 @@ static void enc_rxldpkt(FAR struct enc_driver_s *priv,
 {
   DEBUGASSERT(priv != NULL && descr != NULL);
 
-  nllinfo("load packet @%04x len: %d\n", descr->addr, descr->len);
+  ninfo("load packet @%04x len: %d\n", descr->addr, descr->len);
 
   /* Set the rx data pointer to the start of the received packet (ERXRDPT) */
 
@@ -1403,7 +1403,7 @@ static void enc_rxrmpkt(FAR struct enc_driver_s *priv, FAR struct enc_descr_s *d
 {
   uint16_t addr;
 
-  nllinfo("free descr: %p\n", descr);
+  ninfo("free descr: %p\n", descr);
 
   /* If it is the last descriptor in the queue, advance ERXTAIL.
    * This way it is possible that gaps occcur. Maybe pending packets
@@ -1420,7 +1420,7 @@ static void enc_rxrmpkt(FAR struct enc_driver_s *priv, FAR struct enc_descr_s *d
 
           DEBUGASSERT(addr >= PKTMEM_RX_START &&  addr < PKTMEM_RX_END);
 
-          nllinfo("ERXTAIL %04x\n", addr);
+          ninfo("ERXTAIL %04x\n", addr);
 
           enc_wrreg(priv, ENC_ERXTAIL, addr);
 
@@ -1490,7 +1490,7 @@ static void enc_rxdispatch(FAR struct enc_driver_s *priv)
 #ifdef CONFIG_NET_IPv4
       if (BUF->type == HTONS(ETHTYPE_IP))
         {
-          nllinfo("IPv4 frame\n");
+          ninfo("IPv4 frame\n");
           NETDEV_RXIPV4(&priv->dev);
 
           /* Handle ARP on input then give the IPv4 packet to the network
@@ -1540,7 +1540,7 @@ static void enc_rxdispatch(FAR struct enc_driver_s *priv)
 #ifdef CONFIG_NET_IPv6
       if (BUF->type == HTONS(ETHTYPE_IP6))
         {
-          nllinfo("Iv6 frame\n");
+          ninfo("Iv6 frame\n");
           NETDEV_RXIPV6(&priv->dev);
 
           /* Give the IPv6 packet to the network layer */
@@ -1587,7 +1587,7 @@ static void enc_rxdispatch(FAR struct enc_driver_s *priv)
 #ifdef CONFIG_NET_ARP
       if (BUF->type == htons(ETHTYPE_ARP))
         {
-          nllinfo("ARP packet received (%02x)\n", BUF->type);
+          ninfo("ARP packet received (%02x)\n", BUF->type);
           NETDEV_RXARP(&priv->dev);
 
           arp_arpin(&priv->dev);
@@ -1612,7 +1612,7 @@ static void enc_rxdispatch(FAR struct enc_driver_s *priv)
 
           enc_rxrmpkt(priv, descr);
 
-          nllerr("ERROR: Unsupported packet type dropped (%02x)\n", htons(BUF->type));
+          nerr("ERROR: Unsupported packet type dropped (%02x)\n", htons(BUF->type));
           NETDEV_RXDROPPED(&priv->dev);
         }
 
@@ -1684,8 +1684,8 @@ static void enc_pktif(FAR struct enc_driver_s *priv)
       rxstat        = (uint32_t)rsv[7] << 24 | (uint32_t)rsv[6] << 16 |
                       (uint32_t)rsv[5] << 8  | (uint32_t)rsv[4];
 
-      nllinfo("Receiving packet, nextpkt: %04x pktlen: %d rxstat: %08x pktcnt: %d\n",
-             priv->nextpkt, pktlen, rxstat, pktcnt);
+      ninfo("Receiving packet, nextpkt: %04x pktlen: %d rxstat: %08x pktcnt: %d\n",
+            priv->nextpkt, pktlen, rxstat, pktcnt);
 
       /* We enqueue the packet first and remove it later if its faulty.
        * This way we avoid freeing packets that are not processed yet.
@@ -1707,7 +1707,7 @@ static void enc_pktif(FAR struct enc_driver_s *priv)
 
       if ((rxstat & RXSTAT_OK) == 0)
         {
-          nllerr("ERROR: RXSTAT: %08x\n", rxstat);
+          nerr("ERROR: RXSTAT: %08x\n", rxstat);
 
           /* Discard packet */
 
@@ -1719,7 +1719,7 @@ static void enc_pktif(FAR struct enc_driver_s *priv)
 
       else if (pktlen > (CONFIG_NET_ETH_MTU + 4) || pktlen <= (ETH_HDRLEN + 4))
         {
-          nllerr("ERROR: Bad packet size dropped (%d)\n", pktlen);
+          nerr("ERROR: Bad packet size dropped (%d)\n", pktlen);
 
           /* Discard packet */
 
@@ -1774,17 +1774,17 @@ static void enc_rxabtif(FAR struct enc_driver_s *priv)
 #if 0
   /* Free the last received packet from the RX queue */
 
-  nllinfo("rx abort\n");
-  nllinfo("ESTAT:   %04x\n", enc_rdreg(priv, ENC_ESTAT));
-  nllinfo("EIR:     %04x\n", enc_rdreg(priv, ENC_EIR));
-  nllinfo("ERXTAIL: %04x\n", enc_rdreg(priv, ENC_ERXTAIL));
-  nllinfo("ERXHAED: %04x\n", enc_rdreg(priv, ENC_ERXHEAD));
+  ninfo("rx abort\n");
+  ninfo("ESTAT:   %04x\n", enc_rdreg(priv, ENC_ESTAT));
+  ninfo("EIR:     %04x\n", enc_rdreg(priv, ENC_EIR));
+  ninfo("ERXTAIL: %04x\n", enc_rdreg(priv, ENC_ERXTAIL));
+  ninfo("ERXHAED: %04x\n", enc_rdreg(priv, ENC_ERXHEAD));
 
   descr = (FAR struct enc_descr_s *)sq_peek(&priv->rxqueue);
 
   while (descr != NULL)
     {
-      nllinfo("addr: %04x len: %d\n", descr->addr, descr->len);
+      ninfo("addr: %04x len: %d\n", descr->addr, descr->len);
       descr = (FAR struct enc_descr_s *)sq_next(descr);
     }
 
@@ -1797,7 +1797,7 @@ static void enc_rxabtif(FAR struct enc_driver_s *priv)
     {
       enc_rxrmpkt(priv, descr);
 
-      nllinfo("pending packet freed\n");
+      ninfo("pending packet freed\n");
     }
   else
     {
@@ -1859,7 +1859,7 @@ static void enc_irqworker(FAR void *arg)
        * settings.
        */
 
-      nllinfo("EIR: %04x\n", eir);
+      ninfo("EIR: %04x\n", eir);
 
       if ((eir & EIR_DMAIF) != 0) /* DMA interrupt */
         {
@@ -2043,7 +2043,7 @@ static void enc_toworker(FAR void *arg)
   net_lock_t lock;
   int ret;
 
-  nllerr("ERROR: Tx timeout\n");
+  nerr("ERROR: Tx timeout\n");
   DEBUGASSERT(priv);
 
   /* Get exclusive access to the network. */
@@ -2231,9 +2231,9 @@ static int enc_ifup(struct net_driver_s *dev)
   FAR struct enc_driver_s *priv = (FAR struct enc_driver_s *)dev->d_private;
   int ret;
 
-  nllinfo("Bringing up: %d.%d.%d.%d\n",
-          dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff,
-          (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24);
+  ninfo("Bringing up: %d.%d.%d.%d\n",
+        dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff,
+        (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24);
 
   /* Lock the SPI bus so that we have exclusive access */
 
@@ -2307,9 +2307,9 @@ static int enc_ifdown(struct net_driver_s *dev)
   irqstate_t flags;
   int ret;
 
-  nllinfo("Taking down: %d.%d.%d.%d\n",
-          dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff,
-          (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24);
+  ninfo("Taking down: %d.%d.%d.%d\n",
+        dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff,
+        (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24);
 
   /* Lock the SPI bus so that we have exclusive access */
 
@@ -2420,7 +2420,7 @@ static int enc_rxavail(struct net_driver_s *dev)
 
   if (!sq_empty(&priv->rxqueue))
     {
-      nllinfo("RX queue not empty, trying to dispatch\n");
+      ninfo("RX queue not empty, trying to dispatch\n");
       enc_rxdispatch(priv);
     }
 
@@ -2546,7 +2546,7 @@ static void enc_pwrsave(FAR struct enc_driver_s *priv)
 {
   uint16_t regval;
 
-  nllinfo("Set PWRSV\n");
+  ninfo("Set PWRSV\n");
 
   /* 1. Turn off AES */
 
@@ -2728,7 +2728,7 @@ static int enc_reset(FAR struct enc_driver_s *priv)
   int ret;
   uint16_t regval;
 
-  nllinfo("Reset\n");
+  ninfo("Reset\n");
 
   do
     {
@@ -2742,7 +2742,7 @@ static int enc_reset(FAR struct enc_driver_s *priv)
 
   if (ret != OK)
     {
-      nllerr("ERROR: encx24j600 clock failed to become ready\n");
+      nerr("ERROR: encx24j600 clock failed to become ready\n");
       return -ENODEV;
     }
 
@@ -2756,7 +2756,7 @@ static int enc_reset(FAR struct enc_driver_s *priv)
 
   if (regval != 0x0000)
     {
-      nllerr("ERROR: encx24j600 seems not to be reset properly\n");
+      nerr("ERROR: encx24j600 seems not to be reset properly\n");
       return -ENODEV;
     }
 
@@ -2793,7 +2793,7 @@ static int enc_reset(FAR struct enc_driver_s *priv)
     }
   while ((regval & PHSTAT1_ANDONE) != 0);
 
-  nllinfo("Auto-negotation completed\n");
+  ninfo("Auto-negotation completed\n");
 
 #endif
 
@@ -2813,7 +2813,7 @@ static int enc_reset(FAR struct enc_driver_s *priv)
 #if 0
   if (ret != OK)
     {
-      nllerr("ERROR: encx24j600 failed to establish link\n");
+      nerr("ERROR: encx24j600 failed to establish link\n");
       return -ENODEV;
     }
 #endif
diff --git a/drivers/net/ftmac100.c b/drivers/net/ftmac100.c
index 9349a3da010..32890af9069 100644
--- a/drivers/net/ftmac100.c
+++ b/drivers/net/ftmac100.c
@@ -685,7 +685,7 @@ static void ftmac100_receive(FAR struct ftmac100_driver_s *priv)
 #ifdef CONFIG_NET_IPv4
       if (BUF->type == HTONS(ETHTYPE_IP))
         {
-          nllinfo("IPv4 frame\n");
+          ninfo("IPv4 frame\n");
 
           /* Handle ARP on input then give the IPv4 packet to the network
            * layer
@@ -725,7 +725,7 @@ static void ftmac100_receive(FAR struct ftmac100_driver_s *priv)
 #ifdef CONFIG_NET_IPv6
       if (BUF->type == HTONS(ETHTYPE_IP6))
         {
-          nllinfo("Iv6 frame\n");
+          ninfo("Iv6 frame\n");
 
           /* Give the IPv6 packet to the network layer */
 
diff --git a/drivers/net/loopback.c b/drivers/net/loopback.c
index 5a519486152..f0aa532a016 100644
--- a/drivers/net/loopback.c
+++ b/drivers/net/loopback.c
@@ -187,7 +187,7 @@ static int lo_txpoll(FAR struct net_driver_s *dev)
 #ifdef CONFIG_NET_IPv4
       if ((IPv4BUF->vhl & IP_VERSION_MASK) == IPv4_VERSION)
         {
-          nllinfo("IPv4 frame\n");
+          ninfo("IPv4 frame\n");
           NETDEV_RXIPV4(&priv->lo_dev);
           ipv4_input(&priv->lo_dev);
         }
@@ -196,7 +196,7 @@ static int lo_txpoll(FAR struct net_driver_s *dev)
 #ifdef CONFIG_NET_IPv6
       if ((IPv6BUF->vtc & IP_VERSION_MASK) == IPv6_VERSION)
         {
-          nllinfo("Iv6 frame\n");
+          ninfo("Iv6 frame\n");
           NETDEV_RXIPV6(&priv->lo_dev);
           ipv6_input(&priv->lo_dev);
         }
diff --git a/drivers/net/phy_notify.c b/drivers/net/phy_notify.c
index 96b6109b67b..5f202f9ae93 100644
--- a/drivers/net/phy_notify.c
+++ b/drivers/net/phy_notify.c
@@ -83,14 +83,10 @@
 
 #ifdef CONFIG_NETDEV_PHY_DEBUG
 #  define phyinfo   _info
-#  define phyllinfo _llinfo
 #  define phyerr    _err
-#  define phyllerr  _llerr
 #else
 #  define phyinfo(x...)
-#  define phyllinfo(x...)
 #  define phyerr(x...)
-#  define phyllerr(x...)
 #endif
 
 /****************************************************************************
@@ -270,8 +266,8 @@ static int phy_handler(FAR struct phy_notify_s *client)
   int ret;
 
   DEBUGASSERT(client && client->assigned && client->enable);
-  phyllinfo("Entry client %d, signalling PID=%d with signal %d\n",
-            client->index, client->pid, client->signo);
+  phyinfo("Entry client %d, signalling PID=%d with signal %d\n",
+          client->index, client->pid, client->signo);
 
   /* Disable further interrupts */
 
@@ -291,7 +287,7 @@ static int phy_handler(FAR struct phy_notify_s *client)
       int errcode = errno;
       DEBUGASSERT(errcode > 0);
 
-      nllinfo("ERROR: sigqueue failed: %d\n", errcode);
+      nerr("ERROR: sigqueue failed: %d\n", errcode);
       UNUSED(errcode);
     }
 
diff --git a/drivers/net/skeleton.c b/drivers/net/skeleton.c
index ca3ea335dd8..82568cb0915 100644
--- a/drivers/net/skeleton.c
+++ b/drivers/net/skeleton.c
@@ -334,7 +334,7 @@ static void skel_receive(FAR struct skel_driver_s *priv)
 #ifdef CONFIG_NET_IPv4
       if (BUF->type == HTONS(ETHTYPE_IP))
         {
-          nllinfo("IPv4 frame\n");
+          ninfo("IPv4 frame\n");
           NETDEV_RXIPV4(&priv->sk_dev);
 
           /* Handle ARP on input then give the IPv4 packet to the network
@@ -375,7 +375,7 @@ static void skel_receive(FAR struct skel_driver_s *priv)
 #ifdef CONFIG_NET_IPv6
       if (BUF->type == HTONS(ETHTYPE_IP6))
         {
-          nllinfo("Iv6 frame\n");
+          ninfo("Iv6 frame\n");
           NETDEV_RXIPV6(&priv->sk_dev);
 
           /* Give the IPv6 packet to the network layer */
diff --git a/drivers/net/telnet.c b/drivers/net/telnet.c
index e2a5dd270a6..374af780cab 100644
--- a/drivers/net/telnet.c
+++ b/drivers/net/telnet.c
@@ -277,12 +277,12 @@ static ssize_t telnet_receive(FAR struct telnet_dev_s *priv, FAR const char *src
   int nread;
   uint8_t ch;
 
-  nllinfo("srclen: %d destlen: %d\n", srclen, destlen);
+  ninfo("srclen: %d destlen: %d\n", srclen, destlen);
 
   for (nread = 0; srclen > 0 && nread < destlen; srclen--)
     {
       ch = *src++;
-      nllinfo("ch=%02x state=%d\n", ch, priv->td_state);
+      ninfo("ch=%02x state=%d\n", ch, priv->td_state);
 
       switch (priv->td_state)
         {
@@ -447,7 +447,7 @@ static void telnet_sendopt(FAR struct telnet_dev_s *priv, uint8_t option,
   telnet_dumpbuffer("Send optbuf", optbuf, 4);
   if (psock_send(&priv->td_psock, optbuf, 4, 0) < 0)
     {
-      nllerr("ERROR: Failed to send TELNET_IAC\n");
+      nerr("ERROR: Failed to send TELNET_IAC\n");
     }
 }
 
@@ -462,7 +462,7 @@ static int telnet_open(FAR struct file *filep)
   int tmp;
   int ret;
 
-  nllinfo("td_crefs: %d\n", priv->td_crefs);
+  ninfo("td_crefs: %d\n", priv->td_crefs);
 
   /* O_NONBLOCK is not supported */
 
@@ -518,7 +518,7 @@ static int telnet_close(FAR struct file *filep)
   FAR char *devpath;
   int ret;
 
-  nllinfo("td_crefs: %d\n", priv->td_crefs);
+  ninfo("td_crefs: %d\n", priv->td_crefs);
 
   /* Get exclusive access to the device structures */
 
@@ -548,7 +548,7 @@ static int telnet_close(FAR struct file *filep)
       ret = asprintf(&devpath, TELNETD_DEVFMT, priv->td_minor);
       if (ret < 0)
         {
-          nllerr("ERROR: Failed to allocate the driver path\n");
+          nerr("ERROR: Failed to allocate the driver path\n");
         }
       else
         {
@@ -566,8 +566,8 @@ static int telnet_close(FAR struct file *filep)
 
               if (ret != -EBUSY)
                 {
-                  nllerr("ERROR: Failed to unregister the driver %s: %d\n",
-                         devpath, ret);
+                  nerr("ERROR: Failed to unregister the driver %s: %d\n",
+                       devpath, ret);
                 }
             }
 
@@ -608,7 +608,7 @@ static ssize_t telnet_read(FAR struct file *filep, FAR char *buffer, size_t len)
   FAR struct telnet_dev_s *priv = inode->i_private;
   ssize_t ret;
 
-  nllinfo("len: %d\n", len);
+  ninfo("len: %d\n", len);
 
   /* First, handle the case where there are still valid bytes left in the
    * I/O buffer from the last time that read was called.  NOTE:  Much of
@@ -681,7 +681,7 @@ static ssize_t telnet_write(FAR struct file *filep, FAR const char *buffer, size
   char ch;
   bool eol;
 
-  nllinfo("len: %d\n", len);
+  ninfo("len: %d\n", len);
 
   /* Process each character from the user buffer */
 
@@ -706,7 +706,7 @@ static ssize_t telnet_write(FAR struct file *filep, FAR const char *buffer, size
           ret = psock_send(&priv->td_psock, priv->td_txbuffer, ncopied, 0);
           if (ret < 0)
             {
-              nllerr("ERROR: psock_send failed '%s': %d\n", priv->td_txbuffer, ret);
+              nerr("ERROR: psock_send failed '%s': %d\n", priv->td_txbuffer, ret);
               return ret;
             }
 
@@ -723,7 +723,7 @@ static ssize_t telnet_write(FAR struct file *filep, FAR const char *buffer, size
       ret = psock_send(&priv->td_psock, priv->td_txbuffer, ncopied, 0);
       if (ret < 0)
         {
-          nllerr("ERROR: psock_send failed '%s': %d\n", priv->td_txbuffer, ret);
+          nerr("ERROR: psock_send failed '%s': %d\n", priv->td_txbuffer, ret);
           return ret;
         }
     }
@@ -767,7 +767,7 @@ static int telnet_session(FAR struct telnet_session_s *session)
   priv = (FAR struct telnet_dev_s*)malloc(sizeof(struct telnet_dev_s));
   if (!priv)
     {
-      nllerr("ERROR: Failed to allocate the driver data structure\n");
+      nerr("ERROR: Failed to allocate the driver data structure\n");
       return -ENOMEM;
     }
 
@@ -788,7 +788,7 @@ static int telnet_session(FAR struct telnet_session_s *session)
   psock = sockfd_socket(session->ts_sd);
   if (!psock)
     {
-      nllerr("ERROR: Failed to convert sd=%d to a socket structure\n", session->ts_sd);
+      nerr("ERROR: Failed to convert sd=%d to a socket structure\n", session->ts_sd);
       ret = -EINVAL;
       goto errout_with_dev;
     }
@@ -796,7 +796,7 @@ static int telnet_session(FAR struct telnet_session_s *session)
   ret = net_clone(psock, &priv->td_psock);
   if (ret < 0)
     {
-      nllerr("ERROR: net_clone failed: %d\n", ret);
+      nerr("ERROR: net_clone failed: %d\n", ret);
       goto errout_with_dev;
     }
 
@@ -834,7 +834,7 @@ static int telnet_session(FAR struct telnet_session_s *session)
 
   if (ret >= 0)
     {
-      nllerr("ERROR: Too many sessions\n");
+      nerr("ERROR: Too many sessions\n");
       ret = -ENFILE;
       goto errout_with_semaphore;
     }
@@ -844,8 +844,8 @@ static int telnet_session(FAR struct telnet_session_s *session)
   ret = register_driver(session->ts_devpath, &g_telnet_fops, 0666, priv);
   if (ret < 0)
     {
-      nllerr("ERROR: Failed to register the driver %s: %d\n",
-             session->ts_devpath, ret);
+      nerr("ERROR: Failed to register the driver %s: %d\n",
+           session->ts_devpath, ret);
       goto errout_with_semaphore;
     }
 
diff --git a/drivers/net/tun.c b/drivers/net/tun.c
index 965fcd97e55..37c199d167b 100644
--- a/drivers/net/tun.c
+++ b/drivers/net/tun.c
@@ -425,7 +425,7 @@ static void tun_receive(FAR struct tun_device_s *priv)
   /* We only accept IP packets of the configured type and ARP packets */
 
 #if defined(CONFIG_NET_IPv4)
-  nllinfo("IPv4 frame\n");
+  ninfo("IPv4 frame\n");
   NETDEV_RXIPV4(&priv->dev);
 
   /* Give the IPv4 packet to the network layer */
@@ -448,7 +448,7 @@ static void tun_receive(FAR struct tun_device_s *priv)
     }
 
 #elif defined(CONFIG_NET_IPv6)
-  nllinfo("Iv6 frame\n");
+  ninfo("Iv6 frame\n");
   NETDEV_RXIPV6(&priv->dev);
 
   /* Give the IPv6 packet to the network layer */
diff --git a/drivers/net/vnet.c b/drivers/net/vnet.c
index 7da2e9f3c4e..8f6f14afb29 100644
--- a/drivers/net/vnet.c
+++ b/drivers/net/vnet.c
@@ -332,7 +332,7 @@ void rtos_vnet_recv(struct rgmp_vnet *rgmp_vnet, char *data, int len)
 #ifdef CONFIG_NET_IPv4
       if (BUF->type == HTONS(ETHTYPE_IP))
         {
-          nllinfo("IPv4 frame\n");
+          ninfo("IPv4 frame\n");
 
           /* Handle ARP on input then give the IPv4 packet to the network
            * layer
@@ -372,7 +372,7 @@ void rtos_vnet_recv(struct rgmp_vnet *rgmp_vnet, char *data, int len)
 #ifdef CONFIG_NET_IPv6
       if (BUF->type == HTONS(ETHTYPE_IP6))
         {
-          nllinfo("Iv6 frame\n");
+          ninfo("Iv6 frame\n");
 
           /* Give the IPv6 packet to the network layer */
 
diff --git a/drivers/pipes/pipe_common.c b/drivers/pipes/pipe_common.c
index 21fe124f16f..759b7e474bc 100644
--- a/drivers/pipes/pipe_common.c
+++ b/drivers/pipes/pipe_common.c
@@ -521,7 +521,7 @@ ssize_t pipecommon_write(FAR struct file *filep, FAR const char *buffer,
    * be called from interrupt level.  This actually happens fairly commonly
    * IF [a-z]err() is called from interrupt handlers and stdout is being redirected
    * via a pipe.  In that case, the debug output will try to go out the pipe
-   * (interrupt handlers should use the  _llerr() APIs).
+   * (interrupt handlers should use the  _err() APIs).
    *
    * On the other hand, it would be very valuable to be able to feed the pipe
    * from an interrupt handler!  TODO:  Consider disabling interrupts instead
diff --git a/drivers/pwm.c b/drivers/pwm.c
index 6a215538d62..7fb6b3436f5 100644
--- a/drivers/pwm.c
+++ b/drivers/pwm.c
@@ -652,7 +652,7 @@ void pwm_expired(FAR void *handle)
 {
   FAR struct pwm_upperhalf_s *upper = (FAR struct pwm_upperhalf_s *)handle;
 
-  pwmllinfo("started: %d waiting: %d\n", upper->started, upper->waiting);
+  pwminfo("started: %d waiting: %d\n", upper->started, upper->waiting);
 
   /* Make sure that the PWM is started */
 
diff --git a/drivers/sensors/adxl345_base.c b/drivers/sensors/adxl345_base.c
index 56375b466b8..8a92d059eb6 100644
--- a/drivers/sensors/adxl345_base.c
+++ b/drivers/sensors/adxl345_base.c
@@ -305,7 +305,7 @@ static void adxl345_interrupt(FAR struct adxl345_config_s *config, FAR void *arg
       ret = work_queue(HPWORK, &priv->work, adxl345_worker, priv, 0);
       if (ret != 0)
         {
-          snllerr("ERROR: Failed to queue work: %d\n", ret);
+          snerr("ERROR: Failed to queue work: %d\n", ret);
         }
     }
 
diff --git a/drivers/sensors/zerocross.c b/drivers/sensors/zerocross.c
index 8ac76652752..d7bc19e381a 100644
--- a/drivers/sensors/zerocross.c
+++ b/drivers/sensors/zerocross.c
@@ -244,7 +244,7 @@ static int zc_open(FAR struct file *filep)
   ret = sem_wait(&priv->exclsem);
   if (ret < 0)
     {
-      sninfo("ERROR: sem_wait failed: %d\n", ret);
+      snerr("ERROR: sem_wait failed: %d\n", ret);
       return ret;
     }
 
@@ -253,7 +253,7 @@ static int zc_open(FAR struct file *filep)
   opriv = (FAR struct zc_open_s *)kmm_zalloc(sizeof(struct zc_open_s));
   if (!opriv)
     {
-      sninfo("ERROR: Failled to allocate open structure\n");
+      snerr("ERROR: Failled to allocate open structure\n");
       ret = -ENOMEM;
       goto errout_with_sem;
     }
@@ -325,7 +325,7 @@ static int zc_close(FAR struct file *filep)
   ret = sem_wait(&priv->exclsem);
   if (ret < 0)
     {
-      sninfo("ERROR: sem_wait failed: %d\n", ret);
+      snerr("ERROR: sem_wait failed: %d\n", ret);
       return ret;
     }
 
@@ -338,7 +338,7 @@ static int zc_close(FAR struct file *filep)
   DEBUGASSERT(curr);
   if (!curr)
     {
-      sninfo("ERROR: Failed to find open entry\n");
+      snerr("ERROR: Failed to find open entry\n");
       ret = -ENOENT;
       goto errout_with_exclsem;
     }
@@ -516,7 +516,7 @@ int zc_register(FAR const char *devname, FAR struct zc_lowerhalf_s *lower)
 
   if (!priv)
     {
-      sninfo("ERROR: Failed to allocate device structure\n");
+      snerr("ERROR: Failed to allocate device structure\n");
       return -ENOMEM;
     }
 
@@ -535,7 +535,7 @@ int zc_register(FAR const char *devname, FAR struct zc_lowerhalf_s *lower)
   ret = register_driver(devname, &g_zcops, 0666, priv);
   if (ret < 0)
     {
-      sninfo("ERROR: register_driver failed: %d\n", ret);
+      snerr("ERROR: register_driver failed: %d\n", ret);
       sem_destroy(&priv->exclsem);
       kmm_free(priv);
     }
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index d5435539f76..5297a824f80 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -13,6 +13,11 @@ config DEV_LOWCONSOLE
 
 config SERIAL_REMOVABLE
 	bool
+	default n
+
+config SERIAL_CONSOLE
+	bool
+	default n
 
 config 16550_UART
 	bool "16550 UART Chip support"
@@ -292,18 +297,22 @@ choice
 config 16550_UART0_SERIAL_CONSOLE
 	bool "16550 UART0 serial console"
 	depends on 16550_UART0
+	select SERIAL_CONSOLE
 
 config 16550_UART1_SERIAL_CONSOLE
 	bool "16550 UART1 serial console"
 	depends on 16550_UART1
+	select SERIAL_CONSOLE
 
 config 16550_UART2_SERIAL_CONSOLE
 	bool "16550 UART2 serial console"
 	depends on 16550_UART2
+	select SERIAL_CONSOLE
 
 config 16550_UART3_SERIAL_CONSOLE
 	bool "16550 UART3 serial console"
 	depends on 16550_UART3
+	select SERIAL_CONSOLE
 
 config 16550_NO_SERIAL_CONSOLE
 	bool "No 16550 serial console"
@@ -566,89 +575,111 @@ choice
 config UART_SERIAL_CONSOLE
 	bool "UART"
 	depends on UART_SERIALDRIVER
+	select SERIAL_CONSOLE
 
 config UART0_SERIAL_CONSOLE
 	bool "UART0"
 	depends on UART0_SERIALDRIVER
+	select SERIAL_CONSOLE
 
 config USART0_SERIAL_CONSOLE
 	bool "USART0"
 	depends on USART0_SERIALDRIVER
+	select SERIAL_CONSOLE
 
 config UART1_SERIAL_CONSOLE
 	bool "UART1"
 	depends on UART1_SERIALDRIVER
+	select SERIAL_CONSOLE
 
 config USART1_SERIAL_CONSOLE
 	bool "USART1"
 	depends on USART1_SERIALDRIVER
+	select SERIAL_CONSOLE
 
 config UART2_SERIAL_CONSOLE
 	bool "UART2"
 	depends on UART2_SERIALDRIVER
+	select SERIAL_CONSOLE
 
 config USART2_SERIAL_CONSOLE
 	bool "USART2"
 	depends on USART2_SERIALDRIVER
+	select SERIAL_CONSOLE
 
 config UART3_SERIAL_CONSOLE
 	bool "UART3"
 	depends on UART3_SERIALDRIVER
+	select SERIAL_CONSOLE
 
 config USART3_SERIAL_CONSOLE
 	bool "USART3"
 	depends on USART3_SERIALDRIVER
+	select SERIAL_CONSOLE
 
 config UART4_SERIAL_CONSOLE
 	bool "UART4"
 	depends on UART4_SERIALDRIVER
+	select SERIAL_CONSOLE
 
 config USART4_SERIAL_CONSOLE
 	bool "USART4"
 	depends on USART4_SERIALDRIVER
+	select SERIAL_CONSOLE
 
 config UART5_SERIAL_CONSOLE
 	bool "UART5"
 	depends on UART5_SERIALDRIVER
+	select SERIAL_CONSOLE
 
 config USART5_SERIAL_CONSOLE
 	bool "USART5"
 	depends on USART5_SERIALDRIVER
+	select SERIAL_CONSOLE
 
 config UART6_SERIAL_CONSOLE
 	bool "UART6"
 	depends on UART6_SERIALDRIVER
+	select SERIAL_CONSOLE
 
 config USART6_SERIAL_CONSOLE
 	bool "USART6"
 	depends on USART6_SERIALDRIVER
+	select SERIAL_CONSOLE
 
 config UART7_SERIAL_CONSOLE
 	bool "UART7"
 	depends on UART7_SERIALDRIVER
+	select SERIAL_CONSOLE
 
 config USART7_SERIAL_CONSOLE
 	bool "USART7"
 	depends on USART7_SERIALDRIVER
+	select SERIAL_CONSOLE
 
 config UART8_SERIAL_CONSOLE
 	bool "UART8"
 	depends on UART8_SERIALDRIVER
+	select SERIAL_CONSOLE
 
 config USART8_SERIAL_CONSOLE
 	bool "USART8"
 	depends on USART8_SERIALDRIVER
+	select SERIAL_CONSOLE
 
 config SCI0_SERIAL_CONSOLE
 	bool "SCI0"
 	depends on SCI0_SERIALDRIVER
+	select SERIAL_CONSOLE
 
 config SCI1_SERIAL_CONSOLE
 	bool "SCI1"
 	depends on SCI1_SERIALDRIVER
+	select SERIAL_CONSOLE
 
 config OTHER_SERIAL_CONSOLE
 	bool "Other serial console"
+	select SERIAL_CONSOLE
 
 config NO_SERIAL_CONSOLE
 	bool "No serial console"
diff --git a/drivers/syslog/Kconfig b/drivers/syslog/Kconfig
index d273e3d1a3a..f3ab33f9eb8 100644
--- a/drivers/syslog/Kconfig
+++ b/drivers/syslog/Kconfig
@@ -3,7 +3,13 @@
 # see the file kconfig-language.txt in the NuttX tools repository.
 #
 
-comment "System Logging"
+menu "System Logging"
+
+# Selected if the architecture has its own, built-in SYSLOGging enabled
+
+config ARCH_SYSLOG
+	bool
+	default n
 
 config RAMLOG
 	bool "RAM log device support"
@@ -20,18 +26,6 @@ config RAMLOG
 		details as needed to support logging.
 
 if RAMLOG
-config RAMLOG_SYSLOG
-	bool "Use RAMLOG for SYSLOG"
-	default n
-	depends on SYSLOG
-	---help---
-		Use the RAM logging device for the syslogging interface.  If this feature
-		is enabled (along with SYSLOG), then all debug output (only) will be re-directed
-		to the circular buffer in RAM.  This RAM log can be view from NSH using the
-		'dmesg'command.
-
-		Do not enable more than one SYSLOG device.
-
 config RAMLOG_CONSOLE
 	bool "Use RAMLOG for /dev/console"
 	default n
@@ -72,21 +66,109 @@ config RAMLOG_NPOLLWAITERS
 
 endif
 
-config SYSLOG_CONSOLE
-	bool "Use SYSLOG for /dev/console"
-	default n
-	depends on DEV_CONSOLE
-	---help---
-		Use the syslog logging device as a system console. If this feature is enabled 
-		(along with DEV_CONSOLE), then all console output will be re-directed to syslog
-		output (syslog_putc). This is useful, for example, if the only console is a Telnet
-		console.  Then in that case, console output from non-Telnet threads will go to
-		the syslog output.
-
 config DRIVER_NOTE
 	bool "Scheduler instrumentation driver"
 	default n
 	depends on SCHED_INSTRUMENTATION_BUFFER
 	---help---
-		Enable building a serial driver that can be used by an application to read data
-		from the in-memory, scheduler instrumentatin "note" buffer.
+		Enable building a serial driver that can be used by an application
+		to read data from the in-memory, scheduler instrumentatin "note"
+		buffer.
+
+config SYSLOG_INTBUFFER
+	bool "Use interrupt buffer"
+	default n
+	---help---
+		Enables an interrupt buffer that will be used to serialize debug
+		output from interrupt handlers.
+
+config SYSLOG_INTBUFSIZE
+	int "Interrupt buffer size"
+	default 512
+	depends on SYSLOG_INTBUFFER
+	---help---
+		The size of the interrupt buffer in bytes.
+
+config SYSLOG_TIMESTAMP
+	bool "Prepend timestamp to syslog message"
+	default n
+	---help---
+		Prepend timestamp to syslog message.
+
+config SYSLOG_SERIAL_CONSOLE
+	bool
+	default n
+
+choice
+	prompt "System log device"
+	default SYSLOG_CONSOLE if DEV_CONSOLE
+	default SYSLOG_NONE if !DEV_CONSOLE
+	depends on !ARCH_SYSLOG
+
+config SYSLOG_CHAR
+	bool "Log to a character device"
+	---help---
+		Enable the generic character device for the SYSLOG. The full path to the
+		SYSLOG device is provided by SYSLOG_DEVPATH. A valid character device (or
+		file) must exist at this path.  It will by opened by syslog_initialize.
+
+config RAMLOG_SYSLOG
+	bool "Use RAMLOG for SYSLOG"
+	depends on RAMLOG && !ARCH_SYSLOG
+	---help---
+		Use the RAM logging device for the syslogging interface.  If this
+		feature is enabled (along with SYSLOG), then all debug output (only)
+		will be re-directed to the circular buffer in RAM.  This RAM log can
+		be viewed from NSH using the 'dmesg'command.
+
+config SYSLOG_CONSOLE
+	bool "Log to /dev/console"
+	depends on DEV_CONSOLE
+	select SYSLOG_SERIAL_CONSOLE if SERIAL_CONSOLE
+	---help---
+		Use the system console as a SYSLOG output device.
+
+config SYSLOG_NONE
+	bool "No SYSLOG device"
+	---help---
+		syslog() interfaces will be present, but all output will go to the
+		bit-bucket.
+
+endchoice
+
+config SYSLOG_FILE
+	bool "Sylog file output"
+	default n
+	---help---
+		Build in support to use a file to collect SYSOG output.  File SYSLOG
+		channels differ from other SYSLOG channels in that they cannot be
+		established until after fully booting and mounting the target file
+		system.  The function syslog_file_channel() would need to be called
+		from board-specific bring-up logic AFTER mounting the file system
+		containing 'devpath'.
+
+		NOTE interrupt level SYSLOG output will be lost in this case unless
+		the interrupt buffer is used.
+
+config CONSOLE_SYSLOG
+	bool "Use SYSLOG for /dev/console"
+	default n
+	depends on DEV_CONSOLE && !SYSLOG_CONSOLE
+	---help---
+		Use the syslog logging device as a system console. If this feature is
+		enabled (along with DEV_CONSOLE), then all console output will be
+		re-directed to syslog output (syslog_putc). This is useful, for
+		example, if the only console is a Telnet console.  Then in that case,
+		console output from non-Telnet threads will go to the syslog output.
+
+config SYSLOG_DEVPATH
+	string "System log device"
+	default "/dev/syslog"
+	depends on SYSLOG_CHAR
+	---help---
+		The full path to the system logging device.  For the RAMLOG SYSLOG device,
+		this is normally "/dev/ramlog".  For character SYSLOG devices, it should be
+		some other existing character device (or file) supported by the configuration
+		(such as "/dev/ttyS1")/
+
+endmenu # System logging
diff --git a/drivers/syslog/Make.defs b/drivers/syslog/Make.defs
index f573217d6de..95583059e16 100644
--- a/drivers/syslog/Make.defs
+++ b/drivers/syslog/Make.defs
@@ -2,7 +2,7 @@
 # drivers/syslog/Make.defs
 # These drivers support system logging devices
 #
-#   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+#   Copyright (C) 2012, 2016 Gregory Nutt. All rights reserved.
 #   Author: Gregory Nutt <gnutt@nuttx.org>
 #
 # Redistribution and use in source and binary forms, with or without
@@ -35,60 +35,60 @@
 ############################################################################
 
 ############################################################################
-# Include SYSLOG drivers (only one should be enabled)
+# Include SYSLOG Infrastructure
 
-ifeq ($(CONFIG_SYSLOG),y)
+CSRCS += vsyslog.c syslog_stream.c syslog_emergstream.c syslog_channel.c
+CSRCS += syslog_putc.c syslog_force.c syslog_flush.c
 
-# If no special loggin devices are implemented, then the default SYSLOG
-# logic at fs/fs_syslog.c will be used
+ifeq ($(CONFIG_SYSLOG_INTBUFFER),y)
+  CSRCS += syslog_intbuffer.c
+endif
 
-# (Add other SYSLOG drivers here)
+ifneq ($(CONFIG_ARCH_SYSLOG),y)
+  CSRCS += syslog_initialize.c
+endif
+
+# The note driver is hosted in this directory, but is not associated with
+# SYSLOGging
+
+ifeq ($(CONFIG_DRIVER_NOTE),y)
+  CSRCS += note_driver.c
+endif
+
+# The RAMLOG device is usable as a system logging device or standalone
 
 ifeq ($(CONFIG_RAMLOG),y)
   CSRCS += ramlog.c
 endif
 
-ifeq ($(CONFIG_DRIVER_NOTE),y)
-  CSRCS += note_driver.c
-endif
+############################################################################
+# Include SYSLOG drivers (only one should be enabled)
 
-# (Add other SYSLOG_CONSOLE drivers here)
+# System logging to a character device (or file)
+
+CSRCS += syslog_device.c
+
+ifeq ($(CONFIG_SYSLOG_CHAR),y)
+CSRCS += syslog_devchannel.c
+endif
 
 ifeq ($(CONFIG_SYSLOG_CONSOLE),y)
+CSRCS += syslog_consolechannel.c
+endif
+
+ifeq ($(CONFIG_SYSLOG_FILE),y)
+CSRCS += syslog_filechannel.c
+endif
+
+# (Add other SYSLOG drivers here)
+
+ifeq ($(CONFIG_CONSOLE_SYSLOG),y)
   CSRCS += syslog_console.c
 endif
 
+# (Add other SYSLOG drivers here)
+
 # Include SYSLOG build support
 
 DEPPATH += --dep-path syslog
 VPATH += :syslog
-
-############################################################################
-# The RAMLOG can be used even if system logging is not enabled.
-
-else ifeq ($(CONFIG_RAMLOG),y)
-
-CSRCS += ramlog.c
-
-ifeq ($(CONFIG_DRIVER_NOTE),y)
-  CSRCS += note_driver.c
-endif
-
-# Include RAMLOG build support
-
-DEPPATH += --dep-path syslog
-VPATH += :syslog
-
-############################################################################
-# The scheduler note driver can be used in any event.
-
-else ifeq ($(CONFIG_DRIVER_NOTE),y)
-
-CSRCS += note_driver.c
-
-# Include note driver build support
-
-DEPPATH += --dep-path syslog
-VPATH += :syslog
-
-endif
diff --git a/drivers/syslog/README.txt b/drivers/syslog/README.txt
index 2d0445992e2..479251a00bb 100644
--- a/drivers/syslog/README.txt
+++ b/drivers/syslog/README.txt
@@ -7,10 +7,10 @@ header file include/syslog.h.  In NuttX, "syslog output" is really
 synonymous to "debug output" and, therefore, the debugging interfaces
 defined in the header file include/debug.h are also sysloggin interfaces.
 
-By default, all system log output goes to console (/dev/console).  But that
-behavior can be changed by the defining CONFIG_SYSLOG in the NuttX
-configuration.  In that, case all low-level debug output will go through
-syslog_putc().
+All SYSLOG output gots to syslog_putc.  What syslog_putc does, however,
+depends on the configuration.  By default, all system log output will go
+to the console device (/dev/console).  But that behavior can be changed
+reconfiguring NuttX.
 
 One version of syslog_putc() is defined in fs/fs_syslog.c; that version is
 used when CONFIG_SYSLOG_CHAR is defined.  That version of syslog_putc()
@@ -60,12 +60,11 @@ ramlog.c
       in that case, console output from non-Telnet threads will go to the
       circular buffer and can be viewed using the NSH 'dmesg' command.
     CONFIG_RAMLOG_SYSLOG - Use the RAM logging device for the syslogging
-      interface.  If this feature is enabled (along with CONFIG_SYSLOG),
-      then all debug output (only) will be re-directed to the circular
-      buffer in RAM.  This RAM log can be view from NSH using the 'dmesg'
-      command.  NOTE:  Unlike the limited, generic character driver SYSLOG
-      device, the RAMLOG *can* be used to generate debug output from interrupt
-      level handlers.
+      interface.  If this feature is enabled then all debug output (only)
+      will be re-directed to the circular buffer in RAM.  This RAM log can
+      be view from NSH using the 'dmesg' command.  NOTE:  Unlike the
+      limited, generic character driver SYSLOG device, the RAMLOG *can*
+      be used to generate debug output from interrupt level handlers.
     CONFIG_RAMLOG_NPOLLWAITERS - The number of threads than can be waiting
       for this driver on poll().  Default: 4
 
diff --git a/drivers/syslog/ramlog.c b/drivers/syslog/ramlog.c
index ad62e935f15..6044b7157b5 100644
--- a/drivers/syslog/ramlog.c
+++ b/drivers/syslog/ramlog.c
@@ -63,10 +63,6 @@
 
 #ifdef CONFIG_RAMLOG
 
-/****************************************************************************
- * Private Types
- ****************************************************************************/
-
 /****************************************************************************
  * Private Types
  ****************************************************************************/
@@ -98,6 +94,13 @@ struct ramlog_dev_s
 /****************************************************************************
  * Private Function Prototypes
  ****************************************************************************/
+
+/* Syslog channel methods */
+
+#ifdef CONFIG_RAMLOG_SYSLOG
+static int ramlog_flush(void);
+#endif
+
 /* Helper functions */
 
 #ifndef CONFIG_DISABLE_POLL
@@ -117,6 +120,19 @@ static int     ramlog_poll(FAR struct file *filep, FAR struct pollfd *fds,
                            bool setup);
 #endif
 
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+#ifdef CONFIG_RAMLOG_SYSLOG
+static const struct syslog_channel_s g_ramlog_syslog_channel =
+{
+  ramlog_putc,
+  ramlog_putc,
+  ramlog_flush
+};
+#endif
+
 /****************************************************************************
  * Private Data
  ****************************************************************************/
@@ -145,7 +161,7 @@ static const struct file_operations g_ramlogfops =
 static char g_sysbuffer[CONFIG_RAMLOG_BUFSIZE];
 
 /* This is the device structure for the console or syslogging function.  It
- * must be statically initialized because the RAMLOG syslog_putc function
+ * must be statically initialized because the RAMLOG ramlog_putc function
  * could be called before the driver initialization logic executes.
  */
 
@@ -169,6 +185,17 @@ static struct ramlog_dev_s g_sysdev =
  * Private Functions
  ****************************************************************************/
 
+/****************************************************************************
+ * Name: ramlog_flush
+ ****************************************************************************/
+
+#ifdef CONFIG_RAMLOG_SYSLOG
+static int ramlog_flush(void)
+{
+  return OK;
+}
+#endif
+
 /****************************************************************************
  * Name: ramlog_pollnotify
  ****************************************************************************/
@@ -704,7 +731,7 @@ int ramlog_consoleinit(void)
 #endif
 
 /****************************************************************************
- * Name: ramlog_sysloginit
+ * Name: ramlog_syslog_channel
  *
  * Description:
  *   Use a pre-allocated RAM logging device and register it at the path
@@ -716,29 +743,34 @@ int ramlog_consoleinit(void)
  ****************************************************************************/
 
 #ifdef CONFIG_RAMLOG_SYSLOG
-int ramlog_sysloginit(void)
+int ramlog_syslog_channel(void)
 {
+  int ret;
+
   /* Register the syslog character driver */
 
-  return register_driver(CONFIG_SYSLOG_DEVPATH, &g_ramlogfops, 0666, &g_sysdev);
+  ret = register_driver(CONFIG_SYSLOG_DEVPATH, &g_ramlogfops, 0666, &g_sysdev);
+  if (ret < 0)
+    {
+      return ret;
+    }
+
+  /* Use the RAMLOG as the SYSLOG channel */
+
+  return syslog_channel(&g_ramlog_syslog_channel);
 }
 #endif
 
 /****************************************************************************
- * Name: syslog_putc
+ * Name: ramlog_putc
  *
  * Description:
- *   This is the low-level system logging interface.  The debugging/syslogging
- *   interfaces are syslog() and lowsyslog().  The difference is that
- *   the syslog() internface writes to syslog device (usually fd=1, stdout)
- *   whereas lowsyslog() uses a lower level interface that works from
- *   interrupt handlers.  This function is a a low-level interface used to
- *   implement lowsyslog() when CONFIG_RAMLOG_SYSLOG=y and CONFIG_SYSLOG=y
+ *   This is the low-level system logging interface.
  *
  ****************************************************************************/
 
 #if defined(CONFIG_RAMLOG_CONSOLE) || defined(CONFIG_RAMLOG_SYSLOG)
-int syslog_putc(int ch)
+int ramlog_putc(int ch)
 {
   FAR struct ramlog_dev_s *priv = &g_sysdev;
   int ret;
diff --git a/drivers/syslog/syslog.h b/drivers/syslog/syslog.h
new file mode 100644
index 00000000000..3ebb480f00a
--- /dev/null
+++ b/drivers/syslog/syslog.h
@@ -0,0 +1,319 @@
+/****************************************************************************
+ * drivers/syslog/syslog.h
+ *
+ *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __DRIVERS_SYSLOG_SYSLOG_H
+#define __DRIVERS_SYSLOG_SYSLOG_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdbool.h>
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/* The default SYSLOG channel */
+
+struct syslog_channel_s; /* Forward reference */
+EXTERN const struct syslog_channel_s g_default_syslog_channel;
+
+/* This is the current syslog channel in use.  It initially points to
+ * g_default_syslog_channel.
+ */
+
+EXTERN FAR const struct syslog_channel_s *g_syslog_channel;
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: syslog_dev_initialize
+ *
+ * Description:
+ *   Initialize to use the character device (or file) at
+ *   CONFIG_SYSLOG_DEVPATH as the SYSLOG sink.
+ *
+ *   One power up, the SYSLOG facility is non-existent or limited to very
+ *   low-level output.  This function may be called later in the
+ *   intialization sequence after full driver support has been initialized.
+ *   (via syslog_initialize())  It installs the configured SYSLOG drivers
+ *   and enables full SYSLOGing capability.
+ *
+ *   NOTE that this implementation excludes using a network connection as
+ *   SYSLOG device.  That would be a good extension.
+ *
+ * Input Parameters:
+ *   devpath - The full path to the character device to be used.
+ *   oflags  - File open flags
+ *   mode    - File open mode (only if oflags include O_CREAT)
+ *
+ * Returned Value:
+ *   Zero (OK) is returned on success; a negated errno value is returned on
+ *   any failure.
+ *
+ ****************************************************************************/
+
+#if CONFIG_NFILE_DESCRIPTORS > 0
+int syslog_dev_initialize(FAR const char *devpath, int oflags, int mode);
+#endif
+
+/****************************************************************************
+ * Name: syslog_dev_uninitialize
+ *
+ * Description:
+ *   Called to disable the last device/file channel in preparation to use
+ *   a different SYSLOG device. Currently only used for CONFIG_SYSLOG_FILE.
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   Zero (OK) is returned on success; a negated errno value is returned on
+ *   any failure.
+ *
+ * Assumptions:
+ *   The caller has already switched the SYSLOG source to some safe channel
+ *   (the default channel).
+ *
+ ****************************************************************************/
+
+#if CONFIG_NFILE_DESCRIPTORS > 0 && defined(CONFIG_SYSLOG_FILE)
+int syslog_dev_uninitialize(void);
+#endif /* CONFIG_SYSLOG_FILE */
+
+/****************************************************************************
+ * Name: syslog_dev_channel
+ *
+ * Description:
+ *   Configure to use the character device (or file) at
+ *   CONFIG_SYSLOG_DEVPATH as the SYSLOG channel.
+ *
+ *   This tiny function is simply a wrapper around syslog_dev_initialize()
+ *   and syslog_channel().  It calls syslog_dev_initialize() to configure
+ *   the character device at CONFIG_SYSLOG_DEVPATH then calls
+ *   syslog_channel() to use that device as the SYSLOG output channel.
+ *
+ *   NOTE interrupt level SYSLOG output will be lost in this case unless
+ *   the interrupt buffer is used.
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   Zero (OK) is returned on success; a negated errno value is returned on
+ *   any failure.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SYSLOG_CHAR
+int syslog_dev_channel(void);
+#endif
+
+/****************************************************************************
+ * Name: syslog_console_channel
+ *
+ * Description:
+ *   Configure to use the character device (or file) at /dev/console as the
+ *   SYSLOG channel.
+ *
+ *   This tiny function is simply a wrapper around syslog_dev_initialize()
+ *   and syslog_channel().  It calls syslog_dev_initialize() to configure
+ *   the character device at /dev/console then calls syslog_channel() to
+ *   use that device as the SYSLOG output channel.
+ *
+ *   NOTE interrupt level SYSLOG output will be lost in the general case
+ *   unless the interrupt buffer is used.  As a special case:  If the serial
+ *   console is used and the architecture provides up_putc(), the interrupt
+ *   level output will be directed to up_putc() is the interrupt buffer is
+ *   disabled.
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   Zero (OK) is returned on success; a negated errno value is returned on
+ *   any failure.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SYSLOG_CONSOLE
+int syslog_console_channel(void);
+#endif
+
+/****************************************************************************
+ * Name: syslog_add_intbuffer
+ *
+ * Description:
+ *   Add one more character to the interrupt buffer.  In the event of
+ *   buffer overlowed, the character will be dropped.  The indication
+ *   "[truncated]\n" will be appended to the end of the interrupt buffer.
+ *
+ * Input Parameters:
+ *   ch - The character to add to the interrupt buffer (must be positive).
+ *
+ * Returned Value:
+ *   Zero success, the character is echoed back to the caller.  A negated
+ *   errno value is returned on any failure.
+ *
+ * Assumptions:
+ *   Called only from interrupt handling logic; Interrupts will be disabled.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SYSLOG_INTBUFFER
+int syslog_add_intbuffer(int ch);
+#endif
+
+/****************************************************************************
+ * Name: syslog_flush_intbuffer
+ *
+ * Description:
+ *   Flush any characters that may have been added to the interrupt buffer
+ *   to the SYSLOG device.
+ *
+ * Input Parameters:
+ *   channel - The syslog channel to use in performing the flush operation.
+ *   force   - Use the force() method of the channel vs. the putc() method.
+ *
+ * Returned Value:
+ *   On success, the character is echoed back to the caller.  A negated
+ *   errno value is returned on any failure.
+ *
+ * Assumptions:
+ *   Interrupts may or may not be disabled.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SYSLOG_INTBUFFER
+int syslog_flush_intbuffer(FAR const struct syslog_channel_s *channel,
+                           bool force);
+#endif
+
+/****************************************************************************
+ * Name: syslog_putc
+ *
+ * Description:
+ *   This is the low-level system logging interface.
+ *
+ * Input Parameters:
+ *   ch - The character to add to the SYSLOG (must be positive).
+ *
+ * Returned Value:
+ *   On success, the character is echoed back to the caller.  A negated
+ *   errno value is returned on any failure.
+ *
+ ****************************************************************************/
+
+int syslog_putc(int ch);
+
+/****************************************************************************
+ * Name: syslog_force
+ *
+ * Description:
+ *   This is the low-level system logging interface.  This version forces
+ *   the output and is only used in emergency situations (e.g., in assertion
+ *   handling).
+ *
+ * Input Parameters:
+ *   ch - The character to add to the SYSLOG (must be positive).
+ *
+ * Returned Value:
+ *   On success, the character is echoed back to the caller.  A negated
+ *   errno value is returned on any failure.
+ *
+ ****************************************************************************/
+
+int syslog_force(int ch);
+
+/****************************************************************************
+ * Name: syslog_dev_putc
+ *
+ * Description:
+ *   This is the low-level system logging interface provided for the
+ *   character driver interface.
+ *
+ * Input Parameters:
+ *   ch - The character to add to the SYSLOG (must be positive).
+ *
+ * Returned Value:
+ *   On success, the character is echoed back to the caller.  A negated
+ *   errno value is returned on any failure.
+ *
+ ****************************************************************************/
+
+#if CONFIG_NFILE_DESCRIPTORS > 0
+int syslog_dev_putc(int ch);
+#endif
+
+/****************************************************************************
+ * Name: syslog_dev_flush
+ *
+ * Description:
+ *   Flush any buffer data in the file system to media.
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   Zero (OK) on success; a negated errno value is returned on any failure.
+ *
+ ****************************************************************************/
+
+#if CONFIG_NFILE_DESCRIPTORS > 0
+int syslog_dev_flush(void);
+#endif
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __DRIVERS_SYSLOG_SYSLOG_H */
diff --git a/drivers/syslog/syslog_channel.c b/drivers/syslog/syslog_channel.c
new file mode 100644
index 00000000000..a36cb6e70f4
--- /dev/null
+++ b/drivers/syslog/syslog_channel.c
@@ -0,0 +1,164 @@
+/****************************************************************************
+ * drivers/syslog/syslog_channel.c
+ *
+ *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+#include <assert.h>
+#include <errno.h>
+
+#include <nuttx/syslog/syslog.h>
+
+#ifdef CONFIG_RAMLOG_SYSLOG
+#  include <nuttx/syslog/ramlog.h>
+#elif defined(CONFIG_ARCH_LOWPUTC)
+#  include <nuttx/arch.h>
+#endif
+
+#include "syslog.h"
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+#if defined(CONFIG_SYSLOG_SERIAL_CONSOLE) && defined(CONFIG_ARCH_LOWPUTC)
+#  define HAVE_LOWPUTC
+#elif !defined(CONFIG_RAMLOG_SYSLOG)
+#  define NEED_LOWPUTC
+#endif
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+#ifdef NEED_LOWPUTC
+static int syslog_default_putc(int ch);
+#endif
+static int syslog_default_flush(void);
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#if defined(CONFIG_RAMLOG_SYSLOG)
+const struct syslog_channel_s g_default_channel =
+{
+  ramlog_putc,
+  ramlog_putc,
+  syslog_default_flush
+};
+#elif defined(HAVE_LOWPUTC)
+const struct syslog_channel_s g_default_channel =
+{
+  up_putc,
+  up_putc,
+  syslog_default_flush
+};
+#else
+const struct syslog_channel_s g_default_channel =
+{
+  syslog_default_putc,
+  syslog_default_putc,
+  syslog_default_flush
+};
+#endif
+
+/* This is the current syslog channel in use */
+
+FAR const struct syslog_channel_s *g_syslog_channel = &g_default_channel;
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: syslog_default_putc and syslog_default_flush
+ *
+ * Description:
+ *   Dummy, no-nothing channel interface methods
+ *
+ ****************************************************************************/
+
+#ifdef NEED_LOWPUTC
+static int syslog_default_putc(int ch)
+{
+  return ch;
+}
+#endif
+
+static int syslog_default_flush(void)
+{
+  return OK;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: syslog_channel
+ *
+ * Description:
+ *   Configure the SYSLOGging function to use the provided channel to
+ *   generate SYSLOG output.
+ *
+ * Input Parameters:
+ *   channel - Provides the interface to the channel to be used.
+ *
+ * Returned Value:
+ *   Zero (OK)is returned on  success.  A negated errno value is returned
+ *   on any failure.
+ *
+ ****************************************************************************/
+
+int syslog_channel(FAR const struct syslog_channel_s *channel)
+{
+  DEBUGASSERT(channel != NULL);
+
+  if (channel != NULL)
+    {
+      DEBUGASSERT(channel->sc_putc != NULL && channel->sc_force != NULL &&
+                  channel->sc_flush != NULL);
+
+      g_syslog_channel = channel;
+      return OK;
+    }
+
+  return -EINVAL;
+}
diff --git a/drivers/syslog/syslog_console.c b/drivers/syslog/syslog_console.c
index a3d3bb2bea3..04a21d2ec91 100644
--- a/drivers/syslog/syslog_console.c
+++ b/drivers/syslog/syslog_console.c
@@ -47,14 +47,6 @@
 #include <nuttx/fs/fs.h>
 #include <nuttx/syslog/syslog.h>
 
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/* The architecture must provide syslog_putc for this driver */
-
-#if defined(CONFIG_SYSLOG)
-
 /****************************************************************************
  * Private Function Prototypes
  ****************************************************************************/
@@ -136,4 +128,3 @@ void syslog_console_init(void)
 {
   (void)register_driver("/dev/console", &g_consoleops, 0666, NULL);
 }
-#endif /* CONFIG_SYSLOG */
diff --git a/drivers/syslog/syslog_consolechannel.c b/drivers/syslog/syslog_consolechannel.c
new file mode 100644
index 00000000000..8ed6374ff65
--- /dev/null
+++ b/drivers/syslog/syslog_consolechannel.c
@@ -0,0 +1,162 @@
+/****************************************************************************
+ * drivers/syslog/syslog_consolechannel.c
+ *
+ *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/stat.h>
+#include <fcntl.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/syslog/syslog.h>
+
+#include "syslog.h"
+
+#ifdef CONFIG_SYSLOG_CONSOLE
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#undef HAVE_LOWPUTC
+#if defined(CONFIG_SYSLOG_SERIAL_CONSOLE) && defined(CONFIG_ARCH_LOWPUTC)
+#  define HAVE_LOWPUTC 1
+#endif
+
+#define OPEN_FLAGS (O_WRONLY)
+#define OPEN_MODE  (S_IROTH | S_IRGRP | S_IRUSR | S_IWUSR)
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/* SYSLOG channel methods */
+
+#ifndef HAVE_LOWPUTC
+static int syslog_console_force(int ch);
+#endif
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/* This structure describes the SYSLOG channel */
+
+static const struct syslog_channel_s g_syslog_console_channel =
+{
+  syslog_dev_putc,
+#ifdef HAVE_LOWPUTC
+  up_putc,
+#else
+  syslog_console_force,
+#endif
+  syslog_dev_flush,
+};
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: syslog_console_force
+ *
+ * Description:
+ *   A dummy FORCE method
+ *
+ ****************************************************************************/
+
+#ifndef HAVE_LOWPUTC
+static int syslog_console_force(int ch)
+{
+  return ch;
+}
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: syslog_console_channel
+ *
+ * Description:
+ *   Configure to use the character device (or file) at /dev/console as the
+ *   SYSLOG channel.
+ *
+ *   This tiny function is simply a wrapper around syslog_dev_initialize()
+ *   and syslog_channel().  It calls syslog_dev_initialize() to configure
+ *   the character device at /dev/console then calls syslog_channel() to
+ *   use that device as the SYSLOG output channel.
+ *
+ *   NOTE interrupt level SYSLOG output will be lost in the general case
+ *   unless the interrupt buffer is used.  As a special case:  If the serial
+ *   console is used and the architecture provides up_putc(), the interrupt
+ *   level output will be directed to up_putc() is the interrupt buffer is
+ *   disabled.
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   Zero (OK) is returned on success; a negated errno value is returned on
+ *   any failure.
+ *
+ ****************************************************************************/
+
+int syslog_console_channel(void)
+{
+  int ret;
+
+  /* Initialize the character driver interface */
+
+  ret = syslog_dev_initialize("/dev/console", OPEN_FLAGS, OPEN_MODE);
+  if (ret < 0)
+    {
+      return ret;
+    }
+
+  /* Use the character driver as the SYSLOG channel */
+
+  return syslog_channel(&g_syslog_console_channel);
+}
+
+#endif /* CONFIG_SYSLOG_CONSOLE */
diff --git a/libc/syslog/lib_lowsyslog.c b/drivers/syslog/syslog_devchannel.c
similarity index 57%
rename from libc/syslog/lib_lowsyslog.c
rename to drivers/syslog/syslog_devchannel.c
index 8c9c84c177a..fc6c439d83a 100644
--- a/libc/syslog/lib_lowsyslog.c
+++ b/drivers/syslog/syslog_devchannel.c
@@ -1,7 +1,7 @@
 /****************************************************************************
- * lib/syslog/lib_lowsyslog.c
+ * drivers/syslog/syslog_devchannel.c
  *
- *   Copyright (C) 2007-2009, 2011-2012 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -39,40 +39,58 @@
 
 #include <nuttx/config.h>
 
-#include <stdio.h>
-#include <syslog.h>
+#include <sys/stat.h>
+#include <fcntl.h>
 
-#include <nuttx/streams.h>
+#include <nuttx/syslog/syslog.h>
 
-#include "syslog/syslog.h"
+#include "syslog.h"
 
-#if defined(CONFIG_ARCH_LOWPUTC) || defined(CONFIG_SYSLOG)
+#ifdef CONFIG_SYSLOG_CHAR
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define OPEN_FLAGS (O_WRONLY)
+#define OPEN_MODE  (S_IROTH | S_IRGRP | S_IRUSR | S_IWUSR)
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/* SYSLOG channel methods */
+
+static int syslog_dev_force(int ch);
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/* This structure describes the SYSLOG channel */
+
+static const struct syslog_channel_s g_syslog_dev_channel =
+{
+  syslog_dev_putc,
+  syslog_dev_force,
+  syslog_dev_flush,
+};
 
 /****************************************************************************
  * Private Functions
  ****************************************************************************/
 
 /****************************************************************************
- * Name: lowvsyslog_internal
+ * Name: syslog_dev_force
  *
  * Description:
- *   This is the internal implementation of lowvsyslog (see the description
- *   of lowsyslog and lowvsyslog below)
+ *   A dummy FORCE method
  *
  ****************************************************************************/
 
-static inline int lowvsyslog_internal(FAR const IPTR char *fmt, va_list ap)
+static int syslog_dev_force(int ch)
 {
-  struct lib_outstream_s stream;
-
-  /* Wrap the stdout in a stream object and let lib_vsprintf do the work. */
-
-#ifdef CONFIG_SYSLOG
-  lib_syslogstream((FAR struct lib_outstream_s *)&stream);
-#else
-  lib_lowoutstream((FAR struct lib_outstream_s *)&stream);
-#endif
-  return lib_vsprintf((FAR struct lib_outstream_s *)&stream, fmt, ap);
+  return ch;
 }
 
 /****************************************************************************
@@ -80,60 +98,44 @@ static inline int lowvsyslog_internal(FAR const IPTR char *fmt, va_list ap)
  ****************************************************************************/
 
 /****************************************************************************
- * Name: lowvsyslog
+ * Name: syslog_dev_channel
  *
  * Description:
- *   The function lowvsyslog() performs the same task as lowsyslog() with
- *   the difference that it takes a set of arguments which have been
- *   obtained using the stdarg variable argument list macros.
+ *   Configure to use the character device at CONFIG_SYSLOG_DEVPATH as the
+ *   SYSLOG channel.
+ *
+ *   This tiny function is simply a wrapper around syslog_dev_initialize()
+ *   and syslog_channel().  It calls syslog_dev_initialize() to configure
+ *   the character device at CONFIG_SYSLOG_DEVPATH then calls
+ *   syslog_channel() to use that device as the SYSLOG output channel.
+ *
+ *   NOTE interrupt level SYSLOG output will be lost in this case unless
+ *   the interrupt buffer is used.
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   Zero (OK) is returned on success; a negated errno value is returned on
+ *   any failure.
  *
  ****************************************************************************/
 
-int lowvsyslog(int priority, FAR const IPTR char *fmt, va_list ap)
+int syslog_dev_channel(void)
 {
-  int ret = 0;
-
-  /* Check if this priority is enabled */
-
-  if ((g_syslog_mask & LOG_MASK(priority)) != 0)
-    {
-      /* Yes.. let vsylog_internal to the deed */
-
-      ret = lowvsyslog_internal(fmt, ap);
-    }
-
-  return ret;
-}
-
-/****************************************************************************
- * Name: lowsyslog
- *
- * Description:
- *   syslog() generates a log message. The priority argument is formed by
- *   ORing the facility and the level values (see include/syslog.h). The
- *   remaining arguments are a format, as in printf and any arguments to the
- *   format.
- *
- *   This is a non-standard, low-level system logging interface.  The
- *   difference between syslog() and lowsyslog() is that the syslog()
- *   interface writes to the syslog device (usually fd=1, stdout) whereas
- *   lowsyslog() uses a lower level interface that works even from interrupt
- *   handlers.
- *
- ****************************************************************************/
-
-int lowsyslog(int priority, FAR const IPTR char *fmt, ...)
-{
-  va_list ap;
   int ret;
 
-  /* Let lowvsyslog do the work */
+  /* Initialize the character driver interface */
 
-  va_start(ap, fmt);
-  ret = lowvsyslog(priority, fmt, ap);
-  va_end(ap);
+  ret = syslog_dev_initialize(CONFIG_SYSLOG_DEVPATH, OPEN_FLAGS, OPEN_MODE);
+  if (ret < 0)
+    {
+      return ret;
+    }
 
-  return ret;
+  /* Use the character driver as the SYSLOG channel */
+
+  return syslog_channel(&g_syslog_dev_channel);
 }
 
-#endif /* CONFIG_ARCH_LOWPUTC || CONFIG_SYSLOG */
+#endif /* CONFIG_SYSLOG_CHAR */
diff --git a/fs/driver/fs_devsyslog.c b/drivers/syslog/syslog_device.c
similarity index 58%
rename from fs/driver/fs_devsyslog.c
rename to drivers/syslog/syslog_device.c
index 84b594077cf..25639e4b50c 100644
--- a/fs/driver/fs_devsyslog.c
+++ b/drivers/syslog/syslog_device.c
@@ -1,7 +1,7 @@
 /****************************************************************************
- * fs/driver/fs_devsyslog.c
+ * driver/syslog/syslog_device.c
  *
- *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2012, 2016 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -44,18 +44,21 @@
 #include <stdint.h>
 #include <stdio.h>
 #include <unistd.h>
+#include <string.h>
+#include <sched.h>
 #include <fcntl.h>
 #include <semaphore.h>
 #include <errno.h>
 #include <assert.h>
 
-#include <nuttx/fs/fs.h>
 #include <nuttx/arch.h>
+#include <nuttx/kmalloc.h>
+#include <nuttx/fs/fs.h>
 #include <nuttx/syslog/syslog.h>
 
-#include "inode/inode.h"
+#include "syslog.h"
 
-#if defined(CONFIG_SYSLOG) && defined(CONFIG_SYSLOG_CHAR)
+#if CONFIG_NFILE_DESCRIPTORS > 0
 
 /****************************************************************************
  * Pre-processor Definitions
@@ -78,7 +81,7 @@
 
 /* This enumeration represents the state of the SYSLOG device interface */
 
-enum syslog_state_e
+enum syslog_dev_state
 {
   SYSLOG_UNINITIALIZED = 0, /* SYSLOG has not been initialized */
   SYSLOG_INITIALIZING,      /* SYSLOG is being initialized */
@@ -91,10 +94,13 @@ enum syslog_state_e
 
 struct syslog_dev_s
 {
-  uint8_t     sl_state;     /* See enum syslog_state_e */
-  sem_t       sl_sem;       /* Enforces mutually exclusive access */
-  pid_t       sl_holder;    /* PID of the thread that holds the semaphore */
-  struct file sl_file;      /* The syslog file structure */
+  uint8_t      sl_state;    /* See enum syslog_dev_state */
+  uint8_t      sl_oflags;   /* Saved open mode (for re-open) */
+  uint16_t     sl_mode;     /* Saved open flags (for re-open) */
+  sem_t        sl_sem;      /* Enforces mutually exclusive access */
+  pid_t        sl_holder;   /* PID of the thread that holds the semaphore */
+  struct file  sl_file;     /* The syslog file structure */
+  FAR char    *sl_devpath;  /* Full path to the character device */
 };
 
 /****************************************************************************
@@ -103,7 +109,7 @@ struct syslog_dev_s
 
 /* This is the device structure for the console or syslogging function. */
 
-static struct syslog_dev_s g_sysdev;
+static struct syslog_dev_s g_syslog_dev;
 static const uint8_t g_syscrlf[2] =
 {
   '\r', '\n'
@@ -114,25 +120,25 @@ static const uint8_t g_syscrlf[2] =
  ****************************************************************************/
 
 /****************************************************************************
- * Name: syslog_takesem
+ * Name: syslog_dev_takesem
  *
  * Description:
  *   Write to the syslog device
  *
  ****************************************************************************/
 
-static inline int syslog_takesem(void)
+static inline int syslog_dev_takesem(void)
 {
   pid_t me = getpid();
   int ret;
 
   /* Does this thread already hold the semaphore?  That could happen if
    * we wer called recursively, i.e., if the logic kicked off by
-   * syslog_write() where to generate more debug output.  Return an error
+   * syslog_dev_write() where to generate more debug output.  Return an error
    * in that case.
    */
 
-  if (g_sysdev.sl_holder == me)
+  if (g_syslog_dev.sl_holder == me)
     {
       /* Return an error (instead of deadlocking) */
 
@@ -143,7 +149,7 @@ static inline int syslog_takesem(void)
    * thread.  Wait for it to become available.
    */
 
-  ret = sem_wait(&g_sysdev.sl_sem);
+  ret = sem_wait(&g_syslog_dev.sl_sem);
   if (ret < 0)
     {
       return -get_errno();
@@ -153,220 +159,238 @@ static inline int syslog_takesem(void)
    * of the semaphore.
    */
 
-  g_sysdev.sl_holder = me;
+  g_syslog_dev.sl_holder = me;
   return OK;
 }
 
 /****************************************************************************
- * Name: syslog_givesem
+ * Name: syslog_dev_givesem
  *
  * Description:
  *   Write to the syslog device
  *
  ****************************************************************************/
 
-static inline void syslog_givesem(void)
+static inline void syslog_dev_givesem(void)
 {
 #ifdef CONFIG_DEBUG_ASSERTIONS
   pid_t me = getpid();
-  DEBUGASSERT(g_sysdev.sl_holder == me);
+  DEBUGASSERT(g_syslog_dev.sl_holder == me);
 #endif
 
   /* Relinquish the semaphore */
 
-  g_sysdev.sl_holder = NO_HOLDER;
-  sem_post(&g_sysdev.sl_sem);
+  g_syslog_dev.sl_holder = NO_HOLDER;
+  sem_post(&g_syslog_dev.sl_sem);
 }
 
 /****************************************************************************
- * Name: syslog_write
+ * Name: syslog_dev_write
  *
  * Description:
  *   Write to the syslog device
  *
  ****************************************************************************/
 
-static inline ssize_t syslog_write(FAR const void *buf, size_t nbytes)
+static inline ssize_t syslog_dev_write(FAR const void *buf, size_t nbytes)
 {
   FAR struct inode *inode;
 
   /* Let the driver perform the write */
 
-  inode = g_sysdev.sl_file.f_inode;
-  return inode->u.i_ops->write(&g_sysdev.sl_file, buf, nbytes);
+  inode = g_syslog_dev.sl_file.f_inode;
+  DEBUGASSERT(inode != NULL);
+
+  return inode->u.i_ops->write(&g_syslog_dev.sl_file, buf, nbytes);
 }
 
-/****************************************************************************
- * Name: syslog_flush
- *
- * Description:
- *   Flush any buffer data in the file system to media.
- *
- ****************************************************************************/
-
-#ifndef CONFIG_DISABLE_MOUNTPOINT
-static inline void syslog_flush(void)
-{
-  FAR struct inode *inode = g_sysdev.sl_file.f_inode;
-
-  /* Is this a mountpoint? Does it support the sync method? */
-
-  if (INODE_IS_MOUNTPT(inode) && inode->u.i_mops->sync)
-    {
-      /* Yes... synchronize to the stream */
-
-      (void)inode->u.i_mops->sync(&g_sysdev.sl_file);
-    }
-}
-#endif
-
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
 
 /****************************************************************************
- * Name: syslog_initialize
+ * Name: syslog_dev_initialize
  *
  * Description:
  *   Initialize to use the character device (or file) at
  *   CONFIG_SYSLOG_DEVPATH as the SYSLOG sink.
  *
+ *   One power up, the SYSLOG facility is non-existent or limited to very
+ *   low-level output.  This function may be called later in the
+ *   intialization sequence after full driver support has been initialized.
+ *   (via syslog_initialize())  It installs the configured SYSLOG drivers
+ *   and enables full SYSLOGing capability.
+ *
  *   NOTE that this implementation excludes using a network connection as
  *   SYSLOG device.  That would be a good extension.
  *
+ * Input Parameters:
+ *   devpath - The full path to the character device to be used.
+ *   oflags  - File open flags
+ *   mode    - File open mode (only if oflags include O_CREAT)
+ *
+ * Returned Value:
+ *   Zero (OK) is returned on success; a negated errno value is returned on
+ *   any failure.
+ *
  ****************************************************************************/
 
-int syslog_initialize(void)
+int syslog_dev_initialize(FAR const char *devpath, int oflags, int mode)
 {
-  FAR struct inode    *inode;
-  FAR const char      *relpath = NULL;
-  int                  ret;
+  int fd;
+  int ret;
 
   /* At this point, the only expected states are SYSLOG_UNINITIALIZED or
    * SYSLOG_REOPEN..  Not SYSLOG_INITIALIZING, SYSLOG_FAILURE, SYSLOG_OPENED.
    */
 
-  DEBUGASSERT(g_sysdev.sl_state == SYSLOG_UNINITIALIZED ||
-              g_sysdev.sl_state == SYSLOG_REOPEN);
+  DEBUGASSERT(g_syslog_dev.sl_state == SYSLOG_UNINITIALIZED ||
+              g_syslog_dev.sl_state == SYSLOG_REOPEN);
 
-  g_sysdev.sl_state = SYSLOG_INITIALIZING;
-
-  /* Try to open the device.
-   *
-   * Note that we cannot just call open.  The syslog device must work on all
-   * threads.  Open returns a file descriptor that is valid only for the
-   * task that opened the device (and its pthread children).  Instead, we
-   * essentially re-implement the guts of open() here so that we can get to
-   * the thread-independent structures of the inode.
+  /* Save the the path to the device in case we have to re-open it.
+   * If we get here and sl_devpath is not equal to NULL, that is a clue
+   * that we will are re-openingthe file.
    */
 
-  /* Get an inode for this file/device */
-
-  inode = inode_find(CONFIG_SYSLOG_DEVPATH, &relpath);
-  if (!inode)
+  if (g_syslog_dev.sl_state == SYSLOG_REOPEN)
     {
-      /* The inode was not found.  In this case, we will attempt to re-open
-       * the device repeatedly.  The assumption is that the device path is
-       * valid but that the driver has not yet been registered.
+      /* Re-opening: Then we should already have a copy of the path to the
+       * device.
        */
 
-      g_sysdev.sl_state = SYSLOG_REOPEN;
-      return -ENOENT;
+      DEBUGASSERT(g_syslog_dev.sl_devpath != NULL &&
+                  strcmp(g_syslog_dev.sl_devpath, devpath) == 0);
+    }
+  else
+    {
+      /* Initializing.  Copy the device path so that we can use it if we
+       * have to re-open the file.
+       */
+
+      DEBUGASSERT(g_syslog_dev.sl_devpath == NULL);
+      g_syslog_dev.sl_oflags  = oflags;
+      g_syslog_dev.sl_mode    = mode;
+      g_syslog_dev.sl_devpath = strdup(devpath);
+      DEBUGASSERT(g_syslog_dev.sl_devpath != NULL);
     }
 
-  /* Verify that the inode is valid and either a character driver or a
-   * mountpoint.
+  g_syslog_dev.sl_state = SYSLOG_INITIALIZING;
+
+  /* Open the device driver. */
+
+  fd = open(devpath, oflags, mode);
+  if (fd < 0)
+    {
+       int errcode = get_errno();
+       DEBUGASSERT(errcode > 0);
+
+      /* We failed to open the file. Perhaps it does exist?  Perhaps it
+       * exists, but is not ready because it depends on insertion of a
+       * removable device?
+       *
+       * In any case we will attempt to re-open the device repeatedly.
+       * The assumption is that the device path is valid but that the
+       * driver has not yet been registered or a removable device has
+       * not yet been installed.
+       */
+
+      g_syslog_dev.sl_state = SYSLOG_REOPEN;
+      return -errcode;
+    }
+
+  /* Detach the file descriptor from the file structure.  The file
+   * descriptor is a task-specific concept.  Detaching the file
+   * descriptor allows us to use the device on all threads in all tasks.
    */
 
-#ifndef CONFIG_DISABLE_MOUNTPOINT
-  if ((!INODE_IS_DRIVER(inode) && !INODE_IS_MOUNTPT(inode)))
-#else
-  if (!INODE_IS_DRIVER(inode))
-#endif
-    {
-      ret = -ENXIO;
-      goto errout_with_inode;
-    }
-
-  /* Make sure that the "entity" at this inode supports write access */
-
-  if (!inode->u.i_ops || !inode->u.i_ops->write)
-    {
-      ret = -EACCES;
-      goto errout_with_inode;
-    }
-
-  /* Initialize the file structure */
-
-  g_sysdev.sl_file.f_oflags = SYSLOG_OFLAGS;
-  g_sysdev.sl_file.f_pos    = 0;
-  g_sysdev.sl_file.f_inode  = inode;
-
-  /* Perform the low-level open operation. */
-
-  ret = OK;
-  if (inode->u.i_ops->open)
-    {
-      /* Is the inode a mountpoint? */
-
-#ifndef CONFIG_DISABLE_MOUNTPOINT
-      if (INODE_IS_MOUNTPT(inode))
-        {
-          /* Yes.  Open the device write-only, try to create it if it
-           * doesn't exist, if the file that already exists, then append the
-           * new log data to end of the file.
-           */
-
-          ret = inode->u.i_mops->open(&g_sysdev.sl_file, relpath,
-                                      SYSLOG_OFLAGS, 0666);
-        }
-
-      /* No... then it must be a character driver in the NuttX pseudo-
-       * file system.
-       */
-
-      else
-#endif
-        {
-          ret = inode->u.i_ops->open(&g_sysdev.sl_file);
-        }
-    }
-
-  /* Was the file/device successfully opened? */
-
+  ret = file_detach(fd, &g_syslog_dev.sl_file);
   if (ret < 0)
     {
-      ret = -ret;
-      goto errout_with_inode;
+      /* This should not happen and means that something very bad has
+       * occurred.
+       */
+
+      g_syslog_dev.sl_state = SYSLOG_FAILURE;
+      close(fd);
+      return ret;
     }
 
   /* The SYSLOG device is open and ready for writing. */
 
-  sem_init(&g_sysdev.sl_sem, 0, 1);
-  g_sysdev.sl_holder = NO_HOLDER;
-  g_sysdev.sl_state  = SYSLOG_OPENED;
+  sem_init(&g_syslog_dev.sl_sem, 0, 1);
+  g_syslog_dev.sl_holder = NO_HOLDER;
+  g_syslog_dev.sl_state  = SYSLOG_OPENED;
   return OK;
-
-errout_with_inode:
-  inode_release(inode);
-  g_sysdev.sl_state = SYSLOG_FAILURE;
-  return ret;
 }
 
 /****************************************************************************
- * Name: syslog_putc
+ * Name: syslog_dev_uninitialize
  *
  * Description:
- *   This is the low-level system logging interface.  The debugging/syslogging
- *   interfaces are syslog() and lowsyslog().  The difference is is that
- *   the syslog() function writes to syslogging device (usually fd=1, stdout)
- *   whereas lowsyslog() uses a lower level interface that works from
- *   interrupt handlers.  This function is a a low-level interface used to
- *   implement lowsyslog().
+ *   Called to disable the last device/file channel in preparation to use
+ *   a different SYSLOG device. Currently only used for CONFIG_SYSLOG_FILE.
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   Zero (OK) is returned on success; a negated errno value is returned on
+ *   any failure.
+ *
+ * Assumptions:
+ *   The caller has already switched the SYSLOG source to some safe channel
+ *   (the default channel).
  *
  ****************************************************************************/
 
-int syslog_putc(int ch)
+#ifdef CONFIG_SYSLOG_FILE /* Currently only used in this configuration */
+int syslog_dev_uninitialize(void)
+{
+  /* Attempt to flush any buffered data */
+
+  sched_lock();
+  (void)syslog_dev_flush();
+
+  /* Close the detached file instance */
+
+  (void)file_close_detached(&g_syslog_dev.sl_file);
+
+  /* Free the device path */
+
+  if (g_syslog_dev.sl_devpath != NULL)
+    {
+      kmm_free(g_syslog_dev.sl_devpath);
+    }
+
+  /* Destroy the semaphore */
+
+  sem_destroy(&g_syslog_dev.sl_sem);
+
+  /* Reset the state structure */
+
+  memset(&g_syslog_dev, 0, sizeof(struct syslog_dev_s));
+  sched_unlock();
+  return OK;
+}
+#endif /* CONFIG_SYSLOG_FILE */
+
+/****************************************************************************
+ * Name: syslog_dev_putc
+ *
+ * Description:
+ *   This is the low-level system logging interface provided for the
+ *   character driver interface.
+ *
+ * Input Parameters:
+ *   ch - The character to add to the SYSLOG (must be positive).
+ *
+ * Returned Value:
+ *   On success, the character is echoed back to the caller.  A negated
+ *   errno value is returned on any failure.
+ *
+ ****************************************************************************/
+
+int syslog_dev_putc(int ch)
 {
   ssize_t nbytes;
   uint8_t uch;
@@ -377,12 +401,12 @@ int syslog_putc(int ch)
    *
    * (1) Before the SYSLOG device has been initialized.  This could happen
    *     from debug output that occurs early in the boot sequence before
-   *     syslog_initialize() is called (SYSLOG_UNINITIALIZED).
+   *     syslog_dev_initialize() is called (SYSLOG_UNINITIALIZED).
    * (2) While the device is being initialized.  The case could happen if
-   *     debug output is generated while syslog_initialize() executes
+   *     debug output is generated while syslog_dev_initialize() executes
    *     (SYSLOG_INITIALIZING).
    * (3) While we are generating SYSLOG output.  The case could happen if
-   *     debug output is generated while syslog_putc() executes
+   *     debug output is generated while syslog_dev_putc() executes
    *     (This case is actually handled inside of syslog_semtake()).
    * (4) Any debug output generated from interrupt handlers.  A disadvantage
    *     of using the generic character device for the SYSLOG is that it
@@ -410,12 +434,12 @@ int syslog_putc(int ch)
    * has been successfully opened.
    */
 
-  if (g_sysdev.sl_state != SYSLOG_OPENED)
+  if (g_syslog_dev.sl_state != SYSLOG_OPENED)
     {
       /* Case (1) and (2) */
 
-      if (g_sysdev.sl_state == SYSLOG_UNINITIALIZED ||
-          g_sysdev.sl_state == SYSLOG_INITIALIZING)
+      if (g_syslog_dev.sl_state == SYSLOG_UNINITIALIZED ||
+          g_syslog_dev.sl_state == SYSLOG_INITIALIZING)
        {
          errcode = EAGAIN; /* Can't access the SYSLOG now... maybe next time? */
          goto errout_with_errcode;
@@ -423,13 +447,13 @@ int syslog_putc(int ch)
 
       /* Case (6) */
 
-      if (g_sysdev.sl_state == SYSLOG_FAILURE)
+      if (g_syslog_dev.sl_state == SYSLOG_FAILURE)
         {
           errcode = ENXIO;  /* There is no SYSLOG device */
           goto errout_with_errcode;
         }
 
-      /* syslog_initialize() is called as soon as enough of the operating
+      /* syslog_dev_initialize() is called as soon as enough of the operating
        * system is in place to support the open operation... but it is
        * possible that the SYSLOG device is not yet registered at that time.
        * In this case, we know that the system is sufficiently initialized
@@ -441,16 +465,19 @@ int syslog_putc(int ch)
        */
 
       sched_lock();
-      if (g_sysdev.sl_state == SYSLOG_REOPEN)
+      if (g_syslog_dev.sl_state == SYSLOG_REOPEN)
         {
           /* Try again to initialize the device.  We may do this repeatedly
            * because the log device might be something that was not ready
-           * the first time that syslog_initializee() was called (such as a
+           * the first time that syslog_dev_initializee() was called (such as a
            * USB serial device that has not yet been connected or a file in
            * an NFS mounted file system that has not yet been mounted).
            */
 
-          ret = syslog_initialize();
+          DEBUGASSERT(g_syslog_dev.sl_devpath != NULL);
+          ret = syslog_dev_initialize(g_syslog_dev.sl_devpath,
+                                      (int)g_syslog_dev.sl_oflags,
+                                      (int)g_syslog_dev.sl_mode);
           if (ret < 0)
             {
               sched_unlock();
@@ -460,7 +487,7 @@ int syslog_putc(int ch)
         }
 
       sched_unlock();
-      DEBUGASSERT(g_sysdev.sl_state == SYSLOG_OPENED);
+      DEBUGASSERT(g_syslog_dev.sl_state == SYSLOG_OPENED);
     }
 
   /* Ignore carriage returns */
@@ -474,11 +501,11 @@ int syslog_putc(int ch)
    * value to write.
    */
 
-  ret = syslog_takesem();
+  ret = syslog_dev_takesem();
   if (ret < 0)
     {
       /* We probably already hold the semaphore and were probably
-       * re-entered by the logic kicked off by syslog_write().
+       * re-entered by the logic kicked off by syslog_dev_write().
        * We might also have been interrupted by a signal.  Either
        * way, we are outta here.
        */
@@ -493,7 +520,7 @@ int syslog_putc(int ch)
     {
       /* Write the CR-LF sequence */
 
-      nbytes = syslog_write(g_syscrlf, 2);
+      nbytes = syslog_dev_write(g_syscrlf, 2);
 
       /* Synchronize the file when each CR-LF is encountered (i.e.,
        * implements line buffering always).
@@ -502,7 +529,7 @@ int syslog_putc(int ch)
 #ifndef CONFIG_DISABLE_MOUNTPOINT
       if (nbytes > 0)
         {
-          syslog_flush();
+          (void)syslog_dev_flush();
         }
 #endif
     }
@@ -511,10 +538,10 @@ int syslog_putc(int ch)
       /* Write the non-newline character (and don't flush) */
 
       uch = (uint8_t)ch;
-      nbytes = syslog_write(&uch, 1);
+      nbytes = syslog_dev_write(&uch, 1);
     }
 
-  syslog_givesem();
+  syslog_dev_givesem();
 
   /* Check if the write was successful.  If not, nbytes will be
    * a negated errno value.
@@ -533,4 +560,38 @@ errout_with_errcode:
   return EOF;
 }
 
-#endif /* CONFIG_SYSLOG && CONFIG_SYSLOG_CHAR */
+/****************************************************************************
+ * Name: syslog_dev_flush
+ *
+ * Description:
+ *   Flush any buffer data in the file system to media.
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   Zero (OK) on success; a negated errno value is returned on any failure.
+ *
+ ****************************************************************************/
+
+int syslog_dev_flush(void)
+{
+  int ret = 0;;
+
+#ifndef CONFIG_DISABLE_MOUNTPOINT
+  FAR struct inode *inode = g_syslog_dev.sl_file.f_inode;
+
+  /* Is this a mountpoint? Does it support the sync method? */
+
+  if (inode && inode->u.i_mops->sync)
+    {
+      /* Yes... synchronize to the stream */
+
+      ret = inode->u.i_mops->sync(&g_syslog_dev.sl_file);
+    }
+#endif
+
+  return ret;
+}
+
+#endif /* CONFIG_NFILE_DESCRIPTORS > 0 */
diff --git a/drivers/syslog/syslog_emergstream.c b/drivers/syslog/syslog_emergstream.c
new file mode 100644
index 00000000000..e0cc2be6ed9
--- /dev/null
+++ b/drivers/syslog/syslog_emergstream.c
@@ -0,0 +1,116 @@
+/****************************************************************************
+ * drivers/syslog/syslog_emergtream.c
+ *
+ *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdio.h>
+#include <unistd.h>
+#include <assert.h>
+#include <errno.h>
+
+#include <nuttx/syslog/syslog.h>
+#include <nuttx/streams.h>
+
+#include "syslog.h"
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: emergstream_putc
+ ****************************************************************************/
+
+static void emergstream_putc(FAR struct lib_outstream_s *this, int ch)
+{
+  int ret;
+
+  /* Try writing until the write was successful or until an irrecoverable
+   * error occurs.
+   */
+
+  do
+    {
+      /* Write the character to the supported logging device.  On failure,
+       * syslog_putc returns EOF with the errno value set;
+       */
+
+      ret = syslog_force(ch);
+      if (ret != EOF)
+        {
+          this->nput++;
+          return;
+        }
+
+      /* The special errno value -EINTR means that syslog_putc() was
+       * awakened by a signal.  This is not a real error and must be
+       * ignored in this context.
+       */
+    }
+  while (errno == -EINTR);
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: emergstream
+ *
+ * Description:
+ *   Initializes a stream for use with the configured emergency syslog
+ *   interface.  Only accessible from with the OS SYSLOG logic.
+ *
+ * Input parameters:
+ *   stream - User allocated, uninitialized instance of struct
+ *            lib_lowoutstream_s to be initialized.
+ *
+ * Returned Value:
+ *   None (User allocated instance initialized).
+ *
+ ****************************************************************************/
+
+void emergstream(FAR struct lib_outstream_s *stream)
+{
+  stream->put   = emergstream_putc;
+#ifdef CONFIG_STDIO_LINEBUFFER
+  stream->flush = lib_noflush;
+#endif
+  stream->nput  = 0;
+}
diff --git a/drivers/syslog/syslog_filechannel.c b/drivers/syslog/syslog_filechannel.c
new file mode 100644
index 00000000000..b703b889288
--- /dev/null
+++ b/drivers/syslog/syslog_filechannel.c
@@ -0,0 +1,186 @@
+/****************************************************************************
+ * drivers/syslog/syslog_filechannel.c
+ *
+ *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/stat.h>
+#include <fcntl.h>
+
+#include <nuttx/syslog/syslog.h>
+
+#include "syslog.h"
+
+#ifdef CONFIG_SYSLOG_FILE
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define OPEN_FLAGS (O_WRONLY | O_CREAT | O_APPEND)
+#define OPEN_MODE  (S_IROTH | S_IRGRP | S_IRUSR | S_IWUSR)
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/* SYSLOG channel methods */
+
+static int syslog_file_force(int ch);
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/* This structure describes the SYSLOG channel */
+
+static const struct syslog_channel_s g_syslog_file_channel =
+{
+  syslog_dev_putc,
+  syslog_file_force,
+  syslog_dev_flush,
+};
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: syslog_file_force
+ *
+ * Description:
+ *   A dummy FORCE method
+ *
+ ****************************************************************************/
+
+static int syslog_file_force(int ch)
+{
+  return ch;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: syslog_file_channel
+ *
+ * Description:
+ *   Configure to use a file in a mounted file system at 'devpath' as the
+ *   SYSLOG channel.
+ *
+ *   This tiny function is simply a wrapper around syslog_dev_initialize()
+ *   and syslog_channel().  It calls syslog_dev_initialize() to configure
+ *   the character file at 'devpath then calls syslog_channel() to use that
+ *   device as the SYSLOG output channel.
+ *
+ *   File SYSLOG channels differ from other SYSLOG channels in that they
+ *   cannot be established until after fully booting and mounting the target
+ *   file system.  This function would need to be called from board-specific
+ *   bring-up logic AFTER mounting the file system containing 'devpath'.
+ *
+ *   SYSLOG data generated prior to calling syslog_file_channel will, of
+ *   course, not be included in the file.
+ *
+ *   NOTE interrupt level SYSLOG output will be lost in this case unless
+ *   the interrupt buffer is used.
+ *
+ * Input Parameters:
+ *   devpath - The full path to the file to be used for SYSLOG output.
+ *     This may be an existing file or not.  If the file exists,
+ *     syslog_file_channel() will append new SYSLOG data to the end of the
+ *     file.  If it does not, then syslog_file_channel() will create the
+ *     file.
+ *
+ * Returned Value:
+ *   Zero (OK) is returned on success; a negated errno value is returned on
+ *   any failure.
+ *
+ ****************************************************************************/
+
+int syslog_file_channel(FAR const char *devpath)
+{
+  FAR const struct syslog_channel_s *saved_channel;
+  int ret;
+
+  /* Reset the default SYSLOG channel so that we can safely modify the
+   * SYSLOG device.  This is an atomic operation and we should be safe
+   * after the default channel has been selected.
+   *
+   * We disable pre-emption only so that we are not suspended and a lot of
+   * important debug output is lost.
+   */
+
+  saved_channel = g_syslog_channel;
+  ret = syslog_channel(&g_default_syslog_channel);
+  if (ret < 0)
+    {
+      return ret;
+    }
+
+  /* Uninitialize any driver interface that may have been in place */
+
+  ret = syslog_dev_uninitialize();
+  if (ret < 0)
+    {
+      /* Nothing fatal has happened yet, we can restore the last channel
+       * since it was not uninitialized (was it?)
+       */
+
+      (void)syslog_channel(saved_channel);
+      return ret;
+    }
+  
+  /* Then initialize the file interface */
+
+  ret = syslog_dev_initialize(devpath, OPEN_FLAGS, OPEN_MODE);
+  if (ret < 0)
+    {
+      /* We should still be able to back-up an re-initialized everything */
+
+      (void)syslog_initialize(SYSLOG_INIT_EARLY);
+      (void)syslog_initialize(SYSLOG_INIT_LATE);
+      return ret;
+    }
+
+  /* Use the file as the SYSLOG channel */
+
+  return syslog_channel(&g_syslog_file_channel);
+}
+
+#endif /* CONFIG_SYSLOG_FILE */
diff --git a/drivers/syslog/syslog_flush.c b/drivers/syslog/syslog_flush.c
new file mode 100644
index 00000000000..bd30c8a506a
--- /dev/null
+++ b/drivers/syslog/syslog_flush.c
@@ -0,0 +1,95 @@
+/****************************************************************************
+ * drivers/syslog/syslog_flush.c
+ *
+ *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdbool.h>
+#include <assert.h>
+
+#include <nuttx/syslog/syslog.h>
+
+#include "syslog.h"
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: syslog_flush
+ *
+ * Description:
+ *   This is called by system crash-handling logic.  It must flush any
+ *   buffered data to the SYSLOG device.
+ *
+ *   Interrupts are disabled at the time of the crash and this logic must
+ *   perform the flush using low-level, non-interrupt driven logic.
+ *
+ * Input Parameters:
+ *   ch - The character to add to the SYSLOG (must be positive).
+ *
+ * Returned Value:
+ *   Zero (OK)is returned on  success.  A negated errno value is returned
+ *   on any failure.
+ *
+ ****************************************************************************/
+
+#if 0
+/* REVISIT: (1) Not yet integrated into assertion handlers and (2) there is
+ * an implementation problem in that if a character driver is the underlying
+ * device, then there is no mechanism to flush the data buffered in the
+ * driver with interrupts disabled.
+ */
+
+int syslog_flush(void)
+{
+  DEBUGASSERT(g_syslog_channel != NULL && g_syslog_channel->sc_flush != NULL);
+
+#ifdef CONFIG_SYSLOG_INTBUFFER
+  /* Flush any characters that may have been added to the interrupt
+   * buffer.
+   */
+
+  (void)syslog_flush_intbuffer(g_syslog_channel, true);
+#endif
+
+  /* Then flush all of the buffered output to the SYSLOG device */
+
+  return g_syslog_channel->sc_flush();
+}
+#endif
diff --git a/drivers/syslog/syslog_force.c b/drivers/syslog/syslog_force.c
new file mode 100644
index 00000000000..418847371dc
--- /dev/null
+++ b/drivers/syslog/syslog_force.c
@@ -0,0 +1,86 @@
+/****************************************************************************
+ * drivers/syslog/syslog_force.c
+ *
+ *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+#include <stdbool.h>
+#include <assert.h>
+
+#include <nuttx/syslog/syslog.h>
+
+#include "syslog.h"
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: syslog_force
+ *
+ * Description:
+ *   This is the low-level system logging interface.  This version forces
+ *   the output and is only used in emergency situations (e.g., in assertion
+ *   handling).
+ *
+ * Input Parameters:
+ *   ch - The character to add to the SYSLOG (must be positive).
+ *
+ * Returned Value:
+ *   On success, the character is echoed back to the caller.  A negated
+ *   errno value is returned on any failure.
+ *
+ ****************************************************************************/
+
+int syslog_force(int ch)
+{
+  DEBUGASSERT(g_syslog_channel != NULL && g_syslog_channel->sc_force != NULL);
+
+#ifdef CONFIG_SYSLOG_INTBUFFER
+  /* Flush any characters that may have been added to the interrupt
+   * buffer through the emergency channel
+   */
+
+  (void)syslog_flush_intbuffer(g_syslog_channel, true);
+#endif
+
+  /* Then send the character to the emergency channel */
+
+  return g_syslog_channel->sc_force(ch);
+}
diff --git a/drivers/syslog/syslog_initialize.c b/drivers/syslog/syslog_initialize.c
new file mode 100644
index 00000000000..08f12831ac2
--- /dev/null
+++ b/drivers/syslog/syslog_initialize.c
@@ -0,0 +1,114 @@
+/****************************************************************************
+ * drivers/syslog/syslog_initialize.c
+ *
+ *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdio.h>
+
+#include <nuttx/syslog/syslog.h>
+
+#include "syslog.h"
+
+#ifndef CONFIG_ARCH_SYSLOG
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: syslog_initialize
+ *
+ * Description:
+ *   One power up, the SYSLOG facility is non-existent or limited to very
+ *   low-level output.  This function is called later in the initialization
+ *   sequence after full driver support has been initialized.  It installs
+ *   the configured SYSLOG drivers and enables full SYSLOGing capability.
+ *
+ *   This function performs these basic operations:
+ *
+ *   - Initialize the SYSLOG device
+ *   - Call syslog_channel() to begin using that device.
+ *
+ *   If CONFIG_ARCH_SYSLOG is selected, then the architecture-specifica
+ *   logic will provide its own SYSLOG device initialize which must include
+ *   as a minimum a call to syslog_channel() to use the device.
+ *
+ * Input Parameters:
+ *   phase - One of {SYSLOG_INIT_EARLY, SYSLOG_INIT_LATE}
+ *
+ * Returned Value:
+ *   Zero (OK) is returned on success; a negated errno value is returned on
+ *   any failure.
+ *
+ ****************************************************************************/
+
+int syslog_initialize(enum syslog_init_e phase)
+{
+  int ret = OK;
+
+#if defined(CONFIG_SYSLOG_CHAR)
+  if (phase == SYSLOG_INIT_LATE)
+    {
+      /* Enable use of a character device as the SYSLOG device */
+
+      ret = syslog_dev_channel();
+    }
+
+#elif defined(CONFIG_RAMLOG_SYSLOG)
+  if (phase == SYSLOG_INIT_EARLY)
+    {
+      /* Use the RAMLOG as the SYSLOG device */
+
+      ret = ramlog_syslog_channel();
+    }
+
+#elif defined(CONFIG_SYSLOG_CONSOLE)
+  if (phase == SYSLOG_INIT_LATE)
+    {
+      /* Use the console device as the SYSLOG device */
+
+      ret = syslog_console_channel();
+    }
+
+#endif
+
+  return ret;
+}
+
+#endif /* CONFIG_ARCH_SYSLOG */
diff --git a/drivers/syslog/syslog_intbuffer.c b/drivers/syslog/syslog_intbuffer.c
new file mode 100644
index 00000000000..28be3a74ca4
--- /dev/null
+++ b/drivers/syslog/syslog_intbuffer.c
@@ -0,0 +1,342 @@
+/****************************************************************************
+ * drivers/syslog/syslog_intbuffer.c
+ *
+ *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdbool.h>
+#include <stdio.h>
+#include <assert.h>
+#include <errno.h>
+
+#include <nuttx/syslog/syslog.h>
+#include <nuttx/irq.h>
+
+#include "syslog.h"
+
+#ifdef CONFIG_SYSLOG_INTBUFFER
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Extend the size of the interrupt buffer so that a "[truncated]\n"
+ * indication can be append to the end.
+ *
+ * The usable capacity of the interrupt buffer is (CONFIG_SYSLOG_INTBUFSIZE - 1).
+ */
+
+#define SYSLOG_BUFOVERRUN_MESSAGE  "[truncated]\n"
+#define SYSLOG_BUFOVERRUN_SIZE     13
+
+#if CONFIG_SYSLOG_INTBUFSIZE > (65535 - SYSLOG_BUFOVERRUN_SIZE)
+#  undef  CONFIG_SYSLOG_INTBUFSIZE
+#  define CONFIG_SYSLOG_INTBUFSIZE (65535 - SYSLOG_BUFOVERRUN_SIZE)
+#  define SYSLOG_INTBUFSIZE        65535
+#else
+#  define SYSLOG_INTBUFSIZE \
+     (CONFIG_SYSLOG_INTBUFSIZE + SYSLOG_BUFOVERRUN_SIZE)
+#endif
+
+#define USABLE_INTBUFSIZE          (CONFIG_SYSLOG_INTBUFSIZE - 1)
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/* This structure encapsulates the interrupt buffer state */
+
+struct g_syslog_intbuffer_s
+{
+  volatile uint16_t si_inndx;
+  volatile uint16_t si_outndx;
+  uint8_t si_buffer[SYSLOG_INTBUFSIZE];
+};
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static struct g_syslog_intbuffer_s g_syslog_intbuffer;
+static const char g_overrun_msg[SYSLOG_BUFOVERRUN_SIZE] = SYSLOG_BUFOVERRUN_MESSAGE;
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: syslog_remove_intbuffer
+ *
+ * Description:
+ *   Extract any characters that may have been added to the interrupt buffer
+ *   to the SYSLOG device.
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   On success, the extracted character is returned.  EOF is returned if
+ *   the interrupt buffer is empty.
+ *
+ * Assumptions:
+ *   Interrupts may or may not be disabled.
+ *
+ ****************************************************************************/
+
+int syslog_remove_intbuffer(void)
+{
+  irqstate_t flags;
+  uint32_t inndx;
+  uint32_t outndx;
+  uint32_t endndx;
+  int inuse = 0;
+  int ch;
+
+  /* Extraction of the character and adjustment of the circular buffer
+   * indices must be performed in a critical section to protect from
+   * concurrent modification from interrupt handlers.
+   */
+
+  flags = enter_critical_section();
+
+  /* How much space is left in the inbuffer? */
+
+  inndx  = (uint32_t)g_syslog_intbuffer.si_inndx;
+  outndx = (uint32_t)g_syslog_intbuffer.si_outndx;
+  if (inndx != outndx)
+    {
+      /* Handle the case where the inndx has wrapped around */
+
+      endndx = inndx;
+      if (endndx < outndx)
+        {
+          endndx += SYSLOG_INTBUFSIZE;
+        }
+
+      inuse = (int)(endndx - outndx);
+
+      /* Take the next character from the interrupt buffer */
+
+      ch = g_syslog_intbuffer.si_buffer[outndx];
+
+      /* Increment the OUT index, handling wrap-around */
+
+      if (++outndx >= SYSLOG_INTBUFSIZE)
+        {
+          outndx -= SYSLOG_INTBUFSIZE;
+        }
+
+      g_syslog_intbuffer.si_outndx = (uint16_t)outndx;
+    }
+
+  leave_critical_section(flags);
+
+  /* Now we can send the extracted character to the SYSLOG device */
+
+  return (inuse > 0) ? ch : EOF;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: syslog_add_intbuffer
+ *
+ * Description:
+ *   Add one more character to the interrupt buffer.  In the event of
+ *   buffer overlowed, the character will be dropped.  The indication
+ *   "[truncated]\n" will be appended to the end of the interrupt buffer.
+ *
+ * Input Parameters:
+ *   ch - The character to add to the interrupt buffer (must be positive).
+ *
+ * Returned Value:
+ *   Zero success, the character is echoed back to the caller.  A negated
+ *   errno value is returned on any failure.
+ *
+ * Assumptions:
+ *   - Called either from (1) interrupt handling logic with interrupts
+ *     disabled or from an IDLE thread with interrupts enabled.
+ *   - Requires caution because there may be an interrupted execution of
+ *     syslog_flush_intbuffer():  Only the outndx can be modified.
+ *
+ ****************************************************************************/
+
+int syslog_add_intbuffer(int ch)
+{
+  irqstate_t flags;
+  uint32_t inndx;
+  uint32_t outndx;
+  uint32_t endndx;
+  unsigned int inuse;
+  int ret;
+  int i;
+
+  /* Disable concurrent modification from interrupt handling logic */
+
+  flags = enter_critical_section();
+
+  /* How much space is left in the inbuffer? */
+
+  inndx  = (uint32_t)g_syslog_intbuffer.si_inndx;
+  outndx = (uint32_t)g_syslog_intbuffer.si_outndx;
+
+  endndx = inndx;
+  if (endndx < outndx)
+    {
+      endndx += SYSLOG_INTBUFSIZE;
+    }
+
+  inuse = (unsigned int)(endndx - outndx);
+
+  /* Is there space for another character (reserving space for the overrun
+   * message)?
+   */
+
+  if (inuse == USABLE_INTBUFSIZE)
+    {
+      /* Copy the truncated message one character at a time, handing index
+       * wrap-around on each character.
+       */
+
+      for (i = 0; i < SYSLOG_BUFOVERRUN_SIZE; i++)
+        {
+          /* Copy one character */
+
+          g_syslog_intbuffer.si_buffer[inndx] = (uint8_t)g_overrun_msg[i];
+
+          /* Increment the IN index, handling wrap-around */
+
+          if (++inndx >= SYSLOG_INTBUFSIZE)
+            {
+              inndx -= SYSLOG_INTBUFSIZE;
+            }
+
+          DEBUGASSERT(inndx != outndx);
+        }
+
+      g_syslog_intbuffer.si_inndx = (uint16_t)inndx;
+      ret = -ENOSPC;
+    }
+  else if (inuse < USABLE_INTBUFSIZE)
+    {
+       /* Copy one character */
+
+       g_syslog_intbuffer.si_buffer[inndx] = (uint8_t)ch;
+
+       /* Increment the IN index, handling wrap-around */
+
+       if (++inndx >= SYSLOG_INTBUFSIZE)
+         {
+           inndx -= SYSLOG_INTBUFSIZE;
+         }
+
+      g_syslog_intbuffer.si_inndx = (uint16_t)inndx;
+      ret = OK;
+    }
+  else
+    {
+      /* This character goes to the bit bucket.  We have already copied
+       * the overrun message so there is nothing else to do.
+       */
+
+      ret = -ENOSPC;
+    }
+
+  leave_critical_section(flags);
+  return ret;
+}
+
+/****************************************************************************
+ * Name: syslog_flush_intbuffer
+ *
+ * Description:
+ *   Flush any characters that may have been added to the interrupt buffer
+ *   to the SYSLOG device.
+ *
+ * Input Parameters:
+ *   channel - The syslog channel to use in performing the flush operation.
+ *   force   - Use the force() method of the channel vs. the putc() method.
+ *
+ * Returned Value:
+ *   On success, the character is echoed back to the caller.  A negated
+ *   errno value is returned on any failure.
+ *
+ * Assumptions:
+ *   Interrupts may or may not be disabled.
+ *
+ ****************************************************************************/
+
+int syslog_flush_intbuffer(FAR const struct syslog_channel_s *channel,
+                           bool force)
+{
+  syslog_putc_t putfunc;
+  int ch;
+  int ret = OK;
+
+  /* Select which putc function to use for this flush */
+
+  putfunc = force ? channel->sc_putc : channel->sc_force;
+
+  /* This logic is performed with the scheduler disabled to protect from
+   * concurrent modification by other tasks.
+   */
+
+  sched_lock();
+  do
+    {
+      /* Transfer one character to time.  This is inefficient, but is
+       * done in this way to: (1) Deal with concurrent modification of
+       * the interrupt buffer from interrupt activity, (2) Avoid keeper
+       * interrupts disabled for a long time, and (3) to handler
+       * wraparound of the circular buffer indices.
+       */
+
+      ch = syslog_remove_intbuffer();
+      if (ch != EOF)
+        {
+          ret = putfunc(ch);
+        }
+    }
+  while (ch != EOF && ret >= 0);
+
+  sched_unlock();
+  return ret;
+}
+
+#endif /* CONFIG_SYSLOG_INTBUFFER */
diff --git a/drivers/syslog/syslog_putc.c b/drivers/syslog/syslog_putc.c
new file mode 100644
index 00000000000..3f19b6c0050
--- /dev/null
+++ b/drivers/syslog/syslog_putc.c
@@ -0,0 +1,110 @@
+/****************************************************************************
+ * drivers/syslog/syslog_putc.c
+ *
+ *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+#include <assert.h>
+#include <errno.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/sched.h>
+#include <nuttx/syslog/syslog.h>
+
+#include "syslog.h"
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: syslog_putc
+ *
+ * Description:
+ *   This is the low-level system logging interface.
+ *
+ * Input Parameters:
+ *   ch - The character to add to the SYSLOG (must be positive).
+ *
+ * Returned Value:
+ *   On success, the character is echoed back to the caller.  A negated
+ *   errno value is returned on any failure.
+ *
+ ****************************************************************************/
+
+int syslog_putc(int ch)
+{
+  DEBUGASSERT(g_syslog_channel != NULL);
+
+  /* Is this an attempt to do SYSLOG output from an interrupt handler? */
+
+  if (up_interrupt_context() || sched_idletask())
+    {
+#if defined(CONFIG_SYSLOG_INTBUFFER)
+      /* Buffer the character in the interrupt buffer.  The interrupt buffer
+       * will be flushed before the next normal, non-interrupt SYSLOG output.
+       */
+
+      return syslog_add_intbuffer(ch);
+#else
+      /* Force the character to the SYSLOG device immediately (if possible).
+       * This means that the interrupt data may not be in synchronization
+       * with output data that may have been buffered by sc_putc().
+       */
+
+      DEBUGASSERT(g_syslog_channel->sc_force != NULL);
+
+      return g_syslog_channel->sc_force(ch);
+#endif
+    }
+  else
+    {
+      DEBUGASSERT(g_syslog_channel->sc_putc != NULL);
+
+#ifdef CONFIG_SYSLOG_INTBUFFER
+      /* Flush any characters that may have been added to the interrupt
+       * buffer.
+       */
+
+      (void)syslog_flush_intbuffer(g_syslog_channel, false);
+#endif
+
+      return g_syslog_channel->sc_putc(ch);
+    }
+}
diff --git a/libc/syslog/lib_syslogstream.c b/drivers/syslog/syslog_stream.c
similarity index 86%
rename from libc/syslog/lib_syslogstream.c
rename to drivers/syslog/syslog_stream.c
index 4c6cfa8c2e1..491da95c266 100644
--- a/libc/syslog/lib_syslogstream.c
+++ b/drivers/syslog/syslog_stream.c
@@ -1,7 +1,7 @@
 /****************************************************************************
- * libc/syslog/lib_syslogstream.c
+ * drivers/syslog/syslog_stream.c
  *
- *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2012, 2016 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -47,13 +47,7 @@
 #include <nuttx/syslog/syslog.h>
 #include <nuttx/streams.h>
 
-#include "syslog/syslog.h"
-
-#ifdef CONFIG_SYSLOG
-
-/****************************************************************************
- * Pre-processor definition
- ****************************************************************************/
+#include "syslog.h"
 
 /****************************************************************************
  * Private Functions
@@ -97,21 +91,22 @@ static void syslogstream_putc(FAR struct lib_outstream_s *this, int ch)
  ****************************************************************************/
 
 /****************************************************************************
- * Name: lib_syslogstream
+ * Name: syslogstream
  *
  * Description:
  *   Initializes a stream for use with the configured syslog interface.
+ *   Only accessible from with the OS SYSLOG logic.
  *
  * Input parameters:
- *   lowoutstream - User allocated, uninitialized instance of struct
- *                  lib_lowoutstream_s to be initialized.
+ *   stream - User allocated, uninitialized instance of struct
+ *            lib_lowoutstream_s to be initialized.
  *
  * Returned Value:
  *   None (User allocated instance initialized).
  *
  ****************************************************************************/
 
-void lib_syslogstream(FAR struct lib_outstream_s *stream)
+void syslogstream(FAR struct lib_outstream_s *stream)
 {
   stream->put   = syslogstream_putc;
 #ifdef CONFIG_STDIO_LINEBUFFER
@@ -119,5 +114,3 @@ void lib_syslogstream(FAR struct lib_outstream_s *stream)
 #endif
   stream->nput  = 0;
 }
-
-#endif /* CONFIG_SYSLOG */
diff --git a/drivers/syslog/vsyslog.c b/drivers/syslog/vsyslog.c
new file mode 100644
index 00000000000..27fab399ecb
--- /dev/null
+++ b/drivers/syslog/vsyslog.c
@@ -0,0 +1,114 @@
+/****************************************************************************
+ * drivers/syslog/vsyslog.c
+ *
+ *   Copyright (C) 2007-2009, 2011-2014, 2016 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdio.h>
+#include <syslog.h>
+
+#include <nuttx/init.h>
+#include <nuttx/arch.h>
+#include <nuttx/clock.h>
+#include <nuttx/streams.h>
+#include <nuttx/syslog/syslog.h>
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: _vsyslog
+ *
+ * Description:
+ *   _vsyslog() handles the system logging system calls. It is functionally
+ *   equivalent to vsyslog() except that (1) the per-process priority
+ *   filtering has already been performed and the va_list parameter is
+ *   passed by reference.  That is because the va_list is a structure in
+ *   some compilers and passing of structures in the NuttX sycalls does
+ *   not work.
+ *
+ ****************************************************************************/
+
+int _vsyslog(int priority, FAR const IPTR char *fmt, FAR va_list *ap)
+{
+  struct lib_outstream_s stream;
+#ifdef CONFIG_SYSLOG_TIMESTAMP
+  struct timespec ts;
+
+  /* Get the current time.  Since debug output may be generated very early
+   * in the start-up sequence, hardware timer support may not yet be
+   * available.
+   */
+
+  if (!OSINIT_HW_READY() || clock_systimespec(&ts) < 0)
+    {
+      /* Timer hardware is not available, or clock_systimespec failed */
+
+      ts.tv_sec  = 0;
+      ts.tv_nsec = 0;
+    }
+#endif
+
+  /* Wrap the low-level output in a stream object and let lib_vsprintf
+   * do the work.  NOTE that emergency priority output is handled
+   * differently.. it will use the SYSLOG emergency stream.
+   */
+
+  if (priority == LOG_EMERG)
+    {
+      /* Use the SYSLOG emergency stream */
+
+      emergstream((FAR struct lib_outstream_s *)&stream);
+    }
+  else
+    {
+      /* Use the normal SYSLOG stream */
+
+      syslogstream((FAR struct lib_outstream_s *)&stream);
+    }
+
+#if defined(CONFIG_SYSLOG_TIMESTAMP)
+  /* Pre-pend the message with the current time, if available */
+
+  (void)lib_sprintf((FAR struct lib_outstream_s *)&stream,
+                    "[%6d.%06d]", ts.tv_sec, ts.tv_nsec/1000);
+#endif
+
+  return lib_vsprintf((FAR struct lib_outstream_s *)&stream, fmt, *ap);
+}
diff --git a/drivers/usbdev/usbdev_trace.c b/drivers/usbdev/usbdev_trace.c
index 3e9831562e2..857cd3e0294 100644
--- a/drivers/usbdev/usbdev_trace.c
+++ b/drivers/usbdev/usbdev_trace.c
@@ -100,10 +100,10 @@ static int usbtrace_syslog(const char *fmt, ...)
   va_list ap;
   int ret;
 
-  /* Let lowvsyslog do the real work */
+  /* Let vsyslog do the real work */
 
   va_start(ap, fmt);
-  ret = lowvsyslog(LOG_INFO, fmt, ap);
+  ret = vsyslog(LOG_INFO, fmt, ap);
   va_end(ap);
   return ret;
 }
@@ -190,7 +190,7 @@ void usbtrace(uint16_t event, uint16_t value)
             }
         }
 #else
-      /* Just print the data using lowsyslog */
+      /* Just print the data using syslog */
 
       usbtrace_trprintf(usbtrace_syslog, event, value);
 #endif
diff --git a/drivers/usbdev/usbmsc_scsi.c b/drivers/usbdev/usbmsc_scsi.c
index 66f2b586b9c..fd9e55cb6b4 100644
--- a/drivers/usbdev/usbmsc_scsi.c
+++ b/drivers/usbdev/usbmsc_scsi.c
@@ -200,13 +200,13 @@ static void usbmsc_dumpdata(const char *msg, const uint8_t *buf, int buflen)
 {
   int i;
 
-  lowsyslog(LOG_DEBUG, "%s:", msg);
+  syslog(LOG_DEBUG, "%s:", msg);
   for (i = 0; i < buflen; i++)
     {
-      lowsyslog(LOG_DEBUG, " %02x", buf[i]);
+      syslog(LOG_DEBUG, " %02x", buf[i]);
     }
 
-  lowsyslog(LOG_DEBUG, "\n");
+  syslog(LOG_DEBUG, "\n");
 }
 #endif
 
diff --git a/drivers/usbhost/usbhost_hidkbd.c b/drivers/usbhost/usbhost_hidkbd.c
index 3cce14abddd..c8a3c582f7c 100644
--- a/drivers/usbhost/usbhost_hidkbd.c
+++ b/drivers/usbhost/usbhost_hidkbd.c
@@ -178,12 +178,8 @@
 #ifndef CONFIG_DEBUG_INPUT
 #  undef  ierr
 #  define ierr    uerr
-#  undef  illerr
-#  define illerr  ullerr
 #  undef  iinfo
 #  define iinfo   uinfo
-#  undef  illinfo
-#  define illinfo ullinfo
 #endif
 
 /****************************************************************************
@@ -1524,9 +1520,9 @@ static inline int usbhost_cfgdesc(FAR struct usbhost_state_s *priv,
 
   if ((found & USBHOST_RQDFOUND) != USBHOST_RQDFOUND)
     {
-      ullerr("ERROR: Found IF:%s EPIN:%s\n",
-             (found & USBHOST_IFFOUND) != 0  ? "YES" : "NO",
-             (found & USBHOST_EPINFOUND) != 0 ? "YES" : "NO");
+      uerr("ERROR: Found IF:%s EPIN:%s\n",
+           (found & USBHOST_IFFOUND) != 0  ? "YES" : "NO",
+           (found & USBHOST_EPINFOUND) != 0 ? "YES" : "NO");
       return -EINVAL;
     }
 
@@ -1543,8 +1539,8 @@ static inline int usbhost_cfgdesc(FAR struct usbhost_state_s *priv,
 
   /* Then the optional interrupt OUT endpoint */
 
-  ullinfo("Found EPOOUT:%s\n",
-         (found & USBHOST_EPOUTFOUND) != 0 ? "YES" : "NO");
+  uinfo("Found EPOOUT:%s\n",
+       (found & USBHOST_EPOUTFOUND) != 0 ? "YES" : "NO");
 
   if ((found & USBHOST_EPOUTFOUND) != 0)
     {
@@ -1557,7 +1553,7 @@ static inline int usbhost_cfgdesc(FAR struct usbhost_state_s *priv,
         }
     }
 
-  ullinfo("Endpoints allocated\n");
+  uinfo("Endpoints allocated\n");
   return OK;
 }
 
@@ -1991,7 +1987,7 @@ static int usbhost_disconnected(struct usbhost_class_s *usbclass)
    */
 
   priv->disconnected = true;
-  ullinfo("Disconnected\n");
+  uinfo("Disconnected\n");
 
   /* Is there a thread waiting for keyboard data that will never come? */
 
diff --git a/drivers/usbhost/usbhost_hidmouse.c b/drivers/usbhost/usbhost_hidmouse.c
index 2c04dc4a6d4..922e133c8b9 100644
--- a/drivers/usbhost/usbhost_hidmouse.c
+++ b/drivers/usbhost/usbhost_hidmouse.c
@@ -199,12 +199,8 @@
 #ifndef CONFIG_DEBUG_INPUT
 #  undef  ierr
 #  define ierr    uerr
-#  undef  illerr
-#  define illerr  ullerr
 #  undef  iinfo
 #  define iinfo   uinfo
-#  undef  illinfo
-#  define illinfo ullinfo
 #endif
 
 /****************************************************************************
@@ -1613,9 +1609,9 @@ static inline int usbhost_cfgdesc(FAR struct usbhost_state_s *priv,
 
   if ((found & USBHOST_ALLFOUND) != USBHOST_ALLFOUND)
     {
-      ullerr("ERROR: Found IF:%s EPIN:%s\n",
-             (found & USBHOST_IFFOUND) != 0  ? "YES" : "NO",
-             (found & USBHOST_EPINFOUND) != 0 ? "YES" : "NO");
+      uerr("ERROR: Found IF:%s EPIN:%s\n",
+           (found & USBHOST_IFFOUND) != 0  ? "YES" : "NO",
+           (found & USBHOST_EPINFOUND) != 0 ? "YES" : "NO");
       return -EINVAL;
     }
 
@@ -1628,7 +1624,7 @@ static inline int usbhost_cfgdesc(FAR struct usbhost_state_s *priv,
       return ret;
     }
 
-  ullinfo("Endpoint allocated\n");
+  uinfo("Endpoint allocated\n");
   return OK;
 }
 
@@ -2062,7 +2058,7 @@ static int usbhost_disconnected(struct usbhost_class_s *usbclass)
    */
 
   priv->disconnected = true;
-  ullinfo("Disconnected\n");
+  uinfo("Disconnected\n");
 
   /* Are there a thread(s) waiting for mouse data that will never come? */
 
diff --git a/drivers/usbhost/usbhost_hub.c b/drivers/usbhost/usbhost_hub.c
index 0956bd104bb..add1455ca3b 100644
--- a/drivers/usbhost/usbhost_hub.c
+++ b/drivers/usbhost/usbhost_hub.c
@@ -463,9 +463,9 @@ static inline int usbhost_cfgdesc(FAR struct usbhost_class_s *hubclass,
 
   if (found != USBHOST_ALLFOUND)
     {
-      ullerr("ERROR: Found IF=%s EPIN=%s\n",
-             (found & USBHOST_IFFOUND) != 0  ? "YES" : "NO",
-             (found & USBHOST_EPINFOUND) != 0 ? "YES" : "NO");
+      uerr("ERROR: Found IF=%s EPIN=%s\n",
+           (found & USBHOST_IFFOUND) != 0  ? "YES" : "NO",
+           (found & USBHOST_EPINFOUND) != 0 ? "YES" : "NO");
       return -EINVAL;
     }
 
@@ -479,7 +479,7 @@ static inline int usbhost_cfgdesc(FAR struct usbhost_class_s *hubclass,
       return ret;
     }
 
-  ullinfo("Endpoint allocated\n");
+  uinfo("Endpoint allocated\n");
   return OK;
 }
 
@@ -1190,7 +1190,7 @@ static void usbhost_callback(FAR void *arg, ssize_t nbytes)
       if (nbytes != -EAGAIN)
 #endif
         {
-          ullerr("ERROR: Transfer failed: %d\n", (int)nbytes);
+          uerr("ERROR: Transfer failed: %d\n", (int)nbytes);
         }
 
       /* Indicate there there is nothing to do.  So when the work is
diff --git a/drivers/usbhost/usbhost_skeleton.c b/drivers/usbhost/usbhost_skeleton.c
index fa44f541094..a03d1101f7c 100644
--- a/drivers/usbhost/usbhost_skeleton.c
+++ b/drivers/usbhost/usbhost_skeleton.c
@@ -576,10 +576,10 @@ static inline int usbhost_cfgdesc(FAR struct usbhost_state_s *priv,
 
   if (found != USBHOST_ALLFOUND)
     {
-      ullerr("ERROR: Found IF:%s BIN:%s BOUT:%s\n",
-             (found & USBHOST_IFFOUND) != 0  ? "YES" : "NO",
-             (found & USBHOST_BINFOUND) != 0 ? "YES" : "NO",
-             (found & USBHOST_BOUTFOUND) != 0 ? "YES" : "NO");
+      uerr("ERROR: Found IF:%s BIN:%s BOUT:%s\n",
+           (found & USBHOST_IFFOUND) != 0  ? "YES" : "NO",
+           (found & USBHOST_BINFOUND) != 0 ? "YES" : "NO",
+           (found & USBHOST_BOUTFOUND) != 0 ? "YES" : "NO");
       return -EINVAL;
     }
 
@@ -600,7 +600,7 @@ static inline int usbhost_cfgdesc(FAR struct usbhost_state_s *priv,
       return ret;
     }
 
-  ullinfo("Endpoints allocated\n");
+  uinfo("Endpoints allocated\n");
   return OK;
 }
 
@@ -1013,7 +1013,7 @@ static int usbhost_disconnected(struct usbhost_class_s *usbclass)
    * block driver.
    */
 
-  ullinfo("crefs: %d\n", priv->crefs);
+  uinfo("crefs: %d\n", priv->crefs);
   if (priv->crefs == 1)
     {
       /* Destroy the class instance.  If we are executing from an interrupt
diff --git a/drivers/usbhost/usbhost_storage.c b/drivers/usbhost/usbhost_storage.c
index 13e6fae03d9..c7df71a7f43 100644
--- a/drivers/usbhost/usbhost_storage.c
+++ b/drivers/usbhost/usbhost_storage.c
@@ -377,7 +377,7 @@ static inline FAR struct usbhost_state_s *usbhost_allocclass(void)
     }
 
   leave_critical_section(flags);
-  ullinfo("Allocated: %p\n", entry);
+  uinfo("Allocated: %p\n", entry);
   return (FAR struct usbhost_state_s *)entry;
 }
 #else
@@ -417,7 +417,7 @@ static inline void usbhost_freeclass(FAR struct usbhost_state_s *usbclass)
   irqstate_t flags;
   DEBUGASSERT(entry != NULL);
 
-  ullinfo("Freeing: %p\n", entry);
+  uinfo("Freeing: %p\n", entry);
 
   /* Just put the pre-allocated class structure back on the freelist */
 
@@ -1161,10 +1161,10 @@ static inline int usbhost_cfgdesc(FAR struct usbhost_state_s *priv,
 
   if (found != USBHOST_ALLFOUND)
     {
-      ullerr("ERROR: Found IF:%s BIN:%s BOUT:%s\n",
-             (found & USBHOST_IFFOUND) != 0  ? "YES" : "NO",
-             (found & USBHOST_BINFOUND) != 0 ? "YES" : "NO",
-             (found & USBHOST_BOUTFOUND) != 0 ? "YES" : "NO");
+      uerr("ERROR: Found IF:%s BIN:%s BOUT:%s\n",
+           (found & USBHOST_IFFOUND) != 0  ? "YES" : "NO",
+           (found & USBHOST_BINFOUND) != 0 ? "YES" : "NO",
+           (found & USBHOST_BOUTFOUND) != 0 ? "YES" : "NO");
       return -EINVAL;
     }
 
@@ -1185,7 +1185,7 @@ static inline int usbhost_cfgdesc(FAR struct usbhost_state_s *priv,
       return ret;
     }
 
-  ullinfo("Endpoints allocated\n");
+  uinfo("Endpoints allocated\n");
   return OK;
 }
 
@@ -1830,7 +1830,7 @@ static int usbhost_disconnected(struct usbhost_class_s *usbclass)
    * block driver.
    */
 
-  ullinfo("crefs: %d\n", priv->crefs);
+  uinfo("crefs: %d\n", priv->crefs);
   if (priv->crefs == 1)
     {
       /* Destroy the class instance.  If we are executing from an interrupt
diff --git a/drivers/wireless/cc3000/cc3000.c b/drivers/wireless/cc3000/cc3000.c
index 4d08431d9e6..6c0fb748286 100644
--- a/drivers/wireless/cc3000/cc3000.c
+++ b/drivers/wireless/cc3000/cc3000.c
@@ -124,8 +124,8 @@ CCASSERT(sizeof(cc3000_buffer_desc) <= CONFIG_MQ_MAXMSGSIZE);
 #  define PROBE(pin,state)
 #endif
 
-#define waitllerr(x,...) //  _llerr
-#define waitllinfo(x,...) // _llinfo
+#define waiterr(x,...) //  _err
+#define waitinfo(x,...) // _info
 
 /****************************************************************************
  * Private Function Prototypes
@@ -419,7 +419,7 @@ static void cc3000_pollnotify(FAR struct cc3000_dev_s *priv, uint32_t type)
       if (fds)
         {
           fds->revents |= type;
-          nllinfo("Report events: %02x\n", fds->revents);
+          ninfo("Report events: %02x\n", fds->revents);
           sem_post(fds->sem);
         }
     }
@@ -497,7 +497,7 @@ static void * select_thread_func(FAR void *arg)
               if (priv->sockets[s].sd == CLOSE_SLOT)
                 {
                   priv->sockets[s].sd = FREE_SLOT;
-                  waitllinfo("Close\n");
+                  waitinfo("Close\n");
                   int count;
                   do
                     {
@@ -506,7 +506,7 @@ static void * select_thread_func(FAR void *arg)
                         {
                           /* Release the waiting threads */
 
-                          waitllinfo("Closed Signaled %d\n", count);
+                          waitinfo("Closed Signaled %d\n", count);
                           sem_post(&priv->sockets[s].semwait);
                         }
                     }
@@ -553,17 +553,17 @@ static void * select_thread_func(FAR void *arg)
             {
               if (ret > 0 && CC3000_FD_ISSET(priv->sockets[s].sd, &readsds)) /* and has pending data */
                 {
-                  waitllinfo("Signaled %d\n", priv->sockets[s].sd);
+                  waitinfo("Signaled %d\n", priv->sockets[s].sd);
                   sem_post(&priv->sockets[s].semwait);                       /* release the waiting thread */
                 }
               else if (ret > 0 && CC3000_FD_ISSET(priv->sockets[s].sd, &exceptsds)) /* or has pending exception */
                 {
-                  waitllinfo("Signaled %d (exception)\n", priv->sockets[s].sd);
+                  waitinfo("Signaled %d (exception)\n", priv->sockets[s].sd);
                   sem_post(&priv->sockets[s].semwait);                       /* release the waiting thread */
                 }
               else if (priv->sockets[s].received_closed_event)               /* or remote has closed connection and we have now read all of HW buffer. */
                 {
-                  waitllinfo("Signaled %d (closed & empty)\n", priv->sockets[s].sd);
+                  waitinfo("Signaled %d (closed & empty)\n", priv->sockets[s].sd);
                   priv->sockets[s].emptied_and_remotely_closed = true;
                   sem_post(&priv->sockets[s].semwait);                       /* release the waiting thread */
                 }
@@ -620,7 +620,7 @@ static void * cc3000_worker(FAR void *arg)
       if ((cc3000_wait_irq(priv) != -EINTR) && (priv->workertid != -1))
         {
           PROBE(0, 0);
-          nllinfo("State%d\n", priv->state);
+          ninfo("State%d\n", priv->state);
           switch (priv->state)
             {
             case eSPI_STATE_POWERUP:
@@ -676,7 +676,7 @@ static void * cc3000_worker(FAR void *arg)
 
                     if (data_to_recv >= priv->rx_buffer_max_len)
                       {
-                        lowsyslog(LOG_INFO, "data_to_recv %d", data_to_recv);
+                        ninfo("data_to_recv %d", data_to_recv);
                       }
 
                     DEBUGASSERT(data_to_recv < priv->rx_buffer_max_len);
@@ -707,10 +707,10 @@ static void * cc3000_worker(FAR void *arg)
 
                     cc3000_devgive(priv);
 
-                    nllinfo("Wait On Completion\n");
+                    ninfo("Wait On Completion\n");
                     sem_wait(priv->wrkwaitsem);
-                    nllinfo("Completed S:%d irq :%d\n",
-                            priv->state, priv->config->irq_read(priv->config));
+                    ninfo("Completed S:%d irq :%d\n",
+                          priv->state, priv->config->irq_read(priv->config));
 
                     sem_getvalue(&priv->irqsem, &count);
                     if (priv->config->irq_read(priv->config) && count == 0)
@@ -729,7 +729,7 @@ static void * cc3000_worker(FAR void *arg)
               break;
 
             default:
-              nllinfo("default: State%d\n", priv->state);
+              ninfo("default: State%d\n", priv->state);
               break;
             }
         }
@@ -799,7 +799,7 @@ static int cc3000_open(FAR struct file *filep)
 
   CHECK_GUARD(priv);
 
-  nllinfo("crefs: %d\n", priv->crefs);
+  ninfo("crefs: %d\n", priv->crefs);
 
   /* Get exclusive access to the driver data structure */
 
@@ -979,7 +979,7 @@ static int cc3000_close(FAR struct file *filep)
 
   CHECK_GUARD(priv);
 
-  nllinfo("crefs: %d\n", priv->crefs);
+  ninfo("crefs: %d\n", priv->crefs);
 
   /* Get exclusive access to the driver data structure */
 
@@ -1049,7 +1049,7 @@ static ssize_t cc3000_read(FAR struct file *filep, FAR char *buffer, size_t len)
   int ret;
   ssize_t nread;
 
-  nllinfo("buffer:%p len:%d\n", buffer, len);
+  ninfo("buffer:%p len:%d\n", buffer, len);
   DEBUGASSERT(filep);
   inode = filep->f_inode;
 
@@ -1088,7 +1088,7 @@ static ssize_t cc3000_read(FAR struct file *filep, FAR char *buffer, size_t len)
        * option, then just return an error.
        */
 
-      nllinfo("CC3000 data is not available\n");
+      ninfo("CC3000 data is not available\n");
       if (filep->f_oflags & O_NONBLOCK)
         {
           nread = -EAGAIN;
@@ -1109,7 +1109,7 @@ static ssize_t cc3000_read(FAR struct file *filep, FAR char *buffer, size_t len)
        * but will be re-enabled while we are waiting.
        */
 
-      nllinfo("Waiting..\n");
+      ninfo("Waiting..\n");
       ret = sem_wait(&priv->waitsem);
       priv->nwaiters--;
       sched_unlock();
@@ -1163,7 +1163,7 @@ errout_with_sem:
   cc3000_devgive(priv);
 
 errout_without_sem:
-  nllinfo("Returning: %d\n", nread);
+  ninfo("Returning: %d\n", nread);
 #ifndef CONFIG_DISABLE_POLL
   if (nread > 0)
     {
@@ -1195,7 +1195,7 @@ static ssize_t cc3000_write(FAR struct file *filep, FAR const char *usrbuffer, s
 
   size_t tx_len = (len & 1) ? len : len +1;
 
-  nllinfo("buffer:%p len:%d tx_len:%d\n", buffer, len, tx_len);
+  ninfo("buffer:%p len:%d tx_len:%d\n", buffer, len, tx_len);
 
   DEBUGASSERT(filep);
   inode = filep->f_inode;
@@ -1260,18 +1260,18 @@ static ssize_t cc3000_write(FAR struct file *filep, FAR const char *usrbuffer, s
     }
   else
     {
-      nllinfo("Assert CS\n");
+      ninfo("Assert CS\n");
       priv->state  = eSPI_STATE_WRITE_WAIT_IRQ;
       cc3000_lock_and_select(priv->spi); /* Assert CS */
-      nllinfo("Wait on IRQ Active\n");
+      ninfo("Wait on IRQ Active\n");
       ret = cc3000_wait_ready(priv);
-      nllinfo("IRQ Signaled\n");
+      ninfo("IRQ Signaled\n");
       if (ret < 0)
         {
           /* This should only happen if the wait was canceled by an signal */
 
           cc3000_deselect_and_unlock(priv->spi);
-          nllinfo("sem_wait: %d\n", errno);
+          ninfo("sem_wait: %d\n", errno);
           DEBUGASSERT(errno == EINTR);
           nwritten = ret;
           goto errout_without_sem;
@@ -1281,13 +1281,13 @@ static ssize_t cc3000_write(FAR struct file *filep, FAR const char *usrbuffer, s
     }
 
   priv->state  = eSPI_STATE_WRITE_DONE;
-  nllinfo("Deassert CS S:eSPI_STATE_WRITE_DONE\n");
+  ninfo("Deassert CS S:eSPI_STATE_WRITE_DONE\n");
   cc3000_deselect_and_unlock(priv->spi);
   nwritten = tx_len;
   cc3000_devgive(priv);
 
 errout_without_sem:
-  nllinfo("Returning: %d\n", ret);
+  ninfo("Returning: %d\n", ret);
   return nwritten;
 }
 
@@ -1301,7 +1301,7 @@ static int cc3000_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
   FAR struct cc3000_dev_s *priv;
   int ret;
 
-  nllinfo("cmd: %d arg: %ld\n", cmd, arg);
+  ninfo("cmd: %d arg: %ld\n", cmd, arg);
   DEBUGASSERT(filep);
   inode = filep->f_inode;
 
@@ -1406,7 +1406,7 @@ static int cc3000_poll(FAR struct file *filep, FAR struct pollfd *fds,
   int ret = OK;
   int i;
 
-  nllinfo("setup: %d\n", (int)setup);
+  ninfo("setup: %d\n", (int)setup);
   DEBUGASSERT(filep && fds);
   inode = filep->f_inode;
 
@@ -1514,7 +1514,7 @@ int cc3000_register(FAR struct spi_dev_s *spi,
 #endif
   int ret;
 
-  nllinfo("spi: %p minor: %d\n", spi, minor);
+  ninfo("spi: %p minor: %d\n", spi, minor);
 
   /* Debug-only sanity checks */
 
@@ -1569,7 +1569,7 @@ int cc3000_register(FAR struct spi_dev_s *spi,
   /* Register the device as an input device */
 
   (void)snprintf(drvname, DEV_NAMELEN, DEV_FORMAT, minor);
-  nllinfo("Registering %s\n", drvname);
+  ninfo("Registering %s\n", drvname);
 
   ret = register_driver(drvname, &cc3000_fops, 0666, priv);
   if (ret < 0)
diff --git a/drivers/wireless/cc3000/cc3000drv.c b/drivers/wireless/cc3000/cc3000drv.c
index 02e366dd3cc..ab114c0515a 100644
--- a/drivers/wireless/cc3000/cc3000drv.c
+++ b/drivers/wireless/cc3000/cc3000drv.c
@@ -98,7 +98,7 @@ void cc3000_resume(void)
 {
   DEBUGASSERT(spiconf.cc3000fd >= 0 && spiconf.done);
   sem_post(spiconf.done);
-  nllinfo("Done\n");
+  ninfo("Done\n");
 }
 
 /****************************************************************************
@@ -203,7 +203,7 @@ static void *unsoliced_thread_func(void *parameter)
                           sizeof(spiconf.rx_buffer), 0);
       if (nbytes > 0)
         {
-          nllinfo("%d Processed\n", nbytes);
+          ninfo("%d Processed\n", nbytes);
           spiconf.pfRxHandler(spiconf.rx_buffer.pbuffer);
         }
     }
diff --git a/drivers/wireless/cc3000/evnt_handler.c b/drivers/wireless/cc3000/evnt_handler.c
index 82d4943906b..b53fd24db37 100644
--- a/drivers/wireless/cc3000/evnt_handler.c
+++ b/drivers/wireless/cc3000/evnt_handler.c
@@ -924,12 +924,12 @@ void SimpleLinkWaitEvent(uint16_t opcode, void *pRetParams)
    */
 
   tSLInformation.usRxEventOpcode = opcode;
-  nllinfo("Looking for opcode 0x%x\n", opcode);
+  ninfo("Looking for opcode 0x%x\n", opcode);
   uint16_t event_type;
 
   do
     {
-      nllinfo("cc3000_wait\n");
+      ninfo("cc3000_wait\n");
       tSLInformation.pucReceivedData = cc3000_wait();
       tSLInformation.usEventOrDataReceived = 1;
       STREAM_TO_UINT16((FAR char *)tSLInformation.pucReceivedData,
@@ -937,25 +937,25 @@ void SimpleLinkWaitEvent(uint16_t opcode, void *pRetParams)
 
       if (*tSLInformation.pucReceivedData == HCI_TYPE_EVNT)
         {
-          nllinfo("Evtn:0x%x\n", event_type);
+          ninfo("Evtn:0x%x\n", event_type);
         }
 
       if (event_type != opcode)
         {
           if (hci_unsolicited_event_handler() == 1)
             {
-              nllinfo("Processed Event  0x%x want 0x%x\n", event_type, opcode);
+              ninfo("Processed Event  0x%x want 0x%x\n", event_type, opcode);
             }
         }
       else
         {
-          nllinfo("Processing opcode 0x%x\n", opcode);
+          ninfo("Processing opcode 0x%x\n", opcode);
           hci_event_handler(pRetParams, 0, 0);
         }
     }
   while (tSLInformation.usRxEventOpcode != 0);
 
-  nllinfo("Done for opcode 0x%x\n", opcode);
+  ninfo("Done for opcode 0x%x\n", opcode);
 }
 
 /****************************************************************************
@@ -981,7 +981,7 @@ void SimpleLinkWaitData(uint8_t *pBuf, uint8_t *from, uint8_t *fromlen)
    * after the end of current transaction, i.e. only after data will be received
    */
 
-  nllinfo("Looking for Data\n");
+  ninfo("Looking for Data\n");
   uint16_t event_type;
   uint16_t opcode = tSLInformation.usRxEventOpcode;
 
@@ -999,15 +999,15 @@ void SimpleLinkWaitData(uint8_t *pBuf, uint8_t *from, uint8_t *fromlen)
       else
         {
           STREAM_TO_UINT16((char *)tSLInformation.pucReceivedData, HCI_EVENT_OPCODE_OFFSET, event_type);
-          nllinfo("Evtn:0x%x\n", event_type);
+          ninfo("Evtn:0x%x\n", event_type);
 
           if (hci_unsolicited_event_handler() == 1)
             {
-              nllinfo("Processed Event  0x%x want Data! Opcode 0x%x\n", event_type, opcode);
+              ninfo("Processed Event  0x%x want Data! Opcode 0x%x\n", event_type, opcode);
             }
           else
             {
-              nllinfo("!!!!!opcode 0x%x\n", opcode);
+              ninfo("!!!!!opcode 0x%x\n", opcode);
             }
 
           UNUSED(event_type);
@@ -1015,6 +1015,6 @@ void SimpleLinkWaitData(uint8_t *pBuf, uint8_t *from, uint8_t *fromlen)
     }
   while (*tSLInformation.pucReceivedData == HCI_TYPE_EVNT);
 
-  nllinfo("Done for Data 0x%x\n", opcode);
+  ninfo("Done for Data 0x%x\n", opcode);
   UNUSED(opcode);
 }
diff --git a/drivers/wireless/cc3000/hci.c b/drivers/wireless/cc3000/hci.c
index 742f09bae7d..7555290640d 100644
--- a/drivers/wireless/cc3000/hci.c
+++ b/drivers/wireless/cc3000/hci.c
@@ -79,7 +79,7 @@ uint16_t hci_command_send(uint16_t usOpcode, uint8_t *pucBuff,
 
   stream = (pucBuff + SPI_HEADER_SIZE);
 
-  nllinfo("Send 0x%x\n", usOpcode);
+  ninfo("Send 0x%x\n", usOpcode);
   UINT8_TO_STREAM(stream, HCI_TYPE_CMND);
   stream = UINT16_TO_STREAM(stream, usOpcode);
   UINT8_TO_STREAM(stream, ucArgsLength);
@@ -87,7 +87,7 @@ uint16_t hci_command_send(uint16_t usOpcode, uint8_t *pucBuff,
   /* Update the opcode of the event we will be waiting for */
 
   cc3000_write(pucBuff, ucArgsLength + SIMPLE_LINK_HCI_CMND_HEADER_SIZE);
-  nllinfo("Send of 0x%x Completed\n", usOpcode);
+  ninfo("Send of 0x%x Completed\n", usOpcode);
 
   return 0;
 }
diff --git a/drivers/wireless/cc3000/socket.c b/drivers/wireless/cc3000/socket.c
index d8eea4ebd39..a1d238365c2 100644
--- a/drivers/wireless/cc3000/socket.c
+++ b/drivers/wireless/cc3000/socket.c
@@ -62,8 +62,8 @@
 #  define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
 #endif
 
-#define waitllerr(x,...) //  _llerr
-#define waitllinfo(x,...) // _llinfo
+#define waiterr(x,...) //  _err
+#define waitinfo(x,...) // _info
 
 /****************************************************************************
  * Private Types
@@ -195,13 +195,13 @@ int cc3000_closesocket(int sockfd)
   int ret;
 
 #ifdef CONFIG_CC3000_MT
-  waitllinfo("remove\n");
+  waitinfo("remove\n");
   cc3000_remove_socket(sockfd);
 #endif
   cc3000_lib_lock();
-  waitllinfo("Call closesocketl\n");
+  waitinfo("Call closesocketl\n");
   ret = cc3000_closesocket_impl(sockfd);
-  waitllinfo("return closesocket\n");
+  waitinfo("return closesocket\n");
   cc3000_lib_unlock();
   return ret;
 }
@@ -597,9 +597,9 @@ ssize_t cc3000_recv(int sockfd, FAR void *buf, size_t len, int flags)
   ssize_t ret;
 
 #ifdef CONFIG_CC3000_MT
-  waitllinfo("wait\n");
+  waitinfo("wait\n");
   ret = cc3000_wait_data(sockfd);
-  waitllinfo("wait %d\n", ret);
+  waitinfo("wait %d\n", ret);
 
   if (ret == -ECONNABORTED)
     {
@@ -613,9 +613,9 @@ ssize_t cc3000_recv(int sockfd, FAR void *buf, size_t len, int flags)
 #endif
 
   cc3000_lib_lock();
-  waitllinfo("recv\n");
+  waitinfo("recv\n");
   ret = cc3000_recv_impl(sockfd, buf, len, flags);
-  waitllinfo("recv %d\n", ret);
+  waitinfo("recv %d\n", ret);
   cc3000_lib_unlock();
   return ret;
 }
diff --git a/drivers/wireless/cc3000/wlan.c b/drivers/wireless/cc3000/wlan.c
index 3a5bd0f31d2..23d853a6819 100644
--- a/drivers/wireless/cc3000/wlan.c
+++ b/drivers/wireless/cc3000/wlan.c
@@ -261,7 +261,7 @@ void SpiReceiveHandler(void *pvBuffer)
   STREAM_TO_UINT16((char *)tSLInformation.pucReceivedData,
                    HCI_EVENT_OPCODE_OFFSET, event_type);
 
-  nllinfo("Evnt:0x%x\n", event_type);
+  ninfo("Evnt:0x%x\n", event_type);
   UNUSED(event_type);
 
   hci_unsolicited_event_handler();
diff --git a/drivers/wireless/ieee802154/mrf24j40.c b/drivers/wireless/ieee802154/mrf24j40.c
index efbbb8c7b28..77079fe468e 100644
--- a/drivers/wireless/ieee802154/mrf24j40.c
+++ b/drivers/wireless/ieee802154/mrf24j40.c
@@ -779,7 +779,7 @@ static int mrf24j40_settxpower(FAR struct ieee802154_dev_s *ieee,
       return -EINVAL;
     }
 
-  _llinfo("remaining attenuation: %d mBm\n",txpwr);
+  _info("remaining attenuation: %d mBm\n",txpwr);
 
   switch(txpwr/100)
     {
diff --git a/drivers/wireless/nrf24l01.c b/drivers/wireless/nrf24l01.c
index 4010efd0fef..ff79034ad68 100644
--- a/drivers/wireless/nrf24l01.c
+++ b/drivers/wireless/nrf24l01.c
@@ -495,7 +495,7 @@ static int nrf24l01_irqhandler(int irq, FAR void *context)
 {
   FAR struct nrf24l01_dev_s *dev = g_nrf24l01dev;
 
-  wllinfo("*IRQ*");
+  winfo("*IRQ*");
 
 #ifdef CONFIG_WL_NRF24L01_RXSUPPORT
 
diff --git a/fs/Kconfig b/fs/Kconfig
index fe436402b3a..603d9a51152 100644
--- a/fs/Kconfig
+++ b/fs/Kconfig
@@ -74,45 +74,3 @@ source fs/binfs/Kconfig
 source fs/procfs/Kconfig
 source fs/unionfs/Kconfig
 source fs/hostfs/Kconfig
-
-comment "System Logging"
-
-config SYSLOG
-	bool "Advanced SYSLOG features"
-	default n
-	---help---
-		Enables generic system logging features.  NOTE: This setting is not
-		required to enable system logging.  If this feature is not enable
-		system logging will still be available and will log to the system
-		console (like printf()).  This setting is required to enable
-		customization of the basic system loggin capability.
-
-config SYSLOG_TIMESTAMP
-	bool "Prepend timestamp to syslog message"
-	default n
-	---help---
-		Prepend timestamp to syslog message.
-
-if SYSLOG
-
-config SYSLOG_CHAR
-	bool "System log character device support"
-	default y
-	---help---
-		Enable the generic character device for the SYSLOG. The full path to the
-		SYSLOG device is provided by SYSLOG_DEVPATH. A valid character device (or
-		file) must exist at this path.  It will by opened by syslog_initialize.
-
-		Do not enable more than one SYSLOG device.
-
-config SYSLOG_DEVPATH
-	string "System log device"
-	default "/dev/syslog"
-	depends on SYSLOG_CHAR
-	---help---
-		The full path to the system logging device.  For the RAMLOG SYSLOG device,
-		this is normally "/dev/ramlog".  For character SYSLOG devices, it should be
-		some other existing character device (or file) supported by the configuration
-		(such as "/dev/ttyS1")/
-
-endif
diff --git a/fs/driver/Make.defs b/fs/driver/Make.defs
index e280ea1580a..739e2e16f14 100644
--- a/fs/driver/Make.defs
+++ b/fs/driver/Make.defs
@@ -50,14 +50,6 @@ CSRCS += fs_blockproxy.c
 endif
 endif
 
-# System logging to a character device (or file)
-
-ifeq ($(CONFIG_SYSLOG),y)
-ifeq ($(CONFIG_SYSLOG_CHAR),y)
-CSRCS += fs_devsyslog.c
-endif
-endif
-
 # Include driver build support
 
 DEPPATH += --dep-path driver
diff --git a/fs/inode/fs_filedetach.c b/fs/inode/fs_filedetach.c
index 8b13250cbc1..b865e03b4a1 100644
--- a/fs/inode/fs_filedetach.c
+++ b/fs/inode/fs_filedetach.c
@@ -84,7 +84,7 @@ static inline void _files_semtake(FAR struct filelist *list)
  * Name: file_detach
  *
  * Description:
- *   This function is used to device drivers to create a task-independent
+ *   This function is used in device drivers to create a task-independent
  *   handle to an entity in the file system.  file_detach() duplicates the
  *   'struct file' that underlies the file descriptor, then closes the file
  *   descriptor.
diff --git a/fs/mount/fs_automount.c b/fs/mount/fs_automount.c
index f67f43573cb..1bee61d7f5a 100644
--- a/fs/mount/fs_automount.c
+++ b/fs/mount/fs_automount.c
@@ -315,7 +315,7 @@ static int automount_unmount(FAR struct automounter_state_s *priv)
 
           else
             {
-              finfo("ERROR: umount2 failed: %d\n", errcode);
+              ferr("ERROR: umount2 failed: %d\n", errcode);
               return -errcode;
             }
         }
@@ -363,7 +363,7 @@ static void automount_timeout(int argc, uint32_t arg1, ...)
     (FAR struct automounter_state_s *)((uintptr_t)arg1);
   int ret;
 
-  fllinfo("Timeout!\n");
+  finfo("Timeout!\n");
   DEBUGASSERT(argc == 1 && priv);
 
   /* Check the state of things.  This timeout at the interrupt level and
@@ -372,7 +372,7 @@ static void automount_timeout(int argc, uint32_t arg1, ...)
    * there should be no pending work.
    */
 
-  fllinfo("inserted=%d\n", priv->inserted);
+  finfo("inserted=%d\n", priv->inserted);
   DEBUGASSERT(!priv->inserted && work_available(&priv->work));
 
   /* Queue work to occur immediately. */
@@ -463,7 +463,7 @@ static int automount_interrupt(FAR const struct automount_lower_s *lower,
 
   DEBUGASSERT(lower && priv && priv->lower == lower);
 
-  fllinfo("inserted=%d\n", inserted);
+  finfo("inserted=%d\n", inserted);
 
   /* Cancel any pending work.  We could get called multiple times if, for
    * example there is bounce in the detection mechanism.  Work is performed
diff --git a/graphics/vnc/server/vnc_fbdev.c b/graphics/vnc/server/vnc_fbdev.c
index 2e56d53e8ef..54abc1dc5c3 100644
--- a/graphics/vnc/server/vnc_fbdev.c
+++ b/graphics/vnc/server/vnc_fbdev.c
@@ -635,7 +635,7 @@ int up_fbinitialize(int display)
   ret = vnc_start_server(display);
   if (ret < 0)
     {
-      ginfo("ERROR: vnc_start_server() failed: %d\n", ret);
+      gerr("ERROR: vnc_start_server() failed: %d\n", ret);
       return ret;
     }
 
@@ -644,7 +644,7 @@ int up_fbinitialize(int display)
   ret = vnc_wait_connect(display);
   if (ret < 0)
     {
-      ginfo("ERROR: vnc_wait_connect() failed: %d\n", ret);
+      gerr("ERROR: vnc_wait_connect() failed: %d\n", ret);
     }
 
   return ret;
@@ -716,7 +716,7 @@ int vnc_fbinitialize(int display, vnc_kbdout_t kbdout,
   ret = vnc_start_server(display);
   if (ret < 0)
     {
-      ginfo("ERROR: vnc_start_server() failed: %d\n", ret);
+      gerr("ERROR: vnc_start_server() failed: %d\n", ret);
       return ret;
     }
 
@@ -725,7 +725,7 @@ int vnc_fbinitialize(int display, vnc_kbdout_t kbdout,
   ret = vnc_wait_start(display);
   if (ret < 0)
     {
-      ginfo("ERROR: vnc_wait_start() failed: %d\n", ret);
+      gerr("ERROR: vnc_wait_start() failed: %d\n", ret);
       return ret;
     }
 
diff --git a/graphics/vnc/server/vnc_server.c b/graphics/vnc/server/vnc_server.c
index 7c4aa84ad32..513d10c7367 100644
--- a/graphics/vnc/server/vnc_server.c
+++ b/graphics/vnc/server/vnc_server.c
@@ -248,17 +248,25 @@ int vnc_server(int argc, FAR char *argv[])
 
   if (argc != 2)
     {
+      /* In this case the start-up logic will probably hang, waiting for the
+       * display-related semaphore to be set.
+       */
+
       gerr("ERROR: Unexpected number of arguments: %d\n", argc);
       ret = -EINVAL;
-      goto errout_with_post;
+      goto errout_with_hang;
     }
 
   display = atoi(argv[1]);
   if (display < 0 || display >= RFB_MAX_DISPLAYS)
     {
+      /* In this case the start-up logic will probably hang, waiting for the
+       * display-related semaphore to be set.
+       */
+
       gerr("ERROR: Invalid display number: %d\n", display);
       ret = -EINVAL;
-      goto errout_with_post;
+      goto errout_with_hang;
     }
 
   ginfo("Server started for Display %d\n", display);
@@ -373,5 +381,7 @@ errout_with_fb:
 errout_with_post:
   g_fbstartup[display].result = ret;
   sem_post(&g_fbstartup[display].fbconnect);
+
+errout_with_hang:
   return EXIT_FAILURE;
 }
diff --git a/graphics/vnc/server/vnc_server.h b/graphics/vnc/server/vnc_server.h
index fc1e398fc42..b513861fe85 100644
--- a/graphics/vnc/server/vnc_server.h
+++ b/graphics/vnc/server/vnc_server.h
@@ -187,34 +187,22 @@
 #ifdef CONFIG_VNCSERVER_UPDATE_DEBUG
 #  ifdef CONFIG_CPP_HAVE_VARARGS
 #    define upderr(format, ...)    _err(format, ##__VA_ARGS__)
-#    define updllerr(format, ...)  _llerr(format, ##__VA_ARGS__)
 #    define updinfo(format, ...)   _info(format, ##__VA_ARGS__)
-#    define updllinfo(format, ...) _llinfo(format, ##__VA_ARGS__)
 #    define updinfo(format, ...)   _info(format, ##__VA_ARGS__)
-#    define updllinfo(format, ...) _llinfo(format, ##__VA_ARGS__)
 #  else
 #   define upderr                  _err
-#   define updllerr                _llerr
 #   define updwarn                 _warn
-#   define updllwarn               _llwarn
 #   define updinfo                 _info
-#   define updllinfo               _llinfo
 #  endif
 #else
 #  ifdef CONFIG_CPP_HAVE_VARARGS
 #    define upderr(x...)
-#    define updllerr(x...)
 #    define updwarn(x...)
-#    define updllwarn(x...)
 #    define updinfo(x...)
-#    define updllinfo(x...)
 #  else
 #    define upderr                 (void)
-#    define updllerr               (void)
 #    define updwarn                (void)
-#    define updllwarn              (void)
 #    define updinfo                (void)
-#    define updllinfo              (void)
 #  endif
 #endif
 
diff --git a/include/assert.h b/include/assert.h
index 847146494a0..88254f64945 100644
--- a/include/assert.h
+++ b/include/assert.h
@@ -89,6 +89,14 @@
 #  define assert(f) ASSERT(f)
 #endif
 
+/* Definition required for C11 compile-time assertion checking.  The
+ * static_assert macro simply expands to the _Static_assert keyword.
+ */
+
+#ifndef __cplusplus
+#  define static_assert _Static_assert
+#endif
+
 /****************************************************************************
  * Included Files
  ****************************************************************************/
diff --git a/include/debug.h b/include/debug.h
index 9994b3a4217..c2fc93dd53f 100644
--- a/include/debug.h
+++ b/include/debug.h
@@ -85,27 +85,6 @@
  *    information that you probably not want to suppress during normal debug
  *    general debugging.
  *
- * [a-z]llinfo() -- Identical to [a-z]err() except this is uses special
- *    interfaces provided by architecture-specific logic to talk directly
- *    to the underlying console hardware.  If the architecture provides such
- *    logic, it should define CONFIG_ARCH_LOWPUTC.
- *
- *    [a-z]llinfo() should not be used in normal code because the implementation
- *    probably disables interrupts and does things that are not consistent with
- *    good real-time performance.  However, [a-z]llinfo() is particularly useful
- *    in low-level code where it is inappropriate to use file descriptors.  For
- *    example, only [a-z]llinfo() should be used in interrupt handlers.
- *
- * [a-z]llwarn() -- Identical to [a-z]llinfo() except that it also requires that
- *    CONFIG_DEBUG_WARN be defined.  This is intended for important exception
- *    conditions that are potential errors (or perhaps real errors with non-
- *    fatal consequences).
- *
- * [a-z]llerr() -- Identical to [a-z]llinfo() except that it also requires that
- *    CONFIG_DEBUG_ERROR be defined. This is intended for important error-related
- *    information that you probably not want to suppress during normal debug
- *    general debugging.
- *
  * _alert() - is a special, high-priority, unconditional version that is really
  *    intended only for crash error reporting.
  */
@@ -133,1491 +112,1101 @@
 #ifndef __arch_syslog
 #  define __arch_syslog syslog
 #endif
-#ifndef __arch_lowsyslog
-#  define __arch_lowsyslog lowsyslog
-#endif
 
-#ifdef CONFIG_ARCH_LOWPUTC
+#ifdef CONFIG_DEBUG_ALERT
 #  define _alert(format, ...) \
-   __arch_lowsyslog(LOG_EMERG, EXTRA_FMT format EXTRA_ARG, ##__VA_ARGS__)
-# else
-#  define _alert(x...)
-# endif
+   __arch_syslog(LOG_EMERG, EXTRA_FMT format EXTRA_ARG, ##__VA_ARGS__)
+#else /* CONFIG_DEBUG_ERROR */
+#  define  _alert(x...)
+#endif
 
 #ifdef CONFIG_DEBUG_ERROR
 #  define  _err(format, ...) \
    __arch_syslog(LOG_ERR, EXTRA_FMT format EXTRA_ARG, ##__VA_ARGS__)
-
-# ifdef CONFIG_ARCH_LOWPUTC
-#  define  _llerr(format, ...) \
-   __arch_lowsyslog(LOG_ERR, EXTRA_FMT format EXTRA_ARG, ##__VA_ARGS__)
-# else
-#  define  _llerr(x...)
-# endif
-#else /* CONFIG_DEBUG_ERROR */
+#else
 #  define  _err(x...)
-#  define  _llerr(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_WARN
 #  define _warn(format, ...) \
    __arch_syslog(LOG_WARNING, EXTRA_FMT format EXTRA_ARG, ##__VA_ARGS__)
-
-#  ifdef CONFIG_ARCH_LOWPUTC
-#    define _llwarn(format, ...) \
-     __arch_lowsyslog(LOG_WARNING, EXTRA_FMT format EXTRA_ARG, ##__VA_ARGS__)
-#  else
-#    define _llwarn(x...)
-#  endif
-#else /* CONFIG_DEBUG_INFO */
+#else
 #  define _warn(x...)
-#  define _llwarn(x...)
-#endif /* CONFIG_DEBUG_INFO */
+#endif
 
 #ifdef CONFIG_DEBUG_INFO
 #  define _info(format, ...) \
    __arch_syslog(LOG_INFO, EXTRA_FMT format EXTRA_ARG, ##__VA_ARGS__)
-
-#  ifdef CONFIG_ARCH_LOWPUTC
-#    define _llinfo(format, ...) \
-     __arch_lowsyslog(LOG_INFO, EXTRA_FMT format EXTRA_ARG, ##__VA_ARGS__)
-#  else
-#    define _llinfo(x...)
-#  endif
-#else /* CONFIG_DEBUG_INFO */
+#else
 #  define _info(x...)
-#  define _llinfo(x...)
-#endif /* CONFIG_DEBUG_INFO */
+#endif
 
 /* Subsystem specific debug */
 
 #ifdef CONFIG_DEBUG_MM_ERROR
 #  define merr(format, ...)     _err(format, ##__VA_ARGS__)
-#  define mllerr(format, ...)   _llerr(format, ##__VA_ARGS__)
 #else
 #  define merr(x...)
-#  define mllerr(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_MM_WARN
 #  define mwarn(format, ...)   _warn(format, ##__VA_ARGS__)
-#  define mllwarn(format, ...) _llwarn(format, ##__VA_ARGS__)
 #else
 #  define mwarn(x...)
-#  define mllwarn(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_MM_INFO
 #  define minfo(format, ...)   _info(format, ##__VA_ARGS__)
-#  define mllinfo(format, ...) _llinfo(format, ##__VA_ARGS__)
 #else
 #  define minfo(x...)
-#  define mllinfo(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_SCHED_ERROR
 #  define serr(format, ...)     _err(format, ##__VA_ARGS__)
-#  define sllerr(format, ...)   _llerr(format, ##__VA_ARGS__)
 #else
 #  define serr(x...)
-#  define sllerr(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_SCHED_WARN
 #  define swarn(format, ...)   _warn(format, ##__VA_ARGS__)
-#  define sllwarn(format, ...) _llwarn(format, ##__VA_ARGS__)
 #else
 #  define swarn(x...)
-#  define sllwarn(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_SCHED_INFO
 #  define sinfo(format, ...)   _info(format, ##__VA_ARGS__)
-#  define sllinfo(format, ...) _llinfo(format, ##__VA_ARGS__)
 #else
 #  define sinfo(x...)
-#  define sllinfo(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_SYSCALL_ERROR
 #  define svcerr(format, ...)     _err(format, ##__VA_ARGS__)
-#  define svcllerr(format, ...)   _llerr(format, ##__VA_ARGS__)
 #else
 #  define svcerr(x...)
-#  define svcllerr(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_SYSCALL_WARN
 #  define svcwarn(format, ...)   _warn(format, ##__VA_ARGS__)
-#  define svcllwarn(format, ...) _llwarn(format, ##__VA_ARGS__)
 #else
 #  define svcwarn(x...)
-#  define svcllwarn(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_SYSCALL_INFO
 #  define svcinfo(format, ...)   _info(format, ##__VA_ARGS__)
-#  define svcllinfo(format, ...) _llinfo(format, ##__VA_ARGS__)
 #else
 #  define svcinfo(x...)
-#  define svcllinfo(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_PAGING_ERROR
 #  define pgerr(format, ...)     _err(format, ##__VA_ARGS__)
-#  define pgllerr(format, ...)   _llerr(format, ##__VA_ARGS__)
 #else
 #  define pgerr(x...)
-#  define pgllerr(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_PAGING_WARN
 #  define pgwarn(format, ...)   _warn(format, ##__VA_ARGS__)
-#  define pgllwarn(format, ...) _llwarn(format, ##__VA_ARGS__)
 #else
 #  define pgwarn(x...)
-#  define pgllwarn(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_PAGING_INFO
 #  define pginfo(format, ...)   _info(format, ##__VA_ARGS__)
-#  define pgllinfo(format, ...) _llinfo(format, ##__VA_ARGS__)
 #else
-#  define pgerr(x...)
-#  define pgllerr(x...)
+#  define pginfo(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_NET_ERROR
 #  define nerr(format, ...)     _err(format, ##__VA_ARGS__)
-#  define nllerr(format, ...)   _llerr(format, ##__VA_ARGS__)
 #else
 #  define nerr(x...)
-#  define nllerr(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_NET_WARN
 #  define nwarn(format, ...)   _warn(format, ##__VA_ARGS__)
-#  define nllwarn(format, ...) _llwarn(format, ##__VA_ARGS__)
 #else
 #  define nwarn(x...)
-#  define nllwarn(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_NET_INFO
 #  define ninfo(format, ...)   _info(format, ##__VA_ARGS__)
-#  define nllinfo(format, ...) _llinfo(format, ##__VA_ARGS__)
 #else
 #  define ninfo(x...)
-#  define nllinfo(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_FS_ERROR
 #  define ferr(format, ...)     _err(format, ##__VA_ARGS__)
-#  define fllerr(format, ...)   _llerr(format, ##__VA_ARGS__)
 #else
 #  define ferr(x...)
-#  define fllerr(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_FS_WARN
 #  define fwarn(format, ...)   _warn(format, ##__VA_ARGS__)
-#  define fllwarn(format, ...) _llwarn(format, ##__VA_ARGS__)
 #else
 #  define fwarn(x...)
-#  define fllwarn(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_FS_INFO
 #  define finfo(format, ...)   _info(format, ##__VA_ARGS__)
-#  define fllinfo(format, ...) _llinfo(format, ##__VA_ARGS__)
 #else
 #  define finfo(x...)
-#  define fllinfo(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_CRYPTO_ERROR
 #  define crypterr(format, ...)     _err(format, ##__VA_ARGS__)
-#  define cryptllerr(format, ...)   _llerr(format, ##__VA_ARGS__)
 #else
 #  define crypterr(x...)
-#  define cryptllerr(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_CRYPTO_WARN
 #  define cryptwarn(format, ...)   _warn(format, ##__VA_ARGS__)
-#  define cryptllwarn(format, ...) _llwarn(format, ##__VA_ARGS__)
 #else
 #  define cryptwarn(x...)
-#  define cryptllwarn(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_CRYPTO_INFO
 #  define cryptinfo(format, ...)   _info(format, ##__VA_ARGS__)
-#  define cryptllinfo(format, ...) _llinfo(format, ##__VA_ARGS__)
 #else
 #  define cryptinfo(x...)
-#  define cryptllinfo(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_INPUT_ERROR
 #  define ierr(format, ...)     _err(format, ##__VA_ARGS__)
-#  define illerr(format, ...)   _llerr(format, ##__VA_ARGS__)
 #else
 #  define ierr(x...)
-#  define illerr(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_INPUT_WARN
 #  define iwarn(format, ...)   _warn(format, ##__VA_ARGS__)
-#  define illwarn(format, ...) _llwarn(format, ##__VA_ARGS__)
 #else
 #  define iwarn(x...)
-#  define illwarn(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_INPUT_INFO
 #  define iinfo(format, ...)   _info(format, ##__VA_ARGS__)
-#  define illinfo(format, ...) _llinfo(format, ##__VA_ARGS__)
 #else
 #  define iinfo(x...)
-#  define illinfo(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_ANALOG_ERROR
 #  define aerr(format, ...)     _err(format, ##__VA_ARGS__)
-#  define allerr(format, ...)   _llerr(format, ##__VA_ARGS__)
 #else
 #  define aerr(x...)
-#  define allerr(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_ANALOG_WARN
 #  define awarn(format, ...)   _warn(format, ##__VA_ARGS__)
-#  define allwarn(format, ...) _llwarn(format, ##__VA_ARGS__)
 #else
 #  define awarn(x...)
-#  define allwarn(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_ANALOG_INFO
 #  define ainfo(format, ...)   _info(format, ##__VA_ARGS__)
-#  define allinfo(format, ...) _llinfo(format, ##__VA_ARGS__)
 #else
 #  define ainfo(x...)
-#  define allinfo(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_CAN_ERROR
 #  define canerr(format, ...)     _err(format, ##__VA_ARGS__)
-#  define canllerr(format, ...)   _llerr(format, ##__VA_ARGS__)
 #else
 #  define canerr(x...)
-#  define canllerr(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_CAN_WARN
 #  define canwarn(format, ...)   _warn(format, ##__VA_ARGS__)
-#  define canllwarn(format, ...) _llwarn(format, ##__VA_ARGS__)
 #else
 #  define canwarn(x...)
-#  define canllwarn(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_CAN_INFO
 #  define caninfo(format, ...)   _info(format, ##__VA_ARGS__)
-#  define canllinfo(format, ...) _llinfo(format, ##__VA_ARGS__)
 #else
 #  define caninfo(x...)
-#  define canllinfo(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_GRAPHICS_ERROR
 #  define gerr(format, ...)     _err(format, ##__VA_ARGS__)
-#  define gllerr(format, ...)   _llerr(format, ##__VA_ARGS__)
 #else
 #  define gerr(x...)
-#  define gllerr(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_GRAPHICS_WARN
 #  define gwarn(format, ...)   _warn(format, ##__VA_ARGS__)
-#  define gllwarn(format, ...) _llwarn(format, ##__VA_ARGS__)
 #else
 #  define gwarn(x...)
-#  define gllwarn(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_GRAPHICS_INFO
 #  define ginfo(format, ...)   _info(format, ##__VA_ARGS__)
-#  define gllinfo(format, ...) _llinfo(format, ##__VA_ARGS__)
 #else
 #  define ginfo(x...)
-#  define gllinfo(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_BINFMT_ERROR
 #  define berr(format, ...)     _err(format, ##__VA_ARGS__)
-#  define bllerr(format, ...)   _llerr(format, ##__VA_ARGS__)
 #else
 #  define berr(x...)
-#  define bllerr(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_BINFMT_WARN
 #  define bwarn(format, ...)   _warn(format, ##__VA_ARGS__)
-#  define bllwarn(format, ...) _llwarn(format, ##__VA_ARGS__)
 #else
 #  define bwarn(x...)
-#  define bllwarn(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_BINFMT_INFO
 #  define binfo(format, ...)   _info(format, ##__VA_ARGS__)
-#  define bllinfo(format, ...) _llinfo(format, ##__VA_ARGS__)
 #else
 #  define binfo(x...)
-#  define bllinfo(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_LIB_ERROR
 #  define lerr(format, ...)     _err(format, ##__VA_ARGS__)
-#  define lllerr(format, ...)   _llerr(format, ##__VA_ARGS__)
 #else
 #  define lerr(x...)
-#  define lllerr(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_LIB_WARN
 #  define lwarn(format, ...)   _warn(format, ##__VA_ARGS__)
-#  define lllwarn(format, ...) _llwarn(format, ##__VA_ARGS__)
 #else
 #  define lwarn(x...)
-#  define lllwarn(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_LIB_INFO
 #  define linfo(format, ...)   _info(format, ##__VA_ARGS__)
-#  define lllinfo(format, ...) _llinfo(format, ##__VA_ARGS__)
 #else
 #  define linfo(x...)
-#  define lllinfo(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_AUDIO_ERROR
 #  define auderr(format, ...)     _err(format, ##__VA_ARGS__)
-#  define audllerr(format, ...)   _llerr(format, ##__VA_ARGS__)
 #else
 #  define auderr(x...)
-#  define audllerr(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_AUDIO_WARN
 #  define audwarn(format, ...)   _warn(format, ##__VA_ARGS__)
-#  define audllwarn(format, ...) _llwarn(format, ##__VA_ARGS__)
 #else
 #  define audwarn(x...)
-#  define audllwarn(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_AUDIO_INFO
 #  define audinfo(format, ...)   _info(format, ##__VA_ARGS__)
-#  define audllinfo(format, ...) _llinfo(format, ##__VA_ARGS__)
 #else
 #  define audinfo(x...)
-#  define audllinfo(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_DMA_ERROR
 #  define dmaerr(format, ...)     _err(format, ##__VA_ARGS__)
-#  define dmallerr(format, ...)   _llerr(format, ##__VA_ARGS__)
 #else
 #  define dmaerr(x...)
-#  define dmallerr(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_DMA_WARN
 #  define dmawarn(format, ...)   _warn(format, ##__VA_ARGS__)
-#  define dmallwarn(format, ...) _llwarn(format, ##__VA_ARGS__)
 #else
 #  define dmawarn(x...)
-#  define dmallwarn(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_DMA_INFO
 #  define dmainfo(format, ...)   _info(format, ##__VA_ARGS__)
-#  define dmallinfo(format, ...) _llinfo(format, ##__VA_ARGS__)
 #else
 #  define dmainfo(x...)
-#  define dmallinfo(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_IRQ_ERROR
 #  define irqerr(format, ...)     _err(format, ##__VA_ARGS__)
-#  define irqllerr(format, ...)   _llerr(format, ##__VA_ARGS__)
 #else
 #  define irqerr(x...)
-#  define irqllerr(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_IRQ_WARN
 #  define irqwarn(format, ...)   _warn(format, ##__VA_ARGS__)
-#  define irqllwarn(format, ...) _llwarn(format, ##__VA_ARGS__)
 #else
 #  define irqwarn(x...)
-#  define irqllwarn(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_IRQ_INFO
 #  define irqinfo(format, ...)   _info(format, ##__VA_ARGS__)
-#  define irqllinfo(format, ...) _llinfo(format, ##__VA_ARGS__)
 #else
 #  define irqinfo(x...)
-#  define irqllinfo(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_LCD_ERROR
 #  define lcderr(format, ...)     _err(format, ##__VA_ARGS__)
-#  define lcdllerr(format, ...)   _llerr(format, ##__VA_ARGS__)
 #else
 #  define lcderr(x...)
-#  define lcdllerr(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_LCD_WARN
 #  define lcdwarn(format, ...)   _warn(format, ##__VA_ARGS__)
-#  define lcdllwarn(format, ...) _llwarn(format, ##__VA_ARGS__)
 #else
 #  define lcdwarn(x...)
-#  define lcdllwarn(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_LCD_INFO
 #  define lcdinfo(format, ...)   _info(format, ##__VA_ARGS__)
-#  define lcdllinfo(format, ...) _llinfo(format, ##__VA_ARGS__)
 #else
 #  define lcdinfo(x...)
-#  define lcdllinfo(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_LEDS_ERROR
 #  define lederr(format, ...)     _err(format, ##__VA_ARGS__)
-#  define ledllerr(format, ...)   _llerr(format, ##__VA_ARGS__)
 #else
 #  define lederr(x...)
-#  define ledllerr(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_LEDS_WARN
 #  define ledwarn(format, ...)   _warn(format, ##__VA_ARGS__)
-#  define ledllwarn(format, ...) _llwarn(format, ##__VA_ARGS__)
 #else
 #  define ledwarn(x...)
-#  define ledllwarn(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_LEDS_INFO
 #  define ledinfo(format, ...)   _info(format, ##__VA_ARGS__)
-#  define ledllinfo(format, ...) _llinfo(format, ##__VA_ARGS__)
 #else
 #  define ledinfo(x...)
-#  define ledllinfo(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_GPIO_ERROR
 #  define gpioerr(format, ...)    _err(format, ##__VA_ARGS__)
-#  define gpiollerr(format, ...)  _llerr(format, ##__VA_ARGS__)
 #else
 #  define gpioerr(x...)
-#  define gpiollerr(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_GPIO_WARN
 #  define gpiowarn(format, ...)   _warn(format, ##__VA_ARGS__)
-#  define gpiollwarn(format, ...) _llwarn(format, ##__VA_ARGS__)
 #else
 #  define gpiowarn(x...)
-#  define gpiollwarn(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_GPIO_INFO
 #  define gpioinfo(format, ...)   _info(format, ##__VA_ARGS__)
-#  define gpiollinfo(format, ...) _llinfo(format, ##__VA_ARGS__)
 #else
 #  define gpioinfo(x...)
-#  define gpiollinfo(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_I2C_ERROR
 #  define i2cerr(format, ...)    _err(format, ##__VA_ARGS__)
-#  define i2cllerr(format, ...)  _llerr(format, ##__VA_ARGS__)
 #else
 #  define i2cerr(x...)
-#  define i2cllerr(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_I2C_WARN
 #  define i2cwarn(format, ...)   _warn(format, ##__VA_ARGS__)
-#  define i2cllwarn(format, ...) _llwarn(format, ##__VA_ARGS__)
 #else
 #  define i2cwarn(x...)
-#  define i2cllwarn(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_I2C_INFO
 #  define i2cinfo(format, ...)   _info(format, ##__VA_ARGS__)
-#  define i2cllinfo(format, ...) _llinfo(format, ##__VA_ARGS__)
 #else
 #  define i2cinfo(x...)
-#  define i2cllinfo(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_I2S_ERROR
 #  define i2serr(format, ...)    _err(format, ##__VA_ARGS__)
-#  define i2sllerr(format, ...)  _llerr(format, ##__VA_ARGS__)
 #else
 #  define i2serr(x...)
-#  define i2sllerr(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_I2S_WARN
 #  define i2swarn(format, ...)   _warn(format, ##__VA_ARGS__)
-#  define i2sllwarn(format, ...) _llwarn(format, ##__VA_ARGS__)
 #else
 #  define i2swarn(x...)
-#  define i2sllwarn(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_I2S_INFO
 #  define i2sinfo(format, ...)   _info(format, ##__VA_ARGS__)
-#  define i2sllinfo(format, ...) _llinfo(format, ##__VA_ARGS__)
 #else
 #  define i2sinfo(x...)
-#  define i2sllinfo(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_PWM_ERROR
 #  define pwmerr(format, ...)    _err(format, ##__VA_ARGS__)
-#  define pwmllerr(format, ...)  _llerr(format, ##__VA_ARGS__)
 #else
 #  define pwmerr(x...)
-#  define pwmllerr(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_PWM_WARN
 #  define pwmwarn(format, ...)   _warn(format, ##__VA_ARGS__)
-#  define pwmllwarn(format, ...) _llwarn(format, ##__VA_ARGS__)
 #else
 #  define pwmwarn(x...)
-#  define pwmllwarn(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_PWM_INFO
 #  define pwminfo(format, ...)   _info(format, ##__VA_ARGS__)
-#  define pwmllinfo(format, ...) _llinfo(format, ##__VA_ARGS__)
 #else
 #  define pwminfo(x...)
-#  define pwmllinfo(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_RTC_ERROR
 #  define rtcerr(format, ...)    _err(format, ##__VA_ARGS__)
-#  define rtcllerr(format, ...)  _llerr(format, ##__VA_ARGS__)
 #else
 #  define rtcerr(x...)
-#  define rtcllerr(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_RTC_WARN
 #  define rtcwarn(format, ...)   _warn(format, ##__VA_ARGS__)
-#  define rtcllwarn(format, ...) _llwarn(format, ##__VA_ARGS__)
 #else
 #  define rtcwarn(x...)
-#  define rtcllwarn(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_RTC_INFO
 #  define rtcinfo(format, ...)   _info(format, ##__VA_ARGS__)
-#  define rtcllinfo(format, ...) _llinfo(format, ##__VA_ARGS__)
 #else
 #  define rtcinfo(x...)
-#  define rtcllinfo(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_MEMCARD_ERROR
 #  define mcerr(format, ...)    _err(format, ##__VA_ARGS__)
-#  define mcllerr(format, ...)  _llerr(format, ##__VA_ARGS__)
 #else
 #  define mcerr(x...)
-#  define mcllerr(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_MEMCARD_WARN
 #  define mcwarn(format, ...)   _warn(format, ##__VA_ARGS__)
-#  define mcllwarn(format, ...) _llwarn(format, ##__VA_ARGS__)
 #else
 #  define mcwarn(x...)
-#  define mcllwarn(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_MEMCARD_INFO
 #  define mcinfo(format, ...)   _info(format, ##__VA_ARGS__)
-#  define mcllinfo(format, ...) _llinfo(format, ##__VA_ARGS__)
 #else
 #  define mcinfo(x...)
-#  define mcllinfo(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_SENSORS_ERROR
 #  define snerr(format, ...)     _err(format, ##__VA_ARGS__)
-#  define snllerr(format, ...)   _llerr(format, ##__VA_ARGS__)
 #else
 #  define snerr(x...)
-#  define snllerr(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_SENSORS_WARN
 #  define snwarn(format, ...)   _warn(format, ##__VA_ARGS__)
-#  define snllwarn(format, ...) _llwarn(format, ##__VA_ARGS__)
 #else
 #  define snwarn(x...)
-#  define snllwarn(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_SENSORS_INFO
 #  define sninfo(format, ...)   _info(format, ##__VA_ARGS__)
-#  define snllinfo(format, ...) _llinfo(format, ##__VA_ARGS__)
 #else
 #  define sninfo(x...)
-#  define snllinfo(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_SPI_ERROR
 #  define spierr(format, ...)     _err(format, ##__VA_ARGS__)
-#  define spillerr(format, ...)   _llerr(format, ##__VA_ARGS__)
 #else
 #  define spierr(x...)
-#  define spillerr(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_SPI_WARN
 #  define spiwarn(format, ...)   _warn(format, ##__VA_ARGS__)
-#  define spillwarn(format, ...) _llwarn(format, ##__VA_ARGS__)
 #else
 #  define spiwarn(x...)
-#  define spillwarn(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_SPI_INFO
 #  define spiinfo(format, ...)   _info(format, ##__VA_ARGS__)
-#  define spillinfo(format, ...) _llinfo(format, ##__VA_ARGS__)
 #else
 #  define spiinfo(x...)
-#  define spillinfo(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_TIMER_ERROR
 #  define tmrerr(format, ...)     _err(format, ##__VA_ARGS__)
-#  define tmrllerr(format, ...)   _llerr(format, ##__VA_ARGS__)
 #else
 #  define tmrerr(x...)
-#  define tmrllerr(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_TIMER_WARN
 #  define tmrwarn(format, ...)   _warn(format, ##__VA_ARGS__)
-#  define tmrllwarn(format, ...) _llwarn(format, ##__VA_ARGS__)
 #else
 #  define tmrwarn(x...)
-#  define tmrllwarn(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_TIMER_INFO
 #  define tmrinfo(format, ...)   _info(format, ##__VA_ARGS__)
-#  define tmrllinfo(format, ...) _llinfo(format, ##__VA_ARGS__)
 #else
 #  define tmrinfo(x...)
-#  define tmrllinfo(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_USB_ERROR
 #  define uerr(format, ...)     _err(format, ##__VA_ARGS__)
-#  define ullerr(format, ...)   _llerr(format, ##__VA_ARGS__)
 #else
 #  define uerr(x...)
-#  define ullerr(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_USB_WARN
 #  define uwarn(format, ...)   _warn(format, ##__VA_ARGS__)
-#  define ullwarn(format, ...) _llwarn(format, ##__VA_ARGS__)
 #else
 #  define uwarn(x...)
-#  define ullwarn(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_USB_INFO
 #  define uinfo(format, ...)   _info(format, ##__VA_ARGS__)
-#  define ullinfo(format, ...) _llinfo(format, ##__VA_ARGS__)
 #else
 #  define uinfo(x...)
-#  define ullinfo(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_WATCHDOG_ERROR
 #  define wderr(format, ...)     _err(format, ##__VA_ARGS__)
-#  define wdllerr(format, ...)   _llerr(format, ##__VA_ARGS__)
 #else
 #  define wderr(x...)
-#  define wdllerr(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_WATCHDOG_WARN
 #  define wdwarn(format, ...)   _warn(format, ##__VA_ARGS__)
-#  define wdllwarn(format, ...) _llwarn(format, ##__VA_ARGS__)
 #else
 #  define wdwarn(x...)
-#  define wdllwarn(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_WATCHDOG_INFO
 #  define wdinfo(format, ...)   _info(format, ##__VA_ARGS__)
-#  define wdllinfo(format, ...) _llinfo(format, ##__VA_ARGS__)
 #else
 #  define wdinfo(x...)
-#  define wdllinfo(x...)
 #endif
 
 #else /* CONFIG_CPP_HAVE_VARARGS */
 
 /* Variadic macros NOT supported */
 
-#ifndef CONFIG_ARCH_LOWPUTC
+#ifndef CONFIG_DEBUG_ALERT
 #  define _alert      (void)
 # endif
 
-#ifdef CONFIG_DEBUG_ERROR
-#  ifndef CONFIG_ARCH_LOWPUTC
-#    define _llerr    (void)
-#  endif
-#else
+#ifndef CONFIG_DEBUG_ERROR
 #  define _err        (void)
-#  define _llerr      (void)
 #endif
 
-#ifdef CONFIG_DEBUG_WARN
-#  ifndef CONFIG_ARCH_LOWPUTC
-#    define _llwarn   (void)
-#  endif
-#else
+#ifndef CONFIG_DEBUG_WARN
 #  define _warn       (void)
-#  define _llwarn     (void)
 #endif
 
-#ifdef CONFIG_DEBUG_INFO
-#  ifndef CONFIG_ARCH_LOWPUTC
-#    define _llinfo   (void)
-#  endif
-#else
+#ifndef CONFIG_DEBUG_INFO
 #  define _info       (void)
-#  define _llinfo     (void)
 #endif
 
 /* Subsystem specific debug */
 
 #ifdef CONFIG_DEBUG_MM_ERROR
 #  define merr         _err
-#  define mllerr       _llerr
 #else
 #  define merr        (void)
-#  define mllerr      (void)
 #endif
 
 #ifdef CONFIG_DEBUG_MM_WARN
 #  define mwarn       _warn
-#  define mllwarn     _llwarn
 #else
 #  define mwarn       (void)
-#  define mllwarn     (void)
 #endif
 
 #ifdef CONFIG_DEBUG_MM_INFO
 #  define minfo       _info
-#  define mllinfo     _llinfo
 #else
 #  define minfo       (void)
-#  define mllinfo     (void)
 #endif
 
 #ifdef CONFIG_DEBUG_SCHED_ERROR
 #  define serr         _err
-#  define sllerr       _llerr
 #else
 #  define serr        (void)
-#  define sllerr      (void)
 #endif
 
 #ifdef CONFIG_DEBUG_SCHED_WARN
 #  define swarn       _warn
-#  define sllwarn     _llwarn
 #else
 #  define swarn       (void)
-#  define sllwarn     (void)
 #endif
 
 #ifdef CONFIG_DEBUG_SCHED_INFO
 #  define sinfo       _info
-#  define sllinfo     _llinfo
 #else
 #  define sinfo       (void)
-#  define sllinfo     (void)
 #endif
 
 #ifdef CONFIG_DEBUG_SYSCALL_ERROR
 #  define svcerr       _err
-#  define svcllerr     _llerr
 #else
 #  define svcerr      (void)
-#  define svcllerr    (void)
 #endif
 
 #ifdef CONFIG_DEBUG_SYSCALL_WARN
 #  define svcwarn     _warn
-#  define svcllwarn   _llwarn
 #else
 #  define svcwarn     (void)
-#  define svcllwarn   (void)
 #endif
 
 #ifdef CONFIG_DEBUG_SYSCALL_INFO
 #  define svcinfo     _info
-#  define svcllinfo   _llinfo
 #else
 #  define svcinfo     (void)
-#  define svcllinfo   (void)
 #endif
 
 #ifdef CONFIG_DEBUG_PAGING_ERROR
 #  define pgerr        _err
-#  define pgllerr      _llerr
 #else
 #  define pgerr       (void)
-#  define pgllerr     (void)
 #endif
 
 #ifdef CONFIG_DEBUG_PAGING_WARN
 #  define pgwarn      _warn
-#  define pgllwarn    _llwarn
 #else
 #  define pgwarn      (void)
-#  define pgllwarn    (void)
 #endif
 
 #ifdef CONFIG_DEBUG_PAGING_INFO
 #  define pginfo      _info
-#  define pgllinfo    _llinfo
 #else
 #  define pginfo      (void)
-#  define pgllinfo    (void)
 #endif
 
 #ifdef CONFIG_DEBUG_NET_ERROR
 #  define nerr         _err
-#  define nllerr       _llerr
 #else
 #  define nerr        (void)
-#  define nllerr      (void)
 #endif
 
 #ifdef CONFIG_DEBUG_NET_WARN
 #  define nwarn       _warn
-#  define nllwarn     _llwarn
 #else
 #  define nwarn       (void)
-#  define nllwarn     (void)
 #endif
 
 #ifdef CONFIG_DEBUG_NET_INFO
 #  define ninfo       _info
-#  define nllinfo     _llinfo
 #else
 #  define ninfo       (void)
-#  define nllinfo     (void)
 #endif
 
 #ifdef CONFIG_DEBUG_FS_ERROR
 #  define ferr         _err
-#  define fllerr       _llerr
 #else
 #  define ferr        (void)
-#  define fllerr      (void)
 #endif
 
 #ifdef CONFIG_DEBUG_FS_WARN
 #  define fwarn       _warn
-#  define fllwarn     _llwarn
 #else
 #  define fwarn       (void)
-#  define fllwarn     (void)
 #endif
 
 #ifdef CONFIG_DEBUG_FS_INFO
 #  define finfo       _info
-#  define fllinfo     _llinfo
 #else
 #  define finfo       (void)
-#  define fllinfo     (void)
 #endif
 
 #ifdef CONFIG_DEBUG_CRYPTO_ERROR
 #  define crypterr     _err
-#  define cryptllerr   _llerr
 #else
 #  define crypterr    (void)
-#  define cryptllerr  (void)
 #endif
 
 #ifdef CONFIG_DEBUG_CRYPTO_WARN
 #  define cryptwarn   _warn
-#  define cryptllwarn _llwarn
 #else
 #  define cryptwarn   (void)
-#  define cryptllwarn (void)
 #endif
 
 #ifdef CONFIG_DEBUG_CRYPTO_INFO
 #  define cryptinfo   _info
-#  define cryptllinfo _llinfo
 #else
 #  define cryptinfo(x...)
-#  define cryptllinfo(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_INPUT_ERROR
 #  define ierr         _err
-#  define illerr       _llerr
 #else
 #  define ierr        (void)
-#  define illerr      (void)
 #endif
 
 #ifdef CONFIG_DEBUG_INPUT_WARN
 #  define iwarn       _warn
-#  define illwarn     _llwarn
 #else
 #  define iwarn       (void)
-#  define illwarn     (void)
 #endif
 
 #ifdef CONFIG_DEBUG_INPUT_INFO
 #  define iinfo       _info
-#  define illinfo     _llinfo
 #else
 #  define iinfo       (void)
-#  define illinfo     (void)
 #endif
 
 #ifdef CONFIG_DEBUG_ANALOG_ERROR
 #  define aerr         _err
-#  define allerr       _llerr
 #else
 #  define aerr        (void)
-#  define allerr      (void)
 #endif
 
 #ifdef CONFIG_DEBUG_ANALOG_WARN
 #  define awarn       _warn
-#  define allwarn     _llwarn
 #else
 #  define awarn       (void)
-#  define allwarn     (void)
 #endif
 
 #ifdef CONFIG_DEBUG_ANALOG_INFO
 #  define ainfo       _info
-#  define allinfo     _llinfo
 #else
 #  define ainfo       (void)
-#  define allinfo     (void)
 #endif
 
 #ifdef CONFIG_DEBUG_CAN_ERROR
 #  define canerr       _err
-#  define canllerr     _llerr
 #else
 #  define canerr      (void)
-#  define canllerr    (void)
 #endif
 
 #ifdef CONFIG_DEBUG_CAN_WARN
 #  define canwarn     _warn
-#  define canllwarn   _llwarn
 #else
 #  define canwarn     (void)
-#  define canllwarn   (void)
 #endif
 
 #ifdef CONFIG_DEBUG_CAN_INFO
 #  define caninfo     _info
-#  define canllinfo   _llinfo
 #else
 #  define caninfo     (void)
-#  define canllinfo   (void)
 #endif
 
 #ifdef CONFIG_DEBUG_GRAPHICS_ERROR
 #  define gerr         _err
-#  define gllerr       _llerr
 #else
 #  define gerr        (void)
-#  define gllerr      (void)
 #endif
 
 #ifdef CONFIG_DEBUG_GRAPHICS_WARN
 #  define gwarn       _warn
-#  define gllwarn     _llwarn
 #else
 #  define gwarn       (void)
-#  define gllwarn     (void)
 #endif
 
 #ifdef CONFIG_DEBUG_GRAPHICS_INFO
 #  define ginfo       _info
-#  define gllinfo     _llinfo
 #else
 #  define ginfo       (void)
-#  define gllinfo     (void)
 #endif
 
 #ifdef CONFIG_DEBUG_BINFMT_ERROR
 #  define berr         _err
-#  define bllerr       _llerr
 #else
 #  define berr        (void)
-#  define bllerr      (void)
 #endif
 
 #ifdef CONFIG_DEBUG_BINFMT_WARN
 #  define bwarn       _warn
-#  define bllwarn     _llwarn
 #else
 #  define bwarn       (void)
-#  define bllwarn     (void)
 #endif
 
 #ifdef CONFIG_DEBUG_BINFMT_INFO
 #  define binfo       _info
-#  define bllinfo     _llinfo
 #else
 #  define binfo       (void)
-#  define bllinfo     (void)
 #endif
 
 #ifdef CONFIG_DEBUG_LIB_ERROR
 #  define lerr         _err
-#  define lllerr       _llerr
 #else
 #  define lerr        (void)
-#  define lllerr      (void)
 #endif
 
 #ifdef CONFIG_DEBUG_LIB_WARN
 #  define lwarn       _warn
-#  define lllwarn     _llwarn
 #else
 #  define lwarn       (void)
-#  define lllwarn     (void)
 #endif
 
 #ifdef CONFIG_DEBUG_LIB_INFO
 #  define linfo       _info
-#  define lllinfo     _llinfo
 #else
 #  define linfo       (void)
-#  define lllinfo     (void)
 #endif
 
 #ifdef CONFIG_DEBUG_AUDIO_ERROR
 #  define auderr       _err
-#  define audllerr     _llerr
 #else
 #  define auderr      (void)
-#  define audllerr    (void)
 #endif
 
 #ifdef CONFIG_DEBUG_AUDIO_WARN
 #  define audwarn     _warn
-#  define audllwarn   _llwarn
 #else
 #  define audwarn     (void)
-#  define audllwarn   (void)
 #endif
 
 #ifdef CONFIG_DEBUG_AUDIO_INFO
 #  define audinfo     _info
-#  define audllinfo   _llinfo
 #else
 #  define audinfo     (void)
-#  define audllinfo   (void)
 #endif
 
 #ifdef CONFIG_DEBUG_DMA_ERROR
 #  define dmaerr       _err
-#  define dmallerr     _llerr
 #else
 #  define dmaerr      (void)
-#  define dmallerr    (void)
 #endif
 
 #ifdef CONFIG_DEBUG_DMA_WARN
 #  define dmawarn     _warn
-#  define dmallwarn   _llwarn
 #else
 #  define dmawarn     (void)
-#  define dmallwarn   (void)
 #endif
 
 #ifdef CONFIG_DEBUG_DMA_INFO
 #  define dmainfo     _info
-#  define dmallinfo   _llinfo
 #else
 #  define dmainfo     (void)
-#  define dmallinfo   (void)
 #endif
 
 #ifdef CONFIG_DEBUG_IRQ_ERROR
 #  define irqerr       _err
-#  define irqllerr     _llerr
 #else
 #  define irqerr      (void)
-#  define irqllerr    (void)
 #endif
 
 #ifdef CONFIG_DEBUG_IRQ_WARN
 #  define irqwarn     _warn
-#  define irqllwarn   _llwarn
 #else
 #  define irqwarn     (void)
-#  define irqllwarn   (void)
 #endif
 
 #ifdef CONFIG_DEBUG_IRQ_INFO
 #  define irqinfo     _info
-#  define irqllinfo   _llinfo
 #else
 #  define irqinfo     (void)
-#  define irqllinfo   (void)
 #endif
 
 #ifdef CONFIG_DEBUG_LCD_ERROR
 #  define lcderr       _err
-#  define lcdllerr     _llerr
 #else
 #  define lcderr      (void)
-#  define lcdllerr    (void)
 #endif
 
 #ifdef CONFIG_DEBUG_LCD_WARN
 #  define lcdwarn     _warn
-#  define lcdllwarn   _llwarn
 #else
 #  define lcdwarn     (void)
-#  define lcdllwarn   (void)
 #endif
 
 #ifdef CONFIG_DEBUG_LCD_INFO
 #  define lcdinfo     _info
-#  define lcdllinfo   _llinfo
 #else
 #  define lcdinfo     (void)
-#  define lcdllinfo   (void)
 #endif
 
 #ifdef CONFIG_DEBUG_LEDS_ERROR
 #  define lederr       _err
-#  define ledllerr     _llerr
 #else
 #  define lederr      (void)
-#  define ledllerr    (void)
 #endif
 
 #ifdef CONFIG_DEBUG_LEDS_WARN
 #  define ledwarn     _warn
-#  define ledllwarn   _llwarn
 #else
 #  define ledwarn     (void)
-#  define ledllwarn   (void)
 #endif
 
 #ifdef CONFIG_DEBUG_LEDS_INFO
 #  define ledinfo     _info
-#  define ledllinfo   _llinfo
 #else
 #  define ledinfo     (void)
-#  define ledllinfo   (void)
 #endif
 
 #ifdef CONFIG_DEBUG_GPIO_ERROR
 #  define gpioerr      _err
-#  define gpiollerr    _llerr
 #else
 #  define gpioerr     (void)
-#  define gpiollerr   (void)
 #endif
 
 #ifdef CONFIG_DEBUG_GPIO_WARN
 #  define gpiowarn    _warn
-#  define gpiollwarn  _llwarn
 #else
 #  define gpiowarn    (void)
-#  define gpiollwarn  (void)
 #endif
 
 #ifdef CONFIG_DEBUG_GPIO_INFO
 #  define gpioinfo    _info
-#  define gpiollinfo  _llinfo
 #else
 #  define gpioinfo    (void)
-#  define gpiollinfo  (void)
 #endif
 
 #ifdef CONFIG_DEBUG_I2C_ERROR
 #  define i2cerr       _err
-#  define i2cllerr     _llerr
 #else
 #  define i2cerr      (void)
-#  define i2cllerr    (void)
 #endif
 
 #ifdef CONFIG_DEBUG_I2C_WARN
 #  define i2cwarn     _warn
-#  define i2cllwarn   _llwarn
 #else
 #  define i2cwarn     (void)
-#  define i2cllwarn   (void)
 #endif
 
 #ifdef CONFIG_DEBUG_I2C_INFO
 #  define i2cinfo     _info
-#  define i2cllinfo   _llinfo
 #else
 #  define i2cinfo     (void)
-#  define i2cllinfo   (void)
 #endif
 
 #ifdef CONFIG_DEBUG_I2S_ERROR
 #  define i2serr       _err
-#  define i2sllerr     _llerr
 #else
 #  define i2serr      (void)
-#  define i2sllerr    (void)
 #endif
 
 #ifdef CONFIG_DEBUG_I2S_WARN
 #  define i2swarn     _warn
-#  define i2sllwarn   _llwarn
 #else
 #  define i2swarn     (void)
-#  define i2sllwarn   (void)
 #endif
 
 #ifdef CONFIG_DEBUG_I2S_INFO
 #  define i2sinfo     _info
-#  define i2sllinfo   _llinfo
 #else
 #  define i2sinfo     (void)
-#  define i2sllinfo   (void)
 #endif
 
 #ifdef CONFIG_DEBUG_PWM_ERROR
 #  define pwmerr       _err
-#  define pwmllerr     _llerr
 #else
 #  define pwmerr      (void)
-#  define pwmllerr    (void)
 #endif
 
 #ifdef CONFIG_DEBUG_PWM_WARN
 #  define pwmwarn     _warn
-#  define pwmllwarn   _llwarn
 #else
 #  define pwmwarn     (void)
-#  define pwmllwarn   (void)
 #endif
 
 #ifdef CONFIG_DEBUG_PWM_INFO
 #  define pwminfo     _info
-#  define pwmllinfo   _llinfo
 #else
 #  define pwminfo     (void)
-#  define pwmllinfo   (void)
 #endif
 
 #ifdef CONFIG_DEBUG_RTC_ERROR
 #  define rtcerr       _err
-#  define rtcllerr     _llerr
 #else
 #  define rtcerr      (void)
-#  define rtcllerr    (void)
 #endif
 
 #ifdef CONFIG_DEBUG_RTC_WARN
 #  define rtcwarn     _warn
-#  define rtcllwarn   _llwarn
 #else
 #  define rtcwarn     (void)
-#  define rtcllwarn   (void)
 #endif
 
 #ifdef CONFIG_DEBUG_RTC_INFO
 #  define rtcinfo     _info
-#  define rtcllinfo   _llinfo
 #else
 #  define rtcinfo     (void)
-#  define rtcllinfo   (void)
 #endif
 
 #ifdef CONFIG_DEBUG_MEMCARD_ERROR
 #  define mcerr        _err
-#  define mcllerr      _llerr
 #else
 #  define mcerr       (void)
-#  define mcllerr     (void)
 #endif
 
 #ifdef CONFIG_DEBUG_MEMCARD_WARN
 #  define mcwarn      _warn
-#  define mcllwarn    _llwarn
 #else
 #  define mcwarn      (void)
-#  define mcllwarn    (void)
 #endif
 
 #ifdef CONFIG_DEBUG_MEMCARD_INFO
 #  define mcinfo      _info
-#  define mcllinfo    _llinfo
 #else
 #  define mcinfo      (void)
-#  define mcllinfo    (void)
 #endif
 
 #ifdef CONFIG_DEBUG_SENSORS_ERROR
 #  define snerr        _err
-#  define snllerr      _llerr
 #else
 #  define snerr       (void)
-#  define snllerr     (void)
 #endif
 
 #ifdef CONFIG_DEBUG_SENSORS_WARN
 #  define snwarn      _warn
-#  define snllwarn    _llwarn
 #else
 #  define snwarn      (void)
-#  define snllwarn    (void)
 #endif
 
 #ifdef CONFIG_DEBUG_SENSORS_INFO
 #  define sninfo      _info
-#  define snllinfo    _llinfo
 #else
 #  define sninfo      (void)
-#  define snllinfo    (void)
 #endif
 
 #ifdef CONFIG_DEBUG_SPI_ERROR
 #  define spierr       _err
-#  define spillerr     _llerr
 #else
 #  define spierr      (void)
-#  define spillerr    (void)
 #endif
 
 #ifdef CONFIG_DEBUG_SPI_WARN
 #  define spiwarn     _warn
-#  define spillwarn   _llwarn
 #else
 #  define spiwarn     (void)
-#  define spillwarn   (void)
 #endif
 
 #ifdef CONFIG_DEBUG_SPI_INFO
 #  define spiinfo     _info
-#  define spillinfo   _llinfo
 #else
 #  define spiinfo     (void)
-#  define spillinfo   (void)
 #endif
 
 #ifdef CONFIG_DEBUG_TIMER_ERROR
 #  define tmrerr       _err
-#  define tmrllerr     _llerr
 #else
 #  define tmrerr      (void)
-#  define tmrllerr    (void)
 #endif
 
 #ifdef CONFIG_DEBUG_TIMER_WARN
 #  define tmrwarn     _warn
-#  define tmrllwarn   _llwarn
 #else
 #  define tmrwarn     (void)
-#  define tmrllwarn   (void)
 #endif
 
 #ifdef CONFIG_DEBUG_TIMER_INFO
 #  define tmrinfo     _info
-#  define tmrllinfo   _llinfo
 #else
 #  define tmrinfo     (void)
-#  define tmrllinfo   (void)
 #endif
 
 #ifdef CONFIG_DEBUG_USB_ERROR
 #  define uerr         _err
-#  define ullerr       _llerr
 #else
 #  define uerr        (void)
-#  define ullerr      (void)
 #endif
 
 #ifdef CONFIG_DEBUG_USB_WARN
 #  define uwarn       _warn
-#  define ullwarn     _llwarn
 #else
 #  define uwarn       (void)
-#  define ullwarn     (void)
 #endif
 
 #ifdef CONFIG_DEBUG_USB_INFO
 #  define uinfo       _info
-#  define ullinfo     _llinfo
 #else
 #  define uinfo       (void)
-#  define ullinfo     (void)
 #endif
 
 #ifdef CONFIG_DEBUG_WATCHDOG_ERROR
 #  define wderr        _err
-#  define wdllerr      _llerr
 #else
 #  define wderr       (void)
-#  define wdllerr     (void)
 #endif
 
 #ifdef CONFIG_DEBUG_WATCHDOG_WARN
 #  define wdwarn      _warn
-#  define wdllwarn    _llwarn
 #else
 #  define wdwarn      (void)
-#  define wdllwarn    (void)
 #endif
 
 #ifdef CONFIG_DEBUG_WATCHDOG_INFO
 #  define wdinfo      _info
-#  define wdllinfo    _llinfo
 #else
 #  define wdinfo      (void)
-#  define wdllinfo    (void)
 #endif
 
 #endif /* CONFIG_CPP_HAVE_VARARGS */
@@ -1894,33 +1483,21 @@ void lib_dumpbuffer(FAR const char *msg, FAR const uint8_t *buffer,
  */
 
 #ifndef CONFIG_CPP_HAVE_VARARGS
-#ifndef CONFIG_ARCH_LOWPUTC
+#ifdef CONFIG_DEBUG_ALERT
 int _alert(const char *format, ...);
 #endif
 
 #ifdef CONFIG_DEBUG_ERROR
 int  _err(const char *format, ...);
-
-# ifdef CONFIG_ARCH_LOWPUTC
-int  _llerr(const char *format, ...);
-# endif
-#endif /* CONFIG_DEBUG_ERROR */
+#endif
 
 #ifdef CONFIG_DEBUG_WARN
 int _warn(const char *format, ...);
-
-# ifdef CONFIG_ARCH_LOWPUTC
-int _llwarn(const char *format, ...);
-# endif
-#endif /* CONFIG_DEBUG_WARN */
+#endif
 
 #ifdef CONFIG_DEBUG_INFO
 int _info(const char *format, ...);
-
-# ifdef CONFIG_ARCH_LOWPUTC
-int _llinfo(const char *format, ...);
-# endif
-#endif /* CONFIG_DEBUG_INFO */
+#endif
 #endif /* CONFIG_CPP_HAVE_VARARGS */
 
 #if defined(__cplusplus)
diff --git a/include/nuttx/can.h b/include/nuttx/can.h
index 573edd16b2b..afcb8eb7505 100644
--- a/include/nuttx/can.h
+++ b/include/nuttx/can.h
@@ -504,6 +504,9 @@ struct can_dev_s
   uint8_t              cd_error;         /* Flags to indicate internal device errors */
 #endif
   sem_t                cd_closesem;      /* Locks out new opens while close is in progress */
+#ifndef CONFIG_DISABLE_POLL
+  sem_t                cd_pollsem;       /* Manages exclusive access to cd_fds[] */
+#endif
   struct can_txfifo_s  cd_xmit;          /* Describes transmit FIFO */
   struct can_rxfifo_s  cd_recv;          /* Describes receive FIFO */
 #ifdef CONFIG_CAN_TXREADY
@@ -513,6 +516,10 @@ struct can_dev_s
   struct can_rtrwait_s cd_rtr[CONFIG_CAN_NPENDINGRTR];
   FAR const struct can_ops_s *cd_ops;    /* Arch-specific operations */
   FAR void            *cd_priv;          /* Used by the arch-specific logic */
+
+#ifndef CONFIG_DISABLE_POLL
+  FAR struct pollfd   *cd_fds[CONFIG_CAN_NPOLLWAITERS];
+#endif
 };
 
 /* Structures used with ioctl calls */
diff --git a/include/nuttx/streams.h b/include/nuttx/streams.h
index ab57b33b35d..6ae6b8c9430 100644
--- a/include/nuttx/streams.h
+++ b/include/nuttx/streams.h
@@ -1,7 +1,7 @@
 /****************************************************************************
  * include/nuttx/streams.h
  *
- *   Copyright (C) 2009, 2011-2012, 2014-2015 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2009, 2011-2012, 2014-2016 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -354,23 +354,40 @@ void lib_nullinstream(FAR struct lib_instream_s *nullinstream);
 void lib_nulloutstream(FAR struct lib_outstream_s *nulloutstream);
 
 /****************************************************************************
- * Name: lib_sylogstream
+ * Name: syslogstream
  *
  * Description:
  *   Initializes a stream for use with the configured syslog interface.
+ *   Only accessible from with the OS SYSLOG logic.
  *
  * Input parameters:
- *   lowoutstream - User allocated, uninitialized instance of struct
- *                  lib_lowoutstream_s to be initialized.
+ *   stream - User allocated, uninitialized instance of struct
+ *            lib_lowoutstream_s to be initialized.
  *
  * Returned Value:
  *   None (User allocated instance initialized).
  *
  ****************************************************************************/
 
-#ifdef CONFIG_SYSLOG
-void lib_syslogstream(FAR struct lib_outstream_s *stream);
-#endif
+void syslogstream(FAR struct lib_outstream_s *stream);
+
+/****************************************************************************
+ * Name: emergstream
+ *
+ * Description:
+ *   Initializes a stream for use with the configured emergency syslog
+ *   interface.  Only accessible from with the OS SYSLOG logic.
+ *
+ * Input parameters:
+ *   stream - User allocated, uninitialized instance of struct
+ *            lib_lowoutstream_s to be initialized.
+ *
+ * Returned Value:
+ *   None (User allocated instance initialized).
+ *
+ ****************************************************************************/
+
+void emergstream(FAR struct lib_outstream_s *stream);
 
 /****************************************************************************
  * Name: lib_noflush
diff --git a/include/nuttx/syslog/ramlog.h b/include/nuttx/syslog/ramlog.h
index 75c767819cb..70ec26f316e 100644
--- a/include/nuttx/syslog/ramlog.h
+++ b/include/nuttx/syslog/ramlog.h
@@ -70,12 +70,11 @@
  *   in that case, console output from non-Telnet threads will go to the
  *   circular buffer and can be viewed using the NSH 'dmesg' command.
  * CONFIG_RAMLOG_SYSLOG - Use the RAM logging device for the syslogging
- *   interface.  If this feature is enabled (along with CONFIG_SYSLOG),
- *   then all debug output (only) will be re-directed to the circular
- *   buffer in RAM.  This RAM log can be view from NSH using the 'dmesg'
- *   command.  NOTE:  Unlike the limited, generic character driver SYSLOG
- *   device, the RAMLOG *can* be used to generate debug output from interrupt
- *   level handlers.
+ *   interface.  If this feature is enabled then all debug output (only)
+ *   will be re-directed to the circular buffer in RAM.  This RAM log can
+ *   be viewied from NSH using the 'dmesg' command.  NOTE:  Unlike the
+ *   limited, generic character driver SYSLOG device, the RAMLOG *can* be
+ *   used to generate debug output from interrupt level handlers.
  * CONFIG_RAMLOG_NPOLLWAITERS - The number of threads than can be waiting
  *   for this driver on poll().  Default: 4
  *
@@ -89,10 +88,6 @@
 #  undef CONFIG_RAMLOG_CONSOLE
 #endif
 
-#ifndef CONFIG_SYSLOG
-#  undef CONFIG_RAMLOG_SYSLOG
-#endif
-
 #if defined(CONFIG_RAMLOG_SYSLOG) && !defined(CONFIG_SYSLOG_DEVPATH)
 #  define CONFIG_SYSLOG_DEVPATH "/dev/ramlog"
 #endif
@@ -101,25 +96,10 @@
 #  define CONFIG_RAMLOG_NPOLLWAITERS 4
 #endif
 
-#ifndef CONFIG_SYSLOG
-#  undef CONFIG_RAMLOG_SYSLOG
-#endif
-
 #ifndef CONFIG_RAMLOG_BUFSIZE
 #  define CONFIG_RAMLOG_BUFSIZE 1024
 #endif
 
-/* The normal behavior of the RAM log when used as a SYSLOG is to return
- * end-of-file if there is no data in the RAM log (rather than blocking until
- * data is available).  That allows you to 'cat' the SYSLOG with no ill
- * consequences.
- */
-
-#ifdef CONFIG_SYSLOG
-#  undef CONFIG_RAMLOG_NONBLOCKING
-#  define CONFIG_RAMLOG_NONBLOCKING 1
-#endif
-
 /* When used as a console or syslogging device, the RAM log will pre-pend
  * line-feeds with carriage returns.
  */
@@ -183,7 +163,7 @@ int ramlog_consoleinit(void);
 #endif
 
 /****************************************************************************
- * Name: ramlog_sysloginit
+ * Name: ramlog_syslog_channel
  *
  * Description:
  *   Create the RAM logging device and register it at the specified path.
@@ -195,7 +175,19 @@ int ramlog_consoleinit(void);
  ****************************************************************************/
 
 #ifdef CONFIG_RAMLOG_SYSLOG
-int ramlog_sysloginit(void);
+int ramlog_syslog_channel(void);
+#endif
+
+/****************************************************************************
+ * Name: ramlog_putc
+ *
+ * Description:
+ *   This is the low-level system logging interface.
+ *
+ ****************************************************************************/
+
+#if defined(CONFIG_RAMLOG_CONSOLE) || defined(CONFIG_RAMLOG_SYSLOG)
+int ramlog_putc(int ch);
 #endif
 
 #undef EXTERN
diff --git a/include/nuttx/syslog/syslog.h b/include/nuttx/syslog/syslog.h
index 836440da816..fdb2794b79b 100644
--- a/include/nuttx/syslog/syslog.h
+++ b/include/nuttx/syslog/syslog.h
@@ -2,7 +2,7 @@
  * include/nuttx/syslog/syslog.h
  * The NuttX SYSLOGing interface
  *
- *   Copyright (C) 2012, 2014-2015 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2012, 2014-2016 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -42,16 +42,20 @@
  ****************************************************************************/
 
 #include <nuttx/config.h>
+#include <nuttx/compiler.h>
+#include <stdarg.h>
 
 /****************************************************************************
  * Pre-processor Definitions
  ****************************************************************************/
 /* Configuration ************************************************************/
-/* CONFIG_SYSLOG - Enables generic system logging features.
+/* CONFIG_SYSLOG_INTBUFFER - Enables an interrupt buffer that will be used
+ *   to serialize debug output from interrupt handlers.
+ * CONFIG_SYSLOG_INTBUFSIZE - The size of the interrupt buffer in bytes.
  * CONFIG_SYSLOG_DEVPATH - The full path to the system logging device
  *
  * In addition, some SYSLOG device must also be enabled that will provide
- * the syslog_putc() function.  As of this writing, there are two SYSLOG
+ * the syslog output "channel.  As of this writing, there are two SYSLOG
  * devices avaiable:
  *
  *   1. A RAM SYSLOGing device that will log data into a circular buffer
@@ -66,19 +70,54 @@
  * CONFIG_SYSLOG_CHAR - Enable the generic character device for the SYSLOG.
  *   The full path to the SYSLOG device is provided by CONFIG_SYSLOG_DEVPATH.
  *   A valid character device must exist at this path.  It will by opened
- *   by syslog_initialize.
+ *   by logic in syslog_initialize() based on the current configuration.
  *
  *   NOTE:  No more than one SYSLOG device should be configured.
  */
 
-#ifndef CONFIG_SYSLOG
-#  undef CONFIG_SYSLOG_CHAR
-#endif
-
 #if defined(CONFIG_SYSLOG_CHAR) && !defined(CONFIG_SYSLOG_DEVPATH)
 #  define CONFIG_SYSLOG_DEVPATH "/dev/ttyS1"
 #endif
 
+#ifdef CONFIG_SYSLOG_INTBUFFER
+#  ifndef CONFIG_SYSLOG_INTBUFSIZE
+#    define CONFIG_SYSLOG_INTBUFSIZE 512
+#  endif
+#  if CONFIG_SYSLOG_INTBUFSIZE > 65535
+#    undef  CONFIG_SYSLOG_INTBUFSIZE
+#    define CONFIG_SYSLOG_INTBUFSIZE 65535
+#  endif
+#endif
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/* Initialization phases */
+
+enum syslog_init_e
+{
+  SYSLOG_INIT_RESET = 0, /* Power on SYSLOG initializaton phase */
+  SYSLOG_INIT_EARLY,     /* Early initialization in up_initialize() */
+  SYSLOG_INIT_LATE       /* Late initialization in os_start(). */
+};
+
+/* This structure provides the interface to a SYSLOG device */
+
+typedef CODE int (*syslog_putc_t)(int ch);
+typedef CODE int (*syslog_flush_t)(void);
+
+struct syslog_channel_s
+{
+  /* I/O redirection methods */
+
+  syslog_putc_t sc_putc;    /* Normal buffered output */
+  syslog_putc_t sc_force;   /* Low-level output for interrupt handlers */
+  syslog_flush_t sc_flush;  /* Flush buffered output (on crash) */
+
+  /* Implementation specific logic may follow */
+};
+
 /****************************************************************************
  * Public Data
  ****************************************************************************/
@@ -96,38 +135,142 @@ extern "C"
 /****************************************************************************
  * Public Function Prototypes
  ****************************************************************************/
+
+/****************************************************************************
+ * Name: syslog_channel
+ *
+ * Description:
+ *   Configure the SYSLOGging function to use the provided channel to
+ *   generate SYSLOG output.
+ *
+ * Input buffer:
+ *   channel - Provides the interface to the channel to be used.
+ *
+ * Returned Value:
+ *   Zero (OK)is returned on  success.  A negated errno value is returned
+ *   on any failure.
+ *
+ ****************************************************************************/
+
+int syslog_channel(FAR const struct syslog_channel_s *channel);
+
 /****************************************************************************
  * Name: syslog_initialize
  *
  * Description:
- *   Initialize to use the character device (or file) at
- *   CONFIG_SYSLOG_DEVPATH as the SYSLOG sink.
+ *   One power up, the SYSLOG facility is non-existent or limited to very
+ *   low-level output.  This function is called later in the initialization
+ *   sequence after full driver support has been initialized.  It installs
+ *   the configured SYSLOG drivers and enables full SYSLOGing capability.
  *
- *   NOTE that this implementation excludes using a network connection as
- *   SYSLOG device.  That would be a good extension.
+ *   This function performs these basic operations:
+ *
+ *   - Initialize the SYSLOG device
+ *   - Call syslog_channel() to begin using that device.
+ *
+ *   If CONFIG_ARCH_SYSLOG is selected, then the architecture-specifica
+ *   logic will provide its own SYSLOG device initialize which must include
+ *   as a minimum a call to syslog_channel() to use the device.
+ *
+ * Input Parameters:
+ *   phase - One of {SYSLOG_INIT_EARLY, SYSLOG_INIT_LATE}
+ *
+ * Returned Value:
+ *   Zero (OK) is returned on success; a negated errno value is returned on
+ *   any failure.
  *
  ****************************************************************************/
 
-#ifdef CONFIG_SYSLOG_CHAR
-int syslog_initialize(void);
+#ifndef CONFIG_ARCH_SYSLOG
+int syslog_initialize(enum syslog_init_e phase);
+#else
+#  define syslog_initialize(phase)
 #endif
 
 /****************************************************************************
- * Name: syslog_putc
+ * Name: syslog_file_channel
  *
  * Description:
- *   This is the low-level system logging interface.  The debugging/syslogging
- *   interfaces are syslog() and lowsyslog().  The difference is that
- *   the syslog() internface writes to fd=1 (stdout) whereas lowsyslog() uses
- *   a lower level interface that works from interrupt handlers.  This
- *   function is the low-level interface used to implement lowsyslog().
+ *   Configure to use a file in a mounted file system at 'devpath' as the
+ *   SYSLOG channel.
+ *
+ *   This tiny function is simply a wrapper around syslog_dev_initialize()
+ *   and syslog_channel().  It calls syslog_dev_initialize() to configure
+ *   the character file at 'devpath then calls syslog_channel() to use that
+ *   device as the SYSLOG output channel.
+ *
+ *   File SYSLOG channels differ from other SYSLOG channels in that they
+ *   cannot be established until after fully booting and mounting the target
+ *   file system.  This function would need to be called from board-specific
+ *   bring-up logic AFTER mounting the file system containing 'devpath'.
+ *
+ *   SYSLOG data generated prior to calling syslog_file_channel will, of
+ *   course, not be included in the file.
+ *
+ *   NOTE interrupt level SYSLOG output will be lost in this case unless
+ *   the interrupt buffer is used.
+ *
+ * Input Parameters:
+ *   devpath - The full path to the file to be used for SYSLOG output.
+ *     This may be an existing file or not.  If the file exists,
+ *     syslog_file_channel() will append new SYSLOG data to the end of the
+ *     file.  If it does not, then syslog_file_channel() will create the
+ *     file.
+ *
+ * Returned Value:
+ *   Zero (OK) is returned on success; a negated errno value is returned on
+ *   any failure.
  *
  ****************************************************************************/
 
-#ifdef CONFIG_SYSLOG
-int syslog_putc(int ch);
+#ifdef CONFIG_SYSLOG_FILE
+int syslog_file_channel(FAR const char *devpath);
 #endif
 
+/****************************************************************************
+ * Name: syslog_flush
+ *
+ * Description:
+ *   This is called by system crash-handling logic.  It must flush any
+ *   buffered data to the SYSLOG device.
+ *
+ *   Interrupts are disabled at the time of the crash and this logic must
+ *   perform the flush using low-level, non-interrupt driven logic.
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   Zero (OK)is returned on  success.  A negated errno value is returned
+ *   on any failure.
+ *
+ ****************************************************************************/
+
+#if 0
+/* REVISIT: (1) Not yet integrated into assertion handlers and (2) there is
+ * an implementation problem in that if a character driver is the underlying
+ * device, then there is no mechanism to flush the data buffered in the
+ * driver with interrupts disabled.
+ */
+
+int syslog_flush(void);
+#endif
+
+/****************************************************************************
+ * Name: _vsyslog
+ *
+ * Description:
+ *   _vsyslog() handles the system logging system calls. It is functionally
+ *   equivalent to vsyslog() except that (1) the per-process priority
+ *   filtering has already been performed and the va_list parameter is
+ *   passed by reference.  That is because the va_list is a structure in
+ *   some compilers and passing of structures in the NuttX sycalls does
+ *   not work.
+ *
+ ****************************************************************************/
+
+int _vsyslog(int priority, FAR const IPTR char *src, FAR va_list *ap);
+
 #undef EXTERN
 #ifdef __cplusplus
 }
diff --git a/include/nuttx/syslog/syslog_console.h b/include/nuttx/syslog/syslog_console.h
index a14d75d9633..18283d9f393 100644
--- a/include/nuttx/syslog/syslog_console.h
+++ b/include/nuttx/syslog/syslog_console.h
@@ -43,22 +43,22 @@
 #include <nuttx/config.h>
 #include <nuttx/syslog/syslog.h>
 
-#ifdef CONFIG_SYSLOG_CONSOLE
+#ifdef CONFIG_CONSOLE_SYSLOG
 
 /****************************************************************************
  * Pre-processor Definitions
  ****************************************************************************/
 /* Configuration ************************************************************/
-/* CONFIG_SYSLOG_CONSOLE - Use the syslog logging output as a system console.
+/* CONFIG_CONSOLE_SYSLOG - Use the syslog logging output as a system console.
  *   If this feature is enabled (along with CONFIG_DEV_CONSOLE), then all
- *   console output will be re-directed to a syslog_putc function.  This
+ *   console output will be re-directed to the SYSLOG output channel.  This
  *   is useful, for example, if the only console is a Telnet console.  Then
  *   in that case, console output from non-Telnet threads will go to the
- *   syslog_putc output.
+ *   SYSLOG output channel.
  */
 
 #ifndef CONFIG_DEV_CONSOLE
-#  undef CONFIG_SYSLOG_CONSOLE
+#  undef CONFIG_CONSOLE_SYSLOG
 #endif
 
 /****************************************************************************
@@ -88,7 +88,7 @@ extern "C"
  *
  ****************************************************************************/
 
-#ifdef CONFIG_SYSLOG_CONSOLE
+#ifdef CONFIG_CONSOLE_SYSLOG
 int syslog_console_init(void);
 #endif
 
@@ -98,5 +98,5 @@ int syslog_console_init(void);
 #endif
 
 #endif /* __ASSEMBLY__ */
-#endif /* CONFIG_SYSLOG_CONSOLE */
+#endif /* CONFIG_CONSOLE_SYSLOG */
 #endif /* __INCLUDE_NUTTX_SYSLOG_SYSLOG_CONSOLE_H */
diff --git a/include/nuttx/wireless/nrf24l01.h b/include/nuttx/wireless/nrf24l01.h
index 4bb14827573..4ed00c1a47b 100644
--- a/include/nuttx/wireless/nrf24l01.h
+++ b/include/nuttx/wireless/nrf24l01.h
@@ -92,14 +92,12 @@
 
 #ifdef NRF24L01_DEBUG
 # define werr(format, ...)           _err(format, ##__VA_ARGS__)
-# define wllerr(format, ...)         _llerr(format, ##__VA_ARGS__)
+# define werr(format, ...)         _err(format, ##__VA_ARGS__)
 # define winfo(format, ...)          _info(format, ##__VA_ARGS__)
-# define wllinfo(format, ...)        _llinfo(format, ##__VA_ARGS__)
 #else
 # define werr(x...)
-# define wllerr(x...)
+# define werr(x...)
 # define winfo(x...)
-# define wllinfo(x...)
 #endif
 
 /****************************************************************************
diff --git a/include/sched.h b/include/sched.h
index b9a21f0f6f0..0c4443e93d4 100644
--- a/include/sched.h
+++ b/include/sched.h
@@ -44,6 +44,7 @@
 
 #include <sys/types.h>
 #include <stdint.h>
+#include <stdbool.h>
 #include <nuttx/sched.h>
 
 /********************************************************************************
@@ -255,6 +256,10 @@ int    sched_lock(void);
 int    sched_unlock(void);
 int    sched_lockcount(void);
 
+/* Queries */
+
+bool   sched_idletask(void);
+
 #undef EXTERN
 #if defined(__cplusplus)
 }
diff --git a/include/sys/syscall.h b/include/sys/syscall.h
index 198b27c9533..389c11bf08f 100644
--- a/include/sys/syscall.h
+++ b/include/sys/syscall.h
@@ -225,11 +225,16 @@
 #  define SYS_timer_getoverrun         (__SYS_timers+2)
 #  define SYS_timer_gettime            (__SYS_timers+3)
 #  define SYS_timer_settime            (__SYS_timers+4)
-#  define __SYS_descriptors            (__SYS_timers+5)
+#  define __SYS_syslog                 (__SYS_timers+5)
 #else
-#  define __SYS_descriptors             __SYS_timers
+#  define __SYS_syslog                 __SYS_timers
 #endif
 
+/* Unconditional system logging */
+
+#define SYS__vsyslog                   (__SYS_syslog+0)
+#define __SYS_descriptors              (__SYS_syslog+1)
+
 /* The following are defined if either file or socket descriptor are
  * enabled.
  */
diff --git a/include/syslog.h b/include/syslog.h
index efc62ac599d..4c1112cf76d 100644
--- a/include/syslog.h
+++ b/include/syslog.h
@@ -137,8 +137,60 @@ extern "C"
 {
 #endif
 
+/****************************************************************************
+ * Name: openlog
+ *
+ * Description:
+ *   The openlog() function sets process attributes that affect subsequent
+ *   calls to syslog(). The ident argument is a string that is prepended to
+ *   every message. The logopt argument indicates logging options. Values
+ *   for logopt are constructed by a bitwise-inclusive OR of zero or more of
+ *   the following:
+ *
+ *     LOG_PID - Log the process ID with each message. This is useful for
+ *       identifying specific processes.
+ *
+ *     LOG_CONS - Write messages to the system console if they cannot be
+ *       sent to the logging facility. The syslog() function ensures that
+ *       the process does not acquire the console as a controlling terminal
+ *       in the process of writing the message.
+ *
+ *     LOG_NDELAY - Open the connection to the logging facility immediately.
+ *       Normally the open is delayed until the first message is logged.
+ *       This is useful for programs that need to manage the order in which
+ *       file descriptors are allocated.
+ *
+ *     LOG_ODELAY - Delay open until syslog() is called.
+ *
+ *     LOG_NOWAIT - Do not wait for child processes that may have been
+ *       created during the course of logging the message. This option
+ *       should be used by processes that enable notification of child
+ *       termination using SIGCHLD, since syslog() may otherwise block
+ *       waiting for a child whose exit status has already been collected.
+ *
+ *   The facility argument encodes a default facility to be assigned to all
+ *   messages that do not have an explicit facility already encoded. The
+ *   initial default facility is LOG_USER.
+ *
+ *   It is not necessary to call openlog() prior to calling syslog().
+ *
+ ****************************************************************************/
+
 #if 0 /* Not supported */
 void openlog(FAR const char *ident, int option, int facility);
+#endif
+
+/****************************************************************************
+ * Name: closelog
+ *
+ * Description:
+ *   The openlog() and syslog() functions may allocate a file descriptor.
+ *   The closelog() function will close any open file descriptors allocated
+ *   by previous calls to openlog() or syslog().
+ *
+ ****************************************************************************/
+
+#if 0 /* Not supported */
 void closelog(void);
 #endif
 
@@ -163,48 +215,6 @@ void closelog(void);
 int syslog(int priority, FAR const IPTR char *format, ...);
 int vsyslog(int priority, FAR const IPTR char *src, va_list ap);
 
-/****************************************************************************
- * Name: lowsyslog and lowvsyslog
- *
- * Description:
- *   syslog() generates a log message. The priority argument is formed by
- *   ORing the facility and the level values (see include/syslog.h). The
- *   remaining arguments are a format, as in printf and any arguments to the
- *   format.
- *
- *   This is a non-standard, low-level system logging interface.  The
- *   difference between syslog() and lowsyslog() is that the syslog()
- *   interface writes to the syslog device (usually fd=1, stdout) whereas
- *   lowsyslog() uses a lower level interface that works even from interrupt
- *   handlers.
- *
- *   If the platform cannot support lowsyslog, then we will substitute the
- *   standard syslogging functions.  These will, however, probably cause
- *   problems if called from interrupt handlers, depending upon the nature of
- *   the underlying syslog device.
- *
- *   The function lowvsyslog() performs the same task as lowsyslog() with
- *   the difference that it takes a set of arguments which have been
- *   obtained using the stdarg variable argument list macros.
- *
- ****************************************************************************/
-
-#ifdef CONFIG_ARCH_LOWPUTC
-
-int lowsyslog(int priority, FAR const IPTR char *format, ...);
-int lowvsyslog(int priority, FAR const IPTR char *format, va_list ap);
-
-#else
-
-#  ifdef CONFIG_CPP_HAVE_VARARGS
-#    define lowsyslog(p,f,...) syslog(p,f,##__VA_ARGS__)
-#  else
-#    define lowsyslog (void)
-#  endif
-#  define lowvsyslog(p,f,a) vsyslog(p,f,a)
-
-#endif
-
 /****************************************************************************
  * Name: setlogmask
  *
diff --git a/libc/libc.csv b/libc/libc.csv
index 2c9eabe0b95..9a385a215b9 100644
--- a/libc/libc.csv
+++ b/libc/libc.csv
@@ -64,11 +64,6 @@
 "lib_dumpbuffer","debug.h","","void","FAR const char *","FAR const uint8_t *","unsigned int"
 "lio_listio","aio.h","defined(CONFIG_FS_AIO)","int","int","FAR struct aiocb *const []|FAR struct aiocb *const *","int","FAR struct sigevent *"
 "llabs","stdlib.h","defined(CONFIG_HAVE_LONG_LONG)","long long int","long long int"
-"_llerr","debug.h","!defined(CONFIG_CPP_HAVE_VARARGS) && defined(CONFIG_DEBUG_ERROR) && defined(CONFIG_ARCH_LOWPUTC)","int","const char *","..."
-"_llinfo","debug.h","!defined(CONFIG_CPP_HAVE_VARARGS) && defined(CONFIG_DEBUG_INFO) && defined(CONFIG_ARCH_LOWPUTC)","int","const char *","..."
-"_llwarn","debug.h","!defined(CONFIG_CPP_HAVE_VARARGS) && defined(CONFIG_DEBUG_WARN) && defined(CONFIG_ARCH_LOWPUTC)","int","const char *","..."
-"lowsyslog","syslog.h","","int","int","FAR const char *","..."
-"lowvsyslog","syslog.h","","int","int","FAR const char *","va_list"
 "match","nuttx/regex.h","","int","const char *","const char *"
 "memccpy","string.h","","FAR void","FAR void *","FAR const void *","int c","size_t"
 "memchr","string.h","","FAR void","FAR const void *","int c","size_t"
diff --git a/libc/misc/lib_debug.c b/libc/misc/lib_debug.c
index 7e6a33f8aa1..098f3cc2dd7 100644
--- a/libc/misc/lib_debug.c
+++ b/libc/misc/lib_debug.c
@@ -51,7 +51,7 @@
  ****************************************************************************/
 
 /****************************************************************************
- * Name: alert, err, llerr, warn, llwarn, info, _llinfo
+ * Name: alert, err, warn, and info
  *
  * Description:
  *  If the cross-compiler's pre-processor does not support variable
@@ -59,21 +59,21 @@
  *
  ****************************************************************************/
 
-#ifdef CONFIG_ARCH_LOWPUTC
+#ifdef CONFIG_DEBUG_ALERT
 int _alert(const char *format, ...)
 {
   va_list ap;
   int     ret;
 
   va_start(ap, format);
-  ret = lowvsyslog(LOG_EMERG, format, ap);
+  ret = vsyslog(LOG_EMERG, format, ap);
   va_end(ap);
 
   return ret;
 }
-#endif /* CONFIG_ARCH_LOWPUTC */
+#endif /* CONFIG_DEBUG_ALERT */
 
-#ifdef CONFIG_DEBUG_FEATURES
+#ifdef CONFIG_DEBUG_ERROR
 int  _err(const char *format, ...)
 {
   va_list ap;
@@ -85,21 +85,7 @@ int  _err(const char *format, ...)
 
   return ret;
 }
-
-#ifdef CONFIG_ARCH_LOWPUTC
-int  _llerr(const char *format, ...)
-{
-  va_list ap;
-  int     ret;
-
-  va_start(ap, format);
-  ret = lowvsyslog(LOG_ERR, format, ap);
-  va_end(ap);
-
-  return ret;
-}
-#endif /* CONFIG_ARCH_LOWPUTC */
-#endif /* CONFIG_DEBUG_FEATURES */
+#endif /* CONFIG_DEBUG_ERROR */
 
 #ifdef CONFIG_DEBUG_WARN
 int _warn(const char *format, ...)
@@ -113,21 +99,7 @@ int _warn(const char *format, ...)
 
   return ret;
 }
-
-#ifdef CONFIG_ARCH_LOWPUTC
-int _llwarn(const char *format, ...)
-{
-  va_list ap;
-  int     ret;
-
-  va_start(ap, format);
-  ret = lowvsyslog(LOG_WARNING, format, ap);
-  va_end(ap);
-
-  return ret;
-}
-#endif /* CONFIG_ARCH_LOWPUTC */
-#endif /* CONFIG_DEBUG_INFO */
+#endif /* CONFIG_DEBUG_WARN */
 
 #ifdef CONFIG_DEBUG_INFO
 int _info(const char *format, ...)
@@ -141,20 +113,6 @@ int _info(const char *format, ...)
 
   return ret;
 }
-
-#ifdef CONFIG_ARCH_LOWPUTC
-int _llinfo(const char *format, ...)
-{
-  va_list ap;
-  int     ret;
-
-  va_start(ap, format);
-  ret = lowvsyslog(LOG_INFO, format, ap);
-  va_end(ap);
-
-  return ret;
-}
-#endif /* CONFIG_ARCH_LOWPUTC */
 #endif /* CONFIG_DEBUG_INFO */
 
 #endif /* CONFIG_CPP_HAVE_VARARGS */
diff --git a/libc/misc/lib_dumpbuffer.c b/libc/misc/lib_dumpbuffer.c
index 23e7e617b8f..b1024d00b73 100644
--- a/libc/misc/lib_dumpbuffer.c
+++ b/libc/misc/lib_dumpbuffer.c
@@ -66,52 +66,52 @@ void lib_dumpbuffer(FAR const char *msg, FAR const uint8_t *buffer,
   unsigned int j;
   unsigned int k;
 
-  lowsyslog(LOG_INFO, "%s (%p):\n", msg, buffer);
+  syslog(LOG_INFO, "%s (%p):\n", msg, buffer);
   for (i = 0; i < buflen; i += 32)
     {
-      lowsyslog(LOG_INFO, "%04x: ", i);
+      syslog(LOG_INFO, "%04x: ", i);
       for (j = 0; j < 32; j++)
         {
           k = i + j;
 
           if (j == 16)
             {
-              lowsyslog(LOG_INFO, " ");
+              syslog(LOG_INFO, " ");
             }
 
           if (k < buflen)
             {
-              lowsyslog(LOG_INFO, "%02x", buffer[k]);
+              syslog(LOG_INFO, "%02x", buffer[k]);
             }
           else
             {
-              lowsyslog(LOG_INFO, "  ");
+              syslog(LOG_INFO, "  ");
             }
         }
 
-      lowsyslog(LOG_INFO, " ");
+      syslog(LOG_INFO, " ");
       for (j = 0; j < 32; j++)
         {
          k = i + j;
 
           if (j == 16)
             {
-              lowsyslog(LOG_INFO, " ");
+              syslog(LOG_INFO, " ");
             }
 
           if (k < buflen)
             {
               if (buffer[k] >= 0x20 && buffer[k] < 0x7f)
                 {
-                  lowsyslog(LOG_INFO, "%c", buffer[k]);
+                  syslog(LOG_INFO, "%c", buffer[k]);
                 }
               else
                 {
-                  lowsyslog(LOG_INFO, ".");
+                  syslog(LOG_INFO, ".");
                 }
             }
         }
 
-      lowsyslog(LOG_INFO, "\n");
+      syslog(LOG_INFO, "\n");
    }
 }
diff --git a/libc/netdb/lib_dnsaddserver.c b/libc/netdb/lib_dnsaddserver.c
index d0b7c42323a..3efbeb9ca0a 100644
--- a/libc/netdb/lib_dnsaddserver.c
+++ b/libc/netdb/lib_dnsaddserver.c
@@ -161,7 +161,7 @@ int dns_add_nameserver(FAR const struct sockaddr *addr, socklen_t addrlen)
   else
 #endif
     {
-      ninfo("ERROR: Unsupported family: %d\n",
+      nerr("ERROR: Unsupported family: %d\n",
             g_dns_server.addr.sa_family);
       ret = -ENOSYS;
       goto errout;
@@ -242,7 +242,7 @@ int dns_add_nameserver(FAR const struct sockaddr *addr, socklen_t addrlen)
   else
 #endif
     {
-      ninfo("ERROR: Unsupported family: %d\n", addr->sa_family);
+      nerr("ERROR: Unsupported family: %d\n", addr->sa_family);
       return -ENOSYS;
     }
 
@@ -250,7 +250,7 @@ int dns_add_nameserver(FAR const struct sockaddr *addr, socklen_t addrlen)
 
   if (addrlen < copylen)
     {
-      ninfo("ERROR: Invalid addrlen %ld for family %d\n",
+      nerr("ERROR: Invalid addrlen %ld for family %d\n",
             (long)addrlen, addr->sa_family);
       return -EINVAL;
     }
diff --git a/libc/netdb/lib_dnsforeach.c b/libc/netdb/lib_dnsforeach.c
index a6693e3c573..cc34b1658f2 100644
--- a/libc/netdb/lib_dnsforeach.c
+++ b/libc/netdb/lib_dnsforeach.c
@@ -276,7 +276,7 @@ int dns_foreach_nameserver(dns_callback_t callback, FAR void *arg)
       else
 #endif
         {
-          ninfo("ERROR: Unsupported family: %d\n",
+          nerr("ERROR: Unsupported family: %d\n",
                 g_dns_server.addr.sa_family);
           ret = -ENOSYS;
         }
diff --git a/libc/stdio/lib_fprintf.c b/libc/stdio/lib_fprintf.c
index 191dc2e34a4..bb744c4698b 100644
--- a/libc/stdio/lib_fprintf.c
+++ b/libc/stdio/lib_fprintf.c
@@ -33,44 +33,12 @@
  *
  ****************************************************************************/
 
-/****************************************************************************
- * Compilation Switches
- ****************************************************************************/
-
 /****************************************************************************
  * Included Files
  ****************************************************************************/
 
 #include <stdio.h>
 
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Private Type Declarations
- ****************************************************************************/
-
-/****************************************************************************
- * Private Function Prototypes
- ****************************************************************************/
-
-/****************************************************************************
- * Public Constant Data
- ****************************************************************************/
-
-/****************************************************************************
- * Public Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Constant Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
diff --git a/libc/stdio/lib_printf.c b/libc/stdio/lib_printf.c
index 5f1096a3a2f..b760abb4bb9 100644
--- a/libc/stdio/lib_printf.c
+++ b/libc/stdio/lib_printf.c
@@ -1,7 +1,7 @@
 /****************************************************************************
  * libc/stdio/lib_printf.c
  *
- *   Copyright (C) 2007-2008, 2011-2012, 2014 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2007-2008, 2011-2012, 2014, 2016 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -60,8 +60,6 @@ int printf(FAR const IPTR char *fmt, ...)
   ret = vfprintf(stdout, fmt, ap);
 #elif CONFIG_NFILE_DESCRIPTORS > 0
   ret = vsyslog(LOG_INFO, fmt, ap);
-#elif defined(CONFIG_ARCH_LOWPUTC)
-  ret = lowvsyslog(LOG_INFO, fmt, ap);
 #else
 # ifdef CONFIG_CPP_HAVE_WARNING
 #   warning "printf has no data sink"
diff --git a/libc/syslog/Make.defs b/libc/syslog/Make.defs
index 7ebdc907cf5..b1d6b093043 100644
--- a/libc/syslog/Make.defs
+++ b/libc/syslog/Make.defs
@@ -35,11 +35,7 @@
 
 # Add the internal C files to the build
 
-CSRCS += lib_syslog.c lib_lowsyslog.c lib_setlogmask.c
-
-ifeq ($(CONFIG_SYSLOG),y)
-CSRCS += lib_syslogstream.c
-endif
+CSRCS += lib_syslog.c lib_setlogmask.c
 
 # Add the syslog directory to the build
 
diff --git a/libc/syslog/lib_syslog.c b/libc/syslog/lib_syslog.c
index f6e35b35b56..408ffc10015 100644
--- a/libc/syslog/lib_syslog.c
+++ b/libc/syslog/lib_syslog.c
@@ -39,111 +39,12 @@
 
 #include <nuttx/config.h>
 
-#include <stdio.h>
 #include <syslog.h>
 
-#include <nuttx/init.h>
-#include <nuttx/clock.h>
-#include <nuttx/streams.h>
+#include <nuttx/syslog/syslog.h>
 
 #include "syslog/syslog.h"
 
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
-/****************************************************************************
- * Name: vsyslog_internal
- *
- * Description:
- *   This is the internal implementation of vsyslog (see the description of
- *   syslog and vsyslog below)
- *
- ****************************************************************************/
-
-static inline int vsyslog_internal(FAR const IPTR char *fmt, va_list ap)
-{
-#if defined(CONFIG_SYSLOG)
-  struct lib_outstream_s stream;
-#elif CONFIG_NFILE_DESCRIPTORS > 0
-  struct lib_rawoutstream_s stream;
-#elif defined(CONFIG_ARCH_LOWPUTC)
-  struct lib_outstream_s stream;
-#endif
-
-#if defined(CONFIG_SYSLOG_TIMESTAMP)
-  struct timespec ts;
-
-  /* Get the current time.  Since debug output may be generated very early
-   * in the start-up sequence, hardware timer support may not yet be
-   * available.
-   */
-
-  if (!OSINIT_HW_READY() || clock_systimespec(&ts) < 0)
-    {
-      /* Timer hardware is not available, or clock_systimespec failed */
-
-      ts.tv_sec  = 0;
-      ts.tv_nsec = 0;
-    }
-#endif
-
-#if defined(CONFIG_SYSLOG)
-  /* Wrap the low-level output in a stream object and let lib_vsprintf
-   * do the work.
-   */
-
-  lib_syslogstream((FAR struct lib_outstream_s *)&stream);
-
-#if defined(CONFIG_SYSLOG_TIMESTAMP)
-  /* Pre-pend the message with the current time, if available */
-
-  (void)lib_sprintf((FAR struct lib_outstream_s *)&stream,
-                    "[%6d.%06d]", ts.tv_sec, ts.tv_nsec/1000);
-
-#endif
-
-  return lib_vsprintf((FAR struct lib_outstream_s *)&stream, fmt, ap);
-
-#elif CONFIG_NFILE_DESCRIPTORS > 0
-  /* Wrap the stdout in a stream object and let lib_vsprintf
-   * do the work.
-   */
-
-  lib_rawoutstream(&stream, 1);
-
-#if defined(CONFIG_SYSLOG_TIMESTAMP)
-  /* Pre-pend the message with the current time, if available */
-
-  (void)lib_sprintf((FAR struct lib_outstream_s *)&stream,
-                    "[%6d.%06d]",  ts.tv_sec, ts.tv_nsec/1000);
-#endif
-
-  return lib_vsprintf(&stream.public, fmt, ap);
-
-#elif defined(CONFIG_ARCH_LOWPUTC)
-  /* Wrap the low-level output in a stream object and let lib_vsprintf
-   * do the work.
-   */
-
-  lib_lowoutstream((FAR struct lib_outstream_s *)&stream);
-
-#if defined(CONFIG_SYSLOG_TIMESTAMP)
-  /* Pre-pend the message with the current time, if available */
-
-  (void)lib_sprintf((FAR struct lib_outstream_s *)&stream,
-                    "[%6d.%06d]", ts.tv_sec, ts.tv_nsec/1000);
-#endif
-
-  return lib_vsprintf((FAR struct lib_outstream_s *)&stream, fmt, ap);
-
-#else /* CONFIG_SYSLOG */
-
-  return 0;
-
-#endif /* CONFIG_SYSLOG */
-}
-
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
@@ -166,9 +67,14 @@ int vsyslog(int priority, FAR const IPTR char *fmt, va_list ap)
 
   if ((g_syslog_mask & LOG_MASK(priority)) != 0)
     {
-      /* Yes.. let vsylog_internal do the deed */
+      /* Yes.. Perform the _vsyslog system call.
+       *
+       * NOTE:  The va_list parameter is passed by reference.  That is
+       * because the va_list is a structure in some compilers and passing
+       * of structures in the NuttX sycalls does not work.
+       */
 
-      ret = vsyslog_internal(fmt, ap);
+      ret = _vsyslog(priority, fmt, &ap);
     }
 
   return ret;
diff --git a/libc/syslog/syslog.h b/libc/syslog/syslog.h
index 3188d3f2d63..31ad268770e 100644
--- a/libc/syslog/syslog.h
+++ b/libc/syslog/syslog.h
@@ -41,7 +41,6 @@
  ****************************************************************************/
 
 #include <nuttx/config.h>
-#include <stdbool.h>
 
 /****************************************************************************
  * Public Data
diff --git a/mm/mm_heap/mm_initialize.c b/mm/mm_heap/mm_initialize.c
index d92a8d8de76..cacff9c0471 100644
--- a/mm/mm_heap/mm_initialize.c
+++ b/mm/mm_heap/mm_initialize.c
@@ -96,7 +96,7 @@ void mm_addregion(FAR struct mm_heap_s *heap, FAR void *heapstart,
   heapend  = MM_ALIGN_DOWN((uintptr_t)heapstart + (uintptr_t)heapsize);
   heapsize = heapend - heapbase;
 
-  mllinfo("Region %d: base=%p size=%u\n", IDX+1, heapstart, heapsize);
+  minfo("Region %d: base=%p size=%u\n", IDX+1, heapstart, heapsize);
 
   /* Add the size of this region to the total size of the heap */
 
@@ -157,7 +157,7 @@ void mm_initialize(FAR struct mm_heap_s *heap, FAR void *heapstart,
 {
   int i;
 
-  mllinfo("Heap: start=%p size=%u\n", heapstart, heapsize);
+  minfo("Heap: start=%p size=%u\n", heapstart, heapsize);
 
   /* The following two lines have cause problems for some older ZiLog
    * compilers in the past (but not the more recent).  Life is easier if we
diff --git a/net/arp/Kconfig b/net/arp/Kconfig
index 3004ab943e5..b4935e4c55c 100644
--- a/net/arp/Kconfig
+++ b/net/arp/Kconfig
@@ -65,7 +65,7 @@ endif # NET_ARP_SEND
 config NET_ARP_DUMP
 	bool "Dump ARP packet header"
 	default n
-	depends on DEBUG_FEATURES
+	depends on DEBUG_NET_INFO
 	---help---
 		Dump ARP packets to the SYSLOG device.
 
diff --git a/net/arp/arp_arpin.c b/net/arp/arp_arpin.c
index fcd84b4b85d..40c557c41d7 100644
--- a/net/arp/arp_arpin.c
+++ b/net/arp/arp_arpin.c
@@ -96,7 +96,7 @@ void arp_arpin(FAR struct net_driver_s *dev)
 
   if (dev->d_len < (sizeof(struct arp_hdr_s) + ETH_HDRLEN))
     {
-      nllerr("ERROR: Packet Too small\n");
+      nerr("ERROR: Packet Too small\n");
       dev->d_len = 0;
       return;
     }
@@ -107,7 +107,7 @@ void arp_arpin(FAR struct net_driver_s *dev)
   switch (arp->ah_opcode)
     {
       case HTONS(ARP_REQUEST):
-        nllinfo("ARP request for IP %04lx\n", (long)ipaddr);
+        ninfo("ARP request for IP %04lx\n", (long)ipaddr);
 
         /* ARP request. If it asked for our address, we send out a reply. */
 
@@ -139,7 +139,7 @@ void arp_arpin(FAR struct net_driver_s *dev)
         break;
 
       case HTONS(ARP_REPLY):
-        nllinfo("ARP reply for IP %04lx\n", (long)ipaddr);
+        ninfo("ARP reply for IP %04lx\n", (long)ipaddr);
 
         /* ARP reply. We insert or update the ARP table if it was meant
          * for us.
diff --git a/net/arp/arp_dump.c b/net/arp/arp_dump.c
index ba916db2f2d..8466763d859 100644
--- a/net/arp/arp_dump.c
+++ b/net/arp/arp_dump.c
@@ -69,20 +69,20 @@
 
 void arp_dump(FAR struct arp_hdr_s *arp)
 {
-  nllerr("  HW type: %04x Protocol: %04x\n",
-         arp->ah_hwtype, arp->ah_protocol);
-  nllerr("  HW len: %02x Proto len: %02x Operation: %04x\n",
-         arp->ah_hwlen, arp->ah_protolen, arp->ah_opcode);
-  nllerr("  Sender MAC: %02x:%02x:%02x:%02x:%02x:%02x IP: %d.%d.%d.%d\n",
-         arp->ah_shwaddr[0], arp->ah_shwaddr[1], arp->ah_shwaddr[2],
-         arp->ah_shwaddr[3], arp->ah_shwaddr[4], arp->ah_shwaddr[5],
-         arp->ah_sipaddr[0] & 0xff, arp->ah_sipaddr[0] >> 8,
-         arp->ah_sipaddr[1] & 0xff, arp->ah_sipaddr[1] >> 8);
-  nllerr("  Dest MAC:   %02x:%02x:%02x:%02x:%02x:%02x IP: %d.%d.%d.%d\n",
-         arp->ah_dhwaddr[0], arp->ah_dhwaddr[1], arp->ah_dhwaddr[2],
-         arp->ah_dhwaddr[3], arp->ah_dhwaddr[4], arp->ah_dhwaddr[5],
-         arp->ah_dipaddr[0] & 0xff, arp->ah_dipaddr[0] >> 8,
-         arp->ah_dipaddr[1] & 0xff, arp->ah_dipaddr[1] >> 8);
+  ninfo("  HW type: %04x Protocol: %04x\n",
+        arp->ah_hwtype, arp->ah_protocol);
+  ninfo("  HW len: %02x Proto len: %02x Operation: %04x\n",
+        arp->ah_hwlen, arp->ah_protolen, arp->ah_opcode);
+  ninfo("  Sender MAC: %02x:%02x:%02x:%02x:%02x:%02x IP: %d.%d.%d.%d\n",
+        arp->ah_shwaddr[0], arp->ah_shwaddr[1], arp->ah_shwaddr[2],
+        arp->ah_shwaddr[3], arp->ah_shwaddr[4], arp->ah_shwaddr[5],
+        arp->ah_sipaddr[0] & 0xff, arp->ah_sipaddr[0] >> 8,
+        arp->ah_sipaddr[1] & 0xff, arp->ah_sipaddr[1] >> 8);
+  ninfo("  Dest MAC:   %02x:%02x:%02x:%02x:%02x:%02x IP: %d.%d.%d.%d\n",
+        arp->ah_dhwaddr[0], arp->ah_dhwaddr[1], arp->ah_dhwaddr[2],
+        arp->ah_dhwaddr[3], arp->ah_dhwaddr[4], arp->ah_dhwaddr[5],
+        arp->ah_dipaddr[0] & 0xff, arp->ah_dipaddr[0] >> 8,
+        arp->ah_dipaddr[1] & 0xff, arp->ah_dipaddr[1] >> 8);
 }
 
 #endif /* CONFIG_NET_ARP_DUMP */
diff --git a/net/arp/arp_out.c b/net/arp/arp_out.c
index 8eaaf555a6f..667851a200f 100644
--- a/net/arp/arp_out.c
+++ b/net/arp/arp_out.c
@@ -231,7 +231,7 @@ void arp_out(FAR struct net_driver_s *dev)
       tabptr = arp_find(ipaddr);
       if (!tabptr)
         {
-           nllinfo("ARP request for IP %08lx\n", (unsigned long)ipaddr);
+           ninfo("ARP request for IP %08lx\n", (unsigned long)ipaddr);
 
           /* The destination address was not in our ARP table, so we
            * overwrite the IP packet with an ARP request.
diff --git a/net/arp/arp_send.c b/net/arp/arp_send.c
index 7fd6e78f095..faec0a13f46 100644
--- a/net/arp/arp_send.c
+++ b/net/arp/arp_send.c
@@ -102,7 +102,7 @@ static uint16_t arp_send_interrupt(FAR struct net_driver_s *dev,
 {
   FAR struct arp_send_s *state = (FAR struct arp_send_s *)priv;
 
-  nllinfo("flags: %04x sent: %d\n", flags, state->snd_sent);
+  ninfo("flags: %04x sent: %d\n", flags, state->snd_sent);
 
   if (state)
     {
@@ -110,7 +110,7 @@ static uint16_t arp_send_interrupt(FAR struct net_driver_s *dev,
 
       if ((flags & NETDEV_DOWN) != 0)
         {
-          nllerr("ERROR: Interface is down\n");
+          nerr("ERROR: Interface is down\n");
           arp_send_terminate(state, -ENETUNREACH);
           return flags;
         }
diff --git a/net/devif/devif_callback.c b/net/devif/devif_callback.c
index f5d794ad0b4..01986a3a9e8 100644
--- a/net/devif/devif_callback.c
+++ b/net/devif/devif_callback.c
@@ -260,7 +260,7 @@ FAR struct devif_callback_s *
 #ifdef CONFIG_DEBUG_FEATURES
   else
     {
-      nllerr("ERROR: Failed to allocate callback\n");
+      nerr("ERROR: Failed to allocate callback\n");
     }
 #endif
 
@@ -410,7 +410,7 @@ uint16_t devif_conn_event(FAR struct net_driver_s *dev, void *pvconn,
            * beginning of the list (which will be ignored on this pass)
            */
 
-          nllinfo("Call event=%p with flags=%04x\n", list->event, flags);
+          ninfo("Call event=%p with flags=%04x\n", list->event, flags);
           flags = list->event(dev, pvconn, list->priv, flags);
         }
 
@@ -475,7 +475,7 @@ uint16_t devif_dev_event(FAR struct net_driver_s *dev, void *pvconn,
            * beginning of the list (which will be ignored on this pass)
            */
 
-          nllinfo("Call event=%p with flags=%04x\n", cb->event, flags);
+          ninfo("Call event=%p with flags=%04x\n", cb->event, flags);
           flags = cb->event(dev, pvconn, cb->priv, flags);
         }
 
diff --git a/net/devif/ipv4_input.c b/net/devif/ipv4_input.c
index 05f661a39db..ee959754e23 100644
--- a/net/devif/ipv4_input.c
+++ b/net/devif/ipv4_input.c
@@ -339,8 +339,8 @@ int ipv4_input(FAR struct net_driver_s *dev)
       g_netstats.ipv4.drop++;
       g_netstats.ipv4.vhlerr++;
 #endif
-      nllwarn("WARNING: Invalid IP version or header length: %02x\n",
-              pbuf->vhl);
+      nwarn("WARNING: Invalid IP version or header length: %02x\n",
+            pbuf->vhl);
       goto drop;
     }
 
@@ -349,7 +349,7 @@ int ipv4_input(FAR struct net_driver_s *dev)
   hdrlen = NET_LL_HDRLEN(dev);
   if ((hdrlen + IPv4_HDRLEN) > dev->d_len)
     {
-      nllwarn("WARNING: Packet shorter than IPv4 header\n");
+      nwarn("WARNING: Packet shorter than IPv4 header\n");
       goto drop;
     }
 
@@ -369,7 +369,7 @@ int ipv4_input(FAR struct net_driver_s *dev)
     }
   else
     {
-      nllwarn("WARNING: IP packet shorter than length in IP header\n");
+      nwarn("WARNING: IP packet shorter than length in IP header\n");
       goto drop;
     }
 
@@ -388,7 +388,7 @@ int ipv4_input(FAR struct net_driver_s *dev)
       g_netstats.ipv4.drop++;
       g_netstats.ipv4.fragerr++;
 #endif
-      nllwarn("WARNING: IP fragment dropped\n");
+      nwarn("WARNING: IP fragment dropped\n");
       goto drop;
 #endif /* CONFIG_NET_TCP_REASSEMBLY */
     }
@@ -414,7 +414,7 @@ int ipv4_input(FAR struct net_driver_s *dev)
 #ifdef CONFIG_NET_ICMP
   if (net_ipv4addr_cmp(dev->d_ipaddr, INADDR_ANY))
     {
-      nllwarn("WARNING: No IP address assigned\n");
+      nwarn("WARNING: No IP address assigned\n");
       goto drop;
     }
 
@@ -447,7 +447,7 @@ int ipv4_input(FAR struct net_driver_s *dev)
       g_netstats.ipv4.drop++;
       g_netstats.ipv4.chkerr++;
 #endif
-      nllwarn("WARNING: Bad IP checksum\n");
+      nwarn("WARNING: Bad IP checksum\n");
       goto drop;
     }
 
@@ -495,7 +495,7 @@ int ipv4_input(FAR struct net_driver_s *dev)
         g_netstats.ipv4.protoerr++;
 #endif
 
-        nllwarn("WARNING: Unrecognized IP protocol\n");
+        nwarn("WARNING: Unrecognized IP protocol\n");
         goto drop;
     }
 
diff --git a/net/devif/ipv6_input.c b/net/devif/ipv6_input.c
index e3e7ba46f2d..d51d7aa8050 100644
--- a/net/devif/ipv6_input.c
+++ b/net/devif/ipv6_input.c
@@ -151,7 +151,7 @@ int ipv6_input(FAR struct net_driver_s *dev)
       g_netstats.ipv6.vhlerr++;
 #endif
 
-      nllwarn("WARNING: Invalid IPv6 version: %d\n", ipv6->vtc >> 4);
+      nwarn("WARNING: Invalid IPv6 version: %d\n", ipv6->vtc >> 4);
       goto drop;
     }
 
@@ -160,7 +160,7 @@ int ipv6_input(FAR struct net_driver_s *dev)
   hdrlen = NET_LL_HDRLEN(dev);
   if ((hdrlen + IPv6_HDRLEN) > dev->d_len)
     {
-      nllwarn("WARNING: Packet shorter than IPv6 header\n");
+      nwarn("WARNING: Packet shorter than IPv6 header\n");
       goto drop;
     }
 
@@ -187,7 +187,7 @@ int ipv6_input(FAR struct net_driver_s *dev)
     }
   else
     {
-      nllwarn("WARNING: IP packet shorter than length in IP header\n");
+      nwarn("WARNING: IP packet shorter than length in IP header\n");
       goto drop;
     }
 
@@ -216,7 +216,7 @@ int ipv6_input(FAR struct net_driver_s *dev)
        * packets.
        */
 
-      nllwarn("WARNING: No IP address assigned\n");
+      nwarn("WARNING: No IP address assigned\n");
       goto drop;
     }
 
@@ -279,7 +279,7 @@ int ipv6_input(FAR struct net_driver_s *dev)
         g_netstats.ipv6.protoerr++;
 #endif
 
-        nllwarn("WARNING: Unrecognized IP protocol: %04x\n", ipv6->proto);
+        nwarn("WARNING: Unrecognized IP protocol: %04x\n", ipv6->proto);
         goto drop;
     }
 
diff --git a/net/icmp/icmp_input.c b/net/icmp/icmp_input.c
index a0658482705..ff822e493a2 100644
--- a/net/icmp/icmp_input.c
+++ b/net/icmp/icmp_input.c
@@ -140,7 +140,7 @@ void icmp_input(FAR struct net_driver_s *dev)
         }
 #endif
 
-      nllinfo("Outgoing ICMP packet length: %d (%d)\n",
+      ninfo("Outgoing ICMP packet length: %d (%d)\n",
               dev->d_len, (picmp->len[0] << 8) | picmp->len[1]);
 
 #ifdef CONFIG_NET_STATISTICS
@@ -164,7 +164,7 @@ void icmp_input(FAR struct net_driver_s *dev)
 
   else
     {
-      nllwarn("WARNING: Unknown ICMP cmd: %d\n", picmp->type);
+      nwarn("WARNING: Unknown ICMP cmd: %d\n", picmp->type);
       goto typeerr;
     }
 
diff --git a/net/icmp/icmp_ping.c b/net/icmp/icmp_ping.c
index 73f29ff0daf..a121ddfbbdb 100644
--- a/net/icmp/icmp_ping.c
+++ b/net/icmp/icmp_ping.c
@@ -154,7 +154,7 @@ static uint16_t ping_interrupt(FAR struct net_driver_s *dev, FAR void *conn,
   FAR uint8_t *ptr;
   int i;
 
-  nllinfo("flags: %04x\n", flags);
+  ninfo("flags: %04x\n", flags);
 
   if (pstate)
     {
@@ -162,7 +162,7 @@ static uint16_t ping_interrupt(FAR struct net_driver_s *dev, FAR void *conn,
 
       if ((flags & NETDEV_DOWN) != 0)
         {
-          nllerr("ERROR: Interface is down\n");
+          nerr("ERROR: Interface is down\n");
           pstate->png_result = -ENETUNREACH;
           goto end_wait;
         }
@@ -177,8 +177,8 @@ static uint16_t ping_interrupt(FAR struct net_driver_s *dev, FAR void *conn,
         {
           FAR struct icmp_iphdr_s *icmp = (FAR struct icmp_iphdr_s *)conn;
 
-          nllinfo("ECHO reply: id=%d seqno=%d\n",
-                  ntohs(icmp->id), ntohs(icmp->seqno));
+          ninfo("ECHO reply: id=%d seqno=%d\n",
+                ntohs(icmp->id), ntohs(icmp->seqno));
 
           if (ntohs(icmp->id) == pstate->png_id)
             {
@@ -236,7 +236,7 @@ static uint16_t ping_interrupt(FAR struct net_driver_s *dev, FAR void *conn,
            * of the ICMP header.
            */
 
-          nllinfo("Send ECHO request: seqno=%d\n", pstate->png_seqno);
+          ninfo("Send ECHO request: seqno=%d\n", pstate->png_seqno);
 
           dev->d_sndlen = pstate->png_datlen + 4;
           icmp_send(dev, &pstate->png_addr);
@@ -262,12 +262,12 @@ static uint16_t ping_interrupt(FAR struct net_driver_s *dev, FAR void *conn,
                * that the destination address is not reachable.
                */
 
-              nllerr("ERROR:Not reachable\n");
+              nerr("ERROR:Not reachable\n");
               failcode = -ENETUNREACH;
             }
           else
             {
-              nllerr("ERROR:Ping timeout\n");
+              nerr("ERROR:Ping timeout\n");
               failcode = -ETIMEDOUT;
             }
 
@@ -283,7 +283,7 @@ static uint16_t ping_interrupt(FAR struct net_driver_s *dev, FAR void *conn,
   return flags;
 
 end_wait:
-  nllinfo("Resuming\n");
+  ninfo("Resuming\n");
 
   /* Do not allow any further callbacks */
 
@@ -397,7 +397,7 @@ int icmp_ping(in_addr_t addr, uint16_t id, uint16_t seqno, uint16_t datalen,
        * re-enabled when the task restarts.
        */
 
-      nllinfo("Start time: 0x%08x seqno: %d\n", state.png_time, seqno);
+      ninfo("Start time: 0x%08x seqno: %d\n", state.png_time, seqno);
       net_lockedwait(&state.png_sem);
 
       icmp_callback_free(dev, state.png_cb);
@@ -411,12 +411,12 @@ int icmp_ping(in_addr_t addr, uint16_t id, uint16_t seqno, uint16_t datalen,
 
   if (!state.png_result)
     {
-      nllinfo("Return seqno=%d\n", state.png_seqno);
+      ninfo("Return seqno=%d\n", state.png_seqno);
       return (int)state.png_seqno;
     }
   else
     {
-      nllerr("ERROR: Return error=%d\n", -state.png_result);
+      nerr("ERROR: Return error=%d\n", -state.png_result);
       return state.png_result;
     }
 }
diff --git a/net/icmp/icmp_send.c b/net/icmp/icmp_send.c
index b45d12acc36..768451c9d71 100644
--- a/net/icmp/icmp_send.c
+++ b/net/icmp/icmp_send.c
@@ -131,7 +131,7 @@ void icmp_send(FAR struct net_driver_s *dev, FAR in_addr_t *destaddr)
           picmp->icmpchksum = 0xffff;
         }
 
-      nllinfo("Outgoing ICMP packet length: %d (%d)\n",
+      ninfo("Outgoing ICMP packet length: %d (%d)\n",
               dev->d_len, (picmp->len[0] << 8) | picmp->len[1]);
 
 #ifdef CONFIG_NET_STATISTICS
diff --git a/net/icmpv6/icmpv6_advertise.c b/net/icmpv6/icmpv6_advertise.c
index 5ac4932c4dd..68d417873af 100644
--- a/net/icmpv6/icmpv6_advertise.c
+++ b/net/icmpv6/icmpv6_advertise.c
@@ -180,7 +180,7 @@ void icmpv6_advertise(FAR struct net_driver_s *dev,
 
   IFF_SET_NOARP(dev->d_flags);
 
-  nllinfo("Outgoing ICMPv6 Neighbor Advertise length: %d (%d)\n",
+  ninfo("Outgoing ICMPv6 Neighbor Advertise length: %d (%d)\n",
           dev->d_len, (icmp->len[0] << 8) | icmp->len[1]);
 
 #ifdef CONFIG_NET_STATISTICS
diff --git a/net/icmpv6/icmpv6_autoconfig.c b/net/icmpv6/icmpv6_autoconfig.c
index 26650bbae4b..eb404e78123 100644
--- a/net/icmpv6/icmpv6_autoconfig.c
+++ b/net/icmpv6/icmpv6_autoconfig.c
@@ -119,7 +119,7 @@ static uint16_t icmpv6_router_interrupt(FAR struct net_driver_s *dev,
 {
   FAR struct icmpv6_router_s *state = (FAR struct icmpv6_router_s *)priv;
 
-  nllinfo("flags: %04x sent: %d\n", flags, state->snd_sent);
+  ninfo("flags: %04x sent: %d\n", flags, state->snd_sent);
 
   if (state)
     {
@@ -127,7 +127,7 @@ static uint16_t icmpv6_router_interrupt(FAR struct net_driver_s *dev,
 
       if ((flags & NETDEV_DOWN) != 0)
         {
-          nllerr("ERROR: Interface is down\n");
+          nerr("ERROR: Interface is down\n");
           icmpv6_router_terminate(state, -ENETUNREACH);
           return flags;
         }
diff --git a/net/icmpv6/icmpv6_input.c b/net/icmpv6/icmpv6_input.c
index 31de97b3326..21f171fbf84 100644
--- a/net/icmpv6/icmpv6_input.c
+++ b/net/icmpv6/icmpv6_input.c
@@ -307,12 +307,12 @@ void icmpv6_input(FAR struct net_driver_s *dev)
 
     default:
       {
-        nllwarn("WARNING: Unknown ICMPv6 type: %d\n", icmp->type);
+        nwarn("WARNING: Unknown ICMPv6 type: %d\n", icmp->type);
         goto icmpv6_type_error;
       }
     }
 
-  nllinfo("Outgoing ICMPv6 packet length: %d (%d)\n",
+  ninfo("Outgoing ICMPv6 packet length: %d (%d)\n",
           dev->d_len, (icmp->len[0] << 8) | icmp->len[1]);
 
 #ifdef CONFIG_NET_STATISTICS
diff --git a/net/icmpv6/icmpv6_neighbor.c b/net/icmpv6/icmpv6_neighbor.c
index 0b4d9d13ce3..9bb02f34b4f 100644
--- a/net/icmpv6/icmpv6_neighbor.c
+++ b/net/icmpv6/icmpv6_neighbor.c
@@ -103,7 +103,7 @@ static uint16_t icmpv6_neighbor_interrupt(FAR struct net_driver_s *dev,
 {
   FAR struct icmpv6_neighbor_s *state = (FAR struct icmpv6_neighbor_s *)priv;
 
-  nllinfo("flags: %04x sent: %d\n", flags, state->snd_sent);
+  ninfo("flags: %04x sent: %d\n", flags, state->snd_sent);
 
   if (state)
     {
diff --git a/net/icmpv6/icmpv6_ping.c b/net/icmpv6/icmpv6_ping.c
index 7f3e7c8e4eb..507d09a266a 100644
--- a/net/icmpv6/icmpv6_ping.c
+++ b/net/icmpv6/icmpv6_ping.c
@@ -164,7 +164,7 @@ static void icmpv6_echo_request(FAR struct net_driver_s *dev,
   uint16_t reqlen;
   int i;
 
-  nllinfo("Send ECHO request: seqno=%d\n", pstate->png_seqno);
+  ninfo("Send ECHO request: seqno=%d\n", pstate->png_seqno);
 
   /* Set up the IPv6 header (most is probably already in place) */
 
@@ -217,8 +217,8 @@ static void icmpv6_echo_request(FAR struct net_driver_s *dev,
   dev->d_sndlen = reqlen;
   dev->d_len    = reqlen + IPv6_HDRLEN;
 
-  nllinfo("Outgoing ICMPv6 Echo Request length: %d (%d)\n",
-          dev->d_len, (icmp->len[0] << 8) | icmp->len[1]);
+  ninfo("Outgoing ICMPv6 Echo Request length: %d (%d)\n",
+        dev->d_len, (icmp->len[0] << 8) | icmp->len[1]);
 
 #ifdef CONFIG_NET_STATISTICS
   g_netstats.icmpv6.sent++;
@@ -253,7 +253,7 @@ static uint16_t ping_interrupt(FAR struct net_driver_s *dev, FAR void *conn,
 {
   FAR struct icmpv6_ping_s *pstate = (struct icmpv6_ping_s *)pvpriv;
 
-  nllinfo("flags: %04x\n", flags);
+  ninfo("flags: %04x\n", flags);
 
   if (pstate)
     {
@@ -261,7 +261,7 @@ static uint16_t ping_interrupt(FAR struct net_driver_s *dev, FAR void *conn,
 
       if ((flags & NETDEV_DOWN) != 0)
         {
-          nllerr("ERROR: Interface is down\n");
+          nerr("ERROR: Interface is down\n");
           pstate->png_result = -ENETUNREACH;
           goto end_wait;
         }
@@ -276,8 +276,8 @@ static uint16_t ping_interrupt(FAR struct net_driver_s *dev, FAR void *conn,
         {
           FAR struct icmpv6_echo_reply_s *reply = ICMPv6ECHOREPLY;
 
-          nllinfo("ECHO reply: id=%d seqno=%d\n",
-                  ntohs(reply->id), ntohs(reply->seqno));
+          ninfo("ECHO reply: id=%d seqno=%d\n",
+                ntohs(reply->id), ntohs(reply->seqno));
 
           if (ntohs(reply->id) == pstate->png_id)
             {
@@ -336,12 +336,12 @@ static uint16_t ping_interrupt(FAR struct net_driver_s *dev, FAR void *conn,
                * reason is that the destination address is not reachable.
                */
 
-              nllerr("ERROR: Not reachable\n");
+              nerr("ERROR: Not reachable\n");
               failcode = -ENETUNREACH;
             }
           else
             {
-              nllerr("ERROR: Ping timeout\n");
+              nerr("ERROR: Ping timeout\n");
               failcode = -ETIMEDOUT;
             }
 
@@ -357,7 +357,7 @@ static uint16_t ping_interrupt(FAR struct net_driver_s *dev, FAR void *conn,
   return flags;
 
 end_wait:
-  nllinfo("Resuming\n");
+  ninfo("Resuming\n");
 
   /* Do not allow any further callbacks */
 
@@ -471,7 +471,7 @@ int icmpv6_ping(net_ipv6addr_t addr, uint16_t id, uint16_t seqno,
        * re-enabled when the task restarts.
        */
 
-      nllinfo("Start time: 0x%08x seqno: %d\n", state.png_time, seqno);
+      ninfo("Start time: 0x%08x seqno: %d\n", state.png_time, seqno);
       net_lockedwait(&state.png_sem);
 
       icmpv6_callback_free(dev, state.png_cb);
@@ -485,12 +485,12 @@ int icmpv6_ping(net_ipv6addr_t addr, uint16_t id, uint16_t seqno,
 
   if (!state.png_result)
     {
-      nllinfo("Return seqno=%d\n", state.png_seqno);
+      ninfo("Return seqno=%d\n", state.png_seqno);
       return (int)state.png_seqno;
     }
   else
     {
-      nllerr("ERROR: Return error=%d\n", -state.png_result);
+      nerr("ERROR: Return error=%d\n", -state.png_result);
       return state.png_result;
     }
 }
diff --git a/net/icmpv6/icmpv6_radvertise.c b/net/icmpv6/icmpv6_radvertise.c
index 0b1ed2fea56..040d1e39f7a 100644
--- a/net/icmpv6/icmpv6_radvertise.c
+++ b/net/icmpv6/icmpv6_radvertise.c
@@ -242,7 +242,7 @@ void icmpv6_radvertise(FAR struct net_driver_s *dev)
 
   IFF_SET_NOARP(dev->d_flags);
 
-  nllinfo("Outgoing ICMPv6 Router Advertise length: %d (%d)\n",
+  ninfo("Outgoing ICMPv6 Router Advertise length: %d (%d)\n",
           dev->d_len, (icmp->len[0] << 8) | icmp->len[1]);
 
 #ifdef CONFIG_NET_STATISTICS
diff --git a/net/icmpv6/icmpv6_rsolicit.c b/net/icmpv6/icmpv6_rsolicit.c
index 81c87ac9112..db21f7f0a72 100644
--- a/net/icmpv6/icmpv6_rsolicit.c
+++ b/net/icmpv6/icmpv6_rsolicit.c
@@ -183,7 +183,7 @@ void icmpv6_rsolicit(FAR struct net_driver_s *dev)
    * outgoing packet.
    */
   dev->d_len += netdev_ipv6_hdrlen(dev);
-  nllinfo("Outgoing ICMPv6 Router Solicitation length: %d (%d)\n",
+  ninfo("Outgoing ICMPv6 Router Solicitation length: %d (%d)\n",
           dev->d_len, (icmp->len[0] << 8) | icmp->len[1]);
 
 #ifdef CONFIG_NET_STATISTICS
diff --git a/net/icmpv6/icmpv6_solicit.c b/net/icmpv6/icmpv6_solicit.c
index 08d99190ee7..5a9c6e868a7 100644
--- a/net/icmpv6/icmpv6_solicit.c
+++ b/net/icmpv6/icmpv6_solicit.c
@@ -211,7 +211,7 @@ void icmpv6_solicit(FAR struct net_driver_s *dev,
    * outgoing packet.
    */
   dev->d_len += netdev_ipv6_hdrlen(dev);
-  nllinfo("Outgoing ICMPv6 Neighbor Solicitation length: %d (%d)\n",
+  ninfo("Outgoing ICMPv6 Neighbor Solicitation length: %d (%d)\n",
           dev->d_len, (icmp->len[0] << 8) | icmp->len[1]);
 
 #ifdef CONFIG_NET_STATISTICS
diff --git a/net/igmp/igmp_group.c b/net/igmp/igmp_group.c
index dc1a3e36129..90e8fb65790 100644
--- a/net/igmp/igmp_group.c
+++ b/net/igmp/igmp_group.c
@@ -89,26 +89,18 @@
 #ifdef CONFIG_CPP_HAVE_VARARGS
 #  ifdef IGMP_GRPDEBUG
 #    define grperr(format, ...)    nerr(format, ##__VA_ARGS__)
-#    define grpllerr(format, ...)  nllerr(format, ##__VA_ARGS__)
 #    define grpinfo(format, ...)   ninfo(format, ##__VA_ARGS__)
-#    define grpllinfo(format, ...) nllinfo(format, ##__VA_ARGS__)
 #  else
 #    define grperr(x...)
-#    define grpllerr(x...)
 #    define grpinfo(x...)
-#    define grpllinfo(x...)
 #  endif
 #else
 #  ifdef IGMP_GRPDEBUG
 #    define grperr    nerr
-#    define grpllerr  nllerr
 #    define grpinfo   ninfo
-#    define grpllinfo nllinfo
 #  else
 #    define grperr    (void)
-#    define grpllerr  (void)
 #    define grpinfo   (void)
-#    define grpllinfo (void)
 #  endif
 #endif
 
@@ -194,7 +186,7 @@ void igmp_grpinit(void)
   FAR struct igmp_group_s *group;
   int i;
 
-  grpllinfo("Initializing\n");
+  grpinfo("Initializing\n");
 
 #if CONFIG_PREALLOC_IGMPGROUPS > 0
   for (i = 0; i < CONFIG_PREALLOC_IGMPGROUPS; i++)
@@ -222,24 +214,24 @@ FAR struct igmp_group_s *igmp_grpalloc(FAR struct net_driver_s *dev,
   FAR struct igmp_group_s *group;
   net_lock_t flags;
 
-  nllinfo("addr: %08x dev: %p\n", *addr, dev);
+  ninfo("addr: %08x dev: %p\n", *addr, dev);
   if (up_interrupt_context())
     {
 #if CONFIG_PREALLOC_IGMPGROUPS > 0
-      grpllinfo("Use a pre-allocated group entry\n");
+      grpinfo("Use a pre-allocated group entry\n");
       group = igmp_grpprealloc();
 #else
-      grpllerr("ERROR: Cannot allocate from interrupt handler\n");
+      grperr("ERROR: Cannot allocate from interrupt handler\n");
       group = NULL;
 #endif
     }
   else
     {
-      grpllinfo("Allocate from the heap\n");
+      grpinfo("Allocate from the heap\n");
       group = igmp_grpheapalloc();
     }
 
-  grpllinfo("group: %p\n", group);
+  grpinfo("group: %p\n", group);
 
   /* Check if we successfully allocated a group structure */
 
@@ -285,7 +277,7 @@ FAR struct igmp_group_s *igmp_grpfind(FAR struct net_driver_s *dev,
   FAR struct igmp_group_s *group;
   net_lock_t flags;
 
-  grpllinfo("Searching for addr %08x\n", (int)*addr);
+  grpinfo("Searching for addr %08x\n", (int)*addr);
 
   /* We must disable interrupts because we don't which context we were
    * called from.
@@ -296,10 +288,10 @@ FAR struct igmp_group_s *igmp_grpfind(FAR struct net_driver_s *dev,
        group;
        group = group->next)
     {
-      grpllinfo("Compare: %08x vs. %08x\n", group->grpaddr, *addr);
+      grpinfo("Compare: %08x vs. %08x\n", group->grpaddr, *addr);
       if (net_ipv4addr_cmp(group->grpaddr, *addr))
         {
-          grpllinfo("Match!\n");
+          grpinfo("Match!\n");
           break;
         }
     }
@@ -325,13 +317,13 @@ FAR struct igmp_group_s *igmp_grpallocfind(FAR struct net_driver_s *dev,
 {
   FAR struct igmp_group_s *group = igmp_grpfind(dev, addr);
 
-  grpllinfo("group: %p addr: %08x\n", group, (int)*addr);
+  grpinfo("group: %p addr: %08x\n", group, (int)*addr);
   if (!group)
     {
       group = igmp_grpalloc(dev, addr);
     }
 
-  grpllinfo("group: %p\n", group);
+  grpinfo("group: %p\n", group);
   return group;
 }
 
@@ -350,7 +342,7 @@ void igmp_grpfree(FAR struct net_driver_s *dev, FAR struct igmp_group_s *group)
 {
   net_lock_t flags;
 
-  grpllinfo("Free: %p flags: %02x\n", group, group->flags);
+  grpinfo("Free: %p flags: %02x\n", group, group->flags);
 
   /* Cancel the wdog */
 
@@ -376,7 +368,7 @@ void igmp_grpfree(FAR struct net_driver_s *dev, FAR struct igmp_group_s *group)
 #if CONFIG_PREALLOC_IGMPGROUPS > 0
   if (IS_PREALLOCATED(group->flags))
     {
-      grpllinfo("Put back on free list\n");
+      grpinfo("Put back on free list\n");
       sq_addlast((FAR sq_entry_t *)group, &g_freelist);
       net_unlock(flags);
     }
@@ -388,7 +380,7 @@ void igmp_grpfree(FAR struct net_driver_s *dev, FAR struct igmp_group_s *group)
        */
 
       net_unlock(flags);
-      grpllinfo("Call sched_kfree()\n");
+      grpinfo("Call sched_kfree()\n");
       sched_kfree(group);
     }
 }
diff --git a/net/igmp/igmp_input.c b/net/igmp/igmp_input.c
index 01d645715ce..d89569b5098 100644
--- a/net/igmp/igmp_input.c
+++ b/net/igmp/igmp_input.c
@@ -117,14 +117,14 @@ void igmp_input(struct net_driver_s *dev)
   in_addr_t grpaddr;
   unsigned int ticks;
 
-  nllinfo("IGMP message: %04x%04x\n", IGMPBUF->destipaddr[1], IGMPBUF->destipaddr[0]);
+  ninfo("IGMP message: %04x%04x\n", IGMPBUF->destipaddr[1], IGMPBUF->destipaddr[0]);
 
   /* Verify the message length */
 
   if (dev->d_len < NET_LL_HDRLEN(dev) + IPIGMP_HDRLEN)
     {
       IGMP_STATINCR(g_netstats.igmp.length_errors);
-      nllwarn("WARNING: Length error\n");
+      nwarn("WARNING: Length error\n");
       return;
     }
 
@@ -133,7 +133,7 @@ void igmp_input(struct net_driver_s *dev)
   if (net_chksum((FAR uint16_t *)&IGMPBUF->type, IGMP_HDRLEN) != 0)
     {
       IGMP_STATINCR(g_netstats.igmp.chksum_errors);
-      nllwarn("WARNING: Checksum error\n");
+      nwarn("WARNING: Checksum error\n");
       return;
     }
 
@@ -143,7 +143,7 @@ void igmp_input(struct net_driver_s *dev)
   group = igmp_grpallocfind(dev, &destipaddr);
   if (!group)
     {
-      nllerr("ERROR: Failed to allocate/find group: %08x\n", destipaddr);
+      nerr("ERROR: Failed to allocate/find group: %08x\n", destipaddr);
       return;
     }
 
@@ -186,13 +186,13 @@ void igmp_input(struct net_driver_s *dev)
 
                 /* This is the general query */
 
-                nllinfo("General multicast query\n");
+                ninfo("General multicast query\n");
                 if (IGMPBUF->maxresp == 0)
                   {
                     IGMP_STATINCR(g_netstats.igmp.v1_received);
                     IGMPBUF->maxresp = 10;
 
-                    nllwarn("WARNING: V1 not implemented\n");
+                    nwarn("WARNING: V1 not implemented\n");
                   }
 
                 IGMP_STATINCR(g_netstats.igmp.query_received);
@@ -216,7 +216,7 @@ void igmp_input(struct net_driver_s *dev)
               }
             else /* if (IGMPBUF->grpaddr != 0) */
               {
-                nllinfo("Group-specific multicast queury\n");
+                ninfo("Group-specific multicast queury\n");
 
                 /* We first need to re-lookup the group since we used dest last time.
                  * Use the incoming IPaddress!
@@ -238,10 +238,10 @@ void igmp_input(struct net_driver_s *dev)
 
         else if (group->grpaddr != 0)
           {
-            nllinfo("Unicast query\n");
+            ninfo("Unicast query\n");
             IGMP_STATINCR(g_netstats.igmp.ucast_query);
 
-            nllinfo("Query to a specific group with the group address as destination\n");
+            ninfo("Query to a specific group with the group address as destination\n");
 
             ticks = net_dsec2tick((int)IGMPBUF->maxresp);
             if (IS_IDLEMEMBER(group->flags) || igmp_cmptimer(group, ticks))
@@ -254,7 +254,7 @@ void igmp_input(struct net_driver_s *dev)
 
       case IGMPv2_MEMBERSHIP_REPORT:
         {
-          nllinfo("Membership report\n");
+          ninfo("Membership report\n");
 
           IGMP_STATINCR(g_netstats.igmp.report_received);
           if (!IS_IDLEMEMBER(group->flags))
@@ -270,7 +270,7 @@ void igmp_input(struct net_driver_s *dev)
 
       default:
         {
-          nllwarn("WARNING: Unexpected msg %02x\n", IGMPBUF->type);
+          nwarn("WARNING: Unexpected msg %02x\n", IGMPBUF->type);
         }
       break;
     }
diff --git a/net/igmp/igmp_poll.c b/net/igmp/igmp_poll.c
index a789ba8331d..0fe705868fa 100644
--- a/net/igmp/igmp_poll.c
+++ b/net/igmp/igmp_poll.c
@@ -87,8 +87,8 @@ static inline void igmp_sched_send(FAR struct net_driver_s *dev,
   if (group->msgid == IGMPv2_MEMBERSHIP_REPORT)
     {
       dest = &group->grpaddr;
-      nllinfo("Send IGMPv2_MEMBERSHIP_REPORT, dest=%08x flags=%02x\n",
-               *dest, group->flags);
+      ninfo("Send IGMPv2_MEMBERSHIP_REPORT, dest=%08x flags=%02x\n",
+             *dest, group->flags);
       IGMP_STATINCR(g_netstats.igmp.report_sched);
       SET_LASTREPORT(group->flags); /* Remember we were the last to report */
     }
@@ -96,8 +96,8 @@ static inline void igmp_sched_send(FAR struct net_driver_s *dev,
     {
       DEBUGASSERT(group->msgid == IGMP_LEAVE_GROUP);
       dest = &g_ipv4_allrouters;
-      nllinfo("Send IGMP_LEAVE_GROUP, dest=%08x flags=%02x\n",
-               *dest, group->flags);
+      ninfo("Send IGMP_LEAVE_GROUP, dest=%08x flags=%02x\n",
+             *dest, group->flags);
       IGMP_STATINCR(g_netstats.igmp.leave_sched);
     }
 
@@ -114,7 +114,7 @@ static inline void igmp_sched_send(FAR struct net_driver_s *dev,
 
   if (IS_WAITMSG(group->flags))
     {
-      nllinfo("Awakening waiter\n");
+      ninfo("Awakening waiter\n");
       sem_post(&group->sem);
     }
 }
@@ -143,7 +143,7 @@ void igmp_poll(FAR struct net_driver_s *dev)
 {
   FAR struct igmp_group_s *group;
 
-  nllinfo("Entry\n");
+  ninfo("Entry\n");
 
   /* Setup the poll operation */
 
diff --git a/net/igmp/igmp_send.c b/net/igmp/igmp_send.c
index b05b2ca40a9..7e51068ab25 100644
--- a/net/igmp/igmp_send.c
+++ b/net/igmp/igmp_send.c
@@ -116,7 +116,7 @@ static uint16_t igmp_chksum(FAR uint8_t *buffer, int buflen)
 void igmp_send(FAR struct net_driver_s *dev, FAR struct igmp_group_s *group,
                FAR in_addr_t *destipaddr)
 {
-  nllinfo("msgid: %02x destipaddr: %08x\n", group->msgid, (int)*destipaddr);
+  ninfo("msgid: %02x destipaddr: %08x\n", group->msgid, (int)*destipaddr);
 
   /* The total length to send is the size of the IP and IGMP headers and 4
    * bytes for the ROUTER ALERT (and, eventually, the Ethernet header)
@@ -169,7 +169,7 @@ void igmp_send(FAR struct net_driver_s *dev, FAR struct igmp_group_s *group,
   IGMP_STATINCR(g_netstats.igmp.poll_send);
   IGMP_STATINCR(g_netstats.ipv4.sent);
 
-  nllinfo("Outgoing IGMP packet length: %d (%d)\n",
+  ninfo("Outgoing IGMP packet length: %d (%d)\n",
           dev->d_len, (IGMPBUF->len[0] << 8) | IGMPBUF->len[1]);
   igmp_dumppkt(RA, IPIGMP_HDRLEN + RASIZE);
 }
diff --git a/net/igmp/igmp_timer.c b/net/igmp/igmp_timer.c
index 0725d1805ea..e413eb75fb8 100644
--- a/net/igmp/igmp_timer.c
+++ b/net/igmp/igmp_timer.c
@@ -74,26 +74,18 @@
 #ifdef CONFIG_CPP_HAVE_VARARGS
 #  ifdef IGMP_GTMRDEBUG
 #    define gtmrerr(format, ...)    nerr(format, ##__VA_ARGS__)
-#    define gtmrllerr(format, ...)  nllerr(format, ##__VA_ARGS__)
 #    define gtmrinfo(format, ...)   ninfo(format, ##__VA_ARGS__)
-#    define gtmrllinfo(format, ...) nllinfo(format, ##__VA_ARGS__)
 #  else
 #    define gtmrerr(x...)
-#    define gtmrllerr(x...)
 #    define gtmrinfo(x...)
-#    define gtmrllinfo(x...)
 #  endif
 #else
 #  ifdef IGMP_GTMRDEBUG
 #    define gtmrerr    nerr
-#    define gtmrllerr  nllerr
 #    define gtmrinfo   ninfo
-#    define gtmrllinfo nllinfo
 #  else
 #    define gtmrerr    (void)
-#    define gtmrllerr  (void)
 #    define gtmrinfo   (void)
-#    define gtmrllinfo (void)
 #  endif
 #endif
 
@@ -119,7 +111,7 @@ static void igmp_timeout(int argc, uint32_t arg, ...)
 
   /* If the state is DELAYING_MEMBER then we send a report for this group */
 
-  nllinfo("Timeout!\n");
+  ninfo("Timeout!\n");
   group = (FAR struct igmp_group_s *)arg;
   DEBUGASSERT(argc == 1 && group);
 
@@ -170,7 +162,7 @@ void igmp_startticks(FAR struct igmp_group_s *group, unsigned int ticks)
 
   /* Start the timer */
 
-  gtmrllinfo("ticks: %d\n", ticks);
+  gtmrinfo("ticks: %d\n", ticks);
 
   ret = wd_start(group->wdog, ticks, igmp_timeout, 1, (uint32_t)group);
 
diff --git a/net/iob/iob_add_queue.c b/net/iob/iob_add_queue.c
index 16c615d0e89..b59646ef8d4 100644
--- a/net/iob/iob_add_queue.c
+++ b/net/iob/iob_add_queue.c
@@ -150,7 +150,7 @@ int iob_tryadd_queue(FAR struct iob_s *iob, FAR struct iob_queue_s *iobq)
   qentry = iob_tryalloc_qentry();
   if (!qentry)
     {
-      nllerr("ERROR: Failed to allocate a container\n");
+      nerr("ERROR: Failed to allocate a container\n");
       return -ENOMEM;
     }
 
diff --git a/net/iob/iob_copyin.c b/net/iob/iob_copyin.c
index 53c9379e3b9..3507bc50048 100644
--- a/net/iob/iob_copyin.c
+++ b/net/iob/iob_copyin.c
@@ -97,7 +97,7 @@ static int iob_copyin_internal(FAR struct iob_s *iob, FAR const uint8_t *src,
   unsigned int avail;
   unsigned int total = len;
 
-  nllinfo("iob=%p len=%u offset=%u\n", iob, len, offset);
+  ninfo("iob=%p len=%u offset=%u\n", iob, len, offset);
   DEBUGASSERT(iob && src);
 
   /* The offset must applied to data that is already in the I/O buffer chain */
@@ -130,7 +130,7 @@ static int iob_copyin_internal(FAR struct iob_s *iob, FAR const uint8_t *src,
       dest  = &iob->io_data[iob->io_offset + offset];
       avail = iob->io_len - offset;
 
-      nllinfo("iob=%p avail=%u len=%u next=%p\n", iob, avail, len, next);
+      ninfo("iob=%p avail=%u len=%u next=%p\n", iob, avail, len, next);
 
       /* Will the rest of the copy fit into this buffer, overwriting
        * existing data.
@@ -187,8 +187,8 @@ static int iob_copyin_internal(FAR struct iob_s *iob, FAR const uint8_t *src,
       /* Copy from the user buffer to the I/O buffer.  */
 
       memcpy(dest, src, ncopy);
-      nllinfo("iob=%p Copy %u bytes new len=%u\n",
-              iob, ncopy, iob->io_len);
+      ninfo("iob=%p Copy %u bytes new len=%u\n",
+            iob, ncopy, iob->io_len);
 
       /* Adjust the total length of the copy and the destination address in
        * the user buffer.
@@ -227,7 +227,7 @@ static int iob_copyin_internal(FAR struct iob_s *iob, FAR const uint8_t *src,
           /* Add the new, empty I/O buffer to the end of the buffer chain. */
 
           iob->io_flink = next;
-          nllinfo("iob=%p added to the chain\n", iob);
+          ninfo("iob=%p added to the chain\n", iob);
         }
 
       iob = next;
diff --git a/net/iob/iob_dump.c b/net/iob/iob_dump.c
index d8dab7b684d..2be0198a5bd 100644
--- a/net/iob/iob_dump.c
+++ b/net/iob/iob_dump.c
@@ -77,7 +77,7 @@ void iob_dump(FAR const char *msg, FAR struct iob_s *iob, unsigned int len,
   unsigned int cndx;
 
   head = iob;
-  lowsyslog(LOG_DEBUG, "%s: iob=%p pktlen=%d\n", msg, head, head->io_pktlen);
+  syslog(LOG_DEBUG, "%s: iob=%p pktlen=%d\n", msg, head, head->io_pktlen);
 
   /* Check if the offset is beyond the data in the I/O buffer chain */
 
@@ -92,8 +92,8 @@ void iob_dump(FAR const char *msg, FAR struct iob_s *iob, unsigned int len,
 
   for (; iob; iob = iob->io_flink)
     {
-      lowsyslog(LOG_DEBUG, "  iob=%p len=%d offset=%d\n",
-                iob, iob->io_len, iob->io_offset);
+      syslog(LOG_DEBUG, "  iob=%p len=%d offset=%d\n",
+             iob, iob->io_len, iob->io_offset);
     }
 
   /* Get the amount of data to be displayed, limited by the amount that we
@@ -117,47 +117,47 @@ void iob_dump(FAR const char *msg, FAR struct iob_s *iob, unsigned int len,
 
       if (nbytes > 0)
         {
-          lowsyslog(LOG_DEBUG, "  %04x: ", offset);
+          syslog(LOG_DEBUG, "  %04x: ", offset);
 
           for (cndx = 0; cndx < 32; cndx++)
             {
               if (cndx == 16)
                 {
-                  lowsyslog(LOG_DEBUG, " ");
+                  syslog(LOG_DEBUG, " ");
                 }
 
               if ((lndx + cndx) < len)
                 {
-                  lowsyslog(LOG_DEBUG, "%02x", data[cndx]);
+                  syslog(LOG_DEBUG, "%02x", data[cndx]);
                 }
               else
                 {
-                  lowsyslog(LOG_DEBUG, "  ");
+                  syslog(LOG_DEBUG, "  ");
                 }
             }
 
-          lowsyslog(LOG_DEBUG, " ");
+          syslog(LOG_DEBUG, " ");
           for (cndx = 0; cndx < 32; cndx++)
             {
               if (cndx == 16)
                 {
-                  lowsyslog(LOG_DEBUG, " ");
+                  syslog(LOG_DEBUG, " ");
                 }
 
               if ((lndx + cndx) < len)
                 {
                   if (data[cndx] >= 0x20 && data[cndx] < 0x7f)
                     {
-                      lowsyslog(LOG_DEBUG, "%c", data[cndx]);
+                      syslog(LOG_DEBUG, "%c", data[cndx]);
                     }
                   else
                     {
-                      lowsyslog(LOG_DEBUG, ".");
+                      syslog(LOG_DEBUG, ".");
                     }
                 }
             }
 
-          lowsyslog(LOG_DEBUG, "\n");
+          syslog(LOG_DEBUG, "\n");
         }
     }
 }
diff --git a/net/iob/iob_free.c b/net/iob/iob_free.c
index 67a3016088f..38eb5fb3458 100644
--- a/net/iob/iob_free.c
+++ b/net/iob/iob_free.c
@@ -74,8 +74,8 @@ FAR struct iob_s *iob_free(FAR struct iob_s *iob)
   FAR struct iob_s *next = iob->io_flink;
   irqstate_t flags;
 
-  nllinfo("iob=%p io_pktlen=%u io_len=%u next=%p\n",
-          iob, iob->io_pktlen, iob->io_len, next);
+  ninfo("iob=%p io_pktlen=%u io_len=%u next=%p\n",
+        iob, iob->io_pktlen, iob->io_len, next);
 
   /* Copy the data that only exists in the head of a I/O buffer chain into
    * the next entry.
@@ -104,8 +104,8 @@ FAR struct iob_s *iob_free(FAR struct iob_s *iob)
           DEBUGASSERT(next->io_len == 0 && next->io_flink == NULL);
         }
 
-      nllinfo("next=%p io_pktlen=%u io_len=%u\n",
-               next, next->io_pktlen, next->io_len);
+      ninfo("next=%p io_pktlen=%u io_len=%u\n",
+            next, next->io_pktlen, next->io_len);
     }
 
   /* Free the I/O buffer by adding it to the head of the free list. We don't
diff --git a/net/iob/iob_trimhead.c b/net/iob/iob_trimhead.c
index ce4f642588c..c11cfa43b99 100644
--- a/net/iob/iob_trimhead.c
+++ b/net/iob/iob_trimhead.c
@@ -78,7 +78,7 @@ FAR struct iob_s *iob_trimhead(FAR struct iob_s *iob, unsigned int trimlen)
 {
   uint16_t pktlen;
 
-  nllinfo("iob=%p trimlen=%d\n", iob, trimlen);
+  ninfo("iob=%p trimlen=%d\n", iob, trimlen);
 
   if (iob && trimlen > 0)
     {
@@ -89,8 +89,8 @@ FAR struct iob_s *iob_trimhead(FAR struct iob_s *iob, unsigned int trimlen)
         {
           /* Do we trim this entire I/O buffer away? */
 
-          nllinfo("iob=%p io_len=%d pktlen=%d trimlen=%d\n",
-                  iob, iob->io_len, pktlen, trimlen);
+          ninfo("iob=%p io_len=%d pktlen=%d trimlen=%d\n",
+                iob, iob->io_len, pktlen, trimlen);
 
           if (iob->io_len <= trimlen)
             {
@@ -120,7 +120,7 @@ FAR struct iob_s *iob_trimhead(FAR struct iob_s *iob, unsigned int trimlen)
 
               /* Free this entry and set the next I/O buffer as the head */
 
-              nllinfo("iob=%p: Freeing\n", iob);
+              ninfo("iob=%p: Freeing\n", iob);
               (void)iob_free(iob);
               iob = next;
             }
diff --git a/net/iob/iob_trimtail.c b/net/iob/iob_trimtail.c
index cfcfd68b264..039e3c6db7c 100644
--- a/net/iob/iob_trimtail.c
+++ b/net/iob/iob_trimtail.c
@@ -72,7 +72,7 @@ FAR struct iob_s *iob_trimtail(FAR struct iob_s *iob, unsigned int trimlen)
   FAR struct iob_s *last;
   int len;
 
-  nllinfo("iob=%p pktlen=%d trimlen=%d\n", iob, iob->io_pktlen, trimlen);
+  ninfo("iob=%p pktlen=%d trimlen=%d\n", iob, iob->io_pktlen, trimlen);
 
   if (iob && trimlen > 0)
     {
@@ -101,7 +101,7 @@ FAR struct iob_s *iob_trimtail(FAR struct iob_s *iob, unsigned int trimlen)
            * I/O buffer away?
            */
 
-          nllinfo("iob=%p len=%d vs %d\n", last, last->io_len, len);
+          ninfo("iob=%p len=%d vs %d\n", last, last->io_len, len);
           if (last->io_len <= len)
             {
               /* Yes.. Consume the entire buffer */
diff --git a/net/neighbor/neighbor_add.c b/net/neighbor/neighbor_add.c
index dd09f93596f..fed15353ae0 100644
--- a/net/neighbor/neighbor_add.c
+++ b/net/neighbor/neighbor_add.c
@@ -76,17 +76,17 @@ void neighbor_add(FAR net_ipv6addr_t ipaddr, FAR struct neighbor_addr_s *addr)
   int     oldest_ndx;
   int     i;
 
-  nllinfo("Add neighbor: %04x:%04x:%04x:%04x:%04x:%04x:%04x:%04x\n",
-          ntohs(ipaddr[0]), ntohs(ipaddr[1]), ntohs(ipaddr[2]),
-          ntohs(ipaddr[3]), ntohs(ipaddr[4]), ntohs(ipaddr[5]),
-          ntohs(ipaddr[6]), ntohs(ipaddr[7]));
-  nllinfo("  at: %02x:%02x:%02x:%02x:%02x:%02x\n",
-          addr->na_addr.ether_addr_octet[0],
-          addr->na_addr.ether_addr_octet[1],
-          addr->na_addr.ether_addr_octet[2],
-          addr->na_addr.ether_addr_octet[3],
-          addr->na_addr.ether_addr_octet[4],
-          addr->na_addr.ether_addr_octet[5]);
+  ninfo("Add neighbor: %04x:%04x:%04x:%04x:%04x:%04x:%04x:%04x\n",
+        ntohs(ipaddr[0]), ntohs(ipaddr[1]), ntohs(ipaddr[2]),
+        ntohs(ipaddr[3]), ntohs(ipaddr[4]), ntohs(ipaddr[5]),
+        ntohs(ipaddr[6]), ntohs(ipaddr[7]));
+  ninfo("  at: %02x:%02x:%02x:%02x:%02x:%02x\n",
+        addr->na_addr.ether_addr_octet[0],
+        addr->na_addr.ether_addr_octet[1],
+        addr->na_addr.ether_addr_octet[2],
+        addr->na_addr.ether_addr_octet[3],
+        addr->na_addr.ether_addr_octet[4],
+        addr->na_addr.ether_addr_octet[5]);
 
   /* Find the first unused entry or the oldest used entry. */
 
diff --git a/net/neighbor/neighbor_findentry.c b/net/neighbor/neighbor_findentry.c
index 8d9949dff7e..fe6a7b7b319 100644
--- a/net/neighbor/neighbor_findentry.c
+++ b/net/neighbor/neighbor_findentry.c
@@ -72,10 +72,10 @@ FAR struct neighbor_entry *neighbor_findentry(const net_ipv6addr_t ipaddr)
 {
   int i;
 
-  nllinfo("Find neighbor: %04x:%04x:%04x:%04x:%04x:%04x:%04x:%04x\n",
-          ntohs(ipaddr[0]), ntohs(ipaddr[1]), ntohs(ipaddr[2]),
-          ntohs(ipaddr[3]), ntohs(ipaddr[4]), ntohs(ipaddr[5]),
-          ntohs(ipaddr[6]), ntohs(ipaddr[7]));
+  ninfo("Find neighbor: %04x:%04x:%04x:%04x:%04x:%04x:%04x:%04x\n",
+        ntohs(ipaddr[0]), ntohs(ipaddr[1]), ntohs(ipaddr[2]),
+        ntohs(ipaddr[3]), ntohs(ipaddr[4]), ntohs(ipaddr[5]),
+        ntohs(ipaddr[6]), ntohs(ipaddr[7]));
 
   for (i = 0; i < CONFIG_NET_IPv6_NCONF_ENTRIES; ++i)
     {
@@ -83,18 +83,18 @@ FAR struct neighbor_entry *neighbor_findentry(const net_ipv6addr_t ipaddr)
 
       if (net_ipv6addr_cmp(neighbor->ne_ipaddr, ipaddr))
         {
-          nllinfo("  at: %02x:%02x:%02x:%02x:%02x:%02x\n",
-                  neighbor->ne_addr.na_addr.ether_addr_octet[0],
-                  neighbor->ne_addr.na_addr.ether_addr_octet[1],
-                  neighbor->ne_addr.na_addr.ether_addr_octet[2],
-                  neighbor->ne_addr.na_addr.ether_addr_octet[3],
-                  neighbor->ne_addr.na_addr.ether_addr_octet[4],
-                  neighbor->ne_addr.na_addr.ether_addr_octet[5]);
+          ninfo("  at: %02x:%02x:%02x:%02x:%02x:%02x\n",
+                neighbor->ne_addr.na_addr.ether_addr_octet[0],
+                neighbor->ne_addr.na_addr.ether_addr_octet[1],
+                neighbor->ne_addr.na_addr.ether_addr_octet[2],
+                neighbor->ne_addr.na_addr.ether_addr_octet[3],
+                neighbor->ne_addr.na_addr.ether_addr_octet[4],
+                neighbor->ne_addr.na_addr.ether_addr_octet[5]);
 
           return &g_neighbors[i];
         }
     }
 
-  nllinfo("  Not found\n");
+  ninfo("  Not found\n");
   return NULL;
 }
diff --git a/net/neighbor/neighbor_lookup.c b/net/neighbor/neighbor_lookup.c
index a0a3e856d71..01f029b69fa 100644
--- a/net/neighbor/neighbor_lookup.c
+++ b/net/neighbor/neighbor_lookup.c
@@ -76,13 +76,13 @@ FAR const struct neighbor_addr_s *neighbor_lookup(const net_ipv6addr_t ipaddr)
   neighbor = neighbor_findentry(ipaddr);
   if (neighbor != NULL)
     {
-      nllinfo("Lookup neighbor: %02x:%02x:%02x:%02x:%02x:%02x\n",
-              neighbor->ne_addr.na_addr.ether_addr_octet[0],
-              neighbor->ne_addr.na_addr.ether_addr_octet[1],
-              neighbor->ne_addr.na_addr.ether_addr_octet[2],
-              neighbor->ne_addr.na_addr.ether_addr_octet[3],
-              neighbor->ne_addr.na_addr.ether_addr_octet[4],
-              neighbor->ne_addr.na_addr.ether_addr_octet[5]);
+      ninfo("Lookup neighbor: %02x:%02x:%02x:%02x:%02x:%02x\n",
+            neighbor->ne_addr.na_addr.ether_addr_octet[0],
+            neighbor->ne_addr.na_addr.ether_addr_octet[1],
+            neighbor->ne_addr.na_addr.ether_addr_octet[2],
+            neighbor->ne_addr.na_addr.ether_addr_octet[3],
+            neighbor->ne_addr.na_addr.ether_addr_octet[4],
+            neighbor->ne_addr.na_addr.ether_addr_octet[5]);
 
       return &neighbor->ne_addr;
     }
diff --git a/net/neighbor/neighbor_out.c b/net/neighbor/neighbor_out.c
index 8e40982b9cc..c00253ffe3e 100644
--- a/net/neighbor/neighbor_out.c
+++ b/net/neighbor/neighbor_out.c
@@ -227,7 +227,7 @@ void neighbor_out(FAR struct net_driver_s *dev)
       naddr = neighbor_lookup(ipaddr);
       if (!naddr)
         {
-           nllinfo("IPv6 Neighbor solicitation for IPv6\n");
+           ninfo("IPv6 Neighbor solicitation for IPv6\n");
 
           /* The destination address was not in our Neighbor Table, so we
            * overwrite the IPv6 packet with an ICMDv6 Neighbor Solicitation
@@ -253,6 +253,6 @@ void neighbor_out(FAR struct net_driver_s *dev)
    */
 
   dev->d_len += netdev_ipv6_hdrlen(dev);
-  nllinfo("Outgoing IPv6 Packet length: %d (%d)\n",
+  ninfo("Outgoing IPv6 Packet length: %d (%d)\n",
           dev->d_len, (ip->len[0] << 8) | ip->len[1]);
 }
diff --git a/net/netdev/netdev_register.c b/net/netdev/netdev_register.c
index bdd9a812fbd..81bfe8232b3 100644
--- a/net/netdev/netdev_register.c
+++ b/net/netdev/netdev_register.c
@@ -248,7 +248,7 @@ int netdev_register(FAR struct net_driver_s *dev, enum net_lltype_e lltype)
 #endif
 
           default:
-            nllerr("ERROR: Unrecognized link type: %d\n", lltype);
+            nerr("ERROR: Unrecognized link type: %d\n", lltype);
             return -EINVAL;
         }
 
@@ -319,13 +319,13 @@ int netdev_register(FAR struct net_driver_s *dev, enum net_lltype_e lltype)
       net_unlock(save);
 
 #ifdef CONFIG_NET_ETHERNET
-      nllinfo("Registered MAC: %02x:%02x:%02x:%02x:%02x:%02x as dev: %s\n",
-              dev->d_mac.ether_addr_octet[0], dev->d_mac.ether_addr_octet[1],
-              dev->d_mac.ether_addr_octet[2], dev->d_mac.ether_addr_octet[3],
-              dev->d_mac.ether_addr_octet[4], dev->d_mac.ether_addr_octet[5],
-              dev->d_ifname);
+      ninfo("Registered MAC: %02x:%02x:%02x:%02x:%02x:%02x as dev: %s\n",
+            dev->d_mac.ether_addr_octet[0], dev->d_mac.ether_addr_octet[1],
+            dev->d_mac.ether_addr_octet[2], dev->d_mac.ether_addr_octet[3],
+            dev->d_mac.ether_addr_octet[4], dev->d_mac.ether_addr_octet[5],
+            dev->d_ifname);
 #else
-      nllinfo("Registered dev: %s\n", dev->d_ifname);
+      ninfo("Registered dev: %s\n", dev->d_ifname);
 #endif
       return OK;
     }
diff --git a/net/netdev/netdev_unregister.c b/net/netdev/netdev_unregister.c
index 8509a5733c6..405118e308a 100644
--- a/net/netdev/netdev_unregister.c
+++ b/net/netdev/netdev_unregister.c
@@ -128,13 +128,13 @@ int netdev_unregister(FAR struct net_driver_s *dev)
       net_unlock(save);
 
 #ifdef CONFIG_NET_ETHERNET
-      nllinfo("Unregistered MAC: %02x:%02x:%02x:%02x:%02x:%02x as dev: %s\n",
-              dev->d_mac.ether_addr_octet[0], dev->d_mac.ether_addr_octet[1],
-              dev->d_mac.ether_addr_octet[2], dev->d_mac.ether_addr_octet[3],
-              dev->d_mac.ether_addr_octet[4], dev->d_mac.ether_addr_octet[5],
-              dev->d_ifname);
+      ninfo("Unregistered MAC: %02x:%02x:%02x:%02x:%02x:%02x as dev: %s\n",
+            dev->d_mac.ether_addr_octet[0], dev->d_mac.ether_addr_octet[1],
+            dev->d_mac.ether_addr_octet[2], dev->d_mac.ether_addr_octet[3],
+            dev->d_mac.ether_addr_octet[4], dev->d_mac.ether_addr_octet[5],
+            dev->d_ifname);
 #else
-      nllinfo("Registered dev: %s\n", dev->d_ifname);
+      ninfo("Registered dev: %s\n", dev->d_ifname);
 #endif
       return OK;
     }
diff --git a/net/pkt/pkt_callback.c b/net/pkt/pkt_callback.c
index e4c47834579..53df4c4afdf 100644
--- a/net/pkt/pkt_callback.c
+++ b/net/pkt/pkt_callback.c
@@ -70,7 +70,7 @@
 uint16_t pkt_callback(FAR struct net_driver_s *dev,
                       FAR struct pkt_conn_s *conn, uint16_t flags)
 {
-  nllinfo("flags: %04x\n", flags);
+  ninfo("flags: %04x\n", flags);
 
   /* Some sanity checking */
 
diff --git a/net/pkt/pkt_input.c b/net/pkt/pkt_input.c
index e7969cd8f00..b585dd5432f 100644
--- a/net/pkt/pkt_input.c
+++ b/net/pkt/pkt_input.c
@@ -118,7 +118,7 @@ int pkt_input(struct net_driver_s *dev)
     }
   else
     {
-      nllerr("ERROR: No listener\n");
+      nerr("ERROR: No listener\n");
     }
 
   return ret;
diff --git a/net/pkt/pkt_poll.c b/net/pkt/pkt_poll.c
index 0b1f12f8733..c289b146d83 100644
--- a/net/pkt/pkt_poll.c
+++ b/net/pkt/pkt_poll.c
@@ -78,7 +78,7 @@
 
 void pkt_poll(FAR struct net_driver_s *dev, FAR struct pkt_conn_s *conn)
 {
-  nllinfo("IN\n");
+  ninfo("IN\n");
 
   /* Verify that the packet connection is valid */
 
diff --git a/net/pkt/pkt_send.c b/net/pkt/pkt_send.c
index 164f187ebca..a419d69d8fb 100644
--- a/net/pkt/pkt_send.c
+++ b/net/pkt/pkt_send.c
@@ -93,7 +93,7 @@ static uint16_t psock_send_interrupt(FAR struct net_driver_s *dev,
 {
   FAR struct send_s *pstate = (FAR struct send_s *)pvpriv;
 
-  nllinfo("flags: %04x sent: %d\n", flags, pstate->snd_sent);
+  ninfo("flags: %04x sent: %d\n", flags, pstate->snd_sent);
 
   if (pstate)
     {
diff --git a/net/socket/connect.c b/net/socket/connect.c
index aa9903c4d7f..22c9cbbe318 100644
--- a/net/socket/connect.c
+++ b/net/socket/connect.c
@@ -185,7 +185,7 @@ static uint16_t psock_connect_interrupt(FAR struct net_driver_s *dev,
 {
   struct tcp_connect_s *pstate = (struct tcp_connect_s *)pvpriv;
 
-  nllinfo("flags: %04x\n", flags);
+  ninfo("flags: %04x\n", flags);
 
   /* 'priv' might be null in some race conditions (?) */
 
@@ -261,7 +261,7 @@ static uint16_t psock_connect_interrupt(FAR struct net_driver_s *dev,
           return flags & ~TCP_NEWDATA;
         }
 
-      nllinfo("Resuming: %d\n", pstate->tc_result);
+      ninfo("Resuming: %d\n", pstate->tc_result);
 
       /* Stop further callbacks */
 
diff --git a/net/socket/net_close.c b/net/socket/net_close.c
index c4f2e5ca3a8..261e1d4a883 100644
--- a/net/socket/net_close.c
+++ b/net/socket/net_close.c
@@ -161,7 +161,7 @@ static uint16_t netclose_interrupt(FAR struct net_driver_s *dev,
 
   DEBUGASSERT(conn != NULL);
 
-  nllinfo("conn: %p flags: %04x\n", conn, flags);
+  ninfo("conn: %p flags: %04x\n", conn, flags);
 
   /* TCP_DISCONN_EVENTS:
    *   TCP_CLOSE:    The remote host has closed the connection
@@ -209,7 +209,7 @@ static uint16_t netclose_interrupt(FAR struct net_driver_s *dev,
     {
       /* Yes.. Wake up the waiting thread and report the timeout */
 
-      nllerr("ERROR: CLOSE timeout\n");
+      nerr("ERROR: CLOSE timeout\n");
       pstate->cl_result = -ETIMEDOUT;
       goto end_wait;
     }
@@ -250,7 +250,7 @@ end_wait:
   pstate->cl_cb->event = NULL;
   sem_post(&pstate->cl_sem);
 
-  nllinfo("Resuming\n");
+  ninfo("Resuming\n");
   return 0;
 #endif
 }
diff --git a/net/socket/net_monitor.c b/net/socket/net_monitor.c
index 2c61a6a673e..d7d566725ba 100644
--- a/net/socket/net_monitor.c
+++ b/net/socket/net_monitor.c
@@ -145,7 +145,7 @@ static uint16_t connection_event(FAR struct net_driver_s *dev,
 
   if (psock)
     {
-      nllinfo("flags: %04x s_flags: %02x\n", flags, psock->s_flags);
+      ninfo("flags: %04x s_flags: %02x\n", flags, psock->s_flags);
 
       /* TCP_DISCONN_EVENTS: TCP_CLOSE, TCP_ABORT, TCP_TIMEDOUT, or
        * NETDEV_DOWN.  All loss-of-connection events.
diff --git a/net/socket/net_sendfile.c b/net/socket/net_sendfile.c
index c1c42b4b313..6c70cab18e6 100644
--- a/net/socket/net_sendfile.c
+++ b/net/socket/net_sendfile.c
@@ -156,7 +156,7 @@ static uint16_t ack_interrupt(FAR struct net_driver_s *dev, FAR void *pvconn,
 {
   FAR struct sendfile_s *pstate = (FAR struct sendfile_s *)pvpriv;
 
-  nllinfo("flags: %04x\n", flags);
+  ninfo("flags: %04x\n", flags);
 
   if ((flags & TCP_ACKDATA) != 0)
     {
@@ -197,8 +197,8 @@ static uint16_t ack_interrupt(FAR struct net_driver_s *dev, FAR void *pvconn,
        */
 
       pstate->snd_acked = tcp_getsequence(tcp->ackno) - pstate->snd_isn;
-      nllinfo("ACK: acked=%d sent=%d flen=%d\n",
-             pstate->snd_acked, pstate->snd_sent, pstate->snd_flen);
+      ninfo("ACK: acked=%d sent=%d flen=%d\n",
+            pstate->snd_acked, pstate->snd_sent, pstate->snd_flen);
 
       dev->d_sndlen = 0;
 
@@ -206,7 +206,7 @@ static uint16_t ack_interrupt(FAR struct net_driver_s *dev, FAR void *pvconn,
     }
   else if ((flags & TCP_REXMIT) != 0)
     {
-      nllwarn("WARNING: TCP_REXMIT\n");
+      nwarn("WARNING: TCP_REXMIT\n");
 
       /* Yes.. in this case, reset the number of bytes that have been sent
        * to the number of bytes that have been ACKed.
@@ -221,7 +221,7 @@ static uint16_t ack_interrupt(FAR struct net_driver_s *dev, FAR void *pvconn,
     {
       /* Report not connected */
 
-      nllwarn("WARNING: Lost connection\n");
+      nwarn("WARNING: Lost connection\n");
 
       net_lostconnection(pstate->snd_sock, flags);
       pstate->snd_sent = -ENOTCONN;
@@ -336,8 +336,8 @@ static uint16_t sendfile_interrupt(FAR struct net_driver_s *dev, FAR void *pvcon
     }
 #endif
 
-  nllinfo("flags: %04x acked: %d sent: %d\n",
-          flags, pstate->snd_acked, pstate->snd_sent);
+  ninfo("flags: %04x acked: %d sent: %d\n",
+        flags, pstate->snd_acked, pstate->snd_sent);
 
   /* Check for a loss of connection */
 
@@ -345,7 +345,7 @@ static uint16_t sendfile_interrupt(FAR struct net_driver_s *dev, FAR void *pvcon
     {
       /* Report not connected */
 
-      nllwarn("WARNING: Lost connection\n");
+      nwarn("WARNING: Lost connection\n");
 
       net_lostconnection(pstate->snd_sock, flags);
       pstate->snd_sent = -ENOTCONN;
@@ -386,7 +386,7 @@ static uint16_t sendfile_interrupt(FAR struct net_driver_s *dev, FAR void *pvcon
           if (ret < 0)
             {
               int errcode = get_errno();
-              nllerr("ERROR: Failed to lseek: %d\n", errcode);
+              nerr("ERROR: Failed to lseek: %d\n", errcode);
               pstate->snd_sent = -errcode;
               goto end_wait;
             }
@@ -395,7 +395,7 @@ static uint16_t sendfile_interrupt(FAR struct net_driver_s *dev, FAR void *pvcon
           if (ret < 0)
             {
               int errcode = get_errno();
-              nllerr("ERROR: Failed to read from input file: %d\n", errcode);
+              nerr("ERROR: Failed to read from input file: %d\n", errcode);
               pstate->snd_sent = -errcode;
               goto end_wait;
             }
@@ -410,7 +410,7 @@ static uint16_t sendfile_interrupt(FAR struct net_driver_s *dev, FAR void *pvcon
            */
 
           seqno = pstate->snd_sent + pstate->snd_isn;
-          nllinfo("SEND: sndseq %08x->%08x len: %d\n", conn->sndseq, seqno, ret);
+          ninfo("SEND: sndseq %08x->%08x len: %d\n", conn->sndseq, seqno, ret);
 
           tcp_setsequence(conn->sndseq, seqno);
 
@@ -424,13 +424,13 @@ static uint16_t sendfile_interrupt(FAR struct net_driver_s *dev, FAR void *pvcon
               /* Update the amount of data sent (but not necessarily ACKed) */
 
               pstate->snd_sent += sndlen;
-              nllinfo("pid: %d SEND: acked=%d sent=%d flen=%d\n", getpid(),
-                     pstate->snd_acked, pstate->snd_sent, pstate->snd_flen);
+              ninfo("pid: %d SEND: acked=%d sent=%d flen=%d\n", getpid(),
+                    pstate->snd_acked, pstate->snd_sent, pstate->snd_flen);
             }
         }
       else
         {
-          nllwarn("WARNING: Window full, wait for ack\n");
+          nwarn("WARNING: Window full, wait for ack\n");
           goto wait;
         }
     }
@@ -444,7 +444,7 @@ static uint16_t sendfile_interrupt(FAR struct net_driver_s *dev, FAR void *pvcon
     {
       /* Yes.. report the timeout */
 
-      nllwarn("WARNING: SEND timeout\n");
+      nwarn("WARNING: SEND timeout\n");
       pstate->snd_sent = -ETIMEDOUT;
       goto end_wait;
     }
@@ -687,7 +687,7 @@ ssize_t net_sendfile(int outfd, struct file *infile, off_t *offset,
 
   if (state.snd_datacb == NULL)
     {
-      nllerr("ERROR: Failed to allocate data callback\n");
+      nerr("ERROR: Failed to allocate data callback\n");
       errcode = ENOMEM;
       goto errout_locked;
     }
@@ -696,7 +696,7 @@ ssize_t net_sendfile(int outfd, struct file *infile, off_t *offset,
 
   if (state.snd_ackcb == NULL)
     {
-      nllerr("ERROR: Failed to allocate ack callback\n");
+      nerr("ERROR: Failed to allocate ack callback\n");
       errcode = ENOMEM;
       goto errout_datacb;
     }
diff --git a/net/socket/recvfrom.c b/net/socket/recvfrom.c
index 7ee8c8820f3..8b318bb6df8 100644
--- a/net/socket/recvfrom.c
+++ b/net/socket/recvfrom.c
@@ -181,7 +181,7 @@ static size_t recvfrom_newdata(FAR struct net_driver_s *dev,
   /* Copy the new appdata into the user buffer */
 
   memcpy(pstate->rf_buffer, dev->d_appdata, recvlen);
-  nllinfo("Received %d bytes (of %d)\n", (int)recvlen, (int)dev->d_len);
+  ninfo("Received %d bytes (of %d)\n", (int)recvlen, (int)dev->d_len);
 
   /* Update the accumulated size of the data read */
 
@@ -227,7 +227,7 @@ static void recvfrom_newpktdata(FAR struct net_driver_s *dev,
   /* Copy the new packet data into the user buffer */
 
   memcpy(pstate->rf_buffer, dev->d_buf, recvlen);
-  nllinfo("Received %d bytes (of %d)\n", (int)recvlen, (int)dev->d_len);
+  ninfo("Received %d bytes (of %d)\n", (int)recvlen, (int)dev->d_len);
 
   /* Update the accumulated size of the data read */
 
@@ -378,7 +378,7 @@ static inline void recvfrom_tcpreadahead(struct recvfrom_s *pstate)
        */
 
       recvlen = iob_copyout(pstate->rf_buffer, iob, pstate->rf_buflen, 0);
-      nllinfo("Received %d bytes (of %d)\n", recvlen, iob->io_pktlen);
+      ninfo("Received %d bytes (of %d)\n", recvlen, iob->io_pktlen);
 
       /* Update the accumulated size of the data read */
 
@@ -478,7 +478,7 @@ static inline void recvfrom_udpreadahead(struct recvfrom_s *pstate)
           recvlen = iob_copyout(pstate->rf_buffer, iob, pstate->rf_buflen,
                                 src_addr_size + sizeof(uint8_t));
 
-          nllinfo("Received %d bytes (of %d)\n", recvlen, iob->io_pktlen);
+          ninfo("Received %d bytes (of %d)\n", recvlen, iob->io_pktlen);
 
           /* Update the accumulated size of the data read */
 
@@ -621,7 +621,7 @@ static uint16_t recvfrom_pktinterrupt(FAR struct net_driver_s *dev,
 {
   struct recvfrom_s *pstate = (struct recvfrom_s *)pvpriv;
 
-  nllinfo("flags: %04x\n", flags);
+  ninfo("flags: %04x\n", flags);
 
   /* 'priv' might be null in some race conditions (?) */
 
@@ -636,7 +636,7 @@ static uint16_t recvfrom_pktinterrupt(FAR struct net_driver_s *dev,
 
           /* We are finished. */
 
-          nllinfo("PKT done\n");
+          ninfo("PKT done\n");
 
           /* Don't allow any further call backs. */
 
@@ -778,7 +778,7 @@ static uint16_t recvfrom_tcpinterrupt(FAR struct net_driver_s *dev,
 #endif
 #endif
 
-  nllinfo("flags: %04x\n", flags);
+  ninfo("flags: %04x\n", flags);
 
   /* 'priv' might be null in some race conditions (?) */
 
@@ -827,7 +827,7 @@ static uint16_t recvfrom_tcpinterrupt(FAR struct net_driver_s *dev,
           if (pstate->rf_recvlen > 0)
 #endif
             {
-              nllinfo("TCP resume\n");
+              ninfo("TCP resume\n");
 
               /* The TCP receive buffer is full.  Return now and don't allow
                * any further TCP call backs.
@@ -864,7 +864,7 @@ static uint16_t recvfrom_tcpinterrupt(FAR struct net_driver_s *dev,
 
       else if ((flags & TCP_DISCONN_EVENTS) != 0)
         {
-          nllinfo("Lost connection\n");
+          ninfo("Lost connection\n");
 
           /* Stop further callbacks */
 
@@ -924,7 +924,7 @@ static uint16_t recvfrom_tcpinterrupt(FAR struct net_driver_s *dev,
            * callbacks
            */
 
-          nllinfo("TCP timeout\n");
+          ninfo("TCP timeout\n");
 
           pstate->rf_cb->flags   = 0;
           pstate->rf_cb->priv    = NULL;
@@ -1122,7 +1122,7 @@ static uint16_t recvfrom_udp_interrupt(FAR struct net_driver_s *dev,
 {
   FAR struct recvfrom_s *pstate = (FAR struct recvfrom_s *)pvpriv;
 
-  nllinfo("flags: %04x\n", flags);
+  ninfo("flags: %04x\n", flags);
 
   /* 'priv' might be null in some race conditions (?) */
 
@@ -1136,7 +1136,7 @@ static uint16_t recvfrom_udp_interrupt(FAR struct net_driver_s *dev,
         {
           /* Terminate the transfer with an error. */
 
-          nllerr("ERROR: Network is down\n");
+          nerr("ERROR: Network is down\n");
           recvfrom_udp_terminate(pstate, -ENETUNREACH);
         }
 
@@ -1150,7 +1150,7 @@ static uint16_t recvfrom_udp_interrupt(FAR struct net_driver_s *dev,
 
           /* We are finished. */
 
-          nllinfo("UDP done\n");
+          ninfo("UDP done\n");
 
           /* Save the sender's address in the caller's 'from' location */
 
@@ -1176,7 +1176,7 @@ static uint16_t recvfrom_udp_interrupt(FAR struct net_driver_s *dev,
            * callbacks
            */
 
-          nllinfo("ERROR: UDP timeout\n");
+          nerr("ERROR: UDP timeout\n");
 
           /* Terminate the transfer with an -EAGAIN error */
 
diff --git a/net/tcp/tcp.h b/net/tcp/tcp.h
index e95d50cdf4b..c53475d75a4 100644
--- a/net/tcp/tcp.h
+++ b/net/tcp/tcp.h
@@ -206,6 +206,8 @@ struct tcp_conn_s
                            * it can only be updated at TCP_ESTABLISHED state */
   uint32_t   sent;        /* The number of bytes sent (ACKed and un-ACKed) */
   uint32_t   isn;         /* Initial sequence number */
+  uint32_t   sndseq_max;  /* The sequence number of next not-retransmitted
+                           * segment (next greater sndseq) */
 #endif
 
 #ifdef CONFIG_NET_TCPBACKLOG
@@ -665,7 +667,7 @@ void tcp_poll(FAR struct net_driver_s *dev, FAR struct tcp_conn_s *conn);
  * Parameters:
  *   dev  - The device driver structure to use in the send operation
  *   conn - The TCP "connection" to poll for TX data
- *   hsed - The polling interval in halves of a second
+ *   hsec - The polling interval in halves of a second
  *
  * Return:
  *   None
diff --git a/net/tcp/tcp_appsend.c b/net/tcp/tcp_appsend.c
index 924415378e2..e638bf18b76 100644
--- a/net/tcp/tcp_appsend.c
+++ b/net/tcp/tcp_appsend.c
@@ -87,8 +87,8 @@ void tcp_appsend(FAR struct net_driver_s *dev, FAR struct tcp_conn_s *conn,
 
   /* Handle the result based on the application response */
 
-  nllinfo("result: %04x d_sndlen: %d conn->unacked: %d\n",
-          result, dev->d_sndlen, conn->unacked);
+  ninfo("result: %04x d_sndlen: %d conn->unacked: %d\n",
+        result, dev->d_sndlen, conn->unacked);
 
   /* Get the IP header length associated with the IP domain configured for
    * this TCP connection.
@@ -124,7 +124,7 @@ void tcp_appsend(FAR struct net_driver_s *dev, FAR struct tcp_conn_s *conn,
 
       dev->d_sndlen = 0;
       conn->tcpstateflags = TCP_CLOSED;
-      nllinfo("TCP state: NETDEV_DOWN\n");
+      ninfo("TCP state: NETDEV_DOWN\n");
     }
 
   /* Check for connection aborted */
@@ -133,7 +133,7 @@ void tcp_appsend(FAR struct net_driver_s *dev, FAR struct tcp_conn_s *conn,
     {
       dev->d_sndlen = 0;
       conn->tcpstateflags = TCP_CLOSED;
-      nllinfo("TCP state: TCP_CLOSED\n");
+      ninfo("TCP state: TCP_CLOSED\n");
 
       tcp_send(dev, conn, TCP_RST | TCP_ACK, hdrlen);
     }
@@ -145,7 +145,7 @@ void tcp_appsend(FAR struct net_driver_s *dev, FAR struct tcp_conn_s *conn,
       conn->tcpstateflags = TCP_FIN_WAIT_1;
       conn->unacked  = 1;
       conn->nrtx     = 0;
-      nllinfo("TCP state: TCP_FIN_WAIT_1\n");
+      ninfo("TCP state: TCP_FIN_WAIT_1\n");
 
       dev->d_sndlen  = 0;
       tcp_send(dev, conn, TCP_FIN | TCP_ACK, hdrlen);
@@ -210,8 +210,8 @@ void tcp_rexmit(FAR struct net_driver_s *dev, FAR struct tcp_conn_s *conn,
 {
   uint8_t hdrlen;
 
-  nllinfo("result: %04x d_sndlen: %d conn->unacked: %d\n",
-          result, dev->d_sndlen, conn->unacked);
+  ninfo("result: %04x d_sndlen: %d conn->unacked: %d\n",
+        result, dev->d_sndlen, conn->unacked);
 
   /* Get the IP header length associated with the IP domain configured for
    * this TCP connection.
diff --git a/net/tcp/tcp_backlog.c b/net/tcp/tcp_backlog.c
index ad5e6893239..6d7122fd3d0 100644
--- a/net/tcp/tcp_backlog.c
+++ b/net/tcp/tcp_backlog.c
@@ -77,7 +77,7 @@ int tcp_backlogcreate(FAR struct tcp_conn_s *conn, int nblg)
   int offset;
   int i;
 
-  nllinfo("conn=%p nblg=%d\n", conn, nblg);
+  ninfo("conn=%p nblg=%d\n", conn, nblg);
 
 #ifdef CONFIG_DEBUG_FEATURES
   if (!conn)
@@ -109,7 +109,7 @@ int tcp_backlogcreate(FAR struct tcp_conn_s *conn, int nblg)
       bls = (FAR struct tcp_backlog_s *)kmm_zalloc(size);
       if (!bls)
         {
-          nllerr("ERROR: Failed to allocate backlog\n");
+          nerr("ERROR: Failed to allocate backlog\n");
           return -ENOMEM;
         }
 
@@ -161,7 +161,7 @@ int tcp_backlogdestroy(FAR struct tcp_conn_s *conn)
   FAR struct tcp_blcontainer_s *blc;
   FAR struct tcp_conn_s        *blconn;
 
-  nllinfo("conn=%p\n", conn);
+  ninfo("conn=%p\n", conn);
 
 #ifdef CONFIG_DEBUG_FEATURES
   if (!conn)
@@ -222,7 +222,7 @@ int tcp_backlogadd(FAR struct tcp_conn_s *conn, FAR struct tcp_conn_s *blconn)
   FAR struct tcp_blcontainer_s *blc;
   int ret = -EINVAL;
 
-  nllinfo("conn=%p blconn=%p\n", conn, blconn);
+  ninfo("conn=%p blconn=%p\n", conn, blconn);
 
 #ifdef CONFIG_DEBUG_FEATURES
   if (!conn)
@@ -239,7 +239,7 @@ int tcp_backlogadd(FAR struct tcp_conn_s *conn, FAR struct tcp_conn_s *blconn)
       blc = (FAR struct tcp_blcontainer_s *)sq_remfirst(&bls->bl_free);
       if (!blc)
         {
-          nllerr("ERROR: Failed to allocate container\n");
+          nerr("ERROR: Failed to allocate container\n");
           ret = -ENOMEM;
         }
       else
@@ -321,7 +321,7 @@ FAR struct tcp_conn_s *tcp_backlogremove(FAR struct tcp_conn_s *conn)
         }
     }
 
-  nllinfo("conn=%p, returning %p\n", conn, blconn);
+  ninfo("conn=%p, returning %p\n", conn, blconn);
   return blconn;
 }
 
@@ -345,7 +345,7 @@ int tcp_backlogdelete(FAR struct tcp_conn_s *conn,
   FAR struct tcp_blcontainer_s *blc;
   FAR struct tcp_blcontainer_s *prev;
 
-  nllinfo("conn=%p blconn=%p\n", conn, blconn);
+  ninfo("conn=%p blconn=%p\n", conn, blconn);
 
 #ifdef CONFIG_DEBUG_FEATURES
   if (!conn)
@@ -390,7 +390,7 @@ int tcp_backlogdelete(FAR struct tcp_conn_s *conn,
             }
         }
 
-      nllerr("ERROR: Failed to find pending connection\n");
+      nerr("ERROR: Failed to find pending connection\n");
       return -EINVAL;
     }
 
diff --git a/net/tcp/tcp_callback.c b/net/tcp/tcp_callback.c
index e5df8f1fe39..2ed5476d4f2 100644
--- a/net/tcp/tcp_callback.c
+++ b/net/tcp/tcp_callback.c
@@ -95,7 +95,7 @@ tcp_data_event(FAR struct net_driver_s *dev, FAR struct tcp_conn_s *conn,
       uint16_t recvlen;
 #endif
 
-      nllinfo("No listener on connection\n");
+      ninfo("No listener on connection\n");
 
 #ifdef CONFIG_NET_TCP_READAHEAD
       /* Save as the packet data as in the read-ahead buffer.  NOTE that
@@ -110,7 +110,7 @@ tcp_data_event(FAR struct net_driver_s *dev, FAR struct tcp_conn_s *conn,
            * read-ahead buffers to retain the data -- drop the packet.
            */
 
-         nllinfo("Dropped %d bytes\n", dev->d_len);
+         ninfo("Dropped %d bytes\n", dev->d_len);
 
 #ifdef CONFIG_NET_STATISTICS
           g_netstats.tcp.syndrop++;
@@ -152,7 +152,7 @@ uint16_t tcp_callback(FAR struct net_driver_s *dev,
    * explicitly set in the callback.
    */
 
-  nllinfo("flags: %04x\n", flags);
+  ninfo("flags: %04x\n", flags);
 
   /* Perform the data callback.  When a data callback is executed from 'list',
    * the input flags are normally returned, however, the implementation
@@ -245,7 +245,7 @@ uint16_t tcp_datahandler(FAR struct tcp_conn_s *conn, FAR uint8_t *buffer,
   iob = iob_tryalloc(true);
   if (iob == NULL)
     {
-      nllerr("ERROR: Failed to create new I/O buffer chain\n");
+      nerr("ERROR: Failed to create new I/O buffer chain\n");
       return 0;
     }
 
@@ -258,7 +258,7 @@ uint16_t tcp_datahandler(FAR struct tcp_conn_s *conn, FAR uint8_t *buffer,
        * not free any I/O buffers.
        */
 
-      nllerr("ERROR: Failed to add data to the I/O buffer chain: %d\n", ret);
+      nerr("ERROR: Failed to add data to the I/O buffer chain: %d\n", ret);
       (void)iob_free_chain(iob);
       return 0;
     }
@@ -270,12 +270,12 @@ uint16_t tcp_datahandler(FAR struct tcp_conn_s *conn, FAR uint8_t *buffer,
   ret = iob_tryadd_queue(iob, &conn->readahead);
   if (ret < 0)
     {
-      nllerr("ERROR: Failed to queue the I/O buffer chain: %d\n", ret);
+      nerr("ERROR: Failed to queue the I/O buffer chain: %d\n", ret);
       (void)iob_free_chain(iob);
       return 0;
     }
 
-  nllinfo("Buffered %d bytes\n", buflen);
+  ninfo("Buffered %d bytes\n", buflen);
   return buflen;
 }
 #endif /* CONFIG_NET_TCP_READAHEAD */
diff --git a/net/tcp/tcp_conn.c b/net/tcp/tcp_conn.c
index fa11c42c4a1..ac861c24d4e 100644
--- a/net/tcp/tcp_conn.c
+++ b/net/tcp/tcp_conn.c
@@ -727,7 +727,7 @@ FAR struct tcp_conn_s *tcp_alloc(uint8_t domain)
 
       while (tmp)
         {
-          nllinfo("conn: %p state: %02x\n", tmp, tmp->tcpstateflags);
+          ninfo("conn: %p state: %02x\n", tmp, tmp->tcpstateflags);
 
           /* Is this connection in a state we can sacrifice. */
 
@@ -760,7 +760,7 @@ FAR struct tcp_conn_s *tcp_alloc(uint8_t domain)
 
       if (conn != NULL)
         {
-          nllwarn("WARNING: Closing unestablished connection: %p\n", conn);
+          nwarn("WARNING: Closing unestablished connection: %p\n", conn);
 
           /* Yes... free it.  This will remove the connection from the list
            * of active connections and release all resources held by the
@@ -1083,11 +1083,12 @@ FAR struct tcp_conn_s *tcp_alloc_accept(FAR struct net_driver_s *dev,
       conn->tcpstateflags = TCP_SYN_RCVD;
 
       tcp_initsequence(conn->sndseq);
-      conn->unacked = 1;
+      conn->unacked       = 1;
 #ifdef CONFIG_NET_TCP_WRITE_BUFFERS
-      conn->expired = 0;
-      conn->isn     = 0;
-      conn->sent    = 0;
+      conn->expired       = 0;
+      conn->isn           = 0;
+      conn->sent          = 0;
+      conn->sndseq_max    = 0;
 #endif
 
       /* rcvseq should be the seqno from the incoming packet + 1. */
@@ -1344,6 +1345,7 @@ int tcp_connect(FAR struct tcp_conn_s *conn, FAR const struct sockaddr *addr)
   conn->expired    = 0;
   conn->isn        = 0;
   conn->sent       = 0;
+  conn->sndseq_max = 0;
 #endif
 
 #ifdef CONFIG_NET_TCP_READAHEAD
diff --git a/net/tcp/tcp_input.c b/net/tcp/tcp_input.c
index 277db67412e..184dfebb01c 100644
--- a/net/tcp/tcp_input.c
+++ b/net/tcp/tcp_input.c
@@ -126,7 +126,7 @@ static void tcp_input(FAR struct net_driver_s *dev, unsigned int iplen)
       g_netstats.tcp.drop++;
       g_netstats.tcp.chkerr++;
 #endif
-      nllwarn("WARNING: Bad TCP checksum\n");
+      nwarn("WARNING: Bad TCP checksum\n");
       goto drop;
     }
 
@@ -206,7 +206,7 @@ static void tcp_input(FAR struct net_driver_s *dev, unsigned int iplen)
 #ifdef CONFIG_NET_STATISTICS
               g_netstats.tcp.syndrop++;
 #endif
-              nllerr("ERROR: No free TCP connections\n");
+              nerr("ERROR: No free TCP connections\n");
               goto drop;
             }
 
@@ -308,7 +308,7 @@ found:
   if ((tcp->flags & TCP_RST) != 0)
     {
       conn->tcpstateflags = TCP_CLOSED;
-      nllwarn("WARNING: RESET - TCP state: TCP_CLOSED\n");
+      nwarn("WARNING: RESET - TCP state: TCP_CLOSED\n");
 
       (void)tcp_callback(dev, conn, TCP_ABORT);
       goto drop;
@@ -364,7 +364,7 @@ found:
        */
 
 #ifdef CONFIG_NET_TCP_WRITE_BUFFERS
-      unackseq = conn->isn + conn->sent;
+      unackseq = conn->sndseq_max;
 #else
       unackseq = tcp_addsequence(conn->sndseq, conn->unacked);
 #endif
@@ -398,8 +398,8 @@ found:
 
           if ((conn->tcpstateflags & TCP_STATE_MASK) == TCP_ESTABLISHED)
             {
-              nllwarn("WARNING: conn->sndseq %d, conn->unacked %d\n",
-                     tcp_getsequence(conn->sndseq), conn->unacked);
+              nwarn("WARNING: conn->sndseq %d, conn->unacked %d\n",
+                    tcp_getsequence(conn->sndseq), conn->unacked);
               goto reset;
             }
         }
@@ -409,8 +409,8 @@ found:
        * be beyond ackseq.
        */
 
-      nllinfo("sndseq: %08x->%08x unackseq: %08x new unacked: %d\n",
-              conn->sndseq, ackseq, unackseq, conn->unacked);
+      ninfo("sndseq: %08x->%08x unackseq: %08x new unacked: %d\n",
+            conn->sndseq, ackseq, unackseq, conn->unacked);
       tcp_setsequence(conn->sndseq, ackseq);
 
       /* Do RTT estimation, unless we have done retransmissions. */
@@ -468,10 +468,11 @@ found:
             conn->isn           = tcp_getsequence(tcp->ackno);
             tcp_setsequence(conn->sndseq, conn->isn);
             conn->sent          = 0;
+            conn->sndseq_max    = 0;
 #endif
             conn->unacked       = 0;
             flags               = TCP_CONNECTED;
-            nllinfo("TCP state: TCP_ESTABLISHED\n");
+            ninfo("TCP state: TCP_ESTABLISHED\n");
 
             if (dev->d_len > 0)
               {
@@ -571,7 +572,7 @@ found:
             dev->d_len          = 0;
             dev->d_sndlen       = 0;
 
-            nllinfo("TCP state: TCP_ESTABLISHED\n");
+            ninfo("TCP state: TCP_ESTABLISHED\n");
             result = tcp_callback(dev, conn, TCP_CONNECTED | TCP_NEWDATA);
             tcp_appsend(dev, conn, result);
             return;
@@ -584,7 +585,7 @@ found:
         /* The connection is closed after we send the RST */
 
         conn->tcpstateflags = TCP_CLOSED;
-        nllinfo("Connection failed - TCP state: TCP_CLOSED\n");
+        ninfo("Connection failed - TCP state: TCP_CLOSED\n");
 
         /* We do not send resets in response to resets. */
 
@@ -640,7 +641,7 @@ found:
             conn->tcpstateflags = TCP_LAST_ACK;
             conn->unacked       = 1;
             conn->nrtx          = 0;
-            nllinfo("TCP state: TCP_LAST_ACK\n");
+            ninfo("TCP state: TCP_LAST_ACK\n");
 
             tcp_send(dev, conn, TCP_FIN | TCP_ACK, tcpiplen);
             return;
@@ -748,7 +749,7 @@ found:
         if ((flags & TCP_ACKDATA) != 0)
           {
             conn->tcpstateflags = TCP_CLOSED;
-            nllinfo("TCP_LAST_ACK TCP state: TCP_CLOSED\n");
+            ninfo("TCP_LAST_ACK TCP state: TCP_CLOSED\n");
 
             (void)tcp_callback(dev, conn, TCP_CLOSE);
           }
@@ -772,12 +773,12 @@ found:
                 conn->tcpstateflags = TCP_TIME_WAIT;
                 conn->timer         = 0;
                 conn->unacked       = 0;
-                nllinfo("TCP state: TCP_TIME_WAIT\n");
+                ninfo("TCP state: TCP_TIME_WAIT\n");
               }
             else
               {
                 conn->tcpstateflags = TCP_CLOSING;
-                nllinfo("TCP state: TCP_CLOSING\n");
+                ninfo("TCP state: TCP_CLOSING\n");
               }
 
             net_incr32(conn->rcvseq, 1);
@@ -789,7 +790,7 @@ found:
           {
             conn->tcpstateflags = TCP_FIN_WAIT_2;
             conn->unacked = 0;
-            nllinfo("TCP state: TCP_FIN_WAIT_2\n");
+            ninfo("TCP state: TCP_FIN_WAIT_2\n");
             goto drop;
           }
 
@@ -811,7 +812,7 @@ found:
           {
             conn->tcpstateflags = TCP_TIME_WAIT;
             conn->timer         = 0;
-            nllinfo("TCP state: TCP_TIME_WAIT\n");
+            ninfo("TCP state: TCP_TIME_WAIT\n");
 
             net_incr32(conn->rcvseq, 1);
             (void)tcp_callback(dev, conn, TCP_CLOSE);
@@ -836,7 +837,7 @@ found:
           {
             conn->tcpstateflags = TCP_TIME_WAIT;
             conn->timer        = 0;
-            nllinfo("TCP state: TCP_TIME_WAIT\n");
+            ninfo("TCP state: TCP_TIME_WAIT\n");
           }
 
       default:
diff --git a/net/tcp/tcp_netpoll.c b/net/tcp/tcp_netpoll.c
index 5344eb43039..41382144c2f 100644
--- a/net/tcp/tcp_netpoll.c
+++ b/net/tcp/tcp_netpoll.c
@@ -93,7 +93,7 @@ static uint16_t tcp_poll_interrupt(FAR struct net_driver_s *dev, FAR void *conn,
 {
   FAR struct tcp_poll_s *info = (FAR struct tcp_poll_s *)pvpriv;
 
-  nllinfo("flags: %04x\n", flags);
+  ninfo("flags: %04x\n", flags);
 
   DEBUGASSERT(!info || (info->psock && info->fds));
 
diff --git a/net/tcp/tcp_send.c b/net/tcp/tcp_send.c
index 12881bcd3ad..edce06a196f 100644
--- a/net/tcp/tcp_send.c
+++ b/net/tcp/tcp_send.c
@@ -167,7 +167,7 @@ static inline void tcp_ipv4_sendcomplete(FAR struct net_driver_s *dev,
   ipv4->ipchksum    = 0;
   ipv4->ipchksum    = ~ipv4_chksum(dev);
 
-  nllinfo("IPv4 length: %d\n", ((int)ipv4->len[0] << 8) + ipv4->len[1]);
+  ninfo("IPv4 length: %d\n", ((int)ipv4->len[0] << 8) + ipv4->len[1]);
 
 #ifdef CONFIG_NET_STATISTICS
   g_netstats.ipv4.sent++;
@@ -230,7 +230,7 @@ static inline void tcp_ipv6_sendcomplete(FAR struct net_driver_s *dev,
   ipv6->tcf    = 0x00;
   ipv6->flow   = 0x00;
 
-  nllinfo("IPv6 length: %d\n", ((int)ipv6->len[0] << 8) + ipv6->len[1]);
+  ninfo("IPv6 length: %d\n", ((int)ipv6->len[0] << 8) + ipv6->len[1]);
 
 #ifdef CONFIG_NET_STATISTICS
   g_netstats.ipv6.sent++;
@@ -277,7 +277,7 @@ static void tcp_sendcomplete(FAR struct net_driver_s *dev,
     }
 #endif /* CONFIG_NET_IPv4 */
 
-  nllinfo("Outgoing TCP packet length: %d bytes\n", dev->d_len);
+  ninfo("Outgoing TCP packet length: %d bytes\n", dev->d_len);
 
 #ifdef CONFIG_NET_STATISTICS
   g_netstats.tcp.sent++;
diff --git a/net/tcp/tcp_send_buffered.c b/net/tcp/tcp_send_buffered.c
index a343d0d046c..468f90b9dac 100644
--- a/net/tcp/tcp_send_buffered.c
+++ b/net/tcp/tcp_send_buffered.c
@@ -201,7 +201,8 @@ static inline void psock_lost_connection(FAR struct socket *psock,
 
   sq_init(&conn->unacked_q);
   sq_init(&conn->write_q);
-  conn->sent = 0;
+  conn->sent       = 0;
+  conn->sndseq_max = 0;
 }
 
 /****************************************************************************
@@ -349,7 +350,7 @@ static uint16_t psock_send_interrupt(FAR struct net_driver_s *dev,
     }
 #endif
 
-  nllinfo("flags: %04x\n", flags);
+  ninfo("flags: %04x\n", flags);
 
   /* If this packet contains an acknowledgement, then update the count of
    * acknowledged bytes.
@@ -388,7 +389,7 @@ static uint16_t psock_send_interrupt(FAR struct net_driver_s *dev,
       /* Get the ACK number from the TCP header */
 
       ackno = tcp_getsequence(tcp->ackno);
-      nllinfo("ACK: ackno=%u flags=%04x\n", ackno, flags);
+      ninfo("ACK: ackno=%u flags=%04x\n", ackno, flags);
 
       /* Look at every write buffer in the unacked_q.  The unacked_q
        * holds write buffers that have been entirely sent, but which
@@ -414,14 +415,14 @@ static uint16_t psock_send_interrupt(FAR struct net_driver_s *dev,
               /* Get the sequence number at the end of the data */
 
               lastseq = WRB_SEQNO(wrb) + WRB_PKTLEN(wrb);
-              nllinfo("ACK: wrb=%p seqno=%u lastseq=%u pktlen=%u ackno=%u\n",
-                      wrb, WRB_SEQNO(wrb), lastseq, WRB_PKTLEN(wrb), ackno);
+              ninfo("ACK: wrb=%p seqno=%u lastseq=%u pktlen=%u ackno=%u\n",
+                    wrb, WRB_SEQNO(wrb), lastseq, WRB_PKTLEN(wrb), ackno);
 
               /* Has the entire buffer been ACKed? */
 
               if (ackno >= lastseq)
                 {
-                  nllinfo("ACK: wrb=%p Freeing write buffer\n", wrb);
+                  ninfo("ACK: wrb=%p Freeing write buffer\n", wrb);
 
                   /* Yes... Remove the write buffer from ACK waiting queue */
 
@@ -449,7 +450,7 @@ static uint16_t psock_send_interrupt(FAR struct net_driver_s *dev,
                       trimlen = WRB_SENT(wrb);
                     }
 
-                  nllinfo("ACK: wrb=%p trim %u bytes\n", wrb, trimlen);
+                  ninfo("ACK: wrb=%p trim %u bytes\n", wrb, trimlen);
 
                   WRB_TRIM(wrb, trimlen);
                   WRB_SEQNO(wrb) = ackno;
@@ -457,7 +458,7 @@ static uint16_t psock_send_interrupt(FAR struct net_driver_s *dev,
 
                   /* Set the new sequence number for what remains */
 
-                  nllinfo("ACK: wrb=%p seqno=%u pktlen=%u\n",
+                  ninfo("ACK: wrb=%p seqno=%u pktlen=%u\n",
                           wrb, WRB_SEQNO(wrb), WRB_PKTLEN(wrb));
                 }
             }
@@ -483,8 +484,8 @@ static uint16_t psock_send_interrupt(FAR struct net_driver_s *dev,
               nacked = WRB_SENT(wrb);
             }
 
-          nllinfo("ACK: wrb=%p seqno=%u nacked=%u sent=%u ackno=%u\n",
-                  wrb, WRB_SEQNO(wrb), nacked, WRB_SENT(wrb), ackno);
+          ninfo("ACK: wrb=%p seqno=%u nacked=%u sent=%u ackno=%u\n",
+                wrb, WRB_SEQNO(wrb), nacked, WRB_SENT(wrb), ackno);
 
           /* Trim the ACKed bytes from the beginning of the write buffer. */
 
@@ -492,8 +493,8 @@ static uint16_t psock_send_interrupt(FAR struct net_driver_s *dev,
           WRB_SEQNO(wrb) = ackno;
           WRB_SENT(wrb) -= nacked;
 
-          nllinfo("ACK: wrb=%p seqno=%u pktlen=%u sent=%u\n",
-                  wrb, WRB_SEQNO(wrb), WRB_PKTLEN(wrb), WRB_SENT(wrb));
+          ninfo("ACK: wrb=%p seqno=%u pktlen=%u sent=%u\n",
+                wrb, WRB_SEQNO(wrb), WRB_PKTLEN(wrb), WRB_SENT(wrb));
         }
     }
 
@@ -501,7 +502,7 @@ static uint16_t psock_send_interrupt(FAR struct net_driver_s *dev,
 
   else if ((flags & TCP_DISCONN_EVENTS) != 0)
     {
-      nllinfo("Lost connection: %04x\n", flags);
+      ninfo("Lost connection: %04x\n", flags);
 
       if (psock->s_conn != NULL)
         {
@@ -523,14 +524,14 @@ static uint16_t psock_send_interrupt(FAR struct net_driver_s *dev,
       FAR struct tcp_wrbuffer_s *wrb;
       FAR sq_entry_t *entry;
 
-      nllinfo("REXMIT: %04x\n", flags);
+      ninfo("REXMIT: %04x\n", flags);
 
       /* If there is a partially sent write buffer at the head of the
        * write_q?  Has anything been sent from that write buffer?
        */
 
       wrb = (FAR struct tcp_wrbuffer_s *)sq_peek(&conn->write_q);
-      nllinfo("REXMIT: wrb=%p sent=%u\n", wrb, wrb ? WRB_SENT(wrb) : 0);
+      ninfo("REXMIT: wrb=%p sent=%u\n", wrb, wrb ? WRB_SENT(wrb) : 0);
 
       if (wrb != NULL && WRB_SENT(wrb) > 0)
         {
@@ -559,15 +560,15 @@ static uint16_t psock_send_interrupt(FAR struct net_driver_s *dev,
             }
 
           WRB_SENT(wrb) = 0;
-          nllinfo("REXMIT: wrb=%p sent=%u, conn unacked=%d sent=%d\n",
-                  wrb, WRB_SENT(wrb), conn->unacked, conn->sent);
+          ninfo("REXMIT: wrb=%p sent=%u, conn unacked=%d sent=%d\n",
+                wrb, WRB_SENT(wrb), conn->unacked, conn->sent);
 
           /* Increment the retransmit count on this write buffer. */
 
           if (++WRB_NRTX(wrb) >= TCP_MAXRTX)
             {
-              nllwarn("WARNING: Expiring wrb=%p nrtx=%u\n",
-                     wrb, WRB_NRTX(wrb));
+              nwarn("WARNING: Expiring wrb=%p nrtx=%u\n",
+                    wrb, WRB_NRTX(wrb));
 
               /* The maximum retry count as been exhausted. Remove the write
                * buffer at the head of the queue.
@@ -625,15 +626,15 @@ static uint16_t psock_send_interrupt(FAR struct net_driver_s *dev,
             }
 
           WRB_SENT(wrb) = 0;
-          nllinfo("REXMIT: wrb=%p sent=%u, conn unacked=%d sent=%d\n",
-                  wrb, WRB_SENT(wrb), conn->unacked, conn->sent);
+          ninfo("REXMIT: wrb=%p sent=%u, conn unacked=%d sent=%d\n",
+                wrb, WRB_SENT(wrb), conn->unacked, conn->sent);
 
           /* Free any write buffers that have exceed the retry count */
 
           if (++WRB_NRTX(wrb) >= TCP_MAXRTX)
             {
-              nllwarn("WARNING: Expiring wrb=%p nrtx=%u\n",
-                     wrb, WRB_NRTX(wrb));
+              nwarn("WARNING: Expiring wrb=%p nrtx=%u\n",
+                    wrb, WRB_NRTX(wrb));
 
               /* Return the write buffer to the free list */
 
@@ -654,11 +655,11 @@ static uint16_t psock_send_interrupt(FAR struct net_driver_s *dev,
             {
               /* Insert the write buffer into the write_q (in sequence
                * number order).  The retransmission will occur below
-               * when the write buffer with the lowest sequenc number
+               * when the write buffer with the lowest sequence number
                * is pulled from the write_q again.
                */
 
-              nllinfo("REXMIT: Moving wrb=%p nrtx=%u\n", wrb, WRB_NRTX(wrb));
+              ninfo("REXMIT: Moving wrb=%p nrtx=%u\n", wrb, WRB_NRTX(wrb));
 
               psock_insert_segment(wrb, &conn->write_q);
             }
@@ -696,6 +697,7 @@ static uint16_t psock_send_interrupt(FAR struct net_driver_s *dev,
       if (psock_send_addrchck(conn))
         {
           FAR struct tcp_wrbuffer_s *wrb;
+          uint32_t predicted_seqno;
           size_t sndlen;
 
           /* Peek at the head of the write queue (but don't remove anything
@@ -723,8 +725,8 @@ static uint16_t psock_send_interrupt(FAR struct net_driver_s *dev,
               sndlen = conn->winsize;
             }
 
-          nllinfo("SEND: wrb=%p pktlen=%u sent=%u sndlen=%u\n",
-                  wrb, WRB_PKTLEN(wrb), WRB_SENT(wrb), sndlen);
+          ninfo("SEND: wrb=%p pktlen=%u sent=%u sndlen=%u\n",
+                wrb, WRB_PKTLEN(wrb), WRB_SENT(wrb), sndlen);
 
           /* Set the sequence number for this segment.  If we are
            * retransmitting, then the sequence number will already
@@ -770,15 +772,25 @@ static uint16_t psock_send_interrupt(FAR struct net_driver_s *dev,
           conn->unacked += sndlen;
           conn->sent    += sndlen;
 
-          nllinfo("SEND: wrb=%p nrtx=%u unacked=%u sent=%u\n",
-                  wrb, WRB_NRTX(wrb), conn->unacked, conn->sent);
+          /* Below prediction will become true, unless retransmission occurrence */
+
+          predicted_seqno = tcp_getsequence(conn->sndseq) + sndlen;
+
+          if ((predicted_seqno > conn->sndseq_max) ||
+              (tcp_getsequence(conn->sndseq) > predicted_seqno)) /* overflow */
+            {
+               conn->sndseq_max = predicted_seqno;
+            }
+
+          ninfo("SEND: wrb=%p nrtx=%u unacked=%u sent=%u\n",
+                wrb, WRB_NRTX(wrb), conn->unacked, conn->sent);
 
           /* Increment the count of bytes sent from this write buffer */
 
           WRB_SENT(wrb) += sndlen;
 
-          nllinfo("SEND: wrb=%p sent=%u pktlen=%u\n",
-                  wrb, WRB_SENT(wrb), WRB_PKTLEN(wrb));
+          ninfo("SEND: wrb=%p sent=%u pktlen=%u\n",
+                wrb, WRB_SENT(wrb), WRB_PKTLEN(wrb));
 
           /* Remove the write buffer from the write queue if the
            * last of the data has been sent from the buffer.
@@ -789,7 +801,7 @@ static uint16_t psock_send_interrupt(FAR struct net_driver_s *dev,
             {
               FAR struct tcp_wrbuffer_s *tmp;
 
-              nllinfo("SEND: wrb=%p Move to unacked_q\n", wrb);
+              ninfo("SEND: wrb=%p Move to unacked_q\n", wrb);
 
               tmp = (FAR struct tcp_wrbuffer_s *)sq_remfirst(&conn->write_q);
               DEBUGASSERT(tmp == wrb);
@@ -1058,9 +1070,9 @@ ssize_t psock_tcp_send(FAR struct socket *psock, FAR const void *buf,
        */
 
       sq_addlast(&wrb->wb_node, &conn->write_q);
-      nllinfo("Queued WRB=%p pktlen=%u write_q(%p,%p)\n",
-              wrb, WRB_PKTLEN(wrb),
-              conn->write_q.head, conn->write_q.tail);
+      ninfo("Queued WRB=%p pktlen=%u write_q(%p,%p)\n",
+            wrb, WRB_PKTLEN(wrb),
+            conn->write_q.head, conn->write_q.tail);
 
       /* Notify the device driver of the availability of TX data */
 
diff --git a/net/tcp/tcp_send_unbuffered.c b/net/tcp/tcp_send_unbuffered.c
index 0e7e9fe7c4b..f0f7c601217 100644
--- a/net/tcp/tcp_send_unbuffered.c
+++ b/net/tcp/tcp_send_unbuffered.c
@@ -302,8 +302,8 @@ static uint16_t tcpsend_interrupt(FAR struct net_driver_s *dev,
     }
 #endif
 
-  nllinfo("flags: %04x acked: %d sent: %d\n",
-          flags, pstate->snd_acked, pstate->snd_sent);
+  ninfo("flags: %04x acked: %d sent: %d\n",
+        flags, pstate->snd_acked, pstate->snd_sent);
 
   /* If this packet contains an acknowledgement, then update the count of
    * acknowledged bytes.
@@ -348,8 +348,8 @@ static uint16_t tcpsend_interrupt(FAR struct net_driver_s *dev,
        */
 
       pstate->snd_acked = tcp_getsequence(tcp->ackno) - pstate->snd_isn;
-      nllinfo("ACK: acked=%d sent=%d buflen=%d\n",
-              pstate->snd_acked, pstate->snd_sent, pstate->snd_buflen);
+      ninfo("ACK: acked=%d sent=%d buflen=%d\n",
+            pstate->snd_acked, pstate->snd_sent, pstate->snd_buflen);
 
       /* Have all of the bytes in the buffer been sent and acknowledged? */
 
@@ -392,7 +392,7 @@ static uint16_t tcpsend_interrupt(FAR struct net_driver_s *dev,
     {
       /* Report not connected */
 
-      nllinfo("Lost connection\n");
+      ninfo("Lost connection\n");
 
       net_lostconnection(pstate->snd_sock, flags);
       pstate->snd_sent = -ENOTCONN;
@@ -526,7 +526,7 @@ static uint16_t tcpsend_interrupt(FAR struct net_driver_s *dev,
            */
 
           seqno = pstate->snd_sent + pstate->snd_isn;
-          nllinfo("SEND: sndseq %08x->%08x\n", conn->sndseq, seqno);
+          ninfo("SEND: sndseq %08x->%08x\n", conn->sndseq, seqno);
           tcp_setsequence(conn->sndseq, seqno);
 
 #ifdef NEED_IPDOMAIN_SUPPORT
@@ -554,8 +554,8 @@ static uint16_t tcpsend_interrupt(FAR struct net_driver_s *dev,
               /* Update the amount of data sent (but not necessarily ACKed) */
 
               pstate->snd_sent += sndlen;
-              nllinfo("SEND: acked=%d sent=%d buflen=%d\n",
-                      pstate->snd_acked, pstate->snd_sent, pstate->snd_buflen);
+              ninfo("SEND: acked=%d sent=%d buflen=%d\n",
+                    pstate->snd_acked, pstate->snd_sent, pstate->snd_buflen);
 
             }
         }
@@ -570,7 +570,7 @@ static uint16_t tcpsend_interrupt(FAR struct net_driver_s *dev,
     {
       /* Yes.. report the timeout */
 
-      nllwarn("WARNING: SEND timeout\n");
+      nwarn("WARNING: SEND timeout\n");
       pstate->snd_sent = -ETIMEDOUT;
       goto end_wait;
     }
diff --git a/net/tcp/tcp_timer.c b/net/tcp/tcp_timer.c
index 4d8871e1af3..eeabb0910c4 100644
--- a/net/tcp/tcp_timer.c
+++ b/net/tcp/tcp_timer.c
@@ -157,7 +157,7 @@ void tcp_timer(FAR struct net_driver_s *dev, FAR struct tcp_conn_s *conn,
           DEBUGASSERT(conn->dev != NULL);
           if (dev != conn->dev)
             {
-              nllinfo("TCP: TCP_CLOSED pending\n");
+              ninfo("TCP: TCP_CLOSED pending\n");
             }
           else
 #endif
@@ -168,7 +168,7 @@ void tcp_timer(FAR struct net_driver_s *dev, FAR struct tcp_conn_s *conn,
 
               result = tcp_callback(dev, conn, TCP_TIMEDOUT);
 
-              nllinfo("TCP state: TCP_CLOSED\n");
+              ninfo("TCP state: TCP_CLOSED\n");
             }
         }
       else
@@ -213,7 +213,7 @@ void tcp_timer(FAR struct net_driver_s *dev, FAR struct tcp_conn_s *conn,
               DEBUGASSERT(conn->dev != NULL);
               if (dev != conn->dev)
                 {
-                  nllinfo("TCP: TCP_CLOSED pending\n");
+                  ninfo("TCP: TCP_CLOSED pending\n");
                   goto done;
                 }
 #endif
@@ -231,7 +231,7 @@ void tcp_timer(FAR struct net_driver_s *dev, FAR struct tcp_conn_s *conn,
                  )
                 {
                   conn->tcpstateflags = TCP_CLOSED;
-                  nllinfo("TCP state: TCP_CLOSED\n");
+                  ninfo("TCP state: TCP_CLOSED\n");
 
                   /* We call tcp_callback() with TCP_TIMEDOUT to
                    * inform the application that the connection has
diff --git a/net/tcp/tcp_wrbuffer_dump.c b/net/tcp/tcp_wrbuffer_dump.c
index 2155a3b4751..6d1fbf85f6b 100644
--- a/net/tcp/tcp_wrbuffer_dump.c
+++ b/net/tcp/tcp_wrbuffer_dump.c
@@ -63,8 +63,8 @@
 void tcp_wrbuffer_dump(FAR const char *msg, FAR struct tcp_wrbuffer_s *wrb,
                        unsigned int len, unsigned int offset)
 {
-  lowsyslog(LOG_DEBUG, "%s: wrb=%p segno=%d sent=%d nrtx=%d\n",
-            msg, wrb, WRB_SEQNO(wrb), WRB_SENT(wrb), WRB_NRTX(wrb));
+  syslog(LOG_DEBUG, "%s: wrb=%p segno=%d sent=%d nrtx=%d\n",
+         msg, wrb, WRB_SEQNO(wrb), WRB_SENT(wrb), WRB_NRTX(wrb));
   iob_dump("I/O Buffer Chain", WRB_IOB(wrb), len, offset);
 }
 
diff --git a/net/udp/udp_callback.c b/net/udp/udp_callback.c
index be6f59d5cbb..74c0527fae8 100644
--- a/net/udp/udp_callback.c
+++ b/net/udp/udp_callback.c
@@ -98,7 +98,7 @@ static uint16_t udp_datahandler(FAR struct net_driver_s *dev, FAR struct udp_con
   iob = iob_tryalloc(true);
   if (iob == NULL)
     {
-      nllerr("ERROR: Failed to create new I/O buffer chain\n");
+      nerr("ERROR: Failed to create new I/O buffer chain\n");
       return 0;
     }
 
@@ -178,7 +178,7 @@ static uint16_t udp_datahandler(FAR struct net_driver_s *dev, FAR struct udp_con
        * not free any I/O buffers.
        */
 
-      nllerr("ERROR: Failed to add data to the I/O buffer chain: %d\n", ret);
+      nerr("ERROR: Failed to add data to the I/O buffer chain: %d\n", ret);
       (void)iob_free_chain(iob);
       return 0;
     }
@@ -191,7 +191,7 @@ static uint16_t udp_datahandler(FAR struct net_driver_s *dev, FAR struct udp_con
        * not free any I/O buffers.
        */
 
-      nllerr("ERROR: Failed to add data to the I/O buffer chain: %d\n", ret);
+      nerr("ERROR: Failed to add data to the I/O buffer chain: %d\n", ret);
       (void)iob_free_chain(iob);
       return 0;
     }
@@ -208,8 +208,8 @@ static uint16_t udp_datahandler(FAR struct net_driver_s *dev, FAR struct udp_con
            * does not free any I/O buffers.
            */
 
-          nllerr("ERROR: Failed to add data to the I/O buffer chain: %d\n",
-                 ret);
+          nerr("ERROR: Failed to add data to the I/O buffer chain: %d\n",
+               ret);
           (void)iob_free_chain(iob);
           return 0;
         }
@@ -220,12 +220,12 @@ static uint16_t udp_datahandler(FAR struct net_driver_s *dev, FAR struct udp_con
   ret = iob_tryadd_queue(iob, &conn->readahead);
   if (ret < 0)
     {
-      nllerr("ERROR: Failed to queue the I/O buffer chain: %d\n", ret);
+      nerr("ERROR: Failed to queue the I/O buffer chain: %d\n", ret);
       (void)iob_free_chain(iob);
       return 0;
     }
 
-  nllinfo("Buffered %d bytes\n", buflen);
+  ninfo("Buffered %d bytes\n", buflen);
   return buflen;
 }
 #endif /* CONFIG_NET_UDP_READAHEAD */
@@ -255,7 +255,7 @@ net_dataevent(FAR struct net_driver_s *dev, FAR struct udp_conn_s *conn,
    * can have zero-length with UDP_NEWDATA set just to cause an ACK).
    */
 
-  nllinfo("No receive on connection\n");
+  ninfo("No receive on connection\n");
 
 #ifdef CONFIG_NET_UDP_READAHEAD
   /* Save as the packet data as in the read-ahead buffer.  NOTE that
@@ -270,7 +270,7 @@ net_dataevent(FAR struct net_driver_s *dev, FAR struct udp_conn_s *conn,
        * read-ahead buffers to retain the data -- drop the packet.
        */
 
-     nllinfo("Dropped %d bytes\n", dev->d_len);
+     ninfo("Dropped %d bytes\n", dev->d_len);
 
 #ifdef CONFIG_NET_STATISTICS
       g_netstats.udp.drop++;
@@ -304,7 +304,7 @@ net_dataevent(FAR struct net_driver_s *dev, FAR struct udp_conn_s *conn,
 uint16_t udp_callback(FAR struct net_driver_s *dev,
                       FAR struct udp_conn_s *conn, uint16_t flags)
 {
-  nllinfo("flags: %04x\n", flags);
+  ninfo("flags: %04x\n", flags);
 
   /* Some sanity checking */
 
diff --git a/net/udp/udp_input.c b/net/udp/udp_input.c
index 9047cf02caa..6678e3e4b50 100644
--- a/net/udp/udp_input.c
+++ b/net/udp/udp_input.c
@@ -149,7 +149,7 @@ static int udp_input(FAR struct net_driver_s *dev, unsigned int iplen)
       g_netstats.udp.drop++;
       g_netstats.udp.chkerr++;
 #endif
-      nllwarn("WARNING: Bad UDP checksum\n");
+      nwarn("WARNING: Bad UDP checksum\n");
       dev->d_len = 0;
     }
   else
@@ -207,7 +207,7 @@ static int udp_input(FAR struct net_driver_s *dev, unsigned int iplen)
         }
       else
         {
-          nllwarn("WARNING: No listener on UDP port\n");
+          nwarn("WARNING: No listener on UDP port\n");
           dev->d_len = 0;
         }
     }
diff --git a/net/udp/udp_netpoll.c b/net/udp/udp_netpoll.c
index 0dc670fe105..eade182fa12 100644
--- a/net/udp/udp_netpoll.c
+++ b/net/udp/udp_netpoll.c
@@ -93,7 +93,7 @@ static uint16_t udp_poll_interrupt(FAR struct net_driver_s *dev, FAR void *conn,
 {
   FAR struct udp_poll_s *info = (FAR struct udp_poll_s *)pvpriv;
 
-  nllinfo("flags: %04x\n", flags);
+  ninfo("flags: %04x\n", flags);
 
   DEBUGASSERT(!info || (info->psock && info->fds));
 
diff --git a/net/udp/udp_psock_sendto.c b/net/udp/udp_psock_sendto.c
index b962dadbfdb..9210a5dcef6 100644
--- a/net/udp/udp_psock_sendto.c
+++ b/net/udp/udp_psock_sendto.c
@@ -224,7 +224,7 @@ static uint16_t sendto_interrupt(FAR struct net_driver_s *dev, FAR void *conn,
 {
   FAR struct sendto_s *pstate = (FAR struct sendto_s *)pvpriv;
 
-  nllinfo("flags: %04x\n", flags);
+  ninfo("flags: %04x\n", flags);
   if (pstate)
     {
       /* If the network device has gone down, then we will have terminate
@@ -235,7 +235,7 @@ static uint16_t sendto_interrupt(FAR struct net_driver_s *dev, FAR void *conn,
         {
           /* Terminate the transfer with an error. */
 
-          nllwarn("WARNING: Network is down\n");
+          nwarn("WARNING: Network is down\n");
           pstate->st_sndlen = -ENETUNREACH;
         }
 
@@ -257,7 +257,7 @@ static uint16_t sendto_interrupt(FAR struct net_driver_s *dev, FAR void *conn,
             {
               /* Yes.. report the timeout */
 
-              nllwarn("WARNING: SEND timeout\n");
+              nwarn("WARNING: SEND timeout\n");
               pstate->st_sndlen = -ETIMEDOUT;
             }
           else
diff --git a/net/udp/udp_send.c b/net/udp/udp_send.c
index 4395da2f8d5..f58bdf5a134 100644
--- a/net/udp/udp_send.c
+++ b/net/udp/udp_send.c
@@ -100,7 +100,7 @@ void udp_send(FAR struct net_driver_s *dev, FAR struct udp_conn_s *conn)
 {
   FAR struct udp_hdr_s *udp;
 
-  nllinfo("UDP payload: %d (%d) bytes\n", dev->d_sndlen, dev->d_len);
+  ninfo("UDP payload: %d (%d) bytes\n", dev->d_sndlen, dev->d_len);
 
   if (dev->d_sndlen > 0)
     {
@@ -252,7 +252,7 @@ void udp_send(FAR struct net_driver_s *dev, FAR struct udp_conn_s *conn)
         }
 #endif /* CONFIG_NET_UDP_CHECKSUMS */
 
-      nllinfo("Outgoing UDP packet length: %d\n", dev->d_len);
+      ninfo("Outgoing UDP packet length: %d\n", dev->d_len);
 
 #ifdef CONFIG_NET_STATISTICS
       g_netstats.udp.sent++;
diff --git a/sched/Kconfig b/sched/Kconfig
index 69b4945fd10..864220286ab 100644
--- a/sched/Kconfig
+++ b/sched/Kconfig
@@ -1013,7 +1013,7 @@ config MODULE_BUFFERINCR
 config MODULE_DUMPBUFFER
 	bool "Dump module buffers"
 	default n
-	depends on DEBUG_FEATURES && CONFIG_DEBUG_INFO
+	depends on DEBUG_INFO
 	---help---
 		Dump various module buffers for debug purposes
 
diff --git a/sched/group/group_setupidlefiles.c b/sched/group/group_setupidlefiles.c
index b40cfe5d80f..0d4eb19ca29 100644
--- a/sched/group/group_setupidlefiles.c
+++ b/sched/group/group_setupidlefiles.c
@@ -120,12 +120,12 @@ int group_setupidlefiles(FAR struct task_tcb_s *tcb)
 
       if (fd > 0)
         {
-          sllinfo("Open /dev/console fd: %d\n", fd);
+          sinfo("Open /dev/console fd: %d\n", fd);
           (void)close(fd);
         }
       else
         {
-          sllerr("ERROR: Failed to open /dev/console: %d\n", errno);
+          serr("ERROR: Failed to open /dev/console: %d\n", errno);
         }
 
       return -ENFILE;
diff --git a/sched/init/os_start.c b/sched/init/os_start.c
index cd13a1fa2e9..1a65af1403c 100644
--- a/sched/init/os_start.c
+++ b/sched/init/os_start.c
@@ -54,6 +54,7 @@
 #include  <nuttx/mm/shm.h>
 #include  <nuttx/kmalloc.h>
 #include  <nuttx/sched_note.h>
+#include  <nuttx/syslog/syslog.h>
 #include  <nuttx/init.h>
 
 #include  "sched/sched.h"
@@ -372,7 +373,7 @@ void os_start(void)
 #endif
   int i;
 
-  sllinfo("Entry\n");
+  sinfo("Entry\n");
 
   /* Boot up is complete */
 
@@ -757,7 +758,15 @@ void os_start(void)
       DEBUGVERIFY(group_initialize(&g_idletcb[cpu]));
       g_idletcb[cpu].cmn.group->tg_flags = GROUP_FLAG_NOCLDWAIT;
 #endif
-}
+    }
+
+  /* Start SYSLOG ***********************************************************/
+  /* Late initialization of the system logging device.  Some SYSLOG channel
+   * must be initialized late in the initialization sequence because it may
+   * depend on having IDLE task file structures setup.
+   */
+
+  syslog_initialize(SYSLOG_INIT_LATE);
 
 #ifdef CONFIG_SMP
   /* Start all CPUs *********************************************************/
diff --git a/sched/irq/irq_unexpectedisr.c b/sched/irq/irq_unexpectedisr.c
index 136abf5791b..9eb250fa491 100644
--- a/sched/irq/irq_unexpectedisr.c
+++ b/sched/irq/irq_unexpectedisr.c
@@ -61,7 +61,7 @@
 int irq_unexpected_isr(int irq, FAR void *context)
 {
   (void)up_irq_save();
-  _llerr("ERROR irq: %d\n", irq);
+  _err("ERROR irq: %d\n", irq);
   PANIC();
   return OK; /* Won't get here */
 }
diff --git a/sched/module/mod_insmod.c b/sched/module/mod_insmod.c
index 7ade292e6a6..3b4b5b3ceb0 100644
--- a/sched/module/mod_insmod.c
+++ b/sched/module/mod_insmod.c
@@ -212,7 +212,7 @@ int insmod(FAR const char *filename, FAR const char *modulename)
   mod_dumploadinfo(&loadinfo);
   if (ret != 0)
     {
-      sinfo("ERROR: Failed to initialize to load module: %d\n", ret);
+      serr("ERROR: Failed to initialize to load module: %d\n", ret);
       goto errout_with_lock;
     }
 
diff --git a/sched/paging/pg_miss.c b/sched/paging/pg_miss.c
index 2b6b44cb0dd..c3eb14cb7ca 100644
--- a/sched/paging/pg_miss.c
+++ b/sched/paging/pg_miss.c
@@ -132,7 +132,7 @@ void pg_miss(void)
    * always present in memory.
    */
 
-  pgllinfo("Blocking TCB: %p PID: %d\n", ftcb, ftcb->pid);
+  pginfo("Blocking TCB: %p PID: %d\n", ftcb, ftcb->pid);
   DEBUGASSERT(g_pgworker != ftcb->pid);
 
   /* Block the currently executing task
@@ -159,8 +159,8 @@ void pg_miss(void)
     {
       /* Reprioritize the page fill worker thread */
 
-      pgllinfo("New worker priority. %d->%d\n",
-               wtcb->sched_priority, ftcb->sched_priority);
+      pginfo("New worker priority. %d->%d\n",
+             wtcb->sched_priority, ftcb->sched_priority);
       sched_setpriority(wtcb, ftcb->sched_priority);
     }
 
@@ -171,7 +171,7 @@ void pg_miss(void)
 
   if (!g_pftcb)
     {
-      pgllinfo("Signaling worker. PID: %d\n", g_pgworker);
+      pginfo("Signaling worker. PID: %d\n", g_pgworker);
       kill(g_pgworker, SIGWORK);
     }
 }
diff --git a/sched/paging/pg_worker.c b/sched/paging/pg_worker.c
index b7385dcb62c..003897e52f7 100644
--- a/sched/paging/pg_worker.c
+++ b/sched/paging/pg_worker.c
@@ -155,7 +155,7 @@ static void pg_callback(FAR struct tcb_s *tcb, int result)
 {
   /* Verify that g_pftcb is non-NULL */
 
-  pgllinfo("g_pftcb: %p\n", g_pftcb);
+  pginfo("g_pftcb: %p\n", g_pftcb);
   if (g_pftcb)
     {
       FAR struct tcb_s *htcb = (FAR struct tcb_s *)g_waitingforfill.head;
@@ -181,8 +181,8 @@ static void pg_callback(FAR struct tcb_s *tcb, int result)
 
       if (priority > wtcb->sched_priority)
         {
-          pgllinfo("New worker priority. %d->%d\n",
-                   wtcb->sched_priority, priority);
+          pginfo("New worker priority. %d->%d\n",
+                 wtcb->sched_priority, priority);
           sched_setpriority(wtcb, priority);
         }
 
@@ -198,7 +198,7 @@ static void pg_callback(FAR struct tcb_s *tcb, int result)
 
   /* Signal the page fill worker thread (in any event) */
 
-  pgllinfo("Signaling worker. PID: %d\n", g_pgworker);
+  pginfo("Signaling worker. PID: %d\n", g_pgworker);
   kill(g_pgworker, SIGWORK);
 }
 #endif
@@ -246,7 +246,7 @@ static inline bool pg_dequeue(void)
       /* Remove the TCB from the head of the list (if any) */
 
       g_pftcb = (FAR struct tcb_s *)dq_remfirst((dq_queue_t *)&g_waitingforfill);
-      pgllinfo("g_pftcb: %p\n", g_pftcb);
+      pginfo("g_pftcb: %p\n", g_pftcb);
       if (g_pftcb != NULL)
         {
           /* Call the architecture-specific function up_checkmapping() to see if
@@ -292,8 +292,8 @@ static inline bool pg_dequeue(void)
 
                   /* Reduce the priority of the page fill worker thread */
 
-                  pgllinfo("New worker priority. %d->%d\n",
-                           wtcb->sched_priority, priority);
+                  pginfo("New worker priority. %d->%d\n",
+                         wtcb->sched_priority, priority);
                   sched_setpriority(wtcb, priority);
                 }
 
@@ -308,7 +308,7 @@ static inline bool pg_dequeue(void)
            * virtual address space -- just restart it.
            */
 
-          pgllinfo("Restarting TCB: %p\n", g_pftcb);
+          pginfo("Restarting TCB: %p\n", g_pftcb);
           up_unblock_task(g_pftcb);
         }
     }
@@ -365,7 +365,7 @@ static inline bool pg_startfill(void)
        * a page in-use, un-map it, and make it available.
        */
 
-      pgllinfo("Call up_allocpage(%p)\n", g_pftcb);
+      pginfo("Call up_allocpage(%p)\n", g_pftcb);
       result = up_allocpage(g_pftcb, &vpage);
       DEBUGASSERT(result == OK);
 
@@ -382,7 +382,7 @@ static inline bool pg_startfill(void)
        * status of the fill will be provided by return value from up_fillpage().
        */
 
-      pgllinfo("Call up_fillpage(%p)\n", g_pftcb);
+      pginfo("Call up_fillpage(%p)\n", g_pftcb);
       result = up_fillpage(g_pftcb, vpage);
       DEBUGASSERT(result == OK);
 #else
@@ -395,7 +395,7 @@ static inline bool pg_startfill(void)
        * This callback will probably from interrupt level.
        */
 
-      pgllinfo("Call up_fillpage(%p)\n", g_pftcb);
+      pginfo("Call up_fillpage(%p)\n", g_pftcb);
       result = up_fillpage(g_pftcb, vpage, pg_callback);
       DEBUGASSERT(result == OK);
 
@@ -422,7 +422,7 @@ static inline bool pg_startfill(void)
       return true;
     }
 
-  pgllinfo("Queue empty\n");
+  pginfo("Queue empty\n");
   return false;
 }
 
@@ -454,8 +454,8 @@ static inline void pg_alldone(void)
 {
   FAR struct tcb_s *wtcb = this_task();
   g_pftcb = NULL;
-  pgllinfo("New worker priority. %d->%d\n",
-           wtcb->sched_priority, CONFIG_PAGING_DEFPRIO);
+  pginfo("New worker priority. %d->%d\n",
+         wtcb->sched_priority, CONFIG_PAGING_DEFPRIO);
   sched_setpriority(wtcb, CONFIG_PAGING_DEFPRIO);
 }
 
@@ -490,7 +490,7 @@ static inline void pg_fillcomplete(void)
    * received the fill ready-to-run.
    */
 
-  pgllinfo("Restarting TCB: %p\n", g_pftcb);
+  pginfo("Restarting TCB: %p\n", g_pftcb);
   up_unblock_task(g_pftcb);
 }
 
@@ -532,7 +532,7 @@ int pg_worker(int argc, char *argv[])
    * fill completions should occur while this thread sleeps.
    */
 
-  pgllinfo("Started\n");
+  pginfo("Started\n");
   (void)up_irq_save();
   for (; ; )
     {
@@ -580,7 +580,7 @@ int pg_worker(int argc, char *argv[])
                * task that was blocked waiting for this page fill.
                */
 
-              pgllinfo("Restarting TCB: %p\n", g_pftcb);
+              pginfo("Restarting TCB: %p\n", g_pftcb);
               up_unblock_task(g_pftcb);
 
               /* Yes .. Start the next asynchronous fill.  Check the return
@@ -588,7 +588,7 @@ int pg_worker(int argc, char *argv[])
                * no fill was started).
                */
 
-              pgllinfo("Calling pg_startfill\n");
+              pginfo("Calling pg_startfill\n");
               if (!pg_startfill())
                 {
                   /* No fill was started.  This can mean only that all queued
@@ -596,7 +596,7 @@ int pg_worker(int argc, char *argv[])
                    * nothing more to do.
                    */
 
-                  pgllinfo("Call pg_alldone()\n");
+                  pginfo("Call pg_alldone()\n");
                   pg_alldone();
                 }
             }
@@ -608,7 +608,7 @@ int pg_worker(int argc, char *argv[])
 #ifdef CONFIG_PAGING_TIMEOUT_TICKS
           else
             {
-              pgllerr("ERROR: Timeout!\n");
+              pgerr("ERROR: Timeout!\n");
               ASSERT(clock_systimer() - g_starttime < CONFIG_PAGING_TIMEOUT_TICKS);
             }
 #endif
@@ -626,7 +626,7 @@ int pg_worker(int argc, char *argv[])
            * g_pftcb).
            */
 
-           pgllinfo("Calling pg_startfill\n");
+           pginfo("Calling pg_startfill\n");
            (void)pg_startfill();
         }
 #else
@@ -641,7 +641,7 @@ int pg_worker(int argc, char *argv[])
            * (false means that no fill was perforemd).
            */
 
-          pgllinfo("Calling pg_startfill\n");
+          pginfo("Calling pg_startfill\n");
           if (!pg_startfill())
             {
               /* Break out of the loop -- there is nothing more to do */
@@ -656,13 +656,13 @@ int pg_worker(int argc, char *argv[])
            * returns true.
            */
 
-          pgllinfo("Restarting TCB: %p\n", g_pftcb);
+          pginfo("Restarting TCB: %p\n", g_pftcb);
           up_unblock_task(g_pftcb);
         }
 
       /* All queued fills have been processed */
 
-      pgllinfo("Call pg_alldone()\n");
+      pginfo("Call pg_alldone()\n");
       pg_alldone();
 #endif
     }
diff --git a/sched/sched/Make.defs b/sched/sched/Make.defs
index dff73fdba21..e690aeaa83a 100644
--- a/sched/sched/Make.defs
+++ b/sched/sched/Make.defs
@@ -42,7 +42,8 @@ CSRCS += sched_getsockets.c sched_getstreams.c
 CSRCS += sched_setparam.c sched_setpriority.c sched_getparam.c
 CSRCS += sched_setscheduler.c sched_getscheduler.c
 CSRCS += sched_yield.c sched_rrgetinterval.c sched_foreach.c
-CSRCS += sched_lock.c sched_unlock.c sched_lockcount.c sched_self.c
+CSRCS += sched_lock.c sched_unlock.c sched_lockcount.c
+CSRCS += sched_idletask.c sched_self.c
 
 ifeq ($(CONFIG_PRIORITY_INHERITANCE),y)
 CSRCS += sched_reprioritize.c
diff --git a/sched/sched/sched_idletask.c b/sched/sched/sched_idletask.c
new file mode 100644
index 00000000000..9885aca1a7d
--- /dev/null
+++ b/sched/sched/sched_idletask.c
@@ -0,0 +1,95 @@
+/****************************************************************************
+ * sched/sched/sched_idletask.c
+ *
+ *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+ #include <nuttx/config.h>
+
+#include <stdbool.h>
+
+#include <nuttx/init.h>
+#include <nuttx/sched.h>
+
+#include "sched/sched.h"
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: sched_idletask
+ *
+ * Description:
+ *   Check if the caller is an IDLE thread.  For most implementations of
+ *   the SYSLOG output semaphore locking is required for mutual exclusion.
+ *   The idle threads are unable to lock semaphores because they cannot
+ *   want.  So IDLE thread output is a special case and is treated much as
+ *   we treat debug output from an interrupt handler.
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   true if the calling task is and IDLE thread.
+ *
+ ****************************************************************************/
+
+bool sched_idletask(void)
+{
+  FAR struct tcb_s *rtcb = this_task();
+
+  /* If called early in the initialization sequence, the tasks lists may not
+   * have been initialized and, in that case, rtcb may be NULL.
+   */
+
+  DEBUGASSERT(rtcb != NULL || g_os_initstate < OSINIT_TASKLISTS);
+  if (rtcb != NULL)
+    {
+      /* The IDLE task TCB is distinguishable by a few things:
+       *
+       * (1) It always lies at the end of the task list,
+       * (2) It always has priority zero, and
+       * (3) It should have the TCB_FLAG_CPU_LOCKED flag set.
+       */
+
+      return (rtcb->flink == NULL);
+    }
+
+  /* We must be on the IDLE thread if we are early in initialization */
+
+  return true;
+}
diff --git a/sched/sched/sched_sporadic.c b/sched/sched/sched_sporadic.c
index be16b6f473c..086e27d44f6 100644
--- a/sched/sched/sched_sporadic.c
+++ b/sched/sched/sched_sporadic.c
@@ -150,7 +150,7 @@ static int sporadic_set_lowpriority(FAR struct tcb_s *tcb)
   if (ret < 0)
     {
       int errcode = get_errno();
-      sllerr("ERROR: sched_reprioritize failed: %d\n", errcode);
+      serr("ERROR: sched_reprioritize failed: %d\n", errcode);
       return -errcode;
     }
 
@@ -218,7 +218,7 @@ static int sporadic_set_hipriority(FAR struct tcb_s *tcb)
   if (ret < 0)
     {
       int errcode = get_errno();
-      sllerr("ERROR: sched_reprioritize failed: %d\n", errcode);
+      serr("ERROR: sched_reprioritize failed: %d\n", errcode);
       return -errcode;
     }
 
@@ -771,7 +771,7 @@ int sched_sporadic_initialize(FAR struct tcb_s *tcb)
   sporadic = (FAR struct sporadic_s *)kmm_zalloc(sizeof(struct sporadic_s));
   if (sporadic == NULL)
     {
-      sllerr("ERROR: Failed to allocate sporadic data structure\n");
+      serr("ERROR: Failed to allocate sporadic data structure\n");
       return -ENOMEM;
     }
 
@@ -1078,8 +1078,8 @@ int sched_sporadic_resume(FAR struct tcb_s *tcb)
                * failure from the standpoint of higher level logic.
                */
 
-              sllerr("ERROR: Failed to allocate timer, nrepls=%d\n",
-                     sporadic->nrepls);
+              serr("ERROR: Failed to allocate timer, nrepls=%d\n",
+                   sporadic->nrepls);
             }
         }
     }
diff --git a/sched/sched/sched_timerexpiration.c b/sched/sched/sched_timerexpiration.c
index 7889b2e8e91..a0ebcff8c9c 100644
--- a/sched/sched/sched_timerexpiration.c
+++ b/sched/sched/sched_timerexpiration.c
@@ -362,7 +362,7 @@ static void sched_timer_start(unsigned int ticks)
 
       if (ret < 0)
         {
-          sllerr("ERROR: up_timer_start/up_alarm_start failed: %d\n");
+          serr("ERROR: up_timer_start/up_alarm_start failed: %d\n");
           UNUSED(ret);
         }
     }
diff --git a/sched/wqueue/kwork_hpthread.c b/sched/wqueue/kwork_hpthread.c
index 62725ec75ea..4ef84731eae 100644
--- a/sched/wqueue/kwork_hpthread.c
+++ b/sched/wqueue/kwork_hpthread.c
@@ -165,7 +165,7 @@ int work_hpstart(void)
       int errcode = errno;
       DEBUGASSERT(errcode > 0);
 
-      sllerr("ERROR: kernel_thread failed: %d\n", errcode);
+      serr("ERROR: kernel_thread failed: %d\n", errcode);
       return -errcode;
     }
 
diff --git a/sched/wqueue/kwork_lpthread.c b/sched/wqueue/kwork_lpthread.c
index 64266f9c700..84078c27518 100644
--- a/sched/wqueue/kwork_lpthread.c
+++ b/sched/wqueue/kwork_lpthread.c
@@ -212,7 +212,7 @@ int work_lpstart(void)
           int errcode = errno;
           DEBUGASSERT(errcode > 0);
 
-          sllerr("ERROR: kernel_thread %d failed: %d\n", wndx, errcode);
+          serr("ERROR: kernel_thread %d failed: %d\n", wndx, errcode);
           sched_unlock();
           return -errcode;
         }
diff --git a/syscall/syscall.csv b/syscall/syscall.csv
index a7d81215358..29271925c46 100644
--- a/syscall/syscall.csv
+++ b/syscall/syscall.csv
@@ -159,6 +159,7 @@
 "up_assert","assert.h","","void","FAR const uint8_t*","int"
 #"up_assert","assert.h","","void"
 "vfork","unistd.h","defined(CONFIG_ARCH_HAVE_VFORK)","pid_t"
+"_vsyslog","syslog.h","","int","int","FAR const IPTR char*","FAR va_list*"
 "wait","sys/wait.h","defined(CONFIG_SCHED_WAITPID) && defined(CONFIG_SCHED_HAVE_PARENT)","pid_t","int*"
 "waitid","sys/wait.h","defined(CONFIG_SCHED_WAITPID) && defined(CONFIG_SCHED_HAVE_PARENT)","int","idtype_t","id_t"," FAR siginfo_t *","int"
 "waitpid","sys/wait.h","defined(CONFIG_SCHED_WAITPID)","pid_t","pid_t","int*","int"
diff --git a/syscall/syscall_lookup.h b/syscall/syscall_lookup.h
index 8fb2f507b04..4cd1a3d6765 100644
--- a/syscall/syscall_lookup.h
+++ b/syscall/syscall_lookup.h
@@ -163,6 +163,10 @@ SYSCALL_LOOKUP(up_assert,                 2, STUB_up_assert)
   SYSCALL_LOOKUP(timer_settime,           4, STUB_timer_settime)
 #endif
 
+/* System logging */
+
+  SYSCALL_LOOKUP(_vsyslog,                3, STUB__vsyslog)
+
 /* The following are defined if either file or socket descriptor are
  * enabled.
  */
diff --git a/syscall/syscall_stublookup.c b/syscall/syscall_stublookup.c
index 63af75eb409..96862aa4062 100644
--- a/syscall/syscall_stublookup.c
+++ b/syscall/syscall_stublookup.c
@@ -165,6 +165,11 @@ uintptr_t STUB_timer_gettime(int nbr, uintptr_t parm1, uintptr_t parm2);
 uintptr_t STUB_timer_settime(int nbr, uintptr_t parm1, uintptr_t parm2,
             uintptr_t parm3, uintptr_t parm4);
 
+/* System logging */
+
+uintptr_t STUB__vsyslog(int nbr, uintptr_t parm1, uintptr_t parm2,
+            uintptr_t parm3);
+
 /* The following are defined if either file or socket descriptor are
  * enabled.
  */