diff --git a/arch/arm/src/arm/up_head.S b/arch/arm/src/arm/up_head.S
index 6afdeeb1741..7ed94bd9a6e 100644
--- a/arch/arm/src/arm/up_head.S
+++ b/arch/arm/src/arm/up_head.S
@@ -177,7 +177,7 @@
  * to the base address of the section containing both.
  */
 
-#ifndef CONFIG_ARCH_LOWVECTORS
+#ifdef CONFIG_ARCH_LOWVECTORS
 	.macro	mksection, section, pgtable
 	bic	\section, \pgtable, #0x000ff000
 	.endm
@@ -306,7 +306,6 @@ __start:
 #endif /* CONFIG_PAGING */
 #endif /* CONFIG_ARCH_ROMPGTABLE */
 
-
 	/* The following logic will set up the ARM920/ARM926 for normal operation.
 	 *
 	 * Here we expect to have:
diff --git a/arch/arm/src/imx/imx_boot.c b/arch/arm/src/imx/imx_boot.c
index 9cd4d390eaa..65a6951ce9b 100644
--- a/arch/arm/src/imx/imx_boot.c
+++ b/arch/arm/src/imx/imx_boot.c
@@ -117,7 +117,7 @@ extern void imx_boardinitialize(void);
 
 static inline void up_setlevel1entry(uint32_t paddr, uint32_t vaddr, uint32_t mmuflags)
 {
-  uint32_t *pgtable = (uint32_t*)PGTABLE_VBASE;
+  uint32_t *pgtable = (uint32_t*)PGTABLE_BASE_VADDR;
   uint32_t  index   = vaddr >> 20;
 
   /* Save the page table entry */
diff --git a/arch/arm/src/imx/imx_memorymap.h b/arch/arm/src/imx/imx_memorymap.h
index 0b7603befba..7eafc908a56 100644
--- a/arch/arm/src/imx/imx_memorymap.h
+++ b/arch/arm/src/imx/imx_memorymap.h
@@ -233,19 +233,19 @@
  * We will reuse this memory for coarse page tables as follows:
  */
 
-#define PGTABLE_PBASE             IMX_SDRAM0_PSECTION
-#define PGTABLE_SDRAM_PBASE       PGTABLE_PBASE
-#define PGTABLE_COARSE_PBASE      (PGTABLE_PBASE+0x00000800)
-#define PGTABLE_COARSE_PEND       (PGTABLE_PBASE+0x00003000)
-#define PTTABLE_PERIPHERALS_PBASE (PGTABLE_PBASE+0x00003000)
-#define PGTABLE_PEND              (PGTABLE_PBASE+0x00004000)
+#define PGTABLE_BASE_PADDR        IMX_SDRAM0_PSECTION
+#define PGTABLE_SDRAM_PADDR       PGTABLE_BASE_PADDR
+#define PGTABLE_COARSE_PBASE      (PGTABLE_BASE_PADDR+0x00000800)
+#define PGTABLE_COARSE_PEND       (PGTABLE_BASE_PADDR+0x00003000)
+#define PTTABLE_PERIPHERALS_PBASE (PGTABLE_BASE_PADDR+0x00003000)
+#define PGTABLE_PEND              (PGTABLE_BASE_PADDR+0x00004000)
 
-#define PGTABLE_VBASE             IMX_SDRAM_VSECTION
-#define PGTABLE_SDRAM_VBASE       PGTABLE_VBASE
-#define PGTABLE_COARSE_VBASE      (PGTABLE_VBASE+0x00000800)
-#define PGTABLE_COARSE_VEND       (PGTABLE_VBASE+0x00003000)
-#define PTTABLE_PERIPHERALS_VBASE (PGTABLE_VBASE+0x00003000)
-#define PGTABLE_VEND              (PGTABLE_VBASE+0x00004000)
+#define PGTABLE_BASE_VADDR        IMX_SDRAM_VSECTION
+#define PGTABLE_SDRAM_VADDR       PGTABLE_BASE_VADDR
+#define PGTABLE_COARSE_VBASE      (PGTABLE_BASE_VADDR+0x00000800)
+#define PGTABLE_COARSE_VEND       (PGTABLE_BASE_VADDR+0x00003000)
+#define PTTABLE_PERIPHERALS_VBASE (PGTABLE_BASE_VADDR+0x00003000)
+#define PGTABLE_VEND              (PGTABLE_BASE_VADDR+0x00004000)
 
 #define PGTABLE_COARSE_TABLE_SIZE (4*256)
 #define PGTABLE_COARSE_ALLOC      (PGTABLE_COARSE_VEND-PGTABLE_COARSE_VBASE)