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SAMA5: Adapt clocking for different boot modes. New header files for AXI matrix, BSC, and SFR

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This commit is contained in:
Gregory Nutt
2013-07-23 13:54:49 -06:00
parent ae3f2b2876
commit 596cdf2982
12 changed files with 680 additions and 188 deletions
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arch/arm/src/lpc43xx/Kconfig
+10 -10
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@@ -89,36 +89,36 @@ config ARCH_FAMILY_LPC4357
choice choice
prompt "LPC43XX Boot Configuration" prompt "LPC43XX Boot Configuration"
default BOOT_SRAM default LPC43_BOOT_SRAM
depends on ARCH_CHIP_LPC43XX depends on ARCH_CHIP_LPC43XX
---help--- ---help---
The startup code needs to know if the code is running from internal FLASH, The startup code needs to know if the code is running from internal FLASH,
external FLASH, SPIFI, or SRAM in order to initialize properly. Note that external FLASH, SPIFI, or SRAM in order to initialize properly. Note that
a boot device is not specified for cases where the code is copied into SRAM; a boot device is not specified for cases where the code is copied into SRAM;
those cases are all covered by BOOT_SRAM. those cases are all covered by LPC43_BOOT_SRAM.
config BOOT_SRAM config LPC43_BOOT_SRAM
bool "Running from SRAM" bool "Running from SRAM"
config BOOT_SPIFI config LPC43_BOOT_SPIFI
bool "Running from QuadFLASH" bool "Running from QuadFLASH"
config BOOT_FLASHA config LPC43_BOOT_FLASHA
bool "Running in internal FLASHA" bool "Running in internal FLASHA"
config BOOT_FLASHB config LPC43_BOOT_FLASHB
bool "Running in internal FLASHA" bool "Running in internal FLASHA"
config BOOT_CS0FLASH config LPC43_BOOT_CS0FLASH
bool "Running in external FLASH CS0" bool "Running in external FLASH CS0"
config BOOT_CS1FLASH config LPC43_BOOT_CS1FLASH
bool "Running in external FLASH CS1" bool "Running in external FLASH CS1"
config BOOT_CS2FLASH config LPC43_BOOT_CS2FLASH
bool "Running in external FLASH CS2" bool "Running in external FLASH CS2"
config BOOT_CS3FLASH config LPC43_BOOT_CS3FLASH
bool "Running in external FLASH CS3" bool "Running in external FLASH CS3"
endchoice endchoice
arch/arm/src/lpc43xx/lpc43_allocateheap.c
+1 -1
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@@ -141,7 +141,7 @@
/* Check for Configuration A. */ /* Check for Configuration A. */
#ifndef CONFIG_BOOT_SRAM #ifndef CONFIG_LPC43_BOOT_SRAM
/* Configuration A */ /* Configuration A */
/* CONFIG_DRAM_START should be set to the base of AHB SRAM, local 0. */ /* CONFIG_DRAM_START should be set to the base of AHB SRAM, local 0. */
arch/arm/src/lpc43xx/lpc43_start.c
+6 -6
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@@ -129,31 +129,31 @@ static inline void lpc43_setbootrom(void)
* *
****************************************************************************/ ****************************************************************************/
#if defined(CONFIG_BOOT_CS0FLASH) || defined(CONFIG_BOOT_CS1FLASH) || \ #if defined(CONFIG_LPC43_BOOT_CS0FLASH) || defined(CONFIG_LPC43_BOOT_CS1FLASH) || \
defined(CONFIG_BOOT_CS2FLASH) || defined(CONFIG_BOOT_CS3FLASH) defined(CONFIG_LPC43_BOOT_CS2FLASH) || defined(CONFIG_LPC43_BOOT_CS3FLASH)
static inline void lpc43_enabuffering(void) static inline void lpc43_enabuffering(void)
{ {
uint32_t regval; uint32_t regval;
#ifdef CONFIG_BOOT_CS0FLASH #ifdef CONFIG_LPC43_BOOT_CS0FLASH
regval = getreg32(LPC43_EMC_STATCONFIG0); regval = getreg32(LPC43_EMC_STATCONFIG0);
regval |= EMC_STATCONFIG_BENA regval |= EMC_STATCONFIG_BENA
putreg32(regval, LPC43_EMC_STATCONFIG0); putreg32(regval, LPC43_EMC_STATCONFIG0);
#endif #endif
#ifdef CONFIG_BOOT_CS1FLASH #ifdef CONFIG_LPC43_BOOT_CS1FLASH
regval = getreg32(LPC43_EMC_STATCONFIG1); regval = getreg32(LPC43_EMC_STATCONFIG1);
regval |= EMC_STATCONFIG_BENA regval |= EMC_STATCONFIG_BENA
putreg32(regval, LPC43_EMC_STATCONFIG1); putreg32(regval, LPC43_EMC_STATCONFIG1);
#endif #endif
#ifdef CONFIG_BOOT_CS2FLASH #ifdef CONFIG_LPC43_BOOT_CS2FLASH
regval = getreg32(LPC43_EMC_STATCONFIG2); regval = getreg32(LPC43_EMC_STATCONFIG2);
regval |= EMC_STATCONFIG_BENA regval |= EMC_STATCONFIG_BENA
putreg32(regval, LPC43_EMC_STATCONFIG2); putreg32(regval, LPC43_EMC_STATCONFIG2);
#endif #endif
#ifdef CONFIG_BOOT_CS3FLASH #ifdef CONFIG_LPC43_BOOT_CS3FLASH
regval = getreg32(LPC43_EMC_STATCONFIG3); regval = getreg32(LPC43_EMC_STATCONFIG3);
regval |= EMC_STATCONFIG_BENA regval |= EMC_STATCONFIG_BENA
putreg32(regval, LPC43_EMC_STATCONFIG3); putreg32(regval, LPC43_EMC_STATCONFIG3);
arch/arm/src/sama5/Kconfig
+29
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@@ -236,4 +236,33 @@ config PIOE_IRQ
endif endif
choice
prompt "SAMA5 Boot Configuration"
default SAMA5_BOOT_SRAM
---help---
The startup code needs to know if the code is running from internal SRAM,
external SRAM, or CS0-3 in order to initialize properly. Note that the
boot device is not specified for cases where the code is copied into SRAM;
those cases are all covered by SAMA5_BOOT_SRAM.
config SAMA5_BOOT_SRAM
bool "Running from internal SRAM"
config SAMA5_BOOT_SDRAM
bool "Running from external SDRAM"
config SAMA5_BOOT_CS0FLASH
bool "Running in external FLASH CS0"
config SAMA5_BOOT_CS1FLASH
bool "Running in external FLASH CS1"
config SAMA5_BOOT_CS2FLASH
bool "Running in external FLASH CS2"
config SAMA5_BOOT_CS3FLASH
bool "Running in external FLASH CS3"
endchoice
endif endif
arch/arm/src/sama5/chip/sam_aximx.h
+71
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@@ -0,0 +1,71 @@
/************************************************************************************
* arch/arm/src/sama5/chip/sam_aximx.h
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMA5_CHIP_SAM_AXIMX_H
#define __ARCH_ARM_SRC_SAMA5_CHIP_SAM_AXIMX_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "chip/sam_memorymap.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* AXIMX Register Offsets ***********************************************************/
#define SAM_AXIMX_REMAP_OFFSET 0x0000 /* Remap Register */
/* AXIMX Register Addresses *********************************************************/
#define SAM_AXIMX_REMAP (SAM_AXIMX_VSECTION+SAM_AXIMX_REMAP_OFFSET)
/* AXIMX Register Bit Definitions ***************************************************/
/* Remap Register
*
* Boot state: ROM is seen at address 0x00000000
* Remap State 0: SRAM is seen at address 0x00000000 (through AHB slave interface)
* instead of ROM.
* Remap State 1: HEBI is seen at address 0x00000000 (through AHB slave interface)
* instead of ROM for external boot.
*/
#define AXIMX_REMAP_REMAP0 (1 << 0) /* Remap State 0 */
#define AXIMX_REMAP_REMAP1 (1 << 1) /* Remap State 1 */
#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_AXIMX_H */
arch/arm/src/sama5/chip/sam_bsc.h
+67
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@@ -0,0 +1,67 @@
/************************************************************************************
* arch/arm/src/sama5/chip/sam_bsc.h
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMA5_CHIP_SAM_BSC_H
#define __ARCH_ARM_SRC_SAMA5_CHIP_SAM_BSC_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "chip/sam_memorymap.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* BSC Register Offsets *************************************************************/
#define SAM_BSC_CR_OFFSET 0x0000 /* Boot Sequence Configuration Register */
/* BSC Register Addresses ***********************************************************/
#define SAM_BSC_CR (SAM_BSC_VBASE+SAM_BSC_CR_OFFSET)
/* BSC Register Bit Definitions *****************************************************/
/* Boot Sequence Configuration Register */
#define BSC_CR_BOOT_SHIFT (0) /* Bits 0-7: Boot Media Sequence */
#define BSC_CR_BOOT_MASK (0xff << BSC_CR_BOOT_SHIFT)
#define BSC_CR_BOOTKEY_SHIFT (16) /* Bits 16-31: Book key */
#define BSC_CR_BOOTKEY_MASK (0xffff << BSC_CR_BOOTKEY_SHIFT)
# define BSC_CR_BOOTKEY (0x6683 << BSC_CR_BOOTKEY_SHIFT)
#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_BSC_H */
arch/arm/src/sama5/chip/sam_matrix.h
+71 -71
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@@ -130,80 +130,80 @@
/* MATRIX register adresses *************************************************************/ /* MATRIX register adresses *************************************************************/
#define SAM_MATRIX_MCFG(n)) (SAM_MATRIX_BASE+SAM_MATRIX_MCFG_OFFSET(n)) #define SAM_MATRIX_MCFG(n)) (SAM_MATRIX_VBASE+SAM_MATRIX_MCFG_OFFSET(n))
#define SAM_MATRIX_MCFG0 (SAM_MATRIX_BASE+SAM_MATRIX_MCFG0_OFFSET) #define SAM_MATRIX_MCFG0 (SAM_MATRIX_VBASE+SAM_MATRIX_MCFG0_OFFSET)
#define SAM_MATRIX_MCFG1 (SAM_MATRIX_BASE+SAM_MATRIX_MCFG1_OFFSET) #define SAM_MATRIX_MCFG1 (SAM_MATRIX_VBASE+SAM_MATRIX_MCFG1_OFFSET)
#define SAM_MATRIX_MCFG2 (SAM_MATRIX_BASE+SAM_MATRIX_MCFG2_OFFSET) #define SAM_MATRIX_MCFG2 (SAM_MATRIX_VBASE+SAM_MATRIX_MCFG2_OFFSET)
#define SAM_MATRIX_MCFG3 (SAM_MATRIX_BASE+SAM_MATRIX_MCFG3_OFFSET) #define SAM_MATRIX_MCFG3 (SAM_MATRIX_VBASE+SAM_MATRIX_MCFG3_OFFSET)
#define SAM_MATRIX_MCFG4 (SAM_MATRIX_BASE+SAM_MATRIX_MCFG4_OFFSET) #define SAM_MATRIX_MCFG4 (SAM_MATRIX_VBASE+SAM_MATRIX_MCFG4_OFFSET)
#define SAM_MATRIX_MCFG5 (SAM_MATRIX_BASE+SAM_MATRIX_MCFG5_OFFSET) #define SAM_MATRIX_MCFG5 (SAM_MATRIX_VBASE+SAM_MATRIX_MCFG5_OFFSET)
#define SAM_MATRIX_MCFG6 (SAM_MATRIX_BASE+SAM_MATRIX_MCFG6_OFFSET) #define SAM_MATRIX_MCFG6 (SAM_MATRIX_VBASE+SAM_MATRIX_MCFG6_OFFSET)
#define SAM_MATRIX_MCFG7 (SAM_MATRIX_BASE+SAM_MATRIX_MCFG7_OFFSET) #define SAM_MATRIX_MCFG7 (SAM_MATRIX_VBASE+SAM_MATRIX_MCFG7_OFFSET)
#define SAM_MATRIX_MCFG8 (SAM_MATRIX_BASE+SAM_MATRIX_MCFG8_OFFSET) #define SAM_MATRIX_MCFG8 (SAM_MATRIX_VBASE+SAM_MATRIX_MCFG8_OFFSET)
#define SAM_MATRIX_MCFG9 (SAM_MATRIX_BASE+SAM_MATRIX_MCFG9_OFFSET) #define SAM_MATRIX_MCFG9 (SAM_MATRIX_VBASE+SAM_MATRIX_MCFG9_OFFSET)
#define SAM_MATRIX_MCFG10 (SAM_MATRIX_BASE+SAM_MATRIX_MCFG10_OFFSET) #define SAM_MATRIX_MCFG10 (SAM_MATRIX_VBASE+SAM_MATRIX_MCFG10_OFFSET)
#define SAM_MATRIX_MCFG11 (SAM_MATRIX_BASE+SAM_MATRIX_MCFG11_OFFSET) #define SAM_MATRIX_MCFG11 (SAM_MATRIX_VBASE+SAM_MATRIX_MCFG11_OFFSET)
#define SAM_MATRIX_MCFG12 (SAM_MATRIX_BASE+SAM_MATRIX_MCFG12_OFFSET) #define SAM_MATRIX_MCFG12 (SAM_MATRIX_VBASE+SAM_MATRIX_MCFG12_OFFSET)
#define SAM_MATRIX_MCFG13 (SAM_MATRIX_BASE+SAM_MATRIX_MCFG13_OFFSET) #define SAM_MATRIX_MCFG13 (SAM_MATRIX_VBASE+SAM_MATRIX_MCFG13_OFFSET)
#define SAM_MATRIX_MCFG14 (SAM_MATRIX_BASE+SAM_MATRIX_MCFG14_OFFSET) #define SAM_MATRIX_MCFG14 (SAM_MATRIX_VBASE+SAM_MATRIX_MCFG14_OFFSET)
#define SAM_MATRIX_MCFG15 (SAM_MATRIX_BASE+SAM_MATRIX_MCFG15_OFFSET) #define SAM_MATRIX_MCFG15 (SAM_MATRIX_VBASE+SAM_MATRIX_MCFG15_OFFSET)
#define SAM_MATRIX_SCFG(n) (SAM_MATRIX_BASE+SAM_MATRIX_SCFG_OFFSET(n)) #define SAM_MATRIX_SCFG(n) (SAM_MATRIX_VBASE+SAM_MATRIX_SCFG_OFFSET(n))
#define SAM_MATRIX_SCFG0 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG0_OFFSET) #define SAM_MATRIX_SCFG0 (SAM_MATRIX_VBASE+SAM_MATRIX_SCFG0_OFFSET)
#define SAM_MATRIX_SCFG1 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG1_OFFSET) #define SAM_MATRIX_SCFG1 (SAM_MATRIX_VBASE+SAM_MATRIX_SCFG1_OFFSET)
#define SAM_MATRIX_SCFG2 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG2_OFFSET) #define SAM_MATRIX_SCFG2 (SAM_MATRIX_VBASE+SAM_MATRIX_SCFG2_OFFSET)
#define SAM_MATRIX_SCFG3 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG3_OFFSET) #define SAM_MATRIX_SCFG3 (SAM_MATRIX_VBASE+SAM_MATRIX_SCFG3_OFFSET)
#define SAM_MATRIX_SCFG4 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG4_OFFSET) #define SAM_MATRIX_SCFG4 (SAM_MATRIX_VBASE+SAM_MATRIX_SCFG4_OFFSET)
#define SAM_MATRIX_SCFG5 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG5_OFFSET) #define SAM_MATRIX_SCFG5 (SAM_MATRIX_VBASE+SAM_MATRIX_SCFG5_OFFSET)
#define SAM_MATRIX_SCFG6 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG6_OFFSET) #define SAM_MATRIX_SCFG6 (SAM_MATRIX_VBASE+SAM_MATRIX_SCFG6_OFFSET)
#define SAM_MATRIX_SCFG7 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG7_OFFSET) #define SAM_MATRIX_SCFG7 (SAM_MATRIX_VBASE+SAM_MATRIX_SCFG7_OFFSET)
#define SAM_MATRIX_SCFG8 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG8_OFFSET) #define SAM_MATRIX_SCFG8 (SAM_MATRIX_VBASE+SAM_MATRIX_SCFG8_OFFSET)
#define SAM_MATRIX_SCFG9 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG9_OFFSET) #define SAM_MATRIX_SCFG9 (SAM_MATRIX_VBASE+SAM_MATRIX_SCFG9_OFFSET)
#define SAM_MATRIX_SCFG10 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG10_OFFSET) #define SAM_MATRIX_SCFG10 (SAM_MATRIX_VBASE+SAM_MATRIX_SCFG10_OFFSET)
#define SAM_MATRIX_SCFG11 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG11_OFFSET) #define SAM_MATRIX_SCFG11 (SAM_MATRIX_VBASE+SAM_MATRIX_SCFG11_OFFSET)
#define SAM_MATRIX_SCFG12 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG12_OFFSET) #define SAM_MATRIX_SCFG12 (SAM_MATRIX_VBASE+SAM_MATRIX_SCFG12_OFFSET)
#define SAM_MATRIX_SCFG13 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG13_OFFSET) #define SAM_MATRIX_SCFG13 (SAM_MATRIX_VBASE+SAM_MATRIX_SCFG13_OFFSET)
#define SAM_MATRIX_SCFG14 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG14_OFFSET) #define SAM_MATRIX_SCFG14 (SAM_MATRIX_VBASE+SAM_MATRIX_SCFG14_OFFSET)
#define SAM_MATRIX_SCFG15 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG15_OFFSET) #define SAM_MATRIX_SCFG15 (SAM_MATRIX_VBASE+SAM_MATRIX_SCFG15_OFFSET)
#define SAM_MATRIX_PRAS(n) (SAM_MATRIX_BASE+SAM_MATRIX_PRAS_OFFSET(n)) #define SAM_MATRIX_PRAS(n) (SAM_MATRIX_VBASE+SAM_MATRIX_PRAS_OFFSET(n))
#define SAM_MATRIX_PRBS(n) (SAM_MATRIX_BASE+SAM_MATRIX_PRBS_OFFSET(n)) #define SAM_MATRIX_PRBS(n) (SAM_MATRIX_VBASE+SAM_MATRIX_PRBS_OFFSET(n))
#define SAM_MATRIX_PRAS0 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS0_OFFSET) #define SAM_MATRIX_PRAS0 (SAM_MATRIX_VBASE+SAM_MATRIX_PRAS0_OFFSET)
#define SAM_MATRIX_PRBS0 (SAM_MATRIX_BASE+SAM_MATRIX_PRBS0_OFFSET) #define SAM_MATRIX_PRBS0 (SAM_MATRIX_VBASE+SAM_MATRIX_PRBS0_OFFSET)
#define SAM_MATRIX_PRAS1 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS1_OFFSET) #define SAM_MATRIX_PRAS1 (SAM_MATRIX_VBASE+SAM_MATRIX_PRAS1_OFFSET)
#define SAM_MATRIX_PRBS1 (SAM_MATRIX_BASE+SAM_MATRIX_PRBS1_OFFSET) #define SAM_MATRIX_PRBS1 (SAM_MATRIX_VBASE+SAM_MATRIX_PRBS1_OFFSET)
#define SAM_MATRIX_PRAS2 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS2_OFFSET) #define SAM_MATRIX_PRAS2 (SAM_MATRIX_VBASE+SAM_MATRIX_PRAS2_OFFSET)
#define SAM_MATRIX_PRBS2 (SAM_MATRIX_BASE+SAM_MATRIX_PRBS2_OFFSET) #define SAM_MATRIX_PRBS2 (SAM_MATRIX_VBASE+SAM_MATRIX_PRBS2_OFFSET)
#define SAM_MATRIX_PRAS3 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS3_OFFSET) #define SAM_MATRIX_PRAS3 (SAM_MATRIX_VBASE+SAM_MATRIX_PRAS3_OFFSET)
#define SAM_MATRIX_PRBS3 (SAM_MATRIX_BASE+SAM_MATRIX_PRBS3_OFFSET) #define SAM_MATRIX_PRBS3 (SAM_MATRIX_VBASE+SAM_MATRIX_PRBS3_OFFSET)
#define SAM_MATRIX_PRAS4 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS4_OFFSET) #define SAM_MATRIX_PRAS4 (SAM_MATRIX_VBASE+SAM_MATRIX_PRAS4_OFFSET)
#define SAM_MATRIX_PRBS4 (SAM_MATRIX_BASE+SAM_MATRIX_PRBS4_OFFSET) #define SAM_MATRIX_PRBS4 (SAM_MATRIX_VBASE+SAM_MATRIX_PRBS4_OFFSET)
#define SAM_MATRIX_PRAS5 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS5_OFFSET) #define SAM_MATRIX_PRAS5 (SAM_MATRIX_VBASE+SAM_MATRIX_PRAS5_OFFSET)
#define SAM_MATRIX_PRBS5 (SAM_MATRIX_BASE+SAM_MATRIX_PRBS5_OFFSET) #define SAM_MATRIX_PRBS5 (SAM_MATRIX_VBASE+SAM_MATRIX_PRBS5_OFFSET)
#define SAM_MATRIX_PRAS6 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS6_OFFSET) #define SAM_MATRIX_PRAS6 (SAM_MATRIX_VBASE+SAM_MATRIX_PRAS6_OFFSET)
#define SAM_MATRIX_PRBS6 (SAM_MATRIX_BASE+SAM_MATRIX_PRBS6_OFFSET) #define SAM_MATRIX_PRBS6 (SAM_MATRIX_VBASE+SAM_MATRIX_PRBS6_OFFSET)
#define SAM_MATRIX_PRAS7 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS7_OFFSET) #define SAM_MATRIX_PRAS7 (SAM_MATRIX_VBASE+SAM_MATRIX_PRAS7_OFFSET)
#define SAM_MATRIX_PRBS7 (SAM_MATRIX_BASE+SAM_MATRIX_PRBS7_OFFSET) #define SAM_MATRIX_PRBS7 (SAM_MATRIX_VBASE+SAM_MATRIX_PRBS7_OFFSET)
#define SAM_MATRIX_PRAS8 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS8_OFFSET) #define SAM_MATRIX_PRAS8 (SAM_MATRIX_VBASE+SAM_MATRIX_PRAS8_OFFSET)
#define SAM_MATRIX_PRBS8 (SAM_MATRIX_BASE+SAM_MATRIX_PRBS8_OFFSET) #define SAM_MATRIX_PRBS8 (SAM_MATRIX_VBASE+SAM_MATRIX_PRBS8_OFFSET)
#define SAM_MATRIX_PRAS9 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS9_OFFSET) #define SAM_MATRIX_PRAS9 (SAM_MATRIX_VBASE+SAM_MATRIX_PRAS9_OFFSET)
#define SAM_MATRIX_PRBS9 (SAM_MATRIX_BASE+SAM_MATRIX_PRBS9_OFFSET) #define SAM_MATRIX_PRBS9 (SAM_MATRIX_VBASE+SAM_MATRIX_PRBS9_OFFSET)
#define SAM_MATRIX_PRAS10 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS10_OFFSET) #define SAM_MATRIX_PRAS10 (SAM_MATRIX_VBASE+SAM_MATRIX_PRAS10_OFFSET)
#define SAM_MATRIX_PRBS10 (SAM_MATRIX_BASE+SAM_MATRIX_PRBS10_OFFSET) #define SAM_MATRIX_PRBS10 (SAM_MATRIX_VBASE+SAM_MATRIX_PRBS10_OFFSET)
#define SAM_MATRIX_PRAS11 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS11_OFFSET) #define SAM_MATRIX_PRAS11 (SAM_MATRIX_VBASE+SAM_MATRIX_PRAS11_OFFSET)
#define SAM_MATRIX_PRBS11 (SAM_MATRIX_BASE+SAM_MATRIX_PRBS11_OFFSET) #define SAM_MATRIX_PRBS11 (SAM_MATRIX_VBASE+SAM_MATRIX_PRBS11_OFFSET)
#define SAM_MATRIX_PRAS12 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS12_OFFSET) #define SAM_MATRIX_PRAS12 (SAM_MATRIX_VBASE+SAM_MATRIX_PRAS12_OFFSET)
#define SAM_MATRIX_PRBS12 (SAM_MATRIX_BASE+SAM_MATRIX_PRBS12_OFFSET) #define SAM_MATRIX_PRBS12 (SAM_MATRIX_VBASE+SAM_MATRIX_PRBS12_OFFSET)
#define SAM_MATRIX_PRAS13 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS13_OFFSET) #define SAM_MATRIX_PRAS13 (SAM_MATRIX_VBASE+SAM_MATRIX_PRAS13_OFFSET)
#define SAM_MATRIX_PRBS13 (SAM_MATRIX_BASE+SAM_MATRIX_PRBS13_OFFSET) #define SAM_MATRIX_PRBS13 (SAM_MATRIX_VBASE+SAM_MATRIX_PRBS13_OFFSET)
#define SAM_MATRIX_PRAS14 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS14_OFFSET) #define SAM_MATRIX_PRAS14 (SAM_MATRIX_VBASE+SAM_MATRIX_PRAS14_OFFSET)
#define SAM_MATRIX_PRBS14 (SAM_MATRIX_BASE+SAM_MATRIX_PRBS14_OFFSET) #define SAM_MATRIX_PRBS14 (SAM_MATRIX_VBASE+SAM_MATRIX_PRBS14_OFFSET)
#define SAM_MATRIX_PRAS15 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS15_OFFSET) #define SAM_MATRIX_PRAS15 (SAM_MATRIX_VBASE+SAM_MATRIX_PRAS15_OFFSET)
#define SAM_MATRIX_PRBS15 (SAM_MATRIX_BASE+SAM_MATRIX_PRBS15_OFFSET) #define SAM_MATRIX_PRBS15 (SAM_MATRIX_VBASE+SAM_MATRIX_PRBS15_OFFSET)
#define SAM_MATRIX_MRCR (SAM_MATRIX_BASE+SAM_MATRIX_MRCR_OFFSET) #define SAM_MATRIX_MRCR (SAM_MATRIX_VBASE+SAM_MATRIX_MRCR_OFFSET)
#define SAM_MATRIX_WPMR (SAM_MATRIX_BASE+SAM_MATRIX_WPMR_OFFSET) #define SAM_MATRIX_WPMR (SAM_MATRIX_VBASE+SAM_MATRIX_WPMR_OFFSET)
#define SAM_MATRIX_WPSR (SAM_MATRIX_BASE+SAM_MATRIX_WPSR_OFFSET) #define SAM_MATRIX_WPSR (SAM_MATRIX_VBASE+SAM_MATRIX_WPSR_OFFSET)
/* MATRIX register bit definitions ******************************************************/ /* MATRIX register bit definitions ******************************************************/
/* Master Configuration Registers */ /* Master Configuration Registers */
arch/arm/src/sama5/chip/sam_sfr.h
+126
View File
@@ -0,0 +1,126 @@
/************************************************************************************
* arch/arm/src/sama5/chip/sam_sfr.h
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMA5_CHIP_SAM_SFR_H
#define __ARCH_ARM_SRC_SAMA5_CHIP_SAM_SFR_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "chip/sam_memorymap.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* SFR Register Offsets *************************************************************/
/* 0x0000-0x000c: Reserved */
#define SAM_SFR_OHCIICR_OFFSET 0x1000 /* OHCI Interrupt Configuration Register */
#define SAM_SFR_OHCIISR_OFFSET 0x0014 /* OHCI Interrupt Status Register */
/* 0x0018-0x001c: Reserved */
#define SAM_SFR_SECURE_OFFSET 0x0028 /* Security Configuration Register */
/* 0x002c: Reserved */
#define SAM_SFR_UTMICKTRIM_OFFSET 0x0030 /* UTMI Clock Trimming Register */
#define SAM_SFR_EBICFG_OFFSET 0x0040 /* EBI Configuration Register */
/* 0x0044-0x3ffc: Reserved */
/* SFR Register Addresses ***********************************************************/
#define SAM_SFR_OHCIICR (SAM_SFR_VBASE+SAM_SFR_OHCIICR_OFFSET)
#define SAM_SFR_OHCIISR (SAM_SFR_VBASE+SAM_SFR_OHCIISR_OFFSET)
#define SAM_SFR_SECURE (SAM_SFR_VBASE+SAM_SFR_SECURE_OFFSET)
#define SAM_SFR_UTMICKTRIM (SAM_SFR_VBASE+SAM_SFR_UTMICKTRIM_OFFSET)
#define SAM_SFR_EBICFG (SAM_SFR_VBASE+SAM_SFR_EBICFG_OFFSET)
/* SFR Register Bit Definitions *****************************************************/
/* OHCI Interrupt Configuration Register */
#define SFR_OHCIICR_RES0 (1 << 0) /* Bit 0: USB port 0 reset */
#define SFR_OHCIICR_RES1 (1 << 1) /* Bit 1: USB port 1 reset */
#define SFR_OHCIICR_RES2 (1 << 2) /* Bit 2: USB port 2 reset */
#define SFR_OHCIICR_ARIE (1 << 4) /* Bit 4: OHCI asynchronous resume interrupt enable */
#define SFR_OHCIICR_APPSTART (0) /* Bit 5: Reserved, must write 0 */
#define SFR_OHCIICR_UDPPUDIS (1 << 23) /* Bit 23: USB device pull-up disable */
/* OHCI Interrupt Status Register */
#define SFR_OHCIISR_RIS0 (1 << 0) /* Bit 0: USB port 0 resume detected */
#define SFR_OHCIISR_RIS1 (1 << 1) /* Bit 1: USB port 1 resume detected */
#define SFR_OHCIISR_RIS2 (1 << 2) /* Bit 2: USB port 2 resume detected */
/* Security Configuration Register */
#define SFR_SECURE_ROM (1 << 0) /* Bit 0: Disable Access to ROM Code */
#define SFR_SECURE_FUSE (1 << 8) /* Bit 8: Disable Access to Fuse Controller */
/* UTMI Clock Trimming Register */
#define SFR_UTMICKTRIM_FREQ_SHIFT (0) /* Bits 0-1: UTMI Reference Clock Frequency */
#define SFR_UTMICKTRIM_FREQ_MASK (3 << SFR_UTMICKTRIM_FREQ_SHIFT)
# define SFR_UTMICKTRIM_FREQ_12MHZ (0 << SFR_UTMICKTRIM_FREQ_SHIFT) /* 12 MHz reference clock */
# define SFR_UTMICKTRIM_FREQ_16MHZ (1 << SFR_UTMICKTRIM_FREQ_SHIFT) /* 16 MHz reference clock */
# define SFR_UTMICKTRIM_FREQ_24MHZ (2 << SFR_UTMICKTRIM_FREQ_SHIFT) /* 24 MHz reference clock */
# define SFR_UTMICKTRIM_FREQ_48MHZ (3 << SFR_UTMICKTRIM_FREQ_SHIFT) /* 48 MHz reference clock */
/* EBI Configuration Register */
#define SFR_EBICFG_DRIVE_LOW (0) /* LOW Low drive level */
#define SFR_EBICFG_DRIVE_MEDIUM (2) /* MEDIUM Medium drive level */
#define SFR_EBICFG_DRIVE_HIGH (3) /* HIGH High drive level */
#define SFR_EBICFG_PULL_UP (0) /* Pull-up */
#define SFR_EBICFG_PULL_NONE (1) /* No Pull */
#define SFR_EBICFG_PULL_DOWN (3) /* Pull-down */
#define SFR_EBICFG_DRIVE0_SHIFT (0) /* Bits 0-1: EBI Pins Drive Level */
#define SFR_EBICFG_DRIVE0_MASK (3 << SFR_EBICFG_DRIVE0_SHIFT)
# define SFR_EBICFG_DRIVE0(n) ((n) << SFR_EBICFG_DRIVE0_SHIFT)
#define SFR_EBICFG_PULL0_SHIFT (2) /* Bits 2-3: EBI Pins Pull Value */
#define SFR_EBICFG_PULL0_MASK (3 << SFR_EBICFG_PULL0_SHIFT)
# define SFR_EBICFG_PULL0(n) ((n) << SFR_EBICFG_PULL0_SHIFT)
#define SFR_EBICFG_SCH0 (1 << 4) /* Bit 4: EBI Pins Schmitt Trigger */
#define SFR_EBICFG_DRIVE1_SHIFT (8) /* Bits 8-9: EBI Pins Drive Level */
#define SFR_EBICFG_DRIVE1_MASK (3 << SFR_EBICFG_DRIVE1_SHIFT)
# define SFR_EBICFG_DRIVE1(n) ((n) << SFR_EBICFG_DRIVE1_SHIFT)
#define SFR_EBICFG_PULL1_SHIFT (10) /* Bits 10-11: EBI Pins Pull Value */
#define SFR_EBICFG_PULL1_MASK (3 << SFR_EBICFG_PULL1_SHIFT)
# define SFR_EBICFG_PULL1(n) ((n) << SFR_EBICFG_PULL1_SHIFT)
#define SFR_EBICFG_SCH1 (1 << 12) /* Bit 12: EBI Pins Schmitt Trigger */
#define SFR_EBICFG_BMS (1 << 16) /* Bit 16: BMS Sampled Value (Read Only) */
#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_SFR_H */
arch/arm/src/sama5/chip/sama5d3x_memorymap.h
+5 -5
View File
@@ -87,7 +87,7 @@
#define SAM_UDPHSRAM_PSECTION 0x00500000 /* 0x00500000-0x005fffff: UDPH SRAM */ #define SAM_UDPHSRAM_PSECTION 0x00500000 /* 0x00500000-0x005fffff: UDPH SRAM */
#define SAM_UHPOHCI_PSECTION 0x00600000 /* 0x00600000-0x006fffff: UHP OHCI */ #define SAM_UHPOHCI_PSECTION 0x00600000 /* 0x00600000-0x006fffff: UHP OHCI */
#define SAM_UHPEHCI_PSECTION 0x00700000 /* 0x00700000-0x007fffff: UHP EHCI */ #define SAM_UHPEHCI_PSECTION 0x00700000 /* 0x00700000-0x007fffff: UHP EHCI */
#define SAM_AXIMATRIX_PSECTION 0x00800000 /* 0x00800000-0x008fffff: AXI Matr */ #define SAM_AXIMX_PSECTION 0x00800000 /* 0x00800000-0x008fffff: AXI Matr */
#define SAM_DAP_PSECTION 0x00900000 /* 0x00900000-0x009fffff: DAP */ #define SAM_DAP_PSECTION 0x00900000 /* 0x00900000-0x009fffff: DAP */
/* 0x000a0000-0x0fffffff: Undefined */ /* 0x000a0000-0x0fffffff: Undefined */
/* SAMA5 Internal Peripheral Offsets */ /* SAMA5 Internal Peripheral Offsets */
@@ -179,7 +179,7 @@
#define SAM_UDPHSRAM_SIZE (1*1024*1024) /* 0x00500000-0x005fffff: UDPH SRAM */ #define SAM_UDPHSRAM_SIZE (1*1024*1024) /* 0x00500000-0x005fffff: UDPH SRAM */
#define SAM_UHPOHCI_SIZE (1*1024*1024) /* 0x00600000-0x006fffff: UHP OHCI */ #define SAM_UHPOHCI_SIZE (1*1024*1024) /* 0x00600000-0x006fffff: UHP OHCI */
#define SAM_UHPEHCI_SIZE (1*1024*1024) /* 0x00700000-0x007fffff: UHP EHCI */ #define SAM_UHPEHCI_SIZE (1*1024*1024) /* 0x00700000-0x007fffff: UHP EHCI */
#define SAM_AXIMATRIX_SIZE (1*1024*1024) /* 0x00800000-0x008fffff: AXI Matr */ #define SAM_AXIMX_SIZE (4) /* 0x00800000-0x008fffff: AXI Matr */
#define SAM_DAP_SIZE (1*1024*1024) /* 0x00900000-0x009fffff: DAP */ #define SAM_DAP_SIZE (1*1024*1024) /* 0x00900000-0x009fffff: DAP */
#define SAM_NFCCR_SIZE (256*1024*1024) /* 0x70000000-0x7fffffff: NFC Command Registers */ #define SAM_NFCCR_SIZE (256*1024*1024) /* 0x70000000-0x7fffffff: NFC Command Registers */
/* 0xf0000000-0xffffffff: Internal Peripherals */ /* 0xf0000000-0xffffffff: Internal Peripherals */
@@ -207,7 +207,7 @@
#define SAM_UDPHSRAM_NSECTIONS _NSECTIONS(SAM_UDPHSRAM_SIZE) #define SAM_UDPHSRAM_NSECTIONS _NSECTIONS(SAM_UDPHSRAM_SIZE)
#define SAM_UHPOHCI_NSECTIONS _NSECTIONS(SAM_UHPOHCI_SIZE) #define SAM_UHPOHCI_NSECTIONS _NSECTIONS(SAM_UHPOHCI_SIZE)
#define SAM_UHPEHCI_NSECTIONS _NSECTIONS(SAM_UHPEHCI_SIZE) #define SAM_UHPEHCI_NSECTIONS _NSECTIONS(SAM_UHPEHCI_SIZE)
#define SAM_AXIMATRIX_NSECTIONS _NSECTIONS(SAM_AXIMATRIX_SIZE) #define SAM_AXIMX_NSECTIONS _NSECTIONS(SAM_AXIMX_SIZE)
#define SAM_DAP_NSECTIONS _NSECTIONS(SAM_DAP_SIZE) #define SAM_DAP_NSECTIONS _NSECTIONS(SAM_DAP_SIZE)
#define SAM_EBICS0_NSECTIONS _NSECTIONS(CONFIG_SAMA5_EBISC0_SIZE) #define SAM_EBICS0_NSECTIONS _NSECTIONS(CONFIG_SAMA5_EBISC0_SIZE)
@@ -231,7 +231,7 @@
#define SAM_UDPHSRAM_MMUFLAGS MMU_IOFLAGS #define SAM_UDPHSRAM_MMUFLAGS MMU_IOFLAGS
#define SAM_UHPOHCI_MMUFLAGS MMU_IOFLAGS #define SAM_UHPOHCI_MMUFLAGS MMU_IOFLAGS
#define SAM_UHPEHCI_MMUFLAGS MMU_IOFLAGS #define SAM_UHPEHCI_MMUFLAGS MMU_IOFLAGS
#define SAM_AXIMATRIX_MMUFLAGS MMU_IOFLAGS #define SAM_AXIMX_MMUFLAGS MMU_IOFLAGS
#define SAM_DAP_MMUFLAGS MMU_IOFLAGS #define SAM_DAP_MMUFLAGS MMU_IOFLAGS
#define SAM_EBICS0_MMUFLAGS MMU_MEMFLAGS #define SAM_EBICS0_MMUFLAGS MMU_MEMFLAGS
@@ -273,7 +273,7 @@
# define SAM_UDPHSRAM_VSECTION 0x00500000 /* 0x00500000-0x005fffff: UDPH SRAM */ # define SAM_UDPHSRAM_VSECTION 0x00500000 /* 0x00500000-0x005fffff: UDPH SRAM */
# define SAM_UHPOHCI_VSECTION 0x00600000 /* 0x00600000-0x006fffff: UHP OHCI */ # define SAM_UHPOHCI_VSECTION 0x00600000 /* 0x00600000-0x006fffff: UHP OHCI */
# define SAM_UHPEHCI_VSECTION 0x00700000 /* 0x00700000-0x007fffff: UHP EHCI */ # define SAM_UHPEHCI_VSECTION 0x00700000 /* 0x00700000-0x007fffff: UHP EHCI */
# define SAM_AXIMATRIX_VSECTION 0x00800000 /* 0x00800000-0x008fffff: AXI Matr */ # define SAM_AXIMX_VSECTION 0x00800000 /* 0x00800000-0x008fffff: AXI Matrix */
# define SAM_DAP_VSECTION 0x00900000 /* 0x00900000-0x009fffff: DAP */ # define SAM_DAP_VSECTION 0x00900000 /* 0x00900000-0x009fffff: DAP */
#define SAM_EBICS0_VSECTION 0x10000000 /* 0x10000000-0x1fffffff: EBI Chip select 0 */ #define SAM_EBICS0_VSECTION 0x10000000 /* 0x10000000-0x1fffffff: EBI Chip select 0 */
#define SAM_DDRCS_VSECTION 0x20000000 /* 0x20000000-0x3fffffff: EBI DDRCS */ #define SAM_DDRCS_VSECTION 0x20000000 /* 0x20000000-0x3fffffff: EBI DDRCS */
arch/arm/src/sama5/sam_boot.c
+143 -55
View File
@@ -1,4 +1,4 @@
/************************************************************************************ /****************************************************************************
* arch/arm/src/sama5/sam_boot.c * arch/arm/src/sama5/sam_boot.c
* *
* Copyright (C) 2013 Gregory Nutt. All rights reserved. * Copyright (C) 2013 Gregory Nutt. All rights reserved.
@@ -31,11 +31,11 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE. * POSSIBILITY OF SUCH DAMAGE.
* *
************************************************************************************/ ****************************************************************************/
/************************************************************************************ /****************************************************************************
* Included Files * Included Files
************************************************************************************/ ****************************************************************************/
#include <nuttx/config.h> #include <nuttx/config.h>
#include <stdint.h> #include <stdint.h>
@@ -53,16 +53,17 @@
#include "up_internal.h" #include "up_internal.h"
#include "up_arch.h" #include "up_arch.h"
#include "chip/sam_wdt.h"
#include "sam_clockconfig.h" #include "sam_clockconfig.h"
#include "sam_lowputc.h" #include "sam_lowputc.h"
/************************************************************************************ /****************************************************************************
* Private Types * Private Types
************************************************************************************/ ****************************************************************************/
/************************************************************************************ /****************************************************************************
* Private Types * Private Types
************************************************************************************/ ****************************************************************************/
struct section_mapping_s struct section_mapping_s
{ {
@@ -72,19 +73,19 @@ struct section_mapping_s
uint32_t nsections; /* Number of mappings in the region */ uint32_t nsections; /* Number of mappings in the region */
}; };
/************************************************************************************ /****************************************************************************
* Public Variables * Public Variables
************************************************************************************/ ****************************************************************************/
extern uint32_t _vector_start; /* Beginning of vector block */ extern uint32_t _vector_start; /* Beginning of vector block */
extern uint32_t _vector_end; /* End+1 of vector block */ extern uint32_t _vector_end; /* End+1 of vector block */
/************************************************************************************ /****************************************************************************
* Private Variables * Private Variables
************************************************************************************/ ****************************************************************************/
/* This table describes how to map a set of 1Mb pages to space the physical address /* This table describes how to map a set of 1Mb pages to space the physical
* space of the SAMA5. * address space of the SAMA5.
*/ */
#ifndef CONFIG_ARCH_ROMPGTABLE #ifndef CONFIG_ARCH_ROMPGTABLE
@@ -112,8 +113,8 @@ static const struct section_mapping_s section_mapping[] =
SAM_UHPOHCI_MMUFLAGS, SAM_UHPOHCI_NSECTIONS}, SAM_UHPOHCI_MMUFLAGS, SAM_UHPOHCI_NSECTIONS},
{ SAM_UHPEHCI_PSECTION, SAM_UHPEHCI_VSECTION, { SAM_UHPEHCI_PSECTION, SAM_UHPEHCI_VSECTION,
SAM_UHPEHCI_MMUFLAGS, SAM_UHPEHCI_NSECTIONS}, SAM_UHPEHCI_MMUFLAGS, SAM_UHPEHCI_NSECTIONS},
{ SAM_AXIMATRIX_PSECTION, SAM_AXIMATRIX_VSECTION, { SAM_AXIMX_PSECTION, SAM_AXIMX_VSECTION,
SAM_AXIMATRIX_MMUFLAGS, SAM_AXIMATRIX_NSECTIONS}, SAM_AXIMX_MMUFLAGS, SAM_AXIMX_NSECTIONS},
{ SAM_DAP_PSECTION, SAM_DAP_VSECTION, { SAM_DAP_PSECTION, SAM_DAP_VSECTION,
SAM_DAP_MMUFLAGS, SAM_DAP_NSECTIONS}, SAM_DAP_MMUFLAGS, SAM_DAP_NSECTIONS},
@@ -156,13 +157,13 @@ static const struct section_mapping_s section_mapping[] =
#define NMAPPINGS (sizeof(section_mapping) / sizeof(struct section_mapping_s)) #define NMAPPINGS (sizeof(section_mapping) / sizeof(struct section_mapping_s))
#endif #endif
/************************************************************************************ /****************************************************************************
* Private Functions * Private Functions
************************************************************************************/ ****************************************************************************/
/************************************************************************************ /****************************************************************************
* Name: sam_setlevel1entry * Name: sam_setlevel1entry
************************************************************************************/ ****************************************************************************/
#ifndef CONFIG_ARCH_ROMPGTABLE #ifndef CONFIG_ARCH_ROMPGTABLE
static inline void sam_setlevel1entry(uint32_t paddr, uint32_t vaddr, static inline void sam_setlevel1entry(uint32_t paddr, uint32_t vaddr,
@@ -177,12 +178,13 @@ static inline void sam_setlevel1entry(uint32_t paddr, uint32_t vaddr,
} }
#endif #endif
/************************************************************************************ /****************************************************************************
* Name: sam_setlevel2coarseentry * Name: sam_setlevel2coarseentry
************************************************************************************/ ****************************************************************************/
static inline void sam_setlevel2coarseentry(uint32_t ctabvaddr, uint32_t paddr, static inline void
uint32_t vaddr, uint32_t mmuflags) sam_setlevel2coarseentry(uint32_t ctabvaddr, uint32_t paddr, uint32_t vaddr,
uint32_t mmuflags)
{ {
uint32_t *ctable = (uint32_t*)ctabvaddr; uint32_t *ctable = (uint32_t*)ctabvaddr;
uint32_t index; uint32_t index;
@@ -199,9 +201,9 @@ static inline void sam_setlevel2coarseentry(uint32_t ctabvaddr, uint32_t paddr,
ctable[index] = (paddr | mmuflags); ctable[index] = (paddr | mmuflags);
} }
/************************************************************************************ /****************************************************************************
* Name: sam_setupmappings * Name: sam_setupmappings
************************************************************************************/ ****************************************************************************/
#ifndef CONFIG_ARCH_ROMPGTABLE #ifndef CONFIG_ARCH_ROMPGTABLE
static void sam_setupmappings(void) static void sam_setupmappings(void)
@@ -224,15 +226,16 @@ static void sam_setupmappings(void)
} }
#endif #endif
/************************************************************************************ /****************************************************************************
* Name: sam_vectorpermissions * Name: sam_vectorpermissions
* *
* Description: * Description:
* Set permissions on the vector mapping. * Set permissions on the vector mapping.
* *
************************************************************************************/ ****************************************************************************/
#if !defined(CONFIG_ARCH_ROMPGTABLE) && defined(CONFIG_ARCH_LOWVECTORS) && defined(CONFIG_PAGING) #if !defined(CONFIG_ARCH_ROMPGTABLE) && defined(CONFIG_ARCH_LOWVECTORS) && \
defined(CONFIG_PAGING)
static void sam_vectorpermissions(uint32_t mmuflags) static void sam_vectorpermissions(uint32_t mmuflags)
{ {
/* The PTE for the beginning of ISRAM is at the base of the L2 page table */ /* The PTE for the beginning of ISRAM is at the base of the L2 page table */
@@ -262,18 +265,18 @@ static void sam_vectorpermissions(uint32_t mmuflags)
} }
#endif #endif
/************************************************************************************ /****************************************************************************
* Name: sam_vectormapping * Name: sam_vectormapping
* *
* Description: * Description:
* Setup a special mapping for the interrupt vectors when (1) the interrupt * Setup a special mapping for the interrupt vectors when (1) the
* vectors are not positioned in ROM, and when (2) the interrupt vectors are * interrupt vectors are not positioned in ROM, and when (2) the interrupt
* located at the high address, 0xffff0000. When the interrupt vectors are located * vectors are located at the high address, 0xffff0000. When the
* in ROM, we just have to assume that they were set up correctly; When vectors * interrupt vectors are located in ROM, we just have to assume that they
* are located in low memory, 0x00000000, the shadow memory region will be mapped * were set up correctly; When vectors are located in low memory,
* to support them. * 0x00000000, the mapping for the ROM memory region will be suppressed.
* *
************************************************************************************/ ****************************************************************************/
#if !defined(CONFIG_ARCH_ROMPGTABLE) && !defined(CONFIG_ARCH_LOWVECTORS) #if !defined(CONFIG_ARCH_ROMPGTABLE) && !defined(CONFIG_ARCH_LOWVECTORS)
static void sam_vectormapping(void) static void sam_vectormapping(void)
@@ -282,9 +285,10 @@ static void sam_vectormapping(void)
uint32_t vector_vaddr = SAM_VECTOR_VADDR; uint32_t vector_vaddr = SAM_VECTOR_VADDR;
uint32_t end_paddr = vector_paddr + VECTOR_TABLE_SIZE; uint32_t end_paddr = vector_paddr + VECTOR_TABLE_SIZE;
/* We want to keep our interrupt vectors and interrupt-related logic in zero-wait /* We want to keep our interrupt vectors and interrupt-related logic in
* state internal RAM (IRAM). The DM320 has 16Kb of IRAM positioned at physical * zero-wait state internal SRAM (ISRAM). The SAMA5 has 128Kb of ISRAM
* address 0x0000:0000; we need to map this to 0xffff:0000. * positioned at physical address 0x0300:0000; we need to map this to
* 0xffff:0000.
*/ */
while (vector_paddr < end_paddr) while (vector_paddr < end_paddr)
@@ -302,13 +306,13 @@ static void sam_vectormapping(void)
} }
#endif #endif
/************************************************************************************ /****************************************************************************
* Name: sam_copyvectorblock * Name: sam_copyvectorblock
* *
* Description: * Description:
* Copy the interrupt block to its final destination. * Copy the interrupt block to its final destination.
* *
************************************************************************************/ ****************************************************************************/
static void sam_copyvectorblock(void) static void sam_copyvectorblock(void)
{ {
@@ -320,7 +324,8 @@ static void sam_copyvectorblock(void)
* read only, then temparily mark the mapping write-able (non-buffered). * read only, then temparily mark the mapping write-able (non-buffered).
*/ */
#if !defined(CONFIG_ARCH_ROMPGTABLE) && defined(CONFIG_ARCH_LOWVECTORS) && defined(CONFIG_PAGING) #if !defined(CONFIG_ARCH_ROMPGTABLE) && defined(CONFIG_ARCH_LOWVECTORS) && \
defined(CONFIG_PAGING)
sam_vectorpermissions(MMU_L2_VECTRWFLAGS); sam_vectorpermissions(MMU_L2_VECTRWFLAGS);
#endif #endif
@@ -329,7 +334,8 @@ static void sam_copyvectorblock(void)
* *
* SAM_VECTOR_PADDR - Unmapped, physical address of vector table in SRAM * SAM_VECTOR_PADDR - Unmapped, physical address of vector table in SRAM
* SAM_VECTOR_VSRAM - Virtual address of vector table in SRAM * SAM_VECTOR_VSRAM - Virtual address of vector table in SRAM
* SAM_VECTOR_VADDR - Virtual address of vector table (0x00000000 or 0xffff0000) * SAM_VECTOR_VADDR - Virtual address of vector table (0x00000000 or
* 0xffff0000)
*/ */
src = (uint32_t*)&_vector_start; src = (uint32_t*)&_vector_start;
@@ -343,34 +349,110 @@ static void sam_copyvectorblock(void)
/* Make the vectors read-only, cacheable again */ /* Make the vectors read-only, cacheable again */
#if !defined(CONFIG_ARCH_ROMPGTABLE) && defined(CONFIG_ARCH_LOWVECTORS) && defined(CONFIG_PAGING) #if !defined(CONFIG_ARCH_ROMPGTABLE) && defined(CONFIG_ARCH_LOWVECTORS) && \
defined(CONFIG_PAGING)
sam_vectorpermissions(MMU_L2_VECTROFLAGS); sam_vectorpermissions(MMU_L2_VECTROFLAGS);
#endif #endif
} }
/************************************************************************************ /****************************************************************************
* Public Functions * Name: sam_wdtdisable
************************************************************************************/ *
* Description:
* Disable the watchdog timer
*
****************************************************************************/
/************************************************************************************ static inline void sam_wdtdisable(void)
{
putreg32(WDT_MR_WDDIS, SAM_WDT_MR);
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_boot * Name: up_boot
* *
* Description: * Description:
* Complete boot operations started in arm_head.S * Complete boot operations started in arm_head.S
* *
************************************************************************************/ * Boot Sequence
*
* This logic may be executing in ISRAM or in external mmemory: CS0, DDR,
* CS1, CS2, or CS3. It may be executing in CS0 or ISRAM through the
* action of the SAMA5 "first level bootloader;" it might be executing in
* CS1-3 through the action of some second level bootloader that provides
* configuration for those memories.
*
* The system always boots from the ROM memory at address 0x0000:0000,
* starting the internal first level bootloader. That bootloader can be
* configured to work in different ways using the BMS pin and the contents
* of the Boot Sequence Configuration Register (BSC_CR).
*
* If the BMS_BIT is read "1", then the first level bootloader will
* support execution of code in the memory connected to CS0 on the EBI
* interface (presumably NOR flash). The following sequence is performed
* by the first level bootloader if BMS_BIT is "1":
*
* - The main clock is the on-chip 12 MHz RC oscillator,
* - The Static Memory Controller is configured with timing allowing
* code execution in CS0 external memory at 12 MHz
* - AXI matrix is configured to remap EBI CS0 address at 0x0
* - 0x0000:0000 is loaded in the Program Counter register
*
* The user software in the external memory must perform the next
* operation in order to complete the clocks and SMC timings configuration
* to run at a higher clock frequency:
*
* - Enable the 32768 Hz oscillator if best accuracy is needed
* - Reprogram the SMC setup, cycle, hold, mode timing registers for EBI
* CS0, to adapt them to the new clock.
* - Program the PMC (Main Oscillator Enable or Bypass mode)
* - Program and Start the PLL
* - Switch the system clock to the new value
*
* If the BMS_BIT is read "0", then the first level bootloader will
* perform:
*
* - Basic chip initialization: XTal or external clock frequency
* detection:
*
* a. Stack Setup for ARM supervisor mode
* b. Main Oscillator Detection: The bootloader attempts to use an
* external crystal. If this is not successful, then the 12 MHz
* Fast RC internal oscillator is used as the main osciallator.
* c. Main Clock Selection: The Master Clock source is switched from
* to the main oscillator without prescaler. PCK and MCK are now
* the Main Clock.
* d. PLLA Initialization: PLLA is configured to get a PCK at 96 MHz
* and an MCK at 48 MHz. If an external clock or crystal frequency
* running at 12 MHz is found, then the PLLA is configured to allow
* USB communication.
*
* - Attempt to retrieve a valid code from external non-volatile
* memories (NVM): SPI0 CS0 Flash Boot, SD Card Boot, NAND Flash Boot,
* SPI0 CS1 Flash Boot, or TWI EEPROM Boot. Different heuristics are
* used with each media type. If a valid image is found, it is copied
* to internal SRAM and started.
*
* - In case no valid application has been found on any NVM, the SAM-BA
* Monitor is started.
*
****************************************************************************/
void up_boot(void) void up_boot(void)
{ {
/* __start provided the basic MMU mappings for SRAM. Now provide mappings for all /* __start provided the basic MMU mappings for SRAM. Now provide mappings
* IO regions (Including the vector region). * for all IO regions (Including the vector region).
*/ */
#ifndef CONFIG_ARCH_ROMPGTABLE #ifndef CONFIG_ARCH_ROMPGTABLE
sam_setupmappings(); sam_setupmappings();
/* Provide a special mapping for the IRAM interrupt vector positioned in high /* Provide a special mapping for the IRAM interrupt vector positioned in
* memory. * high memory.
*/ */
#ifndef CONFIG_ARCH_LOWVECTORS #ifndef CONFIG_ARCH_LOWVECTORS
@@ -384,6 +466,10 @@ void up_boot(void)
sam_copyvectorblock(); sam_copyvectorblock();
/* Disable the watchdog timer */
sam_wdtdisable();
/* Initialize clocking to settings provided by board-specific logic */ /* Initialize clocking to settings provided by board-specific logic */
sam_clockconfig(); sam_clockconfig();
@@ -398,7 +484,9 @@ void up_boot(void)
sam_lowsetup(); sam_lowsetup();
/* Perform early serial initialization if we are going to use the serial driver */ /* Perform early serial initialization if we are going to use the serial
* driver.
*/
#ifdef USE_EARLYSERIALINIT #ifdef USE_EARLYSERIALINIT
sam_earlyserialinit(); sam_earlyserialinit();
arch/arm/src/sama5/sam_clockconfig.c
+117 -21
View File
@@ -50,13 +50,16 @@
#include "sam_clockconfig.h" #include "sam_clockconfig.h"
#include "chip/sam_pmc.h" #include "chip/sam_pmc.h"
#include "chip/sam_wdt.h" #include "chip/sam_sfr.h"
#include "chip/sam_matrix.h"
/**************************************************************************** /****************************************************************************
* Pre-processor Definitions * Pre-processor Definitions
****************************************************************************/ ****************************************************************************/
/****************************************************************************
* Private Types
****************************************************************************/
/**************************************************************************** /****************************************************************************
* Public Data * Public Data
****************************************************************************/ ****************************************************************************/
@@ -69,19 +72,6 @@
* Private Functions * Private Functions
****************************************************************************/ ****************************************************************************/
/****************************************************************************
* Name: sam_wdtsetup
*
* Description:
* Disable the watchdog timer
*
****************************************************************************/
static inline void sam_wdtsetup(void)
{
putreg32(WDT_MR_WDDIS, SAM_WDT_MR);
}
/**************************************************************************** /****************************************************************************
* Name: sam_pmcwait * Name: sam_pmcwait
* *
@@ -364,22 +354,125 @@ static inline void sam_upllsetup(void)
* performs other low-level chip initialization of the chip including master * performs other low-level chip initialization of the chip including master
* clock, IRQ & watchdog configuration. * clock, IRQ & watchdog configuration.
* *
* Boot Sequence
*
* This logic may be executing in ISRAM or in external mmemory: CS0, DDR,
* CS1, CS2, or CS3. It may be executing in CS0 or ISRAM through the
* action of the SAMA5 "first level bootloader;" it might be executing in
* CS1-3 through the action of some second level bootloader that provides
* configuration for those memories.
*
* The system always boots from the ROM memory at address 0x0000:0000,
* starting the internal first level bootloader. That bootloader can be
* configured to work in different ways using the BMS pin and the contents
* of the Boot Sequence Configuration Register (BSC_CR).
*
* If the BMS_BIT is read "1", then the first level bootloader will
* support execution of code in the memory connected to CS0 on the EBI
* interface (presumably NOR flash). The following sequence is performed
* by the first level bootloader if BMS_BIT is "1":
*
* - The main clock is the on-chip 12 MHz RC oscillator,
* - The Static Memory Controller is configured with timing allowing
* code execution in CS0 external memory at 12 MHz
* - AXI matrix is configured to remap EBI CS0 address at 0x0
* - 0x0000:0000 is loaded in the Program Counter register
*
* The user software in the external memory must perform the next
* operation in order to complete the clocks and SMC timings configuration
* to run at a higher clock frequency:
*
* - Enable the 32768 Hz oscillator if best accuracy is needed
* - Reprogram the SMC setup, cycle, hold, mode timing registers for EBI
* CS0, to adapt them to the new clock.
* - Program the PMC (Main Oscillator Enable or Bypass mode)
* - Program and Start the PLL
* - Switch the system clock to the new value
*
* If the BMS_BIT is read "0", then the first level bootloader will
* perform:
*
* - Basic chip initialization: XTal or external clock frequency
* detection:
*
* a. Stack Setup for ARM supervisor mode
* b. Main Oscillator Detection: The bootloader attempts to use an
* external crystal. If this is not successful, then the 12 MHz
* Fast RC internal oscillator is used as the main osciallator.
* c. Main Clock Selection: The Master Clock source is switched from
* to the main oscillator without prescaler. PCK and MCK are now
* the Main Clock.
* d. PLLA Initialization: PLLA is configured to get a PCK at 96 MHz
* and an MCK at 48 MHz. If an external clock or crystal frequency
* running at 12 MHz is found, then the PLLA is configured to allow
* USB communication.
*
* - Attempt to retrieve a valid code from external non-volatile
* memories (NVM): SPI0 CS0 Flash Boot, SD Card Boot, NAND Flash Boot,
* SPI0 CS1 Flash Boot, or TWI EEPROM Boot. Different heuristics are
* used with each media type. If a valid image is found, it is copied
* to internal SRAM and started.
*
* - In case no valid application has been found on any NVM, the SAM-BA
* Monitor is started.
*
****************************************************************************/ ****************************************************************************/
void sam_clockconfig(void) void sam_clockconfig(void)
{ {
/* Configure the watchdog timer */ #ifdef CONFIG_SAMA5_BOOT_CS0FLASH
bool config = false;
#endif
sam_wdtsetup(); /* Initialize clocking.
*
* Check first: Are we running in CS0?
*/
/* Initialize clocking */ #ifdef CONFIG_SAMA5_BOOT_CS0FLASH
/* Yes... did we get here via the first level bootloader? */
if ((getreg32(SAM_SFR_EBICFG) & SFR_EBICFG_BMS) != 0)
{
/* Yes.. Perform the following operations in order to complete the
* clocks and SMC timings configuration to run at a higher clock
* frequency:
*
* - Enable the 32768 Hz oscillator if best accuracy is needed
* - Reprogram the SMC setup, cycle, hold, mode timing registers for EBI
* CS0, to adapt them to the new clock.
* - Program the PMC (Main Oscillator Enable or Bypass mode)
* - Program and Start the PLL
* - Switch the system clock to the new value
*/
#error Missing logic
config = true;
}
#endif
/* If we are running from DDRAM or CS1-3, then we will not modify the
* clock configuration. In these cases, we have to assume that some
* secondary bootloader started us here and that the bootloader has
* configured clocking appropriately.
*
* If we are running in CS0, then we may have been started by either
* the first or second level bootloader. In either case, we need to
* update the PLLA settings in order to get a higher performance
* clock.
*/
#ifdef CONFIG_SAMA5_BOOT_CS0FLASH
if (config)
#if define(CONFIG_SAMA5_BOOT_SRAM) || defined(CONFIG_SAMA5_BOOT_CS0FLASH)
{
/* Enable main oscillator (if it has not already been selected) */ /* Enable main oscillator (if it has not already been selected) */
sam_enablemosc(); sam_enablemosc();
/* Select the main oscillator as the input clock for processor clock (PCK) /* Select the main oscillator as the input clock for processor clock
* and the main clock (MCK). The PCK and MCK differ only by the MDIV * (PCK) and the main clock (MCK). The PCK and MCK differ only by the
* divisor that permits the MCK to run at a lower rate. * MDIV divisor that permits the MCK to run at a lower rate.
*/ */
sam_selectmosc(); sam_selectmosc();
@@ -407,4 +500,7 @@ void sam_clockconfig(void)
/* Setup UTMI for USB */ /* Setup UTMI for USB */
sam_upllsetup(); sam_upllsetup();
}
#endif /* CONFIG_SAMA5_BOOT_SRAM || CONFIG_SAMA5_BOOT_CS0FLASH */
#endif /* CONFIG_SAMA5_BOOT_CS0FLASH */
} }
arch/arm/src/sama5/sam_irq.c
+16 -1
View File
@@ -51,10 +51,13 @@
#include "up_internal.h" #include "up_internal.h"
#ifdef CONFIG_PIO_IRQ #ifdef CONFIG_PIO_IRQ
# include "sam_pio.h" # include "sam_gpio.h"
#endif #endif
#include "chip/sam_aic.h" #include "chip/sam_aic.h"
#include "chip/sam_matrix.h"
#include "chip/sam_aximx.h"
#include "sam_irq.h" #include "sam_irq.h"
/**************************************************************************** /****************************************************************************
@@ -280,6 +283,18 @@ void up_irqinitialize(void)
putreg32(AIC_WPMR_WPKEY | AIC_WPMR_WPEN, SAM_AIC_WPMR); putreg32(AIC_WPMR_WPKEY | AIC_WPMR_WPEN, SAM_AIC_WPMR);
/* Set remap state 0:
*
* Boot state: ROM is seen at address 0x00000000
* Remap State 0: SRAM is seen at address 0x00000000 (through AHB slave
* interface) instead of ROM.
* Remap State 1: HEBI is seen at address 0x00000000 (through AHB slave
* interface) instead of ROM for external boot.
*/
putreg32(MATRIX_MRCR_RCB0, SAM_MATRIX_MRCR); /* Enable remap */
putreg32(AXIMX_REMAP_REMAP0, SAM_AXIMX_REMAP); /* Remap SRAM */
/* currents_regs is non-NULL only while processing an interrupt */ /* currents_regs is non-NULL only while processing an interrupt */
current_regs = NULL; current_regs = NULL;