From 58c92be39c72e2dff41848e821936cd4fd744a75 Mon Sep 17 00:00:00 2001 From: Anthony Merlino Date: Sun, 11 Apr 2021 15:37:17 -0400 Subject: [PATCH] stm32 timers: Make some register operations more readable. --- arch/arm/src/stm32/hardware/stm32_tim_v1v2.h | 2 ++ arch/arm/src/stm32/hardware/stm32_tim_v3.h | 2 ++ arch/arm/src/stm32/stm32_capture.c | 6 ++--- arch/arm/src/stm32/stm32_tickless.c | 5 ++-- arch/arm/src/stm32/stm32_tim.c | 7 +++--- arch/arm/src/stm32f0l0g0/hardware/stm32_tim.h | 2 ++ arch/arm/src/stm32f0l0g0/stm32_tim.c | 7 +++--- .../src/stm32f7/hardware/stm32f72xx73xx_tim.h | 2 ++ .../src/stm32f7/hardware/stm32f74xx75xx_tim.h | 2 ++ .../src/stm32f7/hardware/stm32f76xx77xx_tim.h | 2 ++ arch/arm/src/stm32f7/stm32_capture.c | 6 ++--- arch/arm/src/stm32f7/stm32_tickless.c | 23 ++++++++++--------- arch/arm/src/stm32f7/stm32_tim.c | 9 ++++---- arch/arm/src/stm32l4/hardware/stm32l4_tim.h | 2 ++ arch/arm/src/stm32l4/stm32l4_adc.c | 5 ++-- arch/arm/src/stm32l4/stm32l4_tim.c | 7 +++--- arch/arm/src/stm32l5/hardware/stm32l5_tim.h | 2 ++ arch/arm/src/stm32l5/stm32l5_tim.c | 7 +++--- 18 files changed, 61 insertions(+), 37 deletions(-) diff --git a/arch/arm/src/stm32/hardware/stm32_tim_v1v2.h b/arch/arm/src/stm32/hardware/stm32_tim_v1v2.h index dabccee4119..138cd37fefd 100644 --- a/arch/arm/src/stm32/hardware/stm32_tim_v1v2.h +++ b/arch/arm/src/stm32/hardware/stm32_tim_v1v2.h @@ -826,6 +826,7 @@ # define ATIM_CCER_CC6E (1 << 20) /* Bit 20: Capture/Compare 6 output enable */ # define ATIM_CCER_CC6P (1 << 21) /* Bit 21: Capture/Compare 6 output Polarity */ #endif +#define ATIM_CCER_CCXBASE(ch) (ch << 2) /* Each channel uses 4-bits */ /* 16-bit counter register */ @@ -1222,6 +1223,7 @@ * no CC4N output, so it does not make sense! */ #endif +#define GTIM_CCER_CCXBASE(ch) (ch << 2) /* Each channel uses 4-bits */ /* 16-bit counter register */ diff --git a/arch/arm/src/stm32/hardware/stm32_tim_v3.h b/arch/arm/src/stm32/hardware/stm32_tim_v3.h index 61a77c516c7..f5e546b771c 100644 --- a/arch/arm/src/stm32/hardware/stm32_tim_v3.h +++ b/arch/arm/src/stm32/hardware/stm32_tim_v3.h @@ -769,6 +769,7 @@ #define ATIM_CCER_CC5P (1 << 17) /* Bit 17: Capture/Compare 5 Output Polarity */ #define ATIM_CCER_CC6E (1 << 20) /* Bit 20: Capture/Compare 6 Output Enable */ #define ATIM_CCER_CC6P (1 << 21) /* Bit 21: Capture/Compare 6 Output Polarity */ +#define ATIM_CCER_CCXBASE(ch) (ch << 2) /* Each channel uses 4-bits */ /* ATIM Counter (CNT) */ @@ -1236,6 +1237,7 @@ #define GTIM_CCER_CC4E (1 << 12) /* Bit 12: Capture/Compare 4 Output Enable */ #define GTIM_CCER_CC4P (1 << 13) /* Bit 13: Capture/Compare 4 Output Polarity */ #define GTIM_CCER_CC4NP (1 << 15) /* Bit 15: Capture/Compare 4 Complementary Output Polarity */ +#define GTIM_CCER_CCXBASE(ch) (ch << 2) /* Each channel uses 4-bits */ /* GTIM Counter (CNT) */ diff --git a/arch/arm/src/stm32/stm32_capture.c b/arch/arm/src/stm32/stm32_capture.c index 3ff5419230a..a8d4a3ea1e9 100644 --- a/arch/arm/src/stm32/stm32_capture.c +++ b/arch/arm/src/stm32/stm32_capture.c @@ -963,9 +963,9 @@ static int stm32_cap_setchannel(FAR struct stm32_cap_dev_s *dev, /* Shift all CCER bits to corresponding channel */ mask = (GTIM_CCER_CC1E | GTIM_CCER_CC1P | GTIM_CCER_CC1NP); - mask <<= (channel << 2); - regval <<= (channel << 2); - ccer_en_bit <<= (channel << 2); + mask <<= GTIM_CCER_CCXBASE(channel); + regval <<= GTIM_CCER_CCXBASE(channel); + ccer_en_bit <<= GTIM_CCER_CCXBASE(channel); stm32_modifyreg16(priv, STM32_GTIM_CCER_OFFSET, mask, regval); diff --git a/arch/arm/src/stm32/stm32_tickless.c b/arch/arm/src/stm32/stm32_tickless.c index 53a25d75fdc..ac7f6783d7e 100644 --- a/arch/arm/src/stm32/stm32_tickless.c +++ b/arch/arm/src/stm32/stm32_tickless.c @@ -237,7 +237,8 @@ static int stm32_tickless_setchannel(uint8_t channel) /* Assume that channel is disabled and polarity is active high */ - ccer_val &= ~(3 << (channel << 2)); + ccer_val &= ~((GTIM_CCER_CC1P | GTIM_CCER_CC1E) << + GTIM_CCER_CCXBASE(channel)); /* This function is not supported on basic timers. To enable or * disable it, simply set its clock to valid frequency or zero. @@ -264,7 +265,7 @@ static int stm32_tickless_setchannel(uint8_t channel) /* Set polarity */ - ccer_val |= ATIM_CCER_CC1P << (channel << 2); + ccer_val |= ATIM_CCER_CC1P << GTIM_CCER_CCXBASE(channel); /* Define its position (shift) and get register offset */ diff --git a/arch/arm/src/stm32/stm32_tim.c b/arch/arm/src/stm32/stm32_tim.c index 27b3fa96998..c1813eeda27 100644 --- a/arch/arm/src/stm32/stm32_tim.c +++ b/arch/arm/src/stm32/stm32_tim.c @@ -985,7 +985,8 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, /* Assume that channel is disabled and polarity is active high */ - ccer_val &= ~(3 << (channel << 2)); + ccer_val &= ~((GTIM_CCER_CC1P | GTIM_CCER_CC1E) << + GTIM_CCER_CCXBASE(channel)); /* This function is not supported on basic timers. To enable or * disable it, simply set its clock to valid frequency or zero. @@ -1014,7 +1015,7 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, case STM32_TIM_CH_OUTPWM: ccmr_val = (ATIM_CCMR_MODE_PWM1 << ATIM_CCMR1_OC1M_SHIFT) + ATIM_CCMR1_OC1PE; - ccer_val |= ATIM_CCER_CC1E << (channel << 2); + ccer_val |= ATIM_CCER_CC1E << GTIM_CCER_CCXBASE(channel); break; default: @@ -1025,7 +1026,7 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, if (mode & STM32_TIM_CH_POLARITY_NEG) { - ccer_val |= ATIM_CCER_CC1P << (channel << 2); + ccer_val |= ATIM_CCER_CC1P << GTIM_CCER_CCXBASE(channel); } /* Define its position (shift) and get register offset */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_tim.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_tim.h index e356e220e80..3744ed0c484 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_tim.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_tim.h @@ -611,6 +611,7 @@ #define ATIM_CCER_CC5P (1 << 17) /* Bit 17: Capture/Compare 5 output Polarity */ #define ATIM_CCER_CC6E (1 << 20) /* Bit 20: Capture/Compare 6 output enable */ #define ATIM_CCER_CC6P (1 << 21) /* Bit 21: Capture/Compare 6 output Polarity */ +#define ATIM_CCER_CCXBASE(ch) (ch << 2) /* Each channel uses 4-bits */ /* 16-bit counter register */ @@ -1030,6 +1031,7 @@ #define GTIM_CCER_CC4E (1 << 12) /* Bit 12: Capture/Compare 4 output enable (TIM3 only) */ #define GTIM_CCER_CC4P (1 << 13) /* Bit 13: Capture/Compare 4 output Polarity (TIM3 only) */ #define GTIM_CCER_CC4NP (1 << 15) /* Bit 15: Capture/Compare 4 output Polarity (TIM3 only) */ +#define GTIM_CCER_CCXBASE(ch) (ch << 2) /* Each channel uses 4-bits */ /* 16-bit counter register */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_tim.c b/arch/arm/src/stm32f0l0g0/stm32_tim.c index 993a549830e..e4db4065191 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_tim.c +++ b/arch/arm/src/stm32f0l0g0/stm32_tim.c @@ -969,7 +969,8 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, /* Assume that channel is disabled and polarity is active high */ - ccer_val &= ~(3 << (channel << 2)); + ccer_val &= ~((GTIM_CCER_CC1P | GTIM_CCER_CC1E) << + GTIM_CCER_CCXBASE(channel)); /* This function is not supported on basic timers. To enable or * disable it, simply set its clock to valid frequency or zero. @@ -991,7 +992,7 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, case STM32_TIM_CH_OUTPWM: ccmr_val = (ATIM_CCMR_MODE_PWM1 << ATIM_CCMR1_OC1M_SHIFT) + ATIM_CCMR1_OC1PE; - ccer_val |= ATIM_CCER_CC1E << (channel << 2); + ccer_val |= ATIM_CCER_CC1E << GTIM_CCER_CCXBASE(channel); break; default: @@ -1002,7 +1003,7 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, if (mode & STM32_TIM_CH_POLARITY_NEG) { - ccer_val |= ATIM_CCER_CC1P << (channel << 2); + ccer_val |= ATIM_CCER_CC1P << GTIM_CCER_CCXBASE(channel); } /* Define its position (shift) and get register offset */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_tim.h b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_tim.h index 048a4697ec6..a0266da3bb0 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_tim.h +++ b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_tim.h @@ -694,6 +694,7 @@ #define ATIM_CCER_CC5P (1 << 17) /* Bit 17: Capture/Compare 5 output Polarity */ #define ATIM_CCER_CC6E (1 << 20) /* Bit 20: Capture/Compare 6 output enable */ #define ATIM_CCER_CC6P (1 << 21) /* Bit 21: Capture/Compare 6 output Polarity */ +#define ATIM_CCER_CCXBASE(ch) (ch << 2) /* Each channel uses 4-bits */ /* 16-bit counter register */ @@ -1073,6 +1074,7 @@ #define GTIM_CCER_CC4E (1 << 12) /* Bit 12: Capture/Compare 4 output enable (TIM2-5 only) */ #define GTIM_CCER_CC4P (1 << 13) /* Bit 13: Capture/Compare 4 output Polarity (TIM2-5 only) */ #define GTIM_CCER_CC4NP (1 << 15) /* Bit 15: Capture/Compare 4 output Polarity */ +#define GTIM_CCER_CCXBASE(ch) (ch << 2) /* Each channel uses 4-bits */ /* 16-bit counter register */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_tim.h b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_tim.h index 46e89338df2..0cc21659e60 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_tim.h +++ b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_tim.h @@ -696,6 +696,7 @@ #define ATIM_CCER_CC5P (1 << 17) /* Bit 17: Capture/Compare 5 output Polarity */ #define ATIM_CCER_CC6E (1 << 20) /* Bit 20: Capture/Compare 6 output enable */ #define ATIM_CCER_CC6P (1 << 21) /* Bit 21: Capture/Compare 6 output Polarity */ +#define ATIM_CCER_CCXBASE(ch) (ch << 2) /* Each channel uses 4-bits */ /* 16-bit counter register */ @@ -1075,6 +1076,7 @@ #define GTIM_CCER_CC4E (1 << 12) /* Bit 12: Capture/Compare 4 output enable (TIM2-5 only) */ #define GTIM_CCER_CC4P (1 << 13) /* Bit 13: Capture/Compare 4 output Polarity (TIM2-5 only) */ #define GTIM_CCER_CC4NP (1 << 15) /* Bit 15: Capture/Compare 4 output Polarity */ +#define GTIM_CCER_CCXBASE(ch) (ch << 2) /* Each channel uses 4-bits */ /* 16-bit counter register */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_tim.h b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_tim.h index c701d1353cf..947ceaffd68 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_tim.h +++ b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_tim.h @@ -702,6 +702,7 @@ #define ATIM_CCER_CC5P (1 << 17) /* Bit 17: Capture/Compare 5 output Polarity */ #define ATIM_CCER_CC6E (1 << 20) /* Bit 20: Capture/Compare 6 output enable */ #define ATIM_CCER_CC6P (1 << 21) /* Bit 21: Capture/Compare 6 output Polarity */ +#define ATIM_CCER_CCXBASE(ch) (ch << 2) /* Each channel uses 4-bits */ /* 16-bit counter register */ @@ -1093,6 +1094,7 @@ #define GTIM_CCER_CC4E (1 << 12) /* Bit 12: Capture/Compare 4 output enable (TIM2-5 only) */ #define GTIM_CCER_CC4P (1 << 13) /* Bit 13: Capture/Compare 4 output Polarity (TIM2-5 only) */ #define GTIM_CCER_CC4NP (1 << 15) /* Bit 15: Capture/Compare 4 output Polarity */ +#define GTIM_CCER_CCXBASE(ch) (ch << 2) /* Each channel uses 4-bits */ /* 16-bit counter register */ diff --git a/arch/arm/src/stm32f7/stm32_capture.c b/arch/arm/src/stm32f7/stm32_capture.c index c3f1b82b576..21beb11233e 100644 --- a/arch/arm/src/stm32f7/stm32_capture.c +++ b/arch/arm/src/stm32f7/stm32_capture.c @@ -969,9 +969,9 @@ static int stm32_cap_setchannel(FAR struct stm32_cap_dev_s *dev, /* Shift all CCER bits to corresponding channel */ mask = (GTIM_CCER_CC1E | GTIM_CCER_CC1P | GTIM_CCER_CC1NP); - mask <<= (channel << 2); - regval <<= (channel << 2); - ccer_en_bit <<= (channel << 2); + mask <<= GTIM_CCER_CCXBASE(channel); + regval <<= GTIM_CCER_CCXBASE(channel); + ccer_en_bit <<= GTIM_CCER_CCXBASE(channel); stm32_modifyreg16(priv, STM32_GTIM_CCER_OFFSET, mask, regval); diff --git a/arch/arm/src/stm32f7/stm32_tickless.c b/arch/arm/src/stm32f7/stm32_tickless.c index 74d4614a84e..8e127788f60 100644 --- a/arch/arm/src/stm32f7/stm32_tickless.c +++ b/arch/arm/src/stm32f7/stm32_tickless.c @@ -113,13 +113,13 @@ #endif #if CONFIG_STM32F7_TICKLESS_CHANNEL == 1 -#define DIER_CAPT_IE ATIM_DIER_CC1IE +#define DIER_CAPT_IE GTIM_DIER_CC1IE #elif CONFIG_STM32F7_TICKLESS_CHANNEL == 2 -#define DIER_CAPT_IE ATIM_DIER_CC2IE +#define DIER_CAPT_IE GTIM_DIER_CC2IE #elif CONFIG_STM32F7_TICKLESS_CHANNEL == 3 -#define DIER_CAPT_IE ATIM_DIER_CC3IE +#define DIER_CAPT_IE GTIM_DIER_CC3IE #elif CONFIG_STM32F7_TICKLESS_CHANNEL == 4 -#define DIER_CAPT_IE ATIM_DIER_CC4IE +#define DIER_CAPT_IE GTIM_DIER_CC4IE #endif /**************************************************************************** @@ -248,7 +248,8 @@ static int stm32_tickless_setchannel(uint8_t channel) /* Assume that channel is disabled and polarity is active high */ - ccer_val &= ~(3 << (channel << 2)); + ccer_val &= ~((GTIM_CCER_CC1P | GTIM_CCER_CC1E) << + GTIM_CCER_CCXBASE(channel)); /* This function is not supported on basic timers. To enable or * disable it, simply set its clock to valid frequency or zero. @@ -264,11 +265,11 @@ static int stm32_tickless_setchannel(uint8_t channel) * disabled. */ - ccmr_val = (ATIM_CCMR_MODE_FRZN << ATIM_CCMR1_OC1M_SHIFT); + ccmr_val = (GTIM_CCMR_MODE_FRZN << GTIM_CCMR1_OC1M_SHIFT); /* Set polarity */ - ccer_val |= ATIM_CCER_CC1P << (channel << 2); + ccer_val |= GTIM_CCER_CC1P << GTIM_CCER_CCXBASE(channel); /* Define its position (shift) and get register offset */ @@ -351,7 +352,7 @@ static void stm32_timing_handler(void) { g_tickless.overflow++; - STM32_TIM_ACKINT(g_tickless.tch, ATIM_SR_UIF); + STM32_TIM_ACKINT(g_tickless.tch, GTIM_SR_UIF); } /**************************************************************************** @@ -373,7 +374,7 @@ static int stm32_tickless_handler(int irq, void *context, void *arg) { int interrupt_flags = stm32_tickless_getint(); - if (interrupt_flags & ATIM_SR_UIF) + if (interrupt_flags & GTIM_SR_UIF) { stm32_timing_handler(); } @@ -684,7 +685,7 @@ int up_timer_gettime(FAR struct timespec *ts) overflow = g_tickless.overflow; counter = STM32_TIM_GETCOUNTER(g_tickless.tch); - pending = STM32_TIM_CHECKINT(g_tickless.tch, ATIM_SR_UIF); + pending = STM32_TIM_CHECKINT(g_tickless.tch, GTIM_SR_UIF); verify = STM32_TIM_GETCOUNTER(g_tickless.tch); /* If an interrupt was pending before we re-enabled interrupts, @@ -693,7 +694,7 @@ int up_timer_gettime(FAR struct timespec *ts) if (pending) { - STM32_TIM_ACKINT(g_tickless.tch, ATIM_SR_UIF); + STM32_TIM_ACKINT(g_tickless.tch, GTIM_SR_UIF); /* Increment the overflow count and use the value of the * guaranteed to be AFTER the overflow occurred. diff --git a/arch/arm/src/stm32f7/stm32_tim.c b/arch/arm/src/stm32f7/stm32_tim.c index 0b6d1647e44..31437450b4d 100644 --- a/arch/arm/src/stm32f7/stm32_tim.c +++ b/arch/arm/src/stm32f7/stm32_tim.c @@ -750,7 +750,8 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, /* Assume that channel is disabled and polarity is active high */ - ccer_val &= ~(3 << (channel << 2)); + ccer_val &= ~((GTIM_CCER_CC1P | GTIM_CCER_CC1E) << + GTIM_CCER_CCXBASE(channel)); /* This function is not supported on basic timers. To enable or * disable it, simply set its clock to valid frequency or zero. @@ -772,13 +773,13 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, case STM32_TIM_CH_OUTPWM: ccmr_val = (ATIM_CCMR_MODE_PWM1 << ATIM_CCMR1_OC1M_SHIFT) + ATIM_CCMR1_OC1PE; - ccer_val |= ATIM_CCER_CC1E << (channel << 2); + ccer_val |= ATIM_CCER_CC1E << GTIM_CCER_CCXBASE(channel); break; case STM32_TIM_CH_OUTTOGGLE: ccmr_val = (ATIM_CCMR_MODE_OCREFTOG << ATIM_CCMR1_OC1M_SHIFT) + ATIM_CCMR1_OC1PE; - ccer_val |= ATIM_CCER_CC1E << (channel << 2); + ccer_val |= ATIM_CCER_CC1E << GTIM_CCER_CCXBASE(channel); break; default: @@ -789,7 +790,7 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, if (mode & STM32_TIM_CH_POLARITY_NEG) { - ccer_val |= ATIM_CCER_CC1P << (channel << 2); + ccer_val |= ATIM_CCER_CC1P << GTIM_CCER_CCXBASE(channel); } /* Define its position (shift) and get register offset */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_tim.h b/arch/arm/src/stm32l4/hardware/stm32l4_tim.h index 29fd6d1fec7..8152c7661a6 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_tim.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_tim.h @@ -674,6 +674,7 @@ #define ATIM_CCER_CC5P (1 << 17) /* Bit 17: Capture/Compare 5 output Polarity */ #define ATIM_CCER_CC6E (1 << 20) /* Bit 20: Capture/Compare 6 output enable */ #define ATIM_CCER_CC6P (1 << 21) /* Bit 21: Capture/Compare 6 output Polarity */ +#define ATIM_CCER_CCXBASE(ch) (ch << 2) /* Each channel uses 4-bits */ /* 16-bit counter register */ @@ -1049,6 +1050,7 @@ #define GTIM_CCER_CC4E (1 << 12) /* Bit 12: Capture/Compare 4 output enable (TIM2-5 only) */ #define GTIM_CCER_CC4P (1 << 13) /* Bit 13: Capture/Compare 4 output Polarity (TIM2-5 only) */ #define GTIM_CCER_CC4NP (1 << 15) /* Bit 15: Capture/Compare 4 output Polarity */ +#define GTIM_CCER_CCXBASE(ch) (ch << 2) /* Each channel uses 4-bits */ /* 16-bit counter register */ diff --git a/arch/arm/src/stm32l4/stm32l4_adc.c b/arch/arm/src/stm32l4/stm32l4_adc.c index c1162ff5bd3..3c986f61590 100644 --- a/arch/arm/src/stm32l4/stm32l4_adc.c +++ b/arch/arm/src/stm32l4/stm32l4_adc.c @@ -959,12 +959,13 @@ static int adc_timinit(FAR struct stm32_dev_s *priv) /* Assume that channel is disabled and polarity is active high */ ccer_val = tim_getreg(priv, STM32L4_GTIM_CCER_OFFSET); - ccer_val &= ~(3 << (channel << 2)); + ccer_val &= ~((GTIM_CCER_CC1P | GTIM_CCER_CC1E) << + GTIM_CCER_CCXBASE(channel)); ccmr_val = (ATIM_CCMR_MODE_PWM1 << ATIM_CCMR1_OC1M_SHIFT) | (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR1_CC1S_SHIFT) | ATIM_CCMR1_OC1PE; - ccer_val |= ATIM_CCER_CC1E << (channel << 2); + ccer_val |= ATIM_CCER_CC1E << GTIM_CCER_CCXBASE(channel); if (channel & 1) { diff --git a/arch/arm/src/stm32l4/stm32l4_tim.c b/arch/arm/src/stm32l4/stm32l4_tim.c index f1e62e9b680..c06cbaf0265 100644 --- a/arch/arm/src/stm32l4/stm32l4_tim.c +++ b/arch/arm/src/stm32l4/stm32l4_tim.c @@ -1157,7 +1157,8 @@ static int stm32l4_tim_setchannel(FAR struct stm32l4_tim_dev_s *dev, /* Assume that channel is disabled and polarity is active high */ ccer_val = stm32l4_getreg16(dev, STM32L4_GTIM_CCER_OFFSET); - ccer_val &= ~(3 << (channel << 2)); + ccer_val &= ~((GTIM_CCER_CC1P | GTIM_CCER_CC1E) << + GTIM_CCER_CCXBASE(channel)); /* This function is not supported on basic timers. To enable or * disable it, simply set its clock to valid frequency or zero. @@ -1186,7 +1187,7 @@ static int stm32l4_tim_setchannel(FAR struct stm32l4_tim_dev_s *dev, case STM32L4_TIM_CH_OUTPWM: ccmr_val = (ATIM_CCMR_MODE_PWM1 << ATIM_CCMR1_OC1M_SHIFT) + ATIM_CCMR1_OC1PE; - ccer_val |= ATIM_CCER_CC1E << (channel << 2); + ccer_val |= ATIM_CCER_CC1E << GTIM_CCER_CCXBASE(channel); break; default: @@ -1197,7 +1198,7 @@ static int stm32l4_tim_setchannel(FAR struct stm32l4_tim_dev_s *dev, if (mode & STM32L4_TIM_CH_POLARITY_NEG) { - ccer_val |= ATIM_CCER_CC1P << (channel << 2); + ccer_val |= ATIM_CCER_CC1P << GTIM_CCER_CCXBASE(channel); } /* Define its position (shift) and get register offset */ diff --git a/arch/arm/src/stm32l5/hardware/stm32l5_tim.h b/arch/arm/src/stm32l5/hardware/stm32l5_tim.h index 0675e025d7d..e673f9c0af7 100644 --- a/arch/arm/src/stm32l5/hardware/stm32l5_tim.h +++ b/arch/arm/src/stm32l5/hardware/stm32l5_tim.h @@ -625,6 +625,7 @@ #define ATIM_CCER_CC5P (1 << 17) /* Bit 17: Capture/Compare 5 output Polarity */ #define ATIM_CCER_CC6E (1 << 20) /* Bit 20: Capture/Compare 6 output enable */ #define ATIM_CCER_CC6P (1 << 21) /* Bit 21: Capture/Compare 6 output Polarity */ +#define ATIM_CCER_CCXBASE(ch) (ch << 2) /* Each channel uses 4-bits */ /* 16-bit counter register */ @@ -970,6 +971,7 @@ #define GTIM_CCER_CC4E (1 << 12) /* Bit 12: Capture/Compare 4 output enable (TIM2-5 only) */ #define GTIM_CCER_CC4P (1 << 13) /* Bit 13: Capture/Compare 4 output Polarity (TIM2-5 only) */ #define GTIM_CCER_CC4NP (1 << 15) /* Bit 15: Capture/Compare 4 output Polarity */ +#define GTIM_CCER_CCXBASE(ch) (ch << 2) /* Each channel uses 4-bits */ /* 16-bit counter register */ diff --git a/arch/arm/src/stm32l5/stm32l5_tim.c b/arch/arm/src/stm32l5/stm32l5_tim.c index 93009cdfbe6..5a289df9b5a 100644 --- a/arch/arm/src/stm32l5/stm32l5_tim.c +++ b/arch/arm/src/stm32l5/stm32l5_tim.c @@ -943,7 +943,8 @@ static int stm32l5_tim_setchannel(FAR struct stm32l5_tim_dev_s *dev, /* Assume that channel is disabled and polarity is active high */ ccer_val = stm32l5_getreg16(dev, STM32L5_GTIM_CCER_OFFSET); - ccer_val &= ~(3 << (channel << 2)); + ccer_val &= ~((GTIM_CCER_CC1P | GTIM_CCER_CC1E) << + GTIM_CCER_CCXBASE(channel)); /* This function is not supported on basic timers. To enable or * disable it, simply set its clock to valid frequency or zero. @@ -972,7 +973,7 @@ static int stm32l5_tim_setchannel(FAR struct stm32l5_tim_dev_s *dev, case STM32L5_TIM_CH_OUTPWM: ccmr_val = (ATIM_CCMR_MODE_PWM1 << ATIM_CCMR1_OC1M_SHIFT) + ATIM_CCMR1_OC1PE; - ccer_val |= ATIM_CCER_CC1E << (channel << 2); + ccer_val |= ATIM_CCER_CC1E << GTIM_CCER_CCXBASE(channel); break; default: @@ -983,7 +984,7 @@ static int stm32l5_tim_setchannel(FAR struct stm32l5_tim_dev_s *dev, if (mode & STM32L5_TIM_CH_POLARITY_NEG) { - ccer_val |= ATIM_CCER_CC1P << (channel << 2); + ccer_val |= ATIM_CCER_CC1P << GTIM_CCER_CCXBASE(channel); } /* Define its position (shift) and get register offset */