From 5854a1cd37acac479d3f2755df94b6451eeb0ea0 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 11 Dec 2017 10:40:45 -0600 Subject: [PATCH] arch/arm/src/lpc54xx/chip: Add framework that will eventually support I2C and SPI. --- arch/arm/src/lpc54xx/Kconfig | 162 +++++++++++ arch/arm/src/lpc54xx/Make.defs | 15 +- arch/arm/src/lpc54xx/chip/lpc54_i2c.h | 329 ++++++++++++++++++++++ arch/arm/src/lpc54xx/chip/lpc54_lcd.h | 332 ++++++++++++++++++++++ arch/arm/src/lpc54xx/chip/lpc54_spi.h | 297 +++++++++++++++++++ arch/arm/src/lpc54xx/chip/lpc54_usart.h | 360 ++++++++++++------------ 6 files changed, 1313 insertions(+), 182 deletions(-) create mode 100644 arch/arm/src/lpc54xx/chip/lpc54_i2c.h create mode 100644 arch/arm/src/lpc54xx/chip/lpc54_lcd.h create mode 100644 arch/arm/src/lpc54xx/chip/lpc54_spi.h diff --git a/arch/arm/src/lpc54xx/Kconfig b/arch/arm/src/lpc54xx/Kconfig index eaaa786ac61..08b468961b3 100644 --- a/arch/arm/src/lpc54xx/Kconfig +++ b/arch/arm/src/lpc54xx/Kconfig @@ -109,6 +109,10 @@ config ARCH_LPC54_HAVE_SHA # Peripheral Selection +config LPC54_HAVE_I2C + bool + default n + config LPC54_HAVE_FLEXCOMM bool default n @@ -163,71 +167,229 @@ config LPC54_FLEXCOMM9 default n select LPC54_HAVE_FLEXCOMM +config LPC54_HAVE_SPI + bool + default n + +config LPC54_HAVE_USART + bool + default n + menu "LPC54xx Peripheral Selection" +config LPC54_I2C0 + bool "I2C0" + default n + select LPC54_FLEXCOMM0 + select LPC54_HAVE_I2C + +config LPC54_I2C1 + bool "I2C1" + default n + select LPC54_FLEXCOMM1 + select LPC54_HAVE_I2C + +config LPC54_I2C2 + bool "I2C2" + default n + select LPC54_FLEXCOMM2 + select LPC54_HAVE_I2C + +config LPC54_I2C3 + bool "I2C3" + default n + select LPC54_FLEXCOMM3 + select LPC54_HAVE_I2C + +config LPC54_I2C4 + bool "I2C4" + default n + select LPC54_FLEXCOMM4 + select LPC54_HAVE_I2C + +config LPC54_I2C5 + bool "I2C5" + default n + select LPC54_FLEXCOMM5 + select LPC54_HAVE_I2C + +config LPC54_I2C6 + bool "I2C6" + default n + select LPC54_FLEXCOMM6 + select LPC54_HAVE_I2C + +config LPC54_I2C7 + bool "I2C7" + default n + select LPC54_FLEXCOMM7 + select LPC54_HAVE_I2C + +config LPC54_I2C8 + bool "I2C8" + default n + select LPC54_FLEXCOMM8 + select LPC54_HAVE_I2C + +config LPC54_I2C9 + bool "I2C9" + default n + select LPC54_FLEXCOMM9 + select LPC54_HAVE_I2C + config LPC54_EMC bool "External Memory Controller (EMC)" default n +config LPC54_SPI0 + bool "SPI0" + default n + depends on !LPC54_I2C0 + select LPC54_FLEXCOMM0 + select LPC54_HAVE_SPI + +config LPC54_SPI1 + bool "SPI1" + default n + depends on !LPC54_I2C1 + select LPC54_FLEXCOMM1 + select LPC54_HAVE_SPI + +config LPC54_SPI2 + bool "SPI2" + default n + depends on !LPC54_I2C2 + select LPC54_FLEXCOMM2 + select LPC54_HAVE_SPI + +config LPC54_SPI3 + bool "SPI3" + default n + depends on !LPC54_I2C3 + select LPC54_FLEXCOMM3 + select LPC54_HAVE_SPI + +config LPC54_SPI4 + bool "SPI4" + default n + depends on !LPC54_I2C4 + select LPC54_FLEXCOMM4 + select LPC54_HAVE_SPI + +config LPC54_SPI5 + bool "SPI5" + default n + depends on !LPC54_I2C5 + select LPC54_FLEXCOMM5 + select LPC54_HAVE_SPI + +config LPC54_SPI6 + bool "SPI6" + default n + depends on !LPC54_I2C6 + select LPC54_FLEXCOMM6 + select LPC54_HAVE_SPI + +config LPC54_SPI7 + bool "SPI7" + default n + depends on !LPC54_I2C7 + select LPC54_FLEXCOMM7 + select LPC54_HAVE_SPI + +config LPC54_SPI8 + bool "SPI8" + default n + depends on !LPC54_I2C8 + select LPC54_FLEXCOMM8 + select LPC54_HAVE_SPI + +config LPC54_SPI9 + bool "SPI9" + default n + depends on !LPC54_I2C9 + select LPC54_FLEXCOMM9 + select LPC54_HAVE_SPI + config LPC54_USART0 bool "USART0" default n + depends on !LPC54_I2C0 && !LPC54_SPI0 select LPC54_FLEXCOMM0 select USART0_SERIALDRIVER + select LPC54_HAVE_USART config LPC54_USART1 bool "USART1" default n + depends on !LPC54_I2C1 && !LPC54_SPI1 select LPC54_FLEXCOMM1 select USART1_SERIALDRIVER + select LPC54_HAVE_USART config LPC54_USART2 bool "USART2" default n + depends on !LPC54_I2C2 && !LPC54_SPI2 select LPC54_FLEXCOMM2 select USART2_SERIALDRIVER + select LPC54_HAVE_USART config LPC54_USART3 bool "USART3" default n + depends on !LPC54_I2C3 && !LPC54_SPI3 select LPC54_FLEXCOMM3 select USART3_SERIALDRIVER + select LPC54_HAVE_USART config LPC54_USART4 bool "USART4" default n + depends on !LPC54_I2C4 && !LPC54_SPI4 select LPC54_FLEXCOMM4 select USART4_SERIALDRIVER + select LPC54_HAVE_USART config LPC54_USART5 bool "USART5" default n + depends on !LPC54_I2C5 && !LPC54_SPI5 select LPC54_FLEXCOMM5 select USART5_SERIALDRIVER + select LPC54_HAVE_USART config LPC54_USART6 bool "USART6" default n + depends on !LPC54_I2C6 && !LPC54_SPI6 select LPC54_FLEXCOMM6 select USART6_SERIALDRIVER + select LPC54_HAVE_USART config LPC54_USART7 bool "USART7" default n + depends on !LPC54_I2C7 && !LPC54_SPI7 select LPC54_FLEXCOMM7 select USART7_SERIALDRIVER + select LPC54_HAVE_USART config LPC54_USART8 bool "USART8" default n + depends on !LPC54_I2C8 && !LPC54_SPI8 select LPC54_FLEXCOMM8 select USART8_SERIALDRIVER + select LPC54_HAVE_USART config LPC54_USART9 bool "USART9" default n + depends on !LPC54_I2C9 && !LPC54_SPI9 select LPC54_FLEXCOMM9 select USART9_SERIALDRIVER + select LPC54_HAVE_USART endmenu # LPC54xx Peripheral Selection diff --git a/arch/arm/src/lpc54xx/Make.defs b/arch/arm/src/lpc54xx/Make.defs index fda98809275..7e15297ba73 100644 --- a/arch/arm/src/lpc54xx/Make.defs +++ b/arch/arm/src/lpc54xx/Make.defs @@ -81,8 +81,7 @@ endif CHIP_ASRCS = CHIP_CSRCS = lpc54_start.c lpc54_clockconfig.c lpc54_irq.c lpc54_clrpend.c -CHIP_CSRCS += lpc54_allocateheap.c lpc54_lowputc.c lpc54_serial.c -CHIP_CSRCS += lpc54_gpio.c +CHIP_CSRCS += lpc54_allocateheap.c lpc54_lowputc.c lpc54_gpio.c ifneq ($(CONFIG_SCHED_TICKLESS),y) CHIP_CSRCS += lpc54_timerisr.c @@ -102,6 +101,18 @@ ifeq ($(CONFIG_LPC54_GPIOIRQ),y) CHIP_CSRCS += lpc54_gpioirq.c endif +ifeq ($(CONFIG_LPC54_HAVE_USART),y) +CHIP_CSRCS += lpc54_serial.c +endif + +ifeq ($(CONFIG_LPC54_HAVE_I2C),y) +CHIP_CSRCS += lpc54_i2c.c +endif + +ifeq ($(CONFIG_LPC54_HAVE_SPI),y) +CHIP_CSRCS += lpc54_spi.c +endif + ifeq ($(CONFIG_LPC54_EMC),y) CHIP_CSRCS += lpc54_emc.c endif diff --git a/arch/arm/src/lpc54xx/chip/lpc54_i2c.h b/arch/arm/src/lpc54xx/chip/lpc54_i2c.h new file mode 100644 index 00000000000..1513845dfa8 --- /dev/null +++ b/arch/arm/src/lpc54xx/chip/lpc54_i2c.h @@ -0,0 +1,329 @@ +/**************************************************************************************************** + * arch/arm/src/lpc54xx/lpc54_i2c.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_I2C_H +#define __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_I2C_H + +/**************************************************************************************************** + * Included Files + ****************************************************************************************************/ + +#include +#include "chip/lpc54_memorymap.h" + +/**************************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************************/ + +/* Register offsets *********************************************************************************/ + +/* Shared I2C registers */ + +#define LPC54_I2C_CFG_OFFSET 0x0800 /* Configuration for shared functions */ +#define LPC54_I2C_STAT_OFFSET 0x0804 /* Status register for shared functions */ +#define LPC54_I2C_INTENSET_OFFSET 0x0808 /* Interrupt enable set and read */ +#define LPC54_I2C_INTENCLR_OFFSET 0x080c /* Interrupt enable clear */ +#define LPC54_I2C_TIMEOUT_OFFSET 0x0810 /* Time-out value */ +#define LPC54_I2C_CLKDIV_OFFSET 0x0814 /* Clock pre-divider for the entire I2C interface */ +#define LPC54_I2C_INTSTAT_OFFSET 0x0818 /* Interrupt status register for shared functions */ + +/* Master function registers */ + +#define LPC54_I2C_MSTCTL_OFFSET 0x0820 /* Master control */ +#define LPC54_I2C_MSTTIME_OFFSET 0x0824 /* Master timing configuration */ +#define LPC54_I2C_MSTDAT_OFFSET 0x0828 /* Combined Master receiver and transmitter data */ + +/* Slave function registers */ + +#define LPC54_I2C_SLVCTL_OFFSET 0x0840 /* Slave control */ +#define LPC54_I2C_SLVDAT_OFFSET 0x0844 /* Combined Slave receiver and transmitter data */ +#define LPC54_I2C_SLVADR0_OFFSET 0x0848 /* Slave address 0 */ +#define LPC54_I2C_SLVADR1_OFFSET 0x084c /* Slave address 1 */ +#define LPC54_I2C_SLVADR2_OFFSET 0x0850 /* Slave address 2 */ +#define LPC54_I2C_SLVADR3_OFFSET 0x0854 /* Slave address 3 */ +#define LPC54_I2C_SLVQUAL0_OFFSET 0x0858 /* Slave qualification for address 0 */ + +/* Monitor function registers */ + +#define LPC54_I2C_MONRXDAT_OFFSET 0x0880 /* Monitor receiver data */ + +/* ID register */ + +#define LPC54_I2C_ID_OFFSET 0x0ffc /* I2C module Identification */ + +/* Register addresses *******************************************************************************/ + +#define LPC54_I2C0_CFG (LPC54_FLEXCOMM0_BASE + LPC54_I2C_CFG_OFFSET) +#define LPC54_I2C0_STAT (LPC54_FLEXCOMM0_BASE + LPC54_I2C_STAT_OFFSET) +#define LPC54_I2C0_INTENSET (LPC54_FLEXCOMM0_BASE + LPC54_I2C_INTENSET_OFFSET) +#define LPC54_I2C0_INTENCLR (LPC54_FLEXCOMM0_BASE + LPC54_I2C_INTENCLR_OFFSET) +#define LPC54_I2C0_TIMEOUT (LPC54_FLEXCOMM0_BASE + LPC54_I2C_TIMEOUT_OFFSET) +#define LPC54_I2C0_CLKDIV (LPC54_FLEXCOMM0_BASE + LPC54_I2C_CLKDIV_OFFSET) +#define LPC54_I2C0_INTSTAT (LPC54_FLEXCOMM0_BASE + LPC54_I2C_INTSTAT_OFFSET) +#define LPC54_I2C0_MSTCTL (LPC54_FLEXCOMM0_BASE + LPC54_I2C_MSTCTL_OFFSET) +#define LPC54_I2C0_MSTTIME (LPC54_FLEXCOMM0_BASE + LPC54_I2C_MSTTIME_OFFSET) +#define LPC54_I2C0_MSTDAT (LPC54_FLEXCOMM0_BASE + LPC54_I2C_MSTDAT_OFFSET) +#define LPC54_I2C0_SLVCTL (LPC54_FLEXCOMM0_BASE + LPC54_I2C_SLVCTL_OFFSET) +#define LPC54_I2C0_SLVDAT (LPC54_FLEXCOMM0_BASE + LPC54_I2C_SLVDAT_OFFSET) +#define LPC54_I2C0_SLVADR0 (LPC54_FLEXCOMM0_BASE + LPC54_I2C_SLVADR0_OFFSET) +#define LPC54_I2C0_SLVADR1 (LPC54_FLEXCOMM0_BASE + LPC54_I2C_SLVADR1_OFFSET) +#define LPC54_I2C0_SLVADR2 (LPC54_FLEXCOMM0_BASE + LPC54_I2C_SLVADR2_OFFSET) +#define LPC54_I2C0_SLVADR3 (LPC54_FLEXCOMM0_BASE + LPC54_I2C_SLVADR3_OFFSET) +#define LPC54_I2C0_SLVQUAL0 (LPC54_FLEXCOMM0_BASE + LPC54_I2C_SLVQUAL0_OFFSET) +#define LPC54_I2C0_MONRXDAT (LPC54_FLEXCOMM0_BASE + LPC54_I2C_MONRXDAT_OFFSET) +#define LPC54_I2C0_ID (LPC54_FLEXCOMM0_BASE + LPC54_I2C_ID_OFFSET + +#define LPC54_I2C1_CFG (LPC54_FLEXCOMM1_BASE + LPC54_I2C_CFG_OFFSET) +#define LPC54_I2C1_STAT (LPC54_FLEXCOMM1_BASE + LPC54_I2C_STAT_OFFSET) +#define LPC54_I2C1_INTENSET (LPC54_FLEXCOMM1_BASE + LPC54_I2C_INTENSET_OFFSET) +#define LPC54_I2C1_INTENCLR (LPC54_FLEXCOMM1_BASE + LPC54_I2C_INTENCLR_OFFSET) +#define LPC54_I2C1_TIMEOUT (LPC54_FLEXCOMM1_BASE + LPC54_I2C_TIMEOUT_OFFSET) +#define LPC54_I2C1_CLKDIV (LPC54_FLEXCOMM1_BASE + LPC54_I2C_CLKDIV_OFFSET) +#define LPC54_I2C1_INTSTAT (LPC54_FLEXCOMM1_BASE + LPC54_I2C_INTSTAT_OFFSET) +#define LPC54_I2C1_MSTCTL (LPC54_FLEXCOMM1_BASE + LPC54_I2C_MSTCTL_OFFSET) +#define LPC54_I2C1_MSTTIME (LPC54_FLEXCOMM1_BASE + LPC54_I2C_MSTTIME_OFFSET) +#define LPC54_I2C1_MSTDAT (LPC54_FLEXCOMM1_BASE + LPC54_I2C_MSTDAT_OFFSET) +#define LPC54_I2C1_SLVCTL (LPC54_FLEXCOMM1_BASE + LPC54_I2C_SLVCTL_OFFSET) +#define LPC54_I2C1_SLVDAT (LPC54_FLEXCOMM1_BASE + LPC54_I2C_SLVDAT_OFFSET) +#define LPC54_I2C1_SLVADR0 (LPC54_FLEXCOMM1_BASE + LPC54_I2C_SLVADR0_OFFSET) +#define LPC54_I2C1_SLVADR1 (LPC54_FLEXCOMM1_BASE + LPC54_I2C_SLVADR1_OFFSET) +#define LPC54_I2C1_SLVADR2 (LPC54_FLEXCOMM1_BASE + LPC54_I2C_SLVADR2_OFFSET) +#define LPC54_I2C1_SLVADR3 (LPC54_FLEXCOMM1_BASE + LPC54_I2C_SLVADR3_OFFSET) +#define LPC54_I2C1_SLVQUAL0 (LPC54_FLEXCOMM1_BASE + LPC54_I2C_SLVQUAL0_OFFSET) +#define LPC54_I2C1_MONRXDAT (LPC54_FLEXCOMM1_BASE + LPC54_I2C_MONRXDAT_OFFSET) +#define LPC54_I2C1_ID (LPC54_FLEXCOMM1_BASE + LPC54_I2C_ID_OFFSET + +#define LPC54_I2C2_CFG (LPC54_FLEXCOMM2_BASE + LPC54_I2C_CFG_OFFSET) +#define LPC54_I2C2_STAT (LPC54_FLEXCOMM2_BASE + LPC54_I2C_STAT_OFFSET) +#define LPC54_I2C2_INTENSET (LPC54_FLEXCOMM2_BASE + LPC54_I2C_INTENSET_OFFSET) +#define LPC54_I2C2_INTENCLR (LPC54_FLEXCOMM2_BASE + LPC54_I2C_INTENCLR_OFFSET) +#define LPC54_I2C2_TIMEOUT (LPC54_FLEXCOMM2_BASE + LPC54_I2C_TIMEOUT_OFFSET) +#define LPC54_I2C2_CLKDIV (LPC54_FLEXCOMM2_BASE + LPC54_I2C_CLKDIV_OFFSET) +#define LPC54_I2C2_INTSTAT (LPC54_FLEXCOMM2_BASE + LPC54_I2C_INTSTAT_OFFSET) +#define LPC54_I2C2_MSTCTL (LPC54_FLEXCOMM2_BASE + LPC54_I2C_MSTCTL_OFFSET) +#define LPC54_I2C2_MSTTIME (LPC54_FLEXCOMM2_BASE + LPC54_I2C_MSTTIME_OFFSET) +#define LPC54_I2C2_MSTDAT (LPC54_FLEXCOMM2_BASE + LPC54_I2C_MSTDAT_OFFSET) +#define LPC54_I2C2_SLVCTL (LPC54_FLEXCOMM2_BASE + LPC54_I2C_SLVCTL_OFFSET) +#define LPC54_I2C2_SLVDAT (LPC54_FLEXCOMM2_BASE + LPC54_I2C_SLVDAT_OFFSET) +#define LPC54_I2C2_SLVADR0 (LPC54_FLEXCOMM2_BASE + LPC54_I2C_SLVADR0_OFFSET) +#define LPC54_I2C2_SLVADR1 (LPC54_FLEXCOMM2_BASE + LPC54_I2C_SLVADR1_OFFSET) +#define LPC54_I2C2_SLVADR2 (LPC54_FLEXCOMM2_BASE + LPC54_I2C_SLVADR2_OFFSET) +#define LPC54_I2C2_SLVADR3 (LPC54_FLEXCOMM2_BASE + LPC54_I2C_SLVADR3_OFFSET) +#define LPC54_I2C2_SLVQUAL0 (LPC54_FLEXCOMM2_BASE + LPC54_I2C_SLVQUAL0_OFFSET) +#define LPC54_I2C2_MONRXDAT (LPC54_FLEXCOMM2_BASE + LPC54_I2C_MONRXDAT_OFFSET) +#define LPC54_I2C2_ID (LPC54_FLEXCOMM2_BASE + LPC54_I2C_ID_OFFSET + +#define LPC54_I2C3_CFG (LPC54_FLEXCOMM3_BASE + LPC54_I2C_CFG_OFFSET) +#define LPC54_I2C3_STAT (LPC54_FLEXCOMM3_BASE + LPC54_I2C_STAT_OFFSET) +#define LPC54_I2C3_INTENSET (LPC54_FLEXCOMM3_BASE + LPC54_I2C_INTENSET_OFFSET) +#define LPC54_I2C3_INTENCLR (LPC54_FLEXCOMM3_BASE + LPC54_I2C_INTENCLR_OFFSET) +#define LPC54_I2C3_TIMEOUT (LPC54_FLEXCOMM3_BASE + LPC54_I2C_TIMEOUT_OFFSET) +#define LPC54_I2C3_CLKDIV (LPC54_FLEXCOMM3_BASE + LPC54_I2C_CLKDIV_OFFSET) +#define LPC54_I2C3_INTSTAT (LPC54_FLEXCOMM3_BASE + LPC54_I2C_INTSTAT_OFFSET) +#define LPC54_I2C3_MSTCTL (LPC54_FLEXCOMM3_BASE + LPC54_I2C_MSTCTL_OFFSET) +#define LPC54_I2C3_MSTTIME (LPC54_FLEXCOMM3_BASE + LPC54_I2C_MSTTIME_OFFSET) +#define LPC54_I2C3_MSTDAT (LPC54_FLEXCOMM3_BASE + LPC54_I2C_MSTDAT_OFFSET) +#define LPC54_I2C3_SLVCTL (LPC54_FLEXCOMM3_BASE + LPC54_I2C_SLVCTL_OFFSET) +#define LPC54_I2C3_SLVDAT (LPC54_FLEXCOMM3_BASE + LPC54_I2C_SLVDAT_OFFSET) +#define LPC54_I2C3_SLVADR0 (LPC54_FLEXCOMM3_BASE + LPC54_I2C_SLVADR0_OFFSET) +#define LPC54_I2C3_SLVADR1 (LPC54_FLEXCOMM3_BASE + LPC54_I2C_SLVADR1_OFFSET) +#define LPC54_I2C3_SLVADR2 (LPC54_FLEXCOMM3_BASE + LPC54_I2C_SLVADR2_OFFSET) +#define LPC54_I2C3_SLVADR3 (LPC54_FLEXCOMM3_BASE + LPC54_I2C_SLVADR3_OFFSET) +#define LPC54_I2C3_SLVQUAL0 (LPC54_FLEXCOMM3_BASE + LPC54_I2C_SLVQUAL0_OFFSET) +#define LPC54_I2C3_MONRXDAT (LPC54_FLEXCOMM3_BASE + LPC54_I2C_MONRXDAT_OFFSET) +#define LPC54_I2C3_ID (LPC54_FLEXCOMM3_BASE + LPC54_I2C_ID_OFFSET + +#define LPC54_I2C4_CFG (LPC54_FLEXCOMM4_BASE + LPC54_I2C_CFG_OFFSET) +#define LPC54_I2C4_STAT (LPC54_FLEXCOMM4_BASE + LPC54_I2C_STAT_OFFSET) +#define LPC54_I2C4_INTENSET (LPC54_FLEXCOMM4_BASE + LPC54_I2C_INTENSET_OFFSET) +#define LPC54_I2C4_INTENCLR (LPC54_FLEXCOMM4_BASE + LPC54_I2C_INTENCLR_OFFSET) +#define LPC54_I2C4_TIMEOUT (LPC54_FLEXCOMM4_BASE + LPC54_I2C_TIMEOUT_OFFSET) +#define LPC54_I2C4_CLKDIV (LPC54_FLEXCOMM4_BASE + LPC54_I2C_CLKDIV_OFFSET) +#define LPC54_I2C4_INTSTAT (LPC54_FLEXCOMM4_BASE + LPC54_I2C_INTSTAT_OFFSET) +#define LPC54_I2C4_MSTCTL (LPC54_FLEXCOMM4_BASE + LPC54_I2C_MSTCTL_OFFSET) +#define LPC54_I2C4_MSTTIME (LPC54_FLEXCOMM4_BASE + LPC54_I2C_MSTTIME_OFFSET) +#define LPC54_I2C4_MSTDAT (LPC54_FLEXCOMM4_BASE + LPC54_I2C_MSTDAT_OFFSET) +#define LPC54_I2C4_SLVCTL (LPC54_FLEXCOMM4_BASE + LPC54_I2C_SLVCTL_OFFSET) +#define LPC54_I2C4_SLVDAT (LPC54_FLEXCOMM4_BASE + LPC54_I2C_SLVDAT_OFFSET) +#define LPC54_I2C4_SLVADR0 (LPC54_FLEXCOMM4_BASE + LPC54_I2C_SLVADR0_OFFSET) +#define LPC54_I2C4_SLVADR1 (LPC54_FLEXCOMM4_BASE + LPC54_I2C_SLVADR1_OFFSET) +#define LPC54_I2C4_SLVADR2 (LPC54_FLEXCOMM4_BASE + LPC54_I2C_SLVADR2_OFFSET) +#define LPC54_I2C4_SLVADR3 (LPC54_FLEXCOMM4_BASE + LPC54_I2C_SLVADR3_OFFSET) +#define LPC54_I2C4_SLVQUAL0 (LPC54_FLEXCOMM4_BASE + LPC54_I2C_SLVQUAL0_OFFSET) +#define LPC54_I2C4_MONRXDAT (LPC54_FLEXCOMM4_BASE + LPC54_I2C_MONRXDAT_OFFSET) +#define LPC54_I2C4_ID (LPC54_FLEXCOMM4_BASE + LPC54_I2C_ID_OFFSET + +#define LPC54_I2C5_CFG (LPC54_FLEXCOMM5_BASE + LPC54_I2C_CFG_OFFSET) +#define LPC54_I2C5_STAT (LPC54_FLEXCOMM5_BASE + LPC54_I2C_STAT_OFFSET) +#define LPC54_I2C5_INTENSET (LPC54_FLEXCOMM5_BASE + LPC54_I2C_INTENSET_OFFSET) +#define LPC54_I2C5_INTENCLR (LPC54_FLEXCOMM5_BASE + LPC54_I2C_INTENCLR_OFFSET) +#define LPC54_I2C5_TIMEOUT (LPC54_FLEXCOMM5_BASE + LPC54_I2C_TIMEOUT_OFFSET) +#define LPC54_I2C5_CLKDIV (LPC54_FLEXCOMM5_BASE + LPC54_I2C_CLKDIV_OFFSET) +#define LPC54_I2C5_INTSTAT (LPC54_FLEXCOMM5_BASE + LPC54_I2C_INTSTAT_OFFSET) +#define LPC54_I2C5_MSTCTL (LPC54_FLEXCOMM5_BASE + LPC54_I2C_MSTCTL_OFFSET) +#define LPC54_I2C5_MSTTIME (LPC54_FLEXCOMM5_BASE + LPC54_I2C_MSTTIME_OFFSET) +#define LPC54_I2C5_MSTDAT (LPC54_FLEXCOMM5_BASE + LPC54_I2C_MSTDAT_OFFSET) +#define LPC54_I2C5_SLVCTL (LPC54_FLEXCOMM5_BASE + LPC54_I2C_SLVCTL_OFFSET) +#define LPC54_I2C5_SLVDAT (LPC54_FLEXCOMM5_BASE + LPC54_I2C_SLVDAT_OFFSET) +#define LPC54_I2C5_SLVADR0 (LPC54_FLEXCOMM5_BASE + LPC54_I2C_SLVADR0_OFFSET) +#define LPC54_I2C5_SLVADR1 (LPC54_FLEXCOMM5_BASE + LPC54_I2C_SLVADR1_OFFSET) +#define LPC54_I2C5_SLVADR2 (LPC54_FLEXCOMM5_BASE + LPC54_I2C_SLVADR2_OFFSET) +#define LPC54_I2C5_SLVADR3 (LPC54_FLEXCOMM5_BASE + LPC54_I2C_SLVADR3_OFFSET) +#define LPC54_I2C5_SLVQUAL0 (LPC54_FLEXCOMM5_BASE + LPC54_I2C_SLVQUAL0_OFFSET) +#define LPC54_I2C5_MONRXDAT (LPC54_FLEXCOMM5_BASE + LPC54_I2C_MONRXDAT_OFFSET) +#define LPC54_I2C5_ID (LPC54_FLEXCOMM5_BASE + LPC54_I2C_ID_OFFSET + +#define LPC54_I2C6_CFG (LPC54_FLEXCOMM6_BASE + LPC54_I2C_CFG_OFFSET) +#define LPC54_I2C6_STAT (LPC54_FLEXCOMM6_BASE + LPC54_I2C_STAT_OFFSET) +#define LPC54_I2C6_INTENSET (LPC54_FLEXCOMM6_BASE + LPC54_I2C_INTENSET_OFFSET) +#define LPC54_I2C6_INTENCLR (LPC54_FLEXCOMM6_BASE + LPC54_I2C_INTENCLR_OFFSET) +#define LPC54_I2C6_TIMEOUT (LPC54_FLEXCOMM6_BASE + LPC54_I2C_TIMEOUT_OFFSET) +#define LPC54_I2C6_CLKDIV (LPC54_FLEXCOMM6_BASE + LPC54_I2C_CLKDIV_OFFSET) +#define LPC54_I2C6_INTSTAT (LPC54_FLEXCOMM6_BASE + LPC54_I2C_INTSTAT_OFFSET) +#define LPC54_I2C6_MSTCTL (LPC54_FLEXCOMM6_BASE + LPC54_I2C_MSTCTL_OFFSET) +#define LPC54_I2C6_MSTTIME (LPC54_FLEXCOMM6_BASE + LPC54_I2C_MSTTIME_OFFSET) +#define LPC54_I2C6_MSTDAT (LPC54_FLEXCOMM6_BASE + LPC54_I2C_MSTDAT_OFFSET) +#define LPC54_I2C6_SLVCTL (LPC54_FLEXCOMM6_BASE + LPC54_I2C_SLVCTL_OFFSET) +#define LPC54_I2C6_SLVDAT (LPC54_FLEXCOMM6_BASE + LPC54_I2C_SLVDAT_OFFSET) +#define LPC54_I2C6_SLVADR0 (LPC54_FLEXCOMM6_BASE + LPC54_I2C_SLVADR0_OFFSET) +#define LPC54_I2C6_SLVADR1 (LPC54_FLEXCOMM6_BASE + LPC54_I2C_SLVADR1_OFFSET) +#define LPC54_I2C6_SLVADR2 (LPC54_FLEXCOMM6_BASE + LPC54_I2C_SLVADR2_OFFSET) +#define LPC54_I2C6_SLVADR3 (LPC54_FLEXCOMM6_BASE + LPC54_I2C_SLVADR3_OFFSET) +#define LPC54_I2C6_SLVQUAL0 (LPC54_FLEXCOMM6_BASE + LPC54_I2C_SLVQUAL0_OFFSET) +#define LPC54_I2C6_MONRXDAT (LPC54_FLEXCOMM6_BASE + LPC54_I2C_MONRXDAT_OFFSET) +#define LPC54_I2C6_ID (LPC54_FLEXCOMM6_BASE + LPC54_I2C_ID_OFFSET + +#define LPC54_I2C7_CFG (LPC54_FLEXCOMM7_BASE + LPC54_I2C_CFG_OFFSET) +#define LPC54_I2C7_STAT (LPC54_FLEXCOMM7_BASE + LPC54_I2C_STAT_OFFSET) +#define LPC54_I2C7_INTENSET (LPC54_FLEXCOMM7_BASE + LPC54_I2C_INTENSET_OFFSET) +#define LPC54_I2C7_INTENCLR (LPC54_FLEXCOMM7_BASE + LPC54_I2C_INTENCLR_OFFSET) +#define LPC54_I2C7_TIMEOUT (LPC54_FLEXCOMM7_BASE + LPC54_I2C_TIMEOUT_OFFSET) +#define LPC54_I2C7_CLKDIV (LPC54_FLEXCOMM7_BASE + LPC54_I2C_CLKDIV_OFFSET) +#define LPC54_I2C7_INTSTAT (LPC54_FLEXCOMM7_BASE + LPC54_I2C_INTSTAT_OFFSET) +#define LPC54_I2C7_MSTCTL (LPC54_FLEXCOMM7_BASE + LPC54_I2C_MSTCTL_OFFSET) +#define LPC54_I2C7_MSTTIME (LPC54_FLEXCOMM7_BASE + LPC54_I2C_MSTTIME_OFFSET) +#define LPC54_I2C7_MSTDAT (LPC54_FLEXCOMM7_BASE + LPC54_I2C_MSTDAT_OFFSET) +#define LPC54_I2C7_SLVCTL (LPC54_FLEXCOMM7_BASE + LPC54_I2C_SLVCTL_OFFSET) +#define LPC54_I2C7_SLVDAT (LPC54_FLEXCOMM7_BASE + LPC54_I2C_SLVDAT_OFFSET) +#define LPC54_I2C7_SLVADR0 (LPC54_FLEXCOMM7_BASE + LPC54_I2C_SLVADR0_OFFSET) +#define LPC54_I2C7_SLVADR1 (LPC54_FLEXCOMM7_BASE + LPC54_I2C_SLVADR1_OFFSET) +#define LPC54_I2C7_SLVADR2 (LPC54_FLEXCOMM7_BASE + LPC54_I2C_SLVADR2_OFFSET) +#define LPC54_I2C7_SLVADR3 (LPC54_FLEXCOMM7_BASE + LPC54_I2C_SLVADR3_OFFSET) +#define LPC54_I2C7_SLVQUAL0 (LPC54_FLEXCOMM7_BASE + LPC54_I2C_SLVQUAL0_OFFSET) +#define LPC54_I2C7_MONRXDAT (LPC54_FLEXCOMM7_BASE + LPC54_I2C_MONRXDAT_OFFSET) +#define LPC54_I2C7_ID (LPC54_FLEXCOMM7_BASE + LPC54_I2C_ID_OFFSET + +#define LPC54_I2C8_CFG (LPC54_FLEXCOMM8_BASE + LPC54_I2C_CFG_OFFSET) +#define LPC54_I2C8_STAT (LPC54_FLEXCOMM8_BASE + LPC54_I2C_STAT_OFFSET) +#define LPC54_I2C8_INTENSET (LPC54_FLEXCOMM8_BASE + LPC54_I2C_INTENSET_OFFSET) +#define LPC54_I2C8_INTENCLR (LPC54_FLEXCOMM8_BASE + LPC54_I2C_INTENCLR_OFFSET) +#define LPC54_I2C8_TIMEOUT (LPC54_FLEXCOMM8_BASE + LPC54_I2C_TIMEOUT_OFFSET) +#define LPC54_I2C8_CLKDIV (LPC54_FLEXCOMM8_BASE + LPC54_I2C_CLKDIV_OFFSET) +#define LPC54_I2C8_INTSTAT (LPC54_FLEXCOMM8_BASE + LPC54_I2C_INTSTAT_OFFSET) +#define LPC54_I2C8_MSTCTL (LPC54_FLEXCOMM8_BASE + LPC54_I2C_MSTCTL_OFFSET) +#define LPC54_I2C8_MSTTIME (LPC54_FLEXCOMM8_BASE + LPC54_I2C_MSTTIME_OFFSET) +#define LPC54_I2C8_MSTDAT (LPC54_FLEXCOMM8_BASE + LPC54_I2C_MSTDAT_OFFSET) +#define LPC54_I2C8_SLVCTL (LPC54_FLEXCOMM8_BASE + LPC54_I2C_SLVCTL_OFFSET) +#define LPC54_I2C8_SLVDAT (LPC54_FLEXCOMM8_BASE + LPC54_I2C_SLVDAT_OFFSET) +#define LPC54_I2C8_SLVADR0 (LPC54_FLEXCOMM8_BASE + LPC54_I2C_SLVADR0_OFFSET) +#define LPC54_I2C8_SLVADR1 (LPC54_FLEXCOMM8_BASE + LPC54_I2C_SLVADR1_OFFSET) +#define LPC54_I2C8_SLVADR2 (LPC54_FLEXCOMM8_BASE + LPC54_I2C_SLVADR2_OFFSET) +#define LPC54_I2C8_SLVADR3 (LPC54_FLEXCOMM8_BASE + LPC54_I2C_SLVADR3_OFFSET) +#define LPC54_I2C8_SLVQUAL0 (LPC54_FLEXCOMM8_BASE + LPC54_I2C_SLVQUAL0_OFFSET) +#define LPC54_I2C8_MONRXDAT (LPC54_FLEXCOMM8_BASE + LPC54_I2C_MONRXDAT_OFFSET) +#define LPC54_I2C8_ID (LPC54_FLEXCOMM8_BASE + LPC54_I2C_ID_OFFSET + +#define LPC54_I2C9_CFG (LPC54_FLEXCOMM9_BASE + LPC54_I2C_CFG_OFFSET) +#define LPC54_I2C9_STAT (LPC54_FLEXCOMM9_BASE + LPC54_I2C_STAT_OFFSET) +#define LPC54_I2C9_INTENSET (LPC54_FLEXCOMM9_BASE + LPC54_I2C_INTENSET_OFFSET) +#define LPC54_I2C9_INTENCLR (LPC54_FLEXCOMM9_BASE + LPC54_I2C_INTENCLR_OFFSET) +#define LPC54_I2C9_TIMEOUT (LPC54_FLEXCOMM9_BASE + LPC54_I2C_TIMEOUT_OFFSET) +#define LPC54_I2C9_CLKDIV (LPC54_FLEXCOMM9_BASE + LPC54_I2C_CLKDIV_OFFSET) +#define LPC54_I2C9_INTSTAT (LPC54_FLEXCOMM9_BASE + LPC54_I2C_INTSTAT_OFFSET) +#define LPC54_I2C9_MSTCTL (LPC54_FLEXCOMM9_BASE + LPC54_I2C_MSTCTL_OFFSET) +#define LPC54_I2C9_MSTTIME (LPC54_FLEXCOMM9_BASE + LPC54_I2C_MSTTIME_OFFSET) +#define LPC54_I2C9_MSTDAT (LPC54_FLEXCOMM9_BASE + LPC54_I2C_MSTDAT_OFFSET) +#define LPC54_I2C9_SLVCTL (LPC54_FLEXCOMM9_BASE + LPC54_I2C_SLVCTL_OFFSET) +#define LPC54_I2C9_SLVDAT (LPC54_FLEXCOMM9_BASE + LPC54_I2C_SLVDAT_OFFSET) +#define LPC54_I2C9_SLVADR0 (LPC54_FLEXCOMM9_BASE + LPC54_I2C_SLVADR0_OFFSET) +#define LPC54_I2C9_SLVADR1 (LPC54_FLEXCOMM9_BASE + LPC54_I2C_SLVADR1_OFFSET) +#define LPC54_I2C9_SLVADR2 (LPC54_FLEXCOMM9_BASE + LPC54_I2C_SLVADR2_OFFSET) +#define LPC54_I2C9_SLVADR3 (LPC54_FLEXCOMM9_BASE + LPC54_I2C_SLVADR3_OFFSET) +#define LPC54_I2C9_SLVQUAL0 (LPC54_FLEXCOMM9_BASE + LPC54_I2C_SLVQUAL0_OFFSET) +#define LPC54_I2C9_MONRXDAT (LPC54_FLEXCOMM9_BASE + LPC54_I2C_MONRXDAT_OFFSET) +#define LPC54_I2C9_ID (LPC54_FLEXCOMM9_BASE + LPC54_I2C_ID_OFFSET + +/* Register bit definitions *************************************************************************/ + +/* Configuration for shared functions */ +#define I2C_CFG_ +/* Status register for shared functions */ +#define I2C_STAT_ +/* Interrupt enable set and read */ +#define I2C_INTENSET_ +/* Interrupt enable clear */ +#define I2C_INTENCLR_ +/* Time-out value */ +#define I2C_TIMEOUT_ +/* Clock pre-divider for the entire I2C interface */ +#define I2C_CLKDIV_ +/* Interrupt status register for shared functions */ +#define I2C_INTSTAT_ +/* Master control */ +#define I2C_MSTCTL_ +/* Master timing configuration */ +#define I2C_MSTTIME_ +/* Combined Master receiver and transmitter data */ +#define I2C_MSTDAT_ +/* Slave control */ +#define I2C_SLVCTL_ +/* Combined Slave receiver and transmitter data */ +#define I2C_SLVDAT_ +/* Slave address 0 */ +#define I2C_SLVADR0_ +/* Slave address 1 */ +#define I2C_SLVADR1_ +/* Slave address 2 */ +#define I2C_SLVADR2_ +/* Slave address 3 */ +#define I2C_SLVADR3_ +/* Slave qualification for address 0 */ +#define I2C_SLVQUAL0_ +/* Monitor receiver data */ +#define I2C_MONRXDAT_ +/* I2C module Identification */ +#define I2C_ID_ + +#endif /* __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_I2C_H */ diff --git a/arch/arm/src/lpc54xx/chip/lpc54_lcd.h b/arch/arm/src/lpc54xx/chip/lpc54_lcd.h new file mode 100644 index 00000000000..ee86593fdd9 --- /dev/null +++ b/arch/arm/src/lpc54xx/chip/lpc54_lcd.h @@ -0,0 +1,332 @@ +/************************************************************************************************ + * arch/arm/src/lpc54xx/chip/lpc54_lcd.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_LCD_H +#define __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_LCD_H + +/************************************************************************************************ + * Included Files + ************************************************************************************************/ + +#include +#include "chip/lpc54_memorymap.h" + +/************************************************************************************************ + * Pre-processor Definitions + ************************************************************************************************/ + +/* Register offsets *****************************************************************************/ + +#define LPC54_LCD_TIMH_OFFSET 0x0000 /* Horizontal Timing Control register */ +#define LPC54_LCD_TIMV_OFFSET 0x0004 /* Vertical Timing Control register */ +#define LPC54_LCD_POL_OFFSET 0x0008 /* Clock & Signal Polarity Control register */ +#define LPC54_LCD_LE_OFFSET 0x000c /* Line End Control register */ +#define LPC54_LCD_UPBASE_OFFSET 0x0010 /* Upper Panel Frame Base Address register */ +#define LPC54_LCD_LPBASE_OFFSET 0x0014 /* Lower Panel Frame Base Address register */ +#define LPC54_LCD_CTRL_OFFSET 0x0018 /* LCD Control register */ +#define LPC54_LCD_INTMSK_OFFSET 0x001c /* Interrupt Mask register */ +#define LPC54_LCD_INTRAW_OFFSET 0x0020 /* Raw Interrupt Status register */ +#define LPC54_LCD_INTSTAT_OFFSET 0x0024 /* Masked Interrupt Status register */ +#define LPC54_LCD_INTCLR_OFFSET 0x0028 /* Interrupt Clear register */ +#define LPC54_LCD_UPCURR_OFFSET 0x002c /* Upper Panel Current Address Value register */ +#define LPC54_LCD_LPCURR_OFFSET 0x0030 /* Lower Panel Current Address Value register */ + +/* 256x16-bit Color Palette registers, n=0-127 */ + +#define LPC54_LCD_PAL_OFFSET(n) (0x0200 + ((n) << 2)) + +/* Cursor Image registers, n=0-255 */ + +#define LPC54_LCD_CRSR_IMG_OFFSET(n) (0x0800 + ((n) << 2)) + +#define LPC54_LCD_CRSR_CRTL_OFFSET 0x0c00 /* Cursor Control register */ +#define LPC54_LCD_CRSR_CFG_OFFSET 0x0c04 /* Cursor Configuration register */ +#define LPC54_LCD_CRSR_PAL0_OFFSET 0x0c08 /* Cursor Palette register 0 */ +#define LPC54_LCD_CRSR_PAL1_OFFSET 0x0c0c /* Cursor Palette register 1 */ +#define LPC54_LCD_CRSR_XY_OFFSET 0x0c10 /* Cursor XY Position register */ +#define LPC54_LCD_CRSR_CLIP_OFFSET 0x0c14 /* Cursor Clip Position register */ +#define LPC54_LCD_CRSR_INTMSK_OFFSET 0x0c20 /* Cursor Interrupt Mask regsiter */ +#define LPC54_LCD_CRSR_INTCLR_OFFSET 0x0c24 /* Cursor Interrupt Clear register */ +#define LPC54_LCD_CRSR_INTRAW_OFFSET 0x0c28 /* Cursor Raw Interrupt Status register */ +#define LPC54_LCD_CRSR_INTSTAT_OFFSET 0x0c2c /* Cursor Masked Interrupt Status register */ + +/* Register Addresses ***************************************************************************/ + +#define LPC54_LCD_TIMH (LPC54_LCD_BASE+LPC54_LCD_TIMH_OFFSET) +#define LPC54_LCD_TIMV (LPC54_LCD_BASE+LPC54_LCD_TIMV_OFFSET) +#define LPC54_LCD_POL (LPC54_LCD_BASE+LPC54_LCD_POL_OFFSET) +#define LPC54_LCD_LE (LPC54_LCD_BASE+LPC54_LCD_LE_OFFSET) +#define LPC54_LCD_UPBASE (LPC54_LCD_BASE+LPC54_LCD_UPBASE_OFFSET) +#define LPC54_LCD_LPBASE (LPC54_LCD_BASE+LPC54_LCD_LPBASE_OFFSET) +#define LPC54_LCD_CTRL (LPC54_LCD_BASE+LPC54_LCD_CTRL_OFFSET) +#define LPC54_LCD_INTMSK (LPC54_LCD_BASE+LPC54_LCD_INTMSK_OFFSET) +#define LPC54_LCD_INTRAW (LPC54_LCD_BASE+LPC54_LCD_INTRAW_OFFSET) +#define LPC54_LCD_INTSTAT (LPC54_LCD_BASE+LPC54_LCD_INTSTAT_OFFSET) +#define LPC54_LCD_INTCLR (LPC54_LCD_BASE+ LPC54_LCD_INTCLR_OFFSET) +#define LPC54_LCD_UPCURR (LPC54_LCD_BASE+LPC54_LCD_UPCURR_OFFSET) +#define LPC54_LCD_LPCURR (LPC54_LCD_BASE+LPC54_LCD_LPCURR_OFFSET) + +#define LPC54_LCD_PAL(n) (LPC54_LCD_BASE+LPC54_LCD_PAL_OFFSET(n)) +#define LPC54_LCD_CRSR_IMG(n) (LPC54_LCD_BASE+LPC54_LCD_CRSR_IMG_OFFSET(n)) + +#define LPC54_LCD_CRSR_CRTL (LPC54_LCD_BASE+LPC54_LCD_CRSR_CRTL_OFFSET) +#define LPC54_LCD_CRSR_CFG (LPC54_LCD_BASE+LPC54_LCD_CRSR_CFG_OFFSET) +#define LPC54_LCD_CRSR_PAL0 (LPC54_LCD_BASE+LPC54_LCD_CRSR_PAL0_OFFSET) +#define LPC54_LCD_CRSR_PAL1 (LPC54_LCD_BASE+LPC54_LCD_CRSR_PAL1_OFFSET) +#define LPC54_LCD_CRSR_XY (LPC54_LCD_BASE+LPC54_LCD_CRSR_XY_OFFSET) +#define LPC54_LCD_CRSR_CLIP (LPC54_LCD_BASE+LPC54_LCD_CRSR_CLIP_OFFSET) +#define LPC54_LCD_CRSR_INTMSK (LPC54_LCD_BASE+LPC54_LCD_CRSR_INTMSK_OFFSET) +#define LPC54_LCD_CRSR_INTCLR (LPC54_LCD_BASE+LPC54_LCD_CRSR_INTCLR_OFFSET) +#define LPC54_LCD_CRSR_INTRAW (LPC54_LCD_BASE+LPC54_LCD_CRSR_INTRAW_OFFSET) +#define LPC54_LCD_CRSR_INTSTAT (LPC54_LCD_BASE+LPC54_LCD_CRSR_INTSTAT_OFFSET) + +/* Register Bitfield Definitions ****************************************************************/ + +/* LCD_TIMH - Horizontal Timing Register */ + /* Bits 0-1: Reserved */ +#define LCD_TIMH_PPL_SHIFT (2) /* Bits 2-7: Pixels Per Line - 16-1024ppl */ +#define LCD_TIMH_PPL_MASK (0x3f << LCD_TIMH_PPL_SHIFT) +#define LCD_TIMH_HSW_SHIFT (8) /* Bits 8-15: Horizontal Sync Pulse Width */ +#define LCD_TIMH_HWS_MASK (0xff << LCD_TIMH_HSW_SHIFT) +#define LCD_TIMH_HFP_SHIFT (16) /* Bits 16-23: Horizontal Front Porch */ +#define LCD_TIMH_HFP_MASK (0xff << LCD_TIMH_HFP_SHIFT) +#define LCD_TIMH_HBP_SHIFT (24) /* Bits 24-31: Horizontal Back Porch */ +#define LCD_TIMH_HBP_MASK (0xff << LCD_TIMH_HBP_SHIFT) + +/* LCD_TIMV - Vertical Timing Register */ + +#define LCD_TIMV_LPP_SHIFT (0) /* Bits 0-9: Lines Per Panel 1-1024 lpp*/ +#define LCD_TIMV_LPP_MASK (0x3ff << LCD_TIMV_LPP_SHIFT) +#define LCD_TIMV_VSW_SHIFT (10) /* Bits 10-15: Vertical Synch Pulse Width */ +#define LCD_TIMV_VSW_MASK (0x3f << LCD_TIMV_VSW_SHIFT) +#define LCD_TIMV_VFP_SHIFT (16) /* Bits 16-23: Vertical Front Porch */ +#define LCD_TIMV_VFP_MASK (0xff << LCD_TIMV_VFP_SHIFT) +#define LCD_TIMV_VBP_SHIFT (24) /* Bits 24-31: Vertical Back Porch */ +#define LCD_TIMV_VBP_MASK (0xff << LCD_TIMV_VBP_SHIFT) + +/* LCD_POL - Clock and Signal Polarity Register */ + +#define LCD_POL_PCDLO_SHIFT (0) /* Bits 0-4: Lower 5 bits of panel clock divisor */ +#define LCD_POL_PCDLO_MASK (0x1f << LCD_POL_PCDLO_SHIFT) + /* Bit 5: Reserved */ +#define LCD_POL_ACB_SHIFT (6) /* Bits 6-10: AC bias pin frequency */ +#define LCD_POL_ACB_MASK (0x1f << LCD_POL_ACB_SHIFT) +#define LCD_POL_IVS (1 << 11) /* Bit 11: Invert vertical sync */ +#define LCD_POL_IHS (1 << 12) /* Bit 12: Invert horizontal sync */ +#define LCD_POL_IPC (1 << 13) /* Bit 13: Invert panel clock */ +#define LCD_POL_IOE (1 << 14) /* Bit 14: Invert output enable */ + /* Bit 15: Reserved */ +#define LCD_POL_CPL_SHIFT (16) /* Bit 16-25: Clocks per line */ +#define LCD_POL_CPL_MASK (0x3ff << LCD_POL_CPL_SHIFT) +#define LCD_POL_BCD (1 << 26) /* Bit 26: Bypass pixel clock divider */ +#define LCD_POL_PCDHI_SHIFT (27) /* Bits 27-31: Upper 5 bits of panel clock divisor */ +#define LCD_POL_PCDHI_MASK (0x1f << LCD_POL_PCDHI_SHIFT) + +/* LCD_LE - Line End Control Register */ + +#define LCD_LE_LED_SHIFT (0) /* Bits 0-6: Line End delay */ +#define LCD_LE_LED_MASK (0x7f << LCD_LE_LED_SHIFT) + /* Bits 7-15: Reserved */ +#define LCD_LE_LEE (1 << 16) /* Bit 16: LCD line end enable */ + /* Bit 17-31: Reserved */ +/* LCD_UPBASE - Upper Panel Frame Base Address Register */ + /* Bits 0-2: Reserved */ +#define LCD_UPBASE_LCDUPBASE_SHIFT (3) /* Bits 3-31: LCD upper panel base address */ +#define LCD_UPBASE_LCDUPBASE_MASK (0x1FFFFFFF << LCD_UPBASE_LCDUPBASE_SHIFT) + +/* LCD_LPBASE - Lower Panel Frame Base Address Register */ + /* Bits 0-2: Reserved */ +#define LCD_LPBASE_LCDLPBASE_SHIFT (3) /* Bits 3-31: LCD lower panel base address */ +#define LCD_LPBASE_LCDLPBASE_MASK (0x1FFFFFFF << LCD_UPBASE_LCDUPBASE_SHIFT) + +/* LCD_CTRL - Controle Register */ + +#define LCD_CTRL_LCDEN (1 << 0) /* Bit 0: LCD enable control bit */ +#define LCD_CTRL_LCDBPP_SHIFT (1) /* Bits 1-3: LCD bits per pixel */ +#define LCD_CTRL_LCDBPP_MASK (7 << LCD_CTRL_LCDBPP_SHIFT) +# define LCD_CTRL_LCDBPP_1 (0 << LCD_CTRL_LCDBPP_SHIFT) /* 1 bpp */ +# define LCD_CTRL_LCDBPP_2 (1 << LCD_CTRL_LCDBPP_SHIFT) /* 2 bpp */ +# define LCD_CTRL_LCDBPP_4 (2 << LCD_CTRL_LCDBPP_SHIFT) /* 4 bpp */ +# define LCD_CTRL_LCDBPP_8 (3 << LCD_CTRL_LCDBPP_SHIFT) /* 8 bpp */ +# define LCD_CTRL_LCDBPP_16 (4 << LCD_CTRL_LCDBPP_SHIFT) /* 16 bpp */ +# define LCD_CTRL_LCDBPP_24 (5 << LCD_CTRL_LCDBPP_SHIFT) /* 24 bpp (TFT panel only) */ +# define LCD_CTRL_LCDBPP_565 (6 << LCD_CTRL_LCDBPP_SHIFT) /* 16 bpp, 5:6:5 mode */ +# define LCD_CTRL_LCDBPP_444 (7 << LCD_CTRL_LCDBPP_SHIFT) /* 12 bpp, 4:4:4 mode */ +#define LCD_CTRL_LCDBW (1 << 4) /* Bit 4: STN LCD monochrome/color selection */ +#define LCD_CTRL_LCDTFT (1 << 5) /* Bit 5: LCD TFT type selection */ +#define LCD_CTRL_LCDMONO8 (1 << 6) /* Bit 6: Monochrome LCD interface bit */ +#define LCD_CTRL_LCDDUAL (1 << 7) /* Bit 7: Single or Dual LCD panel selection */ +#define LCD_CTRL_BGR (1 << 8) /* Bit 8: Color format */ +#define LCD_CTRL_BEBO (1 << 9) /* Bit 9: Big-Endian Byte Order */ +#define LCD_CTRL_BEPO (1 << 10) /* Bit 10: Big-Endian Pixel Ordering */ +#define LCD_CTRL_LCDPWR (1 << 11) /* Bit 11: LCD Power enable */ +#define LCD_CTRL_LCDVCOMP_SHIFT (12) /* Bits 12-13: LCD Vertical compare interrupt */ +#define LCD_CTRL_LCDVCOMP_MASK (3 << LCD_CTRL_LCDVCOMP_SHIFT) + /* Bits 14-15: Reserved */ +#define LCD_CTRL_WATERMARK (1 << 16) /* Bit 16: LCD DMA FIFO watermark level */ + /* Bits 17-31: Reserved */ +/* LCD_INTMSK - Interrupt Mask Register */ + /* Bits 0: Reserved */ +#define LCD_INTMSK_FUFIM (1 << 1) /* Bit 1: FIFO underflow interrupt enable */ +#define LCD_INTMSK_LNBUIM (1 << 2) /* Bit 2: LCD next base address interrupt enable */ +#define LCD_INTMSK_VCOMPIM (1 << 3) /* Bit 3: Vertical compare interrupt enable */ +#define LCD_INTMSK_BERIM (1 << 4) /* Bit 4: AHB Master error interrupt enable */ + /* Bits 5-31: Reserved */ +#define LCD_INTMSK_ALL (0x1e) + +/* LCD_INTRAW - Raw Interrupt Status Register */ + /* Bits 0: Reserved */ +#define LCD_INTRAW_FUFRIS (1 << 1) /* Bit 1: FIFO Undeflow raw interrupt status */ +#define LCD_INTRAW_LNBURIS (1 << 2) /* Bit 2: LCD Next address base update intterupt */ +#define LCD_INTRAW_VCOMPRIS (1 << 3) /* Bit 3: Vertical compare interrupt status */ +#define LCD_INTRAW_BERRAW (1 << 4) /* Bit 4: AHB Master bus error interrupt status */ + /* Bits 5-31: Reserved */ +#define LCD_INTRAW_ALL (0x1e) + +/* LCD_INTSTAT - Masked Interrupt Status Register */ + /* Bits 0: Reserved */ +#define LCD_INTSTAT_FUFMIS (1 << 1) /* Bit 1: FIFO Undeflow raw interrupt status */ +#define LCD_INTSTAT_LNBUMIS (1 << 2) /* Bit 2: LCD Next address base update intterupt */ +#define LCD_INTSTAT_VCOMPMIS (1 << 3) /* Bit 3: Vertical compare interrupt status */ +#define LCD_INTSTAT_BERMIS (1 << 4) /* Bit 4: AHB Master bus error interrupt status */ + /* Bits 15-31: Reserved */ +#define LCD_INTSTAT_ALL (0x1e) + +/* LCD_INTCLR - Interrupt Clear Register */ + /* Bits 0: Reserved */ +#define LCD_INTCLR_FUFIC (1 << 1) /* Bit 1: FIFO Undeflow raw interrupt clear */ +#define LCD_INTCLR_LNBUIC (1 << 2) /* Bit 2: LCD Next address base update intterupt */ +#define LCD_INTCLR_VCOMPIC (1 << 3) /* Bit 3: Vertical compare interrupt clear */ +#define LCD_INTCLR_BERIC (1 << 4) /* Bit 4: AHB Master bus error interrupt clear */ + /* Bits 15-31: Reserved */ +#define LCD_INTCLR_ALL (0x1e) + +/* Upper and Lower Panel Address register has no bitfields */ +/* + * Upper Panel Current Address register (LCDUPCURR) + * Lower Panel Current Address register (LCDLPCURR) + */ + +/* LCD_PAL - Color Palette Registers */ + +#define LCD_PAL_R0_SHIFT (0) /* Bits 0-4: Red palette data */ +#define LCD_PAL_R0_MASK (0x1f << LCD_PAL_R0_SHIFT) +#define LCD_PAL_G0_SHIFT (5) /* Bits 5-9: Green palette data */ +#define LCD_PAL_G0_MASK (0x1f << LCD_PAL_G0_SHIFT) +#define LCD_PAL_B0_SHIFT (10) /* Bits 10-14: Blue paletted data */ +#define LCD_PAL_B0_MASK (0x1f << LCD_PAL_B0_SHIFT) +#define LCD_PAL_I0 (1 << 15) /* Bit 15: Intensity/Unused bit */ +#define LCD_PAL_R1_SHIFT (16) /* Bits 16-20: Red palette data */ +#define LCD_PAL_R1_MASK (0x1f << LCD_PAL_R1_SHIFT) +#define LCD_PAL_G1_SHIFT (21) /* Bits 21-25: Green palette data */ +#define LCD_PAL_G1_MASK (0x1f << LCD_PAL_G1_SHIFT) +#define LCD_PAL_B1_SHIFT (26) /* Bits 26-30: Blue palette data */ +#define LCD_PAL_B1_MASK (0x1f << LCD_PAL_B1_SHIFT) +#define LCD_PAL_I1 (1 << 31) /* Bit 31: Intensity/Unused bit */ + +/* LCD_CRSR_IMG - Cursor Image Register - has no bitfields */ +/* The 256 words of the cursor image register defines the appearance + * of either one 64x64 cursor, or 4 32x32 cursors. + */ + +/* LCD CRSR_CTRL - Cursor Control Register */ + +#define LCD_CRSR_CTRL_CRSON (1 << 0) /* Bit 0: Cursor enable */ + /* Bits 1-3: Reserved */ +#define LCD_CRSR_CTRL_CRSRNUM_SHIFT (4) /* Bits 4-5: Cursor image number */ +#define LCD_CRSR_CTRL_CRSRNUM_MASK (3 << LCD_CRSR_CTRL_CRSRNUM1_0_SHIFT) + /* Bits 6-31: Reserved */ +/* If the selected cursor is 32x32 */ + +#define LCD_CURSOR0 (0) +#define LCD_CURSOR1 (1) +#define LCD_CURSOR2 (2) +#define LCD_CURSOR3 (3) + +/* LCD CRSR_CFG - Cursor Configuration Register */ + +#define LCD_CRSR_CFG_CRSRSIZE (1 << 0) /* Bit 0: Cursor size selection */ +#define LCD_CRSR_CFG_FRAMESYNC (1 << 1) /* Bit 1: Cursor frame sync type */ + /* Bits 2-31: Reserved */ + +#define LCD_CURSOR_SIZE32 (0) /* 32x32 */ +#define LCD_CURSOR_SIZE64 (1) /* 64x64 */ +#define LCD_CURSOR_FRAMEASYNC (0) /* Cursor coordinates are asynchronous */ +#define LCD_CURSOR_FRAMESYNC (1) /* coordinates are synchronize to framesync pulse */ + +/* LCD CRSR_PAL0/1 - Cursor Palette Registers */ + +#define LCD_CRSR_PAL_RED_SHIFT (0) /* Bits 0-7: Red color componnent */ +#define LCD_CRSR_PAL_RED_MASK (0xff << LCD_CRSR_PAL0_RED_SHIFT) +#define LCD_CRSR_PAL_GREEN_SHIFT (8) /* Bits 8-15: Green color component */ +#define LCD_CRSR_PAL_GREEN_MASK (0xff << LCD_CRSR_PAL0_GREEN_SHIFT) +#define LCD_CRSR_PAL_BLUE_SHIFT (16) /* Bits 16-23: Blue color component */ +#define LCD_CRSR_PAL_BLUE_MASK (0xff << LCD_CRSR_PAL0_BLUE_SHIFT) + /* Bits 24-31: Reserved */ +/* LCD CRSR_XY - Cursor XY Position Register */ + +#define LCD_CRSR_CRSRX_SHIFT (0) /* Bits 0-9: X ordinate */ +#define LCD_CRSR_CRSRX_MASK (0x3ff << LCD_CRSR_CRSRX_SHIFT) + /* Bits 10-15: Reserved */ +#define LCD_CRSR_CRSRY_SHIFT (16) /* Bits 16-25: Y ordinate */ +#define LCD_CRSR_CRSRY_MASK (0x3ff << LCD_CRSR_CRSRY_SHIFT) + /* Bits 26-31: Reserved */ +/* LCD CRSR_CLIP - Cursor Clip Position Register */ + +#define LCD_CRSR_CRSRCLIPX_SHIFT (0) /* Bits 0-5: X clip position */ +#define LCD_CRSR_CRSRCLIPX_MASK (0x3f << LCD_CRSR_CRSRCLIPX_SHIFT) + /* Bits 6-7: Reserved */ +#define LCD_CRSR_CRSRCLIPY_SHIFT (8) /* Bits 8-13: Reserved */ +#define LCD_CRSR_CRSRCLIPY_MASK (0x3f << LCD_CRSR_CRSRCLIPY_SHIFT) + /* Bits 14-31: Reserved */ +/* LCD CRSR_INTMSK - Cursor Interrrupt Mask Register */ + +#define LCD_CRSR_INTMSK_CRSRIM (1 << 0) /* Bit 0: Cursor interrupt mask */ + /* Bits 1-31: Reserved */ +/* LCD CRSR_INTCLR - Cursor Interrrupt Clear Register */ + +#define LCD_CRSR_INTCLR_CRSRIC (1 << 0) /* Bit 0: Cursor interrupt clear */ + /* Bits 1-31: Reserved */ + +/* LCD CRSR_INTRAW - Cursor Raw Interrrupt Status Register */ + +#define LCD_CRSR_INTRAW_CRSRRIS (1 << 0) /* Bit 0: Cursor raw interrupt status */ + /* Bits 1-31: Reserved */ +/* LCD CRSR_INTSTAT - Mask Interrrupt Status Register */ + +#define LCD_CRSR_INTSTAT_CRSRMIS (1 << 0) /* Bit 0: Cursor mask interrupt status */ + /* Bits 1-31: Reserved */ + +#endif /* __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_LCD_H */ diff --git a/arch/arm/src/lpc54xx/chip/lpc54_spi.h b/arch/arm/src/lpc54xx/chip/lpc54_spi.h new file mode 100644 index 00000000000..9ab286e18a9 --- /dev/null +++ b/arch/arm/src/lpc54xx/chip/lpc54_spi.h @@ -0,0 +1,297 @@ +/**************************************************************************************************** + * arch/arm/src/lpc54xx/lpc54_spi.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_SPI_H +#define __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_SPI_H + +/**************************************************************************************************** + * Included Files + ****************************************************************************************************/ + +#include +#include "chip/lpc54_memorymap.h" + +/**************************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************************/ + +/* Register offsets *********************************************************************************/ + +/* Registers for the SPI function */ + +#define LPC54_SPI_CFG_OFFSET 0x0400 /* SPI Configuration register */ +#define LPC54_SPI_DLY_OFFSET 0x0404 /* SPI Delay register */ +#define LPC54_SPI_STAT_OFFSET 0x0408 /* SPI Status */ +#define LPC54_SPI_INTENSET_OFFSET 0x040c /* SPI Interrupt Enable read and set */ +#define LPC54_SPI_INTENCLR_OFFSET 0x0410 /* SPI Interrupt Enable Clear */ +#define LPC54_SPI_DIV_OFFSET 0x0424 /* SPI clock Divider */ +#define LPC54_SPI_INTSTAT_OFFSET 0x0428 /* SPI Interrupt Status */ + +/* Registers for FIFO control and data access */ + +#define LPC54_SPI_FIFOCFG_OFFSET 0x0e00 /* FIFO configuration and enable register */ +#define LPC54_SPI_FIFOSTAT_OFFSET 0x0e04 /* FIFO status register */ +#define LPC54_SPI_FIFOTRIG_OFFSET 0x0e08 /* FIFO trigger level settings for interrupt and DMA request */ +#define LPC54_SPI_FIFOINTENSET_OFFSET 0x0e10 /* FIFO interrupt enable set (enable) and read register */ +#define LPC54_SPI_FIFOINTENCLR_OFFSET 0x0e14 /* FIFO interrupt enable clear (disable) and read register */ +#define LPC54_SPI_FIFOINTSTAT_OFFSET 0x0e18 /* FIFO interrupt status register */ +#define LPC54_SPI_FIFOWR_OFFSET 0x0e20 /* FIFO write data */ +#define LPC54_SPI_FIFORD_OFFSET 0x0e30 /* FIFO read data */ +#define LPC54_SPI_FIFORDNOPOP_OFFSET 0x0e40 /* FIFO data read with no FIFO pop */ + +/* ID register */ + +#define LPC54_SPI_ID_OFFSET 0x0ffc /* SPI module Identification */ + +/* Register addresses *******************************************************************************/ + +#define LPC54_SPI0_CFG (LPC54_FLEXCOMM0_BASE + LPC54_SPI_CFG_OFFSET) +#define LPC54_SPI0_DLY (LPC54_FLEXCOMM0_BASE + LPC54_SPI_DLY_OFFSET) +#define LPC54_SPI0_STAT (LPC54_FLEXCOMM0_BASE + LPC54_SPI_STAT_OFFSET) +#define LPC54_SPI0_INTENSET (LPC54_FLEXCOMM0_BASE + LPC54_SPI_INTENSET_OFFSET) +#define LPC54_SPI0_INTENCLR (LPC54_FLEXCOMM0_BASE + LPC54_SPI_INTENCLR_OFFSET) +#define LPC54_SPI0_DIV (LPC54_FLEXCOMM0_BASE + LPC54_SPI_DIV_OFFSET) +#define LPC54_SPI0_INTSTAT (LPC54_FLEXCOMM0_BASE + LPC54_SPI_INTSTAT_OFFSET) +#define LPC54_SPI0_FIFOCFG (LPC54_FLEXCOMM0_BASE + LPC54_SPI_FIFOCFG_OFFSET) +#define LPC54_SPI0_FIFOSTAT (LPC54_FLEXCOMM0_BASE + LPC54_SPI_FIFOSTAT_OFFSET) +#define LPC54_SPI0_FIFOTRIG (LPC54_FLEXCOMM0_BASE + LPC54_SPI_FIFOTRIG_OFFSET) +#define LPC54_SPI0_FIFOINTENSET (LPC54_FLEXCOMM0_BASE + LPC54_SPI_FIFOINTENSET_OFFSET) +#define LPC54_SPI0_FIFOINTENCLR (LPC54_FLEXCOMM0_BASE + LPC54_SPI_FIFOINTENCLR_OFFSET) +#define LPC54_SPI0_FIFOINTSTAT (LPC54_FLEXCOMM0_BASE + LPC54_SPI_FIFOINTSTAT_OFFSET) +#define LPC54_SPI0_FIFOWR (LPC54_FLEXCOMM0_BASE + LPC54_SPI_FIFOWR_OFFSET) +#define LPC54_SPI0_FIFORD (LPC54_FLEXCOMM0_BASE + LPC54_SPI_FIFORD_OFFSET) +#define LPC54_SPI0_FIFORDNOPOP (LPC54_FLEXCOMM0_BASE + LPC54_SPI_FIFORDNOPOP_OFFSET) +#define LPC54_SPI0_ID (LPC54_FLEXCOMM0_BASE + LPC54_SPI_ID_OFFSET) + +#define LPC54_SPI1_CFG (LPC54_FLEXCOMM1_BASE + LPC54_SPI_CFG_OFFSET) +#define LPC54_SPI1_DLY (LPC54_FLEXCOMM1_BASE + LPC54_SPI_DLY_OFFSET) +#define LPC54_SPI1_STAT (LPC54_FLEXCOMM1_BASE + LPC54_SPI_STAT_OFFSET) +#define LPC54_SPI1_INTENSET (LPC54_FLEXCOMM1_BASE + LPC54_SPI_INTENSET_OFFSET) +#define LPC54_SPI1_INTENCLR (LPC54_FLEXCOMM1_BASE + LPC54_SPI_INTENCLR_OFFSET) +#define LPC54_SPI1_DIV (LPC54_FLEXCOMM1_BASE + LPC54_SPI_DIV_OFFSET) +#define LPC54_SPI1_INTSTAT (LPC54_FLEXCOMM1_BASE + LPC54_SPI_INTSTAT_OFFSET) +#define LPC54_SPI1_FIFOCFG (LPC54_FLEXCOMM1_BASE + LPC54_SPI_FIFOCFG_OFFSET) +#define LPC54_SPI1_FIFOSTAT (LPC54_FLEXCOMM1_BASE + LPC54_SPI_FIFOSTAT_OFFSET) +#define LPC54_SPI1_FIFOTRIG (LPC54_FLEXCOMM1_BASE + LPC54_SPI_FIFOTRIG_OFFSET) +#define LPC54_SPI1_FIFOINTENSET (LPC54_FLEXCOMM1_BASE + LPC54_SPI_FIFOINTENSET_OFFSET) +#define LPC54_SPI1_FIFOINTENCLR (LPC54_FLEXCOMM1_BASE + LPC54_SPI_FIFOINTENCLR_OFFSET) +#define LPC54_SPI1_FIFOINTSTAT (LPC54_FLEXCOMM1_BASE + LPC54_SPI_FIFOINTSTAT_OFFSET) +#define LPC54_SPI1_FIFOWR (LPC54_FLEXCOMM1_BASE + LPC54_SPI_FIFOWR_OFFSET) +#define LPC54_SPI1_FIFORD (LPC54_FLEXCOMM1_BASE + LPC54_SPI_FIFORD_OFFSET) +#define LPC54_SPI1_FIFORDNOPOP (LPC54_FLEXCOMM1_BASE + LPC54_SPI_FIFORDNOPOP_OFFSET) +#define LPC54_SPI1_ID (LPC54_FLEXCOMM1_BASE + LPC54_SPI_ID_OFFSET) + +#define LPC54_SPI2_CFG (LPC54_FLEXCOMM2_BASE + LPC54_SPI_CFG_OFFSET) +#define LPC54_SPI2_DLY (LPC54_FLEXCOMM2_BASE + LPC54_SPI_DLY_OFFSET) +#define LPC54_SPI2_STAT (LPC54_FLEXCOMM2_BASE + LPC54_SPI_STAT_OFFSET) +#define LPC54_SPI2_INTENSET (LPC54_FLEXCOMM2_BASE + LPC54_SPI_INTENSET_OFFSET) +#define LPC54_SPI2_INTENCLR (LPC54_FLEXCOMM2_BASE + LPC54_SPI_INTENCLR_OFFSET) +#define LPC54_SPI2_DIV (LPC54_FLEXCOMM2_BASE + LPC54_SPI_DIV_OFFSET) +#define LPC54_SPI2_INTSTAT (LPC54_FLEXCOMM2_BASE + LPC54_SPI_INTSTAT_OFFSET) +#define LPC54_SPI2_FIFOCFG (LPC54_FLEXCOMM2_BASE + LPC54_SPI_FIFOCFG_OFFSET) +#define LPC54_SPI2_FIFOSTAT (LPC54_FLEXCOMM2_BASE + LPC54_SPI_FIFOSTAT_OFFSET) +#define LPC54_SPI2_FIFOTRIG (LPC54_FLEXCOMM2_BASE + LPC54_SPI_FIFOTRIG_OFFSET) +#define LPC54_SPI2_FIFOINTENSET (LPC54_FLEXCOMM2_BASE + LPC54_SPI_FIFOINTENSET_OFFSET) +#define LPC54_SPI2_FIFOINTENCLR (LPC54_FLEXCOMM2_BASE + LPC54_SPI_FIFOINTENCLR_OFFSET) +#define LPC54_SPI2_FIFOINTSTAT (LPC54_FLEXCOMM2_BASE + LPC54_SPI_FIFOINTSTAT_OFFSET) +#define LPC54_SPI2_FIFOWR (LPC54_FLEXCOMM2_BASE + LPC54_SPI_FIFOWR_OFFSET) +#define LPC54_SPI2_FIFORD (LPC54_FLEXCOMM2_BASE + LPC54_SPI_FIFORD_OFFSET) +#define LPC54_SPI2_FIFORDNOPOP (LPC54_FLEXCOMM2_BASE + LPC54_SPI_FIFORDNOPOP_OFFSET) +#define LPC54_SPI2_ID (LPC54_FLEXCOMM2_BASE + LPC54_SPI_ID_OFFSET) + +#define LPC54_SPI3_CFG (LPC54_FLEXCOMM3_BASE + LPC54_SPI_CFG_OFFSET) +#define LPC54_SPI3_DLY (LPC54_FLEXCOMM3_BASE + LPC54_SPI_DLY_OFFSET) +#define LPC54_SPI3_STAT (LPC54_FLEXCOMM3_BASE + LPC54_SPI_STAT_OFFSET) +#define LPC54_SPI3_INTENSET (LPC54_FLEXCOMM3_BASE + LPC54_SPI_INTENSET_OFFSET) +#define LPC54_SPI3_INTENCLR (LPC54_FLEXCOMM3_BASE + LPC54_SPI_INTENCLR_OFFSET) +#define LPC54_SPI3_DIV (LPC54_FLEXCOMM3_BASE + LPC54_SPI_DIV_OFFSET) +#define LPC54_SPI3_INTSTAT (LPC54_FLEXCOMM3_BASE + LPC54_SPI_INTSTAT_OFFSET) +#define LPC54_SPI3_FIFOCFG (LPC54_FLEXCOMM3_BASE + LPC54_SPI_FIFOCFG_OFFSET) +#define LPC54_SPI3_FIFOSTAT (LPC54_FLEXCOMM3_BASE + LPC54_SPI_FIFOSTAT_OFFSET) +#define LPC54_SPI3_FIFOTRIG (LPC54_FLEXCOMM3_BASE + LPC54_SPI_FIFOTRIG_OFFSET) +#define LPC54_SPI3_FIFOINTENSET (LPC54_FLEXCOMM3_BASE + LPC54_SPI_FIFOINTENSET_OFFSET) +#define LPC54_SPI3_FIFOINTENCLR (LPC54_FLEXCOMM3_BASE + LPC54_SPI_FIFOINTENCLR_OFFSET) +#define LPC54_SPI3_FIFOINTSTAT (LPC54_FLEXCOMM3_BASE + LPC54_SPI_FIFOINTSTAT_OFFSET) +#define LPC54_SPI3_FIFOWR (LPC54_FLEXCOMM3_BASE + LPC54_SPI_FIFOWR_OFFSET) +#define LPC54_SPI3_FIFORD (LPC54_FLEXCOMM3_BASE + LPC54_SPI_FIFORD_OFFSET) +#define LPC54_SPI3_FIFORDNOPOP (LPC54_FLEXCOMM3_BASE + LPC54_SPI_FIFORDNOPOP_OFFSET) +#define LPC54_SPI3_ID (LPC54_FLEXCOMM3_BASE + LPC54_SPI_ID_OFFSET) + +#define LPC54_SPI4_CFG (LPC54_FLEXCOMM4_BASE + LPC54_SPI_CFG_OFFSET) +#define LPC54_SPI4_DLY (LPC54_FLEXCOMM4_BASE + LPC54_SPI_DLY_OFFSET) +#define LPC54_SPI4_STAT (LPC54_FLEXCOMM4_BASE + LPC54_SPI_STAT_OFFSET) +#define LPC54_SPI4_INTENSET (LPC54_FLEXCOMM4_BASE + LPC54_SPI_INTENSET_OFFSET) +#define LPC54_SPI4_INTENCLR (LPC54_FLEXCOMM4_BASE + LPC54_SPI_INTENCLR_OFFSET) +#define LPC54_SPI4_DIV (LPC54_FLEXCOMM4_BASE + LPC54_SPI_DIV_OFFSET) +#define LPC54_SPI4_INTSTAT (LPC54_FLEXCOMM4_BASE + LPC54_SPI_INTSTAT_OFFSET) +#define LPC54_SPI4_FIFOCFG (LPC54_FLEXCOMM4_BASE + LPC54_SPI_FIFOCFG_OFFSET) +#define LPC54_SPI4_FIFOSTAT (LPC54_FLEXCOMM4_BASE + LPC54_SPI_FIFOSTAT_OFFSET) +#define LPC54_SPI4_FIFOTRIG (LPC54_FLEXCOMM4_BASE + LPC54_SPI_FIFOTRIG_OFFSET) +#define LPC54_SPI4_FIFOINTENSET (LPC54_FLEXCOMM4_BASE + LPC54_SPI_FIFOINTENSET_OFFSET) +#define LPC54_SPI4_FIFOINTENCLR (LPC54_FLEXCOMM4_BASE + LPC54_SPI_FIFOINTENCLR_OFFSET) +#define LPC54_SPI4_FIFOINTSTAT (LPC54_FLEXCOMM4_BASE + LPC54_SPI_FIFOINTSTAT_OFFSET) +#define LPC54_SPI4_FIFOWR (LPC54_FLEXCOMM4_BASE + LPC54_SPI_FIFOWR_OFFSET) +#define LPC54_SPI4_FIFORD (LPC54_FLEXCOMM4_BASE + LPC54_SPI_FIFORD_OFFSET) +#define LPC54_SPI4_FIFORDNOPOP (LPC54_FLEXCOMM4_BASE + LPC54_SPI_FIFORDNOPOP_OFFSET) +#define LPC54_SPI4_ID (LPC54_FLEXCOMM4_BASE + LPC54_SPI_ID_OFFSET) + +#define LPC54_SPI5_CFG (LPC54_FLEXCOMM5_BASE + LPC54_SPI_CFG_OFFSET) +#define LPC54_SPI5_DLY (LPC54_FLEXCOMM5_BASE + LPC54_SPI_DLY_OFFSET) +#define LPC54_SPI5_STAT (LPC54_FLEXCOMM5_BASE + LPC54_SPI_STAT_OFFSET) +#define LPC54_SPI5_INTENSET (LPC54_FLEXCOMM5_BASE + LPC54_SPI_INTENSET_OFFSET) +#define LPC54_SPI5_INTENCLR (LPC54_FLEXCOMM5_BASE + LPC54_SPI_INTENCLR_OFFSET) +#define LPC54_SPI5_DIV (LPC54_FLEXCOMM5_BASE + LPC54_SPI_DIV_OFFSET) +#define LPC54_SPI5_INTSTAT (LPC54_FLEXCOMM5_BASE + LPC54_SPI_INTSTAT_OFFSET) +#define LPC54_SPI5_FIFOCFG (LPC54_FLEXCOMM5_BASE + LPC54_SPI_FIFOCFG_OFFSET) +#define LPC54_SPI5_FIFOSTAT (LPC54_FLEXCOMM5_BASE + LPC54_SPI_FIFOSTAT_OFFSET) +#define LPC54_SPI5_FIFOTRIG (LPC54_FLEXCOMM5_BASE + LPC54_SPI_FIFOTRIG_OFFSET) +#define LPC54_SPI5_FIFOINTENSET (LPC54_FLEXCOMM5_BASE + LPC54_SPI_FIFOINTENSET_OFFSET) +#define LPC54_SPI5_FIFOINTENCLR (LPC54_FLEXCOMM5_BASE + LPC54_SPI_FIFOINTENCLR_OFFSET) +#define LPC54_SPI5_FIFOINTSTAT (LPC54_FLEXCOMM5_BASE + LPC54_SPI_FIFOINTSTAT_OFFSET) +#define LPC54_SPI5_FIFOWR (LPC54_FLEXCOMM5_BASE + LPC54_SPI_FIFOWR_OFFSET) +#define LPC54_SPI5_FIFORD (LPC54_FLEXCOMM5_BASE + LPC54_SPI_FIFORD_OFFSET) +#define LPC54_SPI5_FIFORDNOPOP (LPC54_FLEXCOMM5_BASE + LPC54_SPI_FIFORDNOPOP_OFFSET) +#define LPC54_SPI5_ID (LPC54_FLEXCOMM5_BASE + LPC54_SPI_ID_OFFSET) + +#define LPC54_SPI6_CFG (LPC54_FLEXCOMM6_BASE + LPC54_SPI_CFG_OFFSET) +#define LPC54_SPI6_DLY (LPC54_FLEXCOMM6_BASE + LPC54_SPI_DLY_OFFSET) +#define LPC54_SPI6_STAT (LPC54_FLEXCOMM6_BASE + LPC54_SPI_STAT_OFFSET) +#define LPC54_SPI6_INTENSET (LPC54_FLEXCOMM6_BASE + LPC54_SPI_INTENSET_OFFSET) +#define LPC54_SPI6_INTENCLR (LPC54_FLEXCOMM6_BASE + LPC54_SPI_INTENCLR_OFFSET) +#define LPC54_SPI6_DIV (LPC54_FLEXCOMM6_BASE + LPC54_SPI_DIV_OFFSET) +#define LPC54_SPI6_INTSTAT (LPC54_FLEXCOMM6_BASE + LPC54_SPI_INTSTAT_OFFSET) +#define LPC54_SPI6_FIFOCFG (LPC54_FLEXCOMM6_BASE + LPC54_SPI_FIFOCFG_OFFSET) +#define LPC54_SPI6_FIFOSTAT (LPC54_FLEXCOMM6_BASE + LPC54_SPI_FIFOSTAT_OFFSET) +#define LPC54_SPI6_FIFOTRIG (LPC54_FLEXCOMM6_BASE + LPC54_SPI_FIFOTRIG_OFFSET) +#define LPC54_SPI6_FIFOINTENSET (LPC54_FLEXCOMM6_BASE + LPC54_SPI_FIFOINTENSET_OFFSET) +#define LPC54_SPI6_FIFOINTENCLR (LPC54_FLEXCOMM6_BASE + LPC54_SPI_FIFOINTENCLR_OFFSET) +#define LPC54_SPI6_FIFOINTSTAT (LPC54_FLEXCOMM6_BASE + LPC54_SPI_FIFOINTSTAT_OFFSET) +#define LPC54_SPI6_FIFOWR (LPC54_FLEXCOMM6_BASE + LPC54_SPI_FIFOWR_OFFSET) +#define LPC54_SPI6_FIFORD (LPC54_FLEXCOMM6_BASE + LPC54_SPI_FIFORD_OFFSET) +#define LPC54_SPI6_FIFORDNOPOP (LPC54_FLEXCOMM6_BASE + LPC54_SPI_FIFORDNOPOP_OFFSET) +#define LPC54_SPI6_ID (LPC54_FLEXCOMM6_BASE + LPC54_SPI_ID_OFFSET) + +#define LPC54_SPI7_CFG (LPC54_FLEXCOMM7_BASE + LPC54_SPI_CFG_OFFSET) +#define LPC54_SPI7_DLY (LPC54_FLEXCOMM7_BASE + LPC54_SPI_DLY_OFFSET) +#define LPC54_SPI7_STAT (LPC54_FLEXCOMM7_BASE + LPC54_SPI_STAT_OFFSET) +#define LPC54_SPI7_INTENSET (LPC54_FLEXCOMM7_BASE + LPC54_SPI_INTENSET_OFFSET) +#define LPC54_SPI7_INTENCLR (LPC54_FLEXCOMM7_BASE + LPC54_SPI_INTENCLR_OFFSET) +#define LPC54_SPI7_DIV (LPC54_FLEXCOMM7_BASE + LPC54_SPI_DIV_OFFSET) +#define LPC54_SPI7_INTSTAT (LPC54_FLEXCOMM7_BASE + LPC54_SPI_INTSTAT_OFFSET) +#define LPC54_SPI7_FIFOCFG (LPC54_FLEXCOMM7_BASE + LPC54_SPI_FIFOCFG_OFFSET) +#define LPC54_SPI7_FIFOSTAT (LPC54_FLEXCOMM7_BASE + LPC54_SPI_FIFOSTAT_OFFSET) +#define LPC54_SPI7_FIFOTRIG (LPC54_FLEXCOMM7_BASE + LPC54_SPI_FIFOTRIG_OFFSET) +#define LPC54_SPI7_FIFOINTENSET (LPC54_FLEXCOMM7_BASE + LPC54_SPI_FIFOINTENSET_OFFSET) +#define LPC54_SPI7_FIFOINTENCLR (LPC54_FLEXCOMM7_BASE + LPC54_SPI_FIFOINTENCLR_OFFSET) +#define LPC54_SPI7_FIFOINTSTAT (LPC54_FLEXCOMM7_BASE + LPC54_SPI_FIFOINTSTAT_OFFSET) +#define LPC54_SPI7_FIFOWR (LPC54_FLEXCOMM7_BASE + LPC54_SPI_FIFOWR_OFFSET) +#define LPC54_SPI7_FIFORD (LPC54_FLEXCOMM7_BASE + LPC54_SPI_FIFORD_OFFSET) +#define LPC54_SPI7_FIFORDNOPOP (LPC54_FLEXCOMM7_BASE + LPC54_SPI_FIFORDNOPOP_OFFSET) +#define LPC54_SPI7_ID (LPC54_FLEXCOMM7_BASE + LPC54_SPI_ID_OFFSET) + +#define LPC54_SPI8_CFG (LPC54_FLEXCOMM8_BASE + LPC54_SPI_CFG_OFFSET) +#define LPC54_SPI8_DLY (LPC54_FLEXCOMM8_BASE + LPC54_SPI_DLY_OFFSET) +#define LPC54_SPI8_STAT (LPC54_FLEXCOMM8_BASE + LPC54_SPI_STAT_OFFSET) +#define LPC54_SPI8_INTENSET (LPC54_FLEXCOMM8_BASE + LPC54_SPI_INTENSET_OFFSET) +#define LPC54_SPI8_INTENCLR (LPC54_FLEXCOMM8_BASE + LPC54_SPI_INTENCLR_OFFSET) +#define LPC54_SPI8_DIV (LPC54_FLEXCOMM8_BASE + LPC54_SPI_DIV_OFFSET) +#define LPC54_SPI8_INTSTAT (LPC54_FLEXCOMM8_BASE + LPC54_SPI_INTSTAT_OFFSET) +#define LPC54_SPI8_FIFOCFG (LPC54_FLEXCOMM8_BASE + LPC54_SPI_FIFOCFG_OFFSET) +#define LPC54_SPI8_FIFOSTAT (LPC54_FLEXCOMM8_BASE + LPC54_SPI_FIFOSTAT_OFFSET) +#define LPC54_SPI8_FIFOTRIG (LPC54_FLEXCOMM8_BASE + LPC54_SPI_FIFOTRIG_OFFSET) +#define LPC54_SPI8_FIFOINTENSET (LPC54_FLEXCOMM8_BASE + LPC54_SPI_FIFOINTENSET_OFFSET) +#define LPC54_SPI8_FIFOINTENCLR (LPC54_FLEXCOMM8_BASE + LPC54_SPI_FIFOINTENCLR_OFFSET) +#define LPC54_SPI8_FIFOINTSTAT (LPC54_FLEXCOMM8_BASE + LPC54_SPI_FIFOINTSTAT_OFFSET) +#define LPC54_SPI8_FIFOWR (LPC54_FLEXCOMM8_BASE + LPC54_SPI_FIFOWR_OFFSET) +#define LPC54_SPI8_FIFORD (LPC54_FLEXCOMM8_BASE + LPC54_SPI_FIFORD_OFFSET) +#define LPC54_SPI8_FIFORDNOPOP (LPC54_FLEXCOMM8_BASE + LPC54_SPI_FIFORDNOPOP_OFFSET) +#define LPC54_SPI8_ID (LPC54_FLEXCOMM8_BASE + LPC54_SPI_ID_OFFSET) + +#define LPC54_SPI9_CFG (LPC54_FLEXCOMM9_BASE + LPC54_SPI_CFG_OFFSET) +#define LPC54_SPI9_DLY (LPC54_FLEXCOMM9_BASE + LPC54_SPI_DLY_OFFSET) +#define LPC54_SPI9_STAT (LPC54_FLEXCOMM9_BASE + LPC54_SPI_STAT_OFFSET) +#define LPC54_SPI9_INTENSET (LPC54_FLEXCOMM9_BASE + LPC54_SPI_INTENSET_OFFSET) +#define LPC54_SPI9_INTENCLR (LPC54_FLEXCOMM9_BASE + LPC54_SPI_INTENCLR_OFFSET) +#define LPC54_SPI9_DIV (LPC54_FLEXCOMM9_BASE + LPC54_SPI_DIV_OFFSET) +#define LPC54_SPI9_INTSTAT (LPC54_FLEXCOMM9_BASE + LPC54_SPI_INTSTAT_OFFSET) +#define LPC54_SPI9_FIFOCFG (LPC54_FLEXCOMM9_BASE + LPC54_SPI_FIFOCFG_OFFSET) +#define LPC54_SPI9_FIFOSTAT (LPC54_FLEXCOMM9_BASE + LPC54_SPI_FIFOSTAT_OFFSET) +#define LPC54_SPI9_FIFOTRIG (LPC54_FLEXCOMM9_BASE + LPC54_SPI_FIFOTRIG_OFFSET) +#define LPC54_SPI9_FIFOINTENSET (LPC54_FLEXCOMM9_BASE + LPC54_SPI_FIFOINTENSET_OFFSET) +#define LPC54_SPI9_FIFOINTENCLR (LPC54_FLEXCOMM9_BASE + LPC54_SPI_FIFOINTENCLR_OFFSET) +#define LPC54_SPI9_FIFOINTSTAT (LPC54_FLEXCOMM9_BASE + LPC54_SPI_FIFOINTSTAT_OFFSET) +#define LPC54_SPI9_FIFOWR (LPC54_FLEXCOMM9_BASE + LPC54_SPI_FIFOWR_OFFSET) +#define LPC54_SPI9_FIFORD (LPC54_FLEXCOMM9_BASE + LPC54_SPI_FIFORD_OFFSET) +#define LPC54_SPI9_FIFORDNOPOP (LPC54_FLEXCOMM9_BASE + LPC54_SPI_FIFORDNOPOP_OFFSET) +#define LPC54_SPI9_ID (LPC54_FLEXCOMM9_BASE + LPC54_SPI_ID_OFFSET) + +/* Register bit definitions *************************************************************************/ + +/* SPI Configuration register */ +#define SPI_CFG_ +/* SPI Delay register */ +#define SPI_DLY_ +/* SPI Status register */ +#define SPI_STAT_ +/* SPI Interrupt Enable read and set */ +#define SPI_INTENSET_ +/* SPI Interrupt Enable Clear */ +#define SPI_INTENCLR_ +/* SPI clock Divider */ +#define SPI_DIV_ +/* SPI Interrupt Status */ +#define SPI_INTSTAT_ +/* FIFO configuration and enable register */ +#define SPI_FIFOCFG_ +/* FIFO status register */ +#define SPI_FIFOSTAT_ +/* FIFO trigger level settings for interrupt and DMA request */ +#define SPI_FIFOTRIG_ +/* FIFO interrupt enable set (enable) and read register */ +#define SPI_FIFOINTENSET_ +/* FIFO interrupt enable clear (disable) and read register */ +#define SPI_FIFOINTENCLR_ +/* FIFO interrupt status register */ +#define SPI_FIFOINTSTAT_ +/* FIFO write data */ +#define SPI_FIFOWR_ +/* FIFO read data */ +#define SPI_FIFORD_ +/* FIFO data read with no FIFO pop */ +#define SPI_FIFORDNOPOP_ +/* SPI module Identification */ +#define SPI_ID_ + +#endif /* __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_SPI_H */ diff --git a/arch/arm/src/lpc54xx/chip/lpc54_usart.h b/arch/arm/src/lpc54xx/chip/lpc54_usart.h index e3f562c6066..494f8d268f0 100644 --- a/arch/arm/src/lpc54xx/chip/lpc54_usart.h +++ b/arch/arm/src/lpc54xx/chip/lpc54_usart.h @@ -80,195 +80,195 @@ /* USART Register Adreesses **************************************************************************/ -#define LPC54_USART0_CFG (LPC54_FLEXCOMM0_BASE+LPC54_USART_CFG_OFFSET) -#define LPC54_USART0_CTL (LPC54_FLEXCOMM0_BASE+LPC54_USART_CTL_OFFSET) -#define LPC54_USART0_STAT (LPC54_FLEXCOMM0_BASE+LPC54_USART_STAT_OFFSET) -#define LPC54_USART0_INTENSET (LPC54_FLEXCOMM0_BASE+LPC54_USART_INTENSET_OFFSET) -#define LPC54_USART0_INTENCLR (LPC54_FLEXCOMM0_BASE+LPC54_USART_INTENCLR_OFFSET) -#define LPC54_USART0_BRG (LPC54_FLEXCOMM0_BASE+LPC54_USART_BRG_OFFSET) -#define LPC54_USART0_INTSTAT (LPC54_FLEXCOMM0_BASE+LPC54_USART_INTSTAT_OFFSET) -#define LPC54_USART0_OSR (LPC54_FLEXCOMM0_BASE+LPC54_USART_OSR_OFFSET) -#define LPC54_USART0_FIFOCFG (LPC54_FLEXCOMM0_BASE+LPC54_USART_FIFOCFG_OFFSET) -#define LPC54_USART0_FIFOSTAT (LPC54_FLEXCOMM0_BASE+LPC54_USART_FIFOSTAT_OFFSET) -#define LPC54_USART0_FIFOTRIG (LPC54_FLEXCOMM0_BASE+LPC54_USART_FIFOTRIG_OFFSET) -#define LPC54_USART0_FIFOINTENSET (LPC54_FLEXCOMM0_BASE+LPC54_USART_FIFOINTENSET_OFFSET) -#define LPC54_USART0_FIFOINTENCLR (LPC54_FLEXCOMM0_BASE+LPC54_USART_FIFOINTENCLR_OFFSET) -#define LPC54_USART0_FIFOINTSTAT (LPC54_FLEXCOMM0_BASE+LPC54_USART_FIFOINTSTAT_OFFSET) -#define LPC54_USART0_FIFOWR (LPC54_FLEXCOMM0_BASE+LPC54_USART_FIFOWR_OFFSET) -#define LPC54_USART0_FIFORD (LPC54_FLEXCOMM0_BASE+LPC54_USART_FIFORD_OFFSET) -#define LPC54_USART0_FIFORDNOPOP (LPC54_FLEXCOMM0_BASE+LPC54_USART_FIFORDNOPOP_OFFSET) -#define LPC54_USART0_ID (LPC54_FLEXCOMM0_BASE+LPC54_USART_ID_OFFSET) +#define LPC54_USART0_CFG (LPC54_FLEXCOMM0_BASE + LPC54_USART_CFG_OFFSET) +#define LPC54_USART0_CTL (LPC54_FLEXCOMM0_BASE + LPC54_USART_CTL_OFFSET) +#define LPC54_USART0_STAT (LPC54_FLEXCOMM0_BASE + LPC54_USART_STAT_OFFSET) +#define LPC54_USART0_INTENSET (LPC54_FLEXCOMM0_BASE + LPC54_USART_INTENSET_OFFSET) +#define LPC54_USART0_INTENCLR (LPC54_FLEXCOMM0_BASE + LPC54_USART_INTENCLR_OFFSET) +#define LPC54_USART0_BRG (LPC54_FLEXCOMM0_BASE + LPC54_USART_BRG_OFFSET) +#define LPC54_USART0_INTSTAT (LPC54_FLEXCOMM0_BASE + LPC54_USART_INTSTAT_OFFSET) +#define LPC54_USART0_OSR (LPC54_FLEXCOMM0_BASE + LPC54_USART_OSR_OFFSET) +#define LPC54_USART0_FIFOCFG (LPC54_FLEXCOMM0_BASE + LPC54_USART_FIFOCFG_OFFSET) +#define LPC54_USART0_FIFOSTAT (LPC54_FLEXCOMM0_BASE + LPC54_USART_FIFOSTAT_OFFSET) +#define LPC54_USART0_FIFOTRIG (LPC54_FLEXCOMM0_BASE + LPC54_USART_FIFOTRIG_OFFSET) +#define LPC54_USART0_FIFOINTENSET (LPC54_FLEXCOMM0_BASE + LPC54_USART_FIFOINTENSET_OFFSET) +#define LPC54_USART0_FIFOINTENCLR (LPC54_FLEXCOMM0_BASE + LPC54_USART_FIFOINTENCLR_OFFSET) +#define LPC54_USART0_FIFOINTSTAT (LPC54_FLEXCOMM0_BASE + LPC54_USART_FIFOINTSTAT_OFFSET) +#define LPC54_USART0_FIFOWR (LPC54_FLEXCOMM0_BASE + LPC54_USART_FIFOWR_OFFSET) +#define LPC54_USART0_FIFORD (LPC54_FLEXCOMM0_BASE + LPC54_USART_FIFORD_OFFSET) +#define LPC54_USART0_FIFORDNOPOP (LPC54_FLEXCOMM0_BASE + LPC54_USART_FIFORDNOPOP_OFFSET) +#define LPC54_USART0_ID (LPC54_FLEXCOMM0_BASE + LPC54_USART_ID_OFFSET) -#define LPC54_USART1_CFG (LPC54_FLEXCOMM1_BASE+LPC54_USART_CFG_OFFSET) -#define LPC54_USART1_CTL (LPC54_FLEXCOMM1_BASE+LPC54_USART_CTL_OFFSET) -#define LPC54_USART1_STAT (LPC54_FLEXCOMM1_BASE+LPC54_USART_STAT_OFFSET) -#define LPC54_USART1_INTENSET (LPC54_FLEXCOMM1_BASE+LPC54_USART_INTENSET_OFFSET) -#define LPC54_USART1_INTENCLR (LPC54_FLEXCOMM1_BASE+LPC54_USART_INTENCLR_OFFSET) -#define LPC54_USART1_BRG (LPC54_FLEXCOMM1_BASE+LPC54_USART_BRG_OFFSET) -#define LPC54_USART1_INTSTAT (LPC54_FLEXCOMM1_BASE+LPC54_USART_INTSTAT_OFFSET) -#define LPC54_USART1_OSR (LPC54_FLEXCOMM1_BASE+LPC54_USART_OSR_OFFSET) -#define LPC54_USART1_FIFOCFG (LPC54_FLEXCOMM1_BASE+LPC54_USART_FIFOCFG_OFFSET) -#define LPC54_USART1_FIFOSTAT (LPC54_FLEXCOMM1_BASE+LPC54_USART_FIFOSTAT_OFFSET) -#define LPC54_USART1_FIFOTRIG (LPC54_FLEXCOMM1_BASE+LPC54_USART_FIFOTRIG_OFFSET) -#define LPC54_USART1_FIFOINTENSET (LPC54_FLEXCOMM1_BASE+LPC54_USART_FIFOINTENSET_OFFSET) -#define LPC54_USART1_FIFOINTENCLR (LPC54_FLEXCOMM1_BASE+LPC54_USART_FIFOINTENCLR_OFFSET) -#define LPC54_USART1_FIFOINTSTAT (LPC54_FLEXCOMM1_BASE+LPC54_USART_FIFOINTSTAT_OFFSET) -#define LPC54_USART1_FIFOWR (LPC54_FLEXCOMM1_BASE+LPC54_USART_FIFOWR_OFFSET) -#define LPC54_USART1_FIFORD (LPC54_FLEXCOMM1_BASE+LPC54_USART_FIFORD_OFFSET) -#define LPC54_USART1_FIFORDNOPOP (LPC54_FLEXCOMM1_BASE+LPC54_USART_FIFORDNOPOP_OFFSET) -#define LPC54_USART1_ID (LPC54_FLEXCOMM1_BASE+LPC54_USART_ID_OFFSET) +#define LPC54_USART1_CFG (LPC54_FLEXCOMM1_BASE + LPC54_USART_CFG_OFFSET) +#define LPC54_USART1_CTL (LPC54_FLEXCOMM1_BASE + LPC54_USART_CTL_OFFSET) +#define LPC54_USART1_STAT (LPC54_FLEXCOMM1_BASE + LPC54_USART_STAT_OFFSET) +#define LPC54_USART1_INTENSET (LPC54_FLEXCOMM1_BASE + LPC54_USART_INTENSET_OFFSET) +#define LPC54_USART1_INTENCLR (LPC54_FLEXCOMM1_BASE + LPC54_USART_INTENCLR_OFFSET) +#define LPC54_USART1_BRG (LPC54_FLEXCOMM1_BASE + LPC54_USART_BRG_OFFSET) +#define LPC54_USART1_INTSTAT (LPC54_FLEXCOMM1_BASE + LPC54_USART_INTSTAT_OFFSET) +#define LPC54_USART1_OSR (LPC54_FLEXCOMM1_BASE + LPC54_USART_OSR_OFFSET) +#define LPC54_USART1_FIFOCFG (LPC54_FLEXCOMM1_BASE + LPC54_USART_FIFOCFG_OFFSET) +#define LPC54_USART1_FIFOSTAT (LPC54_FLEXCOMM1_BASE + LPC54_USART_FIFOSTAT_OFFSET) +#define LPC54_USART1_FIFOTRIG (LPC54_FLEXCOMM1_BASE + LPC54_USART_FIFOTRIG_OFFSET) +#define LPC54_USART1_FIFOINTENSET (LPC54_FLEXCOMM1_BASE + LPC54_USART_FIFOINTENSET_OFFSET) +#define LPC54_USART1_FIFOINTENCLR (LPC54_FLEXCOMM1_BASE + LPC54_USART_FIFOINTENCLR_OFFSET) +#define LPC54_USART1_FIFOINTSTAT (LPC54_FLEXCOMM1_BASE + LPC54_USART_FIFOINTSTAT_OFFSET) +#define LPC54_USART1_FIFOWR (LPC54_FLEXCOMM1_BASE + LPC54_USART_FIFOWR_OFFSET) +#define LPC54_USART1_FIFORD (LPC54_FLEXCOMM1_BASE + LPC54_USART_FIFORD_OFFSET) +#define LPC54_USART1_FIFORDNOPOP (LPC54_FLEXCOMM1_BASE + LPC54_USART_FIFORDNOPOP_OFFSET) +#define LPC54_USART1_ID (LPC54_FLEXCOMM1_BASE + LPC54_USART_ID_OFFSET) -#define LPC54_USART2_CFG (LPC54_FLEXCOMM2_BASE+LPC54_USART_CFG_OFFSET) -#define LPC54_USART2_CTL (LPC54_FLEXCOMM2_BASE+LPC54_USART_CTL_OFFSET) -#define LPC54_USART2_STAT (LPC54_FLEXCOMM2_BASE+LPC54_USART_STAT_OFFSET) -#define LPC54_USART2_INTENSET (LPC54_FLEXCOMM2_BASE+LPC54_USART_INTENSET_OFFSET) -#define LPC54_USART2_INTENCLR (LPC54_FLEXCOMM2_BASE+LPC54_USART_INTENCLR_OFFSET) -#define LPC54_USART2_BRG (LPC54_FLEXCOMM2_BASE+LPC54_USART_BRG_OFFSET) -#define LPC54_USART2_INTSTAT (LPC54_FLEXCOMM2_BASE+LPC54_USART_INTSTAT_OFFSET) -#define LPC54_USART2_OSR (LPC54_FLEXCOMM2_BASE+LPC54_USART_OSR_OFFSET) -#define LPC54_USART2_FIFOCFG (LPC54_FLEXCOMM2_BASE+LPC54_USART_FIFOCFG_OFFSET) -#define LPC54_USART2_FIFOSTAT (LPC54_FLEXCOMM2_BASE+LPC54_USART_FIFOSTAT_OFFSET) -#define LPC54_USART2_FIFOTRIG (LPC54_FLEXCOMM2_BASE+LPC54_USART_FIFOTRIG_OFFSET) -#define LPC54_USART2_FIFOINTENSET (LPC54_FLEXCOMM2_BASE+LPC54_USART_FIFOINTENSET_OFFSET) -#define LPC54_USART2_FIFOINTENCLR (LPC54_FLEXCOMM2_BASE+LPC54_USART_FIFOINTENCLR_OFFSET) -#define LPC54_USART2_FIFOINTSTAT (LPC54_FLEXCOMM2_BASE+LPC54_USART_FIFOINTSTAT_OFFSET) -#define LPC54_USART2_FIFOWR (LPC54_FLEXCOMM2_BASE+LPC54_USART_FIFOWR_OFFSET) -#define LPC54_USART2_FIFORD (LPC54_FLEXCOMM2_BASE+LPC54_USART_FIFORD_OFFSET) -#define LPC54_USART2_FIFORDNOPOP (LPC54_FLEXCOMM2_BASE+LPC54_USART_FIFORDNOPOP_OFFSET) -#define LPC54_USART2_ID (LPC54_FLEXCOMM2_BASE+LPC54_USART_ID_OFFSET) +#define LPC54_USART2_CFG (LPC54_FLEXCOMM2_BASE + LPC54_USART_CFG_OFFSET) +#define LPC54_USART2_CTL (LPC54_FLEXCOMM2_BASE + LPC54_USART_CTL_OFFSET) +#define LPC54_USART2_STAT (LPC54_FLEXCOMM2_BASE + LPC54_USART_STAT_OFFSET) +#define LPC54_USART2_INTENSET (LPC54_FLEXCOMM2_BASE + LPC54_USART_INTENSET_OFFSET) +#define LPC54_USART2_INTENCLR (LPC54_FLEXCOMM2_BASE + LPC54_USART_INTENCLR_OFFSET) +#define LPC54_USART2_BRG (LPC54_FLEXCOMM2_BASE + LPC54_USART_BRG_OFFSET) +#define LPC54_USART2_INTSTAT (LPC54_FLEXCOMM2_BASE + LPC54_USART_INTSTAT_OFFSET) +#define LPC54_USART2_OSR (LPC54_FLEXCOMM2_BASE + LPC54_USART_OSR_OFFSET) +#define LPC54_USART2_FIFOCFG (LPC54_FLEXCOMM2_BASE + LPC54_USART_FIFOCFG_OFFSET) +#define LPC54_USART2_FIFOSTAT (LPC54_FLEXCOMM2_BASE + LPC54_USART_FIFOSTAT_OFFSET) +#define LPC54_USART2_FIFOTRIG (LPC54_FLEXCOMM2_BASE + LPC54_USART_FIFOTRIG_OFFSET) +#define LPC54_USART2_FIFOINTENSET (LPC54_FLEXCOMM2_BASE + LPC54_USART_FIFOINTENSET_OFFSET) +#define LPC54_USART2_FIFOINTENCLR (LPC54_FLEXCOMM2_BASE + LPC54_USART_FIFOINTENCLR_OFFSET) +#define LPC54_USART2_FIFOINTSTAT (LPC54_FLEXCOMM2_BASE + LPC54_USART_FIFOINTSTAT_OFFSET) +#define LPC54_USART2_FIFOWR (LPC54_FLEXCOMM2_BASE + LPC54_USART_FIFOWR_OFFSET) +#define LPC54_USART2_FIFORD (LPC54_FLEXCOMM2_BASE + LPC54_USART_FIFORD_OFFSET) +#define LPC54_USART2_FIFORDNOPOP (LPC54_FLEXCOMM2_BASE + LPC54_USART_FIFORDNOPOP_OFFSET) +#define LPC54_USART2_ID (LPC54_FLEXCOMM2_BASE + LPC54_USART_ID_OFFSET) -#define LPC54_USART3_CFG (LPC54_FLEXCOMM3_BASE+LPC54_USART_CFG_OFFSET) -#define LPC54_USART3_CTL (LPC54_FLEXCOMM3_BASE+LPC54_USART_CTL_OFFSET) -#define LPC54_USART3_STAT (LPC54_FLEXCOMM3_BASE+LPC54_USART_STAT_OFFSET) -#define LPC54_USART3_INTENSET (LPC54_FLEXCOMM3_BASE+LPC54_USART_INTENSET_OFFSET) -#define LPC54_USART3_INTENCLR (LPC54_FLEXCOMM3_BASE+LPC54_USART_INTENCLR_OFFSET) -#define LPC54_USART3_BRG (LPC54_FLEXCOMM3_BASE+LPC54_USART_BRG_OFFSET) -#define LPC54_USART3_INTSTAT (LPC54_FLEXCOMM3_BASE+LPC54_USART_INTSTAT_OFFSET) -#define LPC54_USART3_OSR (LPC54_FLEXCOMM3_BASE+LPC54_USART_OSR_OFFSET) -#define LPC54_USART3_FIFOCFG (LPC54_FLEXCOMM3_BASE+LPC54_USART_FIFOCFG_OFFSET) -#define LPC54_USART3_FIFOSTAT (LPC54_FLEXCOMM3_BASE+LPC54_USART_FIFOSTAT_OFFSET) -#define LPC54_USART3_FIFOTRIG (LPC54_FLEXCOMM3_BASE+LPC54_USART_FIFOTRIG_OFFSET) -#define LPC54_USART3_FIFOINTENSET (LPC54_FLEXCOMM3_BASE+LPC54_USART_FIFOINTENSET_OFFSET) -#define LPC54_USART3_FIFOINTENCLR (LPC54_FLEXCOMM3_BASE+LPC54_USART_FIFOINTENCLR_OFFSET) -#define LPC54_USART3_FIFOINTSTAT (LPC54_FLEXCOMM3_BASE+LPC54_USART_FIFOINTSTAT_OFFSET) -#define LPC54_USART3_FIFOWR (LPC54_FLEXCOMM3_BASE+LPC54_USART_FIFOWR_OFFSET) -#define LPC54_USART3_FIFORD (LPC54_FLEXCOMM3_BASE+LPC54_USART_FIFORD_OFFSET) -#define LPC54_USART3_FIFORDNOPOP (LPC54_FLEXCOMM3_BASE+LPC54_USART_FIFORDNOPOP_OFFSET) -#define LPC54_USART3_ID (LPC54_FLEXCOMM3_BASE+LPC54_USART_ID_OFFSET) +#define LPC54_USART3_CFG (LPC54_FLEXCOMM3_BASE + LPC54_USART_CFG_OFFSET) +#define LPC54_USART3_CTL (LPC54_FLEXCOMM3_BASE + LPC54_USART_CTL_OFFSET) +#define LPC54_USART3_STAT (LPC54_FLEXCOMM3_BASE + LPC54_USART_STAT_OFFSET) +#define LPC54_USART3_INTENSET (LPC54_FLEXCOMM3_BASE + LPC54_USART_INTENSET_OFFSET) +#define LPC54_USART3_INTENCLR (LPC54_FLEXCOMM3_BASE + LPC54_USART_INTENCLR_OFFSET) +#define LPC54_USART3_BRG (LPC54_FLEXCOMM3_BASE + LPC54_USART_BRG_OFFSET) +#define LPC54_USART3_INTSTAT (LPC54_FLEXCOMM3_BASE + LPC54_USART_INTSTAT_OFFSET) +#define LPC54_USART3_OSR (LPC54_FLEXCOMM3_BASE + LPC54_USART_OSR_OFFSET) +#define LPC54_USART3_FIFOCFG (LPC54_FLEXCOMM3_BASE + LPC54_USART_FIFOCFG_OFFSET) +#define LPC54_USART3_FIFOSTAT (LPC54_FLEXCOMM3_BASE + LPC54_USART_FIFOSTAT_OFFSET) +#define LPC54_USART3_FIFOTRIG (LPC54_FLEXCOMM3_BASE + LPC54_USART_FIFOTRIG_OFFSET) +#define LPC54_USART3_FIFOINTENSET (LPC54_FLEXCOMM3_BASE + LPC54_USART_FIFOINTENSET_OFFSET) +#define LPC54_USART3_FIFOINTENCLR (LPC54_FLEXCOMM3_BASE + LPC54_USART_FIFOINTENCLR_OFFSET) +#define LPC54_USART3_FIFOINTSTAT (LPC54_FLEXCOMM3_BASE + LPC54_USART_FIFOINTSTAT_OFFSET) +#define LPC54_USART3_FIFOWR (LPC54_FLEXCOMM3_BASE + LPC54_USART_FIFOWR_OFFSET) +#define LPC54_USART3_FIFORD (LPC54_FLEXCOMM3_BASE + LPC54_USART_FIFORD_OFFSET) +#define LPC54_USART3_FIFORDNOPOP (LPC54_FLEXCOMM3_BASE + LPC54_USART_FIFORDNOPOP_OFFSET) +#define LPC54_USART3_ID (LPC54_FLEXCOMM3_BASE + LPC54_USART_ID_OFFSET) -#define LPC54_USART4_CFG (LPC54_FLEXCOMM4_BASE+LPC54_USART_CFG_OFFSET) -#define LPC54_USART4_CTL (LPC54_FLEXCOMM4_BASE+LPC54_USART_CTL_OFFSET) -#define LPC54_USART4_STAT (LPC54_FLEXCOMM4_BASE+LPC54_USART_STAT_OFFSET) -#define LPC54_USART4_INTENSET (LPC54_FLEXCOMM4_BASE+LPC54_USART_INTENSET_OFFSET) -#define LPC54_USART4_INTENCLR (LPC54_FLEXCOMM4_BASE+LPC54_USART_INTENCLR_OFFSET) -#define LPC54_USART4_BRG (LPC54_FLEXCOMM4_BASE+LPC54_USART_BRG_OFFSET) -#define LPC54_USART4_INTSTAT (LPC54_FLEXCOMM4_BASE+LPC54_USART_INTSTAT_OFFSET) -#define LPC54_USART4_OSR (LPC54_FLEXCOMM4_BASE+LPC54_USART_OSR_OFFSET) -#define LPC54_USART4_FIFOCFG (LPC54_FLEXCOMM4_BASE+LPC54_USART_FIFOCFG_OFFSET) -#define LPC54_USART4_FIFOSTAT (LPC54_FLEXCOMM4_BASE+LPC54_USART_FIFOSTAT_OFFSET) -#define LPC54_USART4_FIFOTRIG (LPC54_FLEXCOMM4_BASE+LPC54_USART_FIFOTRIG_OFFSET) -#define LPC54_USART4_FIFOINTENSET (LPC54_FLEXCOMM4_BASE+LPC54_USART_FIFOINTENSET_OFFSET) -#define LPC54_USART4_FIFOINTENCLR (LPC54_FLEXCOMM4_BASE+LPC54_USART_FIFOINTENCLR_OFFSET) -#define LPC54_USART4_FIFOINTSTAT (LPC54_FLEXCOMM4_BASE+LPC54_USART_FIFOINTSTAT_OFFSET) -#define LPC54_USART4_FIFOWR (LPC54_FLEXCOMM4_BASE+LPC54_USART_FIFOWR_OFFSET) -#define LPC54_USART4_FIFORD (LPC54_FLEXCOMM4_BASE+LPC54_USART_FIFORD_OFFSET) -#define LPC54_USART4_FIFORDNOPOP (LPC54_FLEXCOMM4_BASE+LPC54_USART_FIFORDNOPOP_OFFSET) -#define LPC54_USART4_ID (LPC54_FLEXCOMM4_BASE+LPC54_USART_ID_OFFSET) +#define LPC54_USART4_CFG (LPC54_FLEXCOMM4_BASE + LPC54_USART_CFG_OFFSET) +#define LPC54_USART4_CTL (LPC54_FLEXCOMM4_BASE + LPC54_USART_CTL_OFFSET) +#define LPC54_USART4_STAT (LPC54_FLEXCOMM4_BASE + LPC54_USART_STAT_OFFSET) +#define LPC54_USART4_INTENSET (LPC54_FLEXCOMM4_BASE + LPC54_USART_INTENSET_OFFSET) +#define LPC54_USART4_INTENCLR (LPC54_FLEXCOMM4_BASE + LPC54_USART_INTENCLR_OFFSET) +#define LPC54_USART4_BRG (LPC54_FLEXCOMM4_BASE + LPC54_USART_BRG_OFFSET) +#define LPC54_USART4_INTSTAT (LPC54_FLEXCOMM4_BASE + LPC54_USART_INTSTAT_OFFSET) +#define LPC54_USART4_OSR (LPC54_FLEXCOMM4_BASE + LPC54_USART_OSR_OFFSET) +#define LPC54_USART4_FIFOCFG (LPC54_FLEXCOMM4_BASE + LPC54_USART_FIFOCFG_OFFSET) +#define LPC54_USART4_FIFOSTAT (LPC54_FLEXCOMM4_BASE + LPC54_USART_FIFOSTAT_OFFSET) +#define LPC54_USART4_FIFOTRIG (LPC54_FLEXCOMM4_BASE + LPC54_USART_FIFOTRIG_OFFSET) +#define LPC54_USART4_FIFOINTENSET (LPC54_FLEXCOMM4_BASE + LPC54_USART_FIFOINTENSET_OFFSET) +#define LPC54_USART4_FIFOINTENCLR (LPC54_FLEXCOMM4_BASE + LPC54_USART_FIFOINTENCLR_OFFSET) +#define LPC54_USART4_FIFOINTSTAT (LPC54_FLEXCOMM4_BASE + LPC54_USART_FIFOINTSTAT_OFFSET) +#define LPC54_USART4_FIFOWR (LPC54_FLEXCOMM4_BASE + LPC54_USART_FIFOWR_OFFSET) +#define LPC54_USART4_FIFORD (LPC54_FLEXCOMM4_BASE + LPC54_USART_FIFORD_OFFSET) +#define LPC54_USART4_FIFORDNOPOP (LPC54_FLEXCOMM4_BASE + LPC54_USART_FIFORDNOPOP_OFFSET) +#define LPC54_USART4_ID (LPC54_FLEXCOMM4_BASE + LPC54_USART_ID_OFFSET) -#define LPC54_USART5_CFG (LPC54_FLEXCOMM5_BASE+LPC54_USART_CFG_OFFSET) -#define LPC54_USART5_CTL (LPC54_FLEXCOMM5_BASE+LPC54_USART_CTL_OFFSET) -#define LPC54_USART5_STAT (LPC54_FLEXCOMM5_BASE+LPC54_USART_STAT_OFFSET) -#define LPC54_USART5_INTENSET (LPC54_FLEXCOMM5_BASE+LPC54_USART_INTENSET_OFFSET) -#define LPC54_USART5_INTENCLR (LPC54_FLEXCOMM5_BASE+LPC54_USART_INTENCLR_OFFSET) -#define LPC54_USART5_BRG (LPC54_FLEXCOMM5_BASE+LPC54_USART_BRG_OFFSET) -#define LPC54_USART5_INTSTAT (LPC54_FLEXCOMM5_BASE+LPC54_USART_INTSTAT_OFFSET) -#define LPC54_USART5_OSR (LPC54_FLEXCOMM5_BASE+LPC54_USART_OSR_OFFSET) -#define LPC54_USART5_FIFOCFG (LPC54_FLEXCOMM5_BASE+LPC54_USART_FIFOCFG_OFFSET) -#define LPC54_USART5_FIFOSTAT (LPC54_FLEXCOMM5_BASE+LPC54_USART_FIFOSTAT_OFFSET) -#define LPC54_USART5_FIFOTRIG (LPC54_FLEXCOMM5_BASE+LPC54_USART_FIFOTRIG_OFFSET) -#define LPC54_USART5_FIFOINTENSET (LPC54_FLEXCOMM5_BASE+LPC54_USART_FIFOINTENSET_OFFSET) -#define LPC54_USART5_FIFOINTENCLR (LPC54_FLEXCOMM5_BASE+LPC54_USART_FIFOINTENCLR_OFFSET) -#define LPC54_USART5_FIFOINTSTAT (LPC54_FLEXCOMM5_BASE+LPC54_USART_FIFOINTSTAT_OFFSET) -#define LPC54_USART5_FIFOWR (LPC54_FLEXCOMM5_BASE+LPC54_USART_FIFOWR_OFFSET) -#define LPC54_USART5_FIFORD (LPC54_FLEXCOMM5_BASE+LPC54_USART_FIFORD_OFFSET) -#define LPC54_USART5_FIFORDNOPOP (LPC54_FLEXCOMM5_BASE+LPC54_USART_FIFORDNOPOP_OFFSET) -#define LPC54_USART5_ID (LPC54_FLEXCOMM5_BASE+LPC54_USART_ID_OFFSET) +#define LPC54_USART5_CFG (LPC54_FLEXCOMM5_BASE + LPC54_USART_CFG_OFFSET) +#define LPC54_USART5_CTL (LPC54_FLEXCOMM5_BASE + LPC54_USART_CTL_OFFSET) +#define LPC54_USART5_STAT (LPC54_FLEXCOMM5_BASE + LPC54_USART_STAT_OFFSET) +#define LPC54_USART5_INTENSET (LPC54_FLEXCOMM5_BASE + LPC54_USART_INTENSET_OFFSET) +#define LPC54_USART5_INTENCLR (LPC54_FLEXCOMM5_BASE + LPC54_USART_INTENCLR_OFFSET) +#define LPC54_USART5_BRG (LPC54_FLEXCOMM5_BASE + LPC54_USART_BRG_OFFSET) +#define LPC54_USART5_INTSTAT (LPC54_FLEXCOMM5_BASE + LPC54_USART_INTSTAT_OFFSET) +#define LPC54_USART5_OSR (LPC54_FLEXCOMM5_BASE + LPC54_USART_OSR_OFFSET) +#define LPC54_USART5_FIFOCFG (LPC54_FLEXCOMM5_BASE + LPC54_USART_FIFOCFG_OFFSET) +#define LPC54_USART5_FIFOSTAT (LPC54_FLEXCOMM5_BASE + LPC54_USART_FIFOSTAT_OFFSET) +#define LPC54_USART5_FIFOTRIG (LPC54_FLEXCOMM5_BASE + LPC54_USART_FIFOTRIG_OFFSET) +#define LPC54_USART5_FIFOINTENSET (LPC54_FLEXCOMM5_BASE + LPC54_USART_FIFOINTENSET_OFFSET) +#define LPC54_USART5_FIFOINTENCLR (LPC54_FLEXCOMM5_BASE + LPC54_USART_FIFOINTENCLR_OFFSET) +#define LPC54_USART5_FIFOINTSTAT (LPC54_FLEXCOMM5_BASE + LPC54_USART_FIFOINTSTAT_OFFSET) +#define LPC54_USART5_FIFOWR (LPC54_FLEXCOMM5_BASE + LPC54_USART_FIFOWR_OFFSET) +#define LPC54_USART5_FIFORD (LPC54_FLEXCOMM5_BASE + LPC54_USART_FIFORD_OFFSET) +#define LPC54_USART5_FIFORDNOPOP (LPC54_FLEXCOMM5_BASE + LPC54_USART_FIFORDNOPOP_OFFSET) +#define LPC54_USART5_ID (LPC54_FLEXCOMM5_BASE + LPC54_USART_ID_OFFSET) -#define LPC54_USART6_CFG (LPC54_FLEXCOMM6_BASE+LPC54_USART_CFG_OFFSET) -#define LPC54_USART6_CTL (LPC54_FLEXCOMM6_BASE+LPC54_USART_CTL_OFFSET) -#define LPC54_USART6_STAT (LPC54_FLEXCOMM6_BASE+LPC54_USART_STAT_OFFSET) -#define LPC54_USART6_INTENSET (LPC54_FLEXCOMM6_BASE+LPC54_USART_INTENSET_OFFSET) -#define LPC54_USART6_INTENCLR (LPC54_FLEXCOMM6_BASE+LPC54_USART_INTENCLR_OFFSET) -#define LPC54_USART6_BRG (LPC54_FLEXCOMM6_BASE+LPC54_USART_BRG_OFFSET) -#define LPC54_USART6_INTSTAT (LPC54_FLEXCOMM6_BASE+LPC54_USART_INTSTAT_OFFSET) -#define LPC54_USART6_OSR (LPC54_FLEXCOMM6_BASE+LPC54_USART_OSR_OFFSET) -#define LPC54_USART6_FIFOCFG (LPC54_FLEXCOMM6_BASE+LPC54_USART_FIFOCFG_OFFSET) -#define LPC54_USART6_FIFOSTAT (LPC54_FLEXCOMM6_BASE+LPC54_USART_FIFOSTAT_OFFSET) -#define LPC54_USART6_FIFOTRIG (LPC54_FLEXCOMM6_BASE+LPC54_USART_FIFOTRIG_OFFSET) -#define LPC54_USART6_FIFOINTENSET (LPC54_FLEXCOMM6_BASE+LPC54_USART_FIFOINTENSET_OFFSET) -#define LPC54_USART6_FIFOINTENCLR (LPC54_FLEXCOMM6_BASE+LPC54_USART_FIFOINTENCLR_OFFSET) -#define LPC54_USART6_FIFOINTSTAT (LPC54_FLEXCOMM6_BASE+LPC54_USART_FIFOINTSTAT_OFFSET) -#define LPC54_USART6_FIFOWR (LPC54_FLEXCOMM6_BASE+LPC54_USART_FIFOWR_OFFSET) -#define LPC54_USART6_FIFORD (LPC54_FLEXCOMM6_BASE+LPC54_USART_FIFORD_OFFSET) -#define LPC54_USART6_FIFORDNOPOP (LPC54_FLEXCOMM6_BASE+LPC54_USART_FIFORDNOPOP_OFFSET) -#define LPC54_USART6_ID (LPC54_FLEXCOMM6_BASE+LPC54_USART_ID_OFFSET) +#define LPC54_USART6_CFG (LPC54_FLEXCOMM6_BASE + LPC54_USART_CFG_OFFSET) +#define LPC54_USART6_CTL (LPC54_FLEXCOMM6_BASE + LPC54_USART_CTL_OFFSET) +#define LPC54_USART6_STAT (LPC54_FLEXCOMM6_BASE + LPC54_USART_STAT_OFFSET) +#define LPC54_USART6_INTENSET (LPC54_FLEXCOMM6_BASE + LPC54_USART_INTENSET_OFFSET) +#define LPC54_USART6_INTENCLR (LPC54_FLEXCOMM6_BASE + LPC54_USART_INTENCLR_OFFSET) +#define LPC54_USART6_BRG (LPC54_FLEXCOMM6_BASE + LPC54_USART_BRG_OFFSET) +#define LPC54_USART6_INTSTAT (LPC54_FLEXCOMM6_BASE + LPC54_USART_INTSTAT_OFFSET) +#define LPC54_USART6_OSR (LPC54_FLEXCOMM6_BASE + LPC54_USART_OSR_OFFSET) +#define LPC54_USART6_FIFOCFG (LPC54_FLEXCOMM6_BASE + LPC54_USART_FIFOCFG_OFFSET) +#define LPC54_USART6_FIFOSTAT (LPC54_FLEXCOMM6_BASE + LPC54_USART_FIFOSTAT_OFFSET) +#define LPC54_USART6_FIFOTRIG (LPC54_FLEXCOMM6_BASE + LPC54_USART_FIFOTRIG_OFFSET) +#define LPC54_USART6_FIFOINTENSET (LPC54_FLEXCOMM6_BASE + LPC54_USART_FIFOINTENSET_OFFSET) +#define LPC54_USART6_FIFOINTENCLR (LPC54_FLEXCOMM6_BASE + LPC54_USART_FIFOINTENCLR_OFFSET) +#define LPC54_USART6_FIFOINTSTAT (LPC54_FLEXCOMM6_BASE + LPC54_USART_FIFOINTSTAT_OFFSET) +#define LPC54_USART6_FIFOWR (LPC54_FLEXCOMM6_BASE + LPC54_USART_FIFOWR_OFFSET) +#define LPC54_USART6_FIFORD (LPC54_FLEXCOMM6_BASE + LPC54_USART_FIFORD_OFFSET) +#define LPC54_USART6_FIFORDNOPOP (LPC54_FLEXCOMM6_BASE + LPC54_USART_FIFORDNOPOP_OFFSET) +#define LPC54_USART6_ID (LPC54_FLEXCOMM6_BASE + LPC54_USART_ID_OFFSET) -#define LPC54_USART7_CFG (LPC54_FLEXCOMM7_BASE+LPC54_USART_CFG_OFFSET) -#define LPC54_USART7_CTL (LPC54_FLEXCOMM7_BASE+LPC54_USART_CTL_OFFSET) -#define LPC54_USART7_STAT (LPC54_FLEXCOMM7_BASE+LPC54_USART_STAT_OFFSET) -#define LPC54_USART7_INTENSET (LPC54_FLEXCOMM7_BASE+LPC54_USART_INTENSET_OFFSET) -#define LPC54_USART7_INTENCLR (LPC54_FLEXCOMM7_BASE+LPC54_USART_INTENCLR_OFFSET) -#define LPC54_USART7_BRG (LPC54_FLEXCOMM7_BASE+LPC54_USART_BRG_OFFSET) -#define LPC54_USART7_INTSTAT (LPC54_FLEXCOMM7_BASE+LPC54_USART_INTSTAT_OFFSET) -#define LPC54_USART7_OSR (LPC54_FLEXCOMM7_BASE+LPC54_USART_OSR_OFFSET) -#define LPC54_USART7_FIFOCFG (LPC54_FLEXCOMM7_BASE+LPC54_USART_FIFOCFG_OFFSET) -#define LPC54_USART7_FIFOSTAT (LPC54_FLEXCOMM7_BASE+LPC54_USART_FIFOSTAT_OFFSET) -#define LPC54_USART7_FIFOTRIG (LPC54_FLEXCOMM7_BASE+LPC54_USART_FIFOTRIG_OFFSET) -#define LPC54_USART7_FIFOINTENSET (LPC54_FLEXCOMM7_BASE+LPC54_USART_FIFOINTENSET_OFFSET) -#define LPC54_USART7_FIFOINTENCLR (LPC54_FLEXCOMM7_BASE+LPC54_USART_FIFOINTENCLR_OFFSET) -#define LPC54_USART7_FIFOINTSTAT (LPC54_FLEXCOMM7_BASE+LPC54_USART_FIFOINTSTAT_OFFSET) -#define LPC54_USART7_FIFOWR (LPC54_FLEXCOMM7_BASE+LPC54_USART_FIFOWR_OFFSET) -#define LPC54_USART7_FIFORD (LPC54_FLEXCOMM7_BASE+LPC54_USART_FIFORD_OFFSET) -#define LPC54_USART7_FIFORDNOPOP (LPC54_FLEXCOMM7_BASE+LPC54_USART_FIFORDNOPOP_OFFSET) -#define LPC54_USART7_ID (LPC54_FLEXCOMM7_BASE+LPC54_USART_ID_OFFSET) +#define LPC54_USART7_CFG (LPC54_FLEXCOMM7_BASE + LPC54_USART_CFG_OFFSET) +#define LPC54_USART7_CTL (LPC54_FLEXCOMM7_BASE + LPC54_USART_CTL_OFFSET) +#define LPC54_USART7_STAT (LPC54_FLEXCOMM7_BASE + LPC54_USART_STAT_OFFSET) +#define LPC54_USART7_INTENSET (LPC54_FLEXCOMM7_BASE + LPC54_USART_INTENSET_OFFSET) +#define LPC54_USART7_INTENCLR (LPC54_FLEXCOMM7_BASE + LPC54_USART_INTENCLR_OFFSET) +#define LPC54_USART7_BRG (LPC54_FLEXCOMM7_BASE + LPC54_USART_BRG_OFFSET) +#define LPC54_USART7_INTSTAT (LPC54_FLEXCOMM7_BASE + LPC54_USART_INTSTAT_OFFSET) +#define LPC54_USART7_OSR (LPC54_FLEXCOMM7_BASE + LPC54_USART_OSR_OFFSET) +#define LPC54_USART7_FIFOCFG (LPC54_FLEXCOMM7_BASE + LPC54_USART_FIFOCFG_OFFSET) +#define LPC54_USART7_FIFOSTAT (LPC54_FLEXCOMM7_BASE + LPC54_USART_FIFOSTAT_OFFSET) +#define LPC54_USART7_FIFOTRIG (LPC54_FLEXCOMM7_BASE + LPC54_USART_FIFOTRIG_OFFSET) +#define LPC54_USART7_FIFOINTENSET (LPC54_FLEXCOMM7_BASE + LPC54_USART_FIFOINTENSET_OFFSET) +#define LPC54_USART7_FIFOINTENCLR (LPC54_FLEXCOMM7_BASE + LPC54_USART_FIFOINTENCLR_OFFSET) +#define LPC54_USART7_FIFOINTSTAT (LPC54_FLEXCOMM7_BASE + LPC54_USART_FIFOINTSTAT_OFFSET) +#define LPC54_USART7_FIFOWR (LPC54_FLEXCOMM7_BASE + LPC54_USART_FIFOWR_OFFSET) +#define LPC54_USART7_FIFORD (LPC54_FLEXCOMM7_BASE + LPC54_USART_FIFORD_OFFSET) +#define LPC54_USART7_FIFORDNOPOP (LPC54_FLEXCOMM7_BASE + LPC54_USART_FIFORDNOPOP_OFFSET) +#define LPC54_USART7_ID (LPC54_FLEXCOMM7_BASE + LPC54_USART_ID_OFFSET) -#define LPC54_USART8_CFG (LPC54_FLEXCOMM8_BASE+LPC54_USART_CFG_OFFSET) -#define LPC54_USART8_CTL (LPC54_FLEXCOMM8_BASE+LPC54_USART_CTL_OFFSET) -#define LPC54_USART8_STAT (LPC54_FLEXCOMM8_BASE+LPC54_USART_STAT_OFFSET) -#define LPC54_USART8_INTENSET (LPC54_FLEXCOMM8_BASE+LPC54_USART_INTENSET_OFFSET) -#define LPC54_USART8_INTENCLR (LPC54_FLEXCOMM8_BASE+LPC54_USART_INTENCLR_OFFSET) -#define LPC54_USART8_BRG (LPC54_FLEXCOMM8_BASE+LPC54_USART_BRG_OFFSET) -#define LPC54_USART8_INTSTAT (LPC54_FLEXCOMM8_BASE+LPC54_USART_INTSTAT_OFFSET) -#define LPC54_USART8_OSR (LPC54_FLEXCOMM8_BASE+LPC54_USART_OSR_OFFSET) -#define LPC54_USART8_FIFOCFG (LPC54_FLEXCOMM8_BASE+LPC54_USART_FIFOCFG_OFFSET) -#define LPC54_USART8_FIFOSTAT (LPC54_FLEXCOMM8_BASE+LPC54_USART_FIFOSTAT_OFFSET) -#define LPC54_USART8_FIFOTRIG (LPC54_FLEXCOMM8_BASE+LPC54_USART_FIFOTRIG_OFFSET) -#define LPC54_USART8_FIFOINTENSET (LPC54_FLEXCOMM8_BASE+LPC54_USART_FIFOINTENSET_OFFSET) -#define LPC54_USART8_FIFOINTENCLR (LPC54_FLEXCOMM8_BASE+LPC54_USART_FIFOINTENCLR_OFFSET) -#define LPC54_USART8_FIFOINTSTAT (LPC54_FLEXCOMM8_BASE+LPC54_USART_FIFOINTSTAT_OFFSET) -#define LPC54_USART8_FIFOWR (LPC54_FLEXCOMM8_BASE+LPC54_USART_FIFOWR_OFFSET) -#define LPC54_USART8_FIFORD (LPC54_FLEXCOMM8_BASE+LPC54_USART_FIFORD_OFFSET) -#define LPC54_USART8_FIFORDNOPOP (LPC54_FLEXCOMM8_BASE+LPC54_USART_FIFORDNOPOP_OFFSET) -#define LPC54_USART8_ID (LPC54_FLEXCOMM8_BASE+LPC54_USART_ID_OFFSET) +#define LPC54_USART8_CFG (LPC54_FLEXCOMM8_BASE + LPC54_USART_CFG_OFFSET) +#define LPC54_USART8_CTL (LPC54_FLEXCOMM8_BASE + LPC54_USART_CTL_OFFSET) +#define LPC54_USART8_STAT (LPC54_FLEXCOMM8_BASE + LPC54_USART_STAT_OFFSET) +#define LPC54_USART8_INTENSET (LPC54_FLEXCOMM8_BASE + LPC54_USART_INTENSET_OFFSET) +#define LPC54_USART8_INTENCLR (LPC54_FLEXCOMM8_BASE + LPC54_USART_INTENCLR_OFFSET) +#define LPC54_USART8_BRG (LPC54_FLEXCOMM8_BASE + LPC54_USART_BRG_OFFSET) +#define LPC54_USART8_INTSTAT (LPC54_FLEXCOMM8_BASE + LPC54_USART_INTSTAT_OFFSET) +#define LPC54_USART8_OSR (LPC54_FLEXCOMM8_BASE + LPC54_USART_OSR_OFFSET) +#define LPC54_USART8_FIFOCFG (LPC54_FLEXCOMM8_BASE + LPC54_USART_FIFOCFG_OFFSET) +#define LPC54_USART8_FIFOSTAT (LPC54_FLEXCOMM8_BASE + LPC54_USART_FIFOSTAT_OFFSET) +#define LPC54_USART8_FIFOTRIG (LPC54_FLEXCOMM8_BASE + LPC54_USART_FIFOTRIG_OFFSET) +#define LPC54_USART8_FIFOINTENSET (LPC54_FLEXCOMM8_BASE + LPC54_USART_FIFOINTENSET_OFFSET) +#define LPC54_USART8_FIFOINTENCLR (LPC54_FLEXCOMM8_BASE + LPC54_USART_FIFOINTENCLR_OFFSET) +#define LPC54_USART8_FIFOINTSTAT (LPC54_FLEXCOMM8_BASE + LPC54_USART_FIFOINTSTAT_OFFSET) +#define LPC54_USART8_FIFOWR (LPC54_FLEXCOMM8_BASE + LPC54_USART_FIFOWR_OFFSET) +#define LPC54_USART8_FIFORD (LPC54_FLEXCOMM8_BASE + LPC54_USART_FIFORD_OFFSET) +#define LPC54_USART8_FIFORDNOPOP (LPC54_FLEXCOMM8_BASE + LPC54_USART_FIFORDNOPOP_OFFSET) +#define LPC54_USART8_ID (LPC54_FLEXCOMM8_BASE + LPC54_USART_ID_OFFSET) -#define LPC54_USART9_CFG (LPC54_FLEXCOMM9_BASE+LPC54_USART_CFG_OFFSET) -#define LPC54_USART9_CTL (LPC54_FLEXCOMM9_BASE+LPC54_USART_CTL_OFFSET) -#define LPC54_USART9_STAT (LPC54_FLEXCOMM9_BASE+LPC54_USART_STAT_OFFSET) -#define LPC54_USART9_INTENSET (LPC54_FLEXCOMM9_BASE+LPC54_USART_INTENSET_OFFSET) -#define LPC54_USART9_INTENCLR (LPC54_FLEXCOMM9_BASE+LPC54_USART_INTENCLR_OFFSET) -#define LPC54_USART9_BRG (LPC54_FLEXCOMM9_BASE+LPC54_USART_BRG_OFFSET) -#define LPC54_USART9_INTSTAT (LPC54_FLEXCOMM9_BASE+LPC54_USART_INTSTAT_OFFSET) -#define LPC54_USART9_OSR (LPC54_FLEXCOMM9_BASE+LPC54_USART_OSR_OFFSET) -#define LPC54_USART9_FIFOCFG (LPC54_FLEXCOMM9_BASE+LPC54_USART_FIFOCFG_OFFSET) -#define LPC54_USART9_FIFOSTAT (LPC54_FLEXCOMM9_BASE+LPC54_USART_FIFOSTAT_OFFSET) -#define LPC54_USART9_FIFOTRIG (LPC54_FLEXCOMM9_BASE+LPC54_USART_FIFOTRIG_OFFSET) -#define LPC54_USART9_FIFOINTENSET (LPC54_FLEXCOMM9_BASE+LPC54_USART_FIFOINTENSET_OFFSET) -#define LPC54_USART9_FIFOINTENCLR (LPC54_FLEXCOMM9_BASE+LPC54_USART_FIFOINTENCLR_OFFSET) -#define LPC54_USART9_FIFOINTSTAT (LPC54_FLEXCOMM9_BASE+LPC54_USART_FIFOINTSTAT_OFFSET) -#define LPC54_USART9_FIFOWR (LPC54_FLEXCOMM9_BASE+LPC54_USART_FIFOWR_OFFSET) -#define LPC54_USART9_FIFORD (LPC54_FLEXCOMM9_BASE+LPC54_USART_FIFORD_OFFSET) -#define LPC54_USART9_FIFORDNOPOP (LPC54_FLEXCOMM9_BASE+LPC54_USART_FIFORDNOPOP_OFFSET) -#define LPC54_USART9_ID (LPC54_FLEXCOMM9_BASE+LPC54_USART_ID_OFFSET) +#define LPC54_USART9_CFG (LPC54_FLEXCOMM9_BASE + LPC54_USART_CFG_OFFSET) +#define LPC54_USART9_CTL (LPC54_FLEXCOMM9_BASE + LPC54_USART_CTL_OFFSET) +#define LPC54_USART9_STAT (LPC54_FLEXCOMM9_BASE + LPC54_USART_STAT_OFFSET) +#define LPC54_USART9_INTENSET (LPC54_FLEXCOMM9_BASE + LPC54_USART_INTENSET_OFFSET) +#define LPC54_USART9_INTENCLR (LPC54_FLEXCOMM9_BASE + LPC54_USART_INTENCLR_OFFSET) +#define LPC54_USART9_BRG (LPC54_FLEXCOMM9_BASE + LPC54_USART_BRG_OFFSET) +#define LPC54_USART9_INTSTAT (LPC54_FLEXCOMM9_BASE + LPC54_USART_INTSTAT_OFFSET) +#define LPC54_USART9_OSR (LPC54_FLEXCOMM9_BASE + LPC54_USART_OSR_OFFSET) +#define LPC54_USART9_FIFOCFG (LPC54_FLEXCOMM9_BASE + LPC54_USART_FIFOCFG_OFFSET) +#define LPC54_USART9_FIFOSTAT (LPC54_FLEXCOMM9_BASE + LPC54_USART_FIFOSTAT_OFFSET) +#define LPC54_USART9_FIFOTRIG (LPC54_FLEXCOMM9_BASE + LPC54_USART_FIFOTRIG_OFFSET) +#define LPC54_USART9_FIFOINTENSET (LPC54_FLEXCOMM9_BASE + LPC54_USART_FIFOINTENSET_OFFSET) +#define LPC54_USART9_FIFOINTENCLR (LPC54_FLEXCOMM9_BASE + LPC54_USART_FIFOINTENCLR_OFFSET) +#define LPC54_USART9_FIFOINTSTAT (LPC54_FLEXCOMM9_BASE + LPC54_USART_FIFOINTSTAT_OFFSET) +#define LPC54_USART9_FIFOWR (LPC54_FLEXCOMM9_BASE + LPC54_USART_FIFOWR_OFFSET) +#define LPC54_USART9_FIFORD (LPC54_FLEXCOMM9_BASE + LPC54_USART_FIFORD_OFFSET) +#define LPC54_USART9_FIFORDNOPOP (LPC54_FLEXCOMM9_BASE + LPC54_USART_FIFORDNOPOP_OFFSET) +#define LPC54_USART9_ID (LPC54_FLEXCOMM9_BASE + LPC54_USART_ID_OFFSET) /* USART Register Bitfield Definitions ***************************************************************/