diff --git a/TODO b/TODO index e3efaa81df6..53030779480 100644 --- a/TODO +++ b/TODO @@ -438,7 +438,7 @@ o pthreads (sched/pthreads) serve as cancellation points. They are, however, simple wrappers around nanosleep which is a true cancellation point. NOTE 02: system() is actually implemented in apps/ as part of NSH. It cannot be - a cancellation point either. + a cancellation point. NOTE 03: sigpause() is a user-space function in the C library and cannot serve as cancellation points. It is, however, a simple wrapper around sigsuspend() which is a true cancellation point. diff --git a/arch/arm/include/kinetis/chip.h b/arch/arm/include/kinetis/chip.h index 2da386c3daa..d7293d30992 100644 --- a/arch/arm/include/kinetis/chip.h +++ b/arch/arm/include/kinetis/chip.h @@ -43,6 +43,8 @@ #include #include +#include +#include /************************************************************************************ * Pre-processor Definitions diff --git a/arch/arm/include/kinetis/kinetis_mcg.h b/arch/arm/include/kinetis/kinetis_mcg.h index 7b46c686322..bca6b188836 100644 --- a/arch/arm/include/kinetis/kinetis_mcg.h +++ b/arch/arm/include/kinetis/kinetis_mcg.h @@ -76,7 +76,7 @@ * KINETIS_MCG_HAS_PLL_INTERNAL_MODE - Has PEI mode or PBI mode * KINETIS_MCG_HAS_RESET_IS_BLPI - Has Reset clock mode is BLPI * - * MCD Register Configuration + * MCG Register Configuration * * KINETIS_MCG_HAS_C1 - SoC has C1 Register * KINETIS_MCG_HAS_C1_IREFS - SoC has C1[IREFS] @@ -289,7 +289,7 @@ # undef KINETIS_MCG_HAS_PLL_INTERNAL_MODE /* Has PEI mode or PBI mode */ # undef KINETIS_MCG_HAS_RESET_IS_BLPI /* Has Reset clock mode is BLPI */ -/* MCD Register Configuration */ +/* MCG Register Configuration */ # define KINETIS_MCG_HAS_C1 1 /* SoC has C1 Register */ # define KINETIS_MCG_HAS_C1_IREFS 1 /* SoC has C1[IREFS] */ @@ -371,7 +371,7 @@ # undef KINETIS_MCG_HAS_PLL_INTERNAL_MODE /* Has PEI mode or PBI mode */ # undef KINETIS_MCG_HAS_RESET_IS_BLPI /* Has Reset clock mode is BLPI */ -/* MCD Register Configuration */ +/* MCG Register Configuration */ # define KINETIS_MCG_HAS_C1 1 /* SoC has C1 Register */ # define KINETIS_MCG_HAS_C1_IREFS 1 /* SoC has C1[IREFS] */ @@ -448,7 +448,7 @@ /* Verified to Document Number: Document Number: K66P144M180SF5RMV2 Rev. 2, May 2015 */ -# define KINETIS_MCG_VERSION KINETIS_K_MCG_VERSION_06 +# define KINETIS_MCG_VERSION KINETIS_MCG_VERSION_06 /* MCG Configuration Parameters */ @@ -463,7 +463,7 @@ # undef KINETIS_MCG_HAS_PLL_INTERNAL_MODE /* Has PEI mode or PBI mode */ # undef KINETIS_MCG_HAS_RESET_IS_BLPI /* Has Reset clock mode is BLPI */ -/* MCD Register Configuration */ +/* MCG Register Configuration */ # define KINETIS_MCG_HAS_C1 1 /* SoC has C1 Register */ # define KINETIS_MCG_HAS_C1_IREFS 1 /* SoC has C1[IREFS] */ @@ -544,7 +544,7 @@ # undef KINETIS_MCG_HAS_PLL_INTERNAL_MODE /* Has PEI mode or PBI mode */ # undef KINETIS_MCG_HAS_RESET_IS_BLPI /* Has Reset clock mode is BLPI */ -/* MCD Register Configuration */ +/* MCG Register Configuration */ # define KINETIS_MCG_HAS_C1 1 /* SoC has C1 Register */ # define KINETIS_MCG_HAS_C1_IREFS 1 /* SoC has C1[IREFS] */ diff --git a/arch/arm/include/kinetis/kinetis_pmc.h b/arch/arm/include/kinetis/kinetis_pmc.h new file mode 100644 index 00000000000..03bc8958426 --- /dev/null +++ b/arch/arm/include/kinetis/kinetis_pmc.h @@ -0,0 +1,324 @@ +/************************************************************************************ + * arch/arm/include/kinetis/kinetis_pmc.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_KINETIS_KINETIS_PMC_H +#define __ARCH_ARM_INCLUDE_KINETIS_KINETIS_PMC_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Note: It is envisioned that in the long term as a chip is added. The author of + * the new chip definitions will either find the exact configuration in an existing + * chip define and add the new chip to it Or add the PMC feature configuration + * #defines to the chip ifdef list below. In either case the author should mark + * it as "Verified to Document Number:" taken from the reference manual. + * + * To maintain backward compatibility to the version of NuttX prior to + * 2/22/2017, the catch all KINETIS_PMC_VERSION_UKN configuration is assigned + * to all the chips that did not have any conditional compilation based on + * KINETIS_K64 or KINETIS_K66. This is a "No worse" than the original code solution. + * N.B. Each original chip "if"definitions have been left intact so that the + * complete legacy definitions prior to 2/22/2017 may be filled in completely when + * vetted. + */ + +/* PMC Register Configuration + * + * KINETIS_PMC_HAS_REGSC - SoC has REGSC Register + * KINETIS_PMC_HAS_REGSC_ACKISO - SoC has REGSC[ACKISO] + * KINETIS_PMC_HAS_REGSC_VLPRS - SoC has REGSC[VLPRS] + * KINETIS_PMC_HAS_REGSC_VLPO - SoC has REGSC[VLPO] + * KINETIS_PMC_HAS_REGSC_REGFPM - SoC has REGSC[REGFPM] + * KINETIS_PMC_HAS_REGSC_BGEN - SoC has REGSC[BGEN] + * KINETIS_PMC_HAS_REGSC_TRAMPO - SoC has REGSC[TRAMPO] + * KINETIS_PMC_HAS_REGSC_REGONS - SoC has REGSC[REGONS] + */ + +/* Describe the version of the PMC + * + * These defines are not related to any NXP reference but are merely + * a way to label the versions we are using + */ + +#define KINETIS_PMC_VERSION_UKN -1 /* What was in nuttx prior to 2/22/2017 */ +#define KINETIS_PMC_VERSION_01 1 /* Verified Document Number: K60P144M150SF3RM Rev. 3, November 2014 */ +#define KINETIS_PMC_VERSION_04 4 /* Verified to Document Numbers: + * K20P64M72SF1RM Rev. 1.1, Dec 2012 + * K64P144M120SF5RM Rev. 2, January 2014 + * K66P144M180SF5RMV2 Rev. 2, May 2015 */ + +/* MK20DX/DN---VLH5 + * + * ------------- ------ --- ------- ------ ------- ------ ----- ---- + * PART NUMBER CPU PIN PACKAGE TOTAL PROGRAM EEPROM SRAM GPIO + * FREQ CNT FLASH FLASH + * ------------- ------ --- ------- ------ ------- ------ ----- ---- + * MK20DN32VLH5 50 MHz 64 LQFP 32 KB 32 KB — 8 KB 40 + * MK20DX32VLH5 50 MHz 64 LQFP 64 KB 32 KB 2 KB 8 KB 40 + * MK20DN64VLH5 50 MHz 64 LQFP 64 KB 64 KB — 16 KB 40 + * MK20DX64VLH5 50 MHz 64 LQFP 96 KB 64 KB 2 KB 16 KB 40 + * MK20DN128VLH5 50 MHz 64 LQFP 128 KB 128 KB — 16 KB 40 + * MK20DX128VLH5 50 MHz 64 LQFP 160 KB 128 KB 2 KB 16 KB 40 + */ + +#if defined(CONFIG_ARCH_CHIP_MK20DN32VLH5) || \ + defined(CONFIG_ARCH_CHIP_MK20DX32VLH5) || \ + defined(CONFIG_ARCH_CHIP_MK20DN64VLH5) || \ + defined(CONFIG_ARCH_CHIP_MK20DX64VLH5) || \ + defined(CONFIG_ARCH_CHIP_MK20DN128VLH5) || \ + defined(CONFIG_ARCH_CHIP_MK20DX128VLH5) + +# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN + +/* MK20DX---VLH7 + * + * ------------- ------ --- ------- ------ ------- ------ ----- ---- + * PART NUMBER CPU PIN PACKAGE TOTAL PROGRAM EEPROM SRAM GPIO + * FREQ CNT FLASH FLASH + * ------------- ------ --- ------- ------ ------- ------ ----- ---- + * MK20DX64VLH7 72 MHz 64 LQFP 96 KB 64 KB 2 KB 16 KB 40 + * MK20DX128VLH7 72 MHz 64 LQFP 160 KB 128 KB 2 KB 32 KB 40 + * MK20DX256VLH7 72 MHz 64 LQFP 288 KB 256 KB 2 KB 64 KB 40 + * ------------- ------ --- ------- ------ ------- ------ ----- ---- + */ + +#elif defined(CONFIG_ARCH_CHIP_MK20DX64VLH7) || defined(CONFIG_ARCH_CHIP_MK20DX128VLH7) || \ + defined(CONFIG_ARCH_CHIP_MK20DX256VLH7) + +/* Verified to Document Number: K20P64M72SF1RM Rev. 1.1, Dec 2012 */ + +# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_04 + +/* PMC Register Configuration */ + +# define KINETIS_PMC_HAS_REGSC 1 /* SoC has REGSC Register */ +# define KINETIS_PMC_HAS_REGSC_ACKISO 1 /* SoC has REGSC[ACKISO] */ +# undef KINETIS_PMC_HAS_REGSC_VLPRS /* SoC has REGSC[VLPRS] */ +# undef KINETIS_PMC_HAS_REGSC_VLPO /* SoC has REGSC[VLPO] */ +# undef KINETIS_PMC_HAS_REGSC_REGFPM /* SoC has REGSC[REGFPM] */ +# define KINETIS_PMC_HAS_REGSC_BGEN 1 /* SoC has REGSC[BGEN] */ +# undef KINETIS_PMC_HAS_REGSC_TRAMPO /* SoC has REGSC[TRAMPO] */ +# define KINETIS_PMC_HAS_REGSC_REGONS 1 /* SoC has REGSC[REGONS] */ + +#elif defined(CONFIG_ARCH_CHIP_MK40X64VFX50) || defined(CONFIG_ARCH_CHIP_MK40X64VLH50) || \ + defined(CONFIG_ARCH_CHIP_MK40X64VLK50) || defined(CONFIG_ARCH_CHIP_MK40X64VMB50) + +# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK40X128VFX50) || defined(CONFIG_ARCH_CHIP_MK40X128VLH50) || \ + defined(CONFIG_ARCH_CHIP_MK40X128VLK50) || defined(CONFIG_ARCH_CHIP_MK40X128VMB50) || \ + defined(CONFIG_ARCH_CHIP_MK40X128VLL50) || defined(CONFIG_ARCH_CHIP_MK40X128VML50) || \ + defined(CONFIG_ARCH_CHIP_MK40X128VFX72) || defined(CONFIG_ARCH_CHIP_MK40X128VLH72) || \ + defined(CONFIG_ARCH_CHIP_MK40X128VLK72) || defined(CONFIG_ARCH_CHIP_MK40X128VMB72) || \ + defined(CONFIG_ARCH_CHIP_MK40X128VLL72) || defined(CONFIG_ARCH_CHIP_MK40X128VML72) + +# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK40X256VLK72) || defined(CONFIG_ARCH_CHIP_MK40X256VMB72) || \ + defined(CONFIG_ARCH_CHIP_MK40X256VLL72) || defined(CONFIG_ARCH_CHIP_MK40X256VML72) + +# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK40X128VLQ100) || defined(CONFIG_ARCH_CHIP_MK40X128VMD100) + +# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK40X256VLQ100) || defined(CONFIG_ARCH_CHIP_MK40X256VMD100) + +# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK40N512VLK100) || defined(CONFIG_ARCH_CHIP_MK40N512VMB100) || \ + defined(CONFIG_ARCH_CHIP_MK40N512VLL100) || defined(CONFIG_ARCH_CHIP_MK40N512VML100) || \ + defined(CONFIG_ARCH_CHIP_MK40N512VLQ100) || defined(CONFIG_ARCH_CHIP_MK40N512VMD100) + +# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK60N256VLL100) + +# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK60X256VLL100) + +# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK60N512VLL100) + +# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK60N256VML100) + +# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK60X256VML100) + +# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK60N512VML100) + +# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK60N256VLQ100) + +# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK60X256VLQ100) + +# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK60N512VLQ100) + +# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK60N256VMD100) + +# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK60X256VMD100) + +# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK60N512VMD100) + +# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK60FN1M0VLQ12) + +/* Verified to Document Number: K60P144M100SF2V2RM Rev. 2 Jun 2012 */ + +# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_01 + +/* PMC Register Configuration */ + +# define KINETIS_PMC_HAS_REGSC 1 /* SoC has REGSC Register */ +# define KINETIS_PMC_HAS_REGSC_ACKISO 1 /* SoC has REGSC[ACKISO] */ +# undef KINETIS_PMC_HAS_REGSC_VLPRS /* SoC has REGSC[VLPRS] */ +# undef KINETIS_PMC_HAS_REGSC_VLPO /* SoC has REGSC[VLPO] */ +# undef KINETIS_PMC_HAS_REGSC_REGFPM /* SoC has REGSC[REGFPM] */ +# undef KINETIS_PMC_HAS_REGSC_BGEN /* SoC has REGSC[BGEN] */ +# undef KINETIS_PMC_HAS_REGSC_TRAMPO /* SoC has REGSC[TRAMPO] */ +# define KINETIS_PMC_HAS_REGSC_REGONS 1 /* SoC has REGSC[REGONS] */ + +#elif defined(CONFIG_ARCH_CHIP_MK64FN1M0VLL12) || defined(CONFIG_ARCH_CHIP_MK64FX512VLL12) || \ + defined(CONFIG_ARCH_CHIP_MK64FX512VDC12) || defined(CONFIG_ARCH_CHIP_MK64FN1M0VDC12) || \ + defined(CONFIG_ARCH_CHIP_MK64FX512VLQ12) || defined(CONFIG_ARCH_CHIP_MK64FN1M0VLQ12) || \ + defined(CONFIG_ARCH_CHIP_MK64FX512VMD12) || defined(CONFIG_ARCH_CHIP_MK64FN1M0VMD12) + +/* Verified to Document Number: K64P144M120SF5RM Rev. 2, January 2014 */ + +# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_04 + +/* PMC Register Configuration */ + +# define KINETIS_PMC_HAS_REGSC 1 /* SoC has REGSC Register */ +# define KINETIS_PMC_HAS_REGSC_ACKISO 1 /* SoC has REGSC[ACKISO] */ +# undef KINETIS_PMC_HAS_REGSC_VLPRS /* SoC has REGSC[VLPRS] */ +# undef KINETIS_PMC_HAS_REGSC_VLPO /* SoC has REGSC[VLPO] */ +# undef KINETIS_PMC_HAS_REGSC_REGFPM /* SoC has REGSC[REGFPM] */ +# define KINETIS_PMC_HAS_REGSC_BGEN 1 /* SoC has REGSC[BGEN] */ +# undef KINETIS_PMC_HAS_REGSC_TRAMPO /* SoC has REGSC[TRAMPO] */ +# define KINETIS_PMC_HAS_REGSC_REGONS 1 /* SoC has REGSC[REGONS] */ + +/* MK66F N/X 1M0/2M0 V MD/LQ 18 + * + * --------------- ------- --- ------- ------- ------ ------ ------ ----- + * PART NUMBER CPU PIN PACKAGE TOTAL PROGRAM EEPROM SRAM GPIO + * FREQ CNT FLASH FLASH + * --------------- ------- --- ------- ------- ------ ------ ------ ----- + * MK66FN2M0VMD18 180 MHz 144 MAPBGA 2 MB — — KB 260 KB 100 + * MK66FX1M0VMD18 180 MHz 144 MAPBGA 1.25 MB 1 MB 4 KB 256 KB 100 + * MK66FN2M0VLQ18 180 MHz 144 LQFP 2 MB — — KB 260 KB 100 + * MK66FX1M0VLQ18 180 MHz 144 LQFP 1.25 MB 1 MB 4 KB 256 KB 100 + */ + +#elif defined(CONFIG_ARCH_CHIP_MK66FN2M0VMD18) || defined(CONFIG_ARCH_CHIP_MK66FX1M0VMD18) || \ + defined(CONFIG_ARCH_CHIP_MK66FN2M0VLQ18) || defined(CONFIG_ARCH_CHIP_MK66FX1M0VLQ18) + +/* Verified to Document Number: Document Number: K66P144M180SF5RMV2 Rev. 2, May 2015 */ + +# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_04 + +/* PMC Register Configuration */ + +# define KINETIS_PMC_HAS_REGSC 1 /* SoC has REGSC Register */ +# define KINETIS_PMC_HAS_REGSC_ACKISO 1 /* SoC has REGSC[ACKISO] */ +# undef KINETIS_PMC_HAS_REGSC_VLPRS /* SoC has REGSC[VLPRS] */ +# undef KINETIS_PMC_HAS_REGSC_VLPO /* SoC has REGSC[VLPO] */ +# undef KINETIS_PMC_HAS_REGSC_REGFPM /* SoC has REGSC[REGFPM] */ +# define KINETIS_PMC_HAS_REGSC_BGEN 1 /* SoC has REGSC[BGEN] */ +# undef KINETIS_PMC_HAS_REGSC_TRAMPO /* SoC has REGSC[TRAMPO] */ +# define KINETIS_PMC_HAS_REGSC_REGONS 1 /* SoC has REGSC[REGONS] */ + +#else +# error "Unsupported Kinetis chip" +#endif + +/* Use the catch all configuration for the PMC based on the implementations in nuttx prior 2/3/2017 */ + +#if KINETIS_PMC_VERSION == KINETIS_PMC_VERSION_UKN + +/* PMC Register Configuration */ + +# define KINETIS_PMC_HAS_REGSC 1 /* SoC has REGSC Register */ +# undef KINETIS_PMC_HAS_REGSC_ACKISO /* SoC has REGSC[ACKISO] */ +# define KINETIS_PMC_HAS_REGSC_VLPRS 1 /* SoC has REGSC[VLPRS] */ +# undef KINETIS_PMC_HAS_REGSC_VLPO /* SoC has REGSC[VLPO] */ +# undef KINETIS_PMC_HAS_REGSC_REGFPM /* SoC has REGSC[REGFPM] */ +# undef KINETIS_PMC_HAS_REGSC_BGEN /* SoC has REGSC[BGEN] */ +# define KINETIS_PMC_HAS_REGSC_TRAMPO 1 /* SoC has REGSC[TRAMPO] */ +# define KINETIS_PMC_HAS_REGSC_REGONS 1 /* SoC has REGSC[REGONS] */ + +#endif + +#if !defined(KINETIS_PMC_VERSION) +# error "No KINETIS_PMC_VERSION defined!" +#endif + +#if defined(KINETIS_PMC_HAS_C5_PRDIV) +# define KINETIS_PMC_C5_PRDIV_MASK ((1 << (KINETIS_PMC_C5_PRDIV_BITS))-1) +#endif + +#if defined(KINETIS_PMC_HAS_C7_OSCSEL) +# define KINETIS_PMC_C7_OSCSEL_MASK ((1 << (KINETIS_PMC_C7_OSCSEL_BITS))-1) +#endif + +#endif /* __ARCH_ARM_INCLUDE_KINETIS_KINETIS_PMC_H */ diff --git a/arch/arm/include/kinetis/kinetis_sim.h b/arch/arm/include/kinetis/kinetis_sim.h new file mode 100644 index 00000000000..224e8b0d787 --- /dev/null +++ b/arch/arm/include/kinetis/kinetis_sim.h @@ -0,0 +1,1322 @@ +/************************************************************************************ + * arch/arm/include/kinetis/kinetis_sim.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_KINETIS_KINETIS_SIM_H +#define __ARCH_ARM_INCLUDE_KINETIS_KINETIS_SIM_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Note: It is envisioned that in the long term as a chip is added. The author of + * the new chip definitions will either find the exact configuration in an existing + * chip define and add the new chip to it Or add the SIM feature configuration + * #defines to the chip ifdef list below. In either case the author should mark + * it as "Verified to Document Number:" taken from the reference manual. + * + * To maintain backward compatibility to the version of NuttX prior to + * 2/16/2017, the catch all KINETIS_SIM_VERSION_UKN configuration is assigned + * to all the chips that did not have any conditional compilation based on + * KINETIS_K64 or KINETIS_K66. This is a "No worse" than the original code solution. + * N.B. Each original chip "if"definitions have been left intact so that the + * complete legacy definitions prior to 2/16/2017 may be filled in completely when + * vetted. + */ + +/* SIM Register Configuration + * + * KINETIS_SIM_HAS_SOPT1 - SoC has SOPT1 Register + * KINETIS_SIM_HAS_SOPT1_OSC32KOUT - SoC has SOPT1[OSC32KOUT] + * KINETIS_SIM_HAS_SOPT1_OSC32KSEL - SoC has SOPT1[OSC32KSEL] + * KINETIS_SIM_HAS_SOPT1_OSC32KSEL_BITS - SoC has n bits SOPT1[OSC32KSEL] + * KINETIS_SIM_HAS_SOPT1_RAMSIZE - SoC has SOPT1[RAMSIZE] + * KINETIS_SIM_HAS_SOPT1_USBREGEN - SoC has SOPT1[USBREGEN] + * KINETIS_SIM_HAS_SOPT1_USBSSTBY - SoC has SOPT1[USBSSTBY] + * KINETIS_SIM_HAS_SOPT1_USBVSTBY - SoC has SOPT1[USBVSTBY] + * KINETIS_SIM_HAS_SOPT1CFG - SoC has SOPT1CFG Register + * KINETIS_SIM_HAS_SOPT1CFG_URWE - SoC has SOPT1CFG[URWE] + * KINETIS_SIM_HAS_SOPT1CFG_USSWE - SoC has SOPT1CFG[USSWE] + * KINETIS_SIM_HAS_SOPT1CFG_UVSWE - SoC has SOPT1CFG[UVSWE] + * KINETIS_SIM_HAS_USBPHYCTL - SoC has USBPHYCTL Register + * KINETIS_SIM_HAS_USBPHYCTL_USB3VOUTTRG - SoC has USBPHYCTL[USB3VOUTTRG] + * KINETIS_SIM_HAS_USBPHYCTL_USBDISILIM - SoC has USBPHYCTL[USBDISILIM] + * KINETIS_SIM_HAS_USBPHYCTL_USBVREGPD - SoC has USBPHYCTL[USBVREGPD] + * KINETIS_SIM_HAS_USBPHYCTL_USBVREGSEL - SoC has USBPHYCTL[USBVREGSEL] + * KINETIS_SIM_HAS_SOPT2 - SoC has SOPT2 Register + * KINETIS_SIM_HAS_SOPT2_CMTUARTPAD - SoC has SOPT2[CMTUARTPAD] + * KINETIS_SIM_HAS_SOPT2_FBSL - SoC has SOPT2[FBSL] + * KINETIS_SIM_HAS_SOPT2_FLEXIOSRC - SoC has SOPT2[FLEXIOSRC] + * KINETIS_SIM_HAS_SOPT2_LPUARTSRC - SoC has SOPT2[LPUARTSRC] + * KINETIS_SIM_HAS_SOPT2_PLLFLLSEL - SoC has SOPT2[PLLFLLSEL] + * KINETIS_SIM_HAS_SOPT2_PLLFLLSEL_BITS - SoC has n bits SOPT2[PLLFLLSEL] + * KINETIS_SIM_HAS_SOPT2_PTD7PAD - SoC has SOPT2[PTD7PAD] + * KINETIS_SIM_HAS_SOPT2_RMIISRC - SoC has SOPT2[RMIISRC] + * KINETIS_SIM_HAS_SOPT2_RTCCLKOUTSEL - SoC has SOPT2[RTCCLKOUTSEL] + * KINETIS_SIM_HAS_SOPT2_CLKOUTSEL - SoC has SOPT2[CLKOUTSEL] + * KINETIS_SIM_HAS_SOPT2_SDHCSRC - SoC has SOPT2[SDHCSRC] + * KINETIS_SIM_HAS_SOPT2_NFCSRC - SoC has SOPT2[NFCSRC] + * KINETIS_SIM_HAS_SOPT2_I2SSRC - SoC has SOPT2[I2SSRC] + * KINETIS_SIM_HAS_SOPT2_TIMESRC - SoC has SOPT2[TIMESRC] + * KINETIS_SIM_HAS_SOPT2_TPMSRC - SoC has SOPT2[TPMSRC] + * KINETIS_SIM_HAS_SOPT2_USBFSRC - SoC has SOPT2[USBFSRC] + * KINETIS_SIM_HAS_SOPT2_TRACECLKSEL - SoC has SOPT2[TRACECLKSEL] + * KINETIS_SIM_HAS_SOPT2_USBREGEN - SoC has SOPT2[USBREGEN] + * KINETIS_SIM_HAS_SOPT2_USBSLSRC - SoC has SOPT2[USBSLSRC] + * KINETIS_SIM_HAS_SOPT2_USBHSRC - SoC has SOPT2[USBHSRC] + * KINETIS_SIM_HAS_SOPT2_USBSRC - SoC has SOPT2[USBSRC] + * KINETIS_SIM_HAS_SOPT2_MCGCLKSEL - SoC has SOPT2[MCGCLKSEL] + * KINETIS_SIM_HAS_SOPT4 - SoC has SOPT4 Register + * KINETIS_SIM_HAS_SOPT4_FTM0FLT0 - SoC has SOPT4[FTM0FLT0] + * KINETIS_SIM_HAS_SOPT4_FTM0FLT1 - SoC has SOPT4[FTM0FLT1] + * KINETIS_SIM_HAS_SOPT4_FTM0FLT2 - SoC has SOPT4[FTM0FLT2] + * KINETIS_SIM_HAS_SOPT4_FTM0FLT3 - SoC has SOPT4[FTM0FLT3] + * KINETIS_SIM_HAS_SOPT4_FTM0TRG0SRC - SoC has SOPT4[FTM0TRG0SRC] + * KINETIS_SIM_HAS_SOPT4_FTM0TRG1SRC - SoC has SOPT4[FTM0TRG1SRC] + * KINETIS_SIM_HAS_SOPT4_FTM1CH0SRC - SoC has SOPT4[FTM1CH0SRC] 1, 3 if SOF + * KINETIS_SIM_HAS_SOPT4_FTM1FLT0 - SoC has SOPT4[FTM1FLT0] + * KINETIS_SIM_HAS_SOPT4_FTM1FLT1 - SoC has SOPT4[FTM1FLT1] + * KINETIS_SIM_HAS_SOPT4_FTM1FLT2 - SoC has SOPT4[FTM1FLT2] + * KINETIS_SIM_HAS_SOPT4_FTM1FLT3 - SoC has SOPT4[FTM1FLT3] + * KINETIS_SIM_HAS_SOPT4_FTM2CH0SRC - SoC has SOPT4[FTM2CH0SRC] + * KINETIS_SIM_HAS_SOPT4_FTM2CH1SRC - SoC has SOPT4[FTM2CH1SRC] + * KINETIS_SIM_HAS_SOPT4_FTM2FLT0 - SoC has SOPT4[FTM2FLT0] + * KINETIS_SIM_HAS_SOPT4_FTM2FLT1 - SoC has SOPT4[FTM2FLT1] + * KINETIS_SIM_HAS_SOPT4_FTM2FLT2 - SoC has SOPT4[FTM2FLT2] + * KINETIS_SIM_HAS_SOPT4_FTM2FLT3 - SoC has SOPT4[FTM2FLT3] + * KINETIS_SIM_HAS_SOPT4_FTM3CH0SRC - SoC has SOPT4[FTM3CH0SRC] + * KINETIS_SIM_HAS_SOPT4_FTM3FLT0 - SoC has SOPT4[FTM3FLT0] + * KINETIS_SIM_HAS_SOPT4_FTM3FLT1 - SoC has SOPT4[FTM3FLT1] + * KINETIS_SIM_HAS_SOPT4_FTM3FLT2 - SoC has SOPT4[FTM3FLT2] + * KINETIS_SIM_HAS_SOPT4_FTM3FLT3 - SoC has SOPT4[FTM3FLT3] + * KINETIS_SIM_HAS_SOPT4_FTM3TRG0SRC - SoC has SOPT4[FTM3TRG0SRC] + * KINETIS_SIM_HAS_SOPT4_FTM3TRG1SRC - SoC has SOPT4[FTM3TRG1SRC] + * KINETIS_SIM_HAS_SOPT4_TPM0CLKSEL - SoC has SOPT4[TPM0CLKSEL] + * KINETIS_SIM_HAS_SOPT4_TPM1CH0SRC - SoC has SOPT4[TPM1CH0SRC] + * KINETIS_SIM_HAS_SOPT4_TPM1CLKSEL - SoC has SOPT4[TPM1CLKSEL] + * KINETIS_SIM_HAS_SOPT4_TPM2CH0SRC - SoC has SOPT4[TPM2CH0SRC] + * KINETIS_SIM_HAS_SOPT4_TPM2CLKSEL - SoC has SOPT4[TPM2CLKSEL] + * KINETIS_SIM_HAS_SOPT5 - SoC has SOPT5 Register + * KINETIS_SIM_HAS_SOPT5_LPUART0RXSRC - SoC has SOPT5[LPUART0RXSRC] + * KINETIS_SIM_HAS_SOPT5_LPUART0TXSRC - SoC has SOPT5[LPUART0TXSRC] + * KINETIS_SIM_HAS_SOPT6 - SoC has SOPT6 Register + * KINETIS_SIM_HAS_SOPT6_MCC - SoC has SOPT6[MCC] + * KINETIS_SIM_HAS_SOPT6_PCR - SoC has SOPT6[PCR] + * KINETIS_SIM_HAS_SOPT6_RSTFLTSEL - SoC has SOPT6[RSTFLTSEL] + * KINETIS_SIM_HAS_SOPT6_RSTFLTEN - SoC has SOPT6[RSTFLTEN] + * KINETIS_SIM_HAS_SOPT7 - SoC has SOPT7 Register + * KINETIS_SIM_HAS_SOPT7_ADC0ALTTRGSEL - SoC has SOPT7[ADC0ALTTRGSEL] + * KINETIS_SIM_HAS_SOPT7_ADC1ALTTRGSEL - SoC has SOPT7[ADC1ALTTRGSEL] + * KINETIS_SIM_HAS_SOPT7_ADC0PRETRGSEL - SoC has SOPT7[ADC0PRETRGSEL] + * KINETIS_SIM_HAS_SOPT7_ADC1PRETRGSEL - SoC has SOPT7[ADC1PRETRGSEL] + * KINETIS_SIM_HAS_SOPT7_ADC2PRETRGSEL - SoC has SOPT7[ADC2PRETRGSEL] + * KINETIS_SIM_HAS_SOPT7_ADC3PRETRGSEL - SoC has SOPT7[ADC3PRETRGSEL] + * KINETIS_SIM_HAS_SOPT7_ADC0TRGSEL - SoC has n SOPT7[ADC0TRGSEL] + * KINETIS_SIM_HAS_SOPT7_ADC1TRGSEL - SoC has n SOPT7[ADC1TRGSEL] + * KINETIS_SIM_HAS_SOPT7_ADC2TRGSEL - SoC has n SOPT7[ADC2TRGSEL] + * KINETIS_SIM_HAS_SOPT7_ADC3TRGSEL - SoC has n SOPT7[ADC3TRGSEL] + * KINETIS_SIM_SOPT7_ADC0ALTTRGEN - SoC has ADC0 alternate trigger enable + * KINETIS_SIM_SOPT7_ADC1ALTTRGEN - SoC has ADC1 alternate trigger enable + * KINETIS_SIM_SOPT7_ADC2ALTTRGEN - SoC has ADC2 alternate trigger enable + * KINETIS_SIM_SOPT7_ADC3ALTTRGEN - SoC has ADC3 alternate trigger enable + * KINETIS_SIM_HAS_SOPT8 - SoC has SOPT8 Register + * KINETIS_SIM_HAS_SOPT8_FTM0SYNCBIT - SoC has SOPT8[FTM0SYNCBIT] + * KINETIS_SIM_HAS_SOPT8_FTM1SYNCBIT - SoC has SOPT8[FTM1SYNCBIT] + * KINETIS_SIM_HAS_SOPT8_FTM2SYNCBIT - SoC has SOPT8[FTM2SYNCBIT] + * KINETIS_SIM_HAS_SOPT8_FTM3SYNCBIT - SoC has SOPT8[FTM3SYNCBIT] + * KINETIS_SIM_HAS_SOPT8_FTM0OCH0SRC - SoC has SOPT8[FTM0OCH0SRC] + * KINETIS_SIM_HAS_SOPT8_FTM0OCH1SRC - SoC has SOPT8[FTM0OCH1SRC] + * KINETIS_SIM_HAS_SOPT8_FTM0OCH2SRC - SoC has SOPT8[FTM0OCH2SRC] + * KINETIS_SIM_HAS_SOPT8_FTM0OCH3SRC - SoC has SOPT8[FTM0OCH3SRC] + * KINETIS_SIM_HAS_SOPT8_FTM0OCH4SRC - SoC has SOPT8[FTM0OCH4SRC] + * KINETIS_SIM_HAS_SOPT8_FTM0OCH5SRC - SoC has SOPT8[FTM0OCH5SRC] + * KINETIS_SIM_HAS_SOPT8_FTM0OCH6SRC - SoC has SOPT8[FTM0OCH6SRC] + * KINETIS_SIM_HAS_SOPT8_FTM0OCH7SRC - SoC has SOPT8[FTM0OCH7SRC] + * KINETIS_SIM_HAS_SOPT8_FTM3OCH0SRC - SoC has SOPT8[FTM3OCH0SRC] + * KINETIS_SIM_HAS_SOPT8_FTM3OCH1SRC - SoC has SOPT8[FTM3OCH1SRC] + * KINETIS_SIM_HAS_SOPT8_FTM3OCH2SRC - SoC has SOPT8[FTM3OCH2SRC] + * KINETIS_SIM_HAS_SOPT8_FTM3OCH3SRC - SoC has SOPT8[FTM3OCH3SRC] + * KINETIS_SIM_HAS_SOPT8_FTM3OCH4SRC - SoC has SOPT8[FTM3OCH4SRC] + * KINETIS_SIM_HAS_SOPT8_FTM3OCH5SRC - SoC has SOPT8[FTM3OCH5SRC] + * KINETIS_SIM_HAS_SOPT8_FTM3OCH6SRC - SoC has SOPT8[FTM3OCH6SRC] + * KINETIS_SIM_HAS_SOPT8_FTM3OCH7SRC - SoC has SOPT8[FTM3OCH7SRC] + * KINETIS_SIM_HAS_SOPT9 - SoC has SOPT9 Register + * KINETIS_SIM_HAS_SOPT9_TPM1CH0SRC - SoC has SOPT9[TPM1CH0SRC] + * KINETIS_SIM_HAS_SOPT9_TPM2CH0SRC - SoC has SOPT9[TPM2CH0SRC] + * KINETIS_SIM_HAS_SOPT9_TPM1CLKSEL - SoC has SOPT9[TPM1CLKSEL] + * KINETIS_SIM_HAS_SOPT9_TPM2CLKSEL - SoC has SOPT9[TPM2CLKSEL] + * KINETIS_SIM_HAS_SDID - SoC has SDID Register + * KINETIS_SIM_HAS_SDID_DIEID - SoC has SDID[DIEID] + * KINETIS_SIM_HAS_SDID_FAMID - SoC has SDID[FAMID] + * KINETIS_SIM_HAS_SDID_FAMILYID - SoC has SDID[FAMILYID] + * KINETIS_SIM_HAS_SDID_SERIESID - SoC has SDID[SERIESID] + * KINETIS_SIM_HAS_SDID_SRAMSIZE - SoC has SDID[SRAMSIZE] + * KINETIS_SIM_HAS_SDID_SUBFAMID - SoC has SDID[SUBFAMID] + * KINETIS_SIM_HAS_SCGC1 - SoC has _SCGC1 Register + * KINETIS_SIM_HAS_SCGC1_UART5 - SoC has SCGC1[UART5] + * KINETIS_SIM_HAS_SCGC1_UART4 - SoC has SCGC1[UART4] + * KINETIS_SIM_HAS_SCGC1_I2C3 - SoC has SCGC1[I2C3] + * KINETIS_SIM_HAS_SCGC1_I2C2 - SoC has SCGC1[I2C2] + * KINETIS_SIM_HAS_SCGC1_OSC1 - SoC has SCGC1[OSC1] + * KINETIS_SIM_HAS_SCGC2 - SoC has SCGC2 Register + * KINETIS_SIM_HAS_SCGC2_ENET - SoC has SCGC2[ENET] + * KINETIS_SIM_HAS_SCGC2_LPUART0 - SoC has SCGC2[LPUART0] + * KINETIS_SIM_HAS_SCGC2_TPM1 - SoC has SCGC2[TPM1] + * KINETIS_SIM_HAS_SCGC2_TPM2 - SoC has SCGC2[TPM2] + * KINETIS_SIM_HAS_SCGC3 - SoC has SCGC3 Register + * KINETIS_SIM_HAS_SCGC3 - SoC has SCGC3 Register + * KINETIS_SIM_HAS_SCGC3_RNGA - SoC has SCGC3[RNGA] + * KINETIS_SIM_HAS_SCGC3_USBHS - SoC has SCGC3[USBHS] + * KINETIS_SIM_HAS_SCGC3_USBHSPHY - SoC has SCGC3[USBHSPHY] + * KINETIS_SIM_HAS_SCGC3_USBHSDCD - SoC has SCGC3[USBHSDCD] + * KINETIS_SIM_HAS_SCGC3_FLEXCAN1 - SoC has SCGC3[FLEXCAN1] + * KINETIS_SIM_HAS_SCGC3_NFC - SoC has SCGC3[NFC] + * KINETIS_SIM_HAS_SCGC3_SPI2 - SoC has SCGC3[SPI2] + * KINETIS_SIM_HAS_SCGC3_SAI1 - SoC has SCGC3[SAI1] + * KINETIS_SIM_HAS_SCGC3_SDHC - SoC has SCGC3[SDHC] + * KINETIS_SIM_HAS_SCGC3_FTM2 - SoC has SCGC3[FTM2] + * KINETIS_SIM_HAS_SCGC3_FTM3 - SoC has SCGC3[FTM3] + * KINETIS_SIM_HAS_SCGC3_ADC1 - SoC has SCGC3[ADC1] + * KINETIS_SIM_HAS_SCGC3_ADC3 - SoC has SCGC3[ADC3] + * KINETIS_SIM_HAS_SCGC3_SLCD - SoC has SCGC3[SLCD] + * KINETIS_SIM_HAS_SCGC4 - SoC has SCGC4 Register + * KINETIS_SIM_HAS_SCGC4_LLWU - SoC has SCGC4[LLWU] clock gate + * KINETIS_SIM_HAS_SCGC4_UART0 - SoC has SCGC4[UART0] + * KINETIS_SIM_HAS_SCGC4_UART1 - SoC has SCGC4[UART1] + * KINETIS_SIM_HAS_SCGC4_UART2 - SoC has SCGC4[UART2] + * KINETIS_SIM_HAS_SCGC4_UART3 - SoC has SCGC4[UART3] + * KINETIS_SIM_HAS_SCGC5 - SoC has _SCGC5 Register + * KINETIS_SIM_HAS_SCGC5_REGFILE - SoC has SCGC5[REGFILE] + * KINETIS_SIM_HAS_SCGC5_TSI - SoC has SCGC5[TSI] + * KINETIS_SIM_HAS_SCGC5_PORTF - SoC has SCGC5[PORTf] + * KINETIS_SIM_HAS_SCGC6 - SoC has SCGC6 Register + * KINETIS_SIM_HAS_SCGC6_FTFL - SoC has SCGC6[FTFL] + * KINETIS_SIM_HAS_SCGC6_DMAMUX1 - SoC has SCGC6[DEMUX1] + * KINETIS_SIM_HAS_SCGC6_USBHS - SoC has SCGC6[USBHS] + * KINETIS_SIM_HAS_SCGC6_RNGA - SoC has SCGC6[RNGA] + * KINETIS_SIM_HAS_SCGC6_FTM2 - SoC has SCGC6[FTM2] + * KINETIS_SIM_HAS_SCGC6_ADC2 - SoC has SCGC6[ADC2] + * KINETIS_SIM_HAS_SCGC6_DAC0 - SoC has SCGC6[DAC0] + * KINETIS_SIM_HAS_SCGC7 - SoC has SCGC7 Register + * KINETIS_SIM_HAS_SCGC7_FLEXBUS - SoC has SCGC7[FLEXBUS] + * KINETIS_SIM_HAS_SCGC7_DMA - SoC has SCGC7[DMS] + * KINETIS_SIM_HAS_SCGC7_MPU - SoC has SCGC7[MPU] + * KINETIS_SIM_HAS_SCGC7_SDRAMC - SoC has SCGC7[SDRAMC] + * KINETIS_SIM_HAS_CLKDIV1 - SoC has CLKDIV1 Register + * KINETIS_SIM_HAS_CLKDIV1_OUTDIV2 - SoC has CLKDIV1[OUTDIV2] + * KINETIS_SIM_HAS_CLKDIV1_OUTDIV3 - SoC has CLKDIV1[OUTDIV3] + * KINETIS_SIM_HAS_CLKDIV1_OUTDIV4 - SoC has CLKDIV1[OUTDIV4] + * KINETIS_SIM_HAS_CLKDIV1_OUTDIV5 - SoC has CLKDIV1[OUTDIV5] + * KINETIS_SIM_HAS_CLKDIV2 - SoC has CLKDIV2 Register + * KINETIS_SIM_HAS_CLKDIV2_USBDIV - SoC has CLKDIV2[USBDIV] + * KINETIS_SIM_HAS_CLKDIV2_USBFRAC - SoC has CLKDIV2[USBFRAC] + * KINETIS_SIM_HAS_CLKDIV2_I2SDIV - SoC has CLKDIV2[I2SDIV] + * KINETIS_SIM_HAS_CLKDIV2_I2SFRAC - SoC has CLKDIV2[I2SFRAC] + * KINETIS_SIM_HAS_CLKDIV2_USBHSDIV - SoC has CLKDIV2[USBHSDIV] + * KINETIS_SIM_HAS_CLKDIV2_USBHSFRAC - SoC has CLKDIV2[USBHSFRAC] + * KINETIS_SIM_HAS_FCFG1 - SoC has FCFG1 Register + * KINETIS_SIM_HAS_FCFG1_DEPART - SoC has FCFG1[DEPART] + * KINETIS_SIM_HAS_FCFG1_EESIZE - SoC has FCFG1[EESIZE] + * KINETIS_SIM_HAS_FCFG1_FLASHDIS - SoC has FCFG1[FLASHDIS] + * KINETIS_SIM_HAS_FCFG1_FLASHDOZE - SoC has FCFG1[FLASHDOZE] + * KINETIS_SIM_HAS_FCFG1_FTFDIS - SoC has FCFG1[FTFDIS] + * KINETIS_SIM_HAS_FCFG1_NVMSIZE - SoC has FCFG1[NVMSIZE] + * KINETIS_SIM_HAS_FCFG2 - SoC has FCFG2 Register + * KINETIS_SIM_HAS_FCFG2_MAXADDR0 - SoC has n bit of FCFG2[MAXADDR0] + * KINETIS_SIM_HAS_FCFG2_MAXADDR1 - SoC has n bit of FCFG2[MAXADDR1] + * KINETIS_SIM_HAS_FCFG2_PFLSH - SoC has FCFG2[PFLSH] + * KINETIS_SIM_HAS_FCFG2_SWAPPFLSH - SoC has FCFG2[SWAPPFLSH] + * KINETIS_SIM_HAS_UIDH - SoC has UIDH Register + * KINETIS_SIM_HAS_UIDMH - SoC has UIDMH Register + * KINETIS_SIM_HAS_UIDML - SoC has UIDML Register + * KINETIS_SIM_HAS_UIDL - SoC has UIDL Register + * KINETIS_SIM_HAS_CLKDIV3 - SoC has CLKDIV3 Register + * KINETIS_SIM_HAS_CLKDIV3_PLLFLLDIV - SoC has CLKDIV3[PLLFLLDIV] + * KINETIS_SIM_HAS_CLKDIV3_PLLFLLFRAC - SoC has CLKDIV3[PLLFLLFRAC] + * KINETIS_SIM_HAS_CLKDIV4 - SoC has CLKDIV4 Register + * KINETIS_SIM_HAS_CLKDIV4_TRACEDIV - SoC has CLKDIV4[TRACEDIV] + * KINETIS_SIM_HAS_CLKDIV4_TRACEFRAC - SoC has CLKDIV4[TRACEFRAC] + * KINETIS_SIM_HAS_CLKDIV4_NFCEDIV - SoC has CLKDIV4[NFCDIV] + * KINETIS_SIM_HAS_CLKDIV4_NFCFRAC - SoC has CLKDIV4[NFCFRAC] + * KINETIS_SIM_HAS_MCR - SoC has MCR Register + */ + +/* Describe the version of the SIM + * + * These defines are not related to any NXP reference but are merely + * a way to label the versions we are using + */ + +#define KINETIS_SIM_VERSION_UKN -1 /* What was in nuttx prior to 2/16/2017 */ +#define KINETIS_SIM_VERSION_01 1 /* Verified Document Number: K60P144M150SF3RM Rev. 3, November 2014 */ +#define KINETIS_SIM_VERSION_04 4 /* Verified to Document Number: K64P144M120SF5RM Rev. 2, January 2014 */ +#define KINETIS_SIM_VERSION_06 6 /* Verified to Document Number: K66P144M180SF5RMV2 Rev. 2, May 2015 */ + +/* MK20DX/DN---VLH5 + * + * ------------- ------ --- ------- ------ ------- ------ ----- ---- + * PART NUMBER CPU PIN PACKAGE TOTAL PROGRAM EEPROM SRAM GPIO + * FREQ CNT FLASH FLASH + * ------------- ------ --- ------- ------ ------- ------ ----- ---- + * MK20DN32VLH5 50 MHz 64 LQFP 32 KB 32 KB — 8 KB 40 + * MK20DX32VLH5 50 MHz 64 LQFP 64 KB 32 KB 2 KB 8 KB 40 + * MK20DN64VLH5 50 MHz 64 LQFP 64 KB 64 KB — 16 KB 40 + * MK20DX64VLH5 50 MHz 64 LQFP 96 KB 64 KB 2 KB 16 KB 40 + * MK20DN128VLH5 50 MHz 64 LQFP 128 KB 128 KB — 16 KB 40 + * MK20DX128VLH5 50 MHz 64 LQFP 160 KB 128 KB 2 KB 16 KB 40 + */ + +#if defined(CONFIG_ARCH_CHIP_MK20DN32VLH5) || \ + defined(CONFIG_ARCH_CHIP_MK20DX32VLH5) || \ + defined(CONFIG_ARCH_CHIP_MK20DN64VLH5) || \ + defined(CONFIG_ARCH_CHIP_MK20DX64VLH5) || \ + defined(CONFIG_ARCH_CHIP_MK20DN128VLH5) || \ + defined(CONFIG_ARCH_CHIP_MK20DX128VLH5) + +# define KINETIS_SIM_VERSION KINETIS_SIM_VERSION_UKN + +/* MK20DX---VLH7 + * + * ------------- ------ --- ------- ------ ------- ------ ----- ---- + * PART NUMBER CPU PIN PACKAGE TOTAL PROGRAM EEPROM SRAM GPIO + * FREQ CNT FLASH FLASH + * ------------- ------ --- ------- ------ ------- ------ ----- ---- + * MK20DX64VLH7 72 MHz 64 LQFP 96 KB 64 KB 2 KB 16 KB 40 + * MK20DX128VLH7 72 MHz 64 LQFP 160 KB 128 KB 2 KB 32 KB 40 + * MK20DX256VLH7 72 MHz 64 LQFP 288 KB 256 KB 2 KB 64 KB 40 + * ------------- ------ --- ------- ------ ------- ------ ----- ---- + */ + +#elif defined(CONFIG_ARCH_CHIP_MK20DX64VLH7) || defined(CONFIG_ARCH_CHIP_MK20DX128VLH7) || \ + defined(CONFIG_ARCH_CHIP_MK20DX256VLH7) + +# define KINETIS_SIM_VERSION KINETIS_SIM_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK40X64VFX50) || defined(CONFIG_ARCH_CHIP_MK40X64VLH50) || \ + defined(CONFIG_ARCH_CHIP_MK40X64VLK50) || defined(CONFIG_ARCH_CHIP_MK40X64VMB50) + +# define KINETIS_SIM_VERSION KINETIS_SIM_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK40X128VFX50) || defined(CONFIG_ARCH_CHIP_MK40X128VLH50) || \ + defined(CONFIG_ARCH_CHIP_MK40X128VLK50) || defined(CONFIG_ARCH_CHIP_MK40X128VMB50) || \ + defined(CONFIG_ARCH_CHIP_MK40X128VLL50) || defined(CONFIG_ARCH_CHIP_MK40X128VML50) || \ + defined(CONFIG_ARCH_CHIP_MK40X128VFX72) || defined(CONFIG_ARCH_CHIP_MK40X128VLH72) || \ + defined(CONFIG_ARCH_CHIP_MK40X128VLK72) || defined(CONFIG_ARCH_CHIP_MK40X128VMB72) || \ + defined(CONFIG_ARCH_CHIP_MK40X128VLL72) || defined(CONFIG_ARCH_CHIP_MK40X128VML72) + +# define KINETIS_SIM_VERSION KINETIS_SIM_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK40X256VLK72) || defined(CONFIG_ARCH_CHIP_MK40X256VMB72) || \ + defined(CONFIG_ARCH_CHIP_MK40X256VLL72) || defined(CONFIG_ARCH_CHIP_MK40X256VML72) + +# define KINETIS_SIM_VERSION KINETIS_SIM_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK40X128VLQ100) || defined(CONFIG_ARCH_CHIP_MK40X128VMD100) + +# define KINETIS_SIM_VERSION KINETIS_SIM_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK40X256VLQ100) || defined(CONFIG_ARCH_CHIP_MK40X256VMD100) + +# define KINETIS_SIM_VERSION KINETIS_SIM_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK40N512VLK100) || defined(CONFIG_ARCH_CHIP_MK40N512VMB100) || \ + defined(CONFIG_ARCH_CHIP_MK40N512VLL100) || defined(CONFIG_ARCH_CHIP_MK40N512VML100) || \ + defined(CONFIG_ARCH_CHIP_MK40N512VLQ100) || defined(CONFIG_ARCH_CHIP_MK40N512VMD100) + +# define KINETIS_SIM_VERSION KINETIS_SIM_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK60N256VLL100) + +# define KINETIS_SIM_VERSION KINETIS_SIM_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK60X256VLL100) + +# define KINETIS_SIM_VERSION KINETIS_SIM_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK60N512VLL100) + +# define KINETIS_SIM_VERSION KINETIS_SIM_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK60N256VML100) + +# define KINETIS_SIM_VERSION KINETIS_SIM_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK60X256VML100) + +# define KINETIS_SIM_VERSION KINETIS_SIM_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK60N512VML100) + +# define KINETIS_SIM_VERSION KINETIS_SIM_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK60N256VLQ100) + +# define KINETIS_SIM_VERSION KINETIS_SIM_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK60X256VLQ100) + +# define KINETIS_SIM_VERSION KINETIS_SIM_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK60N512VLQ100) + +# define KINETIS_SIM_VERSION KINETIS_SIM_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK60N256VMD100) + +# define KINETIS_SIM_VERSION KINETIS_SIM_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK60X256VMD100) + +# define KINETIS_SIM_VERSION KINETIS_SIM_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK60N512VMD100) + +# define KINETIS_SIM_VERSION KINETIS_SIM_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK60FN1M0VLQ12) + +/* Verified to Document Number: K60P144M100SF2V2RM Rev. 2 Jun 2012 */ + +# define KINETIS_SIM_VERSION KINETIS_SIM_VERSION_01 + +/* SIM Register Configuration */ + +# define KINETIS_SIM_HAS_SOPT1 1 /* SoC has SOPT1 Register */ +# undef KINETIS_SIM_HAS_SOPT1_OSC32KOUT /* SoC has SOPT1[OSC32KOUT] */ +# define KINETIS_SIM_HAS_SOPT1_OSC32KSEL 1 /* SoC has SOPT1[OSC32KSEL] */ +# define KINETIS_SIM_HAS_SOPT1_OSC32KSEL_BITS 1 /* SoC has 1 bit SOPT1[OSC32KSEL] */ +# define KINETIS_SIM_HAS_SOPT1_RAMSIZE 1 /* SoC has SOPT1[RAMSIZE] */ +# define KINETIS_SIM_HAS_SOPT1_USBREGEN 1 /* SoC has SOPT1[USBREGEN] */ +# define KINETIS_SIM_HAS_SOPT1_USBSSTBY 1 /* SoC has SOPT1[USBSSTBY] */ +# define KINETIS_SIM_HAS_SOPT1_USBVSTBY 1 /* SoC has SOPT1[USBVSTBY] */ +# define KINETIS_SIM_HAS_SOPT1CFG /* SoC has SOPT1CFG Register */ +# define KINETIS_SIM_HAS_SOPT1CFG_URWE 1 /* SoC has SOPT1CFG[URWE] */ +# define KINETIS_SIM_HAS_SOPT1CFG_USSWE 1 /* SoC has SOPT1CFG[USSWE] */ +# define KINETIS_SIM_HAS_SOPT1CFG_UVSWE 1 /* SoC has SOPT1CFG[UVSWE] */ +# undef KINETIS_SIM_HAS_USBPHYCTL /* SoC has USBPHYCTL Register */ +# undef KINETIS_SIM_HAS_USBPHYCTL_USB3VOUTTRG /* SoC has USBPHYCTL[USB3VOUTTRG] */ +# undef KINETIS_SIM_HAS_USBPHYCTL_USBDISILIM /* SoC has USBPHYCTL[USBDISILIM] */ +# undef KINETIS_SIM_HAS_USBPHYCTL_USBVREGPD /* SoC has USBPHYCTL[USBVREGPD] */ +# undef KINETIS_SIM_HAS_USBPHYCTL_USBVREGSEL /* SoC has USBPHYCTL[USBVREGSEL] */ +# define KINETIS_SIM_HAS_SOPT2 1 /* SoC has SOPT2 Register */ +# define KINETIS_SIM_HAS_SOPT2_FBSL 1 /* SoC has SOPT2[FBSL] */ +# define KINETIS_SIM_HAS_SOPT2_CMTUARTPAD 1 /* SoC has SOPT2[CMTUARTPAD] */ +# define KINETIS_SIM_HAS_SOPT2_FLEXIOSRC 1 /* SoC has SOPT2[FLEXIOSRC] */ +# undef KINETIS_SIM_HAS_SOPT2_LPUARTSRC /* SoC has SOPT2[LPUARTSRC] */ +# define KINETIS_SIM_HAS_SOPT2_PLLFLLSEL 1 /* SoC has SOPT2[PLLFLLSEL] */ +# define KINETIS_SIM_HAS_SOPT2_PLLFLLSEL_BITS 2 /* SoC has 2 bits of SOPT2[PLLFLLSEL] */ +# undef KINETIS_SIM_HAS_SOPT2_PTD7PAD /* SoC has SOPT2[PTD7PAD] */ +# undef KINETIS_SIM_HAS_SOPT2_RMIISRC /* SoC has SOPT2[RMIISRC] */ +# define KINETIS_SIM_HAS_SOPT2_RTCCLKOUTSEL 1 /* SoC has SOPT2[RTCCLKOUTSEL] */ +# define KINETIS_SIM_HAS_SOPT2_CLKOUTSEL 1 /* SoC has SOPT2[CLKOUTSEL] */ +# define KINETIS_SIM_HAS_SOPT2_SDHCSRC 1 /* SoC has SOPT2[SDHCSRC] */ +# define KINETIS_SIM_HAS_SOPT2_NFCSRC 1 /* SoC has SOPT2[NFCSRC] */ +# undef KINETIS_SIM_HAS_SOPT2_I2SSRC /* SoC has SOPT2[I2SSRC] */ +# define KINETIS_SIM_HAS_SOPT2_TIMESRC 1 /* SoC has SOPT2[TIMESRC] */ +# undef KINETIS_SIM_HAS_SOPT2_TPMSRC /* SoC has SOPT2[TPMSRC] */ +# define KINETIS_SIM_HAS_SOPT2_USBFSRC 1 /* SoC has SOPT2[USBFSRC] */ +# define KINETIS_SIM_HAS_SOPT2_TRACECLKSEL 1 /* SoC has SOPT2[TRACECLKSEL] */ +# undef KINETIS_SIM_HAS_SOPT2_USBREGEN /* SoC has SOPT2[USBREGEN] */ +# undef KINETIS_SIM_HAS_SOPT2_USBSLSRC /* SoC has SOPT2[USBSLSRC] */ +# define KINETIS_SIM_HAS_SOPT2_USBHSRC 1 /* SoC has SOPT2[USBHSRC] */ +# define KINETIS_SIM_HAS_SOPT2_USBSRC 1 /* SoC has SOPT2[USBSRC] */ +# undef KINETIS_SIM_HAS_SOPT2_MCGCLKSEL /* SoC has SOPT2[MCGCLKSEL] */ +# define KINETIS_SIM_HAS_SOPT4 1 /* SoC has SOPT4 Register */ +# define KINETIS_SIM_HAS_SOPT4_FTM0FLT0 1 /* SoC has SOPT4[FTM0FLT0] */ +# define KINETIS_SIM_HAS_SOPT4_FTM0FLT1 1 /* SoC has SOPT4[FTM0FLT1] */ +# define KINETIS_SIM_HAS_SOPT4_FTM0FLT2 1 /* SoC has SOPT4[FTM0FLT2] */ +# define KINETIS_SIM_HAS_SOPT4_FTM0FLT3 1 /* SoC has SOPT4[FTM0FLT3] */ +# define KINETIS_SIM_HAS_SOPT4_FTM0TRG0SRC 1 /* SoC has SOPT4[FTM0TRG0SRC] */ +# define KINETIS_SIM_HAS_SOPT4_FTM0TRG1SRC 1 /* SoC has SOPT4[FTM0TRG1SRC] */ +# define KINETIS_SIM_HAS_SOPT4_FTM1CH0SRC 3 /* SoC has SOPT4[FTM1CH0SRC] 1, 3 if SOF */ +# define KINETIS_SIM_HAS_SOPT4_FTM1FLT0 1 /* SoC has SOPT4[FTM1FLT0] */ +# define KINETIS_SIM_HAS_SOPT4_FTM1FLT1 1 /* SoC has SOPT4[FTM1FLT1] */ +# define KINETIS_SIM_HAS_SOPT4_FTM1FLT2 1 /* SoC has SOPT4[FTM1FLT2] */ +# define KINETIS_SIM_HAS_SOPT4_FTM1FLT3 1 /* SoC has SOPT4[FTM1FLT3] */ +# define KINETIS_SIM_HAS_SOPT4_FTM2CH0SRC 1 /* SoC has SOPT4[FTM2CH0SRC] */ +# undef KINETIS_SIM_HAS_SOPT4_FTM2CH1SRC /* SoC has SOPT4[FTM2CH1SRC] */ +# define KINETIS_SIM_HAS_SOPT4_FTM2FLT0 1 /* SoC has SOPT4[FTM2FLT0] */ +# define KINETIS_SIM_HAS_SOPT4_FTM2FLT1 1 /* SoC has SOPT4[FTM2FLT1] */ +# define KINETIS_SIM_HAS_SOPT4_FTM2FLT2 1 /* SoC has SOPT4[FTM2FLT2] */ +# define KINETIS_SIM_HAS_SOPT4_FTM2FLT3 1 /* SoC has SOPT4[FTM2FLT3] */ +# define KINETIS_SIM_HAS_SOPT4_FTM3CH0SRC 1 /* SoC has SOPT4[FTM3CH0SRC] */ +# define KINETIS_SIM_HAS_SOPT4_FTM3FLT0 1 /* SoC has SOPT4[FTM3FLT0] */ +# define KINETIS_SIM_HAS_SOPT4_FTM3FLT1 1 /* SoC has SOPT4[FTM3FLT1] */ +# define KINETIS_SIM_HAS_SOPT4_FTM3FLT2 1 /* SoC has SOPT4[FTM3FLT2] */ +# define KINETIS_SIM_HAS_SOPT4_FTM3FLT3 1 /* SoC has SOPT4[FTM3FLT3] */ +# define KINETIS_SIM_HAS_SOPT4_FTM3TRG0SRC 1 /* SoC has SOPT4[FTM3TRG0SRC] */ +# define KINETIS_SIM_HAS_SOPT4_FTM3TRG1SRC 1 /* SoC has SOPT4[FTM3TRG1SRC] */ +# define KINETIS_SIM_HAS_SOPT4_TPM0CLKSEL 1 /* SoC has SOPT4[TPM0CLKSEL] */ +# define KINETIS_SIM_HAS_SOPT4_TPM1CH0SRC 1 /* SoC has SOPT4[TPM1CH0SRC] */ +# define KINETIS_SIM_HAS_SOPT4_TPM1CLKSEL 1 /* SoC has SOPT4[TPM1CLKSEL] */ +# define KINETIS_SIM_HAS_SOPT4_TPM2CH0SRC 1 /* SoC has SOPT4[TPM2CH0SRC] */ +# define KINETIS_SIM_HAS_SOPT4_TPM2CLKSEL 1 /* SoC has SOPT4[TPM2CLKSEL] */ +# define KINETIS_SIM_HAS_SOPT5 1 /* SoC has SOPT5 Register */ +# undef KINETIS_SIM_HAS_SOPT5_LPUART0RXSRC /* SoC has SOPT5[LPUART0RXSRC] */ +# undef KINETIS_SIM_HAS_SOPT5_LPUART0TXSRC /* SoC has SOPT5[LPUART0TXSRC] */ +# define KINETIS_SIM_HAS_SOPT6 1 /* SoC has SOPT6 Register */ +# define KINETIS_SIM_HAS_SOPT6_MCC 1 /* SoC has SOPT6[MCC] */ +# define KINETIS_SIM_HAS_SOPT6_PCR 1 /* SoC has SOPT6[PCR] */ +# undef KINETIS_SIM_HAS_SOPT6_RSTFLTSEL /* SoC has SOPT6[RSTFLTSEL] */ +# undef KINETIS_SIM_HAS_SOPT6_RSTFLTEN /* SoC has SOPT6[RSTFLTEN] */ +# define KINETIS_SIM_HAS_SOPT7 1 /* SoC has SOPT7 Register */ +# define KINETIS_SIM_HAS_SOPT7_ADC0ALTTRGSEL 1 /* SoC has SOPT7[ADC0ALTTRGSEL] */ +# define KINETIS_SIM_HAS_SOPT7_ADC1ALTTRGSEL 1 /* SoC has SOPT7[ADC1ALTTRGSEL] */ +# define KINETIS_SIM_HAS_SOPT7_ADC0PRETRGSEL 1 /* SoC has SOPT7[ADC0PRETRGSEL] */ +# define KINETIS_SIM_HAS_SOPT7_ADC1PRETRGSEL 1 /* SoC has SOPT7[ADC1PRETRGSEL] */ +# define KINETIS_SIM_HAS_SOPT7_ADC2PRETRGSEL 1 /* SoC has SOPT7[ADC2PRETRGSEL] */ +# define KINETIS_SIM_HAS_SOPT7_ADC3PRETRGSEL 1 /* SoC has SOPT7[ADC3PRETRGSEL] */ +# define KINETIS_SIM_HAS_SOPT7_ADC0TRGSEL 15 /* SoC has 15 SOPT7[ADC0TRGSEL] */ +# define KINETIS_SIM_HAS_SOPT7_ADC1TRGSEL 15 /* SoC has 15 SOPT7[ADC1TRGSEL] */ +# define KINETIS_SIM_HAS_SOPT7_ADC2TRGSEL 15 /* SoC has 15 SOPT7[ADC2TRGSEL] */ +# define KINETIS_SIM_HAS_SOPT7_ADC3TRGSEL 15 /* SoC has 15 SOPT7[ADC3TRGSEL] */ +# define KINETIS_SIM_SOPT7_ADC0ALTTRGEN 1 /* ADC0 alternate trigger enable */ +# define KINETIS_SIM_SOPT7_ADC1ALTTRGEN 1 /* ADC1 alternate trigger enable */ +# define KINETIS_SIM_SOPT7_ADC2ALTTRGEN 1 /* ADC2 alternate trigger enable */ +# define KINETIS_SIM_SOPT7_ADC3ALTTRGEN 1 /* ADC3 alternate trigger enable */ +# undef KINETIS_SIM_HAS_SOPT8 /* SoC has SOPT8 Register */ +# undef KINETIS_SIM_HAS_SOPT8_FTM0SYNCBIT /* SoC has SOPT8[FTM0SYNCBIT] */ +# undef KINETIS_SIM_HAS_SOPT8_FTM1SYNCBIT /* SoC has SOPT8[FTM1SYNCBIT] */ +# undef KINETIS_SIM_HAS_SOPT8_FTM2SYNCBIT /* SoC has SOPT8[FTM2SYNCBIT] */ +# undef KINETIS_SIM_HAS_SOPT8_FTM3SYNCBIT /* SoC has SOPT8[FTM3SYNCBIT] */ +# undef KINETIS_SIM_HAS_SOPT8_FTM0OCH0SRC /* SoC has SOPT8[FTM0OCH0SRC] */ +# undef KINETIS_SIM_HAS_SOPT8_FTM0OCH1SRC /* SoC has SOPT8[FTM0OCH1SRC] */ +# undef KINETIS_SIM_HAS_SOPT8_FTM0OCH2SRC /* SoC has SOPT8[FTM0OCH2SRC] */ +# undef KINETIS_SIM_HAS_SOPT8_FTM0OCH3SRC /* SoC has SOPT8[FTM0OCH3SRC] */ +# undef KINETIS_SIM_HAS_SOPT8_FTM0OCH4SRC /* SoC has SOPT8[FTM0OCH4SRC] */ +# undef KINETIS_SIM_HAS_SOPT8_FTM0OCH5SRC /* SoC has SOPT8[FTM0OCH5SRC] */ +# undef KINETIS_SIM_HAS_SOPT8_FTM0OCH6SRC /* SoC has SOPT8[FTM0OCH6SRC] */ +# undef KINETIS_SIM_HAS_SOPT8_FTM0OCH7SRC /* SoC has SOPT8[FTM0OCH7SRC] */ +# undef KINETIS_SIM_HAS_SOPT8_FTM3OCH0SRC /* SoC has SOPT8[FTM3OCH0SRC] */ +# undef KINETIS_SIM_HAS_SOPT8_FTM3OCH1SRC /* SoC has SOPT8[FTM3OCH1SRC] */ +# undef KINETIS_SIM_HAS_SOPT8_FTM3OCH2SRC /* SoC has SOPT8[FTM3OCH2SRC] */ +# undef KINETIS_SIM_HAS_SOPT8_FTM3OCH3SRC /* SoC has SOPT8[FTM3OCH3SRC] */ +# undef KINETIS_SIM_HAS_SOPT8_FTM3OCH4SRC /* SoC has SOPT8[FTM3OCH4SRC] */ +# undef KINETIS_SIM_HAS_SOPT8_FTM3OCH5SRC /* SoC has SOPT8[FTM3OCH5SRC] */ +# undef KINETIS_SIM_HAS_SOPT8_FTM3OCH6SRC /* SoC has SOPT8[FTM3OCH6SRC] */ +# undef KINETIS_SIM_HAS_SOPT8_FTM3OCH7SRC /* SoC has SOPT8[FTM3OCH7SRC] */ +# undef KINETIS_SIM_HAS_SOPT9 /* SoC has SOPT9 Register */ +# undef KINETIS_SIM_HAS_SOPT9_TPM1CH0SRC /* SoC has SOPT9[TPM1CH0SRC] */ +# undef KINETIS_SIM_HAS_SOPT9_TPM2CH0SRC /* SoC has SOPT9[TPM2CH0SRC] */ +# undef KINETIS_SIM_HAS_SOPT9_TPM1CLKSEL /* SoC has SOPT9[TPM1CLKSEL] */ +# undef KINETIS_SIM_HAS_SOPT9_TPM2CLKSEL /* SoC has SOPT9[TPM2CLKSEL] */ +# define KINETIS_SIM_HAS_SDID 1 /* SoC has SDID Register */ +# undef KINETIS_SIM_HAS_SDID_DIEID /* SoC has SDID[DIEID] */ +# define KINETIS_SIM_HAS_SDID_FAMID 1 /* SoC has SDID[FAMID] */ +# undef KINETIS_SIM_HAS_SDID_FAMILYID /* SoC has SDID[FAMILYID] */ +# undef KINETIS_SIM_HAS_SDID_SERIESID /* SoC has SDID[SERIESID] */ +# undef KINETIS_SIM_HAS_SDID_SRAMSIZE /* SoC has SDID[SRAMSIZE] */ +# undef KINETIS_SIM_HAS_SDID_SUBFAMID /* SoC has SDID[SUBFAMID] */ +# define KINETIS_SIM_HAS_SCGC1 1 /* SoC has _SCGC1 Register */ +# define KINETIS_SIM_HAS_SCGC1_UART5 1 /* SoC has SCGC1[UART5] */ +# define KINETIS_SIM_HAS_SCGC1_UART4 1 /* SoC has SCGC1[UART4] */ +# undef KINETIS_SIM_HAS_SCGC1_I2C3 /* SoC has SCGC1[I2C3] */ +# undef KINETIS_SIM_HAS_SCGC1_I2C2 /* SoC has SCGC1[I2C2] */ +# define KINETIS_SIM_HAS_SCGC1_OSC1 1 /* SoC has SCGC1[OSC1] */ +# define KINETIS_SIM_HAS_SCGC2 1 /* SoC has _SCGC2 Register */ +# define KINETIS_SIM_HAS_SCGC2 1 /* SoC has SCGC2 Register */ +# define KINETIS_SIM_HAS_SCGC2_ENET 1 /* SoC has SCGC2[ENET] */ +# undef KINETIS_SIM_HAS_SCGC2_LPUART0 /* SoC has SCGC2[LPUART0] */ +# undef KINETIS_SIM_HAS_SCGC2_TPM1 /* SoC has SCGC2[TPM1] */ +# undef KINETIS_SIM_HAS_SCGC2_TPM2 /* SoC has SCGC2[TPM2] */ +# define KINETIS_SIM_HAS_SCGC3 1 /* SoC has SCGC3 Register */ +# define KINETIS_SIM_HAS_SCGC3_RNGA 1 /* SoC has SCGC3[RNGA] */ +# undef KINETIS_SIM_HAS_SCGC3_USBHS /* SoC has SCGC3[USBHS] */ +# undef KINETIS_SIM_HAS_SCGC3_USBHSPHY /* SoC has SCGC3[USBHSPHY] */ +# undef KINETIS_SIM_HAS_SCGC3_USBHSDCD /* SoC has SCGC3[USBHSDCD] */ +# define KINETIS_SIM_HAS_SCGC3_FLEXCAN1 1 /* SoC has SCGC3[FLEXCAN1] */ +# define KINETIS_SIM_HAS_SCGC3_NFC 1 /* SoC has SCGC3[NFC] */ +# define KINETIS_SIM_HAS_SCGC3_SPI2 1 /* SoC has SCGC3[SPI2] */ +# define KINETIS_SIM_HAS_SCGC3_SAI1 1 /* SoC has SCGC3[SAI1] */ +# define KINETIS_SIM_HAS_SCGC3_SDHC 1 /* SoC has SCGC3[SDHC] */ +# define KINETIS_SIM_HAS_SCGC3_FTM2 1 /* SoC has SCGC3[FTM2] */ +# define KINETIS_SIM_HAS_SCGC3_FTM3 1 /* SoC has SCGC3[FTM3] */ +# define KINETIS_SIM_HAS_SCGC3_ADC1 1 /* SoC has SCGC3[ADC1] */ +# define KINETIS_SIM_HAS_SCGC3_ADC3 1 /* SoC has SCGC3[ADC3] */ +# undef KINETIS_SIM_HAS_SCGC3_SLCD /* SoC has SCGC3[SLCD] */ +# define KINETIS_SIM_HAS_SCGC4 1 /* SoC has SCGC4 Register */ +# define KINETIS_SIM_HAS_SCGC4_LLWU 1 /* SoC has SCGC4[LLWU] clock gate */ +# define KINETIS_SIM_HAS_SCGC4_UART0 1 /* SoC has SCGC4[UART0] */ +# define KINETIS_SIM_HAS_SCGC4_UART1 1 /* SoC has SCGC4[UART1] */ +# define KINETIS_SIM_HAS_SCGC4_UART2 1 /* SoC has SCGC4[UART2] */ +# define KINETIS_SIM_HAS_SCGC4_UART3 1 /* SoC has SCGC4[UART3] */ +# define KINETIS_SIM_HAS_SCGC5 1 /* SoC has _SCGC5 Register */ +# undef KINETIS_SIM_HAS_SCGC5_REGFILE /* SoC has SCGC5[REGFILE] */ +# define KINETIS_SIM_HAS_SCGC5_TSI 1 /* SoC has SCGC5[TSI] */ +# define KINETIS_SIM_HAS_SCGC5_PORTF 1 /* SoC has SCGC5[PORTF] */ +# define KINETIS_SIM_HAS_SCGC6 1 /* SoC has SCGC6 Register */ +# undef KINETIS_SIM_HAS_SCGC6_FTFL /* SoC has SCGC6[FTFL] */ +# define KINETIS_SIM_HAS_SCGC6_DMAMUX1 1 /* SoC has SCGC6[DEMUX1] */ +# define KINETIS_SIM_HAS_SCGC6_USBHS 1 /* SoC has SCGC6[USBHS] */ +# define KINETIS_SIM_HAS_SCGC6_RNGA 1 /* SoC has SCGC6[RNGA] */ +# undef KINETIS_SIM_HAS_SCGC6_FTM2 /* SoC has SCGC6[FTM2] */ +# define KINETIS_SIM_HAS_SCGC6_ADC2 1 /* SoC has SCGC6[ADC2] */ +# undef KINETIS_SIM_HAS_SCGC6_DAC0 /* SoC has SCGC6[DAC0] */ +# define KINETIS_SIM_HAS_SCGC7 1 /* SoC has SCGC7 Register */ +# define KINETIS_SIM_HAS_SCGC7_FLEXBUS 1 /* SoC has SCGC7[FLEXBUS] */ +# define KINETIS_SIM_HAS_SCGC7_DMA 1 /* SoC has SCGC7[DMS] */ +# define KINETIS_SIM_HAS_SCGC7_MPU 1 /* SoC has SCGC7[MPU] */ +# undef KINETIS_SIM_HAS_SCGC7_SDRAMC /* SoC has SCGC7[SDRAMC] */ +# define KINETIS_SIM_HAS_CLKDIV1 1 /* SoC has CLKDIV1 Register */ +# define KINETIS_SIM_HAS_CLKDIV1_OUTDIV2 1 /* SoC has CLKDIV1[OUTDIV2] */ +# define KINETIS_SIM_HAS_CLKDIV1_OUTDIV3 1 /* SoC has CLKDIV1[OUTDIV3] */ +# define KINETIS_SIM_HAS_CLKDIV1_OUTDIV4 1 /* SoC has CLKDIV1[OUTDIV4] */ +# undef KINETIS_SIM_HAS_CLKDIV1_OUTDIV5 /* SoC has CLKDIV1[OUTDIV5] */ +# define KINETIS_SIM_HAS_CLKDIV2 1 /* SoC has CLKDIV2 Register */ +# define KINETIS_SIM_HAS_CLKDIV2_USBDIV 1 /* SoC has CLKDIV2[USBDIV] */ +# define KINETIS_SIM_HAS_CLKDIV2_USBFRAC 1 /* SoC has CLKDIV2[USBFRAC] */ +# undef KINETIS_SIM_HAS_CLKDIV2_USBFSDIV /* SoC has CLKDIV2[USBFSDIV] */ +# undef KINETIS_SIM_HAS_CLKDIV2_USBFSFRAC /* SoC has CLKDIV2[USBFSFRAC] */ +# define KINETIS_SIM_HAS_CLKDIV2_USBHSDIV 1 /* SoC has CLKDIV2[USBHSDIV] */ +# define KINETIS_SIM_HAS_CLKDIV2_USBHSFRAC 1 /* SoC has CLKDIV2[USBHSFRAC] */ +# undef KINETIS_SIM_HAS_CLKDIV2_I2SDIV /* SoC has CLKDIV2[I2SDIV] */ +# undef KINETIS_SIM_HAS_CLKDIV2_I2SFRAC /* SoC has CLKDIV2[I2SFRAC] */ +# define KINETIS_SIM_HAS_FCFG1 1 /* SoC has FCFG1 Register */ +# define KINETIS_SIM_HAS_FCFG1_DEPART 1 /* SoC has FCFG1[DEPART] */ +# define KINETIS_SIM_HAS_FCFG1_EESIZE 1 /* SoC has FCFG1[EESIZE] */ +# undef KINETIS_SIM_HAS_FCFG1_FLASHDIS /* SoC has FCFG1[FLASHDIS] */ +# undef KINETIS_SIM_HAS_FCFG1_FLASHDOZE /* SoC has FCFG1[FLASHDOZE] */ +# define KINETIS_SIM_HAS_FCFG1_FTFDIS 1 /* SoC has FCFG1[FTFDIS] */ +# define KINETIS_SIM_HAS_FCFG1_NVMSIZE 1 /* SoC has FCFG1[NVMSIZE] */ +# define KINETIS_SIM_HAS_FCFG2 1 /* SoC has FCFG2 Register */ +# define KINETIS_SIM_HAS_FCFG2_MAXADDR0 6 /* SoC has n bit of FCFG2[MAXADDR0] */ +# define KINETIS_SIM_HAS_FCFG2_MAXADDR1 6 /* SoC has n bit of FCFG2[MAXADDR1] */ +# define KINETIS_SIM_HAS_FCFG2_PFLSH 1 /* SoC has FCFG2[PFLSH] */ +# define KINETIS_SIM_HAS_FCFG2_SWAPPFLSH 1 /* SoC has FCFG2[SWAPPFLSH] */ +# define KINETIS_SIM_HAS_UIDH 1 /* SoC has UIDH Register */ +# define KINETIS_SIM_HAS_UIDMH 1 /* SoC has UIDMH Register */ +# define KINETIS_SIM_HAS_UIDML 1 /* SoC has UIDML Register */ +# define KINETIS_SIM_HAS_UIDL 1 /* SoC has UIDL Register */ +# undef KINETIS_SIM_HAS_CLKDIV3 /* SoC has CLKDIV3 Register */ +# undef KINETIS_SIM_HAS_CLKDIV3_PLLFLLDIV /* SoC has CLKDIV3[PLLFLLDIV] */ +# undef KINETIS_SIM_HAS_CLKDIV3_PLLFLLFRAC /* SoC has CLKDIV3[PLLFLLFRAC] */ +# define KINETIS_SIM_HAS_CLKDIV4 1 /* SoC has CLKDIV4 Register */ +# define KINETIS_SIM_HAS_CLKDIV4_TRACEDIV 1 /* SoC has CLKDIV4[TRACEDIV] */ +# define KINETIS_SIM_HAS_CLKDIV4_TRACEFRAC 1 /* SoC has CLKDIV4[TRACEFRAC] */ +# define KINETIS_SIM_HAS_CLKDIV4_NFCDIV 1 /* SoC has CLKDIV4[NFCDIV] */ +# define KINETIS_SIM_HAS_CLKDIV4_NFCFRAC 1 /* SoC has CLKDIV4[NFCFRAC] */ +# define KINETIS_SIM_HAS_MCR 1 /* SoC has MCR Register */ + +#elif defined(CONFIG_ARCH_CHIP_MK64FN1M0VLL12) || defined(CONFIG_ARCH_CHIP_MK64FX512VLL12) || \ + defined(CONFIG_ARCH_CHIP_MK64FX512VDC12) || defined(CONFIG_ARCH_CHIP_MK64FN1M0VDC12) || \ + defined(CONFIG_ARCH_CHIP_MK64FX512VLQ12) || defined(CONFIG_ARCH_CHIP_MK64FN1M0VLQ12) || \ + defined(CONFIG_ARCH_CHIP_MK64FX512VMD12) || defined(CONFIG_ARCH_CHIP_MK64FN1M0VMD12) + +/* Verified to Document Number: K64P144M120SF5RM Rev. 2, January 2014 */ + +# define KINETIS_SIM_VERSION KINETIS_SIM_VERSION_04 + +/* SIM Register Configuration */ + +# define KINETIS_SIM_HAS_SOPT1 1 /* SoC has SOPT1 Register */ +# undef KINETIS_SIM_HAS_SOPT1_OSC32KOUT /* SoC has SOPT1[OSC32KOUT] */ +# define KINETIS_SIM_HAS_SOPT1_OSC32KSEL 1 /* SoC has SOPT1[OSC32KSEL] */ +# define KINETIS_SIM_HAS_SOPT1_OSC32KSEL_BITS 2 /* SoC has 2 bits of SOPT1[OSC32KSEL] */ +# define KINETIS_SIM_HAS_SOPT1_RAMSIZE 1 /* SoC has SOPT1[RAMSIZE] */ +# define KINETIS_SIM_HAS_SOPT1_USBREGEN 1 /* SoC has SOPT1[USBREGEN] */ +# define KINETIS_SIM_HAS_SOPT1_USBSSTBY 1 /* SoC has SOPT1[USBSSTBY] */ +# define KINETIS_SIM_HAS_SOPT1_USBVSTBY 1 /* SoC has SOPT1[USBVSTBY] */ +# define KINETIS_SIM_HAS_SOPT1CFG /* SoC has SOPT1CFG Register */ +# define KINETIS_SIM_HAS_SOPT1CFG_URWE 1 /* SoC has SOPT1CFG[URWE] */ +# define KINETIS_SIM_HAS_SOPT1CFG_USSWE 1 /* SoC has SOPT1CFG[USSWE] */ +# define KINETIS_SIM_HAS_SOPT1CFG_UVSWE 1 /* SoC has SOPT1CFG[UVSWE] */ +# undef KINETIS_SIM_HAS_USBPHYCTL /* SoC has USBPHYCTL Register */ +# undef KINETIS_SIM_HAS_USBPHYCTL_USB3VOUTTRG /* SoC has USBPHYCTL[USB3VOUTTRG] */ +# undef KINETIS_SIM_HAS_USBPHYCTL_USBDISILIM /* SoC has USBPHYCTL[USBDISILIM] */ +# undef KINETIS_SIM_HAS_USBPHYCTL_USBVREGPD /* SoC has USBPHYCTL[USBVREGPD] */ +# undef KINETIS_SIM_HAS_USBPHYCTL_USBVREGSEL /* SoC has USBPHYCTL[USBVREGSEL] */ +# define KINETIS_SIM_HAS_SOPT2 1 /* SoC has SOPT2 Register */ +# define KINETIS_SIM_HAS_SOPT2_FBSL 1 /* SoC has SOPT2[FBSL] */ +# undef KINETIS_SIM_HAS_SOPT2_CMTUARTPAD /* SoC has SOPT2[CMTUARTPAD] */ +# define KINETIS_SIM_HAS_SOPT2_FLEXIOSRC 1 /* SoC has SOPT2[FLEXIOSRC] */ +# undef KINETIS_SIM_HAS_SOPT2_LPUARTSRC /* SoC has SOPT2[LPUARTSRC] */ +# define KINETIS_SIM_HAS_SOPT2_PLLFLLSEL 1 /* SoC has SOPT2[PLLFLLSEL] */ +# define KINETIS_SIM_HAS_SOPT2_PLLFLLSEL_BITS 2 /* SoC has 2 bits of SOPT2[PLLFLLSEL] */ +# define KINETIS_SIM_HAS_SOPT2_PTD7PAD 1 /* SoC has SOPT2[PTD7PAD] */ +# define KINETIS_SIM_HAS_SOPT2_RMIISRC 1 /* SoC has SOPT2[RMIISRC] */ +# define KINETIS_SIM_HAS_SOPT2_RTCCLKOUTSEL 1 /* SoC has SOPT2[RTCCLKOUTSEL] */ +# define KINETIS_SIM_HAS_SOPT2_CLKOUTSEL 1 /* SoC has SOPT2[CLKOUTSEL] */ +# define KINETIS_SIM_HAS_SOPT2_SDHCSRC 1 /* SoC has SOPT2[SDHCSRC] */ +# undef KINETIS_SIM_HAS_SOPT2_NFCSRC /* SoC has SOPT2[NFCSRC] */ +# undef KINETIS_SIM_HAS_SOPT2_I2SSRC /* SoC has SOPT2[I2SSRC] */ +# define KINETIS_SIM_HAS_SOPT2_TIMESRC 1 /* SoC has SOPT2[TIMESRC] */ +# undef KINETIS_SIM_HAS_SOPT2_TPMSRC /* SoC has SOPT2[TPMSRC] */ +# undef KINETIS_SIM_HAS_SOPT2_USBFSRC /* SoC has SOPT2[USBFSRC] */ +# define KINETIS_SIM_HAS_SOPT2_TRACECLKSEL 1 /* SoC has SOPT2[TRACECLKSEL] */ +# undef KINETIS_SIM_HAS_SOPT2_USBREGEN /* SoC has SOPT2[USBREGEN] */ +# undef KINETIS_SIM_HAS_SOPT2_USBSLSRC /* SoC has SOPT2[USBSLSRC] */ +# undef KINETIS_SIM_HAS_SOPT2_USBHSRC /* SoC has SOPT2[USBHSRC] */ +# define KINETIS_SIM_HAS_SOPT2_USBSRC 1 /* SoC has SOPT2[USBSRC] */ +# undef KINETIS_SIM_HAS_SOPT2_MCGCLKSEL /* SoC has SOPT2[MCGCLKSEL] */ +# define KINETIS_SIM_HAS_SOPT4 1 /* SoC has SOPT4 Register */ +# define KINETIS_SIM_HAS_SOPT4_FTM0FLT0 1 /* SoC has SOPT4[FTM0FLT0] */ +# define KINETIS_SIM_HAS_SOPT4_FTM0FLT1 1 /* SoC has SOPT4[FTM0FLT1] */ +# define KINETIS_SIM_HAS_SOPT4_FTM0FLT2 1 /* SoC has SOPT4[FTM0FLT2] */ +# undef KINETIS_SIM_HAS_SOPT4_FTM0FLT3 /* SoC has SOPT4[FTM0FLT3] */ +# define KINETIS_SIM_HAS_SOPT4_FTM0TRG0SRC 1 /* SoC has SOPT4[FTM0TRG0SRC] */ +# define KINETIS_SIM_HAS_SOPT4_FTM0TRG1SRC 1 /* SoC has SOPT4[FTM0TRG1SRC] */ +# define KINETIS_SIM_HAS_SOPT4_FTM1CH0SRC 3 /* SoC has SOPT4[FTM1CH0SRC] 1, 3 if SOF */ +# define KINETIS_SIM_HAS_SOPT4_FTM1FLT0 1 /* SoC has SOPT4[FTM1FLT0] */ +# define KINETIS_SIM_HAS_SOPT4_FTM1FLT1 1 /* SoC has SOPT4[FTM1FLT1] */ +# define KINETIS_SIM_HAS_SOPT4_FTM1FLT2 1 /* SoC has SOPT4[FTM1FLT2] */ +# define KINETIS_SIM_HAS_SOPT4_FTM1FLT3 1 /* SoC has SOPT4[FTM1FLT3] */ +# define KINETIS_SIM_HAS_SOPT4_FTM2CH0SRC 1 /* SoC has SOPT4[FTM2CH0SRC] */ +# undef KINETIS_SIM_HAS_SOPT4_FTM2CH1SRC /* SoC has SOPT4[FTM2CH1SRC] */ +# define KINETIS_SIM_HAS_SOPT4_FTM2FLT0 1 /* SoC has SOPT4[FTM2FLT0] */ +# define KINETIS_SIM_HAS_SOPT4_FTM2FLT1 1 /* SoC has SOPT4[FTM2FLT1] */ +# define KINETIS_SIM_HAS_SOPT4_FTM2FLT2 1 /* SoC has SOPT4[FTM2FLT2] */ +# define KINETIS_SIM_HAS_SOPT4_FTM2FLT3 1 /* SoC has SOPT4[FTM2FLT3] */ +# define KINETIS_SIM_HAS_SOPT4_FTM3CH0SRC 1 /* SoC has SOPT4[FTM3CH0SRC] */ +# define KINETIS_SIM_HAS_SOPT4_FTM3FLT0 1 /* SoC has SOPT4[FTM3FLT0] */ +# define KINETIS_SIM_HAS_SOPT4_FTM3FLT1 1 /* SoC has SOPT4[FTM3FLT1] */ +# define KINETIS_SIM_HAS_SOPT4_FTM3FLT2 1 /* SoC has SOPT4[FTM3FLT2] */ +# define KINETIS_SIM_HAS_SOPT4_FTM3FLT3 1 /* SoC has SOPT4[FTM3FLT3] */ +# define KINETIS_SIM_HAS_SOPT4_FTM3TRG0SRC 1 /* SoC has SOPT4[FTM3TRG0SRC] */ +# define KINETIS_SIM_HAS_SOPT4_FTM3TRG1SRC 1 /* SoC has SOPT4[FTM3TRG1SRC] */ +# define KINETIS_SIM_HAS_SOPT4_TPM0CLKSEL 1 /* SoC has SOPT4[TPM0CLKSEL] */ +# define KINETIS_SIM_HAS_SOPT4_TPM1CH0SRC 1 /* SoC has SOPT4[TPM1CH0SRC] */ +# define KINETIS_SIM_HAS_SOPT4_TPM1CLKSEL 1 /* SoC has SOPT4[TPM1CLKSEL] */ +# define KINETIS_SIM_HAS_SOPT4_TPM2CH0SRC 1 /* SoC has SOPT4[TPM2CH0SRC] */ +# define KINETIS_SIM_HAS_SOPT4_TPM2CLKSEL 1 /* SoC has SOPT4[TPM2CLKSEL] */ +# define KINETIS_SIM_HAS_SOPT5 1 /* SoC has SOPT5 Register */ +# undef KINETIS_SIM_HAS_SOPT5_LPUART0RXSRC /* SoC has SOPT5[LPUART0RXSRC] */ +# undef KINETIS_SIM_HAS_SOPT5_LPUART0TXSRC /* SoC has SOPT5[LPUART0TXSRC] */ +# undef KINETIS_SIM_HAS_SOPT6 /* SoC has SOPT6 Register */ +# undef KINETIS_SIM_HAS_SOPT6_MCC /* SoC has SOPT6[MCC] */ +# undef KINETIS_SIM_HAS_SOPT6_PCR /* SoC has SOPT6[PCR] */ +# undef KINETIS_SIM_HAS_SOPT6_RSTFLTSEL /* SoC has SOPT6[RSTFLTSEL] */ +# undef KINETIS_SIM_HAS_SOPT6_RSTFLTEN /* SoC has SOPT6[RSTFLTEN] */ +# define KINETIS_SIM_HAS_SOPT7 1 /* SoC has SOPT7 Register */ +# define KINETIS_SIM_HAS_SOPT7_ADC0ALTTRGSEL 1 /* SoC has SOPT7[ADC0ALTTRGSEL] */ +# define KINETIS_SIM_HAS_SOPT7_ADC1ALTTRGSEL 1 /* SoC has SOPT7[ADC1ALTTRGSEL] */ +# define KINETIS_SIM_HAS_SOPT7_ADC0PRETRGSEL 1 /* SoC has SOPT7[ADC0PRETRGSEL] */ +# define KINETIS_SIM_HAS_SOPT7_ADC1PRETRGSEL 1 /* SoC has SOPT7[ADC1PRETRGSEL] */ +# undef KINETIS_SIM_HAS_SOPT7_ADC2PRETRGSEL /* SoC has SOPT7[ADC2PRETRGSEL] */ +# undef KINETIS_SIM_HAS_SOPT7_ADC3PRETRGSEL /* SoC has SOPT7[ADC3PRETRGSEL] */ +# define KINETIS_SIM_HAS_SOPT7_ADC0TRGSEL 14 /* SoC has 10 SOPT7[ADC0TRGSEL] */ +# define KINETIS_SIM_HAS_SOPT7_ADC1TRGSEL 14 /* SoC has 10 SOPT7[ADC1TRGSEL] */ +# undef KINETIS_SIM_HAS_SOPT7_ADC2TRGSEL /* SoC has 10 SOPT7[ADC2TRGSEL] */ +# undef KINETIS_SIM_HAS_SOPT7_ADC3TRGSEL /* SoC has 10 SOPT7[ADC3TRGSEL] */ +# define KINETIS_SIM_SOPT7_ADC0ALTTRGEN 1 /* ADC0 alternate trigger enable */ +# define KINETIS_SIM_SOPT7_ADC1ALTTRGEN 1 /* ADC1 alternate trigger enable */ +# undef KINETIS_SIM_SOPT7_ADC2ALTTRGEN /* ADC2 alternate trigger enable */ +# undef KINETIS_SIM_SOPT7_ADC3ALTTRGEN /* ADC3 alternate trigger enable */ +# undef KINETIS_SIM_HAS_SOPT8 /* SoC has SOPT8 Register */ +# undef KINETIS_SIM_HAS_SOPT8_FTM0SYNCBIT /* SoC has SOPT8[FTM0SYNCBIT] */ +# undef KINETIS_SIM_HAS_SOPT8_FTM1SYNCBIT /* SoC has SOPT8[FTM1SYNCBIT] */ +# undef KINETIS_SIM_HAS_SOPT8_FTM2SYNCBIT /* SoC has SOPT8[FTM2SYNCBIT] */ +# undef KINETIS_SIM_HAS_SOPT8_FTM3SYNCBIT /* SoC has SOPT8[FTM3SYNCBIT] */ +# undef KINETIS_SIM_HAS_SOPT8_FTM0OCH0SRC /* SoC has SOPT8[FTM0OCH0SRC] */ +# undef KINETIS_SIM_HAS_SOPT8_FTM0OCH1SRC /* SoC has SOPT8[FTM0OCH1SRC] */ +# undef KINETIS_SIM_HAS_SOPT8_FTM0OCH2SRC /* SoC has SOPT8[FTM0OCH2SRC] */ +# undef KINETIS_SIM_HAS_SOPT8_FTM0OCH3SRC /* SoC has SOPT8[FTM0OCH3SRC] */ +# undef KINETIS_SIM_HAS_SOPT8_FTM0OCH4SRC /* SoC has SOPT8[FTM0OCH4SRC] */ +# undef KINETIS_SIM_HAS_SOPT8_FTM0OCH5SRC /* SoC has SOPT8[FTM0OCH5SRC] */ +# undef KINETIS_SIM_HAS_SOPT8_FTM0OCH6SRC /* SoC has SOPT8[FTM0OCH6SRC] */ +# undef KINETIS_SIM_HAS_SOPT8_FTM0OCH7SRC /* SoC has SOPT8[FTM0OCH7SRC] */ +# undef KINETIS_SIM_HAS_SOPT8_FTM3OCH0SRC /* SoC has SOPT8[FTM3OCH0SRC] */ +# undef KINETIS_SIM_HAS_SOPT8_FTM3OCH1SRC /* SoC has SOPT8[FTM3OCH1SRC] */ +# undef KINETIS_SIM_HAS_SOPT8_FTM3OCH2SRC /* SoC has SOPT8[FTM3OCH2SRC] */ +# undef KINETIS_SIM_HAS_SOPT8_FTM3OCH3SRC /* SoC has SOPT8[FTM3OCH3SRC] */ +# undef KINETIS_SIM_HAS_SOPT8_FTM3OCH4SRC /* SoC has SOPT8[FTM3OCH4SRC] */ +# undef KINETIS_SIM_HAS_SOPT8_FTM3OCH5SRC /* SoC has SOPT8[FTM3OCH5SRC] */ +# undef KINETIS_SIM_HAS_SOPT8_FTM3OCH6SRC /* SoC has SOPT8[FTM3OCH6SRC] */ +# undef KINETIS_SIM_HAS_SOPT8_FTM3OCH7SRC /* SoC has SOPT8[FTM3OCH7SRC] */ +# undef KINETIS_SIM_HAS_SOPT9 /* SoC has SOPT9 Register */ +# undef KINETIS_SIM_HAS_SOPT9_TPM1CH0SRC /* SoC has SOPT9[TPM1CH0SRC] */ +# undef KINETIS_SIM_HAS_SOPT9_TPM2CH0SRC /* SoC has SOPT9[TPM2CH0SRC] */ +# undef KINETIS_SIM_HAS_SOPT9_TPM1CLKSEL /* SoC has SOPT9[TPM1CLKSEL] */ +# undef KINETIS_SIM_HAS_SOPT9_TPM2CLKSEL /* SoC has SOPT9[TPM2CLKSEL] */ +# define KINETIS_SIM_HAS_SDID 1 /* SoC has SDID Register */ +# define KINETIS_SIM_HAS_SDID_DIEID 1 /* SoC has SDID[DIEID] */ +# define KINETIS_SIM_HAS_SDID_FAMID 1 /* SoC has SDID[FAMID] */ +# define KINETIS_SIM_HAS_SDID_FAMILYID 1 /* SoC has SDID[FAMILYID] */ +# define KINETIS_SIM_HAS_SDID_SERIESID 1 /* SoC has SDID[SERIESID] */ +# undef KINETIS_SIM_HAS_SDID_SRAMSIZE /* SoC has SDID[SRAMSIZE] */ +# define KINETIS_SIM_HAS_SDID_SUBFAMID 1 /* SoC has SDID[SUBFAMID] */ +# define KINETIS_SIM_HAS_SCGC1 1 /* SoC has _SCGC1 Register */ +# define KINETIS_SIM_HAS_SCGC1_UART5 1 /* SoC has SCGC1[UART5] */ +# define KINETIS_SIM_HAS_SCGC1_UART4 1 /* SoC has SCGC1[UART4] */ +# undef KINETIS_SIM_HAS_SCGC1_I2C3 /* SoC has SCGC1[I2C3] */ +# define KINETIS_SIM_HAS_SCGC1_I2C2 1 /* SoC has SCGC1[I2C2] */ +# undef KINETIS_SIM_HAS_SCGC1_OSC1 /* SoC has SCGC1[OSC1] */ +# define KINETIS_SIM_HAS_SCGC2 1 /* SoC has _SCGC2 Register */ +# define KINETIS_SIM_HAS_SCGC2 1 /* SoC has SCGC2 Register */ +# define KINETIS_SIM_HAS_SCGC2_ENET 1 /* SoC has SCGC2[ENET] */ +# undef KINETIS_SIM_HAS_SCGC2_LPUART0 /* SoC has SCGC2[LPUART0] */ +# undef KINETIS_SIM_HAS_SCGC2_TPM1 /* SoC has SCGC2[TPM1] */ +# undef KINETIS_SIM_HAS_SCGC2_TPM2 /* SoC has SCGC2[TPM2] */ +# define KINETIS_SIM_HAS_SCGC3 1 /* SoC has SCGC3 Register */ +# define KINETIS_SIM_HAS_SCGC3_RNGA 1 /* SoC has SCGC3[RNGA] */ +# undef KINETIS_SIM_HAS_SCGC3_USBHS /* SoC has SCGC3[USBHS] */ +# undef KINETIS_SIM_HAS_SCGC3_USBHSPHY /* SoC has SCGC3[USBHSPHY] */ +# undef KINETIS_SIM_HAS_SCGC3_USBHSDCD /* SoC has SCGC3[USBHSDCD] */ +# undef KINETIS_SIM_HAS_SCGC3_FLEXCAN1 /* SoC has SCGC3[FLEXCAN1] */ +# undef KINETIS_SIM_HAS_SCGC3_NFC /* SoC has SCGC3[NFC] */ +# define KINETIS_SIM_HAS_SCGC3_SPI2 1 /* SoC has SCGC3[SPI2] */ +# undef KINETIS_SIM_HAS_SCGC3_SAI1 /* SoC has SCGC3[SAI1] */ +# define KINETIS_SIM_HAS_SCGC3_SDHC 1 /* SoC has SCGC3[SDHC] */ +# define KINETIS_SIM_HAS_SCGC3_FTM2 1 /* SoC has SCGC3[FTM2] */ +# define KINETIS_SIM_HAS_SCGC3_FTM3 1 /* SoC has SCGC3[FTM3] */ +# define KINETIS_SIM_HAS_SCGC3_ADC1 1 /* SoC has SCGC3[ADC1] */ +# undef KINETIS_SIM_HAS_SCGC3_ADC3 /* SoC has SCGC3[ADC3] */ +# undef KINETIS_SIM_HAS_SCGC3_SLCD /* SoC has SCGC3[SLCD] */ +# define KINETIS_SIM_HAS_SCGC4 1 /* SoC has SCGC4 Register */ +# undef KINETIS_SIM_HAS_SCGC4_LLWU /* SoC has SCGC4[LLWU] clock gate */ +# define KINETIS_SIM_HAS_SCGC4_UART0 1 /* SoC has SCGC4[UART0] */ +# define KINETIS_SIM_HAS_SCGC4_UART1 1 /* SoC has SCGC4[UART1] */ +# define KINETIS_SIM_HAS_SCGC4_UART2 1 /* SoC has SCGC4[UART2] */ +# define KINETIS_SIM_HAS_SCGC4_UART3 1 /* SoC has SCGC4[UART3] */ +# define KINETIS_SIM_HAS_SCGC5 1 /* SoC has _SCGC5 Register */ +# undef KINETIS_SIM_HAS_SCGC5_REGFILE /* SoC has SCGC5[REGFILE] */ +# undef KINETIS_SIM_HAS_SCGC5_TSI /* SoC has SCGC5[TSI] */ +# undef KINETIS_SIM_HAS_SCGC5_PORTF /* SoC has SCGC5[PORTF] */ +# define KINETIS_SIM_HAS_SCGC6 1 /* SoC has SCGC6 Register */ +# define KINETIS_SIM_HAS_SCGC6_FTFL 1 /* SoC has SCGC6[FTFL] */ +# undef KINETIS_SIM_HAS_SCGC6_DMAMUX1 /* SoC has SCGC6[DEMUX1] */ +# undef KINETIS_SIM_HAS_SCGC6_USBHS /* SoC has SCGC6[USBHS] */ +# define KINETIS_SIM_HAS_SCGC6_RNGA 1 /* SoC has SCGC6[RNGA] */ +# define KINETIS_SIM_HAS_SCGC6_FTM2 1 /* SoC has SCGC6[FTM2] */ +# undef KINETIS_SIM_HAS_SCGC6_ADC2 /* SoC has SCGC6[ADC2] */ +# define KINETIS_SIM_HAS_SCGC6_DAC0 1 /* SoC has SCGC6[DAC0] */ +# define KINETIS_SIM_HAS_SCGC7 1 /* SoC has SCGC7 Register */ +# define KINETIS_SIM_HAS_SCGC7_FLEXBUS 1 /* SoC has SCGC7[FLEXBUS] */ +# define KINETIS_SIM_HAS_SCGC7_DMA 1 /* SoC has SCGC7[DMS] */ +# define KINETIS_SIM_HAS_SCGC7_MPU 1 /* SoC has SCGC7[MPU] */ +# undef KINETIS_SIM_HAS_SCGC7_SDRAMC /* SoC has SCGC7[SDRAMC] */ +# define KINETIS_SIM_HAS_CLKDIV1 1 /* SoC has CLKDIV1 Register */ +# define KINETIS_SIM_HAS_CLKDIV1_OUTDIV2 1 /* SoC has CLKDIV1[OUTDIV2] */ +# define KINETIS_SIM_HAS_CLKDIV1_OUTDIV3 1 /* SoC has CLKDIV1[OUTDIV3] */ +# define KINETIS_SIM_HAS_CLKDIV1_OUTDIV4 1 /* SoC has CLKDIV1[OUTDIV4] */ +# undef KINETIS_SIM_HAS_CLKDIV1_OUTDIV5 /* SoC has CLKDIV1[OUTDIV5] */ +# define KINETIS_SIM_HAS_CLKDIV2 1 /* SoC has CLKDIV2 Register */ +# define KINETIS_SIM_HAS_CLKDIV2_USBDIV 1 /* SoC has CLKDIV2[USBDIV] */ +# define KINETIS_SIM_HAS_CLKDIV2_USBFRAC 1 /* SoC has CLKDIV2[USBFRAC] */ +# undef KINETIS_SIM_HAS_CLKDIV2_USBFSDIV /* SoC has CLKDIV2[USBFSDIV] */ +# undef KINETIS_SIM_HAS_CLKDIV2_USBFSFRAC /* SoC has CLKDIV2[USBFSFRAC] */ +# undef KINETIS_SIM_HAS_CLKDIV2_USBHSDIV /* SoC has CLKDIV2[USBHSDIV] */ +# undef KINETIS_SIM_HAS_CLKDIV2_USBHSFRAC /* SoC has CLKDIV2[USBHSFRAC] */ +# undef KINETIS_SIM_HAS_CLKDIV2_I2SDIV /* SoC has CLKDIV2[I2SDIV] */ +# undef KINETIS_SIM_HAS_CLKDIV2_I2SFRAC /* SoC has CLKDIV2[I2SFRAC] */ +# define KINETIS_SIM_HAS_FCFG1 1 /* SoC has FCFG1 Register */ +# define KINETIS_SIM_HAS_FCFG1_DEPART 1 /* SoC has FCFG1[DEPART] */ +# define KINETIS_SIM_HAS_FCFG1_EESIZE 1 /* SoC has FCFG1[EESIZE] */ +# define KINETIS_SIM_HAS_FCFG1_FLASHDIS 1 /* SoC has FCFG1[FLASHDIS] */ +# define KINETIS_SIM_HAS_FCFG1_FLASHDOZE 1 /* SoC has FCFG1[FLASHDOZE] */ +# undef KINETIS_SIM_HAS_FCFG1_FTFDIS /* SoC has FCFG1[FTFDIS] */ +# define KINETIS_SIM_HAS_FCFG1_NVMSIZE 1 /* SoC has FCFG1[NVMSIZE] */ +# define KINETIS_SIM_HAS_FCFG2 1 /* SoC has FCFG2 Register */ +# define KINETIS_SIM_HAS_FCFG2_MAXADDR0 7 /* SoC has n bit of FCFG2[MAXADDR0] */ +# define KINETIS_SIM_HAS_FCFG2_MAXADDR1 7 /* SoC has n bit of FCFG2[MAXADDR1] */ +# define KINETIS_SIM_HAS_FCFG2_PFLSH 1 /* SoC has FCFG2[PFLSH] */ +# undef KINETIS_SIM_HAS_FCFG2_SWAPPFLSH /* SoC has FCFG2[SWAPPFLSH] */ +# define KINETIS_SIM_HAS_UIDH 1 /* SoC has UIDH Register */ +# define KINETIS_SIM_HAS_UIDMH 1 /* SoC has UIDMH Register */ +# define KINETIS_SIM_HAS_UIDML 1 /* SoC has UIDML Register */ +# define KINETIS_SIM_HAS_UIDL 1 /* SoC has UIDL Register */ +# undef KINETIS_SIM_HAS_CLKDIV3 /* SoC has CLKDIV3 Register */ +# undef KINETIS_SIM_HAS_CLKDIV3_PLLFLLDIV /* SoC has CLKDIV3[PLLFLLDIV] */ +# undef KINETIS_SIM_HAS_CLKDIV3_PLLFLLFRAC /* SoC has CLKDIV3[PLLFLLFRAC] */ +# undef KINETIS_SIM_HAS_CLKDIV4 /* SoC has CLKDIV4 Register */ +# undef KINETIS_SIM_HAS_CLKDIV4_TRACEDIV /* SoC has CLKDIV4[TRACEDIV] */ +# undef KINETIS_SIM_HAS_CLKDIV4_TRACEFRAC /* SoC has CLKDIV4[TRACEFRAC] */ +# undef KINETIS_SIM_HAS_CLKDIV4_NFCDIV /* SoC has CLKDIV4[NFCDIV] */ +# undef KINETIS_SIM_HAS_CLKDIV4_NFCFRAC /* SoC has CLKDIV4[NFCFRAC] */ +# undef KINETIS_SIM_HAS_MCR /* SoC has MCR Register */ + +/* MK66F N/X 1M0/2M0 V MD/LQ 18 + * + * --------------- ------- --- ------- ------- ------ ------ ------ ----- + * PART NUMBER CPU PIN PACKAGE TOTAL PROGRAM EEPROM SRAM GPIO + * FREQ CNT FLASH FLASH + * --------------- ------- --- ------- ------- ------ ------ ------ ----- + * MK66FN2M0VMD18 180 MHz 144 MAPBGA 2 MB — — KB 260 KB 100 + * MK66FX1M0VMD18 180 MHz 144 MAPBGA 1.25 MB 1 MB 4 KB 256 KB 100 + * MK66FN2M0VLQ18 180 MHz 144 LQFP 2 MB — — KB 260 KB 100 + * MK66FX1M0VLQ18 180 MHz 144 LQFP 1.25 MB 1 MB 4 KB 256 KB 100 + */ + +#elif defined(CONFIG_ARCH_CHIP_MK66FN2M0VMD18) || defined(CONFIG_ARCH_CHIP_MK66FX1M0VMD18) || \ + defined(CONFIG_ARCH_CHIP_MK66FN2M0VLQ18) || defined(CONFIG_ARCH_CHIP_MK66FX1M0VLQ18) + +/* Verified to Document Number: Document Number: K66P144M180SF5RMV2 Rev. 2, May 2015 */ + +# define KINETIS_SIM_VERSION KINETIS_SIM_VERSION_06 + +/* SIM Register Configuration */ + +# define KINETIS_SIM_HAS_SOPT1 1 /* SoC has SOPT1 Register */ +# undef KINETIS_SIM_HAS_SOPT1_OSC32KOUT /* SoC has SOPT1[OSC32KOUT] */ +# define KINETIS_SIM_HAS_SOPT1_OSC32KSEL 1 /* SoC has SOPT1[OSC32KSEL] */ +# define KINETIS_SIM_HAS_SOPT1_OSC32KSEL_BITS 2 /* SoC has 1 bit SOPT1[OSC32KSEL] */ +# define KINETIS_SIM_HAS_SOPT1_RAMSIZE 1 /* SoC has SOPT1[RAMSIZE] */ +# define KINETIS_SIM_HAS_SOPT1_USBREGEN 1 /* SoC has SOPT1[USBREGEN] */ +# define KINETIS_SIM_HAS_SOPT1_USBSSTBY 1 /* SoC has SOPT1[USBSSTBY] */ +# define KINETIS_SIM_HAS_SOPT1_USBVSTBY 1 /* SoC has SOPT1[USBVSTBY] */ +# define KINETIS_SIM_HAS_SOPT1CFG /* SoC has SOPT1CFG Register */ +# define KINETIS_SIM_HAS_SOPT1CFG_URWE 1 /* SoC has SOPT1CFG[URWE] */ +# define KINETIS_SIM_HAS_SOPT1CFG_USSWE 1 /* SoC has SOPT1CFG[USSWE] */ +# define KINETIS_SIM_HAS_SOPT1CFG_UVSWE 1 /* SoC has SOPT1CFG[UVSWE] */ +# define KINETIS_SIM_HAS_USBPHYCTL 1 /* SoC has USBPHYCTL Register */ +# define KINETIS_SIM_HAS_USBPHYCTL_USB3VOUTTRG 1 /* SoC has USBPHYCTL[USB3VOUTTRG] */ +# define KINETIS_SIM_HAS_USBPHYCTL_USBDISILIM 1 /* SoC has USBPHYCTL[USBDISILIM] */ +# define KINETIS_SIM_HAS_USBPHYCTL_USBVREGPD 1 /* SoC has USBPHYCTL[USBVREGPD] */ +# define KINETIS_SIM_HAS_USBPHYCTL_USBVREGSEL 1 /* SoC has USBPHYCTL[USBVREGSEL] */ +# define KINETIS_SIM_HAS_SOPT2 1 /* SoC has SOPT2 Register */ +# define KINETIS_SIM_HAS_SOPT2_FBSL 1 /* SoC has SOPT2[FBSL] */ +# undef KINETIS_SIM_HAS_SOPT2_CMTUARTPAD /* SoC has SOPT2[CMTUARTPAD] */ +# define KINETIS_SIM_HAS_SOPT2_FLEXIOSRC 1 /* SoC has SOPT2[FLEXIOSRC] */ +# define KINETIS_SIM_HAS_SOPT2_LPUARTSRC 1 /* SoC has SOPT2[LPUARTSRC] */ +# define KINETIS_SIM_HAS_SOPT2_PLLFLLSEL 1 /* SoC has SOPT2[PLLFLLSEL] */ +# define KINETIS_SIM_HAS_SOPT2_PLLFLLSEL_BITS 2 /* SoC has 2 bits of SOPT2[PLLFLLSEL] */ +# undef KINETIS_SIM_HAS_SOPT2_PTD7PAD /* SoC has SOPT2[PTD7PAD] */ +# define KINETIS_SIM_HAS_SOPT2_RMIISRC 1 /* SoC has SOPT2[RMIISRC] */ +# define KINETIS_SIM_HAS_SOPT2_RTCCLKOUTSEL 1 /* SoC has SOPT2[RTCCLKOUTSEL] */ +# define KINETIS_SIM_HAS_SOPT2_CLKOUTSEL 1 /* SoC has SOPT2[CLKOUTSEL] */ +# define KINETIS_SIM_HAS_SOPT2_SDHCSRC 1 /* SoC has SOPT2[SDHCSRC] */ +# undef KINETIS_SIM_HAS_SOPT2_NFCSRC /* SoC has SOPT2[NFCSRC] */ +# undef KINETIS_SIM_HAS_SOPT2_I2SSRC /* SoC has SOPT2[I2SSRC] */ +# define KINETIS_SIM_HAS_SOPT2_TIMESRC 1 /* SoC has SOPT2[TIMESRC] */ +# define KINETIS_SIM_HAS_SOPT2_TPMSRC 1 /* SoC has SOPT2[TPMSRC] */ +# undef KINETIS_SIM_HAS_SOPT2_USBFSRC /* SoC has SOPT2[USBFSRC] */ +# define KINETIS_SIM_HAS_SOPT2_TRACECLKSEL 1 /* SoC has SOPT2[TRACECLKSEL] */ +# define KINETIS_SIM_HAS_SOPT2_USBREGEN 1 /* SoC has SOPT2[USBREGEN] */ +# define KINETIS_SIM_HAS_SOPT2_USBSLSRC 1 /* SoC has SOPT2[USBSLSRC] */ +# undef KINETIS_SIM_HAS_SOPT2_USBHSRC /* SoC has SOPT2[USBHSRC] */ +# define KINETIS_SIM_HAS_SOPT2_USBSRC 1 /* SoC has SOPT2[USBSRC] */ +# undef KINETIS_SIM_HAS_SOPT2_MCGCLKSEL /* SoC has SOPT2[MCGCLKSEL] */ +# define KINETIS_SIM_HAS_SOPT4 1 /* SoC has SOPT4 Register */ +# define KINETIS_SIM_HAS_SOPT4_FTM0FLT0 1 /* SoC has SOPT4[FTM0FLT0] */ +# define KINETIS_SIM_HAS_SOPT4_FTM0FLT1 1 /* SoC has SOPT4[FTM0FLT1] */ +# define KINETIS_SIM_HAS_SOPT4_FTM0FLT2 1 /* SoC has SOPT4[FTM0FLT2] */ +# define KINETIS_SIM_HAS_SOPT4_FTM0FLT3 1 /* SoC has SOPT4[FTM0FLT3] */ +# define KINETIS_SIM_HAS_SOPT4_FTM0TRG0SRC 1 /* SoC has SOPT4[FTM0TRG0SRC] */ +# define KINETIS_SIM_HAS_SOPT4_FTM0TRG1SRC 1 /* SoC has SOPT4[FTM0TRG1SRC] */ +# define KINETIS_SIM_HAS_SOPT4_FTM1CH0SRC 3 /* SoC has SOPT4[FTM1CH0SRC] 1, 3 if SOF */ +# define KINETIS_SIM_HAS_SOPT4_FTM1FLT0 1 /* SoC has SOPT4[FTM1FLT0] */ +# define KINETIS_SIM_HAS_SOPT4_FTM1FLT1 1 /* SoC has SOPT4[FTM1FLT1] */ +# define KINETIS_SIM_HAS_SOPT4_FTM1FLT2 1 /* SoC has SOPT4[FTM1FLT2] */ +# define KINETIS_SIM_HAS_SOPT4_FTM1FLT3 1 /* SoC has SOPT4[FTM1FLT3] */ +# define KINETIS_SIM_HAS_SOPT4_FTM2CH0SRC 1 /* SoC has SOPT4[FTM2CH0SRC] */ +# define KINETIS_SIM_HAS_SOPT4_FTM2CH1SRC 1 /* SoC has SOPT4[FTM2CH1SRC] */ +# define KINETIS_SIM_HAS_SOPT4_FTM2FLT0 1 /* SoC has SOPT4[FTM2FLT0] */ +# define KINETIS_SIM_HAS_SOPT4_FTM2FLT1 1 /* SoC has SOPT4[FTM2FLT1] */ +# define KINETIS_SIM_HAS_SOPT4_FTM2FLT2 1 /* SoC has SOPT4[FTM2FLT2] */ +# define KINETIS_SIM_HAS_SOPT4_FTM2FLT3 1 /* SoC has SOPT4[FTM2FLT3] */ +# define KINETIS_SIM_HAS_SOPT4_FTM3CH0SRC 1 /* SoC has SOPT4[FTM3CH0SRC] */ +# define KINETIS_SIM_HAS_SOPT4_FTM3FLT0 1 /* SoC has SOPT4[FTM3FLT0] */ +# define KINETIS_SIM_HAS_SOPT4_FTM3FLT1 1 /* SoC has SOPT4[FTM3FLT1] */ +# define KINETIS_SIM_HAS_SOPT4_FTM3FLT2 1 /* SoC has SOPT4[FTM3FLT2] */ +# define KINETIS_SIM_HAS_SOPT4_FTM3FLT3 1 /* SoC has SOPT4[FTM3FLT3] */ +# define KINETIS_SIM_HAS_SOPT4_FTM3TRG0SRC 1 /* SoC has SOPT4[FTM3TRG0SRC] */ +# define KINETIS_SIM_HAS_SOPT4_FTM3TRG1SRC 1 /* SoC has SOPT4[FTM3TRG1SRC] */ +# define KINETIS_SIM_HAS_SOPT4_TPM0CLKSEL 1 /* SoC has SOPT4[TPM0CLKSEL] */ +# define KINETIS_SIM_HAS_SOPT4_TPM1CH0SRC 1 /* SoC has SOPT4[TPM1CH0SRC] */ +# define KINETIS_SIM_HAS_SOPT4_TPM1CLKSEL 1 /* SoC has SOPT4[TPM1CLKSEL] */ +# define KINETIS_SIM_HAS_SOPT4_TPM2CH0SRC 1 /* SoC has SOPT4[TPM2CH0SRC] */ +# define KINETIS_SIM_HAS_SOPT4_TPM2CLKSEL 1 /* SoC has SOPT4[TPM2CLKSEL] */ +# define KINETIS_SIM_HAS_SOPT5 1 /* SoC has SOPT5 Register */ +# define KINETIS_SIM_HAS_SOPT5_LPUART0RXSRC 1 /* SoC has SOPT5[LPUART0RXSRC] */ +# define KINETIS_SIM_HAS_SOPT5_LPUART0TXSRC 1 /* SoC has SOPT5[LPUART0TXSRC] */ +# undef KINETIS_SIM_HAS_SOPT6 /* SoC has SOPT6 Register */ +# undef KINETIS_SIM_HAS_SOPT6_MCC /* SoC has SOPT6[MCC] */ +# undef KINETIS_SIM_HAS_SOPT6_PCR /* SoC has SOPT6[PCR] */ +# undef KINETIS_SIM_HAS_SOPT6_RSTFLTSEL /* SoC has SOPT6[RSTFLTSEL] */ +# undef KINETIS_SIM_HAS_SOPT6_RSTFLTEN /* SoC has SOPT6[RSTFLTEN] */ +# define KINETIS_SIM_HAS_SOPT7 1 /* SoC has SOPT7 Register */ +# define KINETIS_SIM_HAS_SOPT7_ADC0ALTTRGSEL 1 /* SoC has SOPT7[ADC0ALTTRGSEL] */ +# define KINETIS_SIM_HAS_SOPT7_ADC1ALTTRGSEL 1 /* SoC has SOPT7[ADC1ALTTRGSEL] */ +# define KINETIS_SIM_HAS_SOPT7_ADC0PRETRGSEL 1 /* SoC has SOPT7[ADC0PRETRGSEL] */ +# define KINETIS_SIM_HAS_SOPT7_ADC1PRETRGSEL 1 /* SoC has SOPT7[ADC1PRETRGSEL] */ +# undef KINETIS_SIM_HAS_SOPT7_ADC2PRETRGSEL /* SoC has SOPT7[ADC2PRETRGSEL] */ +# undef KINETIS_SIM_HAS_SOPT7_ADC3PRETRGSEL /* SoC has SOPT7[ADC3PRETRGSEL] */ +# define KINETIS_SIM_HAS_SOPT7_ADC0TRGSEL 15 /* SoC has 10 SOPT7[ADC0TRGSEL] */ +# define KINETIS_SIM_HAS_SOPT7_ADC1TRGSEL 15 /* SoC has 10 SOPT7[ADC1TRGSEL] */ +# undef KINETIS_SIM_HAS_SOPT7_ADC2TRGSEL /* SoC has 10 SOPT7[ADC2TRGSEL] */ +# undef KINETIS_SIM_HAS_SOPT7_ADC3TRGSEL /* SoC has 10 SOPT7[ADC3TRGSEL] */ +# define KINETIS_SIM_SOPT7_ADC0ALTTRGEN 1 /* ADC0 alternate trigger enable */ +# define KINETIS_SIM_SOPT7_ADC1ALTTRGEN 1 /* ADC1 alternate trigger enable */ +# undef KINETIS_SIM_SOPT7_ADC2ALTTRGEN /* ADC2 alternate trigger enable */ +# undef KINETIS_SIM_SOPT7_ADC3ALTTRGEN /* ADC3 alternate trigger enable */ +# define KINETIS_SIM_HAS_SOPT8 1 /* SoC has SOPT8 Register */ +# define KINETIS_SIM_HAS_SOPT8_FTM0SYNCBIT 1 /* SoC has SOPT8[FTM0SYNCBIT] */ +# define KINETIS_SIM_HAS_SOPT8_FTM1SYNCBIT 1 /* SoC has SOPT8[FTM1SYNCBIT] */ +# define KINETIS_SIM_HAS_SOPT8_FTM2SYNCBIT 1 /* SoC has SOPT8[FTM2SYNCBIT] */ +# define KINETIS_SIM_HAS_SOPT8_FTM3SYNCBIT 1 /* SoC has SOPT8[FTM3SYNCBIT] */ +# define KINETIS_SIM_HAS_SOPT8_FTM0OCH0SRC 1 /* SoC has SOPT8[FTM0OCH0SRC] */ +# define KINETIS_SIM_HAS_SOPT8_FTM0OCH1SRC 1 /* SoC has SOPT8[FTM0OCH1SRC] */ +# define KINETIS_SIM_HAS_SOPT8_FTM0OCH2SRC 1 /* SoC has SOPT8[FTM0OCH2SRC] */ +# define KINETIS_SIM_HAS_SOPT8_FTM0OCH3SRC 1 /* SoC has SOPT8[FTM0OCH3SRC] */ +# define KINETIS_SIM_HAS_SOPT8_FTM0OCH4SRC 1 /* SoC has SOPT8[FTM0OCH4SRC] */ +# define KINETIS_SIM_HAS_SOPT8_FTM0OCH5SRC 1 /* SoC has SOPT8[FTM0OCH5SRC] */ +# define KINETIS_SIM_HAS_SOPT8_FTM0OCH6SRC 1 /* SoC has SOPT8[FTM0OCH6SRC] */ +# define KINETIS_SIM_HAS_SOPT8_FTM0OCH7SRC 1 /* SoC has SOPT8[FTM0OCH7SRC] */ +# define KINETIS_SIM_HAS_SOPT8_FTM3OCH0SRC 1 /* SoC has SOPT8[FTM3OCH0SRC] */ +# define KINETIS_SIM_HAS_SOPT8_FTM3OCH1SRC 1 /* SoC has SOPT8[FTM3OCH1SRC] */ +# define KINETIS_SIM_HAS_SOPT8_FTM3OCH2SRC 1 /* SoC has SOPT8[FTM3OCH2SRC] */ +# define KINETIS_SIM_HAS_SOPT8_FTM3OCH3SRC 1 /* SoC has SOPT8[FTM3OCH3SRC] */ +# define KINETIS_SIM_HAS_SOPT8_FTM3OCH4SRC 1 /* SoC has SOPT8[FTM3OCH4SRC] */ +# define KINETIS_SIM_HAS_SOPT8_FTM3OCH5SRC 1 /* SoC has SOPT8[FTM3OCH5SRC] */ +# define KINETIS_SIM_HAS_SOPT8_FTM3OCH6SRC 1 /* SoC has SOPT8[FTM3OCH6SRC] */ +# define KINETIS_SIM_HAS_SOPT8_FTM3OCH7SRC 1 /* SoC has SOPT8[FTM3OCH7SRC] */ +# define KINETIS_SIM_HAS_SOPT9 1 /* SoC has SOPT9 Register */ +# define KINETIS_SIM_HAS_SOPT9_TPM1CH0SRC 1 /* SoC has SOPT9[TPM1CH0SRC] */ +# define KINETIS_SIM_HAS_SOPT9_TPM2CH0SRC 1 /* SoC has SOPT9[TPM2CH0SRC] */ +# define KINETIS_SIM_HAS_SOPT9_TPM1CLKSEL 1 /* SoC has SOPT9[TPM1CLKSEL] */ +# define KINETIS_SIM_HAS_SOPT9_TPM2CLKSEL 1 /* SoC has SOPT9[TPM2CLKSEL] */ +# define KINETIS_SIM_HAS_SDID 1 /* SoC has SDID Register */ +# define KINETIS_SIM_HAS_SDID_DIEID 1 /* SoC has SDID[DIEID] */ +# define KINETIS_SIM_HAS_SDID_FAMID 1 /* SoC has SDID[FAMID] */ +# define KINETIS_SIM_HAS_SDID_FAMILYID 1 /* SoC has SDID[FAMILYID] */ +# define KINETIS_SIM_HAS_SDID_SERIESID 1 /* SoC has SDID[SERIESID] */ +# undef KINETIS_SIM_HAS_SDID_SRAMSIZE /* SoC has SDID[SRAMSIZE] */ +# define KINETIS_SIM_HAS_SDID_SUBFAMID 1 /* SoC has SDID[SUBFAMID] */ +# define KINETIS_SIM_HAS_SCGC1 1 /* SoC has _SCGC1 Register */ +# undef KINETIS_SIM_HAS_SCGC1_UART5 /* SoC has SCGC1[UART5] */ +# define KINETIS_SIM_HAS_SCGC1_UART4 1 /* SoC has SCGC1[UART4] */ +# define KINETIS_SIM_HAS_SCGC1_I2C3 1 /* SoC has SCGC1[I2C3] */ +# define KINETIS_SIM_HAS_SCGC1_I2C2 1 /* SoC has SCGC1[I2C2] */ +# undef KINETIS_SIM_HAS_SCGC1_OSC1 /* SoC has SCGC1[OSC1] */ +# define KINETIS_SIM_HAS_SCGC2 1 /* SoC has _SCGC2 Register */ +# define KINETIS_SIM_HAS_SCGC2 1 /* SoC has SCGC2 Register */ +# define KINETIS_SIM_HAS_SCGC2_ENET 1 /* SoC has SCGC2[ENET] */ +# define KINETIS_SIM_HAS_SCGC2_LPUART0 1 /* SoC has SCGC2[LPUART0] */ +# define KINETIS_SIM_HAS_SCGC2_TPM1 1 /* SoC has SCGC2[TPM1] */ +# define KINETIS_SIM_HAS_SCGC2_TPM2 1 /* SoC has SCGC2[TPM2] */ +# define KINETIS_SIM_HAS_SCGC3 1 /* SoC has SCGC3 Register */ +# define KINETIS_SIM_HAS_SCGC3_RNGA 1 /* SoC has SCGC3[RNGA] */ +# define KINETIS_SIM_HAS_SCGC3_USBHS 1 /* SoC has SCGC3[USBHS] */ +# define KINETIS_SIM_HAS_SCGC3_USBHSPHY 1 /* SoC has SCGC3[USBHSPHY] */ +# define KINETIS_SIM_HAS_SCGC3_USBHSDCD 1 /* SoC has SCGC3[USBHSDCD] */ +# define KINETIS_SIM_HAS_SCGC3_FLEXCAN1 1 /* SoC has SCGC3[FLEXCAN1] */ +# undef KINETIS_SIM_HAS_SCGC3_NFC /* SoC has SCGC3[NFC] */ +# define KINETIS_SIM_HAS_SCGC3_SPI2 1 /* SoC has SCGC3[SPI2] */ +# undef KINETIS_SIM_HAS_SCGC3_SAI1 /* SoC has SCGC3[SAI1] */ +# define KINETIS_SIM_HAS_SCGC3_SDHC 1 /* SoC has SCGC3[SDHC] */ +# define KINETIS_SIM_HAS_SCGC3_FTM2 1 /* SoC has SCGC3[FTM2] */ +# define KINETIS_SIM_HAS_SCGC3_FTM3 1 /* SoC has SCGC3[FTM3] */ +# define KINETIS_SIM_HAS_SCGC3_ADC1 1 /* SoC has SCGC3[ADC1] */ +# undef KINETIS_SIM_HAS_SCGC3_ADC3 /* SoC has SCGC3[ADC3] */ +# undef KINETIS_SIM_HAS_SCGC3_SLCD /* SoC has SCGC3[SLCD] */ +# define KINETIS_SIM_HAS_SCGC4 1 /* SoC has SCGC4 Register */ +# undef KINETIS_SIM_HAS_SCGC4_LLWU /* SoC has SCGC4[LLWU] clock gate */ +# define KINETIS_SIM_HAS_SCGC4_UART0 1 /* SoC has SCGC4[UART0] */ +# define KINETIS_SIM_HAS_SCGC4_UART1 1 /* SoC has SCGC4[UART1] */ +# define KINETIS_SIM_HAS_SCGC4_UART2 1 /* SoC has SCGC4[UART2] */ +# define KINETIS_SIM_HAS_SCGC4_UART3 1 /* SoC has SCGC4[UART3] */ +# define KINETIS_SIM_HAS_SCGC5 1 /* SoC has _SCGC5 Register */ +# undef KINETIS_SIM_HAS_SCGC5_REGFILE /* SoC has SCGC5[REGFILE] */ +# define KINETIS_SIM_HAS_SCGC5_TSI 1 /* SoC has SCGC5[TSI] */ +# undef KINETIS_SIM_HAS_SCGC5_PORTF /* SoC has SCGC5[PORTF] */ +# define KINETIS_SIM_HAS_SCGC6 1 /* SoC has SCGC6 Register */ +# define KINETIS_SIM_HAS_SCGC6_FTFL 1 /* SoC has SCGC6[FTFL] */ +# undef KINETIS_SIM_HAS_SCGC6_DMAMUX1 /* SoC has SCGC6[DEMUX1] */ +# undef KINETIS_SIM_HAS_SCGC6_USBHS /* SoC has SCGC6[USBHS] */ +# define KINETIS_SIM_HAS_SCGC6_RNGA 1 /* SoC has SCGC6[RNGA] */ +# define KINETIS_SIM_HAS_SCGC6_FTM2 1 /* SoC has SCGC6[FTM2] */ +# undef KINETIS_SIM_HAS_SCGC6_ADC2 /* SoC has SCGC6[ADC2] */ +# define KINETIS_SIM_HAS_SCGC6_DAC0 1 /* SoC has SCGC6[DAC0] */ +# define KINETIS_SIM_HAS_SCGC7 1 /* SoC has SCGC7 Register */ +# define KINETIS_SIM_HAS_SCGC7_FLEXBUS 1 /* SoC has SCGC7[FLEXBUS] */ +# define KINETIS_SIM_HAS_SCGC7_DMA 1 /* SoC has SCGC7[DMS] */ +# define KINETIS_SIM_HAS_SCGC7_MPU 1 /* SoC has SCGC7[MPU] */ +# define KINETIS_SIM_HAS_SCGC7_SDRAMC 1 /* SoC has SCGC7[SDRAMC] */ +# define KINETIS_SIM_HAS_CLKDIV1 1 /* SoC has CLKDIV1 Register */ +# define KINETIS_SIM_HAS_CLKDIV1_OUTDIV2 1 /* SoC has CLKDIV1[OUTDIV2] */ +# define KINETIS_SIM_HAS_CLKDIV1_OUTDIV3 1 /* SoC has CLKDIV1[OUTDIV3] */ +# define KINETIS_SIM_HAS_CLKDIV1_OUTDIV4 1 /* SoC has CLKDIV1[OUTDIV4] */ +# undef KINETIS_SIM_HAS_CLKDIV1_OUTDIV5 /* SoC has CLKDIV1[OUTDIV5] */ +# define KINETIS_SIM_HAS_CLKDIV2 1 /* SoC has CLKDIV2 Register */ +# define KINETIS_SIM_HAS_CLKDIV2_USBDIV 1 /* SoC has CLKDIV2[USBDIV] */ +# define KINETIS_SIM_HAS_CLKDIV2_USBFRAC 1 /* SoC has CLKDIV2[USBFRAC] */ +# undef KINETIS_SIM_HAS_CLKDIV2_USBFSDIV /* SoC has CLKDIV2[USBFSDIV] */ +# undef KINETIS_SIM_HAS_CLKDIV2_USBFSFRAC /* SoC has CLKDIV2[USBFSFRAC] */ +# undef KINETIS_SIM_HAS_CLKDIV2_USBHSDIV /* SoC has CLKDIV2[USBHSDIV] */ +# undef KINETIS_SIM_HAS_CLKDIV2_USBHSFRAC /* SoC has CLKDIV2[USBHSFRAC] */ +# undef KINETIS_SIM_HAS_CLKDIV2_I2SDIV /* SoC has CLKDIV2[I2SDIV] */ +# undef KINETIS_SIM_HAS_CLKDIV2_I2SFRAC /* SoC has CLKDIV2[I2SFRAC] */ +# define KINETIS_SIM_HAS_FCFG1 1 /* SoC has FCFG1 Register */ +# define KINETIS_SIM_HAS_FCFG1_DEPART 1 /* SoC has FCFG1[DEPART] */ +# define KINETIS_SIM_HAS_FCFG1_EESIZE 1 /* SoC has FCFG1[EESIZE] */ +# define KINETIS_SIM_HAS_FCFG1_FLASHDIS 1 /* SoC has FCFG1[FLASHDIS] */ +# define KINETIS_SIM_HAS_FCFG1_FLASHDOZE 1 /* SoC has FCFG1[FLASHDOZE] */ +# undef KINETIS_SIM_HAS_FCFG1_FTFDIS /* SoC has FCFG1[FTFDIS] */ +# define KINETIS_SIM_HAS_FCFG1_NVMSIZE 1 /* SoC has FCFG1[NVMSIZE] */ +# define KINETIS_SIM_HAS_FCFG2 1 /* SoC has FCFG2 Register */ +# define KINETIS_SIM_HAS_FCFG2_MAXADDR0 7 /* SoC has n bit of FCFG2[MAXADDR0] */ +# define KINETIS_SIM_HAS_FCFG2_MAXADDR1 7 /* SoC has n bit of FCFG2[MAXADDR1] */ +# define KINETIS_SIM_HAS_FCFG2_PFLSH 1 /* SoC has FCFG2[PFLSH] */ +# define KINETIS_SIM_HAS_FCFG2_SWAPPFLSH 1 /* SoC has FCFG2[SWAPPFLSH] */ +# define KINETIS_SIM_HAS_UIDH 1 /* SoC has UIDH Register */ +# define KINETIS_SIM_HAS_UIDMH 1 /* SoC has UIDMH Register */ +# define KINETIS_SIM_HAS_UIDML 1 /* SoC has UIDML Register */ +# define KINETIS_SIM_HAS_UIDL 1 /* SoC has UIDL Register */ +# define KINETIS_SIM_HAS_CLKDIV3 1 /* SoC has CLKDIV3 Register */ +# define KINETIS_SIM_HAS_CLKDIV3_PLLFLLDIV 1 /* SoC has CLKDIV3[PLLFLLDIV] */ +# define KINETIS_SIM_HAS_CLKDIV3_PLLFLLFRAC 1 /* SoC has CLKDIV3[PLLFLLFRAC] */ +# define KINETIS_SIM_HAS_CLKDIV4 1 /* SoC has CLKDIV4 Register */ +# define KINETIS_SIM_HAS_CLKDIV4_TRACEDIV 1 /* SoC has CLKDIV4[TRACEDIV] */ +# define KINETIS_SIM_HAS_CLKDIV4_TRACEFRAC 1 /* SoC has CLKDIV4[TRACEFRAC] */ +# undef KINETIS_SIM_HAS_CLKDIV4_NFCDIV /* SoC has CLKDIV4[NFCDIV] */ +# undef KINETIS_SIM_HAS_CLKDIV4_NFCFRAC /* SoC has CLKDIV4[NFCFRAC] */ +# undef KINETIS_SIM_HAS_MCR /* SoC has MCR Register */ +#else +# error "Unsupported Kinetis chip" +#endif + +/* Use the catch all configuration for the SIM based on the implementations in nuttx prior 2/16/2017 */ + +#if KINETIS_SIM_VERSION == KINETIS_SIM_VERSION_UKN + +/* SIM Register Configuration */ + +# define KINETIS_SIM_HAS_SOPT1 1 /* SoC has SOPT1 Register */ +# undef KINETIS_SIM_HAS_SOPT1_OSC32KOUT /* SoC has SOPT1[OSC32KOUT] */ +# define KINETIS_SIM_HAS_SOPT1_OSC32KSEL 1 /* SoC has SOPT1[OSC32KSEL] */ +# define KINETIS_SIM_HAS_SOPT1_OSC32KSEL_BITS 1 /* SoC has 1 bit SOPT1[OSC32KSEL] */ +# define KINETIS_SIM_HAS_SOPT1_RAMSIZE 1 /* SoC has SOPT1[RAMSIZE] */ +# define KINETIS_SIM_HAS_SOPT1_USBREGEN 1 /* SoC has SOPT1[USBREGEN] */ +# define KINETIS_SIM_HAS_SOPT1_USBSSTBY 1 /* SoC has SOPT1[USBSSTBY] */ +# undef KINETIS_SIM_HAS_SOPT1_USBVSTBY /* SoC has SOPT1[USBVSTBY] */ +# undef KINETIS_SIM_HAS_SOPT1CFG /* SoC has SOPT1CFG Register */ +# undef KINETIS_SIM_HAS_SOPT1CFG_URWE /* SoC has SOPT1CFG[URWE] */ +# undef KINETIS_SIM_HAS_SOPT1CFG_USSWE /* SoC has SOPT1CFG[USSWE] */ +# undef KINETIS_SIM_HAS_SOPT1CFG_UVSWE /* SoC has SOPT1CFG[UVSWE] */ +# undef KINETIS_SIM_HAS_USBPHYCTL /* SoC has USBPHYCTL Register */ +# undef KINETIS_SIM_HAS_USBPHYCTL_USB3VOUTTRG /* SoC has USBPHYCTL[USB3VOUTTRG] */ +# undef KINETIS_SIM_HAS_USBPHYCTL_USBDISILIM /* SoC has USBPHYCTL[USBDISILIM] */ +# undef KINETIS_SIM_HAS_USBPHYCTL_USBVREGPD /* SoC has USBPHYCTL[USBVREGPD] */ +# undef KINETIS_SIM_HAS_USBPHYCTL_USBVREGSEL /* SoC has USBPHYCTL[USBVREGSEL] */ +# define KINETIS_SIM_HAS_SOPT2 1 /* SoC has SOPT2 Register */ +# define KINETIS_SIM_HAS_SOPT2_CMTUARTPAD 1 /* SoC has SOPT2[CMTUARTPAD] */ +# define KINETIS_SIM_HAS_SOPT2_FBSL 1 /* SoC has SOPT2[FBSL] */ +# undef KINETIS_SIM_HAS_SOPT2_FLEXIOSRC /* SoC has SOPT2[FLEXIOSRC] */ +# undef KINETIS_SIM_HAS_SOPT2_LPUARTSRC /* SoC has SOPT2[LPUARTSRC] */ +# define KINETIS_SIM_HAS_SOPT2_PLLFLLSEL 1 /* SoC has SOPT2[PLLFLLSEL] */ +# define KINETIS_SIM_HAS_SOPT2_PLLFLLSEL_BITS 1 /* SoC has 1 bit of SOPT2[PLLFLLSEL] */ +# undef KINETIS_SIM_HAS_SOPT2_PTD7PAD /* SoC has SOPT2[PTD7PAD] */ +# undef KINETIS_SIM_HAS_SOPT2_RMIISRC /* SoC has SOPT2[RMIISRC] */ +# undef KINETIS_SIM_HAS_SOPT2_RTCCLKOUTSEL /* SoC has SOPT2[RTCCLKOUTSEL] */ +# undef KINETIS_SIM_HAS_SOPT2_CLKOUTSEL /* SoC has SOPT2[CLKOUTSEL] */ +# define KINETIS_SIM_HAS_SOPT2_SDHCSRC 1 /* SoC has SOPT2[SDHCSRC] */ +# define KINETIS_SIM_HAS_SOPT2_TIMESRC 1 /* SoC has SOPT2[TIMESRC] */ +# undef KINETIS_SIM_HAS_SOPT2_TPMSRC /* SoC has SOPT2[TPMSRC] */ +# undef KINETIS_SIM_HAS_SOPT2_USBFSRC /* SoC has SOPT2[USBFSRC] */ +# define KINETIS_SIM_HAS_SOPT2_I2SSRC 1 /* SoC has SOPT2[I2SSRC] */ +# define KINETIS_SIM_HAS_SOPT2_TRACECLKSEL 1 /* SoC has SOPT2[TRACECLKSEL] */ +# undef KINETIS_SIM_HAS_SOPT2_USBREGEN /* SoC has SOPT2[USBREGEN] */ +# undef KINETIS_SIM_HAS_SOPT2_USBSLSRC /* SoC has SOPT2[USBSLSRC] */ +# undef KINETIS_SIM_HAS_SOPT2_USBHSRC /* SoC has SOPT2[USBHSRC] */ +# define KINETIS_SIM_HAS_SOPT2_USBSRC 1 /* SoC has SOPT2[USBSRC] */ +# define KINETIS_SIM_HAS_SOPT2_MCGCLKSEL 1 /* SoC has SOPT2[MCGCLKSEL] */ +# define KINETIS_SIM_HAS_SOPT4 1 /* SoC has SOPT4 Register */ +# define KINETIS_SIM_HAS_SOPT4_FTM0FLT0 1 /* SoC has SOPT4[FTM0FLT0] */ +# define KINETIS_SIM_HAS_SOPT4_FTM0FLT1 1 /* SoC has SOPT4[FTM0FLT1] */ +# define KINETIS_SIM_HAS_SOPT4_FTM0FLT2 1 /* SoC has SOPT4[FTM0FLT2] */ +# undef KINETIS_SIM_HAS_SOPT4_FTM0FLT3 /* SoC has SOPT4[FTM0FLT3] */ +# undef KINETIS_SIM_HAS_SOPT4_FTM0TRG0SRC /* SoC has SOPT4[FTM0TRG0SRC] */ +# undef KINETIS_SIM_HAS_SOPT4_FTM0TRG1SRC /* SoC has SOPT4[FTM0TRG1SRC] */ +# define KINETIS_SIM_HAS_SOPT4_FTM1CH0SRC 1 /* SoC has SOPT4[FTM1CH0SRC] No OF */ +# undef KINETIS_SIM_HAS_SOPT4_FTM1FLT0 /* SoC has SOPT4[FTM1FLT0] */ +# undef KINETIS_SIM_HAS_SOPT4_FTM1FLT1 /* SoC has SOPT4[FTM1FLT1] */ +# undef KINETIS_SIM_HAS_SOPT4_FTM1FLT2 /* SoC has SOPT4[FTM1FLT2] */ +# undef KINETIS_SIM_HAS_SOPT4_FTM1FLT3 /* SoC has SOPT4[FTM1FLT3] */ +# define KINETIS_SIM_HAS_SOPT4_FTM2CH0SRC 1 /* SoC has SOPT4[FTM2CH0SRC] */ +# undef KINETIS_SIM_HAS_SOPT4_FTM2CH1SRC /* SoC has SOPT4[FTM2CH1SRC] */ +# undef KINETIS_SIM_HAS_SOPT4_FTM2FLT0 /* SoC has SOPT4[FTM2FLT0] */ +# undef KINETIS_SIM_HAS_SOPT4_FTM2FLT1 /* SoC has SOPT4[FTM2FLT1] */ +# undef KINETIS_SIM_HAS_SOPT4_FTM2FLT2 /* SoC has SOPT4[FTM2FLT2] */ +# undef KINETIS_SIM_HAS_SOPT4_FTM2FLT3 /* SoC has SOPT4[FTM2FLT3] */ +# undef KINETIS_SIM_HAS_SOPT4_FTM3CH0SRC /* SoC has SOPT4[FTM3CH0SRC] */ +# undef KINETIS_SIM_HAS_SOPT4_FTM3FLT0 /* SoC has SOPT4[FTM3FLT0] */ +# undef KINETIS_SIM_HAS_SOPT4_FTM3FLT1 /* SoC has SOPT4[FTM3FLT1] */ +# undef KINETIS_SIM_HAS_SOPT4_FTM3FLT2 /* SoC has SOPT4[FTM3FLT2] */ +# undef KINETIS_SIM_HAS_SOPT4_FTM3FLT3 /* SoC has SOPT4[FTM3FLT3] */ +# undef KINETIS_SIM_HAS_SOPT4_FTM3TRG0SRC /* SoC has SOPT4[FTM3TRG0SRC] */ +# undef KINETIS_SIM_HAS_SOPT4_FTM3TRG1SRC /* SoC has SOPT4[FTM3TRG1SRC] */ +# undef KINETIS_SIM_HAS_SOPT4_TPM0CLKSEL /* SoC has SOPT4[TPM0CLKSEL] */ +# undef KINETIS_SIM_HAS_SOPT4_TPM1CH0SRC /* SoC has SOPT4[TPM1CH0SRC] */ +# undef KINETIS_SIM_HAS_SOPT4_TPM1CLKSEL /* SoC has SOPT4[TPM1CLKSEL] */ +# undef KINETIS_SIM_HAS_SOPT4_TPM2CH0SRC /* SoC has SOPT4[TPM2CH0SRC] */ +# undef KINETIS_SIM_HAS_SOPT4_TPM2CLKSEL /* SoC has SOPT4[TPM2CLKSEL] */ +# define KINETIS_SIM_HAS_SOPT5 /* SoC has SOPT5 Register */ +# undef KINETIS_SIM_HAS_SOPT5_LPUART0RXSRC /* SoC has SOPT5[LPUART0RXSRC] */ +# undef KINETIS_SIM_HAS_SOPT5_LPUART0TXSRC /* SoC has SOPT5[LPUART0TXSRC] */ +# define KINETIS_SIM_HAS_SOPT6 1 /* SoC has SOPT6 Register */ +# undef KINETIS_SIM_HAS_SOPT6_MCC /* SoC has SOPT6[MCC] */ +# undef KINETIS_SIM_HAS_SOPT6_PCR /* SoC has SOPT6[PCR] */ +# define KINETIS_SIM_HAS_SOPT6_RSTFLTSEL 1 /* SoC has SOPT6[RSTFLTSEL] */ +# define KINETIS_SIM_HAS_SOPT6_RSTFLTEN 1 /* SoC has SOPT6[RSTFLTEN] */ +# define KINETIS_SIM_HAS_SOPT7 1 /* SoC has SOPT7 Register */ +# define KINETIS_SIM_HAS_SOPT7_ADC0ALTTRGSEL 1 /* SoC has SOPT7[ADC0ALTTRGSEL] */ +# define KINETIS_SIM_HAS_SOPT7_ADC1ALTTRGSEL 1 /* SoC has SOPT7[ADC1ALTTRGSEL] */ +# define KINETIS_SIM_HAS_SOPT7_ADC0PRETRGSEL 1 /* SoC has SOPT7[ADC0PRETRGSEL] */ +# define KINETIS_SIM_HAS_SOPT7_ADC1PRETRGSEL 1 /* SoC has SOPT7[ADC1PRETRGSEL] */ +# undef KINETIS_SIM_HAS_SOPT7_ADC2PRETRGSEL /* SoC has SOPT7[ADC2PRETRGSEL] */ +# undef KINETIS_SIM_HAS_SOPT7_ADC3PRETRGSEL /* SoC has SOPT7[ADC3PRETRGSEL] */ +# define KINETIS_SIM_HAS_SOPT7_ADC0TRGSEL 14 /* SoC has 10 SOPT7[ADC0TRGSEL] */ +# define KINETIS_SIM_HAS_SOPT7_ADC1TRGSEL 14 /* SoC has 10 SOPT7[ADC1TRGSEL] */ +# undef KINETIS_SIM_HAS_SOPT7_ADC2TRGSEL /* SoC has 10 SOPT7[ADC2TRGSEL] */ +# undef KINETIS_SIM_HAS_SOPT7_ADC3TRGSEL /* SoC has 10 SOPT7[ADC3TRGSEL] */ +# define KINETIS_SIM_SOPT7_ADC0ALTTRGEN 1 /* ADC0 alternate trigger enable */ +# define KINETIS_SIM_SOPT7_ADC1ALTTRGEN 1 /* ADC1 alternate trigger enable */ +# undef KINETIS_SIM_SOPT7_ADC2ALTTRGEN /* ADC2 alternate trigger enable */ +# undef KINETIS_SIM_SOPT7_ADC3ALTTRGEN /* ADC3 alternate trigger enable */ +# undef KINETIS_SIM_HAS_SOPT8 /* SoC has SOPT8 Register */ +# undef KINETIS_SIM_HAS_SOPT9 /* SoC has SOPT9 Register */ +# define KINETIS_SIM_HAS_SDID 1 /* SoC has SDID Register */ +# undef KINETIS_SIM_HAS_SDID_DIEID /* SoC has SDID[DIEID] */ +# define KINETIS_SIM_HAS_SDID_FAMID 1 /* SoC has SDID[FAMID] */ +# undef KINETIS_SIM_HAS_SDID_FAMILYID /* SoC has SDID[FAMILYID] */ +# undef KINETIS_SIM_HAS_SDID_SERIESID /* SoC has SDID[SERIESID] */ +# undef KINETIS_SIM_HAS_SDID_SRAMSIZE /* SoC has SDID[SRAMSIZE] */ +# undef KINETIS_SIM_HAS_SDID_SUBFAMID /* SoC has SDID[SUBFAMID] */ +# define KINETIS_SIM_HAS_SCGC1 1 /* SoC has SCGC1 Register */ +# define KINETIS_SIM_HAS_SCGC1_UART5 1 /* SoC has SCGC1[UART5] */ +# define KINETIS_SIM_HAS_SCGC1_UART4 1 /* SoC has SCGC1[UART4] */ +# undef KINETIS_SIM_HAS_SCGC1_I2C3 /* SoC has SCGC1[I2C3] */ +# undef KINETIS_SIM_HAS_SCGC1_I2C2 /* SoC has SCGC1[I2C2] */ +# undef KINETIS_SIM_HAS_SCGC1_OSC1 /* SoC has SCGC1[OSC1] */ +# define KINETIS_SIM_HAS_SCGC2 1 /* SoC has SCGC2 Register */ +# define KINETIS_SIM_HAS_SCGC2_ENET 1 /* SoC has SCGC2[ENET] */ +# undef KINETIS_SIM_HAS_SCGC2_LPUART0 /* SoC has SCGC2[LPUART0] */ +# undef KINETIS_SIM_HAS_SCGC2_TPM1 /* SoC has SCGC2[TPM1] */ +# undef KINETIS_SIM_HAS_SCGC2_TPM2 /* SoC has SCGC2[TPM2] */ +# define KINETIS_SIM_HAS_SCGC3 1 /* SoC has SCGC3 Register */ +# define KINETIS_SIM_HAS_SCGC3_RNGA 1 /* SoC has SCGC3[RNGA] */ +# undef KINETIS_SIM_HAS_SCGC3_USBHS /* SoC has SCGC3[USBHS] */ +# undef KINETIS_SIM_HAS_SCGC3_USBHSPHY /* SoC has SCGC3[USBHSPHY] */ +# undef KINETIS_SIM_HAS_SCGC3_USBHSDCD /* SoC has SCGC3[USBHSDCD] */ +# define KINETIS_SIM_HAS_SCGC3_FLEXCAN1 1 /* SoC has SCGC3[FLEXCAN1] */ +# undef KINETIS_SIM_HAS_SCGC3_NFC /* SoC has SCGC3[NFC] */ +# define KINETIS_SIM_HAS_SCGC3_SPI2 1 /* SoC has SCGC3[SPI2] */ +# undef KINETIS_SIM_HAS_SCGC3_SAI1 /* SoC has SCGC3[SAI1] */ +# define KINETIS_SIM_HAS_SCGC3_SDHC 1 /* SoC has SCGC3[SDHC] */ +# define KINETIS_SIM_HAS_SCGC3_FTM2 1 /* SoC has SCGC3[FTM2] */ +# define KINETIS_SIM_HAS_SCGC3_FTM3 1 /* SoC has SCGC3[FTM3] */ +# define KINETIS_SIM_HAS_SCGC3_ADC1 1 /* SoC has SCGC3[ADC1] */ +# undef KINETIS_SIM_HAS_SCGC3_ADC3 /* SoC has SCGC3[ADC3] */ +# define KINETIS_SIM_HAS_SCGC3_SLCD 1 /* SoC has SCGC3[SLCD] */ +# define KINETIS_SIM_HAS_SCGC4 1 /* SoC has SCGC4 Register */ +# define KINETIS_SIM_HAS_SCGC4_LLWU 1 /* SoC has SCGC4[LLWU] clock gate */ +# define KINETIS_SIM_HAS_SCGC4_UART0 1 /* SoC has SCGC4[UART0] */ +# define KINETIS_SIM_HAS_SCGC4_UART1 1 /* SoC has SCGC4[UART1] */ +# define KINETIS_SIM_HAS_SCGC4_UART2 1 /* SoC has SCGC4[UART2] */ +# define KINETIS_SIM_HAS_SCGC4_UART3 1 /* SoC has SCGC4[UART3] */ +# define KINETIS_SIM_HAS_SCGC5 1 /* SoC has SCGC5 Register */ +# define KINETIS_SIM_HAS_SCGC5_REGFILE 1 /* SoC has SCGC5[REGFILE] */ +# define KINETIS_SIM_HAS_SCGC5_TSI 1 /* SoC has SCGC5[TSI] */ +# undef KINETIS_SIM_HAS_SCGC5_PORTF /* SoC has SCGC5[PORTF] */ +# define KINETIS_SIM_HAS_SCGC6 1 /* SoC has SCGC6 Register */ +# define KINETIS_SIM_HAS_SCGC6_FTFL 1 /* SoC has SCGC6[FTFL] */ +# undef KINETIS_SIM_HAS_SCGC6_DMAMUX1 /* SoC has SCGC6[DEMUX1] */ +# undef KINETIS_SIM_HAS_SCGC6_USBHS /* SoC has SCGC6[USBHS] */ +# undef KINETIS_SIM_HAS_SCGC6_RNGA /* SoC has SCGC6[RNGA] */ +# undef KINETIS_SIM_HAS_SCGC6_FTM2 /* SoC has SCGC6[FTM2] */ +# undef KINETIS_SIM_HAS_SCGC6_ADC2 /* SoC has SCGC6[ADC2] */ +# undef KINETIS_SIM_HAS_SCGC6_DAC0 /* SoC has SCGC6[DAC0] */ +# define KINETIS_SIM_HAS_SCGC7 1 /* SoC has SCGC7 Register */ +# define KINETIS_SIM_HAS_SCGC7_FLEXBUS 1 /* SoC has SCGC7[FLEXBUS] */ +# define KINETIS_SIM_HAS_SCGC7_DMA 1 /* SoC has SCGC7[DMS] */ +# define KINETIS_SIM_HAS_SCGC7_MPU 1 /* SoC has SCGC7[MPU] */ +# undef KINETIS_SIM_HAS_SCGC7_SDRAMC /* SoC has SCGC7[SDRAMC] */ +# define KINETIS_SIM_HAS_CLKDIV1 1 /* SoC has CLKDIV1 Register */ +# define KINETIS_SIM_HAS_CLKDIV1_OUTDIV2 1 /* SoC has CLKDIV1[OUTDIV2] */ +# define KINETIS_SIM_HAS_CLKDIV1_OUTDIV3 1 /* SoC has CLKDIV1[OUTDIV3] */ +# define KINETIS_SIM_HAS_CLKDIV1_OUTDIV4 1 /* SoC has CLKDIV1[OUTDIV4] */ +# undef KINETIS_SIM_HAS_CLKDIV1_OUTDIV5 /* SoC has CLKDIV1[OUTDIV5] */ +# define KINETIS_SIM_HAS_CLKDIV2 1 /* SoC has CLKDIV2 Register */ +# define KINETIS_SIM_HAS_CLKDIV2_USBDIV 1 /* SoC has CLKDIV2[USBDIV] */ +# define KINETIS_SIM_HAS_CLKDIV2_USBFRAC 1 /* SoC has CLKDIV2[USBFRAC] */ +# undef KINETIS_SIM_HAS_CLKDIV2_USBFSDIV /* SoC has CLKDIV2[USBFSDIV] */ +# undef KINETIS_SIM_HAS_CLKDIV2_USBFSFRAC /* SoC has CLKDIV2[USBFSFRAC] */ +# undef KINETIS_SIM_HAS_CLKDIV2_USBHSDIV /* SoC has CLKDIV2[USBHSDIV] */ +# undef KINETIS_SIM_HAS_CLKDIV2_USBHSFRAC /* SoC has CLKDIV2[USBHSFRAC] */ +# define KINETIS_SIM_HAS_CLKDIV2_I2SDIV 1 /* SoC has CLKDIV2[I2SDIV] */ +# define KINETIS_SIM_HAS_CLKDIV2_I2SFRAC 1 /* SoC has CLKDIV2[I2SFRAC] */ +# define KINETIS_SIM_HAS_FCFG1 1 /* SoC has FCFG1 Register */ +# define KINETIS_SIM_HAS_FCFG1_DEPART 1 /* SoC has FCFG1[DEPART] */ +# define KINETIS_SIM_HAS_FCFG1_EESIZE 1 /* SoC has FCFG1[EESIZE] */ +# undef KINETIS_SIM_HAS_FCFG1_FLASHDIS /* SoC has FCFG1[FLASHDIS] */ +# undef KINETIS_SIM_HAS_FCFG1_FLASHDOZE /* SoC has FCFG1[FLASHDOZE] */ +# undef KINETIS_SIM_HAS_FCFG1_FTFDIS /* SoC has FCFG1[FTFDIS] */ +# define KINETIS_SIM_HAS_FCFG1_NVMSIZE 1 /* SoC has FCFG1[NVMSIZE] */ +# define KINETIS_SIM_HAS_FCFG2 1 /* SoC has FCFG2 Register */ +# define KINETIS_SIM_HAS_FCFG2_MAXADDR0 6 /* SoC has n bit of FCFG2[MAXADDR0] */ +# define KINETIS_SIM_HAS_FCFG2_MAXADDR1 6 /* SoC has n bit of FCFG2[MAXADDR1] */ +# define KINETIS_SIM_HAS_FCFG2_PFLSH 1 /* SoC has FCFG2[PFLSH] */ +# define KINETIS_SIM_HAS_FCFG2_SWAPPFLSH 1 /* SoC has FCFG2[SWAPPFLSH] */ +# define KINETIS_SIM_HAS_UIDH 1 /* SoC has UIDH Register */ +# define KINETIS_SIM_HAS_UIDMH 1 /* SoC has UIDMH Register */ +# define KINETIS_SIM_HAS_UIDML 1 /* SoC has UIDML Register */ +# define KINETIS_SIM_HAS_UIDL 1 /* SoC has UIDL Register */ +# undef KINETIS_SIM_HAS_CLKDIV3 /* SoC has CLKDIV3 Register */ +# undef KINETIS_SIM_HAS_CLKDIV3_PLLFLLDIV /* SoC has CLKDIV3[PLLFLLDIV] */ +# undef KINETIS_SIM_HAS_CLKDIV3_PLLFLLFRAC /* SoC has CLKDIV3[PLLFLLFRAC] */ +# undef KINETIS_SIM_HAS_CLKDIV4 /* SoC has CLKDIV4 Register */ +# undef KINETIS_SIM_HAS_CLKDIV4_TRACEDIV /* SoC has CLKDIV4[TRACEDIV] */ +# undef KINETIS_SIM_HAS_CLKDIV4_TRACEFRAC /* SoC has CLKDIV4[TRACEFRAC] */ +# undef KINETIS_SIM_HAS_CLKDIV4_NFCDIV /* SoC has CLKDIV4[NFCDIV] */ +# undef KINETIS_SIM_HAS_CLKDIV4_NFCFRAC /* SoC has CLKDIV4[NFCFRAC] */ +# undef KINETIS_SIM_HAS_MCR /* SoC has MCR Register */ +#endif + +#if !defined(KINETIS_SIM_VERSION) +# error "No KINETIS_SIM_VERSION defined!" +#endif + +#if defined(KINETIS_SIM_HAS_SOPT1_OSC32KSEL) +# define KINETIS_SIM_SOPT1_OSC32KSEL_MASK ((1 << (KINETIS_SIM_HAS_SOPT1_OSC32KSEL_BITS))-1) +#endif + +#if defined(KINETIS_SIM_HAS_SOPT2_PLLFLLSEL) +# define KINETIS_SIM_SOPT2_PLLFLLSEL_MASK ((1 << (KINETIS_SIM_HAS_SOPT2_PLLFLLSEL_BITS))-1) +#endif + +#if defined(KINETIS_SIM_HAS_FCFG2_MAXADDR0) +# define KINETIS_SIM_FCFG2_MAXADDR0_MASK ((1 << (KINETIS_SIM_HAS_FCFG2_MAXADDR0))-1) +#endif + +#if defined(KINETIS_SIM_HAS_FCFG2_MAXADDR1) +# define KINETIS_SIM_FCFG2_MAXADDR1_MASK ((1 << (KINETIS_SIM_HAS_FCFG2_MAXADDR1))-1) +#endif + +#endif /* __ARCH_ARM_INCLUDE_KINETIS_KINETIS_SIM_H */ diff --git a/arch/arm/src/kinetis/chip/kinetis_llwu.h b/arch/arm/src/kinetis/chip/kinetis_llwu.h index ae5c6c8b04c..c4abaa74ddf 100644 --- a/arch/arm/src/kinetis/chip/kinetis_llwu.h +++ b/arch/arm/src/kinetis/chip/kinetis_llwu.h @@ -232,7 +232,9 @@ /* LLWU Control and Status Register */ -#define LLWU_CS_ACKISO (1 << 7) /* Bit 7: Acknowledge Isolation */ +#if !defined(KINETIS_PMC_HAS_REGSC_ACKISO) +# define LLWU_CS_ACKISO (1 << 7) /* Bit 7: Acknowledge Isolation */ +#endif /* Bits 2-6: Reserved */ #define LLWU_CS_FLTEP (1 << 1) /* Bit 1: Digital Filter on External Pin */ #define LLWU_CS_FLTR (1 << 0) /* Bit 0: Digital Filter on RESET Pin */ diff --git a/arch/arm/src/kinetis/chip/kinetis_pmc.h b/arch/arm/src/kinetis/chip/kinetis_pmc.h index c0ffe575b36..be346bf67fe 100644 --- a/arch/arm/src/kinetis/chip/kinetis_pmc.h +++ b/arch/arm/src/kinetis/chip/kinetis_pmc.h @@ -78,22 +78,33 @@ #define PMC_LVDSC2_LVWV_SHIFT (0) /* Bits 0-1: Low-Voltage Warning Voltage Select */ #define PMC_LVDSC2_LVWV_MASK (3 << PMC_LVDSC2_LVWV_SHIFT) -# define PMC_LVDSC2_LVWV_ LOW (0 << PMC_LVDSC2_LVWV_SHIFT) /* Low trip point selected (VLVW = VLVW1H/L) */ -# define PMC_LVDSC2_LVWV_ MID1 (1 << PMC_LVDSC2_LVWV_SHIFT) /* Mid 1 trip point selected (VLVW = VLVW2H/L) */ -# define PMC_LVDSC2_LVWV_ MID2 (2 << PMC_LVDSC2_LVWV_SHIFT) /* Mid 2 trip point selected (VLVW = VLVW3H/L) */ -# define PMC_LVDSC2_LVWV_ HIGH (3 << PMC_LVDSC2_LVWV_SHIFT) /* High trip point selected (VLVW = VLVW4H/L) */ +# define PMC_LVDSC2_LVWV_LOW (0 << PMC_LVDSC2_LVWV_SHIFT) /* Low trip point selected (VLVW = VLVW1H/L) */ +# define PMC_LVDSC2_LVWV_MID1 (1 << PMC_LVDSC2_LVWV_SHIFT) /* Mid 1 trip point selected (VLVW = VLVW2H/L) */ +# define PMC_LVDSC2_LVWV_MID2 (2 << PMC_LVDSC2_LVWV_SHIFT) /* Mid 2 trip point selected (VLVW = VLVW3H/L) */ +# define PMC_LVDSC2_LVWV_HIGH (3 << PMC_LVDSC2_LVWV_SHIFT) /* High trip point selected (VLVW = VLVW4H/L) */ /* Bits 2-4: Reserved */ #define PMC_LVDSC2_LVWIE (1 << 5) /* Bit 5: Low-Voltage Warning Interrupt Enable */ #define PMC_LVDSC2_LVWACK (1 << 6) /* Bit 6: Low-Voltage Warning Acknowledge */ #define PMC_LVDSC2_LVWF (1 << 7) /* Bit 7: Low-Voltage Warning Flag */ /* Regulator Status and Control Register */ - #define PMC_REGSC_BGBE (1 << 0) /* Bit 0: Bandgap Buffer Enable */ /* Bit 1: Reserved */ -#define PMC_REGSC_REGONS (1 << 2) /* Bit 2: Regulator in Run Regulation Status */ -#define PMC_REGSC_VLPRS (1 << 3) /* Bit 3: Very Low Power Run Status */ -#define PMC_REGSC_TRAMPO (1 << 4) /* Bit 4: For devices with FlexNVM: Traditional RAM Power Option */ +#if defined(KINETIS_PMC_HAS_REGSC_REGONS) +# define PMC_REGSC_REGONS (1 << 2) /* Bit 2: Regulator in Run Regulation Status */ +#endif +#if defined(KINETIS_PMC_HAS_REGSC_ACKISO) +# define PMC_REGSC_ACKISO (1 << 3) /* Bit 3: Acknowledge Isolation */ +#endif +#if defined(KINETIS_PMC_HAS_REGSC_VLPRS) +# define PMC_REGSC_VLPRS (1 << 3) /* Bit 3: Very Low Power Run Status */ +#endif +#if defined(KINETIS_PMC_HAS_REGSC_BGEN) +# define PMC_REGSC_BGEN (1 << 4) /* Bit 4: Bandgap Enable In VLPx Operation */ +#endif +#if defined(KINETIS_PMC_HAS_REGSC_TRAMPO) +# define PMC_REGSC_TRAMPO (1 << 4) /* Bit 4: For devices with FlexNVM: Traditional RAM Power Option */ +#endif /* Bits 5-7: Reserved */ /************************************************************************************ diff --git a/arch/arm/src/kinetis/chip/kinetis_sim.h b/arch/arm/src/kinetis/chip/kinetis_sim.h index 4898c589604..d1a98b3b5a1 100644 --- a/arch/arm/src/kinetis/chip/kinetis_sim.h +++ b/arch/arm/src/kinetis/chip/kinetis_sim.h @@ -51,513 +51,1254 @@ /* Register Offsets *****************************************************************/ -#define KINETIS_SIM_SOPT1_OFFSET 0x0000 /* System Options Register 1 */ -#define KINETIS_SIM_SOPT2_OFFSET 0x0004 /* System Options Register 2 */ -#define KINETIS_SIM_SOPT4_OFFSET 0x000c /* System Options Register 4 */ -#define KINETIS_SIM_SOPT5_OFFSET 0x0010 /* System Options Register 5 */ -#define KINETIS_SIM_SOPT6_OFFSET 0x0014 /* System Options Register 6 */ -#define KINETIS_SIM_SOPT7_OFFSET 0x0018 /* System Options Register 7 */ -#define KINETIS_SIM_SDID_OFFSET 0x0024 /* System Device Identification Register */ -#define KINETIS_SIM_SCGC1_OFFSET 0x0028 /* System Clock Gating Control Register 1 */ -#define KINETIS_SIM_SCGC2_OFFSET 0x002c /* System Clock Gating Control Register 2 */ -#define KINETIS_SIM_SCGC3_OFFSET 0x0030 /* System Clock Gating Control Register 3 */ -#define KINETIS_SIM_SCGC4_OFFSET 0x0034 /* System Clock Gating Control Register 4 */ -#define KINETIS_SIM_SCGC5_OFFSET 0x0038 /* System Clock Gating Control Register 5 */ -#define KINETIS_SIM_SCGC6_OFFSET 0x003c /* System Clock Gating Control Register 6 */ -#define KINETIS_SIM_SCGC7_OFFSET 0x0040 /* System Clock Gating Control Register 7 */ -#define KINETIS_SIM_CLKDIV1_OFFSET 0x0044 /* System Clock Divider Register 1 */ -#define KINETIS_SIM_CLKDIV2_OFFSET 0x0048 /* System Clock Divider Register 2 */ -#define KINETIS_SIM_FCFG1_OFFSET 0x004c /* Flash Configuration Register 1 */ -#define KINETIS_SIM_FCFG2_OFFSET 0x0050 /* Flash Configuration Register 2 */ -#define KINETIS_SIM_UIDH_OFFSET 0x0054 /* Unique Identification Register High */ -#define KINETIS_SIM_UIDMH_OFFSET 0x0058 /* Unique Identification Register Mid-High */ -#define KINETIS_SIM_UIDML_OFFSET 0x005c /* Unique Identification Register Mid Low */ -#define KINETIS_SIM_UIDL_OFFSET 0x0060 /* Unique Identification Register Low */ +#define KINETIS_SIM_SOPT1_OFFSET 0x0000 /* System Options Register 1 */ +#if defined (KINETIS_SIM_HAS_SOPT1CFG) +# define KINETIS_SIM_SOPT1CFG_OFFSET 0x0004 /* SOPT1 Configuration Register */ +#endif +#if defined(KINETIS_SIM_HAS_USBPHYCTL) +# define KINETIS_SIM_USBPHYCTL_OFFSET 0x0008 /* USB PHY Control Register */ +#endif +#define KINETIS_SIM_SOPT2_OFFSET 0x0004 /* System Options Register 2 */ +#define KINETIS_SIM_SOPT4_OFFSET 0x000c /* System Options Register 4 */ +#define KINETIS_SIM_SOPT5_OFFSET 0x0010 /* System Options Register 5 */ +#define KINETIS_SIM_SOPT6_OFFSET 0x0014 /* System Options Register 6 */ +#define KINETIS_SIM_SOPT7_OFFSET 0x0018 /* System Options Register 7 */ +#if defined(KINETIS_SIM_HAS_SOPT8) +# define KINETIS_SIM_SOPT8_OFFSET 0x001c /* System Options Register 8 */ +#endif +#if defined(KINETIS_SIM_HAS_SOPT9) +# define KINETIS_SIM_SOPT9_OFFSET 0x0020 /* System Options Register 9 */ +#endif +#define KINETIS_SIM_SDID_OFFSET 0x0024 /* System Device Identification Register */ +#define KINETIS_SIM_SCGC1_OFFSET 0x0028 /* System Clock Gating Control Register 1 */ +#define KINETIS_SIM_SCGC2_OFFSET 0x002c /* System Clock Gating Control Register 2 */ +#define KINETIS_SIM_SCGC3_OFFSET 0x0030 /* System Clock Gating Control Register 3 */ +#define KINETIS_SIM_SCGC4_OFFSET 0x0034 /* System Clock Gating Control Register 4 */ +#define KINETIS_SIM_SCGC5_OFFSET 0x0038 /* System Clock Gating Control Register 5 */ +#define KINETIS_SIM_SCGC6_OFFSET 0x003c /* System Clock Gating Control Register 6 */ +#define KINETIS_SIM_SCGC7_OFFSET 0x0040 /* System Clock Gating Control Register 7 */ +#define KINETIS_SIM_CLKDIV1_OFFSET 0x0044 /* System Clock Divider Register 1 */ +#define KINETIS_SIM_CLKDIV2_OFFSET 0x0048 /* System Clock Divider Register 2 */ +#define KINETIS_SIM_FCFG1_OFFSET 0x004c /* Flash Configuration Register 1 */ +#define KINETIS_SIM_FCFG2_OFFSET 0x0050 /* Flash Configuration Register 2 */ +#define KINETIS_SIM_UIDH_OFFSET 0x0054 /* Unique Identification Register High */ +#define KINETIS_SIM_UIDMH_OFFSET 0x0058 /* Unique Identification Register Mid-High */ +#define KINETIS_SIM_UIDML_OFFSET 0x005c /* Unique Identification Register Mid Low */ +#define KINETIS_SIM_UIDL_OFFSET 0x0060 /* Unique Identification Register Low */ +#if defined(KINETIS_SIM_HAS_CLKDIV3) +# define KINETIS_SIM_CLKDIV3_OFFSET 0x0064 /* System Clock Divider Register 3 */ +#endif +#if defined(KINETIS_SIM_HAS_CLKDIV4) +# define KINETIS_SIM_CLKDIV4_OFFSET 0x0068 /* System Clock Divider Register 4 */ +#endif /* Register Addresses ***************************************************************/ -/* NOTE: The SIM_SOPT1 register is located at a different base address than the - * other SIM registers. +/* NOTE: The SIM_SOPT1, SIM_SOPT1CFG and SIM_USBPHYCTL registers are located at a + * different base address than the other SIM registers. */ -#define KINETIS_SIM_SOPT1 (KINETIS_SIMLP_BASE+KINETIS_SIM_SOPT1_OFFSET) -#define KINETIS_SIM_SOPT2 (KINETIS_SIM_BASE+KINETIS_SIM_SOPT2_OFFSET) -#define KINETIS_SIM_SOPT4 (KINETIS_SIM_BASE+KINETIS_SIM_SOPT4_OFFSET) -#define KINETIS_SIM_SOPT5 (KINETIS_SIM_BASE+KINETIS_SIM_SOPT5_OFFSET) -#define KINETIS_SIM_SOPT6 (KINETIS_SIM_BASE+KINETIS_SIM_SOPT6_OFFSET) -#define KINETIS_SIM_SOPT7 (KINETIS_SIM_BASE+KINETIS_SIM_SOPT7_OFFSET) -#define KINETIS_SIM_SDID (KINETIS_SIM_BASE+KINETIS_SIM_SDID_OFFSET) -#define KINETIS_SIM_SCGC1 (KINETIS_SIM_BASE+KINETIS_SIM_SCGC1_OFFSET) -#define KINETIS_SIM_SCGC2 (KINETIS_SIM_BASE+KINETIS_SIM_SCGC2_OFFSET) -#define KINETIS_SIM_SCGC3 (KINETIS_SIM_BASE+KINETIS_SIM_SCGC3_OFFSET) -#define KINETIS_SIM_SCGC4 (KINETIS_SIM_BASE+KINETIS_SIM_SCGC4_OFFSET) -#define KINETIS_SIM_SCGC5 (KINETIS_SIM_BASE+KINETIS_SIM_SCGC5_OFFSET) -#define KINETIS_SIM_SCGC6 (KINETIS_SIM_BASE+KINETIS_SIM_SCGC6_OFFSET) -#define KINETIS_SIM_SCGC7 (KINETIS_SIM_BASE+KINETIS_SIM_SCGC7_OFFSET) -#define KINETIS_SIM_CLKDIV1 (KINETIS_SIM_BASE+KINETIS_SIM_CLKDIV1_OFFSET) -#define KINETIS_SIM_CLKDIV2 (KINETIS_SIM_BASE+KINETIS_SIM_CLKDIV2_OFFSET) -#define KINETIS_SIM_FCFG1 (KINETIS_SIM_BASE+KINETIS_SIM_FCFG1_OFFSET) -#define KINETIS_SIM_FCFG2 (KINETIS_SIM_BASE+KINETIS_SIM_FCFG2_OFFSET) -#define KINETIS_SIM_UIDH (KINETIS_SIM_BASE+KINETIS_SIM_UIDH_OFFSET) -#define KINETIS_SIM_UIDMH (KINETIS_SIM_BASE+KINETIS_SIM_UIDMH_OFFSET) -#define KINETIS_SIM_UIDML (KINETIS_SIM_BASE+KINETIS_SIM_UIDML_OFFSET) -#define KINETIS_SIM_UIDL (KINETIS_SIM_BASE+KINETIS_SIM_UIDL_OFFSET) +#define KINETIS_SIM_SOPT1 (KINETIS_SIMLP_BASE+KINETIS_SIM_SOPT1_OFFSET) +#if defined(KINETIS_SIM_HAS_SOPT1CFG) +# define KINETIS_SIM_SOPT1CFG (KINETIS_SIMLP_BASE+KINETIS_SIM_SOPT1CFG_OFFSET) +#endif +#if defined(KINETIS_SIM_HAS_USBPHYCTL) +# define KINETIS_SIM_USBPHYCTL (KINETIS_SIMLP_BASE+KINETIS_SIM_USBPHYCTL_OFFSET) +#endif +#define KINETIS_SIM_SOPT2 (KINETIS_SIM_BASE+KINETIS_SIM_SOPT2_OFFSET) +#define KINETIS_SIM_SOPT4 (KINETIS_SIM_BASE+KINETIS_SIM_SOPT4_OFFSET) +#define KINETIS_SIM_SOPT5 (KINETIS_SIM_BASE+KINETIS_SIM_SOPT5_OFFSET) +#define KINETIS_SIM_SOPT6 (KINETIS_SIM_BASE+KINETIS_SIM_SOPT6_OFFSET) +#define KINETIS_SIM_SOPT7 (KINETIS_SIM_BASE+KINETIS_SIM_SOPT7_OFFSET) +#if defined(KINETIS_SIM_HAS_SOPT8) +# define KINETIS_SIM_SOPT8 (KINETIS_SIM_BASE+KINETIS_SIM_SOPT8_OFFSET) +#endif +#if defined(KINETIS_SIM_HAS_SOPT9) +# define KINETIS_SIM_SOPT9 (KINETIS_SIM_BASE+KINETIS_SIM_SOPT8_OFFSET) +#endif +#define KINETIS_SIM_SDID (KINETIS_SIM_BASE+KINETIS_SIM_SDID_OFFSET) +#define KINETIS_SIM_SCGC1 (KINETIS_SIM_BASE+KINETIS_SIM_SCGC1_OFFSET) +#define KINETIS_SIM_SCGC2 (KINETIS_SIM_BASE+KINETIS_SIM_SCGC2_OFFSET) +#define KINETIS_SIM_SCGC3 (KINETIS_SIM_BASE+KINETIS_SIM_SCGC3_OFFSET) +#define KINETIS_SIM_SCGC4 (KINETIS_SIM_BASE+KINETIS_SIM_SCGC4_OFFSET) +#define KINETIS_SIM_SCGC5 (KINETIS_SIM_BASE+KINETIS_SIM_SCGC5_OFFSET) +#define KINETIS_SIM_SCGC6 (KINETIS_SIM_BASE+KINETIS_SIM_SCGC6_OFFSET) +#define KINETIS_SIM_SCGC7 (KINETIS_SIM_BASE+KINETIS_SIM_SCGC7_OFFSET) +#define KINETIS_SIM_CLKDIV1 (KINETIS_SIM_BASE+KINETIS_SIM_CLKDIV1_OFFSET) +#define KINETIS_SIM_CLKDIV2 (KINETIS_SIM_BASE+KINETIS_SIM_CLKDIV2_OFFSET) +#define KINETIS_SIM_FCFG1 (KINETIS_SIM_BASE+KINETIS_SIM_FCFG1_OFFSET) +#define KINETIS_SIM_FCFG2 (KINETIS_SIM_BASE+KINETIS_SIM_FCFG2_OFFSET) +#define KINETIS_SIM_UIDH (KINETIS_SIM_BASE+KINETIS_SIM_UIDH_OFFSET) +#define KINETIS_SIM_UIDMH (KINETIS_SIM_BASE+KINETIS_SIM_UIDMH_OFFSET) +#define KINETIS_SIM_UIDML (KINETIS_SIM_BASE+KINETIS_SIM_UIDML_OFFSET) +#define KINETIS_SIM_UIDL (KINETIS_SIM_BASE+KINETIS_SIM_UIDL_OFFSET) +#if defined(KINETIS_SIM_HAS_CLKDIV3) +# define KINETIS_SIM_CLKDIV3 (KINETIS_SIM_BASE+KINETIS_SIM_CLKDIV3_OFFSET) +#endif +#if defined(KINETIS_SIM_HAS_CLKDIV4) +# define KINETIS_SIM_CLKDIV4 (KINETIS_SIM_BASE+KINETIS_SIM_CLKDIV4_OFFSET) +#endif /* Register Bit Definitions *********************************************************/ /* System Options Register 1 */ - /* Bits 0-11: Reserved */ -#define SIM_SOPT1_RAMSIZE_SHIFT (12) /* Bits 12-15: RAM size */ -#define SIM_SOPT1_RAMSIZE_MASK (15 << SIM_SOPT1_RAMSIZE_SHIFT) -# define SIM_SOPT1_RAMSIZE_32KB (5 << SIM_SOPT1_RAMSIZE_SHIFT) /* 32 KBytes */ -# define SIM_SOPT1_RAMSIZE_64KB (7 << SIM_SOPT1_RAMSIZE_SHIFT) /* 64 KBytes */ -# define SIM_SOPT1_RAMSIZE_96KB (8 << SIM_SOPT1_RAMSIZE_SHIFT) /* 96 KBytes */ -# define SIM_SOPT1_RAMSIZE_128KB (9 << SIM_SOPT1_RAMSIZE_SHIFT) /* 128 KBytes */ - /* Bits 16-18: Reserved */ -#define SIM_SOPT1_OSC32KSEL (1 << 19) /* Bit 19: 32K oscillator clock select */ - /* Bits 20-22: Reserved */ -#define SIM_SOPT1_MS (1 << 23) /* Bit 23: EzPort chip select pin state */ - /* Bits 24-29: Reserved */ -#define SIM_SOPT1_USBSTBY (1 << 30) /* Bit 30: USB voltage regulator in standby mode */ -#define SIM_SOPT1_USBREGEN (1 << 31) /* Bit 31: USB voltage regulator enable */ + /* Bits 0-11: Reserved */ +#if defined(KINETIS_SIM_HAS_SOPT1_RAMSIZE) +# define SIM_SOPT1_RAMSIZE_SHIFT (12) /* Bits 12-15: RAM size */ +# define SIM_SOPT1_RAMSIZE_MASK (15 << SIM_SOPT1_RAMSIZE_SHIFT) +# define SIM_SOPT1_RAMSIZE_32KB (5 << SIM_SOPT1_RAMSIZE_SHIFT) /* 32 KBytes */ +# define SIM_SOPT1_RAMSIZE_64KB (7 << SIM_SOPT1_RAMSIZE_SHIFT) /* 64 KBytes */ +# define SIM_SOPT1_RAMSIZE_96KB (8 << SIM_SOPT1_RAMSIZE_SHIFT) /* 96 KBytes */ +# define SIM_SOPT1_RAMSIZE_128KB (9 << SIM_SOPT1_RAMSIZE_SHIFT) /* 128 KBytes */ +# define SIM_SOPT1_RAMSIZE_256KB (10 << SIM_SOPT1_RAMSIZE_SHIFT) /* 256 KBytes */ +#endif + /* Bits 16-18: Reserved */ +#if defined(KINETIS_SIM_HAS_SOPT1_OSC32KSEL) +# define SIM_SOPT1_OSC32KSEL_SHIFT (20-KINETIS_SIM_HAS_SOPT1_OSC32KSEL_BITS) /* Bit 19 or 18: 32K oscillator clock select */ +# define SIM_SOPT1_OSC32KSEL_MASK (KINETIS_SIM_SOPT1_OSC32KSEL_MASK << SIM_SOPT1_OSC32KSEL_SHIFT) +# define SIM_SOPT1_OSC32KSEL(n) ((((n) & KINETIS_SIM_SOPT1_OSC32KSEL_MASK)) << SIM_SOPT1_OSC32KSEL_SHIFT) +# if KINETIS_SIM_HAS_SOPT1_OSC32KSEL_BITS == 1 +# define SIM_SOPT1_OSC32KSEL_OSC32KCLK (((0 & KINETIS_SIM_SOPT1_OSC32KSEL_MASK)) << SIM_SOPT1_OSC32KSEL_SHIFT) +# define SIM_SOPT1_OSC32KSEL_RTC (((1 & KINETIS_SIM_SOPT1_OSC32KSEL_MASK)) << SIM_SOPT1_OSC32KSEL_SHIFT) +# endif +# if KINETIS_SIM_HAS_SOPT1_OSC32KSEL_BITS == 2 +# define SIM_SOPT1_OSC32KSEL_OSC32KCLK (((0 & KINETIS_SIM_SOPT1_OSC32KSEL_MASK)) << SIM_SOPT1_OSC32KSEL_SHIFT) +# define SIM_SOPT1_OSC32KSEL_RTC (((2 & KINETIS_SIM_SOPT1_OSC32KSEL_MASK)) << SIM_SOPT1_OSC32KSEL_SHIFT) +# define SIM_SOPT1_OSC32KSEL_LPO1KZ (((3 & KINETIS_SIM_SOPT1_OSC32KSEL_MASK)) << SIM_SOPT1_OSC32KSEL_SHIFT) +# endif +#endif + /* Bits 20-28: Reserved */ +#if defined(KINETIS_SIM_HAS_SOPT1_USBVSTBY) + /* Bits 24-28: Reserved */ +# define SIM_SOPT1_USBVSTBY (1 << 29) /* Bit 29: USB voltage regulator in standby mode during VLPR and VLPW modes */ +#endif +#if defined(KINETIS_SIM_HAS_SOPT1_USBSSTBY) +# define SIM_SOPT1_USBSTBY (1 << 30) /* Bit 30: USB voltage regulator in standby mode */ +#endif +#if defined(KINETIS_SIM_HAS_SOPT1_USBREGEN) +# define SIM_SOPT1_USBREGEN (1 << 31) /* Bit 31: USB voltage regulator enable */ +#endif + +#if defined(KINETIS_SIM_HAS_SOPT1CFG) +/* SOPT1 Configuration Register */ + + /* Bits 0-22: Reserved */ +# if defined(KINETIS_SIM_HAS_SOPT1CFG_URWE) +# define SIM_SOPT1CFG_URWE (1 << 24) /* Bit 24: USB voltage regulator enable write enable */ +# endif +# if defined(KINETIS_SIM_HAS_SOPT1CFG_USSWE) +# define SIM_SOPT1CFG_USSWE (1 << 25) /* Bit 25: USB voltage regulator VLP standby write enable */ +# endif +# if defined(KINETIS_SIM_HAS_SOPT1CFG_UVSWE) +# define SIM_SOPT1CFG_UVSWE (1 << 26) /* Bit 26: USB voltage regulator stop standby write enable */ +# endif + /* Bits 27-31: Reserved */ +#endif + + +#if defined(KINETIS_SIM_HAS_USBPHYCTL) +/* USB PHY Control Register */ + + /* Bits 0-7: Reserved */ +# if defined(KINETIS_SIM_HAS_USBPHYCTL_USBVREGSEL) +# define SIM_USBPHYCTL_USBVREGSEL (1 << 8) /* Bit 8: Selects the default input voltage source */ +# endif +# if defined(KINETIS_SIM_HAS_USBPHYCTL_USBVREGPD) +# define SIM_USBPHYCTL_USBVREGPD (1 << 9) /* Bit 9: Enables the pulldown on the output of the USB Regulator */ +# endif + /* Bits 10-19: Reserved */ +# if defined(KINETIS_SIM_HAS_USBPHYCTL_USB3VOUTTRG) +# define SIM_USBPHYCTL_USB3VOUTTRG_SHIFT (20) /* Bit 20-22: USB 3.3V Output Target */ +# define SIM_USBPHYCTL_USB3VOUTTRG_MASK (7 << SIM_USBPHYCTL_USB3VOUTTRG_SHIFT) +# define SIM_USBPHYCTL_USB3VOUTTRG_2V733 (0 << SIM_USBPHYCTL_USB3VOUTTRG_SHIFT) /* 2.733V */ +# define SIM_USBPHYCTL_USB3VOUTTRG_3V020 (1 << SIM_USBPHYCTL_USB3VOUTTRG_SHIFT) /* 3.020V */ +# define SIM_USBPHYCTL_USB3VOUTTRG_3V074 (2 << SIM_USBPHYCTL_USB3VOUTTRG_SHIFT) /* 3.074V */ +# define SIM_USBPHYCTL_USB3VOUTTRG_3V130 (3 << SIM_USBPHYCTL_USB3VOUTTRG_SHIFT) /* 3.130V */ +# define SIM_USBPHYCTL_USB3VOUTTRG_3V188 (4 << SIM_USBPHYCTL_USB3VOUTTRG_SHIFT) /* 3.188V */ +# define SIM_USBPHYCTL_USB3VOUTTRG_3V248 (5 << SIM_USBPHYCTL_USB3VOUTTRG_SHIFT) /* 3.248V */ +# define SIM_USBPHYCTL_USB3VOUTTRG_3V310 (6 << SIM_USBPHYCTL_USB3VOUTTRG_SHIFT) /* 3.310V (default) */ +# define SIM_USBPHYCTL_USB3VOUTTRG_3V662 (7 << SIM_USBPHYCTL_USB3VOUTTRG_SHIFT) /* 3.662V (For Freescale use only, not for customer use) */ +# endif +# if defined(KINETIS_SIM_HAS_USBPHYCTL_USBDISILIM) +# define SIM_USBPHYCTL_USBDISILIM (1 << 23) /* Bit 23: USB Disable Inrush Current Limit */ +# endif + /* Bits 24-31: Reserved */ +#endif /* System Options Register 2 */ -#define SIM_SOPT2_MCGCLKSEL (1 << 0) /* Bit 0: MCG clock select */ - /* Bits 1-7: Reserved */ -#define SIM_SOPT2_FBSL_SHIFT (8) /* Bits 8-9: FlexBus security level */ -#define SIM_SOPT2_FBSL_MASK (3 << SIM_SOPT2_FBSL_SHIFT) -# define SIM_SOPT2_FBSL_NONE (0 << SIM_SOPT2_FBSL_SHIFT) /* All off-chip accesses disallowed */ -# define SIM_SOPT2_FBSL_DATA (2 << SIM_SOPT2_FBSL_SHIFT) /* Off-chip data accesses are allowed */ -# define SIM_SOPT2_FBSL_ALL (3 << SIM_SOPT2_FBSL_SHIFT) /* All Off-chip accesses allowed */ - /* Bit 10: Reserved */ -#define SIM_SOPT2_CMTUARTPAD (1 << 11) /* Bit 11: CMT/UART pad drive strength */ -#define SIM_SOPT2_TRACECLKSEL (1 << 12) /* Bit 12: Debug trace clock select */ - /* Bits 13-15: Reserved */ -#define SIM_SOPT2_PLLFLLSEL (1 << 16) /* Bit 16: PLL/FLL clock select */ - /* Bit 17: Reserved */ -#define SIM_SOPT2_USBSRC (1 << 18) /* Bit 18: USB clock source select */ - /* Bit 19: Reserved */ -#if defined(KINETIS_K60) || defined(KINETIS_K64) || defined(KINETIS_K66) -# define SIM_SOPT2_RMIISRC_SHIFT (19) /* Bit 19: RMII clock source select */ -# define SIM_SOPT2_RMIISRC_EXTAL (0 << SIM_SOPT2_RMIISRC_SHIFT) /* EXTAL clock */ -# define SIM_SOPT2_RMIISRC_EXTBYP (1 << SIM_SOPT2_RMIISRC_SHIFT) /* External bypass clock (ENET_1588_CLKIN) */ -# define SIM_SOPT2_TIMESRC_SHIFT (20) /* Bit 20-21: IEEE 1588 timestamp clock source select (K60) */ -# define SIM_SOPT2_TIMESRC_MASK (3 << SIM_SOPT2_TIMESRC_SHIFT) -# define SIM_SOPT2_TIMESRC_CORE (0 << SIM_SOPT2_TIMESRC_SHIFT) /* Core/system clock */ -# define SIM_SOPT2_TIMESRC_PLLSEL (1 << SIM_SOPT2_TIMESRC_SHIFT) /* MCGFLLCLK,MCGPLLCLK,IRC48M,USB1 PFD - clock as selected by SOPT2[PLLFLLSEL] */ -# define SIM_SOPT2_TIMESRC_OSCERCLK (2 << SIM_SOPT2_TIMESRC_SHIFT) /* OSCERCLK clock */ -# define SIM_SOPT2_TIMESRC_EXTBYP (0 << SIM_SOPT2_TIMESRC_SHIFT) /* External bypass clock (ENET_1588_CLKIN) */ +#if defined(KINETIS_SIM_HAS_SOPT2) +# if defined(KINETIS_SIM_HAS_SOPT2_MCGCLKSEL) +# define SIM_SOPT2_MCGCLKSEL (1 << 0) /* Bit 0: MCG clock select */ +# endif +# if defined(KINETIS_SIM_HAS_SOPT2_USBSLSRC) +# define SIM_SOPT2_USBSLSRC (1 << 0) /* Bit 0: USB Slow Clock Source */ +# endif +# if defined(KINETIS_SIM_HAS_SOPT2_USBREGEN) +# define SIM_SOPT2_USBREGEN (1 << 1) /* Bit 1: USB PHY PLL Regulator Enable */ +# endif + /* Bits 2-3: Reserved */ +# if defined(KINETIS_SIM_HAS_SOPT2_USBHSRC) +# define SIM_SOPT2_USBSHSRC_SHIFT (2) /* Bit 2-3: USB HS clock source select */ +# define SIM_SOPT2_USBSHSRC_MASK (3 << SIM_SOPT2_USBSHSRC_SHIFT) +# define SIM_SOPT2_USBSHSRC_BUSCLK (0 << SIM_SOPT2_USBSHSRC_SHIFT) +# define SIM_SOPT2_USBSHSRC_MCGPLL0CLK (1 << SIM_SOPT2_USBSHSRC_SHIFT) +# define SIM_SOPT2_USBSHSRC_MCGPLL1CLK (2 << SIM_SOPT2_USBSHSRC_SHIFT) +# define SIM_SOPT2_USBSHSRC_OSC0ERCLK (3 << SIM_SOPT2_USBSHSRC_SHIFT) +# endif +# if defined(KINETIS_SIM_HAS_SOPT2_RTCCLKOUTSEL) +# define SIM_SOPT2_RTCCLKOUTSEL (1 << 4) /* Bit 4: RTC clock out select */ +# endif +# if defined(KINETIS_SIM_HAS_SOPT2_CLKOUTSEL) +# define SIM_SOPT2_CLKOUTSEL_SHIFT (5) /* Bits 5-7: CLKOUT select */ +# define SIM_SOPT2_CLKOUTSEL_MASK (7 << SIM_SOPT2_CLKOUTSEL_SHIFT) +# define SIM_SOPT2_CLKOUTSEL_FBCLKOUT (0 << SIM_SOPT2_CLKOUTSEL_SHIFT) +# define SIM_SOPT2_CLKOUTSEL_FLSHCLK (2 << SIM_SOPT2_CLKOUTSEL_SHIFT) +# define SIM_SOPT2_CLKOUTSEL_LPO1KHZ (3 << SIM_SOPT2_CLKOUTSEL_SHIFT) +# define SIM_SOPT2_CLKOUTSEL_MCGIRCLK (4 << SIM_SOPT2_CLKOUTSEL_SHIFT) +# define SIM_SOPT2_CLKOUTSEL_RTC32768KHZ (5 << SIM_SOPT2_CLKOUTSEL_SHIFT) +# define SIM_SOPT2_CLKOUTSEL_OSCERCLK0 (6 << SIM_SOPT2_CLKOUTSEL_SHIFT) +# define SIM_SOPT2_CLKOUTSEL_IRC48MHZ (7 << SIM_SOPT2_CLKOUTSEL_SHIFT) +# endif +# if defined(KINETIS_SIM_HAS_SOPT2_FBSL) +# define SIM_SOPT2_FBSL_SHIFT (8) /* Bits 8-9: FlexBus security level */ +# define SIM_SOPT2_FBSL_MASK (3 << SIM_SOPT2_FBSL_SHIFT) +# define SIM_SOPT2_FBSL_NONE (0 << SIM_SOPT2_FBSL_SHIFT) /* All off-chip accesses disallowed */ +# define SIM_SOPT2_FBSL_DATA (2 << SIM_SOPT2_FBSL_SHIFT) /* Off-chip data accesses are allowed */ +# define SIM_SOPT2_FBSL_ALL (3 << SIM_SOPT2_FBSL_SHIFT) /* All Off-chip accesses allowed */ +# endif + /* Bit 10: Reserved */ +# if defined(KINETIS_SIM_HAS_SOPT2_CMTUARTPAD) +# define SIM_SOPT2_CMTUARTPAD (1 << 11) /* Bit 11: CMT/UART pad drive strength */ +# endif +# if defined(KINETIS_SIM_HAS_SOPT2_PTD7PAD) +# define SIM_SOPT2_PTD7PAD (1 << 11) /* Bit 11: PTD7P pad drive strength */ +# endif +# if defined(KINETIS_SIM_HAS_SOPT2_TRACECLKSEL) +# define SIM_SOPT2_TRACECLKSEL (1 << 12) /* Bit 12: Debug trace clock select */ +# endif + /* Bits 13-15: Reserved */ +# if defined(KINETIS_SIM_HAS_SOPT2_PLLFLLSEL) +# define SIM_SOPT2_PLLFLLSEL_SHIFT (16) /* Bits 16-[17]: PLL/FLL clock select */ +# define SIM_SOPT2_PLLFLLSEL_MASK (KINETIS_SIM_SOPT2_PLLFLLSEL_MASK << SIM_SOPT2_PLLFLLSEL_SHIFT) +# define SIM_SOPT2_PLLFLLSEL(n) (((n) & KINETIS_SIM_SOPT2_PLLFLLSEL_MASK) << SIM_SOPT2_PLLFLLSEL_SHIFT) +# define SIM_SOPT2_PLLFLLSEL_MCGFLLCLK ((0 & KINETIS_SIM_SOPT2_PLLFLLSEL_MASK) << SIM_SOPT2_PLLFLLSEL_SHIFT) +# define SIM_SOPT2_PLLFLLSEL_MCGPLLCLK ((1 & KINETIS_SIM_SOPT2_PLLFLLSEL_MASK) << SIM_SOPT2_PLLFLLSEL_SHIFT) +# if KINETIS_SIM_HAS_SOPT2_PLLFLLSEL_BITS > 1 +# define SIM_SOPT2_PLLFLLSEL_USB1PFD ((2 & KINETIS_SIM_SOPT2_PLLFLLSEL_MASK) << SIM_SOPT2_PLLFLLSEL_SHIFT) +# define SIM_SOPT2_PLLFLLSEL_IRC48MHZ ((3 & KINETIS_SIM_SOPT2_PLLFLLSEL_MASK) << SIM_SOPT2_PLLFLLSEL_SHIFT) +# endif +# endif + /* Bit 17: Reserved */ +# if defined(KINETIS_SIM_HAS_SOPT2_USBSRC) +# define SIM_SOPT2_USBSRC (1 << 18) /* Bit 18: USB clock source select */ +# endif + /* Bit 19: Reserved */ +# if defined(KINETIS_SIM_HAS_SOPT2_RMIISRC) +# define SIM_SOPT2_RMIISRC_SHIFT (19) /* Bit 19: RMII clock source select */ +# define SIM_SOPT2_RMIISRC_EXTAL (0 << SIM_SOPT2_RMIISRC_SHIFT) /* EXTAL clock */ +# define SIM_SOPT2_RMIISRC_EXTBYP (1 << SIM_SOPT2_RMIISRC_SHIFT) /* External bypass clock (ENET_1588_CLKIN) */ +# endif +# if defined(KINETIS_SIM_HAS_SOPT2_TIMESRC) +# define SIM_SOPT2_TIMESRC_SHIFT (20) /* Bit 20-21: IEEE 1588 timestamp clock source select */ +# define SIM_SOPT2_TIMESRC_MASK (3 << SIM_SOPT2_TIMESRC_SHIFT) +# define SIM_SOPT2_TIMESRC_CORE (0 << SIM_SOPT2_TIMESRC_SHIFT) /* Core/system clock */ +# define SIM_SOPT2_TIMESRC_PLLSEL (1 << SIM_SOPT2_TIMESRC_SHIFT) /* MCGFLLCLK,MCGPLLCLK,IRC48M,USB1 PFD + clock as selected by SOPT2[PLLFLLSEL] */ +# define SIM_SOPT2_TIMESRC_OSCERCLK (2 << SIM_SOPT2_TIMESRC_SHIFT) /* OSCERCLK clock */ +# define SIM_SOPT2_TIMESRC_EXTBYP (3 << SIM_SOPT2_TIMESRC_SHIFT) /* External bypass clock (ENET_1588_CLKIN) */ +# endif +# if defined(KINETIS_SIM_HAS_SOPT2_FLEXIOSRC) + /* TBD */ +# endif + /* Bits 22-23: Reserved */ +# if defined(KINETIS_SIM_HAS_SOPT2_USBFSRC) +# define SIM_SOPT2_USBFSRC_SHIFT (22) /* Bits 22-23: USB FS clock source select */ +# define SIM_SOPT2_USBFSRC_MASK (3 << SIM_SOPT2_USBFSRC_SHIFT) +# define SIM_SOPT2_USBFSRC_MCGCLK (0 << SIM_SOPT2_USBFSRC_SHIFT) /* MCGFLLCLK,MCGPLLCLK clock as selected by SOPT2[PLLFLLSEL] */ +# define SIM_SOPT2_USBFSRC_MCGPLL0CLK (1 << SIM_SOPT2_USBFSRC_SHIFT) /* MCGPLL0CLK clock */ +# define SIM_SOPT2_USBFSRC_MCGPLL1CLK (2 << SIM_SOPT2_USBFSRC_SHIFT) /* MCGPLL1CLK clock */ +# define SIM_SOPT2_USBFSRC_OCS0ERCLK (3 << SIM_SOPT2_USBFSRC_SHIFT) /* OSC0ERCLK clock */ +# endif +# if defined(KINETIS_SIM_HAS_SOPT2_TPMSRC) +# define SIM_SOPT2_TPMSRC_SHIFT (24) /* Bits 24-25: TPM clock source select */ +# define SIM_SOPT2_TPMSRC_MASK (3 << SIM_SOPT2_TPMSRC_SHIFT) +# define SIM_SOPT2_TPMSRC_CORE (0 << SIM_SOPT2_TPMSRC_SHIFT) /* Clock disabled */ +# define SIM_SOPT2_TPMSRC_MCGCLK (1 << SIM_SOPT2_TPMSRC_SHIFT) /* MCGFLLCLK,MCGPLLCLK,IRC48M,USB1 PFD + clock as selected by SOPT2[PLLFLLSEL] and then + divided by the PLLFLLCLK fractional divider + as configured by SIM_CLKDIV3[PLLFLLFRAC, PLLFLLDIV] */ +# define SIM_SOPT2_TPMSRC_OCSERCLK (2 << SIM_SOPT2_TPMSRC_SHIFT) /* OSCERCLK clock */ +# define SIM_SOPT2_TPMSRC_EXTBYP (3 << SIM_SOPT2_TPMSRC_SHIFT) /* MCGIRCLK clock */ +# endif +# if defined(KINETIS_SIM_HAS_SOPT2_I2SSRC) +# define SIM_SOPT2_I2SSRC_SHIFT (24) /* Bits 24-25: I2S master clock source select */ +# define SIM_SOPT2_I2SSRC_MASK (3 << SIM_SOPT2_I2SSRC_SHIFT) +# define SIM_SOPT2_I2SCSRC_CORE (0 << SIM_SOPT2_I2SSRC_SHIFT) /* Core/system clock / I2S fractional divider */ +# define SIM_SOPT2_I2SCSRC_MCGCLK (1 << SIM_SOPT2_I2SSRC_SHIFT) /* MCGPLLCLK/MCGFLLCLK clock/ I2S fractional divider */ +# define SIM_SOPT2_I2SCSRC_OCSERCLK (2 << SIM_SOPT2_I2SSRC_SHIFT) /* OSCERCLK clock */ +# define SIM_SOPT2_I2SCSRC_EXTBYP (3 << SIM_SOPT2_I2SSRC_SHIFT) /* External bypass clock (I2S0_CLKIN) */ +# endif + /* Bits 26-27: Reserved */ +# if defined(KINETIS_SIM_HAS_SOPT2_LPUARTSRC) +# define SIM_SOPT2_LPUARTSRC_SHIFT (26) /* Bits 26-27: LPUART clock source select */ +# define SIM_SOPT2_LPUARTSRC_MASK (3 << SIM_SOPT2_LPUARTSRC_SHIFT) +# define SIM_SOPT2_LPUARTSRC_CORE (0 << SIM_SOPT2_LPUARTSRC_SHIFT) /* Clock disabled */ +# define SIM_SOPT2_LPUARTSRC_MCGCLK (1 << SIM_SOPT2_LPUARTSRC_SHIFT) /* MCGFLLCLK,MCGPLLCLK,IRC48M,USB1 PFD + clock as selected by SOPT2[PLLFLLSEL] and then + divided by the PLLFLLCLK fractional divider + as configured by SIM_CLKDIV3[PLLFLLFRAC, PLLFLLDIV] */ +# define SIM_SOPT2_LPUARTSRC_OCSERCLK (2 << SIM_SOPT2_LPUARTSRC_SHIFT) /* OSCERCLK clock */ +# define SIM_SOPT2_LPUARTSRC_EXTBYP (3 << SIM_SOPT2_LPUARTSRC_SHIFT) /* MCGIRCLK clock */ +# endif +# if defined(KINETIS_SIM_HAS_SOPT2_SDHCSRC) +# define SIM_SOPT2_SDHCSRC_SHIFT (28) /* Bits 28-29: SDHC clock source select */ +# define SIM_SOPT2_SDHCSRC_MASK (3 << SIM_SOPT2_SDHCSRC_SHIFT) +# define SIM_SOPT2_SDHCSRC_CORE (0 << SIM_SOPT2_SDHCSRC_SHIFT) /* Core/system clock */ +# define SIM_SOPT2_SDHCSRC_MCGCLK (1 << SIM_SOPT2_SDHCSRC_SHIFT) /* MCGPLLCLK/MCGFLLCLK clock */ +# define SIM_SOPT2_SDHCSRC_OCSERCLK (2 << SIM_SOPT2_SDHCSRC_SHIFT) /* OSCERCLK clock */ +# define SIM_SOPT2_SDHCSRC_EXTBYP (3 << SIM_SOPT2_SDHCSRC_SHIFT) /* External bypass clock (SDHC0_CLKIN) */ + /* Bits 30-31: Reserved */ +# endif + /* Bits 30-31: Reserved */ +# if defined(KINETIS_SIM_HAS_SOPT2_NFCSRC) +# define SIM_SOPT2_NFCSRC_SHIFT (30) /* Bits 30-31: NFC Flash clock source select */ +# define SIM_SOPT2_NFCSRC_MASK (3 << SIM_SOPT2_NFCSRC_SHIFT) +# define SIM_SOPT2_NFCSRC_BUS (0 << SIM_SOPT2_NFCSRC_SHIFT) /* BUS clock */ +# define SIM_SOPT2_NFCSRC_MCGPLL0CLK (1 << SIM_SOPT2_NFCSRC_SHIFT) /* MCGPLL0CLK clock */ +# define SIM_SOPT2_NFCSRC_MCGPLL1CLK (2 << SIM_SOPT2_NFCSRC_SHIFT) /* MCGPLL1CLK clock */ +# define SIM_SOPT2_NFCSRC_OCS0ERCLK (3 << SIM_SOPT2_NFCSRC_SHIFT) /* OSC0ERCLK clock */ +# endif #endif - /* Bits 12-23: Reserved */ -#define SIM_SOPT2_I2SSRC_SHIFT (24) /* Bits 24-25: I2S master clock source select */ -#define SIM_SOPT2_I2SSRC_MASK (3 << SIM_SOPT2_I2SSRC_SHIFT) -# define SIM_SOPT2_I2SCSRC_CORE (0 << SIM_SOPT2_I2SSRC_SHIFT) /* Core/system clock / I2S fractional divider*/ -# define SIM_SOPT2_I2SCSRC_MCGCLK (1 << SIM_SOPT2_I2SSRC_SHIFT) /* MCGPLLCLK/MCGFLLCLK clock/ I2S fractional divider */ -# define SIM_SOPT2_I2SCSRC_OCSERCLK (2 << SIM_SOPT2_I2SSRC_SHIFT) /* OSCERCLK clock */ -# define SIM_SOPT2_I2SCSRC_EXTBYP (3 << SIM_SOPT2_I2SSRC_SHIFT) /* External bypass clock (I2S0_CLKIN) */ - /* Bits 26-27: Reserved */ -#define SIM_SOPT2_SDHCSRC_SHIFT (28) /* Bits 28-29: SDHC clock source select*/ -#define SIM_SOPT2_SDHCSRC_MASK (3 << SIM_SOPT2_SDHCSRC_SHIFT) -# define SIM_SOPT2_SDHCSRC_CORE (0 << SIM_SOPT2_SDHCSRC_SHIFT) /* Core/system clock */ -# define SIM_SOPT2_SDHCSRC_MCGCLK (1 << SIM_SOPT2_SDHCSRC_SHIFT) /* MCGPLLCLK/MCGFLLCLK clock */ -# define SIM_SOPT2_SDHCSRC_OCSERCLK (2 << SIM_SOPT2_SDHCSRC_SHIFT) /* OSCERCLK clock */ -# define SIM_SOPT2_SDHCSRC_EXTBYP (3 << SIM_SOPT2_SDHCSRC_SHIFT) /* External bypass clock (SDHC0_CLKIN) */ /* Bits 30-31: Reserved */ /* System Options Register 4 */ -#define SIM_SOPT4_FTM0FLT0 (1 << 0) /* Bit 0: FTM0 Fault 0 Select */ -#define SIM_SOPT4_FTM0FLT1 (1 << 1) /* Bit 1: FTM0 Fault 1 Select */ -#define SIM_SOPT4_FTM0FLT2 (1 << 2) /* Bit 2: FTM0 Fault 2 Select */ - /* Bit 3: Reserved */ -#define SIM_SOPT4_FTM1FLT0 (1 << 4) /* Bit 4: FTM1 Fault 0 Select */ - /* Bits 5-7: Reserved */ -#define SIM_SOPT4_FTM2FLT0 (1 << 8) /* Bit 8: FTM2 Fault 0 Select */ - /* Bits 9-17: Reserved */ -#if defined(CONFIG_KINETIS_FTM3) - /* Bits 9-11,13-17: Reserved */ -# define SIM_SOPT4_FTM3FLT0 (1 << 12) /* Bit 12: FTM3 Fault 0 Select */ +#define SIM_SOPT4_FTM0FLT0 (1 << 0) /* Bit 0: FTM0 Fault 0 Select */ +#define SIM_SOPT4_FTM0FLT1 (1 << 1) /* Bit 1: FTM0 Fault 1 Select */ +#define SIM_SOPT4_FTM0FLT2 (1 << 2) /* Bit 2: FTM0 Fault 2 Select */ + /* Bit 3: Reserved */ +#if defined(KINETIS_SIM_HAS_SOPT4_FTM0FLT3) +# define SIM_SOPT4_FTM0FLT3 (1 << 3) /* Bit 3: FTM0 Fault 3 Select */ #endif -#define SIM_SOPT4_FTM1CH0SRC_SHIFT (18) /* Bits 18-19: FTM1 channel 0 input capture source select */ -#define SIM_SOPT4_FTM1CH0SRC_MASK (3 << SIM_SOPT4_FTM1CH0SRC_SHIFT) -# define SIM_SOPT4_FTM1CH0SRC_CH0 (0 << SIM_SOPT4_FTM1CH0SRC_SHIFT) /* FTM1_CH0 signal */ -# define SIM_SOPT4_FTM1CH0SRC_CMP0 (1 << SIM_SOPT4_FTM1CH0SRC_SHIFT) /* CMP0 output */ -# define SIM_SOPT4_FTM1CH0SRC_CMP1 (2 << SIM_SOPT4_FTM1CH0SRC_SHIFT) /* CMP1 output */ -#define SIM_SOPT4_FTM2CH0SRC_SHIFT (20) /* Bits 20-21: FTM2 channel 0 input capture source select */ -#define SIM_SOPT4_FTM2CH0SRC_MASK (3 << SIM_SOPT4_FTM2CH0SRC_SHIFT) -# define SIM_SOPT4_FTM2CH0SRC_CH0 (0 << SIM_SOPT4_FTM2CH0SRC_SHIFT) /* FTM2_CH0 signal */ -# define SIM_SOPT4_FTM2CH0SRC_CMP0 (1 << SIM_SOPT4_FTM2CH0SRC_SHIFT) /* CMP0 output */ -# define SIM_SOPT4_FTM2CH0SRC_CMP1 (2 << SIM_SOPT4_FTM2CH0SRC_SHIFT) /* CMP1 output */ - /* Bits 22-23: Reserved */ -#define SIM_SOPT4_FTM0CLKSEL (1 << 24) /* Bit 24: FlexTimer 0 External Clock Pin Select */ -#define SIM_SOPT4_FTM1CLKSEL (1 << 25) /* Bit 25: FTM1 External Clock Pin Select */ -#define SIM_SOPT4_FTM2CLKSEL (1 << 26) /* Bit 26: FlexTimer 2 External Clock Pin Select */ - /* Bits 27-31: Reserved */ -#if defined(CONFIG_KINETIS_FTM3) -# define SIM_SOPT4_FTM3CLKSEL (1 << 27) /* Bit 27: FlexTimer 3 External Clock Pin Select */ -# define SIM_SOPT4_FTM3TRG0SRC (1 << 30) /* Bit 30: FlexTimer 3 Hardware Trigger 0 Source Select */ -# define SIM_SOPT4_FTM3TRG1SRC (1 << 31) /* Bit 31: FlexTimer 3 Hardware Trigger 1 Source Select */ +#define SIM_SOPT4_FTM1FLT0 (1 << 4) /* Bit 4: FTM1 Fault 0 Select */ + /* Bits 5-7: Reserved */ +#define SIM_SOPT4_FTM2FLT0 (1 << 8) /* Bit 8: FTM2 Fault 0 Select */ + /* Bits 9-17: Reserved */ +#if defined(KINETIS_SIM_HAS_SOPT4_FTM3FLT0) + /* Bits 9-11,13-17: Reserved */ +# define SIM_SOPT4_FTM3FLT0 (1 << 12) /* Bit 12: FTM3 Fault 0 Select */ +#endif +#if defined(KINETIS_SIM_HAS_SOPT4_FTM1CH0SRC) +# define SIM_SOPT4_FTM1CH0SRC_SHIFT (18) /* Bits 18-19: FTM1 channel 0 input capture source select */ +# define SIM_SOPT4_FTM1CH0SRC_MASK (3 << SIM_SOPT4_FTM1CH0SRC_SHIFT) +# define SIM_SOPT4_FTM1CH0SRC_CH0 (0 << SIM_SOPT4_FTM1CH0SRC_SHIFT) /* FTM1_CH0 signal */ +# define SIM_SOPT4_FTM1CH0SRC_CMP0 (1 << SIM_SOPT4_FTM1CH0SRC_SHIFT) /* CMP0 output */ +# define SIM_SOPT4_FTM1CH0SRC_CMP1 (2 << SIM_SOPT4_FTM1CH0SRC_SHIFT) /* CMP1 output */ +# if KINETIS_SIM_HAS_SOPT4_FTM1CH0SRC > 2 +# define SIM_SOPT4_FTM1CH0SRC_USBSOF (3 << SIM_SOPT4_FTM1CH0SRC_SHIFT) /* USB start of frame pulse */ +# endif +#endif +#if defined(KINETIS_SIM_HAS_SOPT4_FTM2CH0SRC) +# define SIM_SOPT4_FTM2CH0SRC_SHIFT (20) /* Bits 20-21: FTM2 channel 0 input capture source select */ +# define SIM_SOPT4_FTM2CH0SRC_MASK (3 << SIM_SOPT4_FTM2CH0SRC_SHIFT) +# define SIM_SOPT4_FTM2CH0SRC_CH0 (0 << SIM_SOPT4_FTM2CH0SRC_SHIFT) /* FTM2_CH0 signal */ +# define SIM_SOPT4_FTM2CH0SRC_CMP0 (1 << SIM_SOPT4_FTM2CH0SRC_SHIFT) /* CMP0 output */ +# define SIM_SOPT4_FTM2CH0SRC_CMP1 (2 << SIM_SOPT4_FTM2CH0SRC_SHIFT) /* CMP1 output */ +#endif + /* Bits 22-23: Reserved */ +#if defined(KINETIS_SIM_HAS_SOPT4_FTM2CH1SRC) + /* Bit 23: Reserved */ + #define SIM_SOPT4_FTM2CH1SRC (1 << 22) /* Bit 22: FTM2 channel 1 input capture source select */ +#endif +#define SIM_SOPT4_FTM0CLKSEL (1 << 24) /* Bit 24: FlexTimer 0 External Clock Pin Select */ +#define SIM_SOPT4_FTM1CLKSEL (1 << 25) /* Bit 25: FTM1 External Clock Pin Select */ +#define SIM_SOPT4_FTM2CLKSEL (1 << 26) /* Bit 26: FlexTimer 2 External Clock Pin Select */ + /* Bits 27-31: Reserved */ +#if defined(KINETIS_SIM_HAS_SOPT4_FTM3TRG1SRC) || defined(KINETIS_SIM_HAS_SOPT4_FTM3TRG0SRC) +# define SIM_SOPT4_FTM3CLKSEL (1 << 27) /* Bit 27: FlexTimer 3 External Clock Pin Select */ +#endif +#if defined(KINETIS_SIM_HAS_SOPT4_FTM0TRG0SRC) + /* Bits 27,30-31: Reserved */ +# define SIM_SOPT4_FTM0TRG0SRC (1 << 28) /* Bit 28: FlexTimer 0 Hardware Trigger 0 Source Select */ +#endif +#if defined(KINETIS_SIM_HAS_SOPT4_FTM0TRG1SRC) + /* Bits 27,30-31: Reserved */ +# define SIM_SOPT4_FTM0TRG1SRC (1 << 29) /* Bit 29: FlexTimer 0 Hardware Trigger 1 Source Select */ +#endif +#if defined(KINETIS_SIM_HAS_SOPT4_FTM3TRG0SRC) +# define SIM_SOPT4_FTM3TRG0SRC (1 << 30) /* Bit 30: FlexTimer 3 Hardware Trigger 0 Source Select */ +#endif +#if defined(KINETIS_SIM_HAS_SOPT4_FTM3TRG1SRC) +# define SIM_SOPT4_FTM3TRG1SRC (1 << 31) /* Bit 31: FlexTimer 3 Hardware Trigger 1 Source Select */ #endif /* System Options Register 5 */ -#define SIM_SOPT5_UART0TXSRC_SHIFT (0) /* Bits 0-1: UART 0 transmit data source select */ -#define SIM_SOPT5_UART0TXSRC_MASK (3 << SIM_SOPT5_UART0TXSRC_SHIFT) -# define SIM_SOPT5_UART0TXSRC_TX (0 << SIM_SOPT5_UART0TXSRC_SHIFT) /* UART0_TX pin */ -# define SIM_SOPT5_UART0TXSRC_FTM1 (1 << SIM_SOPT5_UART0TXSRC_SHIFT) /* UART0_TX modulated with FTM1 ch0 output */ -# define SIM_SOPT5_UART0TXSRC_FTM2 (2 << SIM_SOPT5_UART0TXSRC_SHIFT) /* UART0_TX modulated with FTM2 ch0 output */ -#define SIM_SOPT5_UART0RXSRC_SHIFT (2) /* Bits 2-3: UART 0 receive data source select */ -#define SIM_SOPT5_UART0RXSRC_MASK (3 << SIM_SOPT5_UART0RXSRC_SHIFT) -# define SIM_SOPT5_UART0RXSRC_RX (0 << SIM_SOPT5_UART0RXSRC_SHIFT) /* UART0_RX pin */ -# define SIM_SOPT5_UART0RXSRC_CMP0 (1 << SIM_SOPT5_UART0RXSRC_SHIFT) /* CMP0 */ -# define SIM_SOPT5_UART0RXSRC_CMP1 (2 << SIM_SOPT5_UART0RXSRC_SHIFT) /* CMP1 */ -#define SIM_SOPT5_UART1TXSRC_SHIFT (4) /* Bits 4-5: UART 1 transmit data source select */ -#define SIM_SOPT5_UART1TXSRC_MASK (3 << SIM_SOPT5_UART1TXSRC_SHIFT) -# define SIM_SOPT5_UART1TXSRC_TX (0 << SIM_SOPT5_UART1TXSRC_SHIFT) /* UART1_TX pin */ -# define SIM_SOPT5_UART1TXSRC_FTM1 (1 << SIM_SOPT5_UART1TXSRC_SHIFT) /* UART1_TX modulated with FTM1 ch0 output */ -# define SIM_SOPT5_UART1TXSRC_FTM2 (2 << SIM_SOPT5_UART1TXSRC_SHIFT) /* UART1_TX modulated with FTM2 ch0 output */ -#define SIM_SOPT5_UART1RXSRC_SHIFT (6) /* Bits 6-7: UART 1 receive data source select */ -#define SIM_SOPT5_UART1RXSRC_MASK (3 << SIM_SOPT5_UART1RXSRC_SHIFT) -# define SIM_SOPT5_UART1RXSRC_RX (0 << SIM_SOPT5_UART1RXSRC_SHIFT) /* UART1_RX pin */ -# define SIM_SOPT5_UART1RXSRC_CMP0 (1 << SIM_SOPT5_UART1RXSRC_SHIFT) /* CMP0 */ -# define SIM_SOPT5_UART1RXSRC_CMP1 (2 << SIM_SOPT5_UART1RXSRC_SHIFT) /* CMP1 */ - /* Bits 8-31: Reserved */ +#define SIM_SOPT5_UART0TXSRC_SHIFT (0) /* Bits 0-1: UART 0 transmit data source select */ +#define SIM_SOPT5_UART0TXSRC_MASK (3 << SIM_SOPT5_UART0TXSRC_SHIFT) +# define SIM_SOPT5_UART0TXSRC_TX (0 << SIM_SOPT5_UART0TXSRC_SHIFT) /* UART0_TX pin */ +# define SIM_SOPT5_UART0TXSRC_FTM1 (1 << SIM_SOPT5_UART0TXSRC_SHIFT) /* UART0_TX modulated with FTM1 ch0 output */ +# define SIM_SOPT5_UART0TXSRC_FTM2 (2 << SIM_SOPT5_UART0TXSRC_SHIFT) /* UART0_TX modulated with FTM2 ch0 output */ +#define SIM_SOPT5_UART0RXSRC_SHIFT (2) /* Bits 2-3: UART 0 receive data source select */ +#define SIM_SOPT5_UART0RXSRC_MASK (3 << SIM_SOPT5_UART0RXSRC_SHIFT) +# define SIM_SOPT5_UART0RXSRC_RX (0 << SIM_SOPT5_UART0RXSRC_SHIFT) /* UART0_RX pin */ +# define SIM_SOPT5_UART0RXSRC_CMP0 (1 << SIM_SOPT5_UART0RXSRC_SHIFT) /* CMP0 */ +# define SIM_SOPT5_UART0RXSRC_CMP1 (2 << SIM_SOPT5_UART0RXSRC_SHIFT) /* CMP1 */ +#define SIM_SOPT5_UART1TXSRC_SHIFT (4) /* Bits 4-5: UART 1 transmit data source select */ +#define SIM_SOPT5_UART1TXSRC_MASK (3 << SIM_SOPT5_UART1TXSRC_SHIFT) +# define SIM_SOPT5_UART1TXSRC_TX (0 << SIM_SOPT5_UART1TXSRC_SHIFT) /* UART1_TX pin */ +# define SIM_SOPT5_UART1TXSRC_FTM1 (1 << SIM_SOPT5_UART1TXSRC_SHIFT) /* UART1_TX modulated with FTM1 ch0 output */ +# define SIM_SOPT5_UART1TXSRC_FTM2 (2 << SIM_SOPT5_UART1TXSRC_SHIFT) /* UART1_TX modulated with FTM2 ch0 output */ +#define SIM_SOPT5_UART1RXSRC_SHIFT (6) /* Bits 6-7: UART 1 receive data source select */ +#define SIM_SOPT5_UART1RXSRC_MASK (3 << SIM_SOPT5_UART1RXSRC_SHIFT) +# define SIM_SOPT5_UART1RXSRC_RX (0 << SIM_SOPT5_UART1RXSRC_SHIFT) /* UART1_RX pin */ +# define SIM_SOPT5_UART1RXSRC_CMP0 (1 << SIM_SOPT5_UART1RXSRC_SHIFT) /* CMP0 */ +# define SIM_SOPT5_UART1RXSRC_CMP1 (2 << SIM_SOPT5_UART1RXSRC_SHIFT) /* CMP1 */ + /* Bits 8-31: Reserved */ +#if defined(KINETIS_SIM_HAS_SOPT5_LPUART0TXSRC) + /* Bits 8-15, 18-31: Reserved */ +# define SIM_SOPT5_LPUART0TXSRC_SHIFT (16) /* Bit 16: LPUART0 transmit data source select */ +# define SIM_SOPT5_LPUART0TXSRC_MASK (3 << SIM_SOPT5_LPUART0TXSRC_SHIFT) +# define SIM_SOPT5_LPUART0TXSRC_TX (0 << SIM_SOPT5_LPUART0TXSRC_SHIFT) /* LPUART0_TX pin */ +# define SIM_SOPT5_LPUART0TXSRC_TXTMP1CH0 (1 << SIM_SOPT5_LPUART0TXSRC_SHIFT) /* LPUART0_TX pin modulated with TPM1 channel 0 output */ +# define SIM_SOPT5_LPUART0TXSRC_TXTMP2CH0 (2 << SIM_SOPT5_LPUART0TXSRC_SHIFT) /* LPUART0_TX pin modulated with TPM2 channel 0 output */ +#endif + /* Bits 8-15, 18-31: Reserved */ +#if defined(KINETIS_SIM_HAS_SOPT5_LPUART0RXSRC) + /* Bits 8-15, 20-31: Reserved */ +# define SIM_SOPT5_LPUART0RXSRC_SHIFT (18) /* Bit 18: LPUART0 receive data source select */ +# define SIM_SOPT5_LPUART0RXSRC_MASK (3 << SIM_SOPT5_LPUART0RXSRC_SHIFT) +# define SIM_SOPT5_LPUART0RXSRC_TX (0 << SIM_SOPT5_LPUART0RXSRC_SHIFT) /* LPUART0_RX pin */ +# define SIM_SOPT5_LPUART0RXSRC_TXTMP1CH0 (1 << SIM_SOPT5_LPUART0RXSRC_SHIFT) /* CMP0 output */ +# define SIM_SOPT5_LPUART0RXSRC_TXTMP2CH0 (2 << SIM_SOPT5_LPUART0RXSRC_SHIFT) /* CMP1 output */ +#endif + +#if defined(KINETIS_SIM_HAS_SOPT6) /* System Options Register 6 */ - /* Bits 0-23: Reserved */ -#define SIM_SOPT6_RSTFLTSEL_SHIFT (24) /* Bits 24-28: Reset pin filter select */ -#define SIM_SOPT6_RSTFLTSEL_MASK (31 << SIM_SOPT6_RSTFLTSEL_SHIFT) -# define SIM_SOPT6_RSTFLTSEL(n) ((uint32_t)((n)-1) << SIM_SOPT6_RSTFLTSEL_SHIFT) /* n=1..32 */ -#define SIM_SOPT6_RSTFLTEN_SHIFT (29) /* Bits 29-31: Reset pin filter enable */ -#define SIM_SOPT6_RSTFLTEN_MASK (7 << SIM_SOPT6_RSTFLTEN_SHIFT) -#define SIM_SOPT6_RSTFLTEN_DISABLED (0 << SIM_SOPT6_RSTFLTEN_SHIFT) /* All filtering disabled */ -# define SIM_SOPT6_RSTFLTEN_BUSCLK1 (1 << SIM_SOPT6_RSTFLTEN_SHIFT) /* Bus clock filter enabled (normal); LPO clock filter enabled (stop) */ -# define SIM_SOPT6_RSTFLTEN_LPO1 (2 << SIM_SOPT6_RSTFLTEN_SHIFT) /* LPO clock filter enabled */ -# define SIM_SOPT6_RSTFLTEN_BUSCLK2 (3 << SIM_SOPT6_RSTFLTEN_SHIFT) /* Bus clock filter enabled (normal); All filtering disabled (stop) */ -# define SIM_SOPT6_RSTFLTEN_LPO2 (4 << SIM_SOPT6_RSTFLTEN_SHIFT) /* PO clock filter enabled (normal); All filtering disabled (stop) */ + + /* Bits 0-23: Reserved */ +# if defined(KINETIS_SIM_HAS_SOPT6_MCC) + /* Bits 16-23: Reserved */ +# define SIM_SOPT6_MCC_SHIFT (0) /* Bits 0-15: NFC hold cycle in case FlexBus request while NFC is granted */ +# define SIM_SOPT6_MCC_MASK (0xffff << SIM_SOPT6_MCC_SHIFT) +# define SIM_SOPT6_MCC(n) (((n) & 0xffff) << SIM_SOPT6_MCC_SHIFT) +# endif + /* Bits 16-23: Reserved */ +# if defined(KINETIS_SIM_HAS_SOPT6_PCR) + /* Bits 20-23: Reserved */ +# define SIM_SOPT6_PCR_SHIFT (16) /* Bits 16-19: FlexBus hold cycles before FlexBus can release bus to NFC or to IDLE */ +# define SIM_SOPT6_PCR_MASK (7 << SIM_SOPT6_PCR_SHIFT) +# define SIM_SOPT6_PCR(n) (((n) & 7) << SIM_SOPT6_PCR_SHIFT) +# endif +# if defined(KINETIS_SIM_HAS_SOPT6_RSTFLTSEL) +# define SIM_SOPT6_RSTFLTSEL_SHIFT (24) /* Bits 24-28: Reset pin filter select */ +# define SIM_SOPT6_RSTFLTSEL_MASK (31 << SIM_SOPT6_RSTFLTSEL_SHIFT) +# define SIM_SOPT6_RSTFLTSEL(n) ((uint32_t)((n)-1) << SIM_SOPT6_RSTFLTSEL_SHIFT) /* n=1..32 */ +# endif +# if defined(KINETIS_SIM_HAS_SOPT6_RSTFLTEN) +# define SIM_SOPT6_RSTFLTEN_SHIFT (29) /* Bits 29-31: Reset pin filter enable */ +# define SIM_SOPT6_RSTFLTEN_MASK (7 << SIM_SOPT6_RSTFLTEN_SHIFT) +# define SIM_SOPT6_RSTFLTEN_DISABLED (0 << SIM_SOPT6_RSTFLTEN_SHIFT) /* All filtering disabled */ +# define SIM_SOPT6_RSTFLTEN_BUSCLK1 (1 << SIM_SOPT6_RSTFLTEN_SHIFT) /* Bus clock filter enabled (normal); LPO clock filter enabled (stop) */ +# define SIM_SOPT6_RSTFLTEN_LPO1 (2 << SIM_SOPT6_RSTFLTEN_SHIFT) /* LPO clock filter enabled */ +# define SIM_SOPT6_RSTFLTEN_BUSCLK2 (3 << SIM_SOPT6_RSTFLTEN_SHIFT) /* Bus clock filter enabled (normal); All filtering disabled (stop) */ +# define SIM_SOPT6_RSTFLTEN_LPO2 (4 << SIM_SOPT6_RSTFLTEN_SHIFT) /* PO clock filter enabled (normal); All filtering disabled (stop) */ +# endif +#endif /* System Options Register 7 */ -#define SIM_SOPT7_ADC0TRGSEL_SHIFT (0) /* Bits 0-3: ADC0 trigger select */ -#define SIM_SOPT7_ADC0TRGSEL_MASK (15 << SIM_SOPT7_ADC0TRGSEL_SHIFT) -# define SIM_SOPT7_ADC0TRGSEL_PDB (0 << SIM_SOPT7_ADC0TRGSEL_SHIFT) /* PDB external trigger (PDB0_EXTRG) */ -# define SIM_SOPT7_ADC0TRGSEL_CMP0 (1 << SIM_SOPT7_ADC0TRGSEL_SHIFT) /* High speed comparator 0 output */ -# define SIM_SOPT7_ADC0TRGSEL_CMP1 (2 << SIM_SOPT7_ADC0TRGSEL_SHIFT) /* High speed comparator 1 output */ -# define SIM_SOPT7_ADC0TRGSEL_CMP2 (3 << SIM_SOPT7_ADC0TRGSEL_SHIFT) /* High speed comparator 2 output */ -# define SIM_SOPT7_ADC0TRGSEL_PIT0 (4 << SIM_SOPT7_ADC0TRGSEL_SHIFT) /* PIT trigger 0 */ -# define SIM_SOPT7_ADC0TRGSEL_PIT1 (5 << SIM_SOPT7_ADC0TRGSEL_SHIFT) /* PIT trigger 1 */ -# define SIM_SOPT7_ADC0TRGSEL_PIT2 (6 << SIM_SOPT7_ADC0TRGSEL_SHIFT) /* PIT trigger 2 */ -# define SIM_SOPT7_ADC0TRGSEL_PIT3 (7 << SIM_SOPT7_ADC0TRGSEL_SHIFT) /* PIT trigger 3 */ -# define SIM_SOPT7_ADC0TRGSEL_FTM0 (8 << SIM_SOPT7_ADC0TRGSEL_SHIFT) /* FTM0 trigger */ -# define SIM_SOPT7_ADC0TRGSEL_FTM1 (9 << SIM_SOPT7_ADC0TRGSEL_SHIFT) /* FTM1 trigger */ -# define SIM_SOPT7_ADC0TRGSEL_FTM2 (10 << SIM_SOPT7_ADC0TRGSEL_SHIFT) /* FTM2 trigger */ -#if defined(CONFIG_KINETIS_FTM3) -# define SIM_SOPT7_ADC0TRGSEL_FTM3 (11 << SIM_SOPT7_ADC0TRGSEL_SHIFT) /* FTM3 trigger */ +#if defined(KINETIS_SIM_HAS_SOPT7_ADC0TRGSEL) +# define SIM_SOPT7_ADC0TRGSEL_SHIFT (0) /* Bits 0-3: ADC0 trigger select */ +# define SIM_SOPT7_ADC0TRGSEL_MASK (15 << SIM_SOPT7_ADC0TRGSEL_SHIFT) +# define SIM_SOPT7_ADC0TRGSEL_PDB (0 << SIM_SOPT7_ADC0TRGSEL_SHIFT) /* PDB external trigger (PDB0_EXTRG) */ +# define SIM_SOPT7_ADC0TRGSEL_CMP0 (1 << SIM_SOPT7_ADC0TRGSEL_SHIFT) /* High speed comparator 0 output */ +# define SIM_SOPT7_ADC0TRGSEL_CMP1 (2 << SIM_SOPT7_ADC0TRGSEL_SHIFT) /* High speed comparator 1 output */ +# define SIM_SOPT7_ADC0TRGSEL_CMP2 (3 << SIM_SOPT7_ADC0TRGSEL_SHIFT) /* High speed comparator 2 output */ +# define SIM_SOPT7_ADC0TRGSEL_PIT0 (4 << SIM_SOPT7_ADC0TRGSEL_SHIFT) /* PIT trigger 0 */ +# define SIM_SOPT7_ADC0TRGSEL_PIT1 (5 << SIM_SOPT7_ADC0TRGSEL_SHIFT) /* PIT trigger 1 */ +# define SIM_SOPT7_ADC0TRGSEL_PIT2 (6 << SIM_SOPT7_ADC0TRGSEL_SHIFT) /* PIT trigger 2 */ +# define SIM_SOPT7_ADC0TRGSEL_PIT3 (7 << SIM_SOPT7_ADC0TRGSEL_SHIFT) /* PIT trigger 3 */ +# define SIM_SOPT7_ADC0TRGSEL_FTM0 (8 << SIM_SOPT7_ADC0TRGSEL_SHIFT) /* FTM0 trigger */ +# define SIM_SOPT7_ADC0TRGSEL_FTM1 (9 << SIM_SOPT7_ADC0TRGSEL_SHIFT) /* FTM1 trigger */ +# define SIM_SOPT7_ADC0TRGSEL_FTM2 (10 << SIM_SOPT7_ADC0TRGSEL_SHIFT) /* FTM2 trigger */ +# if KINETIS_SIM_HAS_SOPT7_ADC0TRGSEL > 10 && defined(KINETIS_SIM_HAS_SOPT4_FTM3CH0SRC) +# define SIM_SOPT7_ADC0TRGSEL_FTM3 (11 << SIM_SOPT7_ADC0TRGSEL_SHIFT) /* FTM3 trigger */ +# endif +# if KINETIS_SIM_HAS_SOPT7_ADC0TRGSEL > 11 +# define SIM_SOPT7_ADC0TRGSEL_ALARM (12 << SIM_SOPT7_ADC0TRGSEL_SHIFT) /* RTC alarm */ +# endif +# if KINETIS_SIM_HAS_SOPT7_ADC0TRGSEL > 12 +# define SIM_SOPT7_ADC0TRGSEL_SECS (13 << SIM_SOPT7_ADC0TRGSEL_SHIFT) /* RTC seconds */ +# endif +# if KINETIS_SIM_HAS_SOPT7_ADC0TRGSEL > 13 +# define SIM_SOPT7_ADC0TRGSEL_LPTMR (14 << SIM_SOPT7_ADC0TRGSEL_SHIFT) /* Low-power timer trigger */ +# endif +# if KINETIS_SIM_HAS_SOPT7_ADC0TRGSEL > 14 +# define SIM_SOPT7_ADC0TRGSEL_TPM1CH0 (15 << SIM_SOPT7_ADC0TRGSEL_SHIFT) /* TPM1 channel 0 (A pretrigger) and channel 1 (B pretrigger) */ +# endif #endif -# define SIM_SOPT7_ADC0TRGSEL_ALARM (12 << SIM_SOPT7_ADC0TRGSEL_SHIFT) /* RTC alarm */ -# define SIM_SOPT7_ADC0TRGSEL_SECS (13 << SIM_SOPT7_ADC0TRGSEL_SHIFT) /* RTC seconds */ -# define SIM_SOPT7_ADC0TRGSEL_LPTMR (14 << SIM_SOPT7_ADC0TRGSEL_SHIFT) /* Low-power timer trigger */ -#define SIM_SOPT7_ADC0PRETRGSEL (1 << 4) /* Bit 4: ADC0 pretrigger select */ - /* Bits 5-6: Reserved */ -#define SIM_SOPT7_ADC0ALTTRGEN (1 << 7) /* Bit 7: ADC0 alternate trigger enable */ -#define SIM_SOPT7_ADC1TRGSEL_SHIFT (8) /* Bits 8-11: ADC1 trigger select */ -#define SIM_SOPT7_ADC1TRGSEL_MASK (15 << SIM_SOPT7_ADC1TRGSEL_SHIFT) -# define SIM_SOPT7_ADC1TRGSEL_PDB (0 << SIM_SOPT7_ADC1TRGSEL_SHIFT) /* PDB external trigger (PDB0_EXTRG) */ -# define SIM_SOPT7_ADC1TRGSEL_CMP0 (1 << SIM_SOPT7_ADC1TRGSEL_SHIFT) /* High speed comparator 0 output */ -# define SIM_SOPT7_ADC1TRGSEL_CMP1 (2 << SIM_SOPT7_ADC1TRGSEL_SHIFT) /* High speed comparator 1 output */ -# define SIM_SOPT7_ADC1TRGSEL_CMP2 (3 << SIM_SOPT7_ADC1TRGSEL_SHIFT) /* High speed comparator 2 output */ -# define SIM_SOPT7_ADC1TRGSEL_PIT0 (4 << SIM_SOPT7_ADC1TRGSEL_SHIFT) /* PIT trigger 0 */ -# define SIM_SOPT7_ADC1TRGSEL_PIT1 (5 << SIM_SOPT7_ADC1TRGSEL_SHIFT) /* PIT trigger 1 */ -# define SIM_SOPT7_ADC1TRGSEL_PIT2 (6 << SIM_SOPT7_ADC1TRGSEL_SHIFT) /* PIT trigger 2 */ -# define SIM_SOPT7_ADC1TRGSEL_PIT3 (7 << SIM_SOPT7_ADC1TRGSEL_SHIFT) /* PIT trigger 3 */ -# define SIM_SOPT7_ADC1TRGSEL_FTM0 (8 << SIM_SOPT7_ADC1TRGSEL_SHIFT) /* FTM0 trigger */ -# define SIM_SOPT7_ADC1TRGSEL_FTM1 (9 << SIM_SOPT7_ADC1TRGSEL_SHIFT) /* FTM1 trigger */ -# define SIM_SOPT7_ADC1TRGSEL_FTM2 (10 << SIM_SOPT7_ADC1TRGSEL_SHIFT) /* FTM2 trigger */ -# define SIM_SOPT7_ADC1TRGSEL_ALARM (12 << SIM_SOPT7_ADC1TRGSEL_SHIFT) /* RTC alarm */ -#if defined(CONFIG_KINETIS_FTM3) -# define SIM_SOPT7_ADC1TRGSEL_FTM3 (11 << SIM_SOPT7_ADC1TRGSEL_SHIFT) /* FTM3 trigger */ +#if defined(KINETIS_SIM_HAS_SOPT7_ADC0PRETRGSEL) +# define SIM_SOPT7_ADC0PRETRGSEL (1 << 4) /* Bit 4: ADC0 pretrigger select */ #endif -# define SIM_SOPT7_ADC1TRGSEL_SECS (13 << SIM_SOPT7_ADC1TRGSEL_SHIFT) /* RTC seconds */ -# define SIM_SOPT7_ADC1TRGSEL_LPTMR (14 << SIM_SOPT7_ADC1TRGSEL_SHIFT) /* Low-power timer trigger */ -#define SIM_SOPT7_ADC1PRETRGSEL (1 << 12) /* Bit 12: ADC1 pre-trigger select */ - /* Bits 13-14: Reserved */ -#define SIM_SOPT7_ADC1ALTTRGEN (1 << 15) /* Bit 15: ADC1 alternate trigger enable */ - /* Bits 16-31: Reserved */ + /* Bits 5-6: Reserved */ +#if defined(KINETIS_SIM_SOPT7_ADC0ALTTRGEN) +# define SIM_SOPT7_ADC0ALTTRGEN (1 << 7) /* Bit 7: ADC0 alternate trigger enable */ +#endif + +#if defined(KINETIS_SIM_HAS_SOPT7_ADC1TRGSEL) +# define SIM_SOPT7_ADC1TRGSEL_SHIFT (8) /* Bits 8-11: ADC1 trigger select */ +# define SIM_SOPT7_ADC1TRGSEL_MASK (15 << SIM_SOPT7_ADC1TRGSEL_SHIFT) +# define SIM_SOPT7_ADC1TRGSEL_PDB (0 << SIM_SOPT7_ADC1TRGSEL_SHIFT) /* PDB external trigger (PDB0_EXTRG) */ +# define SIM_SOPT7_ADC1TRGSEL_CMP0 (1 << SIM_SOPT7_ADC1TRGSEL_SHIFT) /* High speed comparator 0 output */ +# define SIM_SOPT7_ADC1TRGSEL_CMP1 (2 << SIM_SOPT7_ADC1TRGSEL_SHIFT) /* High speed comparator 1 output */ +# define SIM_SOPT7_ADC1TRGSEL_CMP2 (3 << SIM_SOPT7_ADC1TRGSEL_SHIFT) /* High speed comparator 2 output */ +# define SIM_SOPT7_ADC1TRGSEL_PIT0 (4 << SIM_SOPT7_ADC1TRGSEL_SHIFT) /* PIT trigger 0 */ +# define SIM_SOPT7_ADC1TRGSEL_PIT1 (5 << SIM_SOPT7_ADC1TRGSEL_SHIFT) /* PIT trigger 1 */ +# define SIM_SOPT7_ADC1TRGSEL_PIT2 (6 << SIM_SOPT7_ADC1TRGSEL_SHIFT) /* PIT trigger 2 */ +# define SIM_SOPT7_ADC1TRGSEL_PIT3 (7 << SIM_SOPT7_ADC1TRGSEL_SHIFT) /* PIT trigger 3 */ +# define SIM_SOPT7_ADC1TRGSEL_FTM0 (8 << SIM_SOPT7_ADC1TRGSEL_SHIFT) /* FTM0 trigger */ +# define SIM_SOPT7_ADC1TRGSEL_FTM1 (9 << SIM_SOPT7_ADC1TRGSEL_SHIFT) /* FTM1 trigger */ +# define SIM_SOPT7_ADC1TRGSEL_FTM2 (10 << SIM_SOPT7_ADC1TRGSEL_SHIFT) /* FTM2 trigger */ +# define SIM_SOPT7_ADC1TRGSEL_ALARM (12 << SIM_SOPT7_ADC1TRGSEL_SHIFT) /* RTC alarm */ +# if KINETIS_SIM_HAS_SOPT7_ADC1TRGSEL > 10 && defined(KINETIS_SIM_HAS_SOPT4_FTM3CH0SRC) +# define SIM_SOPT7_ADC1TRGSEL_FTM3 (11 << SIM_SOPT7_ADC1TRGSEL_SHIFT) /* FTM3 trigger */ +# endif +# if KINETIS_SIM_HAS_SOPT7_ADC1TRGSEL > 11 +# define SIM_SOPT7_ADC1TRGSEL_ALARM (12 << SIM_SOPT7_ADC1TRGSEL_SHIFT) /* RTC alarm */ +# endif +# if KINETIS_SIM_HAS_SOPT7_ADC1TRGSEL > 12 +# define SIM_SOPT7_ADC1TRGSEL_SECS (13 << SIM_SOPT7_ADC1TRGSEL_SHIFT) /* RTC seconds */ +# endif +# if KINETIS_SIM_HAS_SOPT7_ADC1TRGSEL > 13 +# define SIM_SOPT7_ADC1TRGSEL_LPTMR (14 << SIM_SOPT7_ADC1TRGSEL_SHIFT) /* Low-power timer trigger */ +# endif +# if KINETIS_SIM_HAS_SOPT7_ADC1TRGSEL > 14 +# define SIM_SOPT7_ADC1TRGSEL_TPM2CH0 (15 << SIM_SOPT7_ADC1TRGSEL_SHIFT) /* TPM2 channel 0 (A pretrigger) and channel 1 (B pretrigger) */ +# endif +#endif +#if defined(KINETIS_SIM_HAS_SOPT7_ADC1PRETRGSEL) +# define SIM_SOPT7_ADC1PRETRGSEL (1 << 12) /* Bit 12: ADC1 pre-trigger select */ +#endif + /* Bits 13-14: Reserved */ +#if defined(KINETIS_SIM_SOPT7_ADC1ALTTRGEN) +# define SIM_SOPT7_ADC1ALTTRGEN (1 << 15) /* Bit 15: ADC1 alternate trigger enable */ +#endif + /* Bits 16-31: Reserved */ +#if defined(KINETIS_SIM_HAS_SOPT7_ADC2TRGSEL) +# define SIM_SOPT7_ADC2TRGSEL_SHIFT (16) /* Bits 16-19: ADC2 trigger select */ +# define SIM_SOPT7_ADC2TRGSEL_MASK (15 << SIM_SOPT7_ADC2TRGSEL_SHIFT) +# define SIM_SOPT7_ADC2TRGSEL_PDB (0 << SIM_SOPT7_ADC2TRGSEL_SHIFT) /* PDB external trigger (PDB0_EXTRG) */ +# define SIM_SOPT7_ADC2TRGSEL_CMP0 (1 << SIM_SOPT7_ADC2TRGSEL_SHIFT) /* High speed comparator 0 output */ +# define SIM_SOPT7_ADC2TRGSEL_CMP1 (2 << SIM_SOPT7_ADC2TRGSEL_SHIFT) /* High speed comparator 1 output */ +# define SIM_SOPT7_ADC2TRGSEL_CMP2 (3 << SIM_SOPT7_ADC2TRGSEL_SHIFT) /* High speed comparator 2 output */ +# define SIM_SOPT7_ADC2TRGSEL_PIT0 (4 << SIM_SOPT7_ADC2TRGSEL_SHIFT) /* PIT trigger 0 */ +# define SIM_SOPT7_ADC2TRGSEL_PIT1 (5 << SIM_SOPT7_ADC2TRGSEL_SHIFT) /* PIT trigger 1 */ +# define SIM_SOPT7_ADC2TRGSEL_PIT2 (6 << SIM_SOPT7_ADC2TRGSEL_SHIFT) /* PIT trigger 2 */ +# define SIM_SOPT7_ADC2TRGSEL_PIT3 (7 << SIM_SOPT7_ADC2TRGSEL_SHIFT) /* PIT trigger 3 */ +# define SIM_SOPT7_ADC2TRGSEL_FTM0 (8 << SIM_SOPT7_ADC2TRGSEL_SHIFT) /* FTM0 trigger */ +# define SIM_SOPT7_ADC2TRGSEL_FTM1 (9 << SIM_SOPT7_ADC2TRGSEL_SHIFT) /* FTM1 trigger */ +# define SIM_SOPT7_ADC2TRGSEL_FTM2 (10 << SIM_SOPT7_ADC2TRGSEL_SHIFT) /* FTM2 trigger */ +# if KINETIS_SIM_HAS_SOPT7_ADC2TRGSEL > 10 && defined(KINETIS_SIM_HAS_SOPT4_FTM3CH0SRC) +# define SIM_SOPT7_ADC2TRGSEL_FTM3 (11 << SIM_SOPT7_ADC2TRGSEL_SHIFT) /* FTM3 trigger */ +# endif +# if KINETIS_SIM_HAS_SOPT7_ADC2TRGSEL > 11 +# define SIM_SOPT7_ADC2TRGSEL_ALARM (12 << SIM_SOPT7_ADC2TRGSEL_SHIFT) /* RTC alarm */ +# endif +# if KINETIS_SIM_HAS_SOPT7_ADC2TRGSEL > 12 +# define SIM_SOPT7_ADC2TRGSEL_SECS (13 << SIM_SOPT7_ADC2TRGSEL_SHIFT) /* RTC seconds */ +# endif +# if KINETIS_SIM_HAS_SOPT7_ADC2TRGSEL > 13 +# define SIM_SOPT7_ADC2TRGSEL_LPTMR (14 << SIM_SOPT7_ADC2TRGSEL_SHIFT) /* Low-power timer trigger */ +# endif +# if KINETIS_SIM_HAS_SOPT7_ADC2TRGSEL > 14 +# define SIM_SOPT7_ADC2TRGSEL_CMP3 (15 << SIM_SOPT7_ADC2TRGSEL_SHIFT) /* High speed comparator 3 asynchronous interrupt */ +# endif +#endif +#if defined(KINETIS_SIM_HAS_SOPT7_ADC2PRETRGSEL) +# define SIM_SOPT7_ADC2PRETRGSEL (1 << 20) /* Bit 20: ADC2 pretrigger select */ +#endif + /* Bits 21-22: Reserved */ +#if defined(KINETIS_SIM_SOPT7_ADC2ALTTRGEN) +# define SIM_SOPT7_ADC2ALTTRGEN (1 << 23) /* Bit 23: ADC2 alternate trigger enable */ +#endif + /* Bits 23-27: Reserved */ +#if defined(KINETIS_SIM_HAS_SOPT7_ADC3TRGSEL) +# define SIM_SOPT7_ADC3TRGSEL_SHIFT (24) /* Bits 24-27: ADC3 trigger select */ +# define SIM_SOPT7_ADC3TRGSEL_MASK (15 << SIM_SOPT7_ADC3TRGSEL_SHIFT) +# define SIM_SOPT7_ADC3TRGSEL_PDB (0 << SIM_SOPT7_ADC3TRGSEL_SHIFT) /* PDB external trigger (PDB0_EXTRG) */ +# define SIM_SOPT7_ADC3TRGSEL_CMP0 (1 << SIM_SOPT7_ADC3TRGSEL_SHIFT) /* High speed comparator 0 output */ +# define SIM_SOPT7_ADC3TRGSEL_CMP1 (2 << SIM_SOPT7_ADC3TRGSEL_SHIFT) /* High speed comparator 1 output */ +# define SIM_SOPT7_ADC3TRGSEL_CMP2 (3 << SIM_SOPT7_ADC3TRGSEL_SHIFT) /* High speed comparator 2 output */ +# define SIM_SOPT7_ADC3TRGSEL_PIT0 (4 << SIM_SOPT7_ADC3TRGSEL_SHIFT) /* PIT trigger 0 */ +# define SIM_SOPT7_ADC3TRGSEL_PIT1 (5 << SIM_SOPT7_ADC3TRGSEL_SHIFT) /* PIT trigger 1 */ +# define SIM_SOPT7_ADC3TRGSEL_PIT2 (6 << SIM_SOPT7_ADC3TRGSEL_SHIFT) /* PIT trigger 2 */ +# define SIM_SOPT7_ADC3TRGSEL_PIT3 (7 << SIM_SOPT7_ADC3TRGSEL_SHIFT) /* PIT trigger 3 */ +# define SIM_SOPT7_ADC3TRGSEL_FTM0 (8 << SIM_SOPT7_ADC3TRGSEL_SHIFT) /* FTM0 trigger */ +# define SIM_SOPT7_ADC3TRGSEL_FTM1 (9 << SIM_SOPT7_ADC3TRGSEL_SHIFT) /* FTM1 trigger */ +# define SIM_SOPT7_ADC3TRGSEL_FTM2 (10 << SIM_SOPT7_ADC3TRGSEL_SHIFT) /* FTM2 trigger */ +# if KINETIS_SIM_HAS_SOPT7_ADC3TRGSEL > 10 && defined(KINETIS_SIM_HAS_SOPT4_FTM3CH0SRC) +# define SIM_SOPT7_ADC3TRGSEL_FTM3 (11 << SIM_SOPT7_ADC3TRGSEL_SHIFT) /* FTM3 trigger */ +# endif +# if KINETIS_SIM_HAS_SOPT7_ADC3TRGSEL > 11 +# define SIM_SOPT7_ADC3TRGSEL_ALARM (12 << SIM_SOPT7_ADC3TRGSEL_SHIFT) /* RTC alarm */ +# endif +# if KINETIS_SIM_HAS_SOPT7_ADC3TRGSEL > 12 +# define SIM_SOPT7_ADC3TRGSEL_SECS (13 << SIM_SOPT7_ADC3TRGSEL_SHIFT) /* RTC seconds */ +# endif +# if KINETIS_SIM_HAS_SOPT7_ADC3TRGSEL > 13 +# define SIM_SOPT7_ADC3TRGSEL_LPTMR (14 << SIM_SOPT7_ADC3TRGSEL_SHIFT) /* Low-power timer trigger */ +# endif +# if KINETIS_SIM_HAS_SOPT7_ADC3TRGSEL > 14 +# define SIM_SOPT7_ADC3TRGSEL_CMP3 (15 << SIM_SOPT7_ADC3TRGSEL_SHIFT) /* High speed comparator 3 asynchronous interrupt */ +# endif +#endif +#if defined(KINETIS_SIM_HAS_SOPT7_ADC3PRETRGSEL) +# define SIM_SOPT7_ADC3PRETRGSEL (1 << 28) /* Bit 28: ADC3 pretrigger select */ +#endif + /* Bits 29-30: Reserved */ +#if defined(KINETIS_SIM_SOPT7_ADC3ALTTRGEN) +# define SIM_SOPT7_ADC3ALTTRGEN (1 << 31) /* Bit 31: ADC3 alternate trigger enable */ +#endif + +#if defined(KINETIS_SIM_HAS_SOPT8) +/* System Options Register 8 */ + +# if defined(KINETIS_SIM_HAS_SOPT8_FTM0SYNCBIT) +# define SIM_SOPT8_FTM0SYNCBIT (1 << 0) /* Bit 0: FTM0 Hardware Trigger 0 Software Synchronization */ +# endif +# if defined(KINETIS_SIM_HAS_SOPT8_FTM1SYNCBIT) +# define SIM_SOPT8_FTM1SYNCBIT (1 << 1) /* Bit 1: FTM1 Hardware Trigger 0 Software Synchronization */ +# endif +# if defined(KINETIS_SIM_HAS_SOPT8_FTM2SYNCBIT) +# define SIM_SOPT8_FTM2SYNCBIT (1 << 2) /* Bit 2: FTM2 Hardware Trigger 0 Software Synchronization */ +# endif +# if defined(KINETIS_SIM_HAS_SOPT8_FTM3SYNCBIT) +# define SIM_SOPT8_FTM3SYNCBIT (1 << 3) /* Bit 3: FTM3 Hardware Trigger 0 Software Synchronization */ +# endif + /* Bits 4-15: Reserved */ +# if defined(KINETIS_SIM_HAS_SOPT8_FTM0OCH0SRC) +# define SIM_SOPT8_FTM0OCH0SRC (1 << 16) /* Bit 16: FTM0 channel 0 output source */ +# endif +# if defined(KINETIS_SIM_HAS_SOPT8_FTM0OCH1SRC) +# define SIM_SOPT8_FTM0OCH1SRC (1 << 17) /* Bit 17: FTM0 channel 1 output source */ +# endif +# if defined(KINETIS_SIM_HAS_SOPT8_FTM0OCH2SRC) +# define SIM_SOPT8_FTM0OCH2SRC (1 << 18) /* Bit 18: FTM0 channel 2 output source */ +# endif +# if defined(KINETIS_SIM_HAS_SOPT8_FTM0OCH3SRC) +# define SIM_SOPT8_FTM0OCH3SRC (1 << 19) /* Bit 19: FTM0 channel 3 output source */ +# endif +# if defined(KINETIS_SIM_HAS_SOPT8_FTM0OCH4SRC) +# define SIM_SOPT8_FTM0OCH4SRC (1 << 20) /* Bit 20: FTM0 channel 4 output source */ +# endif +# if defined(KINETIS_SIM_HAS_SOPT8_FTM0OCH5SRC) +# define SIM_SOPT8_FTM0OCH5SRC (1 << 21) /* Bit 21: FTM0 channel 5 output source */ +# endif +# if defined(KINETIS_SIM_HAS_SOPT8_FTM0OCH6SRC) +# define SIM_SOPT8_FTM0OCH6SRC (1 << 22) /* Bit 22: FTM0 channel 6 output source */ +# endif +# if defined(KINETIS_SIM_HAS_SOPT8_FTM0OCH7SRC) +# define SIM_SOPT8_FTM0OCH7SRC (1 << 23) /* Bit 23: FTM0 channel 7 output source */ +# endif +# if defined(KINETIS_SIM_HAS_SOPT8_FTM3OCH0SRC) +# define SIM_SOPT8_FTM3OCH0SRC (1 << 24) /* Bit 24: FTM3 channel 0 output source */ +# endif +# if defined(KINETIS_SIM_HAS_SOPT8_FTM3OCH1SRC) +# define SIM_SOPT8_FTM3OCH1SRC (1 << 25) /* Bit 25: FTM3 channel 1 output source */ +# endif +# if defined(KINETIS_SIM_HAS_SOPT8_FTM3OCH2SRC) +# define SIM_SOPT8_FTM3OCH2SRC (1 << 26) /* Bit 26: FTM3 channel 2 output source */ +# endif +# if defined(KINETIS_SIM_HAS_SOPT8_FTM3OCH3SRC) +# define SIM_SOPT8_FTM3OCH3SRC (1 << 27) /* Bit 27: FTM3 channel 3 output source */ +# endif +# if defined(KINETIS_SIM_HAS_SOPT8_FTM3OCH4SRC) +# define SIM_SOPT8_FTM3OCH4SRC (1 << 28) /* Bit 28: FTM3 channel 4 output source */ +# endif +# if defined(KINETIS_SIM_HAS_SOPT8_FTM3OCH5SRC) +# define SIM_SOPT8_FTM3OCH5SRC (1 << 29) /* Bit 29: FTM3 channel 5 output source */ +# endif +# if defined(KINETIS_SIM_HAS_SOPT8_FTM3OCH6SRC) +# define SIM_SOPT8_FTM3OCH6SRC (1 << 30) /* Bit 30: FTM3 channel 6 output source */ +# endif +# if defined(KINETIS_SIM_HAS_SOPT8_FTM3OCH7SRC) +# define SIM_SOPT8_FTM3OCH7SRC (1 << 31) /* Bit 31: FTM3 channel 7 output source */ +# endif +#endif + +#if defined(KINETIS_SIM_HAS_SOPT9) +/* System Options Register 9 */ + + /* Bits 0-17: Reserved */ +# if defined(KINETIS_SIM_HAS_SOPT9_TPM1CH0SRC) +# define SIM_SOPT9_TPM1CH0SRC_SHIFT (18) /* Bits 18-19: TPM1 channel 0 input capture source select */ +# define SIM_SOPT9_TPM1CH0SRC_MASK (3 << SIM_SOPT9_TPM1CH0SRC_SHIFT) +# define SIM_SOPT9_TPM1CH0SRC_TMP1CH0 (0 << SIM_SOPT9_TPM1CH0SRC_SHIFT) +# define SIM_SOPT9_TPM1CH0SRC_CMP0 (1 << SIM_SOPT9_TPM1CH0SRC_SHIFT) +# define SIM_SOPT9_TPM1CH0SRC_CMP1 (2 << SIM_SOPT9_TPM1CH0SRC_SHIFT) +# endif +# if defined(KINETIS_SIM_HAS_SOPT9_TPM2CH0SRC) +# define SIM_SOPT9_TPM2CH0SRC_SHIFT (20) /* Bits 20-21 TPM2 channel 0 input capture source select */ +# define SIM_SOPT9_TPM2CH0SRC_MASK (3 << SIM_SOPT9_TPM2CH0SRC_SHIFT) +# define SIM_SOPT9_TPM2CH0SRC_TMP1CH0 (0 << SIM_SOPT9_TPM2CH0SRC_SHIFT) +# define SIM_SOPT9_TPM2CH0SRC_CMP0 (1 << SIM_SOPT9_TPM2CH0SRC_SHIFT) +# define SIM_SOPT9_TPM2CH0SRC_CMP1 (2 << SIM_SOPT9_TPM2CH0SRC_SHIFT) +# endif + /* Bits 22-24: Reserved */ +# if defined(KINETIS_SIM_HAS_SOPT9_TPM1CLKSEL) +# define SIM_SOPT9_TPM1CLKSEL (1 << 25) /* Bit 25: TPM1 External Clock Pin Select */ +# endif +# if defined(KINETIS_SIM_HAS_SOPT9_TPM2CLKSEL) +# define SIM_SOPT9_TPM2CLKSEL (1 << 26) /* Bit 26: TPM2 External Clock Pin Select */ +# endif + /* Bits 27-31: Reserved */ +#endif + /* System Device Identification Register */ -#define SIM_SDID_PINID_SHIFT (0) /* Bits 0-3: Pincount identification */ -#define SIM_SDID_PINID_MASK (15 << SIM_SDID_PINID_SHIFT) -# define SIM_SDID_PINID_32PIN (2 << SIM_SDID_PINID_SHIFT) /* 32-pin */ -# define SIM_SDID_PINID_48PIN (4 << SIM_SDID_PINID_SHIFT) /* 48-pin */ -# define SIM_SDID_PINID_64PIN (5 << SIM_SDID_PINID_SHIFT) /* 64-pin */ -# define SIM_SDID_PINID_80PIN (6 << SIM_SDID_PINID_SHIFT) /* 80-pin */ -# define SIM_SDID_PINID_81PIN (7 << SIM_SDID_PINID_SHIFT) /* 81-pin */ -# define SIM_SDID_PINID_100PIN (8 << SIM_SDID_PINID_SHIFT) /* 100-pin */ -# define SIM_SDID_PINID_121PIN (9 << SIM_SDID_PINID_SHIFT) /* 121-pin */ -# define SIM_SDID_PINID_144PIN (10 << SIM_SDID_PINID_SHIFT) /* 144-pin */ -# define SIM_SDID_PINID_196PIN (12 << SIM_SDID_PINID_SHIFT) /* 196-pin */ -# define SIM_SDID_PINID_256PIN (14 << SIM_SDID_PINID_SHIFT) /* 256-pin */ -#define SIM_SDID_FAMID_SHIFT (4) /* Bits 4-6: Kinetis family identification */ -#define SIM_SDID_FAMID_MASK (7 << SIM_SDID_FAMID_SHIFT) -# define SIM_SDID_FAMID_K10 (0 << SIM_SDID_FAMID_SHIFT) /* K10 */ -# define SIM_SDID_FAMID_K20 (1 << SIM_SDID_FAMID_SHIFT)) /* K20 */ -# define SIM_SDID_FAMID_K30 (2 << SIM_SDID_FAMID_SHIFT)) /* K30 */ -# define SIM_SDID_FAMID_K40 (3 << SIM_SDID_FAMID_SHIFT)) /* K40 */ -# define SIM_SDID_FAMID_K60 (4 << SIM_SDID_FAMID_SHIFT)) /* K60 */ -# define SIM_SDID_FAMID_K70 (5 << SIM_SDID_FAMID_SHIFT)) /* K70 */ -# define SIM_SDID_FAMID_K50 (6 << SIM_SDID_FAMID_SHIFT)) /* K50 and K52 */ -# define SIM_SDID_FAMID_K51 (7 << SIM_SDID_FAMID_SHIFT)) /* K51 and K53 */ - /* Bits 7-11: Reserved */ -#define SIM_SDID_REVID_SHIFT (12) /* Bits 12-15: Device revision number */ -#define SIM_SDID_REVID_MASK (15 << SIM_SDID_REVID_SHIFT) - /* Bits 16-31: Reserved */ +#define SIM_SDID_PINID_SHIFT (0) /* Bits 0-3: Pincount identification */ +#define SIM_SDID_PINID_MASK (15 << SIM_SDID_PINID_SHIFT) +# define SIM_SDID_PINID_32PIN (2 << SIM_SDID_PINID_SHIFT) /* 32-pin */ +# define SIM_SDID_PINID_48PIN (4 << SIM_SDID_PINID_SHIFT) /* 48-pin */ +# define SIM_SDID_PINID_64PIN (5 << SIM_SDID_PINID_SHIFT) /* 64-pin */ +# define SIM_SDID_PINID_80PIN (6 << SIM_SDID_PINID_SHIFT) /* 80-pin */ +# define SIM_SDID_PINID_81PIN (7 << SIM_SDID_PINID_SHIFT) /* 81-pin */ +# define SIM_SDID_PINID_100PIN (8 << SIM_SDID_PINID_SHIFT) /* 100-pin */ +# define SIM_SDID_PINID_121PIN (9 << SIM_SDID_PINID_SHIFT) /* 121-pin */ +# define SIM_SDID_PINID_144PIN (10 << SIM_SDID_PINID_SHIFT) /* 144-pin */ +# define SIM_SDID_PINID_196PIN (12 << SIM_SDID_PINID_SHIFT) /* 196-pin */ +# define SIM_SDID_PINID_256PIN (14 << SIM_SDID_PINID_SHIFT) /* 256-pin */ +#if defined(KINETIS_SIM_HAS_SDID_FAMID) +# if !defined(KINETIS_SIM_HAS_SDID_FAMILYID) +# define SIM_SDID_FAMID_SHIFT (4) /* Bits 4-6: Kinetis family identification */ +# define SIM_SDID_FAMID_MASK (7 << SIM_SDID_FAMID_SHIFT) +# define SIM_SDID_FAMID_K10 (0 << SIM_SDID_FAMID_SHIFT) /* K10 */ +# define SIM_SDID_FAMID_K20 (1 << SIM_SDID_FAMID_SHIFT)) /* K20 */ +# define SIM_SDID_FAMID_K30 (2 << SIM_SDID_FAMID_SHIFT)) /* K30 */ +# define SIM_SDID_FAMID_K40 (3 << SIM_SDID_FAMID_SHIFT)) /* K40 */ +# define SIM_SDID_FAMID_K60 (4 << SIM_SDID_FAMID_SHIFT)) /* K60 */ +# define SIM_SDID_FAMID_K70 (5 << SIM_SDID_FAMID_SHIFT)) /* K70 */ +# define SIM_SDID_FAMID_K50 (6 << SIM_SDID_FAMID_SHIFT)) /* K50 and K52 */ +# define SIM_SDID_FAMID_K51 (7 << SIM_SDID_FAMID_SHIFT)) /* K51 and K53 */ +# else +# define SIM_SDID_FAMID_K1X (0 << SIM_SDID_FAMID_SHIFT) /* K1X */ +# define SIM_SDID_FAMID_K2X (1 << SIM_SDID_FAMID_SHIFT)) /* K2X */ +# define SIM_SDID_FAMID_K3X (2 << SIM_SDID_FAMID_SHIFT)) /* K3X */ +# define SIM_SDID_FAMID_K4X (3 << SIM_SDID_FAMID_SHIFT)) /* K4X */ +# define SIM_SDID_FAMID_K6X (4 << SIM_SDID_FAMID_SHIFT)) /* K6X */ +# define SIM_SDID_FAMID_K7X (5 << SIM_SDID_FAMID_SHIFT)) /* K7X */ +# endif +#endif + /* Bits 7-11: Reserved */ +#if defined(KINETIS_SIM_HAS_SDID_DIEID) +# define SIM_SDID_DIEID_SHIFT (7) /* Bits 7-11: Device Die ID */ +# define SIM_SDID_DIEID_MASK (31 < SIM_SDID_DIEID_SHIFT) +#endif + +#define SIM_SDID_REVID_SHIFT (12) /* Bits 12-15: Device revision number */ +#define SIM_SDID_REVID_MASK (15 << SIM_SDID_REVID_SHIFT) + /* Bits 16-31: Reserved */ +#if defined(KINETIS_SIM_HAS_SDID_SRAMSIZE) +# define SIM_SDID_SRAMSIZE_SHIFT (16) /* Bits 16-19: SRAM Size */ +# define SIM_SDID_SRAMSIZE_MASK (15 < SIM_SDID_SRAMSIZE_SHIFT) +#endif +#if defined(KINETIS_SIM_HAS_SDID_SERIESID) +# define SIM_SDID_SERIESID_SHIFT (20) /* Bits 20-23: Kinetis Series ID */ +# define SIM_SDID_SERIESID_MASK (15 << SIM_SDID_SERIESID_SHIFT) +# define SIM_SDID_SERIESID_K (0 << SIM_SDID_SERIESID_SHIFT) /* Kinetis K series */ +# define SIM_SDID_SERIESID_L (1 << SIM_SDID_SERIESID_SHIFT) /* Kinetis L series */ +# define SIM_SDID_SERIESID_W (5 << SIM_SDID_SERIESID_SHIFT) /* Kinetis W series */ +# define SIM_SDID_SERIESID_V (6 << SIM_SDID_SERIESID_SHIFT) /* Kinetis V series */ +#endif +#if defined(KINETIS_SIM_HAS_SDID_SUBFAMID) +# define SIM_SDID_SUBFAMID_SHIFT (24) /* Bits 24-27: Kinetis Sub-Family ID */ +# define SIM_SDID_SUBFAMID_MASK (15 << SIM_SDID_SUBFAMID_SHIFT) +# define SIM_SDID_SUBFAMID_KX0 (0 << SIM_SDID_SUBFAMID_SHIFT) /* Kx0 Subfamily */ +# define SIM_SDID_SUBFAMID_KX1 (1 << SIM_SDID_SUBFAMID_SHIFT) /* Kx1 Subfamily (tamper detect) */ +# define SIM_SDID_SUBFAMID_KX2 (2 << SIM_SDID_SUBFAMID_SHIFT) /* Kx2 Subfamily */ +# define SIM_SDID_SUBFAMID_KX3 (3 << SIM_SDID_SUBFAMID_SHIFT) /* Kx3 Subfamily (tamper detect) */ +# define SIM_SDID_SUBFAMID_KX4 (4 << SIM_SDID_SUBFAMID_SHIFT) /* Kx4 Subfamily */ +# define SIM_SDID_SUBFAMID_KX5 (5 << SIM_SDID_SUBFAMID_SHIFT) /* Kx5 Subfamily (tamper detect) */ +# define SIM_SDID_SUBFAMID_KX6 (6 << SIM_SDID_SUBFAMID_SHIFT) /* Kx6 Subfamily */ +#endif +#if defined(KINETIS_SIM_HAS_SDID_FAMILYID) +# define SIM_SDID_FAMILYID_SHIFT (28) /* Bits 28-31: Kinetis Family ID */ +# define SIM_SDID_FAMILYID_MASK (15 << SIM_SDID_FAMILYID_SHIFT) +# define SIM_SDID_FAMILYID_K0X (0 << SIM_SDID_FAMILYID_SHIFT) /* K0x Family */ +# define SIM_SDID_FAMILYID_K1X (1 << SIM_SDID_FAMILYID_SHIFT) /* K1x Family */ +# define SIM_SDID_FAMILYID_K2X (2 << SIM_SDID_FAMILYID_SHIFT) /* K2x Family */ +# define SIM_SDID_FAMILYID_K3X (3 << SIM_SDID_FAMILYID_SHIFT) /* K3x Family */ +# define SIM_SDID_FAMILYID_K4X (4 << SIM_SDID_FAMILYID_SHIFT) /* K4x Family */ +# define SIM_SDID_FAMILYID_K6X (6 << SIM_SDID_FAMILYID_SHIFT) /* K6x Family */ +# define SIM_SDID_FAMILYID_K7X (7 << SIM_SDID_FAMILYID_SHIFT) /* K7x Family */ +# define SIM_SDID_FAMILYID_K8X (8 << SIM_SDID_FAMILYID_SHIFT) /* K8x Family */ +#endif + + /* System Clock Gating Control Register 1 */ - /* Bits 0-9: Reserved */ -#define SIM_SCGC1_UART4 (1 << 10) /* Bit 10: UART4 Clock Gate Control */ -#define SIM_SCGC1_UART5 (1 << 11) /* Bit 11: UART5 Clock Gate Control */ - /* Bits 12-31: Reserved */ + +#if defined(KINETIS_SIM_HAS_SCGC1) + /* Bits 0-9: Reserved */ +# if defined(KINETIS_SIM_HAS_SCGC1_OSC1) + /* Bits 0-4: Reserved */ +# define SIM_SCGC1_OSC1 (1 << 5) /* OSC1 clock gate control */ +# endif + /* Bits 6-9: Reserved */ +# if defined(KINETIS_SIM_HAS_SCGC1_I2C2) +# define SIM_SCGC1_I2C2 (1 << 6) /* Bit 6: I2C2 Clock Gate Control */ +# endif + /* Bits 7-9: Reserved */ +# if defined(KINETIS_SIM_HAS_SCGC1_I2C3) +# define SIM_SCGC1_I2C3 (1 << 7) /* Bit 7: I2C3 Clock Gate Control */ +# endif +# if defined(KINETIS_SIM_HAS_SCGC1_UART4) +# define SIM_SCGC1_UART4 (1 << 10) /* Bit 10: UART4 Clock Gate Control */ +# endif +# if defined(KINETIS_SIM_HAS_SCGC1_UART5) +# define SIM_SCGC1_UART5 (1 << 11) /* Bit 11: UART5 Clock Gate Control */ +# endif + /* Bits 12-31: Reserved */ +#endif + +#if defined(KINETIS_SIM_HAS_SCGC2) /* System Clock Gating Control Register 2 */ -#if defined(KINETIS_NENET) && KINETIS_NENET > 0 -# define SIM_SCGC2_ENET (1 << 0) /* Bit 0: ENET Clock Gate Control (K60) */ +# if defined(KINETIS_SIM_HAS_SCGC2_ENET) && defined(KINETIS_NENET) && KINETIS_NENET > 0 +# define SIM_SCGC2_ENET (1 << 0) /* Bit 0: ENET Clock Gate Control */ +# endif +# if defined(KINETIS_SIM_HAS_SCGC2_LPUART0) +# define SIM_SCGC2_LPUART0 (1 << 4) /* Bit 4: LPUART0 Clock Gate Control */ +# endif +# if defined(KINETIS_SIM_HAS_SCGC2_TPM1) +# define SIM_SCGC2_TPM1 (1 << 9) /* Bit 9: TPM1 Clock Gate Control */ +# endif +# if defined(KINETIS_SIM_HAS_SCGC2_TPM2) +# define SIM_SCGC2_TPM2 (1 << 10) /* Bit 10: TPM2 Clock Gate Control */ +# endif +# define SIM_SCGC2_DAC0 (1 << 12) /* Bit 12: DAC0 Clock Gate Control */ +# define SIM_SCGC2_DAC1 (1 << 13) /* Bit 13: DAC1 Clock Gate Control */ + /* Bits 14-31: Reserved */ #endif - /* Bits 1-11: Reserved */ -#define SIM_SCGC2_DAC0 (1 << 12) /* Bit 12: DAC0 Clock Gate Control */ -#define SIM_SCGC2_DAC1 (1 << 13) /* Bit 13: DAC1 Clock Gate Control */ - /* Bits 14-31: Reserved */ + +#if defined(KINETIS_SIM_HAS_SCGC3) /* System Clock Gating Control Register 3 */ -#if defined(KINETIS_NRNG) && KINETIS_NRNG > 0 -# define SIM_SCGC3_RNGB (1 << 0) /* Bit 0: RNGB Clock Gate Control (K60) */ +# if defined(KINETIS_SIM_HAS_SCGC3_RNGA) && defined(KINETIS_NRNG) && KINETIS_NRNG > 0 +# define SIM_SCGC3_RNGA (1 << 0) /* Bit 0: RNGB Clock Gate Control */ +# endif +# if defined(KINETIS_SIM_HAS_SCGC3_USBHS) +# define SIM_SCGC3_USBHS (1 << 1) /* Bit 1: USBHS Clock Gate Control */ +# endif +# if defined(KINETIS_SIM_HAS_SCGC3_USBHSPHY) +# define SIM_SCGC3_USBHSPHY (1 << 2) /* Bit 2: USBHS PHY Clock Gate Control */ +# endif +# if defined(KINETIS_SIM_HAS_SCGC3_USBHSDCD) +# define SIM_SCGC3_USBHSDCD (1 << 3) /* Bit 3: USBHS DCD Clock Gate Control */ +# endif + /* Bits 5-11: Reserved */ +# if defined(KINETIS_SIM_HAS_SCGC3_FLEXCAN1) +# define SIM_SCGC3_FLEXCAN1 (1 << 4) /* Bit 4: FlexCAN1 Clock Gate Control */ +# endif +# if defined(KINETIS_SIM_HAS_SCGC3_NFC) +# define SIM_SCGC3_FLEXCAN1 (1 << 8) /* Bit 8: NFC Clock Gate Control */ +# endif +# if defined(KINETIS_SIM_HAS_SCGC3_SPI2) +# define SIM_SCGC3_SPI2 (1 << 12) /* Bit 12: SPI2 Clock Gate Control */ +# endif + /* Bits 13-14: Reserved */ +# if defined(KINETIS_SIM_HAS_SCGC3_SAI1) +# define SIM_SCGC3_SAI1 (1 << 15) /* Bit 15: SAI1 clock Gate control */ +# endif + /* Bit 16: Reserved */ +# if defined(KINETIS_SIM_HAS_SCGC3_SDHC) +# define SIM_SCGC3_SDHC (1 << 17) /* Bit 17: SDHC Clock Gate Control */ +# endif + /* Bits 18-23: Reserved */ +# if defined(KINETIS_SIM_HAS_SCGC3_FTM2) +# define SIM_SCGC3_FTM2 (1 << 24) /* Bit 24: FTM2 Clock Gate Control */ +# endif +# if defined(KINETIS_SIM_HAS_SCGC3_FTM3) && defined(KINETIS_SIM_HAS_SOPT4_FTM3CH0SRC) +# define SIM_SCGC3_FTM3 (1 << 25) /* Bit 25: RFTM3 Clock Gate Control */ +# endif + /* Bit 26: Reserved */ +# if defined(KINETIS_SIM_HAS_SCGC3_ADC1) +# define SIM_SCGC3_ADC1 (1 << 27) /* Bit 27: ADC1 Clock Gate Control */ +# endif +# if defined(KINETIS_SIM_HAS_SCGC3_ADC3) +# define SIM_SCGC3_ADC3 (1 << 28) /* Bit 28: ADC3 Clock Gate Control */ +# endif + /* Bit 29: Reserved */ +# if defined(KINETIS_SIM_HAS_SCGC3_SLCD) && defined(KINETIS_NSLCD) && KINETIS_NSLCD > 0 +# define SIM_SCGC3_SLCD (1 << 30) /* Bit 30: Segment LCD Clock Gate Control */ +# endif + /* Bit 31: Reserved */ #endif - /* Bits 1-3: Reserved */ -#define SIM_SCGC3_FLEXCAN1 (1 << 4) /* Bit 4: FlexCAN1 Clock Gate Control */ - /* Bits 5-11: Reserved */ -#define SIM_SCGC3_SPI2 (1 << 12) /* Bit 12: SPI2 Clock Gate Control */ - /* Bits 13-16: Reserved */ -#define SIM_SCGC3_SDHC (1 << 17) /* Bit 17: SDHC Clock Gate Control */ - /* Bits 18-23: Reserved */ -#define SIM_SCGC3_FTM2 (1 << 24) /* Bit 24: FTM2 Clock Gate Control */ - /* Bits 25-26: Reserved */ -#if defined(CONFIG_KINETIS_FTM3) -# define SIM_SCGC3_FTM3 (1 << 25) /* Bit 25: FTM3 Clock Gate Control */ -#endif -#define SIM_SCGC3_ADC1 (1 << 27) /* Bit 27: ADC1 Clock Gate Control */ - /* Bits 28-29: Reserved */ -#if defined(KINETIS_NSLCD) && KINETIS_NSLCD > 0 -# define SIM_SCGC3_SLCD (1 << 30) /* Bit 30: Segment LCD Clock Gate Control (K40) */ -#endif - /* Bit 31: Reserved */ + /* System Clock Gating Control Register 4 */ - /* Bit 0: Reserved */ -#define SIM_SCGC4_EWM (1 << 1) /* Bit 1: EWM Clock Gate Control */ -#define SIM_SCGC4_CMT (1 << 2) /* Bit 2: CMT Clock Gate Control */ - /* Bits 3-5: Reserved */ -#define SIM_SCGC4_I2C0 (1 << 6) /* Bit 6: I2C0 Clock Gate Control */ -#define SIM_SCGC4_I2C1 (1 << 7) /* Bit 7: I2C1 Clock Gate Control */ - /* Bits 8-9: Reserved */ -#define SIM_SCGC4_UART0 (1 << 10) /* Bit 10: UART0 Clock Gate Control */ -#define SIM_SCGC4_UART1 (1 << 11) /* Bit 11: UART1 Clock Gate Control */ -#define SIM_SCGC4_UART2 (1 << 12) /* Bit 12: UART2 Clock Gate Control */ -#define SIM_SCGC4_UART3 (1 << 13) /* Bit 13: UART3 Clock Gate Control */ - /* Bits 14-17: Reserved */ -#define SIM_SCGC4_USBOTG (1 << 18) /* Bit 18: USB Clock Gate Control */ -#define SIM_SCGC4_CMP (1 << 19) /* Bit 19: Comparator Clock Gate Control */ -#define SIM_SCGC4_VREF (1 << 20) /* Bit 20: VREF Clock Gate Control */ - /* Bits 21-17: Reserved */ -#define SIM_SCGC4_LLWU (1 << 28) /* Bit 28: LLWU Clock Gate Control */ + + /* Bit 0: Reserved */ +#define SIM_SCGC4_EWM (1 << 1) /* Bit 1: EWM Clock Gate Control */ +#define SIM_SCGC4_CMT (1 << 2) /* Bit 2: CMT Clock Gate Control */ + /* Bits 3-5: Reserved */ +#define SIM_SCGC4_I2C0 (1 << 6) /* Bit 6: I2C0 Clock Gate Control */ +#define SIM_SCGC4_I2C1 (1 << 7) /* Bit 7: I2C1 Clock Gate Control */ + /* Bits 8-9: Reserved */ +#if defined(KINETIS_SIM_HAS_SCGC4_UART0) +# define SIM_SCGC4_UART0 (1 << 10) /* Bit 10: UART0 Clock Gate Control */ +#endif +#if defined(KINETIS_SIM_HAS_SCGC4_UART1) +# define SIM_SCGC4_UART1 (1 << 11) /* Bit 11: UART1 Clock Gate Control */ +#endif +#if defined(KINETIS_SIM_HAS_SCGC4_UART2) +# define SIM_SCGC4_UART2 (1 << 12) /* Bit 12: UART2 Clock Gate Control */ +#endif +#if defined(KINETIS_SIM_HAS_SCGC4_UART3) +# define SIM_SCGC4_UART3 (1 << 13) /* Bit 13: UART3 Clock Gate Control */ +#endif + /* Bits 14-17: Reserved */ +#define SIM_SCGC4_USBOTG (1 << 18) /* Bit 18: USB Clock Gate Control */ +#define SIM_SCGC4_CMP (1 << 19) /* Bit 19: Comparator Clock Gate Control */ +#define SIM_SCGC4_VREF (1 << 20) /* Bit 20: VREF Clock Gate Control */ + /* Bits 21-17: Reserved */ +#if defined(KINETIS_SIM_HAS_SCGC4_LLWU) +# define SIM_SCGC4_LLWU (1 << 28) /* Bit 28: LLWU Clock Gate Control */ +#endif /* Bits 29-31: Reserved */ + /* System Clock Gating Control Register 5 */ -#define SIM_SCGC5_LPTIMER (1 << 0) /* Bit 0: Low Power Timer Clock Gate Control */ -#define SIM_SCGC5_REGFILE (1 << 1) /* Bit 1: Register File Clock Gate Control */ - /* Bits 2-4: Reserved */ -#define SIM_SCGC5_TSI (1 << 5) /* Bit 5: TSI Clock Gate Control */ - /* Bits 6-8: Reserved */ -#define SIM_SCGC5_PORTA (1 << 9) /* Bit 9: Port A Clock Gate Control */ -#define SIM_SCGC5_PORTB (1 << 10) /* Bit 10: Port B Clock Gate Control */ -#define SIM_SCGC5_PORTC (1 << 11) /* Bit 11: Port C Clock Gate Control */ -#define SIM_SCGC5_PORTD (1 << 12) /* Bit 12: Port D Clock Gate Control */ -#define SIM_SCGC5_PORTE (1 << 13) /* Bit 13: Port E Clock Gate Control */ +#define SIM_SCGC5_LPTIMER (1 << 0) /* Bit 0: Low Power Timer Clock Gate Control */ +#if defined(KINETIS_SIM_HAS_SCGC5_REGFILE) +# define SIM_SCGC5_REGFILE (1 << 1) /* Bit 1: Register File Clock Gate Control */ +#endif + /* Bits 2-4: Reserved */ +#if defined(KINETIS_SIM_HAS_SCGC5_TSI) +# define SIM_SCGC5_TSI (1 << 5) /* Bit 5: TSI Clock Gate Control */ +#endif + /* Bits 6-8: Reserved */ +#define SIM_SCGC5_PORTA (1 << 9) /* Bit 9: Port A Clock Gate Control */ +#define SIM_SCGC5_PORTB (1 << 10) /* Bit 10: Port B Clock Gate Control */ +#define SIM_SCGC5_PORTC (1 << 11) /* Bit 11: Port C Clock Gate Control */ +#define SIM_SCGC5_PORTD (1 << 12) /* Bit 12: Port D Clock Gate Control */ +#define SIM_SCGC5_PORTE (1 << 13) /* Bit 13: Port E Clock Gate Control */ +#if defined(KINETIS_SIM_HAS_SCGC5_PORTF) +# define SIM_SCGC5_PORTF (1 << 14) /* Bit 14: Port F Clock Gate Control */ +#endif /* Bits 14-31: Reserved */ /* System Clock Gating Control Register 6 */ +#if defined(KINETIS_SIM_HAS_SCGC6_FTFL) +# define SIM_SCGC6_FTFL (1 << 0) /* Bit 0: Flash Memory Clock Gate Control */ +#endif +#define SIM_SCGC6_DMAMUX0 (1 << 1) /* Bit 1: DMA Mux 0 Clock Gate Control */ + /* Bits 2-3: Reserved */ +#if defined(KINETIS_SIM_HAS_SCGC6_DMAMUX1) +# define SIM_SCGC6_DMAMUX1 (1 << 2) /* Bit 2: DMA Mux 1 Clock Gate Control */ +#endif +#define SIM_SCGC6_FLEXCAN0 (1 << 4) /* Bit 4: FlexCAN0 Clock Gate Control */ + /* Bits 5-9: Reserved */ -#define SIM_SCGC6_FTFL (1 << 0) /* Bit 0: Flash Memory Clock Gate Control */ -#define SIM_SCGC6_DMAMUX (1 << 1) /* Bit 1: DMA Mux Clock Gate Control */ - /* Bits 2-3: Reserved */ -#define SIM_SCGC6_FLEXCAN0 (1 << 4) /* Bit 4: FlexCAN0 Clock Gate Control */ - /* Bits 5-11: Reserved */ -#define SIM_SCGC6_SPI0 (1 << 12) /* Bit 12: SPI0 Clock Gate Control */ -#define SIM_SCGC6_SPI1 (1 << 13) /* Bit 13: SPI1 Clock Gate Control */ - /* Bit 14: Reserved */ -#define SIM_SCGC6_I2S (1 << 15) /* Bit 15: I2S Clock Gate Control */ - /* Bits 16-17: Reserved */ -#define SIM_SCGC6_CRC (1 << 18) /* Bit 18: CRC Clock Gate Control */ - /* Bits 19-20: Reserved */ -#define SIM_SCGC6_USBDCD (1 << 21) /* Bit 21: USB DCD Clock Gate Control */ -#define SIM_SCGC6_PDB (1 << 22) /* Bit 22: PDB Clock Gate Control */ -#define SIM_SCGC6_PIT (1 << 23) /* Bit 23: PIT Clock Gate Control */ -#define SIM_SCGC6_FTM0 (1 << 24) /* Bit 24: FTM0 Clock Gate Control */ -#define SIM_SCGC6_FTM1 (1 << 25) /* Bit 25: FTM1 Clock Gate Control */ - /* Bit 26: Reserved */ -#define SIM_SCGC6_ADC0 (1 << 27) /* Bit 27: ADC0 Clock Gate Control */ - /* Bit 28: Reserved */ -#define SIM_SCGC6_RTC (1 << 29) /* Bit 29: RTC Clock Gate Control */ - /* Bits 30-31: Reserved */ +#if defined(KINETIS_SIM_HAS_SCGC6_RNGA) +# define SIM_SCGC6_RNGA (1 << 9) /* Bit 9: SPI0 Clock Gate Control */ +#endif + /* Bits 10-11: Reserved */ +#define SIM_SCGC6_SPI0 (1 << 12) /* Bit 12: SPI0 Clock Gate Control */ +#define SIM_SCGC6_SPI1 (1 << 13) /* Bit 13: SPI1 Clock Gate Control */ + /* Bit 14: Reserved */ +#define SIM_SCGC6_I2S (1 << 15) /* Bit 15: I2S Clock Gate Control */ + /* Bits 16-17: Reserved */ +#define SIM_SCGC6_CRC (1 << 18) /* Bit 18: CRC Clock Gate Control */ + /* Bits 19-20: Reserved */ +#if defined(KINETIS_SIM_HAS_SCGC6_USBHS) +# define SIM_SCGC6_USBHS (1 << 20) /* Bit 20: USB HS Clock Gate Control */ +#endif +#define SIM_SCGC6_USBDCD (1 << 21) /* Bit 21: USB DCD Clock Gate Control */ +#define SIM_SCGC6_PDB (1 << 22) /* Bit 22: PDB Clock Gate Control */ +#define SIM_SCGC6_PIT (1 << 23) /* Bit 23: PIT Clock Gate Control */ +#define SIM_SCGC6_FTM0 (1 << 24) /* Bit 24: FTM0 Clock Gate Control */ +#define SIM_SCGC6_FTM1 (1 << 25) /* Bit 25: FTM1 Clock Gate Control */ + /* Bit 26: Reserved */ +#if defined(KINETIS_SIM_HAS_SCGC6_FTM2) +# define SIM_SCGC6_FTM2 (1 << 26) /* Bit 26: FTM2 Clock Gate Control */ +#endif +#define SIM_SCGC6_ADC0 (1 << 27) /* Bit 27: ADC0 Clock Gate Control */ + /* Bit 28: Reserved */ +#if defined(KINETIS_SIM_HAS_SCGC6_ADC2) +# define SIM_SCGC6_ADC2 (1 << 28) /* Bit 28: ADC2 Clock Gate Control */ +#endif +#define SIM_SCGC6_RTC (1 << 29) /* Bit 29: RTC Clock Gate Control */ + /* Bits 30-31: Reserved */ +#if defined(KINETIS_SIM_HAS_SCGC6_DAC0) +# define SIM_SCGC6_DAC0 (1 << 31) /* Bit 31: RTC Clock Gate Control */ +#endif + +#if defined(KINETIS_SIM_HAS_SCGC7) /* System Clock Gating Control Register 7 */ -#define SIM_SCGC7_FLEXBUS (1 << 0) /* Bit 0: FlexBus Clock Gate Control */ -#define SIM_SCGC7_DMA (1 << 1) /* Bit 1: DMA Clock Gate Control */ -#define SIM_SCGC7_MPU (1 << 2) /* Bit 2: MPU Clock Gate Control */ - /* Bits 3-31: Reserved */ +# if defined(KINETIS_SIM_HAS_SCGC7_FLEXBUS) +# define SIM_SCGC7_FLEXBUS (1 << 0) /* Bit 0: FlexBus Clock Gate Control */ +# endif +# if defined(KINETIS_SIM_HAS_SCGC7_DMA) +# define SIM_SCGC7_DMA (1 << 1) /* Bit 1: DMA Clock Gate Control */ +# endif +# if defined(KINETIS_SIM_HAS_SCGC7_MPU) +# define SIM_SCGC7_MPU (1 << 2) /* Bit 2: MPU Clock Gate Control */ +# endif +# if defined(KINETIS_SIM_HAS_SCGC7_SDRAMC) +# define SIM_SCGC7_SDRAMC (1 << 3) /* Bit 3: SDRAMC Clock Gate Control */ +# endif + /* Bits 4-31: Reserved */ +# endif + /* System Clock Divider Register 1 */ - /* Bits 0-15: Reserved */ -#define SIM_CLKDIV1_OUTDIV4_SHIFT (16) /* Bits 16-19: Clock 4 output divider value */ -#define SIM_CLKDIV1_OUTDIV4_MASK (15 << SIM_CLKDIV1_OUTDIV4_SHIFT) -# define SIM_CLKDIV1_OUTDIV4(n) ((uint32_t)((n)-1) << SIM_CLKDIV1_OUTDIV4_SHIFT) /* n=1..16 */ -# define SIM_CLKDIV1_OUTDIV4_1 (0 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 1 */ -# define SIM_CLKDIV1_OUTDIV4_2 (1 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 2 */ -# define SIM_CLKDIV1_OUTDIV4_3 (2 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 3 */ -# define SIM_CLKDIV1_OUTDIV4_4 (3 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 4 */ -# define SIM_CLKDIV1_OUTDIV4_5 (4 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 5 */ -# define SIM_CLKDIV1_OUTDIV4_6 (5 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 6 */ -# define SIM_CLKDIV1_OUTDIV4_7 (6 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 7 */ -# define SIM_CLKDIV1_OUTDIV4_8 (7 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 8 */ -# define SIM_CLKDIV1_OUTDIV4_9 (8 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 9 */ -# define SIM_CLKDIV1_OUTDIV4_10 (9 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 10 */ -# define SIM_CLKDIV1_OUTDIV4_11 (10 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 11 */ -# define SIM_CLKDIV1_OUTDIV4_12 (11 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 12 */ -# define SIM_CLKDIV1_OUTDIV4_13 (12 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 13 */ -# define SIM_CLKDIV1_OUTDIV4_14 (13 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 14 */ -# define SIM_CLKDIV1_OUTDIV4_15 (14 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 15 */ -# define SIM_CLKDIV1_OUTDIV4_16 (15 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 16 */ -#define SIM_CLKDIV1_OUTDIV3_SHIFT (20) /* Bits 20-23: Clock 3 output divider value */ -#define SIM_CLKDIV1_OUTDIV3_MASK (15 << SIM_CLKDIV1_OUTDIV3_SHIFT) -# define SIM_CLKDIV1_OUTDIV3(n) ((uint32_t)((n)-1) << SIM_CLKDIV1_OUTDIV3_SHIFT) /* n=1..16 */ -# define SIM_CLKDIV1_OUTDIV3_1 (0 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 1 */ -# define SIM_CLKDIV1_OUTDIV3_2 (1 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 2 */ -# define SIM_CLKDIV1_OUTDIV3_3 (2 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 3 */ -# define SIM_CLKDIV1_OUTDIV3_4 (3 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 4 */ -# define SIM_CLKDIV1_OUTDIV3_5 (4 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 5 */ -# define SIM_CLKDIV1_OUTDIV3_6 (5 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 6 */ -# define SIM_CLKDIV1_OUTDIV3_7 (6 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 7 */ -# define SIM_CLKDIV1_OUTDIV3_8 (7 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 8 */ -# define SIM_CLKDIV1_OUTDIV3_9 (8 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 9 */ -# define SIM_CLKDIV1_OUTDIV3_10 (9 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 10 */ -# define SIM_CLKDIV1_OUTDIV3_11 (10 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 11 */ -# define SIM_CLKDIV1_OUTDIV3_12 (11 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 12 */ -# define SIM_CLKDIV1_OUTDIV3_13 (12 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 13 */ -# define SIM_CLKDIV1_OUTDIV3_14 (13 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 14 */ -# define SIM_CLKDIV1_OUTDIV3_15 (14 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 15 */ -# define SIM_CLKDIV1_OUTDIV3_16 (15 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 16 */ -#define SIM_CLKDIV1_OUTDIV2_SHIFT (24) /* Bits 24-27: Clock 2 output divider value */ -#define SIM_CLKDIV1_OUTDIV2_MASK (15 << SIM_CLKDIV1_OUTDIV2_SHIFT) -# define SIM_CLKDIV1_OUTDIV2(n) ((uint32_t)((n)-1) << SIM_CLKDIV1_OUTDIV2_SHIFT) /* n=1..16 */ -# define SIM_CLKDIV1_OUTDIV2_1 (0 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 1 */ -# define SIM_CLKDIV1_OUTDIV2_2 (1 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 2 */ -# define SIM_CLKDIV1_OUTDIV2_3 (2 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 3 */ -# define SIM_CLKDIV1_OUTDIV2_4 (3 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 4 */ -# define SIM_CLKDIV1_OUTDIV2_5 (4 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 5 */ -# define SIM_CLKDIV1_OUTDIV2_6 (5 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 6 */ -# define SIM_CLKDIV1_OUTDIV2_7 (6 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 7 */ -# define SIM_CLKDIV1_OUTDIV2_8 (7 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 8 */ -# define SIM_CLKDIV1_OUTDIV2_9 (8 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 9 */ -# define SIM_CLKDIV1_OUTDIV2_10 (9 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 10 */ -# define SIM_CLKDIV1_OUTDIV2_11 (10 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 11 */ -# define SIM_CLKDIV1_OUTDIV2_12 (11 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 12 */ -# define SIM_CLKDIV1_OUTDIV2_13 (12 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 13 */ -# define SIM_CLKDIV1_OUTDIV2_14 (13 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 14 */ -# define SIM_CLKDIV1_OUTDIV2_15 (14 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 15 */ -# define SIM_CLKDIV1_OUTDIV2_16 (15 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 16 */ -#define SIM_CLKDIV1_OUTDIV1_SHIFT (28) /* Bits 28-31: Clock 1 output divider value */ -#define SIM_CLKDIV1_OUTDIV1_MASK (15 << SIM_CLKDIV1_OUTDIV1_SHIFT) -# define SIM_CLKDIV1_OUTDIV1(n) ((uint32_t)((n)-1) << SIM_CLKDIV1_OUTDIV1_SHIFT) /* n=1..16 */ -# define SIM_CLKDIV1_OUTDIV1_1 (0 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 1 */ -# define SIM_CLKDIV1_OUTDIV1_2 (1 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 2 */ -# define SIM_CLKDIV1_OUTDIV1_3 (2 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 3 */ -# define SIM_CLKDIV1_OUTDIV1_4 (3 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 4 */ -# define SIM_CLKDIV1_OUTDIV1_5 (4 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 5 */ -# define SIM_CLKDIV1_OUTDIV1_6 (5 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 6 */ -# define SIM_CLKDIV1_OUTDIV1_7 (6 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 7 */ -# define SIM_CLKDIV1_OUTDIV1_8 (7 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 8 */ -# define SIM_CLKDIV1_OUTDIV1_9 (8 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 9 */ -# define SIM_CLKDIV1_OUTDIV1_10 (9 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 10 */ -# define SIM_CLKDIV1_OUTDIV1_11 (10 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 11 */ -# define SIM_CLKDIV1_OUTDIV1_12 (11 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 12 */ -# define SIM_CLKDIV1_OUTDIV1_13 (12 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 13 */ -# define SIM_CLKDIV1_OUTDIV1_14 (13 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 14 */ -# define SIM_CLKDIV1_OUTDIV1_15 (14 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 15 */ -# define SIM_CLKDIV1_OUTDIV1_16 (15 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 16 */ + +#if defined(KINETIS_SIM_HAS_CLKDIV1_OUTDIV5) + /* Bits 0-15: Reserved */ +#endif +#if defined(KINETIS_SIM_HAS_CLKDIV1_OUTDIV4) +# define SIM_CLKDIV1_OUTDIV4_SHIFT (16) /* Bits 16-19: Clock 4 output divider value */ +# define SIM_CLKDIV1_OUTDIV4_MASK (15 << SIM_CLKDIV1_OUTDIV4_SHIFT) +# define SIM_CLKDIV1_OUTDIV4(n) ((uint32_t)((n)-1) << SIM_CLKDIV1_OUTDIV4_SHIFT) /* n=1..16 */ +# define SIM_CLKDIV1_OUTDIV4_1 (0 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 1 */ +# define SIM_CLKDIV1_OUTDIV4_2 (1 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 2 */ +# define SIM_CLKDIV1_OUTDIV4_3 (2 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 3 */ +# define SIM_CLKDIV1_OUTDIV4_4 (3 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 4 */ +# define SIM_CLKDIV1_OUTDIV4_5 (4 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 5 */ +# define SIM_CLKDIV1_OUTDIV4_6 (5 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 6 */ +# define SIM_CLKDIV1_OUTDIV4_7 (6 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 7 */ +# define SIM_CLKDIV1_OUTDIV4_8 (7 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 8 */ +# define SIM_CLKDIV1_OUTDIV4_9 (8 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 9 */ +# define SIM_CLKDIV1_OUTDIV4_10 (9 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 10 */ +# define SIM_CLKDIV1_OUTDIV4_11 (10 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 11 */ +# define SIM_CLKDIV1_OUTDIV4_12 (11 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 12 */ +# define SIM_CLKDIV1_OUTDIV4_13 (12 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 13 */ +# define SIM_CLKDIV1_OUTDIV4_14 (13 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 14 */ +# define SIM_CLKDIV1_OUTDIV4_15 (14 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 15 */ +# define SIM_CLKDIV1_OUTDIV4_16 (15 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 16 */ +#endif +#if defined(KINETIS_SIM_HAS_CLKDIV1_OUTDIV3) +# define SIM_CLKDIV1_OUTDIV3_SHIFT (20) /* Bits 20-23: Clock 3 output divider value */ +# define SIM_CLKDIV1_OUTDIV3_MASK (15 << SIM_CLKDIV1_OUTDIV3_SHIFT) +# define SIM_CLKDIV1_OUTDIV3(n) ((uint32_t)((n)-1) << SIM_CLKDIV1_OUTDIV3_SHIFT) /* n=1..16 */ +# define SIM_CLKDIV1_OUTDIV3_1 (0 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 1 */ +# define SIM_CLKDIV1_OUTDIV3_2 (1 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 2 */ +# define SIM_CLKDIV1_OUTDIV3_3 (2 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 3 */ +# define SIM_CLKDIV1_OUTDIV3_4 (3 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 4 */ +# define SIM_CLKDIV1_OUTDIV3_5 (4 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 5 */ +# define SIM_CLKDIV1_OUTDIV3_6 (5 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 6 */ +# define SIM_CLKDIV1_OUTDIV3_7 (6 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 7 */ +# define SIM_CLKDIV1_OUTDIV3_8 (7 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 8 */ +# define SIM_CLKDIV1_OUTDIV3_9 (8 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 9 */ +# define SIM_CLKDIV1_OUTDIV3_10 (9 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 10 */ +# define SIM_CLKDIV1_OUTDIV3_11 (10 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 11 */ +# define SIM_CLKDIV1_OUTDIV3_12 (11 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 12 */ +# define SIM_CLKDIV1_OUTDIV3_13 (12 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 13 */ +# define SIM_CLKDIV1_OUTDIV3_14 (13 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 14 */ +# define SIM_CLKDIV1_OUTDIV3_15 (14 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 15 */ +# define SIM_CLKDIV1_OUTDIV3_16 (15 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 16 */ +#endif +#if defined(KINETIS_SIM_HAS_CLKDIV1_OUTDIV2) +# define SIM_CLKDIV1_OUTDIV2_SHIFT (24) /* Bits 24-27: Clock 2 output divider value */ +# define SIM_CLKDIV1_OUTDIV2_MASK (15 << SIM_CLKDIV1_OUTDIV2_SHIFT) +# define SIM_CLKDIV1_OUTDIV2(n) ((uint32_t)((n)-1) << SIM_CLKDIV1_OUTDIV2_SHIFT) /* n=1..16 */ +# define SIM_CLKDIV1_OUTDIV2_1 (0 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 1 */ +# define SIM_CLKDIV1_OUTDIV2_2 (1 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 2 */ +# define SIM_CLKDIV1_OUTDIV2_3 (2 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 3 */ +# define SIM_CLKDIV1_OUTDIV2_4 (3 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 4 */ +# define SIM_CLKDIV1_OUTDIV2_5 (4 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 5 */ +# define SIM_CLKDIV1_OUTDIV2_6 (5 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 6 */ +# define SIM_CLKDIV1_OUTDIV2_7 (6 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 7 */ +# define SIM_CLKDIV1_OUTDIV2_8 (7 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 8 */ +# define SIM_CLKDIV1_OUTDIV2_9 (8 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 9 */ +# define SIM_CLKDIV1_OUTDIV2_10 (9 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 10 */ +# define SIM_CLKDIV1_OUTDIV2_11 (10 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 11 */ +# define SIM_CLKDIV1_OUTDIV2_12 (11 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 12 */ +# define SIM_CLKDIV1_OUTDIV2_13 (12 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 13 */ +# define SIM_CLKDIV1_OUTDIV2_14 (13 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 14 */ +# define SIM_CLKDIV1_OUTDIV2_15 (14 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 15 */ +# define SIM_CLKDIV1_OUTDIV2_16 (15 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 16 */ +#endif +#define SIM_CLKDIV1_OUTDIV1_SHIFT (28) /* Bits 28-31: Clock 1 output divider value */ +#define SIM_CLKDIV1_OUTDIV1_MASK (15 << SIM_CLKDIV1_OUTDIV1_SHIFT) +# define SIM_CLKDIV1_OUTDIV1(n) ((uint32_t)((n)-1) << SIM_CLKDIV1_OUTDIV1_SHIFT) /* n=1..16 */ +# define SIM_CLKDIV1_OUTDIV1_1 (0 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 1 */ +# define SIM_CLKDIV1_OUTDIV1_2 (1 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 2 */ +# define SIM_CLKDIV1_OUTDIV1_3 (2 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 3 */ +# define SIM_CLKDIV1_OUTDIV1_4 (3 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 4 */ +# define SIM_CLKDIV1_OUTDIV1_5 (4 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 5 */ +# define SIM_CLKDIV1_OUTDIV1_6 (5 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 6 */ +# define SIM_CLKDIV1_OUTDIV1_7 (6 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 7 */ +# define SIM_CLKDIV1_OUTDIV1_8 (7 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 8 */ +# define SIM_CLKDIV1_OUTDIV1_9 (8 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 9 */ +# define SIM_CLKDIV1_OUTDIV1_10 (9 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 10 */ +# define SIM_CLKDIV1_OUTDIV1_11 (10 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 11 */ +# define SIM_CLKDIV1_OUTDIV1_12 (11 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 12 */ +# define SIM_CLKDIV1_OUTDIV1_13 (12 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 13 */ +# define SIM_CLKDIV1_OUTDIV1_14 (13 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 14 */ +# define SIM_CLKDIV1_OUTDIV1_15 (14 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 15 */ +# define SIM_CLKDIV1_OUTDIV1_16 (15 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 16 */ /* System Clock Divider Register 2 */ -#define SIM_CLKDIV2_USBFRAC (1 << 0) /* Bit 0: USB clock divider fraction */ -#define SIM_CLKDIV2_USBDIV_SHIFT (1) /* Bits 1-3: USB clock divider divisor */ -#define SIM_CLKDIV2_USBDIV_MASK (7 << SIM_CLKDIV2_USBDIV_SHIFT) - /* Bits 4-7: Reserved */ -#define SIM_CLKDIV2_I2SFRAC_SHIFT (8) /* Bits 8-15: I2S clock divider fraction */ -#define SIM_CLKDIV2_I2SFRAC_MASK (0xff << SIM_CLKDIV2_I2SFRAC_SHIFT) - /* Bits 16-19: Reserved */ -#define SIM_CLKDIV2_I2SDIV_SHIFT (20) /* Bits 20-31: I2S clock divider value */ -#define SIM_CLKDIV2_I2SDIV_MASK (0xfff << SIM_CLKDIV2_I2SDIV_SHIFT) - -/* Flash Configuration Register 1 */ - /* Bits 0-7: Reserved */ -#define SIM_FCFG1_DEPART_SHIFT (8) /* Bits 8-11: FlexNVM partition */ -#define SIM_FCFG1_DEPART_MASK (15 << SIM_FCFG1_DEPART_SHIFT) - /* Bits 12-15: Reserved */ -#define SIM_FCFG1_EESIZE_SHIFT (16) /* Bits 16-19: EEPROM size*/ -#define SIM_FCFG1_EESIZE_MASK (15 << SIM_FCFG1_EESIZE_SHIFT) -# define SIM_FCFG1_EESIZE_4KB (2 << SIM_FCFG1_EESIZE_SHIFT) /* 4 KB */ -# define SIM_FCFG1_EESIZE_2KB (3 << SIM_FCFG1_EESIZE_SHIFT) /* 2 KB */ -# define SIM_FCFG1_EESIZE_1KB (4 << SIM_FCFG1_EESIZE_SHIFT) /* 1 KB */ -# define SIM_FCFG1_EESIZE_512B (5 << SIM_FCFG1_EESIZE_SHIFT) /* 512 Bytes */ -# define SIM_FCFG1_EESIZE_256B (6 << SIM_FCFG1_EESIZE_SHIFT) /* 256 Bytes */ -# define SIM_FCFG1_EESIZE_128B (7 << SIM_FCFG1_EESIZE_SHIFT) /* 128 Bytes */ -# define SIM_FCFG1_EESIZE_64B (8 << SIM_FCFG1_EESIZE_SHIFT) /* 64 Bytes */ -# define SIM_FCFG1_EESIZE_32B (9 << SIM_FCFG1_EESIZE_SHIFT) /* 32 Bytes */ -# define SIM_FCFG1_EESIZE_NONE (15 << SIM_FCFG1_EESIZE_SHIFT) /* 0 Bytes */ - /* Bits 20-23: Reserved */ -#if defined(KINETIS_K40) || defined(KINETIS_K64) -# define SIM_FCFG1_PFSIZE_SHIFT (24) /* Bits 24-27: Program flash size (K40) */ -# define SIM_FCFG1_PFSIZE_MASK (15 << SIM_FCFG1_PFSIZE_SHIFT) -# define SIM_FCFG1_PFSIZE_128KB (7 << SIM_FCFG1_PFSIZE_SHIFT) /* 128KB program flash, 4KB protection region */ -# define SIM_FCFG1_PFSIZE_256KB (9 << SIM_FCFG1_PFSIZE_SHIFT) /* 256KB program flash, 8KB protection region */ -# define SIM_FCFG1_PFSIZE_512KB (11 << SIM_FCFG1_PFSIZE_SHIFT) /* 512KB program flash, 16KB protection region */ -# define SIM_FCFG1_PFSIZE_512KB2 (15 << SIM_FCFG1_PFSIZE_SHIFT) /* 512KB program flash, 16KB protection region */ -# define SIM_FCFG1_NVMSIZE_SHIFT (28) /* Bits 28-31: FlexNVM size (K40)*/ -# define SIM_FCFG1_NVMSIZE_MASK (15 << SIM_FCFG1_NVMSIZE_SHIFT) -# define SIM_FCFG1_NVMSIZE_NONE (0 << SIM_FCFG1_NVMSIZE_SHIFT) /* 0KB FlexNVM */ -# define SIM_FCFG1_NVMSIZE_128KB (7 << SIM_FCFG1_NVMSIZE_SHIFT) /* 128KB FlexNVM, 16KB protection region */ -# define SIM_FCFG1_NVMSIZE_256KB (9 << SIM_FCFG1_NVMSIZE_SHIFT) /* 256KB FlexNVM, 32KB protection region */ -# define SIM_FCFG1_NVMSIZE_256KB2 (15 << SIM_FCFG1_NVMSIZE_SHIFT) /* 256KB FlexNVM, 32KB protection region */ +#if defined(KINETIS_SIM_HAS_CLKDIV2_USBFRAC) +# define SIM_CLKDIV2_USBFRAC (1 << 0) /* Bit 0: USB clock divider fraction */ +#endif +#if defined(KINETIS_SIM_HAS_CLKDIV2_USBDIV) +# define SIM_CLKDIV2_USBDIV_SHIFT (1) /* Bits 1-3: USB clock divider divisor */ +# define SIM_CLKDIV2_USBDIV_MASK (7 << SIM_CLKDIV2_USBDIV_SHIFT) +#endif + /* Bits 4-7: Reserved */ +#if defined(KINETIS_SIM_HAS_CLKDIV2_USBHSFRAC) +# define SIM_CLKDIV2_USBHSFRAC (1 << 8) /* Bit 8: USB HS clock divider fraction */ +#endif +#if defined(KINETIS_SIM_HAS_CLKDIV2_USBHSDIV) +# define SIM_CLKDIV2_USBHSDIV_SHIFT (9) /* Bits 1-3: USB HS clock divider divisor */ +# define SIM_CLKDIV2_USBHSDIV_MASK (7 << SIM_CLKDIV2_USBHSDIV_SHIFT) +#endif +#if defined(KINETIS_SIM_HAS_CLKDIV2_I2SFRAC) +# define SIM_CLKDIV2_I2SFRAC_SHIFT (8) /* Bits 8-15: I2S clock divider fraction */ +# define SIM_CLKDIV2_I2SFRAC_MASK (0xff << SIM_CLKDIV2_I2SFRAC_SHIFT) +#endif + /* Bits 16-19: Reserved */ +#if defined(KINETIS_SIM_HAS_CLKDIV2_I2SDIV) +# define SIM_CLKDIV2_I2SDIV_SHIFT (20) /* Bits 20-31: I2S clock divider value */ +# define SIM_CLKDIV2_I2SDIV_MASK (0xfff << SIM_CLKDIV2_I2SDIV_SHIFT) #endif -#ifdef KINETIS_K60 -# define SIM_FCFG1_FSIZE_SHIFT (24) /* Bits 24-31: Flash size (K60)*/ -# define SIM_FCFG1_FSIZE_MASK (0xff << SIM_FCFG1_FSIZE_SHIFT) -# define SIM_FCFG1_FSIZE_32KB (2 << SIM_FCFG1_FSIZE_SHIFT) /* 32KB program flash, 1KB protection region */ -# define SIM_FCFG1_FSIZE_64KB (4 << SIM_FCFG1_FSIZE_SHIFT) /* 64KB program flash, 2KB protection region */ -# define SIM_FCFG1_FSIZE_128KB (6 << SIM_FCFG1_FSIZE_SHIFT) /* 128KB program flash, 4KB protection region */ -# define SIM_FCFG1_FSIZE_256KB (8 << SIM_FCFG1_FSIZE_SHIFT) /* 256KB program flash, 8KB protection region */ -# define SIM_FCFG1_FSIZE_512KB (12 << SIM_FCFG1_FSIZE_SHIFT) /* 512KB program flash, 16KB protection region */ +/* Flash Configuration Register 1 */ + +#if defined(KINETIS_SIM_HAS_FCFG1_FTFDIS) +# define SIM_FCFG1_FTFDIS (1 << 0) /* Bit 0: Disable FTFE */ +#endif +#if defined(KINETIS_SIM_HAS_FCFG1_FLASHDIS) +# define SIM_FCFG1_FLASHDIS (1 << 0) /* Bit 0: Flash Disable */ +#endif +#if defined(KINETIS_SIM_HAS_FCFG1_FLASHDOZE) +# define SIM_FCFG1_FLASHDOZE (1 << 1) /* Bit 1: Flash Doze */ +#endif + /* Bits 0-7: Reserved */ +#if defined(KINETIS_SIM_HAS_FCFG1_DEPART) +# define SIM_FCFG1_DEPART_SHIFT (8) /* Bits 8-11: FlexNVM partition */ +# define SIM_FCFG1_DEPART_MASK (15 << SIM_FCFG1_DEPART_SHIFT) +#endif + /* Bits 12-15: Reserved */ +#if defined(KINETIS_SIM_HAS_FCFG1_EESIZE) +# define SIM_FCFG1_EESIZE_SHIFT (16) /* Bits 16-19: EEPROM size */ +# define SIM_FCFG1_EESIZE_MASK (15 << SIM_FCFG1_EESIZE_SHIFT) +# define SIM_FCFG1_EESIZE_16KB (0 << SIM_FCFG1_EESIZE_SHIFT) /* 16 KB */ +# define SIM_FCFG1_EESIZE_8KB (1 << SIM_FCFG1_EESIZE_SHIFT) /* 8 KB */ +# define SIM_FCFG1_EESIZE_4KB (2 << SIM_FCFG1_EESIZE_SHIFT) /* 4 KB */ +# define SIM_FCFG1_EESIZE_2KB (3 << SIM_FCFG1_EESIZE_SHIFT) /* 2 KB */ +# define SIM_FCFG1_EESIZE_1KB (4 << SIM_FCFG1_EESIZE_SHIFT) /* 1 KB */ +# define SIM_FCFG1_EESIZE_512B (5 << SIM_FCFG1_EESIZE_SHIFT) /* 512 Bytes */ +# define SIM_FCFG1_EESIZE_256B (6 << SIM_FCFG1_EESIZE_SHIFT) /* 256 Bytes */ +# define SIM_FCFG1_EESIZE_128B (7 << SIM_FCFG1_EESIZE_SHIFT) /* 128 Bytes */ +# define SIM_FCFG1_EESIZE_64B (8 << SIM_FCFG1_EESIZE_SHIFT) /* 64 Bytes */ +# define SIM_FCFG1_EESIZE_32B (9 << SIM_FCFG1_EESIZE_SHIFT) /* 32 Bytes */ +# define SIM_FCFG1_EESIZE_NONE (15 << SIM_FCFG1_EESIZE_SHIFT) /* 0 Bytes */ +#endif + /* Bits 20-23: Reserved */ +#define SIM_FCFG1_PFSIZE_SHIFT (24) /* Bits 24-27: Program flash size */ +#define SIM_FCFG1_PFSIZE_MASK (15 << SIM_FCFG1_PFSIZE_SHIFT) +# if defined(KINETIS_K40) +# define SIM_FCFG1_PFSIZE_128KB (7 << SIM_FCFG1_PFSIZE_SHIFT) /* 128KB program flash, 4KB protection region */ +# define SIM_FCFG1_PFSIZE_256KB (9 << SIM_FCFG1_PFSIZE_SHIFT) /* 256KB program flash, 8KB protection region */ +# define SIM_FCFG1_PFSIZE_512KB (11 << SIM_FCFG1_PFSIZE_SHIFT) /* 512KB program flash, 16KB protection region */ +# define SIM_FCFG1_PFSIZE_512KB2 (15 << SIM_FCFG1_PFSIZE_SHIFT) /* 512KB program flash, 16KB protection region */ +# endif +# if defined(KINETIS_K60) +# define SIM_FCFG1_PFSIZE_512KB (11 << SIM_FCFG1_PFSIZE_SHIFT) /* 512 KB, 16 KB protection size */ +# define SIM_FCFG1_PFSIZE_1024KB (13 << SIM_FCFG1_PFSIZE_SHIFT) /* 1024 KB, 32 KB protection size */ +# define SIM_FCFG1_PFSIZE_2048KB (15 << SIM_FCFG1_PFSIZE_SHIFT) /* 1024 KB, 32 KB protection size */ +# endif +# if defined(KINETIS_K64) || defined(KINETIS_K66) +# define SIM_FCFG1_PFSIZE_32KB (3 << SIM_FCFG1_PFSIZE_SHIFT) /* 32 KB of program flash memory */ +# define SIM_FCFG1_PFSIZE_64KB (5 << SIM_FCFG1_PFSIZE_SHIFT) /* 64 KB of program flash memory */ +# define SIM_FCFG1_PFSIZE_128KB (7 << SIM_FCFG1_PFSIZE_SHIFT) /* 128 KB of program flash memory */ +# define SIM_FCFG1_PFSIZE_256KB (9 << SIM_FCFG1_PFSIZE_SHIFT) /* 256 KB of program flash memory */ +# define SIM_FCFG1_PFSIZE_512KB (11 << SIM_FCFG1_PFSIZE_SHIFT) /* 512 KB of program flash memory */ +# define SIM_FCFG1_PFSIZE_1024KB (13 << SIM_FCFG1_PFSIZE_SHIFT) /* 1024 KB of program flash memory */ +# define SIM_FCFG1_PFSIZE_2048KB (15 << SIM_FCFG1_PFSIZE_SHIFT) /* 2048 KB of program flash memory */ +# endif + +#if defined(KINETIS_SIM_HAS_FCFG1_NVMSIZE) +# define SIM_FCFG1_NVMSIZE_SHIFT (28) /* Bits 28-31: FlexNVM size */ +# define SIM_FCFG1_NVMSIZE_MASK (15 << SIM_FCFG1_NVMSIZE_SHIFT) +# define SIM_FCFG1_NVMSIZE_NONE (0 << SIM_FCFG1_NVMSIZE_SHIFT) /* 0KB FlexNVM */ +# define SIM_FCFG1_NVMSIZE_128KB (7 << SIM_FCFG1_NVMSIZE_SHIFT) /* 128KB FlexNVM, 16KB protection region */ +# define SIM_FCFG1_NVMSIZE_256KB (9 << SIM_FCFG1_NVMSIZE_SHIFT) /* 256KB FlexNVM, 32KB protection region */ +# define SIM_FCFG1_NVMSIZE_256KB2 (15 << SIM_FCFG1_NVMSIZE_SHIFT) /* 256KB FlexNVM, 32KB protection region */ #endif /* Flash Configuration Register 2 */ /* Bits 0-15: Reserved */ -#define SIM_FCFG2_MAXADDR1_SHIFT (16) /* Bits 16-21: Max address block 1 */ -#define SIM_FCFG2_MAXADDR1_MASK (nn << SIM_FCFG2_MAXADDR1_SHIFT) - /* Bit 22: Reserved */ -#define SIM_FCFG2_PFLSH (1 << 23) /* Bit 23: Program flash */ -#define SIM_FCFG2_MAXADDR0_SHIFT (24) /* Bits 24-29: Max address block 0 */ -#define SIM_FCFG2_MAXADDR0_MASK (nn << SIM_FCFG2_MAXADDR0_SHIFT) - /* Bit 30: Reserved */ -#define SIM_FCFG2_SWAPPFLSH (1 << 31) /* Bit 31: Swap program flash */ +#if (KINETIS_SIM_HAS_FCFG2_MAXADDR1) +# define SIM_FCFG2_MAXADDR1_SHIFT (16) /* Bits 16-[21|22]: Max address block 1 */ +# define SIM_FCFG2_MAXADDR1_MASK (KINETIS_SIM_FCFG2_MAXADDR1_MASK << SIM_FCFG2_MAXADDR1_SHIFT) +# define SIM_FCFG2_MAXADDR1(n) (((n) & KINETIS_SIM_FCFG2_MAXADDR1_MASK) << SIM_FCFG2_MAXADDR1_SHIFT) +#endif + /* Bit 22: Reserved */ +#if defined(KINETIS_SIM_HAS_FCFG2_PFLSH) +# define SIM_FCFG2_PFLSH (1 << 23) /* Bit 23: Program flash */ +#endif +#if defined(KINETIS_SIM_HAS_FCFG2_MAXADDR0) +# define SIM_FCFG2_MAXADDR0_SHIFT (24) /* Bits 24-[29|30]: Max address block 0 */ +# define SIM_FCFG2_MAXADDR0_MASK (KINETIS_SIM_FCFG2_MAXADDR0_MASK << SIM_FCFG2_MAXADDR0_SHIFT) +# define SIM_FCFG2_MAXADDR0(n) (((n) & KINETIS_SIM_FCFG2_MAXADDR0_MASK) << SIM_FCFG2_MAXADDR0_SHIFT) + /* Bit 30: Reserved */ +#endif +#if defined(KINETIS_SIM_HAS_FCFG2_SWAPPFLSH) +# define SIM_FCFG2_SWAPPFLSH (1 << 31) /* Bit 31: Swap program flash */ +#endif /* Unique Identification Register High. 32-bit Unique Identification. */ /* Unique Identification Register Mid-High. 32-bit Unique Identification. */ /* Unique Identification Register Mid Low. 32-bit Unique Identification. */ /* Unique Identification Register Low. 32-bit Unique Identification. */ +#if defined(KINETIS_SIM_HAS_CLKDIV3) +/* System Clock Divider Register 3 */ + +# if defined(KINETIS_SIM_HAS_CLKDIV3_PLLFLLFRAC) +# define SIM_CLKDIV3_PLLFLLFRAC (1 << 0) /* Bit 0: PLLFLL clock divider fraction */ +# endif +# if defined(KINETIS_SIM_HAS_CLKDIV3_PLLFLLDIV) +# define SIM_CLKDIV3_PLLFLLDIV_SHIFT (1) /* Bits 1-3: PLLFLL clock divider divisor */ +# define SIM_CLKDIV3_PLLFLLDIV_MASK (7 << SIM_CLKDIV3_PLLFLLDIV_SHIFT) +# define SIM_CLKDIV3_PLLFLLDIV(n) ((((n)-1) & 7) << SIM_CLKDIV3_PLLFLLDIV_SHIFT) /* n=1..8 */ +# endif +#endif +#if defined(KINETIS_SIM_HAS_CLKDIV4) +/* System Clock Divider Register 4 */ + +# if defined(KINETIS_SIM_HAS_CLKDIV4_TRACEFRAC) +# define SIM_CLKDIV4_TRACEFRAC (1 << 0) /* Bit 0: Trace clock divider fraction */ +# endif +# if defined(KINETIS_SIM_HAS_CLKDIV4_TRACEDIV) +# define SIM_CLKDIV4_TRACEDIV_SHIFT (1) /* Bits 1-3: Trace clock divider divisor */ +# define SIM_CLKDIV4_TRACEDIV_MASK (7 << SIM_CLKDIV3_TRACEDIV_SHIFT) +# define SIM_CLKDIV4_TRACEDIV(n) ((((n)-1) & 7) << SIM_CLKDIV4_TRACEDIV_SHIFT) /* n=1..8 */ +# endif +# if defined(KINETIS_SIM_HAS_CLKDIV4_NFCFRAC) +# define SIM_CLKDIV4_NFCFRAC_SHIFT (24) /* Bits 24-26: NFC clock divider fraction */ +# define SIM_CLKDIV4_NFCFRAC_MASK (7 << SIM_CLKDIV4_NFCFRAC_SHIFT) +# define SIM_CLKDIV4_NFCFRAC(n) ((((n)-1) & 7) << SIM_CLKDIV4_NFCFRAC_SHIFT) /* n=1..8 */ +# endif +# if defined(KINETIS_SIM_HAS_CLKDIV4_NFCDIV) +# define SIM_CLKDIV4_NFCDIV_SHIFT (27) /* Bits 27-31: NFC clock divider divisor */ +# define SIM_CLKDIV4_NFCDIV_MASK (31 << SIM_CLKDIV3_NFCDIV_SHIFT) +# define SIM_CLKDIV4_NFCDIV(n) ((((n)-1) & 31) << SIM_CLKDIV4_NFCDIV_SHIFT) /* n=1..32 */ +# endif +#endif + +#if defined(KINETIS_SIM_HAS_MCR) +/* Misc Control Register */ + + /* Bits 0-28: Reserved */ +# define SIM_MCR_PDBLOOP (1<< 29) /* Bit 29: PDB Loop Mode */ + /* Bit 30: Reserved */ +# define SIM_MCR_TRACECLKDIS (1<< 31) /* Bit 31: Trace clock disable. */ +#endif + /************************************************************************************ * Public Types ************************************************************************************/ diff --git a/arch/arm/src/kinetis/kinetis_clockconfig.c b/arch/arm/src/kinetis/kinetis_clockconfig.c index 8080fbd11b3..f4852dbb007 100644 --- a/arch/arm/src/kinetis/kinetis_clockconfig.c +++ b/arch/arm/src/kinetis/kinetis_clockconfig.c @@ -45,6 +45,7 @@ #include "chip/kinetis_mcg.h" #include "chip/kinetis_sim.h" #include "chip/kinetis_fmc.h" +#include "chip/kinetis_pmc.h" #include "chip/kinetis_llwu.h" #include "chip/kinetis_pinmux.h" @@ -191,7 +192,9 @@ static inline void kinesis_portclocks(void) void kinetis_pllconfig(void) { +#if defined(SIM_SCGC4_LLWU) uint32_t regval32; +#endif uint8_t regval8; #if defined(BOARD_MCG_C2) @@ -228,16 +231,25 @@ void kinetis_pllconfig(void) MCG_C2_RANGE_VHIGH | MCG_C2_EREFS, KINETIS_MCG_C2); # endif #endif /* defined(BOARD_MCG_C2) */ - +#if defined(SIM_SCGC4_LLWU) /* Released latched state of oscillator and GPIO */ regval32 = getreg32(KINETIS_SIM_SCGC4); regval32 |= SIM_SCGC4_LLWU; putreg32(regval32, KINETIS_SIM_SCGC4); +#endif +#if defined(LLWU_CS_ACKISO) regval8 = getreg8(KINETIS_LLWU_CS); regval8 |= LLWU_CS_ACKISO; putreg8(regval8, KINETIS_LLWU_CS); +#endif + +#if defined(PMC_REGSC_ACKISO) + regval8 = getreg8(KINETIS_PMC_REGSC); + regval8 |= PMC_REGSC_ACKISO; + putreg8(regval8, KINETIS_PMC_REGSC); +#endif /* Select external oscillator and Reference Divider and clear IREFS to * start the external oscillator. diff --git a/arch/arm/src/kinetis/kinetis_enet.c b/arch/arm/src/kinetis/kinetis_enet.c index a640de5cc6e..e688212ee30 100644 --- a/arch/arm/src/kinetis/kinetis_enet.c +++ b/arch/arm/src/kinetis/kinetis_enet.c @@ -2011,6 +2011,11 @@ static void kinetis_reset(struct kinetis_driver_s *priv) int kinetis_netinitialize(int intf) { struct kinetis_driver_s *priv; +#ifdef CONFIG_NET_ETHERNET + uint32_t uidl; + uint32_t uidml; + uint8_t *mac; +#endif uint32_t regval; /* Get the interface structure associated with this interface number. */ @@ -2158,9 +2163,9 @@ int kinetis_netinitialize(int intf) * 1st octet) */ - uint32_t uidl = getreg32(KINETIS_SIM_UIDL); - uint32_t uidml = getreg32(KINETIS_SIM_UIDML); - uint8_t *mac = priv->dev.d_mac.ether_addr_octet; + uidl = getreg32(KINETIS_SIM_UIDL); + uidml = getreg32(KINETIS_SIM_UIDML); + mac = priv->dev.d_mac.ether_addr_octet; uidml |= 0x00000200; uidml &= 0x0000FEFF; diff --git a/arch/arm/src/kinetis/kinetis_usbdev.c b/arch/arm/src/kinetis/kinetis_usbdev.c index 231fc014303..1a77fafaf1e 100644 --- a/arch/arm/src/kinetis/kinetis_usbdev.c +++ b/arch/arm/src/kinetis/kinetis_usbdev.c @@ -4396,10 +4396,11 @@ void up_usbinitialize(void) * easier. */ #if 1 +#warning "This code needs to be driven by BOARD_ settings and SIM_SOPT2[PLLFLLSE] needs to be set globally" /* 1: Select clock source */ regval = getreg32(KINETIS_SIM_SOPT2); - regval |= SIM_SOPT2_PLLFLLSEL | SIM_SOPT2_USBSRC; + regval |= SIM_SOPT2_PLLFLLSEL_MCGPLLCLK | SIM_SOPT2_USBSRC; putreg32(regval, KINETIS_SIM_SOPT2); regval = getreg32(KINETIS_SIM_CLKDIV2); diff --git a/arch/arm/src/stm32f7/stm32_allocateheap.c b/arch/arm/src/stm32f7/stm32_allocateheap.c index 8b21ad68b76..ffa6d27455b 100644 --- a/arch/arm/src/stm32f7/stm32_allocateheap.c +++ b/arch/arm/src/stm32f7/stm32_allocateheap.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/src/stm32f7/up_allocateheap.c * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2015, 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -57,10 +57,12 @@ #include "up_arch.h" #include "up_internal.h" #include "stm32_mpuinit.h" +#include "stm32_dtcm.h" /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ + /* Internal SRAM is available in all members of the STM32 family. The * following definitions must be provided to specify the size and * location of internal(system) SRAM: @@ -92,6 +94,20 @@ #define SRAM2_START STM32_SRAM2_BASE #define SRAM2_END (SRAM2_START + STM32F7_SRAM2_SIZE) +/* The STM32 F7 has DTCM memory */ + +#undef HAVE_DTCM +#define HAVE_DTCM 1 +#if !defined(DTCM_START) || !defined(DTCM_END) +# undef HAVE_DTCM +#endif + +/* DTCM to be excluded from the main heap. */ + +#ifdef CONFIG_STM32F7_DTCMEXCLUDE +# undef HAVE_DTCM +#endif + /* We can't possibly have FSMC SRAM if the FSMC is not enabled */ #ifndef CONFIG_STM32F7_FSMC @@ -110,7 +126,7 @@ # endif #endif -/* There are 3 possible heap configurations: +/* There are 4 possible heap configurations: * * Configuration 1. System SRAM1 (only) * CONFIG_MM_REGIONS == 1 @@ -118,9 +134,18 @@ * Configuration 2. System SRAM1 and SRAM2 * CONFIG_MM_REGIONS == 2 * CONFIG_STM32F7_FSMC_SRAM NOT defined - * Configuration 3. System SRAM1 and SRAM2 and FSMC SRAM + * Configuration 3. System SRAM1 and SRAM2 and DTCM + * CONFIG_MM_REGIONS == 3 + * CONFIG_STM32F7_FSMC_SRAM undefined + * HAVE_DTCM defined + * Configuration 4. System SRAM1 and SRAM2 and FSMC SRAM * CONFIG_MM_REGIONS == 3 * CONFIG_STM32F7_FSMC_SRAM defined + * HAVE_DTCM undefined + * Configuration 5. System SRAM1 and SRAM2 and DTCM and FSMC SRAM + * CONFIG_MM_REGIONS == 4 + * CONFIG_STM32F7_FSMC_SRAM defined + * HAVE_DTCM defined * * Let's make sure that all definitions are consistent before doing * anything else @@ -128,24 +153,48 @@ #if CONFIG_MM_REGIONS < 2 # ifdef CONFIG_STM32F7_FSMC_SRAM -# warning FSMC SRAM and SRAM2 excluded from the heap -# else -# warning "SRAM2 excluded from the heap" +# warning "FSMC SRAM excluded from the heap" +# undef CONFIG_STM32F7_FSMC_SRAM # endif +# ifdef HAVE_DTCM +# warning "DTCM excluded from the heap" +# undef HAVE_DTCM +# endif +# warning "SRAM2 excluded from the heap" #elif CONFIG_MM_REGIONS < 3 # ifdef CONFIG_STM32F7_FSMC_SRAM -# warning FSMC SRAM excluded from the heap +# warning "FSMC SRAM excluded from the heap" +# undef CONFIG_STM32F7_FSMC_SRAM +# endif +# ifdef HAVE_DTCM +# warning "DTCM excluded from the heap" +# undef HAVE_DTCM # endif #elif CONFIG_MM_REGIONS < 4 -# ifndef CONFIG_STM32F7_FSMC_SRAM -# error CONFIG_MM_REGIONS > 2 but I do not know what some of the region(s) are +# if defined(CONFIG_STM32F7_FSMC_SRAM) && defined(HAVE_DTCM) +# warning "CONFIG_MM_REGIONS == 3 but have both FSMC SRAM and DTCM. DTCM excluded from the heap." +# undef HAVE_DTCM +# elif !defined(CONFIG_STM32F7_FSMC_SRAM) && !defined(HAVE_DTCM) +# error "CONFIG_MM_REGIONS == 3 but I do not know what some of the region(s) are" # undef CONFIG_MM_REGIONS # define CONFIG_MM_REGIONS 2 # endif +#elif CONFIG_MM_REGIONS < 5 +# if !defined(CONFIG_STM32F7_FSMC_SRAM) && !defined(HAVE_DTCM) +# error "CONFIG_MM_REGIONS == 4 but I do not know what some of the region(s) are" +# undef CONFIG_MM_REGIONS +# define CONFIG_MM_REGIONS 2 +# elif !defined(CONFIG_STM32F7_FSMC_SRAM) || !defined(HAVE_DTCM) +# error "CONFIG_MM_REGIONS == 4 but I do not know what some of the region(s) are" +# undef CONFIG_MM_REGIONS +# define CONFIG_MM_REGIONS 3 +# endif #else -# error CONFIG_MM_REGIONS > 3 but I do not know what some of the region(s) are +# error "CONFIG_MM_REGIONS > 4 but I do not know what some of the region(s) are" # undef CONFIG_MM_REGIONS -# ifdef CONFIG_STM32F7_FSMC_SRAM +# if defined(CONFIG_STM32F7_FSMC_SRAM) && defined(HAVE_DTCM) +# define CONFIG_MM_REGIONS 4 +# elif defined(CONFIG_STM32F7_FSMC_SRAM) || defined(HAVE_DTCM) # define CONFIG_MM_REGIONS 3 # else # define CONFIG_MM_REGIONS 2 @@ -338,6 +387,24 @@ void up_addregion(void) kumm_addregion((FAR void *)SRAM2_START, SRAM2_END-SRAM2_START); +#ifdef HAVE_DTCM +#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) + + /* Allow user-mode access to the DTCM heap */ + + stm32_mpu_uheap((uintptr_t)DTCM_START, DTCM_END-DTCM_START); + +#endif + + /* Colorize the heap for debug */ + + up_heap_color((FAR void *)DTCM_START, DTCM_END-DTCM_START); + + /* Add the DTCM user heap region. */ + + kumm_addregion((FAR void *)DTCM_START, DTCM_END-DTCM_START); +#endif + #ifdef CONFIG_STM32F7_FSMC_SRAM #if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) diff --git a/arch/arm/src/stm32l4/chip/stm32l4_comp.h b/arch/arm/src/stm32l4/chip/stm32l4_comp.h index 3f0b4ceeec0..a09c6826527 100644 --- a/arch/arm/src/stm32l4/chip/stm32l4_comp.h +++ b/arch/arm/src/stm32l4/chip/stm32l4_comp.h @@ -69,19 +69,11 @@ # define COMP_CSR_INMSEL_VREF (3 << COMP_CSR_INMSEL_SHIFT) /* VREFINT */ # define COMP_CSR_INMSEL_DAC1 (4 << COMP_CSR_INMSEL_SHIFT) /* DAC Channel1 */ # define COMP_CSR_INMSEL_DAC2 (5 << COMP_CSR_INMSEL_SHIFT) /* DAC Channel2 */ -# define COMP_CSR_INMSEL_PIN1 (6 << COMP_CSR_INMSEL_SHIFT) /* Input minus pin 1 */ -# define COMP_CSR_INMSEL_PIN2 (7 << COMP_CSR_INMSEL_SHIFT) /* Input minus pin 2 */ -# define COMP1_CSR_INMSEL_PB1 (6 << COMP_CSR_INMSEL_SHIFT) /* PB1 */ -# define COMP1_CSR_INMSEL_PC4 (7 << COMP_CSR_INMSEL_SHIFT) /* PC4 */ -# define COMP2_CSR_INMSEL_PB3 (6 << COMP_CSR_INMSEL_SHIFT) /* PB3 */ -# define COMP2_CSR_INMSEL_PB7 (7 << COMP_CSR_INMSEL_SHIFT) /* PB7 */ +# define COMP_CSR_INMSEL_PIN1 (6 << COMP_CSR_INMSEL_SHIFT) /* Input minus pin 1: COMP1=PB1; COMP2=PB3 */ +# define COMP_CSR_INMSEL_PIN2 (7 << COMP_CSR_INMSEL_SHIFT) /* Input minus pin 2: COMP1=PC4; COMP2=PB7 */ #define COMP_CSR_INPSEL_MASK (1 << 7) /* Bit 7: Input plus selection bit */ -# define COMP1_CSR_INPSEL_PIN1 (0) -# define COMP1_CSR_INPSEL_PIN2 COMP_CSR_INPSEL_MASK -# define COMP1_CSR_INPSEL_PC5 (0) -# define COMP1_CSR_INPSEL_PB2 COMP_CSR_INPSEL_MASK -# define COMP2_CSR_INPSEL_PB4 (0) -# define COMP2_CSR_INPSEL_PB6 COMP_CSR_INPSEL_MASK +# define COMP_CSR_INPSEL_PIN1 (0) /* Input plus pin 1: COMP1=PC5; COMP2=PB4 */ +# define COMP_CSR_INPSEL_PIN2 COMP_CSR_INPSEL_MASK /* Input plus pin 1: COMP1=PB2; COMP2=PB6 */ #define COMP2_CSR_WINMODE (1 << 9) /* Bit 9: Windows mode selection bit (COMP2 only) */ # define COMP2_CSR_WINMODE_NOCONN (0) /* Comparator 2 input not connected to Comparator 1 */ # define COMP2_CSR_WINMODE_CONN COMP2_CSR_WINMODE /* Comparator 2 input connected to Comparator 1 */ diff --git a/arch/arm/src/stm32l4/stm32l4_comp.c b/arch/arm/src/stm32l4/stm32l4_comp.c index 1bb374b6bfd..518e648639c 100644 --- a/arch/arm/src/stm32l4/stm32l4_comp.c +++ b/arch/arm/src/stm32l4/stm32l4_comp.c @@ -107,18 +107,18 @@ int stm32l4_compconfig(int cmp, const struct stm32l4_comp_config_s *cfg) { case STM32L4_COMP_INP_PIN_1: stm32l4_configgpio(cmp == STM32L4_COMP1 ? GPIO_COMP1_INP_1 : GPIO_COMP2_INP_1); - regval |= COMP1_CSR_INPSEL_PIN1; + regval |= COMP_CSR_INPSEL_PIN1; break; case STM32L4_COMP_INP_PIN_2: stm32l4_configgpio(cmp == STM32L4_COMP1 ? GPIO_COMP1_INP_2 : GPIO_COMP2_INP_2); - regval |= COMP1_CSR_INPSEL_PIN2; + regval |= COMP_CSR_INPSEL_PIN2; break; #if defined(CONFIG_STM32L4_STM32L4X3) case STM32L4_COMP_INP_PIN_3: stm32l4_configgpio(cmp == STM32L4_COMP1 ? GPIO_COMP1_INP_3 : GPIO_COMP2_INP_3); - regval |= COMP1_CSR_INPSEL_PIN3; + regval |= COMP_CSR_INPSEL_PIN3; break; #endif diff --git a/configs/bambino-200e/netnsh/defconfig b/configs/bambino-200e/netnsh/defconfig index f14b084712a..231bc772b6e 100644 --- a/configs/bambino-200e/netnsh/defconfig +++ b/configs/bambino-200e/netnsh/defconfig @@ -852,7 +852,6 @@ CONFIG_LIBM=y # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/bambino-200e/usbnsh/defconfig b/configs/bambino-200e/usbnsh/defconfig index addc5c43b59..646cdbadd64 100644 --- a/configs/bambino-200e/usbnsh/defconfig +++ b/configs/bambino-200e/usbnsh/defconfig @@ -726,7 +726,6 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/fire-stm32v2/nsh/defconfig b/configs/fire-stm32v2/nsh/defconfig index 73ae596e633..3495a7f0b8c 100644 --- a/configs/fire-stm32v2/nsh/defconfig +++ b/configs/fire-stm32v2/nsh/defconfig @@ -1176,7 +1176,6 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/freedom-k64f/nsh/defconfig b/configs/freedom-k64f/nsh/defconfig index 94a2d1e639b..f8371fbefa8 100644 --- a/configs/freedom-k64f/nsh/defconfig +++ b/configs/freedom-k64f/nsh/defconfig @@ -709,7 +709,6 @@ CONFIG_NUNGET_CHARS=2 # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/freedom-k66f/netnsh/defconfig b/configs/freedom-k66f/netnsh/defconfig index f7da08de50c..b31db4cfb09 100644 --- a/configs/freedom-k66f/netnsh/defconfig +++ b/configs/freedom-k66f/netnsh/defconfig @@ -916,7 +916,6 @@ CONFIG_ARCH_LOWPUTC=y # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set diff --git a/configs/freedom-k66f/nsh/defconfig b/configs/freedom-k66f/nsh/defconfig index 3da05837dad..c8032c952b8 100644 --- a/configs/freedom-k66f/nsh/defconfig +++ b/configs/freedom-k66f/nsh/defconfig @@ -802,7 +802,6 @@ CONFIG_ARCH_LOWPUTC=y # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set diff --git a/configs/hymini-stm32v/nsh/defconfig b/configs/hymini-stm32v/nsh/defconfig index 5bdfc7afe64..c569511e342 100644 --- a/configs/hymini-stm32v/nsh/defconfig +++ b/configs/hymini-stm32v/nsh/defconfig @@ -923,7 +923,6 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/hymini-stm32v/nsh2/defconfig b/configs/hymini-stm32v/nsh2/defconfig index d5127eca8de..b27306fb538 100644 --- a/configs/hymini-stm32v/nsh2/defconfig +++ b/configs/hymini-stm32v/nsh2/defconfig @@ -1139,7 +1139,6 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/hymini-stm32v/usbmsc/defconfig b/configs/hymini-stm32v/usbmsc/defconfig index cc248064cf2..b69eb4a9acb 100644 --- a/configs/hymini-stm32v/usbmsc/defconfig +++ b/configs/hymini-stm32v/usbmsc/defconfig @@ -976,7 +976,6 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/nucleo-144/f767-evalos/defconfig b/configs/nucleo-144/f767-evalos/defconfig index a8983105698..058f4a1c878 100644 --- a/configs/nucleo-144/f767-evalos/defconfig +++ b/configs/nucleo-144/f767-evalos/defconfig @@ -747,7 +747,7 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue" # Memory Management # # CONFIG_MM_SMALL is not set -CONFIG_MM_REGIONS=2 +CONFIG_MM_REGIONS=3 # CONFIG_ARCH_HAVE_HEAP2 is not set # CONFIG_GRAN is not set diff --git a/configs/nucleo-144/f767-nsh/defconfig b/configs/nucleo-144/f767-nsh/defconfig index 12bbaa33e14..5131470f0fa 100644 --- a/configs/nucleo-144/f767-nsh/defconfig +++ b/configs/nucleo-144/f767-nsh/defconfig @@ -734,7 +734,7 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue" # Memory Management # # CONFIG_MM_SMALL is not set -CONFIG_MM_REGIONS=2 +CONFIG_MM_REGIONS=3 # CONFIG_ARCH_HAVE_HEAP2 is not set # CONFIG_GRAN is not set diff --git a/configs/nucleo-l476rg/nsh/defconfig b/configs/nucleo-l476rg/nsh/defconfig index 995507d4e63..b9156d1774e 100644 --- a/configs/nucleo-l476rg/nsh/defconfig +++ b/configs/nucleo-l476rg/nsh/defconfig @@ -760,7 +760,6 @@ CONFIG_ARCH_LOWPUTC=y # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set diff --git a/configs/olimex-stm32-p407/include/board.h b/configs/olimex-stm32-p407/include/board.h index 75038ad39d9..d8458931402 100644 --- a/configs/olimex-stm32-p407/include/board.h +++ b/configs/olimex-stm32-p407/include/board.h @@ -235,6 +235,11 @@ #define GPIO_USART3_CTS GPIO_USART3_CTS_2 /* PD11 */ #define GPIO_USART3_RTS GPIO_USART3_RTS_2 /* PD12 */ +/* USART6: */ + +#define GPIO_USART6_RX GPIO_USART6_RX_2 /* PG9 */ +#define GPIO_USART6_TX GPIO_USART6_TX_1 /* PC6 */ + /* CAN: */ #define GPIO_CAN1_RX GPIO_CAN1_RX_2 /* PB8 */ diff --git a/configs/olimex-stm32-p407/knsh/defconfig b/configs/olimex-stm32-p407/knsh/defconfig index d49b31fbd7d..4e30aad6199 100644 --- a/configs/olimex-stm32-p407/knsh/defconfig +++ b/configs/olimex-stm32-p407/knsh/defconfig @@ -944,7 +944,6 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/olimex-stm32-p407/nsh/defconfig b/configs/olimex-stm32-p407/nsh/defconfig index 1d81763bc97..264454ff37a 100644 --- a/configs/olimex-stm32-p407/nsh/defconfig +++ b/configs/olimex-stm32-p407/nsh/defconfig @@ -937,7 +937,6 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/olimex-stm32-p407/src/Makefile b/configs/olimex-stm32-p407/src/Makefile index fa543389eb4..6c580d3f096 100644 --- a/configs/olimex-stm32-p407/src/Makefile +++ b/configs/olimex-stm32-p407/src/Makefile @@ -48,6 +48,11 @@ ifeq ($(CONFIG_ARCH_BUTTONS),y) CSRCS += stm32_buttons.c endif + +ifeq ($(CONFIG_STM32_FSMC),y) +CSRCS += stm32_sram.c +endif + ifeq ($(CONFIG_STM32_OTGFS),y) CSRCS += stm32_usb.c endif diff --git a/configs/olimex-stm32-p407/src/olimex-stm32-p407.h b/configs/olimex-stm32-p407/src/olimex-stm32-p407.h index ecf95b60c0a..76cc41e8604 100644 --- a/configs/olimex-stm32-p407/src/olimex-stm32-p407.h +++ b/configs/olimex-stm32-p407/src/olimex-stm32-p407.h @@ -190,6 +190,36 @@ int stm32_bringup(void); +/************************************************************************************ + * Name: stm32_stram_configure + * + * Description: + * Initialize to access external SRAM. SRAM will be visible at the FSMC Bank + * NOR/SRAM2 base address (0x64000000) + * + * General transaction rules. The requested AHB transaction data size can be 8-, + * 16- or 32-bit wide whereas the SRAM has a fixed 16-bit data width. Some simple + * transaction rules must be followed: + * + * Case 1: AHB transaction width and SRAM data width are equal + * There is no issue in this case. + * Case 2: AHB transaction size is greater than the memory size + * In this case, the FSMC splits the AHB transaction into smaller consecutive + * memory accesses in order to meet the external data width. + * Case 3: AHB transaction size is smaller than the memory size. + * SRAM supports the byte select feature. + * a) FSMC allows write transactions accessing the right data through its + * byte lanes (NBL[1:0]) + * b) Read transactions are allowed (the controller reads the entire memory + * word and uses the needed byte only). The NBL[1:0] are always kept low + * during read transactions. + * + ************************************************************************************/ + +#ifdef CONFIG_STM32_FSMC +void stm32_stram_configure(void); +#endif + /************************************************************************************ * Name: stm32_usb_configure * diff --git a/configs/olimex-stm32-p407/src/stm32_boot.c b/configs/olimex-stm32-p407/src/stm32_boot.c index 220455fef01..f52fe6d2e03 100644 --- a/configs/olimex-stm32-p407/src/stm32_boot.c +++ b/configs/olimex-stm32-p407/src/stm32_boot.c @@ -63,6 +63,12 @@ void stm32_boardinitialize(void) { +#ifdef CONFIG_STM32_FSMC + /* If the FSMC is enabled, then enable SRAM access */ + + stm32_stram_configure(); +#endif + /* Initialize USB if the 1) OTG FS controller is in the configuration and 2) * disabled, and 3) the weak function stm32_usb_configure() has been brought * into the build. Presumeably either CONFIG_USBDEV or CONFIG_USBHOST is also diff --git a/configs/olimex-stm32-p407/src/stm32_sram.c b/configs/olimex-stm32-p407/src/stm32_sram.c new file mode 100644 index 00000000000..3350c467af4 --- /dev/null +++ b/configs/olimex-stm32-p407/src/stm32_sram.c @@ -0,0 +1,262 @@ +/************************************************************************************ + * configs/olimex-stm32-p407/src/stm32_sram.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include +#include + +#include "chip.h" +#include "up_arch.h" + +#include "stm32.h" +#include "stm3240g-eval.h" + +#ifdef CONFIG_STM32_FSMC + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +#if STM32_NGPIO_PORTS < 6 +# error "Required GPIO ports not enabled" +#endif + +#if defined(CONFIG_STM32_USART3) || defined(CONFIG_STM32_USART6) +# error "USART3 and USART6 conflict with use of SRAM" +#endif + +/* SRAM Timing + * REVIST: These were ported from the STM3240G-EVAL and have not been verified on + * this platform. + */ + +#define SRAM_ADDRESS_SETUP_TIME 3 +#define SRAM_ADDRESS_HOLD_TIME 0 +#define SRAM_DATA_SETUP_TIME 6 +#define SRAM_BUS_TURNAROUND_DURATION 1 +#define SRAM_CLK_DIVISION 0 +#define SRAM_DATA_LATENCY 0 + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Private Data + ************************************************************************************/ + +/* GPIOs Configuration ************************************************************** + *---------------------+------------------+------------------+-----------------+ + * GPIO FSMC NOTE |GPIO FSMC NOTE|GPIO FSMC NOTE|GPIO FSMC NOTE| + *---------------------+------------------+------------------+-----------------+ + * PD0 FSMC_D2 |PE0 FSMC_NBL0 |PF0 FSMC_A0 |PG0 FSMC_A10 | + * PD1 FSMC_D3 |PE1 FSMC_NBL1 |PF1 FSMC_A1 |PG1 FSMC_A11 | + * | |PF2 FSMC_A2 |PG2 FSMC_A12 | + * | |PF3 FSMC_A3 |PG3 FSMC_A13 | + * PD4 FSMC_NOE 2 | |PF4 FSMC_A4 |PG4 FSMC_A14 | + * PD5 FSMC_NWE | |PF5 FSMC_A5 |PG5 FSMC_A15 | + * | | | | + * PD7 FSMC_NE1/NCE2 |PE7 FSMC_D4 | | | + * PD8 FSMC_D13 1 |PE8 FSMC_D5 | | | + * PD9 FSMC_D14 1 |PE9 FSMC_D6 | | | + * PD10 FSMC_D15 1 |PE10 FSMC_D7 | | | + * PD11 FSMC_A16 1 |PE11 FSMC_D8 | | | + * PD12 FSMC_A17 |PE12 FSMC_D9 |PF12 FSMC_A6 | | + * |PE13 FSMC_D10 |PF13 FSMC_A7 | | + * PD14 FSMC_D0 |PE14 FSMC_D11 |PF14 FSMC_A8 | | + * PD15 FSMC_D1 |PE15 FSMC_D12 |PF15 FSMC_A9 | | + *---------------------+------------------+------------------+-----------------+ + * + * NOTES: + * (1) Shared with USART3: PD8=USART3_TX PD9=USART3_RX PD11=USART3_CTS + * PD12=USART3_RTS + * (2) Shared with USB: PD4=USB_HS_FAULT + */ + +/* SRAM GPIO configuration */ + +static const uint32_t g_sramconfig[] = +{ + /* Address configuration: FSMC_A0-FSMC_A17 */ + + GPIO_FSMC_A0, GPIO_FSMC_A1 , GPIO_FSMC_A2, GPIO_FSMC_A3, GPIO_FSMC_A4 , GPIO_FSMC_A5, + GPIO_FSMC_A6, GPIO_FSMC_A7, GPIO_FSMC_A8, GPIO_FSMC_A9, GPIO_FSMC_A10, GPIO_FSMC_A11, + GPIO_FSMC_A12, GPIO_FSMC_A13, GPIO_FSMC_A14, GPIO_FSMC_A15, GPIO_FSMC_A16, GPIO_FSMC_A17, + + /* Data Configuration: FSMC_D0-FSMC_D15 */ + + GPIO_FSMC_D0, GPIO_FSMC_D1 , GPIO_FSMC_D2, GPIO_FSMC_D3, GPIO_FSMC_D4 , GPIO_FSMC_D5, + GPIO_FSMC_D6, GPIO_FSMC_D7, GPIO_FSMC_D8, GPIO_FSMC_D9, GPIO_FSMC_D10, GPIO_FSMC_D11, + GPIO_FSMC_D12, GPIO_FSMC_D13, GPIO_FSMC_D14, GPIO_FSMC_D15 + + /* Control Signals: + * + * /CS = PD7, FSMC_NE1 + * /OE = PD4, FSMC_NOE + * /WE = PD5, FSMC_NWE + * /BHE = PE0, FSMC_NBL0 + * /BHL = PE1, PSMC_NBL1 + */ + + GPIO_FSMC_NE1, GPIO_FSMC_NOE, GPIO_FSMC_NWE, GPIO_FSMC_NBL0, GPIO_FSMC_NBL1 +}; +#define NSRAM_CONFIG (sizeof(g_sramconfig)/sizeof(uint32_t)) + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: stm32_enablefsmc + * + * Description: + * Enable clocking to the FSMC module + * + ************************************************************************************/ + +static void stm32_enablefsmc(void) +{ + uint32_t regval; + + /* Enable AHB clocking to the FSMC */ + + regval = getreg32( STM32_RCC_AHB3ENR); + regval |= RCC_AHB3ENR_FSMCEN; + putreg32(regval, STM32_RCC_AHB3ENR); +} + +/************************************************************************************ + * Name: stm32_sramgpios + * + * Description: + * Configure SRAM GPIO pins + * + ************************************************************************************/ + +static void stm32_sramgpios(void) +{ + int i; + + /* Configure SRAM GPIOs */ + + for (i = 0; i < NSRAM_CONFIG; i++) + { + stm32_configgpio(g_sramconfig[i]); + } +} + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: stm32_stram_configure + * + * Description: + * Initialize to access external SRAM. SRAM will be visible at the FSMC Bank + * NOR/SRAM2 base address (0x64000000) + * + * General transaction rules. The requested AHB transaction data size can be 8-, + * 16- or 32-bit wide whereas the SRAM has a fixed 16-bit data width. Some simple + * transaction rules must be followed: + * + * Case 1: AHB transaction width and SRAM data width are equal + * There is no issue in this case. + * Case 2: AHB transaction size is greater than the memory size + * In this case, the FSMC splits the AHB transaction into smaller consecutive + * memory accesses in order to meet the external data width. + * Case 3: AHB transaction size is smaller than the memory size. + * SRAM supports the byte select feature. + * a) FSMC allows write transactions accessing the right data through its + * byte lanes (NBL[1:0]) + * b) Read transactions are allowed (the controller reads the entire memory + * word and uses the needed byte only). The NBL[1:0] are always kept low + * during read transactions. + * + ************************************************************************************/ + +void stm32_stram_configure(void) +{ + /* Configure GPIO pins */ + + stm32_extmemgpios(g_sramconfig, NSRAM_CONFIG); /* SRAM-specific control lines */ + + /* Enable AHB clocking to the FSMC */ + + stm32_enablefsmc(); + + /* Bank1 NOR/SRAM control register configuration + * + * Bank enable : Not yet + * Data address mux : Disabled + * Memory Type : PSRAM + * Data bus width : 16-bits + * Flash access : Disabled + * Burst access mode : Disabled + * Polarity : Low + * Wrapped burst mode : Disabled + * Write timing : Before state + * Write enable : Yes + * Wait signal : Disabled + * Extended mode : Disabled + * Asynchronous wait : Disabled + * Write burst : Disabled + */ + + putreg32((FSMC_BCR_PSRAM | FSMC_BCR_MWID16 | FSMC_BCR_WREN), STM32_FSMC_BCR2); + + /* Bank1 NOR/SRAM timing register configuration */ + + putreg32((FSMC_BTR_ADDSET(SRAM_ADDRESS_SETUP_TIME) | FSMC_BTR_ADDHLD(SRAM_ADDRESS_HOLD_TIME) | + FSMC_BTR_DATAST(SRAM_DATA_SETUP_TIME) | FSMC_BTR_BUSTURN(SRAM_BUS_TURNAROUND_DURATION) | + FSMC_BTR_CLKDIV(SRAM_CLK_DIVISION) | FSMC_BTR_DATLAT(SRAM_DATA_LATENCY) | + FSMC_BTR_ACCMODA), + STM32_FSMC_BTR2); + + /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */ + + putreg32(0xffffffff, STM32_FSMC_BWTR2); /* Extended mode not used */ + + /* Enable the bank */ + + putreg32((FSMC_BCR_MBKEN | FSMC_BCR_PSRAM | FSMC_BCR_MWID16 | FSMC_BCR_WREN), STM32_FSMC_BCR2); +} + +#endif /* CONFIG_STM32_FSMC */ diff --git a/configs/open1788/knsh/defconfig b/configs/open1788/knsh/defconfig index 07bc4bb806e..77f55906843 100644 --- a/configs/open1788/knsh/defconfig +++ b/configs/open1788/knsh/defconfig @@ -687,7 +687,6 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/open1788/nsh/defconfig b/configs/open1788/nsh/defconfig index 98453cfa474..cadcbd8d9d4 100644 --- a/configs/open1788/nsh/defconfig +++ b/configs/open1788/nsh/defconfig @@ -684,7 +684,6 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/sam4s-xplained-pro/nsh/defconfig b/configs/sam4s-xplained-pro/nsh/defconfig index 1dbfc022368..788b53c4faf 100644 --- a/configs/sam4s-xplained-pro/nsh/defconfig +++ b/configs/sam4s-xplained-pro/nsh/defconfig @@ -831,7 +831,6 @@ CONFIG_NUNGET_CHARS=2 # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/sama5d3x-ek/demo/defconfig b/configs/sama5d3x-ek/demo/defconfig index 59e5a4aadfd..36d6061a81f 100644 --- a/configs/sama5d3x-ek/demo/defconfig +++ b/configs/sama5d3x-ek/demo/defconfig @@ -910,7 +910,6 @@ CONFIG_NUNGET_CHARS=2 # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7A_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/sama5d3x-ek/nxplayer/defconfig b/configs/sama5d3x-ek/nxplayer/defconfig index 2cfc66ab289..72f90e709d6 100644 --- a/configs/sama5d3x-ek/nxplayer/defconfig +++ b/configs/sama5d3x-ek/nxplayer/defconfig @@ -859,7 +859,6 @@ CONFIG_NUNGET_CHARS=2 # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7A_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/sama5d4-ek/elf/defconfig b/configs/sama5d4-ek/elf/defconfig index f655be3561e..12c4f503eb7 100644 --- a/configs/sama5d4-ek/elf/defconfig +++ b/configs/sama5d4-ek/elf/defconfig @@ -782,7 +782,6 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set CONFIG_LIBC_ARCH_ELF=y # CONFIG_ARMV7A_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/sama5d4-ek/ipv6/defconfig b/configs/sama5d4-ek/ipv6/defconfig index c93f8ba6724..94b5c44322e 100644 --- a/configs/sama5d4-ek/ipv6/defconfig +++ b/configs/sama5d4-ek/ipv6/defconfig @@ -1243,7 +1243,6 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7A_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/sama5d4-ek/knsh/defconfig b/configs/sama5d4-ek/knsh/defconfig index 8e8f52d2d6c..ef2d700d1a3 100644 --- a/configs/sama5d4-ek/knsh/defconfig +++ b/configs/sama5d4-ek/knsh/defconfig @@ -831,7 +831,6 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set CONFIG_LIBC_ARCH_ELF=y # CONFIG_ARMV7A_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/sama5d4-ek/nsh/defconfig b/configs/sama5d4-ek/nsh/defconfig index 6b4bd49fa88..6e9b13f709e 100644 --- a/configs/sama5d4-ek/nsh/defconfig +++ b/configs/sama5d4-ek/nsh/defconfig @@ -1247,7 +1247,6 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7A_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/sama5d4-ek/nxwm/defconfig b/configs/sama5d4-ek/nxwm/defconfig index da05e2c1fc2..a77ab4e6cbe 100644 --- a/configs/sama5d4-ek/nxwm/defconfig +++ b/configs/sama5d4-ek/nxwm/defconfig @@ -1239,7 +1239,6 @@ CONFIG_LIBM=y # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7A_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/same70-xplained/netnsh/defconfig b/configs/same70-xplained/netnsh/defconfig index 50457729763..ceff93f76cc 100644 --- a/configs/same70-xplained/netnsh/defconfig +++ b/configs/same70-xplained/netnsh/defconfig @@ -986,7 +986,6 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/same70-xplained/nsh/defconfig b/configs/same70-xplained/nsh/defconfig index f3486acd06b..1c771712930 100644 --- a/configs/same70-xplained/nsh/defconfig +++ b/configs/same70-xplained/nsh/defconfig @@ -819,7 +819,6 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/samv71-xult/knsh/defconfig b/configs/samv71-xult/knsh/defconfig index cf6aeef2e38..369dcc43d4c 100644 --- a/configs/samv71-xult/knsh/defconfig +++ b/configs/samv71-xult/knsh/defconfig @@ -829,7 +829,6 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/samv71-xult/module/defconfig b/configs/samv71-xult/module/defconfig index a5f3e3043b7..2c060c0c5e2 100644 --- a/configs/samv71-xult/module/defconfig +++ b/configs/samv71-xult/module/defconfig @@ -741,7 +741,6 @@ CONFIG_MODLIB_BUFFERINCR=32 # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set CONFIG_LIBC_ARCH_ELF=y # CONFIG_ARMV7M_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/samv71-xult/mxtxplnd/defconfig b/configs/samv71-xult/mxtxplnd/defconfig index 63eef944d0e..858d40340fa 100644 --- a/configs/samv71-xult/mxtxplnd/defconfig +++ b/configs/samv71-xult/mxtxplnd/defconfig @@ -950,7 +950,6 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/samv71-xult/netnsh/defconfig b/configs/samv71-xult/netnsh/defconfig index 535e8d25b45..adcd503dde6 100644 --- a/configs/samv71-xult/netnsh/defconfig +++ b/configs/samv71-xult/netnsh/defconfig @@ -989,7 +989,6 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/samv71-xult/nsh/defconfig b/configs/samv71-xult/nsh/defconfig index 5d1d84fc0a6..90d4a321fcf 100644 --- a/configs/samv71-xult/nsh/defconfig +++ b/configs/samv71-xult/nsh/defconfig @@ -822,7 +822,6 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/samv71-xult/nxwm/defconfig b/configs/samv71-xult/nxwm/defconfig index ee1a5d4f509..be4635e3323 100644 --- a/configs/samv71-xult/nxwm/defconfig +++ b/configs/samv71-xult/nxwm/defconfig @@ -968,7 +968,6 @@ CONFIG_LIBM=y # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/samv71-xult/vnc/defconfig b/configs/samv71-xult/vnc/defconfig index 47bdacb1db8..c8eca8144a6 100644 --- a/configs/samv71-xult/vnc/defconfig +++ b/configs/samv71-xult/vnc/defconfig @@ -1090,7 +1090,6 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/samv71-xult/vnxwm/defconfig b/configs/samv71-xult/vnxwm/defconfig index 7e0ae170591..b17bf8ba95f 100644 --- a/configs/samv71-xult/vnxwm/defconfig +++ b/configs/samv71-xult/vnxwm/defconfig @@ -1118,7 +1118,6 @@ CONFIG_LIBM=y # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/stm3210e-eval/composite/defconfig b/configs/stm3210e-eval/composite/defconfig index f454776e90b..8e3a48b02b9 100644 --- a/configs/stm3210e-eval/composite/defconfig +++ b/configs/stm3210e-eval/composite/defconfig @@ -1056,7 +1056,6 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/stm3210e-eval/nsh/defconfig b/configs/stm3210e-eval/nsh/defconfig index 889b14ce339..d233f7dc33f 100644 --- a/configs/stm3210e-eval/nsh/defconfig +++ b/configs/stm3210e-eval/nsh/defconfig @@ -1013,7 +1013,6 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/stm3210e-eval/nsh2/defconfig b/configs/stm3210e-eval/nsh2/defconfig index 48c896283e2..74add5e1970 100644 --- a/configs/stm3210e-eval/nsh2/defconfig +++ b/configs/stm3210e-eval/nsh2/defconfig @@ -1173,7 +1173,6 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/stm3210e-eval/usbmsc/defconfig b/configs/stm3210e-eval/usbmsc/defconfig index e403f0a600c..6195a105332 100644 --- a/configs/stm3210e-eval/usbmsc/defconfig +++ b/configs/stm3210e-eval/usbmsc/defconfig @@ -981,7 +981,6 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/stm3220g-eval/nsh2/defconfig b/configs/stm3220g-eval/nsh2/defconfig index f537fb7c3c7..34f4a330203 100644 --- a/configs/stm3220g-eval/nsh2/defconfig +++ b/configs/stm3220g-eval/nsh2/defconfig @@ -1145,7 +1145,6 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/stm3240g-eval/nsh2/defconfig b/configs/stm3240g-eval/nsh2/defconfig index 07738c41d00..5065e288c67 100644 --- a/configs/stm3240g-eval/nsh2/defconfig +++ b/configs/stm3240g-eval/nsh2/defconfig @@ -1149,7 +1149,6 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/stm32f103-minimum/Kconfig b/configs/stm32f103-minimum/Kconfig index 15ead9d2c21..3479da27251 100644 --- a/configs/stm32f103-minimum/Kconfig +++ b/configs/stm32f103-minimum/Kconfig @@ -4,4 +4,10 @@ # if ARCH_BOARD_STM32F103_MINIMUM + +config STM32F103MINIMUM_QETIMER + int "Timer to use with QE encoder" + default 4 + depends on QENCODER + endif diff --git a/configs/stm32f103-minimum/README.txt b/configs/stm32f103-minimum/README.txt index 08d359f66a3..48350487d37 100644 --- a/configs/stm32f103-minimum/README.txt +++ b/configs/stm32f103-minimum/README.txt @@ -4,70 +4,86 @@ README This README discusses issues unique to NuttX configurations for the STM32F103C8T6 Minimum System Development Board for ARM Microcontroller. -This board is available from several vendors on the net, and may -be sold under different names or no name at all. It is based on a -STM32F103C8T6 and has a DIP-40 form-factor. +Contents +======== -There are two versions of very similar boards: One is red and one is -blue. See http://www.stm32duino.com/viewtopic.php?f=28&t=117 + - STM32F103C8T6 Minimum System Development Boards: + - LEDs + - UARTs + - Timer Inputs/Outputs + - Using 128KiB of Flash instead of 64KiB + - Quadrature Encoder + - STM32F103 Minimum - specific Configuration Options + - Configurations -The Red Board: +STM32F103C8T6 Minimum System Development Boards: +================================================ - Good things about the red board: + This STM32F103C8T6 minimum system development board is available from + several vendors on the net, and may be sold under different names or + no name at all. It is based on a STM32F103C8T6 and has a DIP-40 form- + factor. - - 1.5k pull up resistor on the PA12 pin (USB D+) which you can - programatically drag down for automated USB reset. - - large power capacitors and LDO power. + There are two versions of very similar boards: One is red and one is + blue. See http://www.stm32duino.com/viewtopic.php?f=28&t=117 - Problems with the red board: + The Red Board: - - Silk screen is barely readable, the text is chopped off on some of - the pins - - USB connector only has two anchor points and it is directly soldered - on the surface - - Small reset button with hardly any resistance + Good things about the red board: -The Blue Board: + - 1.5k pull up resistor on the PA12 pin (USB D+) which you can + programatically drag down for automated USB reset. + - large power capacitors and LDO power. - Good things about the blue board: + Problems with the red board: - - Four soldered anchor point on the USB connector. What you can't tell - from this picture is that there is a notch in the pcb board and the USB - connector sits down inside it some. This provides some lateral stability - that takes some of the stress off the solder points. - - It has nice clear readable silkscreen printing. - - It also a larger reset button. + - Silk screen is barely readable, the text is chopped off on some of + the pins + - USB connector only has two anchor points and it is directly soldered + on the surface + - Small reset button with hardly any resistance - Problems with the blue board: + The Blue Board: - - Probably won't work as a USB device if it has a 10k pull-up on PA12. You - have to check the pull up on PA12 (USB D+). If it has a 10k pull-up - resistor, you will need to replace it with a 1.5k one to use the native - USB. - - Puny voltage regulator probably 100mA. + Good things about the blue board: - A schematic for the blue board is available here: - http://www.stm32duino.com/download/file.php?id=276 + - Four soldered anchor point on the USB connector. What you can't tell + from this picture is that there is a notch in the pcb board and the USB + connector sits down inside it some. This provides some lateral stability + that takes some of the stress off the solder points. + - It has nice clear readable silkscreen printing. + - It also a larger reset button. -Both Boards: + Problems with the blue board: - Nice features common to both: + - Probably won't work as a USB device if it has a 10k pull-up on PA12. You + have to check the pull up on PA12 (USB D+). If it has a 10k pull-up + resistor, you will need to replace it with a 1.5k one to use the native + USB. + - Puny voltage regulator probably 100mA. - - SWD pins broken out and easily connected (VCC, GND, SWDIO, SWCLK) - - USB 5V is broken out with easy access. - - User LED on PC13 - - Power LED - - You can probably use more flash (128k) than officially documented for - the chip (stm32f103c8t6 64k), I was able to load 115k of flash on mine - and it seemed to work. + A schematic for the blue board is available here: + http://www.stm32duino.com/download/file.php?id=276 - Problems with both boards: + Both Boards: - - No preloaded bootloader * to me this isn't really a problem as the - entire 64k of flash is available for use - - No user button + Nice features common to both: -This is the board pinout based on its form-factor for the Blue board: + - SWD pins broken out and easily connected (VCC, GND, SWDIO, SWCLK) + - USB 5V is broken out with easy access. + - User LED on PC13 + - Power LED + - You can probably use more flash (128k) than officially documented for + the chip (stm32f103c8t6 64k), I was able to load 115k of flash on mine + and it seemed to work. + + Problems with both boards: + + - No preloaded bootloader * to me this isn't really a problem as the + entire 64k of flash is available for use + - No user button + + This is the board pinout based on its form-factor for the Blue board: USB ___ @@ -94,25 +110,15 @@ This is the board pinout based on its form-factor for the Blue board: |3.3V VB| |_____________| -Contents -======== - - - LEDs - - UARTs - - Timer Inputs/Outputs - - Using 128KiB of Flash instead of 64KiB - - STM32F103 Minimum - specific Configuration Options - - Configurations - LEDs ==== -The STM32F103 Minimum board has only one software controllable LED. -This LED can be used by the board port when CONFIG_ARCH_LEDS option is -enabled. + The STM32F103 Minimum board has only one software controllable LED. + This LED can be used by the board port when CONFIG_ARCH_LEDS option is + enabled. -If enabled the LED is simply turned on when the board boots -succesfully, and is blinking on panic / assertion failed. + If enabled the LED is simply turned on when the board boots + succesfully, and is blinking on panic / assertion failed. UARTs ===== @@ -139,7 +145,7 @@ UARTs Default USART/UART Configuration -------------------------------- -USART1 (RX & TX only) is available through pins PA9 (TX) and PA10 (RX). + USART1 (RX & TX only) is available through pins PA9 (TX) and PA10 (RX). Timer Inputs/Outputs ==================== @@ -171,69 +177,104 @@ Timer Inputs/Outputs Using 128KiB of Flash instead of 64KiB ====================================== -Some people figured out that the STM32F103C8T6 has 128KiB of internal memory -instead of 64KiB as documented in the datasheet and reported by its internal -register. + Some people figured out that the STM32F103C8T6 has 128KiB of internal memory + instead of 64KiB as documented in the datasheet and reported by its internal + register. -In order to enable 128KiB you need modify the linker script to reflect this -new size. Open the configs/stm32f103-minimum/scripts/ld.script and replace: + In order to enable 128KiB you need modify the linker script to reflect this + new size. Open the configs/stm32f103-minimum/scripts/ld.script and replace: - flash (rx) : ORIGIN = 0x08000000, LENGTH = 64K + flash (rx) : ORIGIN = 0x08000000, LENGTH = 64K -with + with - flash (rx) : ORIGIN = 0x08000000, LENGTH = 128K + flash (rx) : ORIGIN = 0x08000000, LENGTH = 128K -Enable many NuttX features (ie. many filesystems and applications) to get a -large binary image with more than 64K. + Enable many NuttX features (ie. many filesystems and applications) to get a + large binary image with more than 64K. -We will use OpenOCD to write the firmware in the STM32F103C8T6 Flash. Use a -up to dated OpenOCD version (ie. openocd-0.9). + We will use OpenOCD to write the firmware in the STM32F103C8T6 Flash. Use a + up to dated OpenOCD version (ie. openocd-0.9). -You will need to create a copy of original openocd/scripts/target/stm32f1x.cfg -to openocd/scripts/target/stm32f103c8t6.cfg and edit the later file replacing: + You will need to create a copy of original openocd/scripts/target/stm32f1x.cfg + to openocd/scripts/target/stm32f103c8t6.cfg and edit the later file replacing: - flash bank $_FLASHNAME stm32f1x 0x08000000 0 0 0 $_TARGETNAME + flash bank $_FLASHNAME stm32f1x 0x08000000 0 0 0 $_TARGETNAME -with + with - flash bank $_FLASHNAME stm32f1x 0x08000000 0x20000 0 0 $_TARGETNAME + flash bank $_FLASHNAME stm32f1x 0x08000000 0x20000 0 0 $_TARGETNAME -We will use OpenOCD with STLink-V2 programmer, but it will work with other -programmers (JLink, Versaloon, or some based on FTDI FT232, etc). + We will use OpenOCD with STLink-V2 programmer, but it will work with other + programmers (JLink, Versaloon, or some based on FTDI FT232, etc). -Open a terminal and execute: + Open a terminal and execute: - $ sudo openocd -f interface/stlink-v2.cfg -f target/stm32f103c8t6.cfg + $ sudo openocd -f interface/stlink-v2.cfg -f target/stm32f103c8t6.cfg -Now in other terminal execute: + Now in other terminal execute: - $ telnet localhost 4444 + $ telnet localhost 4444 - Trying 127.0.0.1... - Connected to localhost. - Escape character is '^]'. - Open On-Chip Debugger + Trying 127.0.0.1... + Connected to localhost. + Escape character is '^]'. + Open On-Chip Debugger - > reset halt - stm32f1x.cpu: target state: halted - target halted due to debug-request, current mode: Thread - xPSR: 0x01000000 pc: 0x080003ac msp: 0x20000d78 + > reset halt + stm32f1x.cpu: target state: halted + target halted due to debug-request, current mode: Thread + xPSR: 0x01000000 pc: 0x080003ac msp: 0x20000d78 - > flash write_image erase nuttx.bin 0x08000000 - auto erase enabled - device id = 0x20036410 - ignoring flash probed value, using configured bank size - flash size = 128kbytes - stm32f1x.cpu: target state: halted - target halted due to breakpoint, current mode: Thread - xPSR: 0x61000000 pc: 0x2000003a msp: 0x20000d78 - wrote 92160 bytes from file nuttx.bin in 4.942194s (18.211 KiB/s) + > flash write_image erase nuttx.bin 0x08000000 + auto erase enabled + device id = 0x20036410 + ignoring flash probed value, using configured bank size + flash size = 128kbytes + stm32f1x.cpu: target state: halted + target halted due to breakpoint, current mode: Thread + xPSR: 0x61000000 pc: 0x2000003a msp: 0x20000d78 + wrote 92160 bytes from file nuttx.bin in 4.942194s (18.211 KiB/s) - > reset run - > exit + > reset run + > exit -Now NuttX should start normally. + Now NuttX should start normally. + +Quadrature Encoder: +=================== + + The nsh configuration has been used to test the Quadrture Encoder + (QEncoder, QE) with the following modifications to the configuration + file: + + - These setting enable support for the common QEncode upper half driver: + + CONFIG_SENSORS=y + CONFIG_QENCODER=y + + - This is a board setting that selected timer 4 for use with the + quadrature encode: + + CONFIG_STM32F103MINIMUM_QETIMER=4 + + - These settings enable the STM32 Quadrature encoder on timer 4: + + CONFIG_STM32_TIM4_CAP=y + CONFIG_STM32_TIM4_QE=y + CONFIG_STM32_TIM4_QECLKOUT=2800000 + CONFIG_STM32_QENCODER_FILTER=y + CONFIG_STM32_QENCODER_SAMPLE_EVENT_6=y + CONFIG_STM32_QENCODER_SAMPLE_FDTS_4=y + + - These settings enable the test case at apps/examples/qencoder: + + CONFIG_EXAMPLES_QENCODER=y + CONFIG_EXAMPLES_QENCODER_DELAY=100 + CONFIG_EXAMPLES_QENCODER_DEVPATH="/dev/qe0" + + In this configuration, the QEncoder inputs will be on the TIM4 inputs of + PB6 and PB7. STM32F103 Minimum - specific Configuration Options ================================================== @@ -406,21 +447,25 @@ STM32F103 Minimum - specific Configuration Options Configurations ============== -Each STM32F103 Minimum configuration is maintained in a sub-directory and -can be selected as follow: + Instantiating Configurations + ---------------------------- + Each STM32F103 Minimum configuration is maintained in a sub-directory and + can be selected as follow: cd tools ./configure.sh STM32F103 Minimum/ cd - . ./setenv.sh -If this is a Windows native build, then configure.bat should be used -instead of configure.sh: + If this is a Windows native build, then configure.bat should be used + instead of configure.sh: configure.bat STM32F103-Minimum\ -Where is one of the following: + Where is one of the following: + Configuration Directories + ------------------------- nsh: --- Configures the NuttShell (nsh) located at apps/examples/nsh. This diff --git a/configs/stm32f103-minimum/audio_tone/defconfig b/configs/stm32f103-minimum/audio_tone/defconfig index 492e93b565f..47bc80d08ff 100644 --- a/configs/stm32f103-minimum/audio_tone/defconfig +++ b/configs/stm32f103-minimum/audio_tone/defconfig @@ -945,7 +945,6 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/stm32f103-minimum/src/Makefile b/configs/stm32f103-minimum/src/Makefile index 367a1677e43..fd649cb44f2 100644 --- a/configs/stm32f103-minimum/src/Makefile +++ b/configs/stm32f103-minimum/src/Makefile @@ -73,6 +73,10 @@ ifeq ($(CONFIG_LCD_ST7567),y) CSRCS += stm32_lcd.c endif +ifeq ($(CONFIG_QENCODER),y) +CSRCS += stm32_qencoder.c +endif + ifeq ($(CONFIG_VEML6070),y) CSRCS += stm32_veml6070.c endif diff --git a/configs/stm32f103-minimum/src/stm32_bringup.c b/configs/stm32f103-minimum/src/stm32_bringup.c index b193c04ab0b..54e78b27f80 100644 --- a/configs/stm32f103-minimum/src/stm32_bringup.c +++ b/configs/stm32f103-minimum/src/stm32_bringup.c @@ -163,6 +163,18 @@ int stm32_bringup(void) } #endif +#ifdef CONFIG_QENCODER + /* Initialize and register the qencoder driver */ + + ret = stm32_qencoder_initialize("/dev/qe0", CONFIG_STM32F103MINIMUM_QETIMER); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to register the qencoder: %d\n", + ret); + } +#endif + #ifdef CONFIG_USERLED /* Register the LED driver */ diff --git a/configs/stm32f103-minimum/src/stm32_qencoder.c b/configs/stm32f103-minimum/src/stm32_qencoder.c new file mode 100644 index 00000000000..ae4508b02b3 --- /dev/null +++ b/configs/stm32f103-minimum/src/stm32_qencoder.c @@ -0,0 +1,80 @@ +/************************************************************************************ + * configs/stm32f103-minimum/src/stm32_qencoder.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "chip.h" +#include "up_arch.h" +#include "stm32_qencoder.h" +#include "stm32f103_minimum.h" + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: stm32_qencoder_initialize + * + * Description: + * All STM32 architectures must provide the following interface to work with + * examples/qencoder. + * + ************************************************************************************/ + +int stm32_qencoder_initialize(FAR const char *devpath, int timer) +{ + int ret; + + /* Initialize a quadrature encoder interface. */ + + sninfo("Initializing the quadrature encoder using TIM%d\n", timer); + ret = stm32_qeinitialize(devpath, timer); + if (ret < 0) + { + snerr("ERROR: stm32_qeinitialize failed: %d\n", ret); + } + + return ret; +} diff --git a/configs/stm32f429i-disco/extflash/defconfig b/configs/stm32f429i-disco/extflash/defconfig index 45d62cfe047..adb39d76a14 100644 --- a/configs/stm32f429i-disco/extflash/defconfig +++ b/configs/stm32f429i-disco/extflash/defconfig @@ -1022,7 +1022,6 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/stm32f429i-disco/lcd/defconfig b/configs/stm32f429i-disco/lcd/defconfig index 017587b2936..55c086a56c3 100644 --- a/configs/stm32f429i-disco/lcd/defconfig +++ b/configs/stm32f429i-disco/lcd/defconfig @@ -1070,7 +1070,6 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/stm32f429i-disco/ltdc/defconfig b/configs/stm32f429i-disco/ltdc/defconfig index eada5df1f99..f534914cda9 100644 --- a/configs/stm32f429i-disco/ltdc/defconfig +++ b/configs/stm32f429i-disco/ltdc/defconfig @@ -1088,7 +1088,6 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/stm32f429i-disco/nsh/defconfig b/configs/stm32f429i-disco/nsh/defconfig index 9941b7aa49e..aa843ace342 100644 --- a/configs/stm32f429i-disco/nsh/defconfig +++ b/configs/stm32f429i-disco/nsh/defconfig @@ -935,7 +935,6 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/stm32f429i-disco/nxwm/defconfig b/configs/stm32f429i-disco/nxwm/defconfig index 0a9414b9763..6c90c64117a 100644 --- a/configs/stm32f429i-disco/nxwm/defconfig +++ b/configs/stm32f429i-disco/nxwm/defconfig @@ -1141,7 +1141,6 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/stm32f429i-disco/usbmsc/defconfig b/configs/stm32f429i-disco/usbmsc/defconfig index 75fd641a7e2..fa1af2fa910 100644 --- a/configs/stm32f429i-disco/usbmsc/defconfig +++ b/configs/stm32f429i-disco/usbmsc/defconfig @@ -971,7 +971,6 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/stm32f429i-disco/usbnsh/defconfig b/configs/stm32f429i-disco/usbnsh/defconfig index f646ce371e9..aa1481a5e8d 100644 --- a/configs/stm32f429i-disco/usbnsh/defconfig +++ b/configs/stm32f429i-disco/usbnsh/defconfig @@ -985,7 +985,6 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/stm32f4discovery/elf/defconfig b/configs/stm32f4discovery/elf/defconfig index c2b11282d53..254c8c9fadf 100644 --- a/configs/stm32f4discovery/elf/defconfig +++ b/configs/stm32f4discovery/elf/defconfig @@ -930,7 +930,6 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set CONFIG_LIBC_ARCH_ELF=y # CONFIG_ARMV7M_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/stm32f4discovery/ipv6/defconfig b/configs/stm32f4discovery/ipv6/defconfig index 4ffc7411b70..297762a9b9a 100644 --- a/configs/stm32f4discovery/ipv6/defconfig +++ b/configs/stm32f4discovery/ipv6/defconfig @@ -1161,7 +1161,6 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/stm32f4discovery/netnsh/defconfig b/configs/stm32f4discovery/netnsh/defconfig index f797f4176f6..a7f1bfd9e9d 100644 --- a/configs/stm32f4discovery/netnsh/defconfig +++ b/configs/stm32f4discovery/netnsh/defconfig @@ -1165,7 +1165,6 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/stm32f4discovery/nsh/defconfig b/configs/stm32f4discovery/nsh/defconfig index 48d50e75921..f20f8922393 100644 --- a/configs/stm32f4discovery/nsh/defconfig +++ b/configs/stm32f4discovery/nsh/defconfig @@ -951,7 +951,6 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/stm32f4discovery/posix_spawn/defconfig b/configs/stm32f4discovery/posix_spawn/defconfig index e278e58698a..e25f358c9a3 100644 --- a/configs/stm32f4discovery/posix_spawn/defconfig +++ b/configs/stm32f4discovery/posix_spawn/defconfig @@ -930,7 +930,6 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set CONFIG_LIBC_ARCH_ELF=y # CONFIG_ARMV7M_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/stm32f746-ws/nsh/defconfig b/configs/stm32f746-ws/nsh/defconfig index 4c8131f4877..1aecbaa4f1b 100644 --- a/configs/stm32f746-ws/nsh/defconfig +++ b/configs/stm32f746-ws/nsh/defconfig @@ -862,7 +862,7 @@ CONFIG_FAT_DIRECT_RETRY=y # Memory Management # # CONFIG_MM_SMALL is not set -CONFIG_MM_REGIONS=2 +CONFIG_MM_REGIONS=3 # CONFIG_ARCH_HAVE_HEAP2 is not set CONFIG_GRAN=y # CONFIG_GRAN_SINGLE is not set @@ -912,7 +912,6 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set diff --git a/configs/stm32f746g-disco/nsh/defconfig b/configs/stm32f746g-disco/nsh/defconfig index e26a16f8abb..8d24e4b5ee9 100644 --- a/configs/stm32f746g-disco/nsh/defconfig +++ b/configs/stm32f746g-disco/nsh/defconfig @@ -732,7 +732,7 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue" # Memory Management # # CONFIG_MM_SMALL is not set -CONFIG_MM_REGIONS=2 +CONFIG_MM_REGIONS=3 # CONFIG_ARCH_HAVE_HEAP2 is not set # CONFIG_GRAN is not set diff --git a/configs/stm32l476-mdk/nsh/defconfig b/configs/stm32l476-mdk/nsh/defconfig index 4c6771b7c94..9ff2d597c4f 100644 --- a/configs/stm32l476-mdk/nsh/defconfig +++ b/configs/stm32l476-mdk/nsh/defconfig @@ -775,7 +775,6 @@ CONFIG_ARCH_LOWPUTC=y # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set diff --git a/configs/stm32l476vg-disco/nsh/defconfig b/configs/stm32l476vg-disco/nsh/defconfig index dbd3b006648..c98f47a46cf 100644 --- a/configs/stm32l476vg-disco/nsh/defconfig +++ b/configs/stm32l476vg-disco/nsh/defconfig @@ -825,7 +825,6 @@ CONFIG_ARCH_LOWPUTC=y # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set diff --git a/configs/twr-k64f120m/netnsh/defconfig b/configs/twr-k64f120m/netnsh/defconfig index ee8d78de968..d0b964f8ef2 100644 --- a/configs/twr-k64f120m/netnsh/defconfig +++ b/configs/twr-k64f120m/netnsh/defconfig @@ -16,7 +16,7 @@ CONFIG_HOST_LINUX=y # # Build Configuration # -CONFIG_APPS_DIR="../apps" +# CONFIG_APPS_DIR="../apps" CONFIG_BUILD_FLAT=y # CONFIG_BUILD_2PASS is not set @@ -43,56 +43,15 @@ CONFIG_INTELHEX_BINARY=y # Debug Options # CONFIG_DEBUG_ALERT=y -CONFIG_DEBUG_FEATURES=y - -# -# Debug SYSLOG Output Controls -# -CONFIG_DEBUG_ERROR=y -CONFIG_DEBUG_WARN=y -CONFIG_DEBUG_INFO=y -CONFIG_DEBUG_ASSERTIONS=y - -# -# Subsystem Debug Options -# -# CONFIG_DEBUG_BINFMT is not set -CONFIG_DEBUG_FS=y -CONFIG_DEBUG_FS_ERROR=y -CONFIG_DEBUG_FS_WARN=y -# CONFIG_DEBUG_FS_INFO is not set -# CONFIG_DEBUG_GRAPHICS is not set -# CONFIG_DEBUG_LIB is not set -# CONFIG_DEBUG_MM is not set -CONFIG_DEBUG_NET=y -CONFIG_DEBUG_NET_ERROR=y -CONFIG_DEBUG_NET_WARN=y -# CONFIG_DEBUG_NET_INFO is not set -# CONFIG_DEBUG_SCHED is not set - -# -# OS Function Debug Options -# -# CONFIG_DEBUG_IRQ is not set - -# -# Driver Debug Options -# -# CONFIG_DEBUG_LEDS is not set -# CONFIG_DEBUG_GPIO is not set -CONFIG_DEBUG_MEMCARD=y -CONFIG_DEBUG_MEMCARD_ERROR=y -CONFIG_DEBUG_MEMCARD_WARN=y -# CONFIG_DEBUG_MEMCARD_INFO is not set -# CONFIG_DEBUG_TIMER is not set +# CONFIG_DEBUG_FEATURES is not set CONFIG_ARCH_HAVE_STACKCHECK=y # CONFIG_STACK_COLORATION is not set # CONFIG_ARCH_HAVE_HEAPCHECK is not set -CONFIG_DEBUG_SYMBOLS=y +# CONFIG_DEBUG_SYMBOLS is not set CONFIG_ARCH_HAVE_CUSTOMOPT=y -CONFIG_DEBUG_NOOPT=y +# CONFIG_DEBUG_NOOPT is not set # CONFIG_DEBUG_CUSTOMOPT is not set -# CONFIG_DEBUG_FULLOPT is not set +CONFIG_DEBUG_FULLOPT=y # # System Type @@ -174,7 +133,6 @@ CONFIG_ARCH_HAVE_FPU=y # CONFIG_ARCH_HAVE_TRUSTZONE is not set CONFIG_ARM_HAVE_MPU_UNIFIED=y # CONFIG_ARM_MPU is not set -# CONFIG_DEBUG_HARDFAULT is not set # # ARMV7M Configuration Options @@ -545,10 +503,10 @@ CONFIG_DEV_NULL=y # CONFIG_PWM is not set # CONFIG_ARCH_HAVE_I2CRESET is not set # CONFIG_I2C is not set -# CONFIG_SPI is not set # CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set # CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set # CONFIG_ARCH_HAVE_SPI_BITORDER is not set +# CONFIG_SPI is not set # CONFIG_I2S is not set # @@ -609,11 +567,9 @@ CONFIG_NETDEVICES=y CONFIG_NETDEV_TELNET=y CONFIG_TELNET_RXBUFFER_SIZE=256 CONFIG_TELNET_TXBUFFER_SIZE=256 -# CONFIG_TELNET_DUMPBUFFER is not set # CONFIG_NETDEV_MULTINIC is not set CONFIG_ARCH_HAVE_NETDEV_STATISTICS=y # CONFIG_NETDEV_LATEINIT is not set -# CONFIG_NET_DUMPPACKET is not set # # External Ethernet MAC Device Support @@ -642,7 +598,6 @@ CONFIG_ETH0_PHY_KSZ8041=y # CONFIG_ETH0_PHY_LAN8740A is not set # CONFIG_ETH0_PHY_LAN8742A is not set # CONFIG_ETH0_PHY_DM9161 is not set -# CONFIG_NETDEV_PHY_DEBUG is not set # CONFIG_PIPES is not set # CONFIG_PM is not set # CONFIG_POWER is not set @@ -679,7 +634,6 @@ CONFIG_STANDARD_SERIAL=y # CONFIG_SERIAL_IFLOWCONTROL is not set # CONFIG_SERIAL_OFLOWCONTROL is not set # CONFIG_SERIAL_DMA is not set -# CONFIG_SERIAL_TIOCSERGSTRUCT is not set # CONFIG_ARCH_HAVE_SERIAL_TERMIOS is not set CONFIG_UART1_SERIAL_CONSOLE=y # CONFIG_OTHER_SERIAL_CONSOLE is not set @@ -779,8 +733,6 @@ CONFIG_NET_MAX_LISTENPORTS=20 CONFIG_NET_TCP_READAHEAD=y CONFIG_NET_TCP_WRITE_BUFFERS=y CONFIG_NET_TCP_NWRBCHAINS=8 -# CONFIG_NET_TCP_WRBUFFER_DEBUG is not set -# CONFIG_NET_TCP_WRBUFFER_DUMP is not set CONFIG_NET_TCP_RECVDELAY=0 # CONFIG_NET_TCPBACKLOG is not set # CONFIG_NET_SENDFILE is not set @@ -825,7 +777,6 @@ CONFIG_IOB_NBUFFERS=36 CONFIG_IOB_BUFSIZE=196 CONFIG_IOB_NCHAINS=8 CONFIG_IOB_THROTTLE=8 -# CONFIG_IOB_DEBUG is not set # CONFIG_NET_ARCH_INCR32 is not set # CONFIG_NET_ARCH_CHKSUM is not set # CONFIG_NET_STATISTICS is not set @@ -850,7 +801,6 @@ CONFIG_NET_HOSTNAME="TWRK64" # # CONFIG_DISABLE_MOUNTPOINT is not set CONFIG_FS_AUTOMOUNTER=y -CONFIG_FS_AUTOMOUNTER_DEBUG=y # CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set # CONFIG_PSEUDOFS_SOFTLINKS is not set CONFIG_FS_READABLE=y @@ -957,7 +907,6 @@ CONFIG_ARCH_LOWPUTC=y # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set @@ -1065,10 +1014,10 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # CONFIG_EXAMPLES_NRF24L01TERM is not set CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_NULL is not set +# CONFIG_EXAMPLES_NX is not set # CONFIG_EXAMPLES_NXFFS is not set # CONFIG_EXAMPLES_NXHELLO is not set # CONFIG_EXAMPLES_NXIMAGE is not set -# CONFIG_EXAMPLES_NX is not set # CONFIG_EXAMPLES_NXLINES is not set # CONFIG_EXAMPLES_NXTERM is not set # CONFIG_EXAMPLES_NXTEXT is not set @@ -1085,12 +1034,13 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_SLCD is not set # CONFIG_EXAMPLES_SMART is not set # CONFIG_EXAMPLES_SMP is not set +# CONFIG_EXAMPLES_STAT is not set # CONFIG_EXAMPLES_TCPECHO is not set # CONFIG_EXAMPLES_TELNETD is not set # CONFIG_EXAMPLES_TIFF is not set # CONFIG_EXAMPLES_TOUCHSCREEN is not set -# CONFIG_EXAMPLES_UDPBLASTER is not set # CONFIG_EXAMPLES_UDP is not set +# CONFIG_EXAMPLES_UDPBLASTER is not set # CONFIG_EXAMPLES_USBSERIAL is not set # CONFIG_EXAMPLES_USBTERM is not set # CONFIG_EXAMPLES_WATCHDOG is not set @@ -1252,7 +1202,6 @@ CONFIG_NSH_ARCHINIT=y # CONFIG_NSH_NETINIT=y # CONFIG_NSH_NETINIT_THREAD is not set -# CONFIG_NSH_NETINIT_DEBUG is not set # # IP Address Configuration diff --git a/configs/twr-k64f120m/nsh/defconfig b/configs/twr-k64f120m/nsh/defconfig index d02f96daf24..d819dfe55f9 100644 --- a/configs/twr-k64f120m/nsh/defconfig +++ b/configs/twr-k64f120m/nsh/defconfig @@ -16,7 +16,7 @@ CONFIG_HOST_LINUX=y # # Build Configuration # -CONFIG_APPS_DIR="../apps" +# CONFIG_APPS_DIR="../apps" CONFIG_BUILD_FLAT=y # CONFIG_BUILD_2PASS is not set @@ -43,52 +43,15 @@ CONFIG_INTELHEX_BINARY=y # Debug Options # CONFIG_DEBUG_ALERT=y -CONFIG_DEBUG_FEATURES=y - -# -# Debug SYSLOG Output Controls -# -CONFIG_DEBUG_ERROR=y -CONFIG_DEBUG_WARN=y -CONFIG_DEBUG_INFO=y -CONFIG_DEBUG_ASSERTIONS=y - -# -# Subsystem Debug Options -# -# CONFIG_DEBUG_BINFMT is not set -CONFIG_DEBUG_FS=y -CONFIG_DEBUG_FS_ERROR=y -CONFIG_DEBUG_FS_WARN=y -# CONFIG_DEBUG_FS_INFO is not set -# CONFIG_DEBUG_GRAPHICS is not set -# CONFIG_DEBUG_LIB is not set -# CONFIG_DEBUG_MM is not set -# CONFIG_DEBUG_SCHED is not set - -# -# OS Function Debug Options -# -# CONFIG_DEBUG_IRQ is not set - -# -# Driver Debug Options -# -# CONFIG_DEBUG_LEDS is not set -# CONFIG_DEBUG_GPIO is not set -CONFIG_DEBUG_MEMCARD=y -CONFIG_DEBUG_MEMCARD_ERROR=y -CONFIG_DEBUG_MEMCARD_WARN=y -# CONFIG_DEBUG_MEMCARD_INFO is not set -# CONFIG_DEBUG_TIMER is not set +# CONFIG_DEBUG_FEATURES is not set CONFIG_ARCH_HAVE_STACKCHECK=y # CONFIG_STACK_COLORATION is not set # CONFIG_ARCH_HAVE_HEAPCHECK is not set -CONFIG_DEBUG_SYMBOLS=y +# CONFIG_DEBUG_SYMBOLS is not set CONFIG_ARCH_HAVE_CUSTOMOPT=y -CONFIG_DEBUG_NOOPT=y +# CONFIG_DEBUG_NOOPT is not set # CONFIG_DEBUG_CUSTOMOPT is not set -# CONFIG_DEBUG_FULLOPT is not set +CONFIG_DEBUG_FULLOPT=y # # System Type @@ -170,7 +133,6 @@ CONFIG_ARCH_HAVE_FPU=y # CONFIG_ARCH_HAVE_TRUSTZONE is not set CONFIG_ARM_HAVE_MPU_UNIFIED=y # CONFIG_ARM_MPU is not set -# CONFIG_DEBUG_HARDFAULT is not set # # ARMV7M Configuration Options @@ -236,7 +198,8 @@ CONFIG_ARCH_FAMILY_K64=y CONFIG_KINETIS_HAVE_I2C1=y CONFIG_KINETIS_HAVE_I2C2=y # CONFIG_KINETIS_HAVE_I2C3 is not set -# CONFIG_KINETIS_HAVE_I2C4 is not set +CONFIG_KINETIS_HAVE_SPI1=y +CONFIG_KINETIS_HAVE_SPI2=y # CONFIG_KINETIS_TRACE is not set # CONFIG_KINETIS_FLEXBUS is not set # CONFIG_KINETIS_UART0 is not set @@ -266,6 +229,7 @@ CONFIG_KINETIS_SDHC=y # CONFIG_KINETIS_FTM0 is not set # CONFIG_KINETIS_FTM1 is not set # CONFIG_KINETIS_FTM2 is not set +# CONFIG_KINETIS_FTM3 is not set # CONFIG_KINETIS_LPTIMER is not set # CONFIG_KINETIS_RTC is not set # CONFIG_KINETIS_EWM is not set @@ -525,10 +489,10 @@ CONFIG_DEV_NULL=y # CONFIG_PWM is not set # CONFIG_ARCH_HAVE_I2CRESET is not set # CONFIG_I2C is not set -# CONFIG_SPI is not set # CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set # CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set # CONFIG_ARCH_HAVE_SPI_BITORDER is not set +# CONFIG_SPI is not set # CONFIG_I2S is not set # @@ -616,7 +580,6 @@ CONFIG_STANDARD_SERIAL=y # CONFIG_SERIAL_IFLOWCONTROL is not set # CONFIG_SERIAL_OFLOWCONTROL is not set # CONFIG_SERIAL_DMA is not set -# CONFIG_SERIAL_TIOCSERGSTRUCT is not set # CONFIG_ARCH_HAVE_SERIAL_TERMIOS is not set CONFIG_UART1_SERIAL_CONSOLE=y # CONFIG_OTHER_SERIAL_CONSOLE is not set @@ -676,7 +639,6 @@ CONFIG_SYSLOG_CONSOLE=y # # CONFIG_DISABLE_MOUNTPOINT is not set CONFIG_FS_AUTOMOUNTER=y -CONFIG_FS_AUTOMOUNTER_DEBUG=y # CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set # CONFIG_PSEUDOFS_SOFTLINKS is not set CONFIG_FS_READABLE=y @@ -747,13 +709,30 @@ CONFIG_MM_REGIONS=1 # # Standard C Library Options # + +# +# Standard C I/O +# +# CONFIG_STDIO_DISABLE_BUFFERING is not set CONFIG_STDIO_BUFFER_SIZE=64 CONFIG_STDIO_LINEBUFFER=y CONFIG_NUNGET_CHARS=2 -CONFIG_LIB_HOMEDIR="/" -# CONFIG_LIBC_DLLFCN is not set -# CONFIG_LIBC_MODLIB is not set +# CONFIG_NOPRINTF_FIELDWIDTH is not set +# CONFIG_LIBC_FLOATINGPOINT is not set +CONFIG_LIBC_LONG_LONG=y +# CONFIG_LIBC_SCANSET is not set +# CONFIG_EOL_IS_CR is not set +# CONFIG_EOL_IS_LF is not set +# CONFIG_EOL_IS_BOTH_CRLF is not set +CONFIG_EOL_IS_EITHER_CRLF=y +# CONFIG_MEMCPY_VIK is not set # CONFIG_LIBM is not set + +# +# Architecture-Specific Support +# +CONFIG_ARCH_LOWPUTC=y +# CONFIG_ARCH_ROMGETC is not set # CONFIG_LIBC_ARCH_MEMCPY is not set # CONFIG_LIBC_ARCH_MEMCMP is not set # CONFIG_LIBC_ARCH_MEMMOVE is not set @@ -764,41 +743,64 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_ARCH_STRNCPY is not set # CONFIG_LIBC_ARCH_STRLEN is not set # CONFIG_LIBC_ARCH_STRNLEN is not set -# CONFIG_LIBC_ARCH_BZERO is not set # CONFIG_LIBC_ARCH_ELF is not set # CONFIG_ARMV7M_MEMCPY is not set -# CONFIG_NOPRINTF_FIELDWIDTH is not set -# CONFIG_LIBC_FLOATINGPOINT is not set -CONFIG_LIBC_LONG_LONG=y -# CONFIG_LIBC_SCANSET is not set -# CONFIG_LIBC_IOCTL_VARIADIC is not set -# CONFIG_LIBC_WCHAR is not set -# CONFIG_LIBC_LOCALE is not set + +# +# stdlib Options +# CONFIG_LIB_RAND_ORDER=1 -# CONFIG_EOL_IS_CR is not set -# CONFIG_EOL_IS_LF is not set -# CONFIG_EOL_IS_BOTH_CRLF is not set -CONFIG_EOL_IS_EITHER_CRLF=y +CONFIG_LIB_HOMEDIR="/" +CONFIG_LIBC_TMPDIR="/tmp" +CONFIG_LIBC_MAX_TMPFILE=32 + +# +# Program Execution Options +# # CONFIG_LIBC_EXECFUNCS is not set CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=1024 CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=2048 + +# +# errno Decode Support +# # CONFIG_LIBC_STRERROR is not set # CONFIG_LIBC_PERROR_STDOUT is not set -CONFIG_LIBC_TMPDIR="/tmp" -CONFIG_LIBC_MAX_TMPFILE=32 -CONFIG_ARCH_LOWPUTC=y + +# +# memcpy/memset Options +# +# CONFIG_MEMSET_OPTSPEED is not set +# CONFIG_LIBC_DLLFCN is not set +# CONFIG_LIBC_MODLIB is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set + +# +# Time/Time Zone Support +# # CONFIG_LIBC_LOCALTIME is not set # CONFIG_TIME_EXTENDED is not set -CONFIG_LIB_SENDFILE_BUFSIZE=512 -# CONFIG_ARCH_ROMGETC is not set -# CONFIG_MEMCPY_VIK is not set -# CONFIG_MEMSET_OPTSPEED is not set CONFIG_ARCH_HAVE_TLS=y + +# +# Thread Local Storage (TLS) +# # CONFIG_TLS is not set + +# +# Network-Related Options +# # CONFIG_LIBC_IPv4_ADDRCONV is not set # CONFIG_LIBC_IPv6_ADDRCONV is not set # CONFIG_LIBC_NETDB is not set + +# +# NETDB Support +# # CONFIG_NETDB_HOSTFILE is not set +# CONFIG_LIBC_IOCTL_VARIADIC is not set +CONFIG_LIB_SENDFILE_BUFSIZE=512 # # Non-standard Library Support @@ -846,10 +848,10 @@ CONFIG_ARCH_HAVE_TLS=y # CONFIG_EXAMPLES_NRF24L01TERM is not set CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_NULL is not set +# CONFIG_EXAMPLES_NX is not set # CONFIG_EXAMPLES_NXFFS is not set # CONFIG_EXAMPLES_NXHELLO is not set # CONFIG_EXAMPLES_NXIMAGE is not set -# CONFIG_EXAMPLES_NX is not set # CONFIG_EXAMPLES_NXLINES is not set # CONFIG_EXAMPLES_NXTERM is not set # CONFIG_EXAMPLES_NXTEXT is not set @@ -866,6 +868,7 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_SLCD is not set # CONFIG_EXAMPLES_SMART is not set # CONFIG_EXAMPLES_SMP is not set +# CONFIG_EXAMPLES_STAT is not set # CONFIG_EXAMPLES_TCPECHO is not set # CONFIG_EXAMPLES_TELNETD is not set # CONFIG_EXAMPLES_TIFF is not set diff --git a/drivers/Kconfig b/drivers/Kconfig index 740602b9f25..6dc2c875a86 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -337,14 +337,6 @@ if I2C source drivers/i2c/Kconfig endif -menuconfig SPI - bool "SPI Driver Support" - default n - ---help--- - This selection enables selection of common SPI options. This option - should be enabled by all platforms that support SPI interfaces. - See include/nuttx/spi/spi.h for further SPI driver information. - source drivers/spi/Kconfig menuconfig I2S diff --git a/drivers/audio/Kconfig b/drivers/audio/Kconfig index 20664dbe2b3..ade8bc93756 100644 --- a/drivers/audio/Kconfig +++ b/drivers/audio/Kconfig @@ -36,11 +36,11 @@ config AUDIO_I2SCHAR_TXTIMEOUT endif # AUDIO_I2SCHAR config AUDIO_TONE - bool "Audio Tone Generator using PWM" - default n - depends on PWM && AUDIO_DEVICES - ---help--- - This driver enables the Audio Tone Generator for NuttX. + bool "Audio Tone Generator using PWM" + default n + depends on PWM && AUDIO_DEVICES + ---help--- + This driver enables the Audio Tone Generator for NuttX. if AUDIO_TONE diff --git a/drivers/audio/tone.c b/drivers/audio/tone.c index 93d5324e902..f9b5393f73b 100644 --- a/drivers/audio/tone.c +++ b/drivers/audio/tone.c @@ -94,6 +94,9 @@ struct tone_upperhalf_s { uint8_t crefs; /* The number of times the device has been * opened */ +#ifdef CONFIG_PWM_MULTICHAN + uint8_t channel; /* Output channel that drives the tone. */ +#endif volatile bool started; /* True: pulsed output is being generated */ sem_t exclsem; /* Supports mutual exclusion */ struct pwm_info_s tone; /* Pulsed output for Audio Tone */ @@ -146,6 +149,19 @@ static bool g_repeat; * Private Function Prototypes ****************************************************************************/ +static void oneshot_callback(FAR struct oneshot_lowerhalf_s *lower, + FAR void *arg); +static uint32_t note_duration(FAR uint32_t *silence, uint32_t note_length, + uint32_t dots); +static uint32_t rest_duration(uint32_t rest_length, uint32_t dots); +static void start_note(FAR struct tone_upperhalf_s *upper, uint8_t note); +static void stop_note(FAR struct tone_upperhalf_s *upper); +static void start_tune(FAR struct tone_upperhalf_s *upper, const char *tune); +static void next_note(FAR struct tone_upperhalf_s *upper); +static int next_char(void); +static uint8_t next_number(void); +static uint8_t next_dots(void); + static int tone_open(FAR struct file *filep); static int tone_close(FAR struct file *filep); static ssize_t tone_read(FAR struct file *filep, FAR char *buffer, @@ -153,10 +169,6 @@ static ssize_t tone_read(FAR struct file *filep, FAR char *buffer, static ssize_t tone_write(FAR struct file *filep, FAR const char *buffer, size_t buflen); -static int next_char(void); -static uint8_t next_number(void); -static uint8_t next_dots(void); -static void next_note(FAR struct tone_upperhalf_s *upper); /**************************************************************************** * Private Data @@ -294,12 +306,17 @@ static void start_note(FAR struct tone_upperhalf_s *upper, uint8_t note) { FAR struct pwm_lowerhalf_s *tone = upper->devtone; - upper->tone.frequency = g_notes_freq[note - 1]; - upper->tone.duty = 50; + upper->tone.frequency = g_notes_freq[note - 1]; +#ifdef CONFIG_PWM_MULTICHAN + upper->tone.channels[0].channel = upper->channel; + upper->tone.channels[0].duty = b16HALF; +#else + upper->tone.duty = b16HALF; +#endif + + /* REVISIT: Should check the return value */ tone->ops->start(tone, &upper->tone); - - return; } /**************************************************************************** @@ -311,8 +328,6 @@ static void stop_note(FAR struct tone_upperhalf_s *upper) FAR struct pwm_lowerhalf_s *tone = upper->devtone; tone->ops->stop(tone); - - return; } /**************************************************************************** @@ -520,7 +535,6 @@ static void next_note(FAR struct tone_upperhalf_s *upper) ts.tv_nsec = (unsigned long)nsec; ONESHOT_START(upper->oneshot, oneshot_callback, upper, &ts); - return; /* Change tempo */ @@ -648,7 +662,6 @@ static void next_note(FAR struct tone_upperhalf_s *upper) /* And arrange a callback when the note should stop */ ONESHOT_START(upper->oneshot, oneshot_callback, upper, &ts); - return; /* Tune looks bad (unexpected EOF, bad character, etc.) */ @@ -925,10 +938,15 @@ static ssize_t tone_write(FAR struct file *filep, FAR const char *buffer, ****************************************************************************/ int tone_register(FAR const char *path, FAR struct pwm_lowerhalf_s *tone, +#ifdef CONFIG_PWM_MULTICHAN + int channel, +#endif FAR struct oneshot_lowerhalf_s *oneshot) { FAR struct tone_upperhalf_s *upper; + DEBUGASSERT(path != NULL && tone != NULL); + /* Allocate the upper-half data structure */ upper = @@ -947,6 +965,9 @@ int tone_register(FAR const char *path, FAR struct pwm_lowerhalf_s *tone, sem_init(&upper->exclsem, 0, 1); upper->devtone = tone; upper->oneshot = oneshot; +#ifdef CONFIG_PWM_MULTICHAN + upper->channel = (uint8_t)channel; +#endif /* Register the PWM device */ diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 177d863ee2c..c8bd5c72328 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -15,6 +15,14 @@ config ARCH_HAVE_SPI_BITORDER bool default n +menuconfig SPI + bool "SPI Driver Support" + default n + ---help--- + This selection enables selection of common SPI options. This option + should be enabled by all platforms that support SPI interfaces. + See include/nuttx/spi/spi.h for further SPI driver information. + if SPI config SPI_SLAVE diff --git a/fs/vfs/fs_fstatfs.c b/fs/vfs/fs_fstatfs.c index cdeba3c4570..207311ea470 100644 --- a/fs/vfs/fs_fstatfs.c +++ b/fs/vfs/fs_fstatfs.c @@ -79,7 +79,7 @@ int fstatfs(int fd, FAR struct statfs *buf) if ((unsigned int)fd >= CONFIG_NFILE_DESCRIPTORS) { - /* No networking... it is a bad descriptor in any event */ + /* It is a bad, out-of-range descriptor */ set_errno(EBADF); return ERROR; @@ -103,11 +103,20 @@ int fstatfs(int fd, FAR struct statfs *buf) inode = filep->f_inode; DEBUGASSERT(inode != NULL); + /* Check if the file is open */ + + if (inode == NULL) + { + /* The descriptor does not refer to an open file. */ + + ret = -EBADF; + } + else +#ifndef CONFIG_DISABLE_MOUNTPOINT /* The way we handle the stat depends on the type of inode that we * are dealing with. */ -#ifndef CONFIG_DISABLE_MOUNTPOINT if (INODE_IS_MOUNTPT(inode)) { /* The node is a file system mointpoint. Verify that the mountpoint diff --git a/fs/vfs/fs_read.c b/fs/vfs/fs_read.c index 6da412c3793..b00616682a0 100644 --- a/fs/vfs/fs_read.c +++ b/fs/vfs/fs_read.c @@ -92,7 +92,7 @@ ssize_t file_read(FAR struct file *filep, FAR void *buf, size_t nbytes) * method? */ - else if (inode && inode->u.i_ops && inode->u.i_ops->read) + else if (inode != NULL && inode->u.i_ops && inode->u.i_ops->read) { /* Yes.. then let it perform the read. NOTE that for the case of the * mountpoint, we depend on the read methods being identical in diff --git a/include/cxx/cstring b/include/cxx/cstring index 7fca19c45a7..038080e75d0 100644 --- a/include/cxx/cstring +++ b/include/cxx/cstring @@ -87,6 +87,11 @@ namespace std // Declared in legacy strings.h + using ::bcmp; + using ::bcopy; + using ::bzero; + using ::index; + using ::rindex; using ::ffs; using ::strcasecmp; using ::strncasecmp; diff --git a/include/nuttx/audio/tone.h b/include/nuttx/audio/tone.h index 7f15dc69548..e9a9c0059ac 100644 --- a/include/nuttx/audio/tone.h +++ b/include/nuttx/audio/tone.h @@ -1,7 +1,7 @@ /**************************************************************************** * include/nuttx/audio/tone.h * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Copyright (C) 2016-2017 Gregory Nutt. All rights reserved. * Author: Alan Carvalho de Assis * * Redistribution and use in source and binary forms, with or without @@ -76,6 +76,9 @@ extern "C" * filesystem. The recommended convention is to name all PWM drivers * as "/dev/tone0", "/dev/tone1", etc. where the driver path * differs only in the "minor" number at the end of the device name. + * channel - The the PWM peripheral supports multiple output channels, then + * this value must be provided to indicate the output channel that drives + * the tone. * tone - A pointer to an instance of lower half PWM driver tone. This * instance will be bound to the Audio Tone driver and must persists as * long as that driver persists. @@ -86,6 +89,9 @@ extern "C" ****************************************************************************/ int tone_register(FAR const char *path, FAR struct pwm_lowerhalf_s *tone, +#ifdef CONFIG_PWM_MULTICHAN + int channel, +#endif FAR struct oneshot_lowerhalf_s *oneshot); #undef EXTERN diff --git a/include/nuttx/drivers/pwm.h b/include/nuttx/drivers/pwm.h index 7cf80b0d7b3..eddea5804e2 100644 --- a/include/nuttx/drivers/pwm.h +++ b/include/nuttx/drivers/pwm.h @@ -66,12 +66,16 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ + /* Configuration ************************************************************/ /* CONFIG_PWM - Enables because PWM driver support * CONFIG_PWM_PULSECOUNT - Some hardware will support generation of a fixed * number of pulses. This might be used, for example to support a stepper * motor. If the hardware will support a fixed pulse count, then this * configuration should be set to enable the capability. + * CONFIG_PWM_MULTICHAN - Enables support for multiple output channels per + * timer. If selected, then CONFIG_PWM_NCHANNELS must be provided to + * indicated the maximum number of supported PWM output channels. * CONFIG_DEBUG_PWM_INFO - This will generate output that can be use to * debug the PWM driver. */ @@ -122,6 +126,10 @@ * Public Types ****************************************************************************/ +/* If the PWM peripheral supports multiple output channels, then this + * structure describes the output state on one channel. + */ + #ifdef CONFIG_PWM_MULTICHAN struct pwm_chan_s { @@ -135,8 +143,11 @@ struct pwm_chan_s struct pwm_info_s { uint32_t frequency; /* Frequency of the pulse train */ + #ifdef CONFIG_PWM_MULTICHAN + /* Per-channel output state */ struct pwm_chan_s channels[CONFIG_PWM_NCHANNELS]; + #else ub16_t duty; /* Duty of the pulse train, "1"-to-"0" duration. * Maximum: 65535/65536 (0x0000ffff) @@ -145,7 +156,7 @@ struct pwm_info_s uint32_t count; /* The number of pulse to generate. 0 means to * generate an indefinite number of pulses */ # endif -#endif +#endif /* CONFIG_PWM_MULTICHAN */ }; /* This structure is a set a callback functions used to call from the upper- @@ -184,7 +195,7 @@ struct pwm_ops_s FAR const struct pwm_info_s *info); #endif - /* Stop the pulsed output and reset the timer resources*/ + /* Stop the pulsed output and reset the timer resources */ CODE int (*stop)(FAR struct pwm_lowerhalf_s *dev); diff --git a/include/strings.h b/include/strings.h index bff724d9ba3..4b7fc439da4 100644 --- a/include/strings.h +++ b/include/strings.h @@ -47,20 +47,24 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -/* Compatibility definitions */ -#define bcmp(b1,b2,len) memcmp(b1,b2,(size_t)len) -#define bcopy(b1,b2,len) (void)memmove(b2,b1,len) +#if !defined(CONFIG_HAVE_INLINE) && !defined(__cplusplus) +/* Compatibility definitions + * + * Marked LEGACY in Open Group Base Specifications Issue 6/IEEE Std 1003.1-2004 + * Removed from Open Group Base Specifications Issue 7/IEEE Std 1003.1-2008 + */ -#ifndef CONFIG_LIBC_ARCH_BZERO -# define bzero(s,n) (void)memset(s,0,n) -#endif +# define bcmp(b1,b2,len) memcmp(b1,b2,(size_t)len) +# define bcopy(b1,b2,len) (void)memmove(b2,b1,len) +# define bzero(s,n) (void)memset(s,0,n) +# define index(s,c) strchr(s,c) +# define rindex(s,c) strrchr(s,c) -#define index(s,c) strchr(s,c) -#define rindex(s,c) strrchr(s,c) +#endif /* !CONFIG_HAVE_INLINE && !__cplusplus */ /**************************************************************************** - * Public Function Prototypes + * Inline Functions ****************************************************************************/ #undef EXTERN @@ -72,6 +76,43 @@ extern "C" #define EXTERN extern #endif +#if defined(CONFIG_HAVE_INLINE) || defined(__cplusplus) +/* Compatibility inline functions. + * + * Marked LEGACY in Open Group Base Specifications Issue 6/IEEE Std 1003.1-2004 + * Removed from Open Group Base Specifications Issue 7/IEEE Std 1003.1-2008 + */ + +static inline int bcmp(FAR const void *b1, FAR const void *b2, size_t len) +{ + return memcmp(b1, b2, len); +} + +static inline void bcopy(FAR const void *b1, FAR void *b2, size_t len) +{ + (void)memmove(b2, b1, len); +} + +static inline void bzero(FAR void *s, size_t len) +{ + (void)memset(s, 0, len); +} + +static inline FAR char *index(FAR const char *s, int c) +{ + return strchr(s, c); +} + +static inline FAR char *rindex(FAR const char *s, int c) +{ + return strrchr(s, c); +} +#endif /* CONFIG_HAVE_INLINE || __cplusplus */ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + int ffs(int j); int strcasecmp(FAR const char *, FAR const char *); int strncasecmp(FAR const char *, FAR const char *, size_t); diff --git a/libc/machine/Kconfig b/libc/machine/Kconfig index 693ede6a7f3..cd5c2905d2f 100644 --- a/libc/machine/Kconfig +++ b/libc/machine/Kconfig @@ -84,10 +84,6 @@ config LIBC_ARCH_STRNLEN bool default n -config LIBC_ARCH_BZERO - bool - default n - config LIBC_ARCH_ELF bool default n diff --git a/libc/string/lib_strcasestr.c b/libc/string/lib_strcasestr.c index ab8df1eede2..e7ab021ffad 100644 --- a/libc/string/lib_strcasestr.c +++ b/libc/string/lib_strcasestr.c @@ -1,7 +1,7 @@ /**************************************************************************** - * libc/string/lib_strstr.c + * libc/string/lib_strcasestr.c * - * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2012, 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use str source and binary forms, with or without @@ -40,6 +40,7 @@ #include #include +#include #include /**************************************************************************** diff --git a/sched/pthread/pthread_mutexlock.c b/sched/pthread/pthread_mutexlock.c index ebd650df6fb..f94890505df 100644 --- a/sched/pthread/pthread_mutexlock.c +++ b/sched/pthread/pthread_mutexlock.c @@ -150,7 +150,7 @@ int pthread_mutex_lock(FAR pthread_mutex_t *mutex) ret = pthread_takesemaphore((FAR sem_t *)&mutex->sem); - /* If we succussfully obtained the semaphore, then indicate + /* If we successfully obtained the semaphore, then indicate * that we own it. */