diff --git a/arch/arm/src/imx6/Make.defs b/arch/arm/src/imx6/Make.defs index e7aded5a4e8..43771dc63ec 100644 --- a/arch/arm/src/imx6/Make.defs +++ b/arch/arm/src/imx6/Make.defs @@ -132,4 +132,5 @@ CHIP_ASRCS = # i.MX6-specific C source files -CHIP_CSRCS = imx_boot.c imx_memorymap.c imx_irq.c # imx_serial.c +CHIP_CSRCS = imx_boot.c imx_memorymap.c imx_irq.c +CHIP_CSRCS = imx_gpio.c # imx_serial.c diff --git a/arch/arm/src/imx6/chip/imx_gpio.h b/arch/arm/src/imx6/chip/imx_gpio.h index b9d0e2755ca..c4672a03da0 100644 --- a/arch/arm/src/imx6/chip/imx_gpio.h +++ b/arch/arm/src/imx6/chip/imx_gpio.h @@ -57,79 +57,88 @@ /* GPIO Register Offsets ************************************************************/ -#define GPIO_DR_OFFSET 0x0000 /* Data Register */ -#define GPIO_GDIR_OFFSET 0x0004 /* Data Direction Register */ -#define GPIO_PSR_OFFSET 0x0008 /* Pad Status Register */ -#define GPIO_ICR1_OFFSET 0x000c /* Interrupt Configuration Register 1 */ -#define GPIO_ICR2_OFFSET 0x0010 /* Interrupt Configuration Register 2 */ -#define GPIO_IMR_OFFSET 0x0014 /* Interrupt Mask Register */ -#define GPIO_ISR_OFFSET 0x0018 /* Interrupt Status Register */ -#define GPIO_EDGE_OFFSET 0x001c /* Interrupt Status Register */ +#define IMX_GPIO_DR_OFFSET 0x0000 /* Data Register */ +#define IMX_GPIO_GDIR_OFFSET 0x0004 /* Data Direction Register */ +#define IMX_GPIO_PSR_OFFSET 0x0008 /* Pad Status Register */ +#define IMX_GPIO_ICR1_OFFSET 0x000c /* Interrupt Configuration Register 1 */ +#define IMX_GPIO_ICR2_OFFSET 0x0010 /* Interrupt Configuration Register 2 */ +#define IMX_GPIO_IMR_OFFSET 0x0014 /* Interrupt Mask Register */ +#define IMX_GPIO_ISR_OFFSET 0x0018 /* Interrupt Status Register */ +#define IMX_GPIO_EDGE_OFFSET 0x001c /* Interrupt Status Register */ /* GPIO Register Addresses **********************************************************/ -#define GPIO1_DR (IMX_GPIO1_VBASE+GPIO_DR_OFFSET) -#define GPIO1_GDIR (IMX_GPIO1_VBASE+GPIO_GDIR_OFFSET) -#define GPIO1_PSR (IMX_GPIO1_VBASE+GPIO_PSR_OFFSET) -#define GPIO1_ICR1 (IMX_GPIO1_VBASE+GPIO_ICR1_OFFSET) -#define GPIO1_ICR2 (IMX_GPIO1_VBASE+GPIO_ICR2_OFFSET) -#define GPIO1_IMR (IMX_GPIO1_VBASE+GPIO_IMR_OFFSET) -#define GPIO1_ISR (IMX_GPIO1_VBASE+GPIO_ISR_OFFSET) -#define GPIO1_EDGE (IMX_GPIO1_VBASE+GPIO_EDGE_OFFSET) +#define IMX_GPIO_DR(n) (IMX_GPIO_VBASE(n)+IMX_GPIO_DR_OFFSET) +#define IMX_GPIO_GDIR(n) (IMX_GPIO_VBASE(n)+IMX_GPIO_GDIR_OFFSET) +#define IMX_GPIO_PSR(n) (IMX_GPIO_VBASE(n)+IMX_GPIO_PSR_OFFSET) +#define IMX_GPIO_ICR1(n) (IMX_GPIO_VBASE(n)+IMX_GPIO_ICR1_OFFSET) +#define IMX_GPIO_ICR2(n) (IMX_GPIO_VBASE(n)+IMX_GPIO_ICR2_OFFSET) +#define IMX_GPIO_IMR(n) (IMX_GPIO_VBASE(n)+IMX_GPIO_IMR_OFFSET) +#define IMX_GPIO_ISR(n) (IMX_GPIO_VBASE(n)+IMX_GPIO_ISR_OFFSET) +#define IMX_GPIO_EDGE(n) (IMX_GPIO_VBASE(n)+IMX_GPIO_EDGE_OFFSET) -#define GPIO2_DR (IMX_GPIO2_VBASE+GPIO_DR_OFFSET) -#define GPIO2_GDIR (IMX_GPIO2_VBASE+GPIO_GDIR_OFFSET) -#define GPIO2_PSR (IMX_GPIO2_VBASE+GPIO_PSR_OFFSET) -#define GPIO2_ICR1 (IMX_GPIO2_VBASE+GPIO_ICR1_OFFSET) -#define GPIO2_ICR2 (IMX_GPIO2_VBASE+GPIO_ICR2_OFFSET) -#define GPIO2_IMR (IMX_GPIO2_VBASE+GPIO_IMR_OFFSET) -#define GPIO2_ISR (IMX_GPIO2_VBASE+GPIO_ISR_OFFSET) -#define GPIO2_EDGE (IMX_GPIO2_VBASE+GPIO_EDGE_OFFSET) +#define IMX_GPIO1_DR (IMX_GPIO1_VBASE+IMX_GPIO_DR_OFFSET) +#define IMX_GPIO1_GDIR (IMX_GPIO1_VBASE+IMX_GPIO_GDIR_OFFSET) +#define IMX_GPIO1_PSR (IMX_GPIO1_VBASE+IMX_GPIO_PSR_OFFSET) +#define IMX_GPIO1_ICR1 (IMX_GPIO1_VBASE+IMX_GPIO_ICR1_OFFSET) +#define IMX_GPIO1_ICR2 (IMX_GPIO1_VBASE+IMX_GPIO_ICR2_OFFSET) +#define IMX_GPIO1_IMR (IMX_GPIO1_VBASE+IMX_GPIO_IMR_OFFSET) +#define IMX_GPIO1_ISR (IMX_GPIO1_VBASE+IMX_GPIO_ISR_OFFSET) +#define IMX_GPIO1_EDGE (IMX_GPIO1_VBASE+IMX_GPIO_EDGE_OFFSET) -#define GPIO3_DR (IMX_GPIO3_VBASE+GPIO_DR_OFFSET) -#define GPIO3_GDIR (IMX_GPIO3_VBASE+GPIO_GDIR_OFFSET) -#define GPIO3_PSR (IMX_GPIO3_VBASE+GPIO_PSR_OFFSET) -#define GPIO3_ICR1 (IMX_GPIO3_VBASE+GPIO_ICR1_OFFSET) -#define GPIO3_ICR2 (IMX_GPIO3_VBASE+GPIO_ICR2_OFFSET) -#define GPIO3_IMR (IMX_GPIO3_VBASE+GPIO_IMR_OFFSET) -#define GPIO3_ISR (IMX_GPIO3_VBASE+GPIO_ISR_OFFSET) -#define GPIO3_EDGE (IMX_GPIO3_VBASE+GPIO_EDGE_OFFSET) +#define IMX_GPIO2_DR (IMX_GPIO2_VBASE+IMX_GPIO_DR_OFFSET) +#define IMX_GPIO2_GDIR (IMX_GPIO2_VBASE+IMX_GPIO_GDIR_OFFSET) +#define IMX_GPIO2_PSR (IMX_GPIO2_VBASE+IMX_GPIO_PSR_OFFSET) +#define IMX_GPIO2_ICR1 (IMX_GPIO2_VBASE+IMX_GPIO_ICR1_OFFSET) +#define IMX_GPIO2_ICR2 (IMX_GPIO2_VBASE+IMX_GPIO_ICR2_OFFSET) +#define IMX_GPIO2_IMR (IMX_GPIO2_VBASE+IMX_GPIO_IMR_OFFSET) +#define IMX_GPIO2_ISR (IMX_GPIO2_VBASE+IMX_GPIO_ISR_OFFSET) +#define IMX_GPIO2_EDGE (IMX_GPIO2_VBASE+IMX_GPIO_EDGE_OFFSET) -#define GPIO4_DR (IMX_GPIO4_VBASE+GPIO_DR_OFFSET) -#define GPIO4_GDIR (IMX_GPIO4_VBASE+GPIO_GDIR_OFFSET) -#define GPIO4_PSR (IMX_GPIO4_VBASE+GPIO_PSR_OFFSET) -#define GPIO4_ICR1 (IMX_GPIO4_VBASE+GPIO_ICR1_OFFSET) -#define GPIO4_ICR2 (IMX_GPIO4_VBASE+GPIO_ICR2_OFFSET) -#define GPIO4_IMR (IMX_GPIO4_VBASE+GPIO_IMR_OFFSET) -#define GPIO4_ISR (IMX_GPIO4_VBASE+GPIO_ISR_OFFSET) -#define GPIO4_EDGE (IMX_GPIO4_VBASE+GPIO_EDGE_OFFSET) +#define IMX_GPIO3_DR (IMX_GPIO3_VBASE+IMX_GPIO_DR_OFFSET) +#define IMX_GPIO3_GDIR (IMX_GPIO3_VBASE+IMX_GPIO_GDIR_OFFSET) +#define IMX_GPIO3_PSR (IMX_GPIO3_VBASE+IMX_GPIO_PSR_OFFSET) +#define IMX_GPIO3_ICR1 (IMX_GPIO3_VBASE+IMX_GPIO_ICR1_OFFSET) +#define IMX_GPIO3_ICR2 (IMX_GPIO3_VBASE+IMX_GPIO_ICR2_OFFSET) +#define IMX_GPIO3_IMR (IMX_GPIO3_VBASE+IMX_GPIO_IMR_OFFSET) +#define IMX_GPIO3_ISR (IMX_GPIO3_VBASE+IMX_GPIO_ISR_OFFSET) +#define IMX_GPIO3_EDGE (IMX_GPIO3_VBASE+IMX_GPIO_EDGE_OFFSET) -#define GPIO5_DR (IMX_GPIO5_VBASE+GPIO_DR_OFFSET) -#define GPIO5_GDIR (IMX_GPIO5_VBASE+GPIO_GDIR_OFFSET) -#define GPIO5_PSR (IMX_GPIO5_VBASE+GPIO_PSR_OFFSET) -#define GPIO5_ICR1 (IMX_GPIO5_VBASE+GPIO_ICR1_OFFSET) -#define GPIO5_ICR2 (IMX_GPIO5_VBASE+GPIO_ICR2_OFFSET) -#define GPIO5_IMR (IMX_GPIO5_VBASE+GPIO_IMR_OFFSET) -#define GPIO5_ISR (IMX_GPIO5_VBASE+GPIO_ISR_OFFSET) -#define GPIO5_EDGE (IMX_GPIO5_VBASE+GPIO_EDGE_OFFSET) +#define IMX_GPIO4_DR (IMX_GPIO4_VBASE+IMX_GPIO_DR_OFFSET) +#define IMX_GPIO4_GDIR (IMX_GPIO4_VBASE+IMX_GPIO_GDIR_OFFSET) +#define IMX_GPIO4_PSR (IMX_GPIO4_VBASE+IMX_GPIO_PSR_OFFSET) +#define IMX_GPIO4_ICR1 (IMX_GPIO4_VBASE+IMX_GPIO_ICR1_OFFSET) +#define IMX_GPIO4_ICR2 (IMX_GPIO4_VBASE+IMX_GPIO_ICR2_OFFSET) +#define IMX_GPIO4_IMR (IMX_GPIO4_VBASE+IMX_GPIO_IMR_OFFSET) +#define IMX_GPIO4_ISR (IMX_GPIO4_VBASE+IMX_GPIO_ISR_OFFSET) +#define IMX_GPIO4_EDGE (IMX_GPIO4_VBASE+IMX_GPIO_EDGE_OFFSET) -#define GPIO6_DR (IMX_GPIO6_VBASE+GPIO_DR_OFFSET) -#define GPIO6_GDIR (IMX_GPIO6_VBASE+GPIO_GDIR_OFFSET) -#define GPIO6_PSR (IMX_GPIO6_VBASE+GPIO_PSR_OFFSET) -#define GPIO6_ICR1 (IMX_GPIO6_VBASE+GPIO_ICR1_OFFSET) -#define GPIO6_ICR2 (IMX_GPIO6_VBASE+GPIO_ICR2_OFFSET) -#define GPIO6_IMR (IMX_GPIO6_VBASE+GPIO_IMR_OFFSET) -#define GPIO6_ISR (IMX_GPIO6_VBASE+GPIO_ISR_OFFSET) -#define GPIO6_EDGE (IMX_GPIO6_VBASE+GPIO_EDGE_OFFSET) +#define IMX_GPIO5_DR (IMX_GPIO5_VBASE+IMX_GPIO_DR_OFFSET) +#define IMX_GPIO5_GDIR (IMX_GPIO5_VBASE+IMX_GPIO_GDIR_OFFSET) +#define IMX_GPIO5_PSR (IMX_GPIO5_VBASE+IMX_GPIO_PSR_OFFSET) +#define IMX_GPIO5_ICR1 (IMX_GPIO5_VBASE+IMX_GPIO_ICR1_OFFSET) +#define IMX_GPIO5_ICR2 (IMX_GPIO5_VBASE+IMX_GPIO_ICR2_OFFSET) +#define IMX_GPIO5_IMR (IMX_GPIO5_VBASE+IMX_GPIO_IMR_OFFSET) +#define IMX_GPIO5_ISR (IMX_GPIO5_VBASE+IMX_GPIO_ISR_OFFSET) +#define IMX_GPIO5_EDGE (IMX_GPIO5_VBASE+IMX_GPIO_EDGE_OFFSET) -#define GPIO7_DR (IMX_GPIO7_VBASE+GPIO_DR_OFFSET) -#define GPIO7_GDIR (IMX_GPIO7_VBASE+GPIO_GDIR_OFFSET) -#define GPIO7_PSR (IMX_GPIO7_VBASE+GPIO_PSR_OFFSET) -#define GPIO7_ICR1 (IMX_GPIO7_VBASE+GPIO_ICR1_OFFSET) -#define GPIO7_ICR2 (IMX_GPIO7_VBASE+GPIO_ICR2_OFFSET) -#define GPIO7_IMR (IMX_GPIO7_VBASE+GPIO_IMR_OFFSET) -#define GPIO7_ISR (IMX_GPIO7_VBASE+GPIO_ISR_OFFSET) -#define GPIO7_EDGE (IMX_GPIO7_VBASE+GPIO_EDGE_OFFSET) +#define IMX_GPIO6_DR (IMX_GPIO6_VBASE+IMX_GPIO_DR_OFFSET) +#define IMX_GPIO6_GDIR (IMX_GPIO6_VBASE+IMX_GPIO_GDIR_OFFSET) +#define IMX_GPIO6_PSR (IMX_GPIO6_VBASE+IMX_GPIO_PSR_OFFSET) +#define IMX_GPIO6_ICR1 (IMX_GPIO6_VBASE+IMX_GPIO_ICR1_OFFSET) +#define IMX_GPIO6_ICR2 (IMX_GPIO6_VBASE+IMX_GPIO_ICR2_OFFSET) +#define IMX_GPIO6_IMR (IMX_GPIO6_VBASE+IMX_GPIO_IMR_OFFSET) +#define IMX_GPIO6_ISR (IMX_GPIO6_VBASE+IMX_GPIO_ISR_OFFSET) +#define IMX_GPIO6_EDGE (IMX_GPIO6_VBASE+IMX_GPIO_EDGE_OFFSET) + +#define IMX_GPIO7_DR (IMX_GPIO7_VBASE+IMX_GPIO_DR_OFFSET) +#define IMX_GPIO7_GDIR (IMX_GPIO7_VBASE+IMX_GPIO_GDIR_OFFSET) +#define IMX_GPIO7_PSR (IMX_GPIO7_VBASE+IMX_GPIO_PSR_OFFSET) +#define IMX_GPIO7_ICR1 (IMX_GPIO7_VBASE+IMX_GPIO_ICR1_OFFSET) +#define IMX_GPIO7_ICR2 (IMX_GPIO7_VBASE+IMX_GPIO_ICR2_OFFSET) +#define IMX_GPIO7_IMR (IMX_GPIO7_VBASE+IMX_GPIO_IMR_OFFSET) +#define IMX_GPIO7_ISR (IMX_GPIO7_VBASE+IMX_GPIO_ISR_OFFSET) +#define IMX_GPIO7_EDGE (IMX_GPIO7_VBASE+IMX_GPIO_EDGE_OFFSET) /* GPIO Register Bit Definitions ****************************************************/ diff --git a/arch/arm/src/imx6/chip/imx_memorymap.h b/arch/arm/src/imx6/chip/imx_memorymap.h index 08f0d9022eb..a3e981a6516 100644 --- a/arch/arm/src/imx6/chip/imx_memorymap.h +++ b/arch/arm/src/imx6/chip/imx_memorymap.h @@ -344,6 +344,7 @@ #define IMX_CAN1_PBASE (IMX_AIPS1_PSECTION+IMX_CAN1_OFFSET) #define IMX_CAN2_PBASE (IMX_AIPS1_PSECTION+IMX_CAN2_OFFSET) #define IMX_GPT_PBASE (IMX_AIPS1_PSECTION+IMX_GPT_OFFSET) +#define IMX_GPIO_PBASE(n) (IMX_AIPS1_PSECTION+IMX_GPIO_OFFSET(n)) #define IMX_GPIO1_PBASE (IMX_AIPS1_PSECTION+IMX_GPIO1_OFFSET) #define IMX_GPIO2_PBASE (IMX_AIPS1_PSECTION+IMX_GPIO2_OFFSET) #define IMX_GPIO3_PBASE (IMX_AIPS1_PSECTION+IMX_GPIO3_OFFSET) @@ -613,6 +614,7 @@ #define IMX_CAN1_VBASE (IMX_AIPS1_VSECTION+IMX_CAN1_OFFSET) #define IMX_CAN2_VBASE (IMX_AIPS1_VSECTION+IMX_CAN2_OFFSET) #define IMX_GPT_VBASE (IMX_AIPS1_VSECTION+IMX_GPT_OFFSET) +#define IMX_GPIO_VBASE(n) (IMX_AIPS1_VSECTION+IMX_GPIO_OFFSET(n)) #define IMX_GPIO1_VBASE (IMX_AIPS1_VSECTION+IMX_GPIO1_OFFSET) #define IMX_GPIO2_VBASE (IMX_AIPS1_VSECTION+IMX_GPIO2_OFFSET) #define IMX_GPIO3_VBASE (IMX_AIPS1_VSECTION+IMX_GPIO3_OFFSET) diff --git a/arch/arm/src/imx6/imx_gpio.c b/arch/arm/src/imx6/imx_gpio.c new file mode 100644 index 00000000000..cc33bb87ddb --- /dev/null +++ b/arch/arm/src/imx6/imx_gpio.c @@ -0,0 +1,226 @@ +/**************************************************************************** + * arch/arm/src/imx6/imx_gpio.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#include "chip.h" +#include "up_arch.h" +#include "imx_gpio.h" + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imx_gpio_dirout + ****************************************************************************/ + +static inline void imx_gpio_dirout(int port, int pin) +{ + uint32_t regval = getreg32(IMX_GPIO_GDIR(port)); + regval |= GPIO_PIN(pin); + putreg32(regval, IMX_GPIO_GDIR(port)); +} + +/**************************************************************************** + * Name: imx_gpio_dirin + ****************************************************************************/ + +static inline void imx_gpio_dirin(int port, int pin) +{ + uint32_t regval = getreg32(IMX_GPIO_GDIR(port)); + regval &= ~GPIO_PIN(pin); + putreg32(regval, IMX_GPIO_GDIR(port)); +} + +/**************************************************************************** + * Name: imx_gpio_setoutput + ****************************************************************************/ + +static inline void imx_gpio_setoutput(int port, int pin, bool value) +{ + uintptr_t regaddr = IMX_GPIO_DR(port); + uint32_t regval; + + regval = getreg32(regaddr); + if (value) + { + regval |= GPIO_PIN(pin); + } + else + { + regval &= ~GPIO_PIN(pin); + } + + putreg32(regval, regaddr); +} + +/**************************************************************************** + * Name: imx_gpio_getinput + ****************************************************************************/ + +static inline bool imx_gpio_getinput(int port, int pin) +{ + uintptr_t regaddr = IMX_GPIO_DR(port); + uint32_t regval; + + regval = getreg32(regaddr); + return ((regval & GPIO_PIN(pin)) != 0); +} + +/**************************************************************************** + * Name: imx_gpio_configinput + ****************************************************************************/ + +static inline int imx_gpio_configinput(gpio_pinset_t pinset, int port, int pin) +{ + /* Configure pin as in input */ + + imx_gpio_dirin(port, pin); + + /* Configure pin as a GPIO */ +#warning Missing logic + + /* Configure pin pad settings */ +#warning Missing logic + + return OK; +} + +/**************************************************************************** + * Name: imx_gpio_configoutput + ****************************************************************************/ + +static inline int imx_gpio_configoutput(gpio_pinset_t pinset, int port, int pin) +{ + bool value = ((pinset & GPIO_OUTPUT_ONE) != 0); + + /* Set the output value */ + + imx_gpio_setoutput(port, pin, value); + + /* Convert the configured input GPIO to an output */ + + imx_gpio_dirout(port, pin); + return OK; +} + +/**************************************************************************** + * Public Funtions + ****************************************************************************/ + +/**************************************************************************** + * Name: imx_config_gpio + * + * Description: + * Configure a GPIO pin based on pin-encoded description of the pin. + * + ****************************************************************************/ + +int imx_config_gpio(gpio_pinset_t pinset) +{ + irqstate_t flags; + int port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + int pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + int ret; + + /* Configure the pin as an input initially to avoid any spurios outputs */ + + flags = enter_critical_section(); + ret = imx_gpio_configinput(pinset, port, pin); + if (ret >= 0) + { + /* Was it really an output pin? */ + + if ((pinset & GPIO_OUTPUT) != 0) + { + /* YES.. convert the input to an output */ + + ret = imx_gpio_configoutput(pinset, port, pin); + } + } + + leave_critical_section(flags); + return ret; +} + +/************************************************************************************ + * Name: imx_gpio_write + * + * Description: + * Write one or zero to the selected GPIO pin + * + ************************************************************************************/ + +void imx_gpio_write(gpio_pinset_t pinset, bool value) +{ + irqstate_t flags; + int port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + int pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + + flags = enter_critical_section(); + imx_gpio_setoutput(port, pin, value); + leave_critical_section(flags); +} + +/************************************************************************************ + * Name: imx_gpio_read + * + * Description: + * Read one or zero from the selected GPIO pin + * + ************************************************************************************/ + +bool imx_gpio_read(gpio_pinset_t pinset) +{ + irqstate_t flags; + int port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + int pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + bool value; + + flags = enter_critical_section(); + value = imx_gpio_getinput(port, pin); + leave_critical_section(flags); + return value; +} diff --git a/arch/arm/src/imx6/imx_gpio.h b/arch/arm/src/imx6/imx_gpio.h index 1bc9a15a274..5522d0ee8c7 100644 --- a/arch/arm/src/imx6/imx_gpio.h +++ b/arch/arm/src/imx6/imx_gpio.h @@ -42,32 +42,35 @@ #include -#include +#include +#include + +#include "chip/imx_gpio.h" /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ /* Encoding: * - * ENCODING IRRR ODDD SSLT GGGP PPPP - * GPIO INPUT 0... .... ...T GGGP PPPP - * GPIO OUTPUT 1RRR ODDD SSL. GGGP PPPP + * ENCODING ...I RRRO DDDL SSVT GGGP PPPP + * GPIO INPUT ...0 .... .... ...T GGGP PPPP + * GPIO OUTPUT ...1 RRRO DDDL SSV. GGGP PPPP */ /* Input/Output Selection: * - * ENCODING I... .... .... .... .... + * ENCODING ...I .... .... .... .... .... */ -#define GPIO_INPUT (0) /* Bit 19: 0=input */ -#define GPIO_INPUT (1 << 19) /* Bit 19: 1=input */ +#define GPIO_INPUT (0) /* Bit 20: 0=input */ +#define GPIO_OUTPUT (1 << 19) /* Bit 20: 1=output */ /* Output Pull Up/Down: * - * GPIO OUTPUT .RRR .... .... .... .... + * GPIO OUTPUT ...1 RRR. .... .... .... .... */ -#define GPIO_PULL_SHIFT (16) /* Bits 16-18: Pull up/down selection */ +#define GPIO_PULL_SHIFT (17) /* Bits 17-19: Pull up/down selection */ #define GPIO_PULL_MASK (7 << GPIO_PULL_SHIFT) # define GPIO_PULL_NONE (0 << GPIO_PULL_SHIFT) /* Pull/keeper disabled */ # define GPIO_PULL_KEEP (1 << GPIO_PULL_SHIFT) /* Output determined by keeper */ @@ -78,31 +81,39 @@ /* Open Drain Output: * - * GPIO OUTPUT .... O... .... .... .... + * GPIO OUTPUT ...1 ...O .... .... .... .... */ -#define GPIO_CMOS_OUTPUT (1 << 15) /* Bit 15: 0=CMOS output */ -#define GPIO_OPENDRAIN (1 << 15) /* Bit 15: 1=Enable open-drain output */ +#define GPIO_CMOS_OUTPUT (1 << 16) /* Bit 16: 0=CMOS output */ +#define GPIO_OPENDRAIN (1 << 16) /* Bit 16: 1=Enable open-drain output */ /* Output Drive Strength: * - * GPIO OUTPUT .... .DDD .... .... .... + * GPIO OUTPUT ...1 .... DDD. .... .... .... */ -#define GPIO_DRIVE_SHIFT (12) /* Bits 12-14: Output Drive Strength */ +#define GPIO_DRIVE_SHIFT (13) /* Bits 13-15: Output Drive Strength */ #define GPIO_DRIVE_MASK (7 << GPIO_DRIVE_SHIFT) -# define GPIO_DRIVE_HIZ (0 << GPIO_DRIVE_SHIFT) /* HI-Z */ -# define GPIO_DRIVE_260OHM (1 << GPIO_DRIVE_SHIFT) /* 150 Ohm @3.3V, 260 Ohm @1.8V */ -# define GPIO_DRIVE_130OHM (2 << GPIO_DRIVE_SHIFT) /* 75 Ohm @3.3V, 130 Ohm @1.8V */ -# define GPIO_DRIVE_90OHM (3 << GPIO_DRIVE_SHIFT) /* 50 Ohm @3.3V, 90 Ohm @1.8V */ -# define GPIO_DRIVE_60OHM (4 << GPIO_DRIVE_SHIFT) /* 37 Ohm @3.3V, 60 Ohm @1.8V */ -# define GPIO_DRIVE_50OHM (5 << GPIO_DRIVE_SHIFT) /* 30 Ohm @3.3V, 50 Ohm @1.8V */ -# define GPIO_DRIVE_40OHM (6 << GPIO_DRIVE_SHIFT) /* 25 Ohm @3.3V, 40 Ohm @1.8V */ -# define GPIO_DRIVE_33OHM (7 << GPIO_DRIVE_SHIFT) /* 20 Ohm @3.3V, 33 Ohm @1.8V */ +# define GPIO_DRIVE_HIZ (0 << GPIO_DRIVE_SHIFT) /* HI-Z */ +# define GPIO_DRIVE_260OHM (1 << GPIO_DRIVE_SHIFT) /* 150 Ohm @3.3V, 260 Ohm @1.8V */ +# define GPIO_DRIVE_130OHM (2 << GPIO_DRIVE_SHIFT) /* 75 Ohm @3.3V, 130 Ohm @1.8V */ +# define GPIO_DRIVE_90OHM (3 << GPIO_DRIVE_SHIFT) /* 50 Ohm @3.3V, 90 Ohm @1.8V */ +# define GPIO_DRIVE_60OHM (4 << GPIO_DRIVE_SHIFT) /* 37 Ohm @3.3V, 60 Ohm @1.8V */ +# define GPIO_DRIVE_50OHM (5 << GPIO_DRIVE_SHIFT) /* 30 Ohm @3.3V, 50 Ohm @1.8V */ +# define GPIO_DRIVE_40OHM (6 << GPIO_DRIVE_SHIFT) /* 25 Ohm @3.3V, 40 Ohm @1.8V */ +# define GPIO_DRIVE_33OHM (7 << GPIO_DRIVE_SHIFT) /* 20 Ohm @3.3V, 33 Ohm @1.8V */ +/* Output Slew Rate: + * + * GPIO OUTPUT ...1 .... ...L .... .... .... + */ + +#define GPIO_SLEW_SLOW (0) /* Bit 12: 0=Slow Slew Rate */ +#define GPIO_SLEW_FAST (1 << 12) /* Bit 12: 1=Fast Slew Rate */ + /* Output Speed: * - * GPIO OUTPUT .... .... SS.. .... .... + * GPIO OUTPUT ...1 .... .... SS.. .... .... */ #define GPIO_SPEED_SHIFT (10) /* Bits 10-11: Speed */ @@ -111,17 +122,17 @@ # define GPIO_SPEED_MEDIUM (1 << GPIO_SPEED_SHIFT) /* Medium frequency (100, 150 MHz) */ # define GPIO_SPEED_MAX (3 << GPIO_SPEED_SHIFT) /* Maximum frequency (100, 150, 200 MHz) */ -/* Output Slew Rate: +/* Initial Ouptut Value: * - * GPIO OUTPUT .... .... ..L. .... .... + * GPIO OUTPUT ...1 .... .... ..V. .... .... */ -#define GPIO_SLEW_SLOW (0) /* Bit 9: 0=Slow Slew Rate */ -#define GPIO_SLEW_FAST (1 << 9) /* Bit 9: 1=Fast Slew Rate */ +#define GPIO_OUTPUT_ZERO (0) /* Bit 9: 0=Initial output is low */ +#define GPIO_OUTPUT_ONE (1 << 9) /* Bit 9: 1=Initial output is high */ /* Input Schmitt Trigger: * - * GPIO INPUT 0... .... ...T .... .... + * GPIO INPUT ...0 .... .... ...T .... .... */ #define GPIO_CMOS_INPUT (0) /* Bit 8: 0=CMOS input */ @@ -129,7 +140,7 @@ /* GPIO Port Number * - * ENCODING .... .... .... GGG. .... + * ENCODING .... .... .... .... GGG. .... */ #define GPIO_PORT_SHIFT (5) /* Bits 5-7: Speed */ @@ -144,7 +155,7 @@ /* GPIO Pin Number: * - * ENCODING .... .... .... ...P PPPP + * ENCODING .... .... .... .... ...P PPPP */ #define GPIO_PIN_SHIFT (5) /* Bits 0-4: Speed */ @@ -190,12 +201,6 @@ typedef uint32_t gpio_pinset_t; -/************************************************************************************ - * Inline Functions - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - /************************************************************************************ * Public Data ************************************************************************************/ @@ -214,15 +219,15 @@ extern "C" ************************************************************************************/ /************************************************************************************ - * Name: imx_gpioirqinitialize + * Name: imx_gpioirq_initialize * * Description: - * Initialize logic to support a second level of interrupt decoding for PIO pins. + * Initialize logic to support a second level of interrupt decoding for GPIO pins. * ************************************************************************************/ #ifdef CONFIG_IMX6_GPIO_IRQ -void imx_gpioirqinitialize(void); +void imx_gpioirq_initialize(void); #else # define imx_gpioirqinitialize() #endif @@ -231,17 +236,17 @@ void imx_gpioirqinitialize(void); * Name: imx_config_gpio * * Description: - * Configure a PIO pin based on bit-encoded description of the pin. + * Configure a GPIO pin based on bit-encoded description of the pin. * ************************************************************************************/ -int imx_config_gpio(gpio_pinset_t cfgset); +int imx_config_gpio(gpio_pinset_t pinset); /************************************************************************************ * Name: imx_gpio_write * * Description: - * Write one or zero to the selected PIO pin + * Write one or zero to the selected GPIO pin * ************************************************************************************/ @@ -251,7 +256,7 @@ void imx_gpio_write(gpio_pinset_t pinset, bool value); * Name: imx_gpio_read * * Description: - * Read one or zero from the selected PIO pin + * Read one or zero from the selected GPIO pin * ************************************************************************************/ @@ -261,7 +266,7 @@ bool imx_gpio_read(gpio_pinset_t pinset); * Name: imx_gpioirq * * Description: - * Configure an interrupt for the specified PIO pin. + * Configure an interrupt for the specified GPIO pin. * ************************************************************************************/ @@ -275,7 +280,7 @@ void imx_gpioirq(gpio_pinset_t pinset); * Name: imx_gpioirq_enable * * Description: - * Enable the interrupt for specified PIO IRQ + * Enable the interrupt for specified GPIO IRQ * ************************************************************************************/ @@ -289,7 +294,7 @@ void imx_gpioirq_enable(int irq); * Name: imx_gpioirq_disable * * Description: - * Disable the interrupt for specified PIO IRQ + * Disable the interrupt for specified GPIO IRQ * ************************************************************************************/ @@ -303,7 +308,7 @@ void imx_gpioirq_disable(int irq); * Function: imx_dump_gpio * * Description: - * Dump all PIO registers associated with the base address of the provided pinset. + * Dump all GPIO registers associated with the base address of the provided pinset. * ************************************************************************************/