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risc-v: Remove ARCH_RV_ISA_[F|D] use ARCH_HAVE_FPU instead

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Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
This commit is contained in:
Huang Qi
2022-01-15 09:32:45 +08:00
committed by Xiang Xiao
parent 5792d851e5
commit 56a95ad0b5
3 changed files with 10 additions and 25 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/risc-v/Kconfig
+7 -18
View File
@@ -44,8 +44,8 @@ config ARCH_CHIP_BL602
select ARCH_RV32 select ARCH_RV32
select ARCH_RV_ISA_M select ARCH_RV_ISA_M
select ARCH_RV_ISA_A select ARCH_RV_ISA_A
select ARCH_RV_ISA_F
select ARCH_RV_ISA_C select ARCH_RV_ISA_C
select ARCH_HAVE_FPU
select ARCH_HAVE_RESET select ARCH_HAVE_RESET
---help--- ---help---
BouffaloLab BL602(rv32imfc) BouffaloLab BL602(rv32imfc)
@@ -80,9 +80,9 @@ config ARCH_CHIP_C906
select ARCH_RV64 select ARCH_RV64
select ARCH_RV_ISA_M select ARCH_RV_ISA_M
select ARCH_RV_ISA_A select ARCH_RV_ISA_A
select ARCH_RV_ISA_F
select ARCH_RV_ISA_D
select ARCH_RV_ISA_C select ARCH_RV_ISA_C
select ARCH_HAVE_FPU
select ARCH_HAVE_DPFPU
select ARCH_HAVE_MPU select ARCH_HAVE_MPU
---help--- ---help---
THEAD C906 processor (RISC-V 64bit core with GCVX extensions). THEAD C906 processor (RISC-V 64bit core with GCVX extensions).
@@ -92,9 +92,9 @@ config ARCH_CHIP_MPFS
select ARCH_RV64 select ARCH_RV64
select ARCH_RV_ISA_M select ARCH_RV_ISA_M
select ARCH_RV_ISA_A select ARCH_RV_ISA_A
select ARCH_RV_ISA_F
select ARCH_RV_ISA_D
select ARCH_RV_ISA_C select ARCH_RV_ISA_C
select ARCH_HAVE_FPU
select ARCH_HAVE_DPFPU
select ARCH_HAVE_MPU select ARCH_HAVE_MPU
select ARCH_HAVE_RESET select ARCH_HAVE_RESET
select ARCH_HAVE_SPI_CS_CONTROL select ARCH_HAVE_SPI_CS_CONTROL
@@ -112,8 +112,8 @@ config ARCH_CHIP_RV32M1
config ARCH_CHIP_QEMU_RV config ARCH_CHIP_QEMU_RV
bool "QEMU RV" bool "QEMU RV"
select ARCH_RV_ISA_F select ARCH_HAVE_FPU
select ARCH_RV_ISA_D select ARCH_HAVE_DPFPU
---help--- ---help---
QEMU Generic RV32 processor QEMU Generic RV32 processor
@@ -149,17 +149,6 @@ config ARCH_RV_ISA_C
bool bool
default n default n
config ARCH_RV_ISA_F
bool
default n
select ARCH_HAVE_FPU
config ARCH_RV_ISA_D
bool
default n
depends on ARCH_RV_ISA_F
select ARCH_HAVE_DPFPU
config ARCH_FAMILY config ARCH_FAMILY
string string
default "rv32" if ARCH_RV32 default "rv32" if ARCH_RV32
arch/risc-v/src/common/Toolchain.defs
-4
View File
@@ -81,14 +81,10 @@ ifeq ($(CONFIG_RISCV_TOOLCHAIN),GNU_RVG)
ARCHRVISAC = c ARCHRVISAC = c
endif endif
# ARCH_FPU depends on ARCH_RV_ISA_F
ifeq ($(CONFIG_ARCH_FPU),y) ifeq ($(CONFIG_ARCH_FPU),y)
ARCHRVISAF = f ARCHRVISAF = f
endif endif
# ARCH_DPFPU depends on ARCH_RV_ISA_D and ARCH_FPU
ifeq ($(CONFIG_ARCH_DPFPU),y) ifeq ($(CONFIG_ARCH_DPFPU),y)
ARCHRVISAD = d ARCHRVISAD = d
endif endif
arch/risc-v/src/qemu-rv/Kconfig
+3 -3
View File
@@ -22,17 +22,17 @@ endchoice
config ARCH_CHIP_QEMU_RV_ISA_M config ARCH_CHIP_QEMU_RV_ISA_M
bool "Standard Extension for Integer Multiplication and Division" bool "Standard Extension for Integer Multiplication and Division"
default y default n
select ARCH_RV_ISA_M select ARCH_RV_ISA_M
config ARCH_CHIP_QEMU_RV_ISA_A config ARCH_CHIP_QEMU_RV_ISA_A
bool "Standard Extension for Atomic Instructions" bool "Standard Extension for Atomic Instructions"
default y default n
select ARCH_RV_ISA_A select ARCH_RV_ISA_A
config ARCH_CHIP_QEMU_RV_ISA_C config ARCH_CHIP_QEMU_RV_ISA_C
bool "Standard Extension for Compressed Instructions" bool "Standard Extension for Compressed Instructions"
default y default n
select ARCH_RV_ISA_C select ARCH_RV_ISA_C
endif endif