arch/arm: initial support for NRF91

Port based on arch/arm/nrf53.

Modem not fully supported yet. At the moment, initialization and AT interface work.
Sockets and GNSS interface will be added later.

Kconfig

@@ -68,7 +68,7 @@ config ALLOW_MIT_COMPONENTS
 
 config ALLOW_BSDNORDIC_COMPONENTS
 	bool "Use components that have 5-Clause Nordic licenses"
-	depends on ARCH_CHIP_NRF52 || ARCH_CHIP_NRF53
+	depends on ARCH_CHIP_NRF52 || ARCH_CHIP_NRF53 || ARCH_CHIP_NRF91
 	default n
 	---help---
 		When this option is enabled the project will allow the use

LICENSE

@@ -6715,6 +6715,8 @@ drivers/wireless/spirit/
  SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 arch/arm/src/nrf52/sdk-nrfxlib
+arch/arm/src/nrf53/sdk-nrfxlib
+arch/arm/src/nrf91/sdk-nrfxlib
 ===============================
 
  Nordic SoftDevice Controller is based on the 3-Clause BSD License:

arch/arm/Kconfig

@@ -295,6 +295,17 @@ config ARCH_CHIP_NRF53
 	---help---
 		Nordic NRF53 architectures (ARM dual Cortex-M33).
 
+config ARCH_CHIP_NRF91
+	bool "Nordic NRF91"
+	select ARCH_CORTEXM33
+	select ARCH_HAVE_PWM_MULTICHAN
+	select ARCH_HAVE_TRUSTZONE
+	select ARCH_HAVE_TICKLESS
+	depends on EXPERIMENTAL
+	---help---
+		Nordic NRF91 architectures (ARM Cortex-M33 with integrated
+		LTE-M/NB-IoT modem and GNSS).
+
 config ARCH_CHIP_NUC1XX
 	bool "Nuvoton NUC100/120"
 	select ARCH_CORTEXM0
@@ -991,6 +1002,7 @@ config ARCH_CHIP
 	default "moxart"	if ARCH_CHIP_MOXART
 	default "nrf52"		if ARCH_CHIP_NRF52
 	default "nrf53"		if ARCH_CHIP_NRF53
+	default "nrf91"		if ARCH_CHIP_NRF91
 	default "nuc1xx"	if ARCH_CHIP_NUC1XX
 	default "rp2040"	if ARCH_CHIP_RP2040
 	default "s32k1xx"	if ARCH_CHIP_S32K1XX
@@ -1428,6 +1440,9 @@ endif
 if ARCH_CHIP_NRF53
 source "arch/arm/src/nrf53/Kconfig"
 endif
+if ARCH_CHIP_NRF91
+source "arch/arm/src/nrf91/Kconfig"
+endif
 if ARCH_CHIP_NUC1XX
 source "arch/arm/src/nuc1xx/Kconfig"
 endif

arch/arm/include/nrf91/chip.h

@@ -0,0 +1,53 @@
+/****************************************************************************
+ * arch/arm/include/nrf91/chip.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_INCLUDE_NRF91_CHIP_H
+#define __ARCH_ARM_INCLUDE_NRF91_CHIP_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+/****************************************************************************
+ * Pre-processor Prototypes
+ ****************************************************************************/
+
+/* NVIC priority levels *****************************************************/
+
+#define NVIC_SYSH_PRIORITY_MIN          0xe0 /* All bits[7:5] set is minimum priority */
+#define NVIC_SYSH_PRIORITY_DEFAULT      0x80 /* Midpoint is the default */
+#define NVIC_SYSH_PRIORITY_MAX          0x00 /* Zero is maximum priority */
+#define NVIC_SYSH_PRIORITY_STEP         0x20 /* Steps between priorities */
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions Prototypes
+ ****************************************************************************/
+
+#endif /* __ARCH_ARM_INCLUDE_NRF91_CHIP_H */

arch/arm/include/nrf91/irq.h

@@ -0,0 +1,101 @@
+/****************************************************************************
+ * arch/arm/include/nrf91/irq.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather,
+ * only indirectly through nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM_INCLUDE_NRF91_IRQ_H
+#define __ARCH_ARM_INCLUDE_NRF91_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+#  include <stdint.h>
+#endif
+
+/****************************************************************************
+ * Pre-processor Prototypes
+ ****************************************************************************/
+
+/* IRQ numbers.
+ * The IRQ number corresponds vector number and hence map directly to bits in
+ * the NVIC.  This does, however, waste several words of memory in the IRQ to
+ * handle mapping tables.
+ */
+
+/* Processor Exceptions (vectors 0-15) */
+
+#define NRF91_IRQ_RESERVED         (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
+                                       /* Vector  0: Reset stack pointer value */
+                                       /* Vector  1: Reset (not handler as an IRQ) */
+#define NRF91_IRQ_NMI              (2) /* Vector  2: Non-Maskable Interrupt (NMI) */
+#define NRF91_IRQ_HARDFAULT        (3) /* Vector  3: Hard fault */
+#define NRF91_IRQ_MEMFAULT         (4) /* Vector  4: Memory management (MPU) */
+#define NRF91_IRQ_BUSFAULT         (5) /* Vector  5: Bus fault */
+#define NRF91_IRQ_USAGEFAULT       (6) /* Vector  6: Usage fault */
+                                       /* Vectors 7-10: Reserved */
+#define NRF91_IRQ_SVCALL          (11) /* Vector 11: SVC call */
+#define NRF91_IRQ_DBGMONITOR      (12) /* Vector 12: Debug Monitor */
+                                       /* Vector 13: Reserved */
+#define NRF91_IRQ_PENDSV          (14) /* Vector 14: Pendable system service request */
+#define NRF91_IRQ_SYSTICK         (15) /* Vector 15: System tick */
+#define NRF91_IRQ_EXTINT          (16) /* Vector 16: Vector number of the first external interrupt */
+
+/* Cortex-M4 External interrupts (vectors >= 16) */
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#if defined(CONFIG_ARCH_CHIP_NRF9160)
+#  include <arch/nrf91/nrf9160_irq.h>
+#else
+#  error "Unsupported NRF91XX MCU"
+#endif
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+typedef void (*vic_vector_t)(uint32_t *regs);
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+#endif
+
+#endif /* __ARCH_ARM_INCLUDE_NRF91_IRQ_H */

arch/arm/include/nrf91/nrf9160_irq.h

@@ -0,0 +1,76 @@
+/****************************************************************************
+ * arch/arm/include/nrf91/nrf9160_irq.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather,
+ * only indirectly through nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM_INCLUDE_NRF9160_IRQ_H
+#define __ARCH_ARM_INCLUDE_NRF9160_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+/* Cortex-M33 External interrupts (vectors >= 16) */
+
+/* Application core */
+
+#define NRF91_IRQ_SPU           (NRF91_IRQ_EXTINT+3)   /* SPU interrupt */
+#define NRF91_IRQ_REGULATORS    (NRF91_IRQ_EXTINT+4)   /* Regulators */
+#define NRF91_IRQ_POWER_CLOCK   (NRF91_IRQ_EXTINT+5)   /* Power, Clock */
+#define NRF91_IRQ_SERIAL0       (NRF91_IRQ_EXTINT+8)   /* UART/SPI/TWI 0 */
+#define NRF91_IRQ_SERIAL1       (NRF91_IRQ_EXTINT+9)   /* UART/SPI/TWI 1 */
+#define NRF91_IRQ_SERIAL2       (NRF91_IRQ_EXTINT+10)  /* UART/SPI/TWI 2 */
+#define NRF91_IRQ_SERIAL3       (NRF91_IRQ_EXTINT+11)  /* UART/SPI/TWI 3 */
+#define NRF91_IRQ_GPIOTE0       (NRF91_IRQ_EXTINT+13)  /* GPIO Task & Event 0 */
+#define NRF91_IRQ_SAADC         (NRF91_IRQ_EXTINT+14)  /* Analog to Digital Converter */
+#define NRF91_IRQ_TIMER0        (NRF91_IRQ_EXTINT+15)  /* Timer 0 */
+#define NRF91_IRQ_TIMER1        (NRF91_IRQ_EXTINT+16)  /* Timer 1 */
+#define NRF91_IRQ_TIMER2        (NRF91_IRQ_EXTINT+17)  /* Timer 2 */
+#define NRF91_IRQ_RTC0          (NRF91_IRQ_EXTINT+20)  /* Real-time counter 0 */
+#define NRF91_IRQ_RTC1          (NRF91_IRQ_EXTINT+21)  /* Real-time counter 1 */
+#define NRF91_IRQ_WDT0          (NRF91_IRQ_EXTINT+24)  /* Watchdog Timer 0 */
+#define NRF91_IRQ_EGU0          (NRF91_IRQ_EXTINT+27)  /* Event Gen. Unit 0 */
+#define NRF91_IRQ_EGU1          (NRF91_IRQ_EXTINT+28)  /* Event Gen. Unit 1 */
+#define NRF91_IRQ_EGU2          (NRF91_IRQ_EXTINT+29)  /* Event Gen. Unit 2 */
+#define NRF91_IRQ_EGU3          (NRF91_IRQ_EXTINT+30)  /* Event Gen. Unit 3 */
+#define NRF91_IRQ_EGU4          (NRF91_IRQ_EXTINT+31)  /* Event Gen. Unit 4 */
+#define NRF91_IRQ_EGU5          (NRF91_IRQ_EXTINT+32)  /* Event Gen. Unit 5 */
+#define NRF91_IRQ_PWM0          (NRF91_IRQ_EXTINT+33)  /* Pulse Width Modulation Unit 0 */
+#define NRF91_IRQ_PWM1          (NRF91_IRQ_EXTINT+34)  /* Pulse Width Modulation Unit 1 */
+#define NRF91_IRQ_PWM2          (NRF91_IRQ_EXTINT+35)  /* Pulse Width Modulation Unit 2 */
+#define NRF91_IRQ_PWM3          (NRF91_IRQ_EXTINT+36)  /* Pulse Width Modulation Unit 3 */
+#define NRF91_IRQ_PDM           (NRF91_IRQ_EXTINT+38)  /* Pulse Density Modulation (Digital Mic) Interface */
+#define NRF91_IRQ_I2S           (NRF91_IRQ_EXTINT+40)  /* Inter-IC Sound interface */
+#define NRF91_IRQ_IPC           (NRF91_IRQ_EXTINT+42)  /* IPC */
+#define NRF91_IRQ_GPIOTE1       (NRF91_IRQ_EXTINT+49)  /* GPIO Task & Event 1 */
+#define NRF91_IRQ_KMU           (NRF91_IRQ_EXTINT+57)  /* KMU */
+#define NRF91_IRQ_CRYPTOCELL    (NRF91_IRQ_EXTINT+64)  /* CRYPTOCELL */
+
+#define NRF91_IRQ_NEXTINT       (66)
+
+#define NRF91_IRQ_NIRQS         (NRF91_IRQ_EXTINT+NRF91_IRQ_NEXTINT)
+
+/* Total number of IRQ numbers */
+
+#define NR_IRQS                 NRF91_IRQ_NIRQS
+
+#endif /* __ARCH_ARM_INCLUDE_NRF9160_IRQ_H */

arch/arm/src/nrf91/.gitignore

@@ -0,0 +1,2 @@
+sdk-nrfxlib*
+*.tar.gz

arch/arm/src/nrf91/Make.defs

@@ -0,0 +1,134 @@
+############################################################################
+# arch/arm/src/nrf91/Make.defs
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more
+# contributor license agreements.  See the NOTICE file distributed with
+# this work for additional information regarding copyright ownership.  The
+# ASF licenses this file to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance with the
+# License.  You may obtain a copy of the License at
+#
+#   http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+# License for the specific language governing permissions and limitations
+# under the License.
+#
+############################################################################
+
+include armv8-m/Make.defs
+
+ifeq ($(CONFIG_NRF91_SYSTIMER_SYSTICK),y)
+CHIP_CSRCS += nrf91_systick.c
+else
+ifeq ($(CONFIG_NRF91_SYSTIMER_RTC),y)
+CHIP_CSRCS += nrf91_tickless_rtc.c
+endif
+endif
+
+CHIP_CSRCS += nrf91_start.c nrf91_clockconfig.c nrf91_irq.c nrf91_utils.c
+CHIP_CSRCS += nrf91_allocateheap.c nrf91_lowputc.c nrf91_gpio.c
+CHIP_CSRCS += nrf91_uid.c nrf91_spu.c
+
+ifeq ($(CONFIG_NRF91_PROGMEM),y)
+CHIP_CSRCS += nrf91_flash.c
+endif
+
+ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y)
+CHIP_CSRCS += nrf91_idle.c
+endif
+
+ifeq ($(CONFIG_NRF91_GPIOTE),y)
+CHIP_CSRCS += nrf91_gpiote.c
+endif
+
+ifeq ($(CONFIG_NRF91_UART),y)
+CHIP_CSRCS += nrf91_serial.c
+endif
+
+ifeq ($(CONFIG_NRF91_TIMER),y)
+CHIP_CSRCS += nrf91_tim.c
+ifeq ($(CONFIG_TIMER),y)
+CHIP_CSRCS += nrf91_tim_lowerhalf.c
+endif
+endif
+
+ifeq ($(CONFIG_NRF91_PWM),y)
+CHIP_CSRCS += nrf91_pwm.c
+endif
+
+ifeq ($(CONFIG_NRF91_SAADC),y)
+CHIP_CSRCS += nrf91_adc.c
+endif
+
+ifeq ($(CONFIG_NRF91_RTC),y)
+CHIP_CSRCS += nrf91_rtc.c
+endif
+
+ifeq ($(CONFIG_NRF91_SPI_MASTER),y)
+CHIP_CSRCS += nrf91_spi.c
+endif
+
+ifeq ($(CONFIG_PM),y)
+CHIP_CSRCS += nrf91_pminitialize.c
+endif
+
+ifeq ($(CONFIG_NRF91_I2C_MASTER),y)
+CHIP_CSRCS += nrf91_i2c.c
+endif
+
+ifeq ($(CONFIG_NRF91_MODEM),y)
+
+NRFXLIB_UNPACK  := sdk-nrfxlib
+NRFXLIB_VER     := 2.4.0
+NRFXLIB_REF     := v$(NRFXLIB_VER)
+NRFXLIB_TGZ     := $(NRFXLIB_REF).tar.gz
+NRFXLIB_URL     := https://github.com/nrfconnect/sdk-nrfxlib/archive
+
+$(NRFXLIB_TGZ):
+	$(call DOWNLOAD,$(NRFXLIB_URL),$(NRFXLIB_TGZ),chip/$(NRFXLIB_TGZ))
+
+chip/$(NRFXLIB_UNPACK): $(NRFXLIB_TGZ)
+	$(Q) echo "Unpacking: NRXFLIB"
+	$(Q) cd chip && tar zxf $(NRFXLIB_TGZ)
+	$(Q) mv chip/$(NRFXLIB_UNPACK)-$(NRFXLIB_VER)* chip/$(NRFXLIB_UNPACK)
+	$(Q) touch chip/$(NRFXLIB_UNPACK)
+
+ifeq ($(wildcard chip/$(NRFXLIB_UNPACK)/.git),)
+context:: chip/$(NRFXLIB_UNPACK)
+
+distclean::
+	$(call DELFILE, chip/$(NRFXLIB_TGZ))
+	$(call DELDIR, chip/$(NRFXLIB_UNPACK))
+endif
+
+CHIP_CSRCS += nrf91_modem.c nrf91_modem_os.c nrf91_nrfx_ipc.c
+
+ifeq ($(CONFIG_NRF91_MODEM_AT),y)
+CHIP_CSRCS += nrf91_modem_at.c
+endif
+
+NRFXLIB_DIR = $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)sdk-nrfxlib
+
+INCLUDES += \
+	${INCDIR_PREFIX}$(NRFXLIB_DIR)$(DELIM)nrf_modem$(DELIM)include
+
+ifeq ($(CONFIG_ARCH_FPU),y)
+  LIB_VARIANT=hard-float
+else
+  LIB_VARIANT=soft-float
+endif
+
+EXTRA_LIBPATHS += \
+	-L $(NRFXLIB_DIR)$(DELIM)nrf_modem$(DELIM)lib$(DELIM)cortex-m33$(DELIM)$(LIB_VARIANT)
+
+ifeq ($(CONFIG_NRF91_MODEM_LOG),y)
+  EXTRA_LIBS += -lmodem_log
+else
+  EXTRA_LIBS += -lmodem
+endif
+
+
+endif

arch/arm/src/nrf91/chip.h

@@ -0,0 +1,47 @@
+/****************************************************************************
+ * arch/arm/src/nrf91/chip.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_NRF91_CHIP_H
+#define __ARCH_ARM_SRC_NRF91_CHIP_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+/* Include the memory map and the chip definitions file.
+ *  Other chip hardware files should then include this file for the proper
+ * setup.
+ */
+
+#include <arch/irq.h>
+#include <arch/nrf91/chip.h>
+#include "hardware/nrf91_memorymap.h"
+
+/* If the common ARMv7-M vector handling logic is used, then it expects the
+ * following definition in this file that provides the number of supported
+ * external interrupts which, for this architecture, is provided in the
+ * arch/nrf91/chip.h header file.
+ */
+
+#define ARMV8M_PERIPHERAL_INTERRUPTS NRF91_IRQ_NEXTINT
+
+#endif /* __ARCH_ARM_SRC_NRF91_CHIP_H */

arch/arm/src/nrf91/hardware/nrf91_clock.h

@@ -0,0 +1,109 @@
+/****************************************************************************
+ * arch/arm/src/nrf91/hardware/nrf91_clock.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_NRF91_HARDWARE_NRF91_CLOCK_H
+#define __ARCH_ARM_SRC_NRF91_HARDWARE_NRF91_CLOCK_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include "nrf91_memorymap.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Register offsets *********************************************************/
+
+#define NRF91_CLOCK_TASKS_HFCLKSTART_OFFSET         0x0000 /* Start HFCLK crystal oscillator */
+#define NRF91_CLOCK_TASKS_HFCLKSTOP_OFFSET          0x0004 /* Stop HFCLK crystal oscillator */
+#define NRF91_CLOCK_TASKS_LFCLKSTART_OFFSET         0x0008 /* Start LFCLK source */
+#define NRF91_CLOCK_TASKS_LFCLKSTOP_OFFSET          0x000c /* Stop LFCLK source */
+                                                           /* TODO: */
+#define NRF91_CLOCK_EVENTS_HFCLKSTARTED_OFFSET      0x0100 /* HFCLK oscillator started */
+#define NRF91_CLOCK_EVENTS_LFCLKSTARTED_OFFSET      0x0104 /* LFCLK started */
+                                                           /* TODO: */
+#define NRF91_CLOCK_INTENSET_OFFSET                 0x0304 /* Enable interrupt */
+#define NRF91_CLOCK_INTENCLR_OFFSET                 0x0308 /* Disable interrupt */
+                                                           /* TODO: */
+#define NRF91_CLOCK_HFCLKRUN_OFFSET                 0x0408 /* Status indicating that HFCLKSTART task has been triggered */
+#define NRF91_CLOCK_HFCLKSTAT_OFFSET                0x040c /* HFCLK status */
+#define NRF91_CLOCK_LFCLKRUN_OFFSET                 0x0414 /* Status indicating that LFCLKSTART task has been triggered */
+#define NRF91_CLOCK_LFCLKSTAT_OFFSET                0x0418 /* LFCLK status */
+#define NRF91_CLOCK_LFCLKSRCCOPY_OFFSET             0x041c /* Copy of LFCLKSRC register, set when LFCLKSTART task was triggered */
+#define NRF91_CLOCK_LFCLKSRC_OFFSET                 0x0518 /* Clock source for the LFCLK */
+
+/* Register definitions *****************************************************/
+
+#define NRF91_CLOCK_TASKS_HFCLKSTART         (NRF91_CLOCK_BASE + NRF91_CLOCK_TASKS_HFCLKSTART_OFFSET)
+#define NRF91_CLOCK_TASKS_HFCLKSTOP          (NRF91_CLOCK_BASE + NRF91_CLOCK_TASKS_HFCLKSTOP_OFFSET)
+#define NRF91_CLOCK_TASKS_LFCLKSTART         (NRF91_CLOCK_BASE + NRF91_CLOCK_TASKS_LFCLKSTART_OFFSET)
+#define NRF91_CLOCK_TASKS_LFCLKSTOP          (NRF91_CLOCK_BASE + NRF91_CLOCK_TASKS_LFCLKSTOP_OFFSET)
+/* TODO */
+#define NRF91_CLOCK_EVENTS_HFCLKSTARTED      (NRF91_CLOCK_BASE + NRF91_CLOCK_EVENTS_HFCLKSTARTED_OFFSET)
+#define NRF91_CLOCK_EVENTS_LFCLKSTARTED      (NRF91_CLOCK_BASE + NRF91_CLOCK_EVENTS_LFCLKSTARTED_OFFSET)
+/* TODO */
+#define NRF91_CLOCK_INTENSET                 (NRF91_CLOCK_BASE + NRF91_CLOCK_INTENSET_OFFSET)
+#define NRF91_CLOCK_INTENCLR                 (NRF91_CLOCK_BASE + NRF91_CLOCK_INTENCLR_OFFSET)
+/* TODO */
+#define NRF91_CLOCK_HFCLKRUN                 (NRF91_CLOCK_BASE + NRF91_CLOCK_HFCLKRUN_OFFSET)
+#define NRF91_CLOCK_HFCLKSTAT                (NRF91_CLOCK_BASE + NRF91_CLOCK_HFCLKSTAT_OFFSET)
+#define NRF91_CLOCK_LFCLKRUN                 (NRF91_CLOCK_BASE + NRF91_CLOCK_LFCLKRUN_OFFSET)
+#define NRF91_CLOCK_LFCLKSTAT                (NRF91_CLOCK_BASE + NRF91_CLOCK_LFCLKSTAT_OFFSET)
+#define NRF91_CLOCK_LFCLKSRCCOPY             (NRF91_CLOCK_BASE + NRF91_CLOCK_LFCLKSRCCOPY_OFFSET)
+#define NRF91_CLOCK_LFCLKSRC                 (NRF91_CLOCK_BASE + NRF91_CLOCK_LFCLKSRC_OFFSET)
+
+/* Register bit definitions *************************************************/
+
+/* HFCLKRUN Register */
+
+#define CLOCK_HFCLKRUN_STATUS           (1 << 0)  /* Bit 0: HFCLSTART task triggered status */
+
+/* HFCLKSTAT Register */
+
+#define CLOCK_HFCLKSTAT_SRC_SHIFT       (0)                              /* Bit 0: Source of HFCLK */
+#define CLOCK_HFCLKSTAT_SRC_MASK        (1 << CLOCK_HFCLKSTAT_SRC_SHIFT)
+#  define CLOCK_HFCLKSTAT_SRC_HFINT     (0 << CLOCK_HFCLKSTAT_SRC_SHIFT) /* 0b0: 128 MHz internal oscillator (HFINT) */
+#  define CLOCK_HFCLKSTAT_SRC_HFXO      (1 << CLOCK_HFCLKSTAT_SRC_SHIFT) /* 0b1: 128 MHz crystal oscilator (HFXO) */
+#define CLOCK_HFCLKSTAT_STATE           (1 << 16)                        /* Bit 16: HFCLK state */
+
+/* LFCLKRUN Register */
+
+#define CLOCK_LFCLKRUN_STATUS           (1 << 0)  /* Bit 0: LFCLKSTART task triggered status */
+
+/* LFCLKSTAT Register */
+
+#define CLOCK_LFCLKSTAT_SRC_SHIFT       (0)                              /* Bits 0-1: Source of LFCLK */
+#define CLOCK_LFCLKSTAT_SRC_MASK        (3 << CLOCK_LFCLKSTAT_SRC_SHIFT)
+#  define CLOCK_LFCLKSTAT_SRC_LFRC      (1 << CLOCK_LFCLKSTAT_SRC_SHIFT) /* 0b0: 32.768 kHz RC oscillator (LFRC) */
+#  define CLOCK_LFCLKSTAT_SRC_LFXO      (2 << CLOCK_LFCLKSTAT_SRC_SHIFT) /* 0b1: 32.768 kHz crystal oscillator (LFXO) */
+#define CLOCK_LFCLKSTAT_STATE           (1 << 16)                        /* Bit 16: LFCLKSTAT state */
+
+/* LFCLKSRC Register */
+
+#define CLOCK_LFCLKSRC_SRC_SHIFT       (0)       /* Bits 0-1: LFRC clock source */
+#define CLOCK_LFCLKSRC_SRC_MASK        (3 << CLOCK_LFCLKSRC_SRC_SHIFT)
+#  define CLOCK_LFCLKSRC_SRC_RFU       (1 << CLOCK_LFCLKSTAT_SRC_SHIFT)
+#  define CLOCK_LFCLKSRC_SRC_LFRC      (2 << CLOCK_LFCLKSTAT_SRC_SHIFT)
+#  define CLOCK_LFCLKSRC_SRC_LFXO      (3 << CLOCK_LFCLKSTAT_SRC_SHIFT)
+
+#endif /* __ARCH_ARM_SRC_NRF91_HARDWARE_NRF91_CLOCK_H */

arch/arm/src/nrf91/hardware/nrf91_ficr.h

@@ -0,0 +1,59 @@
+/***************************************************************************
+ * arch/arm/src/nrf91/hardware/nrf91_ficr.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ***************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_NRF91_HARDWARE_NRF91_FICR_H
+#define __ARCH_ARM_SRC_NRF91_HARDWARE_NRF91_FICR_H
+
+/***************************************************************************
+ * Included Files
+ ***************************************************************************/
+
+#include <nuttx/config.h>
+#include "hardware/nrf91_memorymap.h"
+
+/***************************************************************************
+ * Pre-processor Definitions
+ ***************************************************************************/
+
+/* FICR Register Offsets ***************************************************/
+
+                                                   /* TODO: SIPINFO */
+#define NRF91_FICR_INFO_DEVICEID0_OFFSET    0x204  /* Device identifier */
+#define NRF91_FICR_INFO_DEVICEID1_OFFSET    0x208  /* Device identifier  */
+#define NRF91_FICR_INFO_RAM_OFFSET          0x218  /* RAM variant */
+#define NRF91_FICR_INFO_FLASH_OFFSET        0x21c  /* Flash variant */
+#define NRF91_FICR_INFO_CODEPAGESIZE_OFFSET 0x220  /* Code memory page size in bytes */
+#define NRF91_FICR_INFO_CODESIZE_OFFSET     0x224  /* Code memory size  */
+#define NRF91_FICR_INFO_DEVICETYPE_OFFSET   0x228  /* Device type */
+                                                   /* TODO */
+
+/* FICR Register Addresses *************************************************/
+
+#define NRF91_FICR_INFO_DEVICEID0           (NRF91_FICR_BASE + NRF91_FICR_INFO_DEVICEID0_OFFSET)
+#define NRF91_FICR_INFO_DEVICEID1           (NRF91_FICR_BASE + NRF91_FICR_INFO_DEVICEID1_OFFSET)
+#define NRF91_FICR_INFO_RAM                 (NRF91_FICR_BASE + NRF91_FICR_INFO_RAM_OFFSET)
+#define NRF91_FICR_INFO_FLASH               (NRF91_FICR_BASE + NRF91_FICR_INFO_FLASH_OFFSET)
+#define NRF91_FICR_INFO_CODEPAGESIZE        (NRF91_FICR_BASE + NRF91_FICR_INFO_CODEPAGESIZE_OFFSET)
+#define NRF91_FICR_INFO_CODESIZE            (NRF91_FICR_BASE + NRF91_FICR_INFO_CODESIZE_OFFSET)
+#define NRF91_FICR_INFO_DEVICETYPE          (NRF91_FICR_BASE + NRF91_FICR_INFO_DEVICETYPE_OFFSET)
+
+/* TODO */
+
+#endif /* __ARCH_ARM_SRC_NRF91_HARDWARE_NRF91_FICR_H */

arch/arm/src/nrf91/hardware/nrf91_gpio.h

@@ -0,0 +1,95 @@
+/****************************************************************************
+ * arch/arm/src/nrf91/hardware/nrf91_gpio.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_NRF91_HARDWARE_NRF91_GPIO_H
+#define __ARCH_ARM_SRC_NRF91_HARDWARE_NRF91_GPIO_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <stdint.h>
+#include "hardware/nrf91_memorymap.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define NRF91_GPIO_NPORTS           2
+#define NRF91_GPIO_PORT0            0
+
+#define NRF91_GPIO_NPINS            32
+
+/* Register offsets *********************************************************/
+
+#define NRF91_GPIO_OUT_OFFSET           0x0004 /* Write GPIO port */
+#define NRF91_GPIO_OUTSET_OFFSET        0x0008 /* Set individual bits in GPIO port */
+#define NRF91_GPIO_OUTCLR_OFFSET        0x000c /* Clear individual bits in GPIO port */
+#define NRF91_GPIO_IN_OFFSET            0x0010 /* Read GPIO port */
+#define NRF91_GPIO_DIR_OFFSET           0x0014 /* Direction of GPIO pins */
+#define NRF91_GPIO_DIRSET_OFFSET        0x0018 /* DIR set register */
+#define NRF91_GPIO_DIRCLR_OFFSET        0x001c /* DIR clear register */
+#define NRF91_GPIO_LATCH_OFFSET         0x0020 /* Latch register  */
+#define NRF91_GPIO_DETECTMODE_OFFSET    0x0024 /* Select between default DETECT signal behaviour and LDETECT mode (non-secure) */
+#define NRF91_GPIO_DETECTMODESEC_OFFSET 0x0024 /* Select between default DETECT signal behaviour and LDETECT mode (secure) */
+
+#define NRF91_GPIO_PIN_CNF_OFFSET(n) (0x0200 + (n << 2))
+
+/* Register addresses *******************************************************/
+
+#define NRF91_GPIO0_OUT              (NRF91_GPIO_P0_BASE + NRF91_GPIO_OUT_OFFSET)
+#define NRF91_GPIO0_OUTSET           (NRF91_GPIO_P0_BASE + NRF91_GPIO_OUTSET_OFFSET)
+#define NRF91_GPIO0_OUTCLR           (NRF91_GPIO_P0_BASE + NRF91_GPIO_OUTCLR_OFFSET)
+#define NRF91_GPIO0_IN               (NRF91_GPIO_P0_BASE + NRF91_GPIO_IN_OFFSET)
+#define NRF91_GPIO0_DIR              (NRF91_GPIO_P0_BASE + NRF91_GPIO_DIR_OFFSET)
+#define NRF91_GPIO0_DIRSET           (NRF91_GPIO_P0_BASE + NRF91_GPIO_DIRSET_OFFSET)
+#define NRF91_GPIO0_DIRCLR           (NRF91_GPIO_P0_BASE + NRF91_GPIO_DIRCLR_OFFSET)
+#define NRF91_GPIO0_CNF(n)           (NRF91_GPIO_P0_BASE + NRF91_GPIO_PIN_CNF_OFFSET(n))
+
+/* Register bit definitions *************************************************/
+
+#define GPIO_DETECTMODE_DEFAULT         (0)
+#define GPIO_DETECTMODE_LDETECT         (1)
+
+#define GPIO_CNF_DIR                    (1 << 0) /* Bit 0: Pin direction */
+#define GPIO_CNF_INPUT                  (1 << 1) /* Bit 1: Input buffer disconnect */
+#define GPIO_CNF_PULL_SHIFT             (2)
+#define GPIO_CNF_PULL_MASK              (0x3 << GPIO_CNF_PULL_SHIFT)
+#  define GPIO_CNF_PULL_DISABLED        (0 << GPIO_CNF_PULL_SHIFT)
+#  define GPIO_CNF_PULL_DOWN            (1 << GPIO_CNF_PULL_SHIFT)
+#  define GPIO_CNF_PULL_UP              (3 << GPIO_CNF_PULL_SHIFT)
+#define GPIO_CNF_DRIVE_SHIFT            (8)
+#define GPIO_CNF_DRIVE_MASK             (0xf << GPIO_CNF_DRIVE_SHIFT)
+#  define GPIO_CNF_DRIVE_S0S1           (0 << GPIO_CNF_DRIVE_SHIFT)
+#  define GPIO_CNF_DRIVE_H0S1           (1 << GPIO_CNF_DRIVE_SHIFT)
+#  define GPIO_CNF_DRIVE_S0H1           (2 << GPIO_CNF_DRIVE_SHIFT)
+#  define GPIO_CNF_DRIVE_H0H1           (3 << GPIO_CNF_DRIVE_SHIFT)
+#  define GPIO_CNF_DRIVE_D0S1           (4 << GPIO_CNF_DRIVE_SHIFT)
+#  define GPIO_CNF_DRIVE_D0H1           (5 << GPIO_CNF_DRIVE_SHIFT)
+#  define GPIO_CNF_DRIVE_S0D1           (6 << GPIO_CNF_DRIVE_SHIFT)
+#  define GPIO_CNF_DRIVE_H0D1           (7 << GPIO_CNF_DRIVE_SHIFT)
+#define GPIO_CNF_SENSE_SHIFT            (16)
+#define GPIO_CNF_SENSE_MASK             (0x3 << GPIO_CNF_SENSE_SHIFT)
+#  define GPIO_CNF_SENSE_DISABLED       (0 << GPIO_CNF_SENSE_SHIFT)
+#  define GPIO_CNF_SENSE_HIGH           (2 << GPIO_CNF_SENSE_SHIFT)
+#  define GPIO_CNF_SENSE_LOW            (3 << GPIO_CNF_SENSE_SHIFT)
+
+#endif /* __ARCH_ARM_SRC_NRF91_HARDWARE_NRF91_GPIO_H */

arch/arm/src/nrf91/hardware/nrf91_ipc.h

@@ -0,0 +1,68 @@
+/****************************************************************************
+ * arch/arm/src/nrf91/hardware/nrf91_ipc.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_NRF91_HARDWARE_NRF91_IPC_H
+#define __ARCH_ARM_SRC_NRF91_HARDWARE_NRF91_IPC_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include "nrf91_memorymap.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define NRF91_IPC_CHANS 8
+
+/* Register offsets *********************************************************/
+
+#define NRF91_IPC_TASKS_SEND_OFFSET(n)      (0x000 + (0x4 * n))  /* Trigger events on IPC channel enabled in SEND_CNF[n] */
+#define NRF91_IPC_SUBSCRIBE_SEND_OFFSET(n)  (0x080 + (0x4 * n))  /* Subscribe configuration for task SEND[n] */
+#define NRF91_IPC_EVENTS_RECEIVE_OFFSET(n)  (0x100 + (0x4 * n))  /* Event received on one or more of the enabled IPC channels in RECEIVE_CNF[n] */
+#define NRF91_IPC_PUBLISH_RECEIVE_OFFSET(n) (0x180 + (0x4 * n))  /* Publish configuration for event RECEIVE[n] */
+#define NRF91_IPC_INTEN_OFFSET              (0x300)              /* Enable or disable interrupt */
+#define NRF91_IPC_INTENSET_OFFSET           (0x304)              /* Enable interrupt */
+#define NRF91_IPC_INTENCLR_OFFSET           (0x308)              /* Disable interrupt */
+#define NRF91_IPC_INTPEND_OFFSET            (0x30C)              /* Pending interrupts */
+#define NRF91_IPC_SEND_CNF_OFFSET(n)        (0x510 + (0x4 * n))  /* Send event configuration for TASKS_SEND[n] */
+#define NRF91_IPC_RECEIVE_CNF_OFFSET(n)     (0x590 + (0x4 * n))  /* Receive event configuration for EVENTS_RECEIVE[n] */
+#define NRF91_IPC_GPMEM_OFFSET(n)           (0x610 + (0x4 * n))  /* General purpose memory */
+
+/* Register definitions *****************************************************/
+
+#define NRF91_IPC_TASKS_SEND(n)             (NRF91_IPC_BASE + NRF91_IPC_TASKS_SEND_OFFSET(n))
+#define NRF91_IPC_SUBSCRIBE_SEND(n)         (NRF91_IPC_BASE + NRF91_IPC_SUBSCRIBE_SEND_OFFSET(n))
+#define NRF91_IPC_EVENTS_RECEIVE(n)         (NRF91_IPC_BASE + NRF91_IPC_EVENTS_RECEIVE_OFFSET(n))
+#define NRF91_IPC_INTEN                     (NRF91_IPC_BASE + NRF91_IPC_INTEN_OFFSET)
+#define NRF91_IPC_INTENSET                  (NRF91_IPC_BASE + NRF91_IPC_INTENSET_OFFSET)
+#define NRF91_IPC_INTENCLR                  (NRF91_IPC_BASE + NRF91_IPC_INTENCLR_OFFSET)
+#define NRF91_IPC_INTPEND                   (NRF91_IPC_BASE + NRF91_IPC_INTPEND_OFFSET)
+#define NRF91_IPC_SEND_CNF(n)               (NRF91_IPC_BASE + NRF91_IPC_SEND_CNF_OFFSET(n))
+#define NRF91_IPC_RECEIVE_CNF(n)            (NRF91_IPC_BASE + NRF91_IPC_RECEIVE_CNF_OFFSET(n))
+#define NRF91_IPC_GPMEM(n)                  (NRF91_IPC_BASE + NRF91_IPC_GPMEM_OFFSET(n))
+
+/* Register bit definitions *************************************************/
+
+#define IPC_CHAN_ID(x)                       (1 << x)  /* Channel ID */
+
+#endif /* __ARCH_ARM_SRC_NRF91_HARDWARE_NRF91_IPC_H */

arch/arm/src/nrf91/hardware/nrf91_memorymap.h

@@ -0,0 +1,158 @@
+/****************************************************************************
+ * arch/arm/src/nrf91/hardware/nrf91_memorymap.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_NRF91_HARDWARE_NRF91_MEMORYMAP_H
+#define __ARCH_ARM_SRC_NRF91_HARDWARE_NRF91_MEMORYMAP_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Memory Map */
+
+#define NRF91_FLASH_BASE        0x00000000 /* Flash memory Start Address */
+#define NRF91_SRAM_BASE         0x20000000 /* SRAM Start Address */
+
+#define NRF91_CORTEXM33_BASE    0xe0000000 /* Cortex-M33 Private Peripheral Bus */
+
+/* Non-secure access address */
+
+#ifdef CONFIG_ARCH_TRUSTZONE_NONSECURE
+#  define NRF91_NS(x)             (x - 0x10000000)
+#else
+#  define NRF91_NS(x)             (x)
+#endif
+
+/* APB Peripherals */
+
+#ifndef CONFIG_ARCH_TRUSTZONE_NONSECURE
+#  define NRF91_SPU_BASE        0x50003000
+#endif
+#define NRF91_REGULATORS_BASE   NRF91_NS(0x50004000)
+#define NRF91_CLOCK_BASE        NRF91_NS(0x50005000)
+#define NRF91_POWER_BASE        NRF91_NS(0x50005000)
+#define NRF91_CTRLAPPERI_BASE   NRF91_NS(0x50006000)
+#define NRF91_SPIM0_BASE        NRF91_NS(0x50008000)
+#define NRF91_SPIS0_BASE        NRF91_NS(0x50008000)
+#define NRF91_TWIM0_BASE        NRF91_NS(0x50008000)
+#define NRF91_TWIS0_BASE        NRF91_NS(0x50008000)
+#define NRF91_UART0_BASE        NRF91_NS(0x50008000)
+#define NRF91_SPIM1_BASE        NRF91_NS(0x50009000)
+#define NRF91_SPIS1_BASE        NRF91_NS(0x50009000)
+#define NRF91_TWIM1_BASE        NRF91_NS(0x50009000)
+#define NRF91_TWIS1_BASE        NRF91_NS(0x50009000)
+#define NRF91_UART1_BASE        NRF91_NS(0x50009000)
+#define NRF91_SPIM2_BASE        NRF91_NS(0x5000A000)
+#define NRF91_SPIS2_BASE        NRF91_NS(0x5000A000)
+#define NRF91_TWIM2_BASE        NRF91_NS(0x5000A000)
+#define NRF91_TWIS2_BASE        NRF91_NS(0x5000A000)
+#define NRF91_UART2_BASE        NRF91_NS(0x5000A000)
+#define NRF91_SPIM3_BASE        NRF91_NS(0x5000C000)
+#define NRF91_SPIS3_BASE        NRF91_NS(0x5000C000)
+#define NRF91_TWIM3_BASE        NRF91_NS(0x5000C000)
+#define NRF91_TWIS3_BASE        NRF91_NS(0x5000C000)
+#define NRF91_UART3_BASE        NRF91_NS(0x5000C000)
+#ifndef CONFIG_ARCH_TRUSTZONE_NONSECURE
+#  define NRF91_GPIOTE0_BASE    0x5000D000
+#endif
+#define NRF91_SAADC_BASE        NRF91_NS(0x5000E000)
+#define NRF91_TIMER0_BASE       NRF91_NS(0x5000F000)
+#define NRF91_TIMER1_BASE       NRF91_NS(0x50010000)
+#define NRF91_TIMER2_BASE       NRF91_NS(0x50011000)
+#define NRF91_RTC0_BASE         NRF91_NS(0x50014000)
+#define NRF91_RTC1_BASE         NRF91_NS(0x50015000)
+#define NRF91_DPPIC_BASE        NRF91_NS(0x50017000)
+#define NRF91_WDT0_BASE         NRF91_NS(0x50018000)
+#define NRF91_WDT1_BASE         NRF91_NS(0x50019000)
+#define NRF91_EGU0_BASE         NRF91_NS(0x5001B000)
+#define NRF91_EGU1_BASE         NRF91_NS(0x5001C000)
+#define NRF91_EGU2_BASE         NRF91_NS(0x5001D000)
+#define NRF91_EGU3_BASE         NRF91_NS(0x5001E000)
+#define NRF91_EGU4_BASE         NRF91_NS(0x5001F000)
+#define NRF91_EGU5_BASE         NRF91_NS(0x50020000)
+#define NRF91_PWM0_BASE         NRF91_NS(0x50021000)
+#define NRF91_PWM1_BASE         NRF91_NS(0x50022000)
+#define NRF91_PWM2_BASE         NRF91_NS(0x50023000)
+#define NRF91_PWM3_BASE         NRF91_NS(0x50024000)
+#define NRF91_PDM0_BASE         NRF91_NS(0x50026000)
+#define NRF91_I2S0_BASE         NRF91_NS(0x50028000)
+#define NRF91_IPC_BASE          NRF91_NS(0x5002A000)
+#define NRF91_FPU_BASE          NRF91_NS(0x5002C000)
+#ifdef CONFIG_ARCH_TRUSTZONE_NONSECURE
+#  define NRF91_GPIOTE1_BASE    0x40031000
+#endif
+#define NRF91_KMU_BASE          NRF91_NS(0x50039000)
+#define NRF91_NVMC_BASE         NRF91_NS(0x50039000)
+#define NRF91_VMC_BASE          NRF91_NS(0x5003A000)
+#ifndef CONFIG_ARCH_TRUSTZONE_NONSECURE
+#  define NRF91_CCHOSTRGF_BASE  0x50840000
+#  define NRF91_CRYPTOCELL_BASE 0x50840000
+#endif
+#define NRF91_GPIO_P0_BASE      NRF91_NS(0x50842500)
+#define NRF91_FICR_BASE         0x00FF0000
+#define NRF91_UICR_BASE         0x00FF8000
+#define NRF91_TAD_BASE          0xE0080000
+
+/* Peripherals IDs */
+
+#define NRF91_SPU_ID            3
+#define NRF91_REGULATORS_ID     4
+#define NRF91_POWER_CLOCK_ID    5
+#define NRF91_CTRLAPPERI_ID     6
+#define NRF91_SERIAL0_ID        8
+#define NRF91_SERIAL1_ID        9
+#define NRF91_SERIAL2_ID        10
+#define NRF91_SERIAL3_ID        11
+#define NRF91_GPIOTE0_ID        13
+#define NRF91_SAADC_ID          14
+#define NRF91_TIMER0_ID         15
+#define NRF91_TIMER1_ID         16
+#define NRF91_TIMER2_ID         17
+#define NRF91_RTC0_ID           20
+#define NRF91_RTC1_ID           21
+#define NRF91_DPPIC_ID          23
+#define NRF91_WDT0_ID           24
+#define NRF91_EGU0_ID           27
+#define NRF91_EGU1_ID           28
+#define NRF91_EGU2_ID           29
+#define NRF91_EGU3_ID           30
+#define NRF91_EGU4_ID           31
+#define NRF91_EGU5_ID           32
+#define NRF91_PWM0_ID           33
+#define NRF91_PWM1_ID           34
+#define NRF91_PWM2_ID           35
+#define NRF91_PWM3_ID           36
+#define NRF91_PDM_ID            38
+#define NRF91_I2S_ID            40
+#define NRF91_IPC_ID            42
+#define NRF91_GPIOTE1_ID        49
+#define NRF91_KMU_ID            57
+#define NRF91_NVMC_ID           57
+#define NRF91_VMC_ID            58
+#define NRF91_CRUPTOCELL_ID     64
+#define NRF91_GPIO0_ID          66
+
+#endif /* __ARCH_ARM_SRC_NRF91_HARDWARE_NRF91_MEMORYMAP_H */

arch/arm/src/nrf91/hardware/nrf91_nvmc.h

@@ -0,0 +1,88 @@
+/****************************************************************************
+ * arch/arm/src/nrf91/hardware/nrf91_nvmc.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_NRF91_HARDWARE_NRF91_NVMC_H
+#define __ARCH_ARM_SRC_NRF91_HARDWARE_NRF91_NVMC_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include "hardware/nrf91_memorymap.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* NVMC Register Offsets ****************************************************/
+
+/* Registers for the NVMC */
+
+#define NRF91_NVMC_READY_OFFSET                0x400  /* Ready flag */
+#define NRF91_NVMC_READYNEXT_OFFSET            0x408  /* Ready flag */
+#define NRF91_NVMC_CONFIG_OFFSET               0x504  /* Configuration register */
+#define NRF91_NVMC_ERASEALL_OFFSET             0x50c  /* Register for erasing all non-volatile user memory */
+#define NRF91_NVMC_ERASEPAGEPARTIALCFG_OFFSET  0x51c  /* Register for partial erase configuration */
+#define NRF91_NVMC_ICACHECNF_OFFSET            0x540  /* I-Code cache configuration register */
+#define NRF91_NVMC_IHIT_OFFSET                 0x548  /* I-Code cache hit counter. */
+#define NRF91_NVMC_IMISS_OFFSET                0x54c  /* I-Code cache miss counter */
+#define NRF91_NVMC_CONFIGNS_OFFSET             0x584  /* Non-secure configuration register */
+#define NRF91_NVMC_WRITEUICRNS_OFFSET          0x588  /* Non-secure APPROTECT enable register */
+
+/* NVMC Register Addresses **************************************************/
+
+#define NRF91_NVMC_READY                 (NRF91_NVMC_BASE + NRF91_NVMC_READY_OFFSET)
+#define NRF91_NVMC_READYNEXT             (NRF91_NVMC_BASE + NRF91_NVMC_READYNEXT_OFFSET)
+#define NRF91_NVMC_CONFIG                (NRF91_NVMC_BASE + NRF91_NVMC_CONFIG_OFFSET)
+#define NRF91_NVMC_ERASEALL              (NRF91_NVMC_BASE + NRF91_NVMC_ERASEALL_OFFSET)
+#define NRF91_NVMC_ERASEPAGEPARTIALCFG   (NRF91_NVMC_BASE + NRF91_NVMC_ERASEPAGEPARTIALCFG_OFFSET)
+#define NRF91_NVMC_ICACHECNF             (NRF91_NVMC_BASE + NRF91_NVMC_ICACHECNF_OFFSET)
+#define NRF91_NVMC_IHIT                  (NRF91_NVMC_BASE + NRF91_NVMC_IHIT_OFFSET)
+#define NRF91_NVMC_IMISS                 (NRF91_NVMC_BASE + NRF91_NVMC_IMISS_OFFSET)
+#define NRF91_NVMC_CONFIGNS              (NRF91_NVMC_BASE + NRF91_NVMC_CONFIGNS_OFFSET)
+#define NRF91_NVMC_WRITEUICRNS           (NRF91_NVMC_BASE + NRF91_NVMC_WRITEUICRNS_OFFSET)
+
+/* NVMC Register Bitfield Definitions ***************************************/
+
+/* READY Register */
+
+#define NVMC_READY_READY                 (1 << 0) /* NVMC is ready */
+
+/* CONFIG Register */
+
+#define NVMC_CONFIG_SHIFT                (0)
+#define NVMC_CONFIG_MASK                 (3 << NVMC_CONFIG_SHIFT)
+#define NVMC_CONFIG_REN                  (0 << NVMC_CONFIG_SHIFT) /* Read-only access */
+#define NVMC_CONFIG_WEN                  (1 << NVMC_CONFIG_SHIFT) /* Write Enabled */
+#define NVMC_CONFIG_EEN                  (2 << NVMC_CONFIG_SHIFT) /* Erase Enabled */
+#define NVMC_CONFIG_PEEN                 (4 << NVMC_CONFIG_SHIFT) /* Partial erase enabled */
+
+/* ICACHECNF Register */
+
+#define NVMC_ICACHECNF_CACHEEN           (1 << 0) /* Cache enable */
+#define NVMC_ICACHECNF_CACHEPROFEN       (1 << 8) /* Cache profiling enable */
+
+/* WRITEUICRNS Register */
+
+#define NVMC_WRITEUICRNS_SET              (1 << 0) /* Allow non-secure code to set APPROTECT */
+#define NVMC_WRITEUICRNS_KEY              (0xAFBE5A7 << 4)
+
+#endif /* __ARCH_ARM_SRC_NRF91_HARDWARE_NRF91_NVMC_H */

arch/arm/src/nrf91/hardware/nrf91_rtc.h

@@ -0,0 +1,110 @@
+/****************************************************************************
+ * arch/arm/src/nrf91/hardware/nrf91_rtc.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_NRF91_HARDWARE_NRF91_RTC_H
+#define __ARCH_ARM_SRC_NRF91_HARDWARE_NRF91_RTC_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include "hardware/nrf91_memorymap.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Register offsets for RTC *************************************************/
+
+#define NRF91_RTC_TASKS_START_OFFSET       0x0000                  /* Start RTC counter */
+#define NRF91_RTC_TASKS_STOP_OFFSET        0x0004                  /* Stop RTC counter */
+#define NRF91_RTC_TASKS_CLEAR_OFFSET       0x0008                  /* Clear RTC counter */
+#define NRF91_RTC_TASKS_TRIGOVRFLW_OFFSET  0x000c                  /* Clear Set counter to 0xfffff0 */
+                                                                   /* TODO: 0x040 - 0x0c */
+#define NRF91_RTC_EVENTS_TICK_OFFSET       0x0100                  /* Event on counter increment */
+#define NRF91_RTC_EVENTS_OVRFLW_OFFSET     0x0104                  /* Event on counter overflow */
+#define NRF91_RTC_EVENTS_COMPARE_OFFSET(x) (0x0140 + ((x) * 0x04)) /* Compare event on CC[x] match */
+                                                                   /* TODO: 0x180 - 0x200 */
+#define NRF91_RTC_INTENSET_OFFSET          0x0304                  /* Enable interrupt */
+#define NRF91_RTC_INTENCLR_OFFSET          0x0308                  /* Disable interrupt */
+#define NRF91_RTC_EVTEN_OFFSET             0x0340                  /* Enable or disable event routing */
+#define NRF91_RTC_EVTENSET_OFFSET          0x0344                  /* Enable event routing */
+#define NRF91_RTC_EVTENCLR_OFFSET          0x0348                  /* Disable event routing */
+#define NRF91_RTC_COUNTER_OFFSET           0x0504                  /* Current counter value */
+#define NRF91_RTC_PRESCALER_OFFSET         0x0508                  /* 12 bit prescaler for counter frequency */
+#define NRF91_RTC_CC_OFFSET(x)             (0x0540 + ((x) * 0x04)) /* Compare register x */
+
+/* Register offsets for RTC *************************************************/
+
+/* TASKS_START Register */
+
+#define RTC_TASKS_START            (1 << 0)                        /* Bit 0: Start RTC counter */
+
+/* TASKS_STOP Register */
+
+#define RTC_TASKS_STOP             (1 << 0)                        /* Bit 0: Stop RTC counter */
+
+/* TASKS_CLEAR Register */
+
+#define RTC_TASKS_CLEAR            (1 << 0)                        /* Bit 0: Clear RTC counter */
+
+/* TASKS_TRIGOVRFLW Register */
+
+#define RTC_TASKS_TRIGOVRFLW       (1 << 0)                        /* Bit 0: Set counter to 0xfffff0 */
+
+/* EVENTS_TICK Register */
+
+#define RTC_EVENTS_TICK            (1 << 0)                        /* Bit 0: Event on counter increment */
+
+/* EVENTS_OVRFLW Register */
+
+#define RTC_EVENTS_OVRFLW          (1 << 0)                        /* Bit 0: Event on counter overflow */
+
+/* EVENTS_COMPARE Register */
+
+#define RTC_EVENTS_COMPARE         (1 << 0)                        /* Bit 0: Eompare event on CC[x] match */
+
+/* INTENSET/INTENCLR Register */
+
+#define RTC_INT_TICK               (1 << 0)                        /* Bit 0: TICK interrupt*/
+#define RTC_INT_OVRFLW             (1 << 1)                        /* Bit 1: OVRFLW interrupt */
+#define RTC_INT_COMPARE(x)         (1 << (16 + (x)))               /* Bit 16-19: COMPARE[x] interrupt */
+
+/* EVTEN/EVTENSET/EVTSENCLR Register */
+
+#define RTC_EVTEN_TICK             (1 << 0)                        /* Bit 0: TICK event */
+#define RTC_EVTEN_OVRFLW           (1 << 1)                        /* Bit 1: OVRFLW event */
+#define RTC_EVTEN_COMPARE(x)       (1 << (16 + (x)))               /* Bit 16-19: COMPARE[x] event */
+
+/* COUNTER Register */
+
+#define RTC_COUNTER_MASK           (0x00ffffff)                    /* Bits 0-23: Counter value */
+
+/* PRESCALER Register */
+
+#define RTC_PRESCALER_MASK         (0x00000fff)                    /* Bits 0-11: Prescaler value */
+#define RTC_PRESCALER_MAX          (0x00000fff)
+
+/* CC Register */
+
+#define RTC_CC_MASK                (0x00ffffff)                    /* Bits 0-23: Compare register */
+
+#endif /* __ARCH_ARM_SRC_NRF91_HARDWARE_NRF91_RTC_H */

arch/arm/src/nrf91/hardware/nrf91_spi.h

@@ -0,0 +1,216 @@
+/****************************************************************************
+ * arch/arm/src/nrf91/hardware/nrf91_spi.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_NRF91_HARDWARE_NRF91_SPI_H
+#define __ARCH_ARM_SRC_NRF91_HARDWARE_NRF91_SPI_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include "hardware/nrf91_memorymap.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Register offsets for SPI master (SPIM) ***********************************/
+
+#define NRF91_SPIM_TASK_START_OFFSET      (0x0010) /* Start SPI transaction */
+#define NRF91_SPIM_TASK_STOP_OFFSET       (0x0014) /* Stop SPI transaction */
+#define NRF91_SPIM_TASK_SUSPEND_OFFSET    (0x001c) /* Suspend SPI transaction */
+#define NRF91_SPIM_TASK_RESUME_OFFSET     (0x0020) /* Resume SPI transaction */
+                                                   /* TODO: 0x090 - 0x0a0 */
+#define NRF91_SPIM_EVENTS_STOPPED_OFFSET  (0x0104) /* SPI transaction has stopped */
+#define NRF91_SPIM_EVENTS_ENDRX_OFFSET    (0x0110) /* End of RXD buffer reached */
+#define NRF91_SPIM_EVENTS_END_OFFSET      (0x0118) /* End of RXD buffer and TXD buffer reached */
+#define NRF91_SPIM_EVENTS_ENDTX_OFFSET    (0x0120) /* End of TXD buffer reached */
+#define NRF91_SPIM_EVENTS_STARTED_OFFSET  (0x014c) /* Transaction started */
+                                                   /* TODO: 0x184 - 0x1cc */
+#define NRF91_SPIM_SHORTS_OFFSET          (0x0200) /* Shortcuts between local events and tasks */
+#define NRF91_SPIM_INTENSET_OFFSET        (0x0304) /* Enable interrupt */
+#define NRF91_SPIM_INTENCLR_OFFSET        (0x0308) /* Disable interrupt */
+#define NRF91_SPIM_STALLSTAT_OFFSET       (0x0400) /* Stall status for EasyDMA RAM accesses */
+#define NRF91_SPIM_ENABLE_OFFSET          (0x0500) /* Enable SPIM */
+#define NRF91_SPIM_PSELSCK_OFFSET         (0x0508) /* Pin select for SCK */
+#define NRF91_SPIM_PSELMOSI_OFFSET        (0x050c) /* Pin select for MOSI */
+#define NRF91_SPIM_PSELMISO_OFFSET        (0x0510) /* Pin select for MISO */
+#define NRF91_SPIM_PSELCSN_OFFSET         (0x0514) /* Pin select for CSN */
+#define NRF91_SPIM_FREQUENCY_OFFSET       (0x0524) /* SPI frequency. */
+#define NRF91_SPIM_RXDPTR_OFFSET          (0x0534) /* Data pointer */
+#define NRF91_SPIM_RXDMAXCNT_OFFSET       (0x0538) /* Maximum number of bytes in receive buffer */
+#define NRF91_SPIM_RXDMAMOUNT_OFFSET      (0x053c) /* Number of bytes transferred in the last transaction */
+#define NRF91_SPIM_RXDLIST_OFFSET         (0x0540) /* RXD EasyDMA list type */
+#define NRF91_SPIM_TXDPTR_OFFSET          (0x0544) /* Data pointer */
+#define NRF91_SPIM_TXDMAXCNT_OFFSET       (0x0548) /* Number of bytes in transmit buffer */
+#define NRF91_SPIM_TXDAMOUNT_OFFSET       (0x054c) /* Number of bytes transferred in the last transaction */
+#define NRF91_SPIM_TXDLIST_OFFSET         (0x0550) /* TXD EasyDMA list type */
+#define NRF91_SPIM_CONFIG_OFFSET          (0x0554) /* Configuration register */
+#define NRF91_SPIM_RXDELAY_OFFSET         (0x0560) /* Sample delay for input serial data on MISO */
+#define NRF91_SPIM_CSNDUR_OFFSET          (0x0564) /* IFTIMING.CSNDUR */
+#define NRF91_SPIM_CSNPOL_OFFSET          (0x0568) /* Polarity of CSN output */
+#define NRF91_SPIM_PSELDCX_OFFSET         (0x056c) /* Pin select for DCX signal */
+#define NRF91_SPIM_DCXCNT_OFFSET          (0x0570) /* DCX configuration */
+#define NRF91_SPIM_ORC_OFFSET             (0x05c0) /* ORC */
+
+/* Register offsets for SPI slave (SPIS) ************************************/
+
+                                                   /* TODO: 0x024 - 0x1a8 */
+#define NRF91_SPIS_SHORTS_OFFSET          (0x0200) /* Shortcuts between local events and tasks */
+#define NRF91_SPIS_INTENSET_OFFSET        (0x0304) /* Enable interrupt */
+#define NRF91_SPIS_INTENCLR_OFFSET        (0x0308) /* Disable interrupt */
+#define NRF91_SPIS_SEMSTAT_OFFSET         (0x0400) /* Semaphore status register */
+#define NRF91_SPIS_STATUS_OFFSET          (0x0440) /* Status from last transaction */
+#define NRF91_SPIS_ENABLE_OFFSET          (0x0500) /* Enable SPIS */
+#define NRF91_SPIS_PSELSCK_OFFSET         (0x0508) /* Pin select for SCK */
+#define NRF91_SPIS_PSELMOSI_OFFSET        (0x050c) /* Pin select for MOSI signal */
+#define NRF91_SPIS_PSELMISO_OFFSET        (0x0510) /* Pin select for MISO signal */
+#define NRF91_SPIS_PSELCSN_OFFSET         (0x0514) /* Pin select for CSN */
+#define NRF91_SPIS_RXDPTR_OFFSET          (0x0534) /* Data pointer */
+#define NRF91_SPIS_RXDMAXCNT_OFFSET       (0x0538) /* Maximum number of bytes in receive buffer */
+#define NRF91_SPIS_RXDMAMOUNT_OFFSET      (0x053c) /* Number of bytes transferred in the last transaction */
+#define NRF91_SPIS_RXDLIST_OFFSET         (0x0540) /* RXD EasyDMA list type */
+#define NRF91_SPIS_TXDPTR_OFFSET          (0x0544) /* Data pointer */
+#define NRF91_SPIS_TXDMAXCNT_OFFSET       (0x0548) /* Number of bytes in transmit buffer */
+#define NRF91_SPIS_TXDAMOUNT_OFFSET       (0x054c) /* Number of bytes transferred in the last transaction */
+#define NRF91_SPIS_TXDLIST_OFFSET         (0x0550) /* TXD EasyDMA list type */
+#define NRF91_SPIS_CONFIG_OFFSET          (0x0554) /* Configuration register */
+#define NRF91_SPIS_DEF_OFFSET             (0x055c) /* Default character */
+#define NRF91_SPIS_ORC_OFFSET             (0x05c0) /* Over-read character */
+
+/* Register Bitfield Definitions for SPIM ***********************************/
+
+/* TASKS_START Register */
+
+#define SPIM_TASKS_START            (1 << 0)  /* Bit 0: Start SPI transaction */
+
+/* TASKS_STOP Register */
+
+#define SPIM_TASKS_STOP             (1 << 0)  /* Bit 0: Stop SPI transaction */
+
+/* TASKS_SUSPEND Register */
+
+#define SPIM_TASKS_SUSPEND          (1 << 0)  /* Bit 0: Suspend SPI transaction */
+
+/* TASKS_RESUME Register */
+
+#define SPIM_TASKS_RESUME           (1 << 0)  /* Bit 0: Resume SPI transaction */
+
+/* EVENTS_STOPPED Register */
+
+#define SPIM_EVENTS_STOPPED         (1 << 0)  /* Bit 0: SPI transaction has stopped */
+
+/* EVENTS_ENDRX Register */
+
+#define SPIM_EVENTS_ENDRX           (1 << 0)  /* Bit 0: End of RXD buffer reached */
+
+/* EVENTS_END Register */
+
+#define SPIM_EVENTS_END             (1 << 0)  /* Bit 0: End of RXD buffer and TXD buffer reached */
+
+/* EVENTS_ENDTX Register */
+
+#define SPIM_EVENTS_ENDTX           (1 << 0)  /* Bit 0: End of TXD buffer reached */
+
+/* EVENTS_STARTED Register */
+
+#define SPIM_EVENTS_STARTED         (1 << 0)  /* Bit 0: Transaction started */
+
+/* SHORTS Register */
+
+#define SPIM_SHORTS_ENDSTART        (1 << 0)  /* Bit 0: Shortcut between event END and task START */
+
+/* INTENSET/INTENCLR Register */
+
+#define SPIM_INT_STOPPED            (1 << 1)  /* Bit 1: Enable interrupt for STOPPED */
+#define SPIM_INT_ENDRX              (1 << 4)  /* Bit 4: Enable interrupt for ENDRX */
+#define SPIM_INT_END                (1 << 6)  /* Bit 6: Enable interrupt for END */
+#define SPIM_INT_ENDTX              (1 << 8)  /* Bit 8: Enable interrupt for ENDTX */
+#define SPIM_INT_STARTED            (1 << 19) /* Bit 19: Enable interrupt for STARTED */
+
+/* STALLLSTAT Register */
+
+#define SPIM_STALLSTAT_RX           (1 << 0)  /* Bit 0: Stall status for EasyDMA RAM reads */
+#define SPIM_STALLSTAT_TX           (1 << 1)  /* Bit 1: Stall status for EasyDMA RAM writes */
+
+/* ENABLE Register */
+
+#define SPIM_ENABLE_DIS             (0)        /* Disable SPIM */
+#define SPIM_ENABLE_EN              (0x7 << 0) /* Enable SPIM */
+
+/* PSEL* Registers */
+
+#define SPIM_PSEL_PIN_SHIFT         (0)       /* Bits 0-4: SCK pin number */
+#define SPIM_PSEL_PIN_MASK          (0x1f << SPIM_PSELSCK_PIN_SHIFT)
+#define SPIM_PSEL_PORT_SHIFT        (5)       /* Bit 5: SCK port number */
+#define SPIM_PSEL_PORT_MASK         (0x1 << SPIM_PSELSCK_PORT_SHIFT)
+#define SPIM_PSEL_CONNECTED         (1 << 31) /* Bit 31: Connection */
+#define SPIM_PSEL_RESET             (0xffffffff)
+
+/* FREQUENCY Register */
+
+#define SPIM_FREQUENCY_125KBPS      (0x02000000) /* 125 kbps */
+#define SPIM_FREQUENCY_250KBPS      (0x04000000) /* 250 kbps */
+#define SPIM_FREQUENCY_500KBPS      (0x08000000) /* 500 kbps */
+#define SPIM_FREQUENCY_1MBPS        (0x10000000) /* 1 Mbps */
+#define SPIM_FREQUENCY_2MBPS        (0x20000000) /* 2 Mbps */
+#define SPIM_FREQUENCY_4MBPS        (0x40000000) /* 4 Mbps */
+#define SPIM_FREQUENCY_8MBPS        (0x80000000) /* 8 Mbps */
+
+/* RXDMAXCNT Register */
+
+#define SPIM_RXDMAXCNT_SHIFT        (0)       /* Bits 0-15: Maximum number of bytes in receive buffer */
+#define SPIM_RXDMAXCNT_MASK         (0xffff << SPIM_RXDMAXCNT_SHIFT)
+
+/* RXDAMOUNT Register */
+
+#define SPIM_RXDAMOUNT_SHIFT        (0)       /* Bits 0-15: Number of bytes transferred in the last transaction */
+#define SPIM_RXDAMOUNT_MASK         (0xffff << SPIM_RXDAMOUNT_SHIFT)
+
+/* TXDMAXCNT Register */
+
+#define SPIM_TXDMAXCNT_SHIFT        (0)       /* Bits 0-15: Maximum number of bytes in transmit buffer */
+#define SPIM_TXDMAXCNT_MASK         (0xffff << SPIM_TXDMAXCNT_MASK)
+
+/* TXDAMOUNT Register */
+
+#define SPIM_TXDAMOUNT_SHIFT        (0)       /* Bits 0-15: Number of bytes transferred in the last transaction */
+#define SPIM_TXDAMOUNT_MASK         (0xffff << SPIM_TXDAMOUNT_SHIFT)
+
+/* CONFIG Register */
+
+#define SPIM_CONFIG_ORDER           (1 << 0)  /* Bit 0: Bit order */
+#define SPIM_CONFIG_CPHA            (1 << 1)  /* Bit 1: Serial clock phase */
+#define SPIM_CONFIG_CPOL            (1 << 2)  /* Bit 2: Serial clock polarity */
+
+/* PSELDCX Register */
+
+#define SPIM_PSELDCX_PIN_SHIFT      (0)       /* Bits 0-4: DCX pin number */
+#define SPIM_PSELDCX_PIN_MASK       (0x1f << SPIM_PSELDCX_PIN_SHIFT)
+#define SPIM_PSELDCX_PORT_SHIFT     (5)       /* Bit 5: SCK port number */
+#define SPIM_PSELDCX_PORT_MASK      (0x1 << SPIM_PSELDCX_PORT_SHIFT)
+#define SPIM_PSELDCX_CONNECTED      (1 << 31) /* Bit 31: Connection */
+
+/* Register Bitfield Definitions for SPIS ***********************************/
+
+/* TODO */
+
+#endif /* __ARCH_ARM_SRC_NRF91_HARDWARE_NRF91_SPI_H */

arch/arm/src/nrf91/hardware/nrf91_spu.h

@@ -0,0 +1,114 @@
+/****************************************************************************
+ * arch/arm/src/nrf91/hardware/nrf91_spu.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_NRF91_HARDWARE_NRF91_SPU_H
+#define __ARCH_ARM_SRC_NRF91_HARDWARE_NRF91_SPU_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include "nrf91_memorymap.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Register offsets *********************************************************/
+
+#define NRF91_SPU_EVENTS_RAMACCERR_OFFSET        0x100                /* A security violation has been detected for the RAM memory space */
+#define NRF91_SPU_EVENTS_FLASHACCERR_OFFSET      0x104                /* A security violation has been detected for the FLASH memory space */
+#define NRF91_SPU_EVENTS_PERIPHACCERR_OFFSET     0x108                /* A security violation has been detected on one or several peripherals */
+#define NRF91_SPU_PUBLISH_RAMACCERR_OFFSET       0x180                /* Publish configuration for event RAMACCERR */
+#define NRF91_SPU_PUBLISH_FLASHACCERR_OFFSET     0x184                /* Publish configuration for event FLASHACCERR */
+#define NRF91_SPU_PUBLISH_PERIPHACCERR_OFFSET    0x188                /* Publish configuration for event PERIPHACCERR */
+#define NRF91_SPU_INTEN_OFFSET                   0x300                /* Enable or disable interrupt */
+#define NRF91_SPU_INTSEL_OFFSET                  0x304                /* Enable interrupt */
+#define NRF91_SPU_INTCLR_OFFSET                  0x308                /* Disable interrupt */
+#define NRF91_SPU_CAP_OFFSET                     0x400                /* Show implemented features for the current device */
+#define NRF91_SPU_CPULOCK_OFFSET                 0x404                /* Configure bits to lock down CPU features at runtime */
+#define NRF91_SPU_EXTDOMAIN_OFFSET(n)            (0x440 + (0x4 * n))  /* Access for bus access generated from the external domain n */
+#define NRF91_SPU_DPPIPERM_OFFSET(n)             (0x480 + (0x8 * n))  /* Select between secure and non-secure attribute for the DPPI channels. */
+#define NRF91_SPU_DPPILOCK_OFFSET(n)             (0x484 + (0x8 * n))  /* Prevent further modification of the corresponding PERM register */
+#define NRF91_SPU_GPIOPORTPERM_OFFSET(n)         (0x4C0 + (0x8 * n))  /* Select between secure and non-secure attribute for pins 0 to 31 of port n. */
+#define NRF91_SPU_GPIOPORTLOCK_OFFSET(n)         (0x4C4 + (0x8 * n))  /* Prevent further modification of the corresponding PERM register */
+#define NRF91_SPU_FLASHNSCREGION_OFFSET(n)       (0x500 + (0x8 * n))  /* Define which flash region can contain the non-secure callable (NSC) region n */
+#define NRF91_SPU_FLASHNSCSIZE_OFFSET(n)         (0x504 + (0x8 * n))  /* Define the size of the non-secure callable (NSC) region n */
+#define NRF91_SPU_RAMNSCREGION_OFFSET(n)         (0x540 + (0x8 * n))  /* Define which RAM region can contain the non-secure callable (NSC) region n */
+#define NRF91_SPU_RAMNSCSIZE_OFFSET(n)           (0x544 + (0x8 * n))  /* Define the size of the non-secure callable (NSC) region n */
+#define NRF91_SPU_FLASHREGIONPERM_OFFSET(n)      (0x600 + (0x4 * n))  /* Access permissions for flash region n */
+#define NRF91_SPU_RAMREGIONPERM_OFFSET(n)        (0x700 + (0x4 * n))  /* Access permissions for RAM region n */
+#define NRF91_SPU_PERIPHIDPERM_OFFSET(n)         (0x800 + (0x4 * n))  /* List capabilities and access permissions for the peripheral with ID n */
+
+/* Register definitions *****************************************************/
+
+#define NRF91_SPU_EVENTS_RAMACCERR        (NRF91_SPU_BASE + NRF91_SPU_EVENTS_RAMACCERR_OFFSET)
+#define NRF91_SPU_EVENTS_FLASHACCERR      (NRF91_SPU_BASE + NRF91_SPU_EVENTS_FLASHACCERR_OFFSET)
+#define NRF91_SPU_EVENTS_PERIPHACCERR     (NRF91_SPU_BASE + NRF91_SPU_EVENTS_PERIPHACCERR_OFFSET)
+#define NRF91_SPU_PUBLISH_RAMACCERR       (NRF91_SPU_BASE + NRF91_SPU_PUBLISH_RAMACCERR_OFFSET)
+#define NRF91_SPU_PUBLISH_FLASHACCERR     (NRF91_SPU_BASE + NRF91_SPU_PUBLISH_FLASHACCERR_OFFSET)
+#define NRF91_SPU_PUBLISH_PERIPHACCERR    (NRF91_SPU_BASE + NRF91_SPU_PUBLISH_PERIPHACCERR_OFFSET)
+#define NRF91_SPU_INTEN                   (NRF91_SPU_BASE + NRF91_SPU_INTEN_OFFSET)
+#define NRF91_SPU_INTSEL                  (NRF91_SPU_BASE + NRF91_SPU_INTSEL_OFFSET)
+#define NRF91_SPU_INTCLR                  (NRF91_SPU_BASE + NRF91_SPU_INTCLR_OFFSET)
+#define NRF91_SPU_CAP                     (NRF91_SPU_BASE + NRF91_SPU_CAP_OFFSET)
+#define NRF91_SPU_CPULOCK                 (NRF91_SPU_BASE + NRF91_SPU_CPULOCK_OFFSET)
+#define NRF91_SPU_EXTDOMAIN(n)            (NRF91_SPU_BASE + NRF91_SPU_EXTDOMAIN_OFFSET(n))
+#define NRF91_SPU_DPPIPERM(n)             (NRF91_SPU_BASE + NRF91_SPU_DPPIPERM_OFFSET(n))
+#define NRF91_SPU_DPPILOCK(n)             (NRF91_SPU_BASE + NRF91_SPU_DPPILOCK_OFFSET(n))
+#define NRF91_SPU_GPIOPORTPERM(n)         (NRF91_SPU_BASE + NRF91_SPU_GPIOPORTPERM_OFFSET(n))
+#define NRF91_SPU_GPIOPORTLOCK(n)         (NRF91_SPU_BASE + NRF91_SPU_GPIOPORTLOCK_OFFSET(n))
+#define NRF91_SPU_FLASHNSCREGION(n)       (NRF91_SPU_BASE + NRF91_SPU_FLASHNSCREGION_OFFSET(n))
+#define NRF91_SPU_FLASHNSCSIZE(n)         (NRF91_SPU_BASE + NRF91_SPU_FLASHNSCSIZE_OFFSET(n))
+#define NRF91_SPU_RAMNSCREGION(n)         (NRF91_SPU_BASE + NRF91_SPU_RAMNSCREGION_OFFSET(n))
+#define NRF91_SPU_RAMNSCSIZE(n)           (NRF91_SPU_BASE + NRF91_SPU_RAMNSCSIZE_OFFSET(n))
+#define NRF91_SPU_FLASHREGIONPERM(n)      (NRF91_SPU_BASE + NRF91_SPU_FLASHREGIONPERM_OFFSET(n))
+#define NRF91_SPU_RAMREGIONPERM(n)        (NRF91_SPU_BASE + NRF91_SPU_RAMREGIONPERM_OFFSET(n))
+#define NRF91_SPU_PERIPHIDPERM(n)         (NRF91_SPU_BASE + NRF91_SPU_PERIPHIDPERM_OFFSET(n))
+
+/* Register bit definitions *************************************************/
+
+#define SPU_RAM_REGIONS                      (32)
+#define SPU_FLASH_REGIONS                    (32)
+
+#define SPU_EXTDOMAIN_SECUREMAPPING_SHIFT    (0)
+#define SPU_EXTDOMAIN_SECUREMAPPING_MASK     (3 << SPU_EXTDOMAIN_SECUREMAPPING_SHIFT)
+#  define SPU_EXTDOMAIN_SECUREMAPPING_NONSEC (0 << SPU_EXTDOMAIN_SECUREMAPPING_SHIFT)
+#  define SPU_EXTDOMAIN_SECUREMAPPING_SEC    (1 << SPU_EXTDOMAIN_SECUREMAPPING_SHIFT)
+#  define SPU_EXTDOMAIN_SECUREMAPPING_USER   (2 << SPU_EXTDOMAIN_SECUREMAPPING_SHIFT)
+#define SPU_EXTDOMAIN_SECUREMAPPING_SECATTR  (1 << 4)
+#define SPU_EXTDOMAIN_SECUREMAPPING_LOCK     (1 << 8)
+
+#define SPU_FLASHREGION_PERM_EXEC            (1 << 0)
+#define SPU_FLASHREGION_PERM_WRITE           (1 << 1)
+#define SPU_FLASHREGION_PERM_READ            (1 << 2)
+#define SPU_FLASHREGION_PERM_SECATTR         (1 << 4)
+#define SPU_FLASHREGION_PERM_LOCK            (1 << 8)
+
+#define SPU_RAMREGION_PERM_EXEC              (1 << 0)
+#define SPU_RAMREGION_PERM_WRITE             (1 << 1)
+#define SPU_RAMREGION_PERM_READ              (1 << 2)
+#define SPU_RAMREGION_PERM_SECATTR           (1 << 4)
+#define SPU_RAMREGION_PERM_LOCK              (1 << 8)
+
+#define SPU_PERM_SECATTR                     (1 << 4)
+
+#endif /* __ARCH_ARM_SRC_NRF91_HARDWARE_NRF91_SPU_H */

arch/arm/src/nrf91/hardware/nrf91_tim.h

@@ -0,0 +1,113 @@
+/****************************************************************************
+ * arch/arm/src/nrf91/hardware/nrf91_tim.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_NRF91_HARDWARE_NRF91_TIM_H
+#define __ARCH_ARM_SRC_NRF91_HARDWARE_NRF91_TIM_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include "hardware/nrf91_memorymap.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* TIMER constants **********************************************************/
+
+#define TIMER_BASE_FERQUENCY              (16000000)
+
+/* Register offsets for TIM *************************************************/
+
+#define NRF91_TIM_TASKS_START_OFFSET       0x0000                  /* Start Timer */
+#define NRF91_TIM_TASKS_STOP_OFFSET        0x0004                  /* Stop Timer */
+#define NRF91_TIM_TASKS_COUNT_OFFSET       0x0008                  /* Increment Timer */
+#define NRF91_TIM_TASKS_CLEAR_OFFSET       0x000c                  /* Clear time */
+#define NRF91_TIM_TASKS_SHUTDOWN_OFFSET    0x0010                  /* Shutdown Timer */
+#define NRF91_TIM_TASKS_CAPTURE_OFFSET(x)  (0x0040 + ((x) * 4))    /* Capture Timer value to CC[x] */
+#define NRF91_TIM_EVENTS_COMPARE_OFFSET(x) (0x0140 + ((x) * 4))    /* Compare event on CC[x] */
+                                                                   /* TODO: 0x080-0x1c0 */
+#define NRF91_TIM_SHORTS_OFFSET            0x0200                  /* Shortcuts between local events and tasks */
+#define NRF91_TIM_INTEN_OFFSET             0x0300                  /* Enable or disable interrupt */
+#define NRF91_TIM_INTENSET_OFFSET          0x0304                  /* Enable interrupt */
+#define NRF91_TIM_INTCLR_OFFSET            0x0308                  /* Disable interrupt */
+#define NRF91_TIM_MODE_OFFSET              0x0504                  /* Timer mode selection */
+#define NRF91_TIM_BITMODE_OFFSET           0x0508                  /* Configure the number of bits used by the Timer */
+#define NRF91_TIM_PRESCALER_OFFSET         0x0510                  /* Timer prescaler register */
+#define NRF91_TIM_CC_OFFSET(x)             (0x0540 + ((x) * 4))    /* Capture/Compare register x */
+#define NRF91_TIM_ONESHOT_OFFSET(x)        (0x0580 + ((x) * 4))    /* Enable one-shot operation for Capture/Compare channel x */
+
+/* Register offsets for TIM *************************************************/
+
+/* TASKS_START Register */
+
+#define TIM_TASKS_START                    (1 << 0)                /* Bit 0: Start Timer */
+
+/* TASKS_STOP Register */
+
+#define TIM_TASKS_STOP                     (1 << 0)                /* Bit 0: Stop Timer */
+
+/* TASKS_COUNT Register */
+
+#define TIM_TASKS_COUNT                    (1 << 0)                /* Bit 0: Increment Timer */
+
+/* TASKS_CLEAR Register */
+
+#define TIM_TASKS_CLEAR                    (1 << 0)                /* Bit 0: Clear Timer */
+
+/* SHORTS Register */
+
+#define TIM_SHORTS_COMPARE_CLEAR(x)        (1 << (x))              /* Bits 0-5: */
+#define TIM_SHORTS_COMPARE_STOP(x)         (1 << (x + 8))          /* Bits 8-13 */
+
+/* INTENSET/INTENCLR Register */
+
+#define TIM_INT_COMPARE(x)                 (1 << (x + 16))         /* Bits 16-21 */
+
+/* MODE Register */
+
+#define TIM_MODE_SHIFT                     (0)                     /* Bits 0-1: Timer mode */
+#define TIM_MODE_MASK                      (0x3 << TIM_MODE_SHIFT)
+#  define TIM_MODE_TIMER                   (0x0 << TIM_MODE_SHIFT) /* 0: Timer mode */
+#  define TIM_MODE_COUNTER                 (0x1 << TIM_MODE_SHIFT) /* 1: Counter mode */
+#  define TIM_MODE_LPCOUNTER               (0x2 << TIM_MODE_SHIFT) /* 2: Low Power Counter mode */
+
+/* BITMODE Register */
+
+#define TIM_BITMODE_SHIFT                  (0)                        /* Bits 0-1: Timer bit width */
+#define TIM_BITMODE_MASK                   (0x3 << TIM_BITMODE_SHIFT)
+#  define TIM_BITMODE_16B                  (0x0 << TIM_BITMODE_SHIFT) /* 0: 16 bit */
+#  define TIM_BITMODE_8B                   (0x1 << TIM_BITMODE_SHIFT) /* 1: 8 bit */
+#  define TIM_BITMODE_24B                  (0x2 << TIM_BITMODE_SHIFT) /* 2: 24 bit */
+#  define TIM_BITMODE_32B                  (0x3 << TIM_BITMODE_SHIFT) /* 3: 32 bit */
+
+/* PRESCALER Register */
+
+#define TIM_PRESCALER_SHIFT                (0)                        /* Bits 0-3: Prescaler value */
+#define TIM_PRESCALER_MAX                  (9)
+#define TIM_PRESCALER_MASK                 (TIM_PRESCALER_MAX << TIM_PRESCALER_SHIFT)
+
+/* ONESHOT Register */
+
+#define TIM_ONESHOT_EN                     (1 << 0)                   /* Bit 0: Enable one-shot operation */
+
+#endif /* __ARCH_ARM_SRC_NRF91_HARDWARE_NRF91_TIM_H */

arch/arm/src/nrf91/hardware/nrf91_twi.h

@@ -0,0 +1,190 @@
+/****************************************************************************
+ * arch/arm/src/nrf91/hardware/nrf91_twi.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_NRF91_HARDWARE_NRF91_TWI_H
+#define __ARCH_ARM_SRC_NRF91_HARDWARE_NRF91_TWI_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include "hardware/nrf91_memorymap.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Register offsets for TWI master (TWIM) ***********************************/
+
+#define NRF91_TWIM_TASKS_STARTRX_OFFSET     0x0000 /* Start TWIM receive sequence */
+#define NRF91_TWIM_TASKS_STARTTX_OFFSET     0x0008 /* Start TWIM transmit sequence */
+#define NRF91_TWIM_TASKS_STOP_OFFSET        0x0014 /* Stop TWIM transaction */
+#define NRF91_TWIM_TASKS_SUSPEND_OFFSET     0x001c /* Suspend TWIM transaction */
+#define NRF91_TWIM_TASKS_RESUME_OFFSET      0x0020 /* Resume TWIM transaction */
+                                                   /* TODO: 0x080 - 0x0a0 */
+#define NRF91_TWIM_EVENTS_STOPPED_OFFSET    0x0104 /* TWIM stopped */
+#define NRF91_TWIM_EVENTS_ERROR_OFFSET      0x0124 /* TWIM error */
+#define NRF91_TWIM_EVENTS_SUSPENDED_OFFSET  0x0148 /* Last byte has been sent out after the SUSPEND task has been issued */
+#define NRF91_TWIM_EVENTS_RXSTARTED_OFFSET  0x014c /* Receive sequence started */
+#define NRF91_TWIM_EVENTS_TXSTARTED_OFFSET  0x0150 /* Transmit sequence started */
+#define NRF91_TWIM_EVENTS_LASTRX_OFFSET     0x015c /* Byte boundary, starting to receive the last byte */
+#define NRF91_TWIM_EVENTS_LASTTX_OFFSET     0x0160 /* Byte boundary, starting to transmit the last byte */
+                                                   /* TODO: 0x184 - 0x1e0 */
+#define NRF91_TWIM_SHORTS_OFFSET            0x0200 /* Shortcuts between local events and tasks */
+#define NRF91_TWIM_INTEN_OFFSET             0x0300 /* Enable or disable interrupt */
+#define NRF91_TWIM_INTENSET_OFFSET          0x0304 /* Enable interrupt */
+#define NRF91_TWIM_INTENCLR_OFFSET          0x0308 /* Disable interrupt */
+#define NRF91_TWIM_ERRORSRC_OFFSET          0x04c4 /* Error source */
+#define NRF91_TWIM_ENABLE_OFFSET            0x0500 /* Enable TWIMS */
+#define NRF91_TWIM_PSELSCL_OFFSET           0x0508 /* Pin select for SCL signal */
+#define NRF91_TWIM_PSELSDA_OFFSET           0x050c /* Pin select for SDA signal */
+#define NRF91_TWIM_FREQUENCY_OFFSET         0x0524 /* TWIM frequency */
+#define NRF91_TWIM_RXDPTR_OFFSET            0x0534 /* RXD Data pointer */
+#define NRF91_TWIM_RXDMAXCNT_OFFSET         0x0538 /* Maximum number of bytes in RXD buffer */
+#define NRF91_TWIM_RXDAMOUNT_OFFSET         0x053c /* Number of bytes transferred in the last RXD transaction */
+#define NRF91_TWIM_RXDLIST_OFFSET           0x0540 /* RX EasyDMA list type */
+#define NRF91_TWIM_TXDPTR_OFFSET            0x0544 /* TXD Data pointer */
+#define NRF91_TWIM_TXMAXCNT_OFFSET          0x0548 /* Maximum number of bytes in TXD buffer */
+#define NRF91_TWIM_TXAMOUNT_OFFSET          0x054c /* Number of bytes transferred in the last TXD transaction */
+#define NRF91_TWIM_TXLIST_OFFSET            0x0550 /* TX EasyDMA list type */
+#define NRF91_TWIM_ADDRESS_OFFSET           0x0588 /* TWIM address */
+
+/* Register offsets for TWI slave (TWIS) ************************************/
+
+#define NRF91_TWIS_TASKS_STOP_OFFSET        0x0014 /* Stop TWIS transaction */
+#define NRF91_TWIS_TASKS_SUSPEND_OFFSET     0x001c /* Suspend TWIS transaction */
+#define NRF91_TWIS_TASKS_RESUME_OFFSET      0x0020 /* Resume TWIS transaction */
+#define NRF91_TWIS_TASKS_PREPARERX_OFFSET   0x0030 /* Prepare the TWIS slave to respond to a write command */
+#define NRF91_TWIS_TASKS_PREPARETX_OFFSET   0x0034 /* Prepare the TWIS slave to respond to a read command */
+#define NRF91_TWIS_EVENTS_STOPPED_OFFSET    0x0104 /* TWIS stopped */
+#define NRF91_TWIS_EVENTS_ERROR_OFFSET      0x0124 /* TWIS error */
+#define NRF91_TWIS_EVENTS_RXSTARTED_OFFSET  0x014c /* Receive sequence started */
+#define NRF91_TWIS_EVENTS_TXSTARTED_OFFSET  0x0150 /* Transmit sequence started */
+#define NRF91_TWIS_EVENTS_WRITE_OFFSET      0x0164 /* Write command received */
+#define NRF91_TWIS_EVENTS_READ_OFFSET       0x0168 /* Read command received */
+#define NRF91_TWIS_SHORTS_OFFSET            0x0200 /* Shortcuts between local events and tasks */
+#define NRF91_TWIS_INTEN_OFFSET             0x0300 /* Enable or disable interrupt */
+#define NRF91_TWIS_INTENSET_OFFSET          0x0304 /* Enable interrupt */
+#define NRF91_TWIS_INTENCLR_OFFSET          0x0308 /* Disable interrupt */
+#define NRF91_TWIS_ERRORSRC_OFFSET          0x04d0 /* Error source */
+#define NRF91_TWIS_MATCH_OFFSET             0x04d4 /* Status register indicating which address had a match */
+#define NRF91_TWIS_ENABLE_OFFSET            0x0500 /* Enable TWISS */
+#define NRF91_TWIS_PSELSCL_OFFSET           0x0508 /* Pin select for SCL signal */
+#define NRF91_TWIS_PSELSDA_OFFSET           0x050c /* Pin select for SDA signal */
+#define NRF91_TWIS_RXDPTR_OFFSET            0x0534 /* RXD Data pointer */
+#define NRF91_TWIS_RXDMAXCNT_OFFSET         0x0538 /* Maximum number of bytes in RXD buffer */
+#define NRF91_TWIS_RXDAMOUNT_OFFSET         0x053c /* Number of bytes transferred in the last RXD transaction */
+#define NRF91_TWIS_RXDLIST_OFFSET           0x0540 /* RX EasyDMA list type */
+#define NRF91_TWIS_TXDPTR_OFFSET            0x0544 /* TXD Data pointer */
+#define NRF91_TWIS_TXMAXCNT_OFFSET          0x0548 /* Maximum number of bytes in TXD buffer */
+#define NRF91_TWIS_TXAMOUNT_OFFSET          0x054c /* Number of bytes transferred in the last TXD transaction */
+#define NRF91_TWIS_TXLIST_OFFSET            0x0550 /* TX EasyDMA list type */
+#define NRF91_TWIS_ADDRESS0_OFFSET          0x0588 /* TWIS address 0 */
+#define NRF91_TWIS_ADDRESS1_OFFSET          0x058c /* TWIS address 1 */
+#define NRF91_TWIS_CONFIG_OFFSET            0x0594 /* Configuration register for the address match mechanism */
+#define NRF91_TWIS_ORC_OFFSET               0x05c0 /* Over-read character */
+
+/* Register Bitfield Definitions for TWIM ***********************************/
+
+/* SHORTS Register */
+
+#define TWIM_SHORTS_LASTTX_STARTRX          (1 << 7)   /* Bit 7: Shortcut between event LASTTX and task STARTRX */
+#define TWIM_SHORTS_LASTTX_SUSPEND          (1 << 8)   /* Bit 8: Shortcut between event LASTTX and task SUSPEND */
+#define TWIM_SHORTS_LASTTX_STOP             (1 << 9)   /* Bit 9: Shortcut between event LASTTX and task STOP */
+#define TWIM_SHORTS_LASTRX_STARTTX          (1 << 10)  /* Bit 10: Shortcut between event LASTRX and task STARTTX */
+#define TWIM_SHORTS_LASTRX_SUSPEND          (1 << 11)  /* Bit 11: Shortcut between event LASTRX and task SUSPEND */
+#define TWIM_SHORTS_LASTRX_STOP             (1 << 12)  /* Bit 12: Shortcut between event LASTRX and task STOP */
+
+/* INTEN/INTENSET/INTENCLR Register */
+
+#define TWIM_INT_STOPPED                    (1 << 1)   /* Bit 1: Interrupt for event STOPPED */
+#define TWIM_INT_ERROR                      (1 << 9)   /* Bit 9: Interrupt for event ERROR */
+#define TWIM_INT_SUSPENDED                  (1 << 18)  /* Bit 18: Interrupt for event SUSPENDED */
+#define TWIM_INT_RXSTARTED                  (1 << 19)  /* Bit 19: Interrupt for event RXSTARTED */
+#define TWIM_INT_TXSTARTED                  (1 << 20)  /* Bit 20: Interrupt for event TXSTARTED */
+#define TWIM_INT_LASTRX                     (1 << 23)  /* Bit 23: Interrupt for event LASTRX */
+#define TWIM_INT_LASTTX                     (1 << 24)  /* Bit 24: Interrupt for event LASTTX */
+
+/* ERRORSRC Register */
+
+#define TWIM_ERRORSRC_OVERRUN               (1 << 0)   /* Bit 0: Overrun error */
+#define TWIM_ERRORSRC_ANACK                 (1 << 1)   /* Bit 1: NACK received after sending the address */
+#define TWIM_ERRORSRC_DNACK                 (1 << 2)   /* Bit 2: NACK received after sending a data byte */
+
+/* ENABLE Register */
+
+#define TWIM_ENABLE_DIS                     (0)        /* Disable TWIM */
+#define TWIM_ENABLE_EN                      (0x6 << 0) /* Disable TWIM */
+
+/* PSELSCL Register */
+
+#define TWIM_PSELSCL_PIN_SHIFT              (0)        /* Bits 0-4: SCL pin number */
+#define TWIM_PSELSCL_PIN_MASK               (0x1f << TWIM_PSELSCL_PIN_SHIFT)
+#define TWIM_PSELSCL_PORT_SHIFT             (5)        /* Bit 5: SCL port number */
+#define TWIM_PSELSCL_PORT_MASK              (0x1 << TWIM_PSELSCL_PORT_SHIFT)
+#define TWIM_PSELSCL_CONNECTED              (1 << 31)  /* Bit 31: Connection */
+#define TWIM_PSELSCL_RESET                  (0xffffffff)
+
+/* PSELSDA Register */
+
+#define TWIM_PSELSDA_PIN_SHIFT              (0)        /* Bits 0-4: SDA pin number */
+#define TWIM_PSELSDA_PIN_MASK               (0x1f << TWIM_PSELSDA_PIN_SHIFT)
+#define TWIM_PSELSDA_PORT_SHIFT             (5)        /* Bit 5: SDA port number */
+#define TWIM_PSELSDA_PORT_MASK              (0x1 << TWIM_PSELSDA_PORT_SHIFT)
+#define TWIM_PSELSDA_CONNECTED              (1 << 31)  /* Bit 31: Connection */
+#define TWIM_PSELSDA_RESET                  (0xffffffff)
+
+/* FREQUENCY Register */
+
+#define TWIM_FREQUENCY_100KBPS              (0x01980000) /* 100 kbps */
+#define TWIM_FREQUENCY_250KBPS              (0x04000000) /* 250 kbps */
+#define TWIM_FREQUENCY_400KBPS              (0x06400000) /* 400 kbps */
+
+/* RXDMAXCNT Register */
+
+#define TWIM_RXDMAXCNT_SHIFT                (0)        /* Bits 0-15: Maximum number of bytes in receive buffer */
+#define TWIM_RXDMAXCNT_MASK                 (0xffff << TWIM_RXDMAXCNT_SHIFT)
+
+/* RXDAMOUNT Register */
+
+#define TWIM_RXDAMOUNT_SHIFT                (0)        /* Bits 0-15: Number of bytes transferred in the last transaction */
+#define TWIM_RXDAMOUNT_MASK                 (0xffff << TWIM_RXDAMOUNT_SHIFT)
+
+/* TXDMAXCNT Register */
+
+#define TWIM_TXDMAXCNT_SHIFT                (0)        /* Bits 0-15: Maximum number of bytes in transmit buffer */
+#define TWIM_TXDMAXCNT_MASK                 (0xffff << TWIM_TXDMAXCNT_SHIFT)
+
+/* TXDAMOUNT Register */
+
+#define TWIM_TXDAMOUNT_SHIFT                (0)        /* Bits 0-15: Number of bytes transferred in the last transaction */
+#define TWIM_TXDAMOUNT_MASK                 (0xffff << TWIM_TXDAMOUNT_SHIFT)
+
+/* ADDRESS Register */
+
+#define TWIM_ADDRESS_SHIFT                  (0)        /* Bits 0-6: Address used in the TWI transfer */
+#define TWIM_ADDRESS_MASK                   (0x7f << TWIM_ADDRESS_SHIFT)
+
+/* Register Bitfield Definitions for TWIS ***********************************/
+
+/* TODO */
+
+#endif /* __ARCH_ARM_SRC_NRF91_HARDWARE_NRF91_TWI_H */

arch/arm/src/nrf91/hardware/nrf91_uarte.h

@@ -0,0 +1,306 @@
+/***************************************************************************
+ * arch/arm/src/nrf91/hardware/nrf91_uarte.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ***************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_NRF91_HARDWARE_NRF91_UARTE_H
+#define __ARCH_ARM_SRC_NRF91_HARDWARE_NRF91_UARTE_H
+
+/***************************************************************************
+ * Included Files
+ ***************************************************************************/
+
+#include <nuttx/config.h>
+#include "hardware/nrf91_memorymap.h"
+
+/***************************************************************************
+ * Pre-processor Definitions
+ ***************************************************************************/
+
+/* UART/UARTE Register Offsets *********************************************/
+
+#define NRF91_UARTE_TASKS_STARTRX_OFFSET    0x0000  /* Start UART receiver */
+#define NRF91_UARTE_TASKS_STOPRX_OFFSET     0x0004  /* Stop UART receiver */
+#define NRF91_UARTE_TASKS_STARTTX_OFFSET    0x0008  /* Start UART transmitter */
+#define NRF91_UARTE_TASKS_STOPTX_OFFSET     0x000c  /* Stop UART transmitter */
+#define NRF91_UARTE_TASKS_FLUSHRX_OFFSET    0x002c  /* Flush RX FIFO into RX buffer */
+#define NRF91_UARTE_EVENTS_CTS_OFFSET       0x0100  /* CTS is activated (set low). Clear To Send. */
+#define NRF91_UARTE_EVENTS_NCTS_OFFSET      0x0104  /* CTS is deactivated (set high). Not Clear To Send. */
+#define NRF91_UARTE_EVENTS_RXDRDY_OFFSET    0x0108  /* Data received in RXD (but potentially not yet transferred to Data RAM) */
+#define NRF91_UARTE_EVENTS_ENDRX_OFFSET     0x0110  /* Receive buffer is filled up */
+#define NRF91_UARTE_EVENTS_TXDRDY_OFFSET    0x011c  /* Data sent from TXD */
+#define NRF91_UARTE_EVENTS_ENDTX_OFFSET     0x0120  /* Last TX byte transmitted */
+#define NRF91_UARTE_EVENTS_ERROR_OFFSET     0x0124  /* Error detected */
+#define NRF91_UARTE_EVENTS_RXTO_OFFSET      0x0144  /* Receiver timeout */
+#define NRF91_UARTE_EVENTS_RXSTARTED_OFFSET 0x014c  /* UART receiver has started */
+#define NRF91_UARTE_EVENTS_TXSTARTED_OFFSET 0x0150  /* UART transmitter has started */
+#define NRF91_UARTE_EVENTS_TXSTOPPED_OFFSET 0x0158  /* Transmitter stopped */
+#define NRF91_UARTE_SHORTS_OFFSET           0x0200  /* Shortcut register */
+#define NRF91_UARTE_INTEN_OFFSET            0x0300  /* Enable or disable interrupt */
+#define NRF91_UARTE_INTENSET_OFFSET         0x0304  /* Enable interrupt */
+#define NRF91_UARTE_INTENCLR_OFFSET         0x0308  /* Disable interrupt */
+#define NRF91_UARTE_ERRORSRC_OFFSET         0x0480  /* Error source */
+#define NRF91_UARTE_ENABLE_OFFSET           0x0500  /* Enable UART */
+#define NRF91_UARTE_PSEL_RTS_OFFSET         0x0508  /* Pin select for RTS signal */
+#define NRF91_UARTE_PSEL_TXD_OFFSET         0x050c  /* Pin select for TXD signal */
+#define NRF91_UARTE_PSEL_CTS_OFFSET         0x0510  /* Pin select for CTS signal */
+#define NRF91_UARTE_PSEL_RXD_OFFSET         0x0514  /* Pin select for RXD signal */
+#define NRF91_UARTE_BAUDRATE_OFFSET         0x0524  /* Baud rate. Accuracy depends on the HFCLK source selected. */
+#define NRF91_UARTE_RXD_PTR_OFFSET          0x0534  /* Data pointer */
+#define NRF91_UARTE_RXD_MAXCNT_OFFSET       0x0538  /* Maximum number of bytes in receive buffer */
+#define NRF91_UARTE_RXD_AMOUNT_OFFSET       0x053c  /* Number of bytes transferred in the last transaction */
+#define NRF91_UARTE_TXD_PTR_OFFSET          0x0544  /* Data pointer */
+#define NRF91_UARTE_TXD_MAXCNT_OFFSET       0x0548  /* Maximum number of bytes in transmit buffer */
+#define NRF91_UARTE_TXD_AMOUNT_OFFSET       0x054c  /* Number of bytes transferred in the last transaction */
+#define NRF91_UARTE_CONFIG_OFFSET           0x056c  /* Configuration of parity and hardware flow control */
+
+#define NRF91_UART_TASKS_STARTRX_OFFSET     0x0000 /* Start UART receiver */
+#define NRF91_UART_TASKS_STOPRX_OFFSET      0x0004 /* Stop UART receiver */
+#define NRF91_UART_TASKS_STARTTX_OFFSET     0x0008 /* Start UART transmitter */
+#define NRF91_UART_TASKS_STOPTX_OFFSET      0x000c /* Stop UART transmitter */
+#define NRF91_UART_TASKS_SUSPEND_OFFSET     0x001c /* Suspend UART */
+#define NRF91_UART_EVENTS_CTS_OFFSET        0x0100 /* CTS is activated (set low). Clear To Send. */
+#define NRF91_UART_EVENTS_NCTS_OFFSET       0x0104 /* CTS is deactivated (set high). Not Clear To Send. */
+#define NRF91_UART_EVENTS_RXDRDY_OFFSET     0x0108 /* Data received in RXD */
+#define NRF91_UART_EVENTS_TXDRDY_OFFSET     0x011c /* Data sent from TXD */
+#define NRF91_UART_EVENTS_ERROR_OFFSET      0x0124 /* Error detected */
+#define NRF91_UART_EVENTS_RXTO_OFFSET       0x0144 /* Receiver timeout */
+#define NRF91_UART_SHORTS_OFFSET            0x0200 /* Shortcut register */
+#define NRF91_UART_INTENSET_OFFSET          0x0304 /* Enable interrupt */
+#define NRF91_UART_INTENCLR_OFFSET          0x0308 /* Disable interrupt */
+#define NRF91_UART_ERRORSRC_OFFSET          0x0480 /* Error source */
+#define NRF91_UART_ENABLE_OFFSET            0x0500 /* Enable UART */
+#define NRF91_UART_PSELRTS_OFFSET           0x0508 /* Pin select for RTS */
+#define NRF91_UART_PSELTXD_OFFSET           0x050c /* Pin select for TXD */
+#define NRF91_UART_PSELCTS_OFFSET           0x0510 /* Pin select for CTS */
+#define NRF91_UART_PSELRXD_OFFSET           0x0514 /* Pin select for RXD */
+#define NRF91_UART_RXD_OFFSET               0x0518 /* RXD register */
+#define NRF91_UART_TXD_OFFSET               0x051c /* TXD register */
+#define NRF91_UART_BAUDRATE_OFFSET          0x0524 /* Baud rate */
+#define NRF91_UART_CONFIG_OFFSET            0x056c /* Configuration of parity and hardware flow control */
+
+/* UART/UARTE Register Addresses *******************************************/
+
+#define NRF91_UARTE0_TASKS_STARTRX          (NRF91_UARTE0_BASE + NRF91_UARTE_TASKS_STARTRX_OFFSET)
+#define NRF91_UARTE0_TASKS_STOPRX           (NRF91_UARTE0_BASE + NRF91_UARTE_TASKS_STOPRX_OFFSET)
+#define NRF91_UARTE0_TASKS_STARTTX          (NRF91_UARTE0_BASE + NRF91_UARTE_TASKS_STARTTX_OFFSET)
+#define NRF91_UARTE0_TASKS_STOPTX           (NRF91_UARTE0_BASE + NRF91_UARTE_TASKS_STOPTX_OFFSET)
+#define NRF91_UARTE0_TASKS_FLUSHRX          (NRF91_UARTE0_BASE + NRF91_UARTE_TASKS_FLUSHRX_OFFSET)
+#define NRF91_UARTE0_EVENTS_CTS             (NRF91_UARTE0_BASE + NRF91_UARTE_EVENTS_CTS_OFFSET)
+#define NRF91_UARTE0_EVENTS_NCTS            (NRF91_UARTE0_BASE + NRF91_UARTE_EVENTS_NCTS_OFFSET)
+#define NRF91_UARTE0_EVENTS_RXDRDY          (NRF91_UARTE0_BASE + NRF91_UARTE_EVENTS_RXDRDY_OFFSET)
+#define NRF91_UARTE0_EVENTS_ENDRX           (NRF91_UARTE0_BASE + NRF91_UARTE_EVENTS_ENDRX_OFFSET)
+#define NRF91_UARTE0_EVENTS_TXDRDY          (NRF91_UARTE0_BASE + NRF91_UARTE_EVENTS_TXDRDY_OFFSET)
+#define NRF91_UARTE0_EVENTS_ENDTX           (NRF91_UARTE0_BASE + NRF91_UARTE_EVENTS_ENDTX_OFFSET)
+#define NRF91_UARTE0_EVENTS_ERROR           (NRF91_UARTE0_BASE + NRF91_UARTE_EVENTS_ERROR_OFFSET)
+#define NRF91_UARTE0_EVENTS_RXTO            (NRF91_UARTE0_BASE + NRF91_UARTE_EVENTS_RXTO_OFFSET)
+#define NRF91_UARTE0_EVENTS_RXSTARTED       (NRF91_UARTE0_BASE + NRF91_UARTE_EVENTS_RXSTARTED_OFFSET)
+#define NRF91_UARTE0_EVENTS_TXSTARTED       (NRF91_UARTE0_BASE + NRF91_UARTE_EVENTS_TXSTARTED_OFFSET)
+#define NRF91_UARTE0_EVENTS_TXSTOPPED       (NRF91_UARTE0_BASE + NRF91_UARTE_EVENTS_TXSTOPPED_OFFSET)
+#define NRF91_UARTE0_SHORTS                 (NRF91_UARTE0_BASE + NRF91_UARTE_SHORTS_OFFSET)
+#define NRF91_UARTE0_INTEN                  (NRF91_UARTE0_BASE + NRF91_UARTE_INTEN_OFFSET)
+#define NRF91_UARTE0_INTENSET               (NRF91_UARTE0_BASE + NRF91_UARTE_INTENSET_OFFSET)
+#define NRF91_UARTE0_INTENCLR               (NRF91_UARTE0_BASE + NRF91_UARTE_INTENCLR_OFFSET)
+#define NRF91_UARTE0_ERRORSRC               (NRF91_UARTE0_BASE + NRF91_UARTE_ERRORSRC_OFFSET)
+#define NRF91_UARTE0_ENABLE                 (NRF91_UARTE0_BASE + NRF91_UARTE_ENABLE_OFFSET)
+#define NRF91_UARTE0_PSEL_RTS               (NRF91_UARTE0_BASE + NRF91_UARTE_PSEL_RTS_OFFSET)
+#define NRF91_UARTE0_PSEL_TXD               (NRF91_UARTE0_BASE + NRF91_UARTE_PSEL_TXD_OFFSET)
+#define NRF91_UARTE0_PSEL_CTS               (NRF91_UARTE0_BASE + NRF91_UARTE_PSEL_CTS_OFFSET)
+#define NRF91_UARTE0_PSEL_RXD               (NRF91_UARTE0_BASE + NRF91_UARTE_PSEL_RXD_OFFSET)
+#define NRF91_UARTE0_BAUDRATE               (NRF91_UARTE0_BASE + NRF91_UARTE_BAUDRATE_OFFSET)
+#define NRF91_UARTE0_RXD_PTR                (NRF91_UARTE0_BASE + NRF91_UARTE_RXD_PTR_OFFSET)
+#define NRF91_UARTE0_RXD_MAXCNT             (NRF91_UARTE0_BASE + NRF91_UARTE_RXD_MAXCNT_OFFSET)
+#define NRF91_UARTE0_RXD_AMOUNT             (NRF91_UARTE0_BASE + NRF91_UARTE_RXD_AMOUNT_OFFSET)
+#define NRF91_UARTE0_TXD_PTR                (NRF91_UARTE0_BASE + NRF91_UARTE_TXD_PTR_OFFSET)
+#define NRF91_UARTE0_TXD_MAXCNT             (NRF91_UARTE0_BASE + NRF91_UARTE_TXD_MAXCNT_OFFSET)
+#define NRF91_UARTE0_TXD_AMOUNT             (NRF91_UARTE0_BASE + NRF91_UARTE_TXD_AMOUNT_OFFSET)
+#define NRF91_UARTE0_CONFIG                 (NRF91_UARTE0_BASE + NRF91_UARTE_CONFIG_OFFSET)
+
+#define NRF91_UART0_TASKS_STARTRX           (NRF91_UART0_BASE + NRF91_UART_TASKS_STARTRX_OFFSET)
+#define NRF91_UART0_TASKS_STOPRX            (NRF91_UART0_BASE + NRF91_UART_TASKS_STOPRX_OFFSET)
+#define NRF91_UART0_TASKS_STARTTX           (NRF91_UART0_BASE + NRF91_UART_TASKS_STARTTX_OFFSET)
+#define NRF91_UART0_TASKS_STOPTX            (NRF91_UART0_BASE + NRF91_UART_TASKS_STOPTX_OFFSET)
+#define NRF91_UART0_TASKS_SUSPEND           (NRF91_UART0_BASE + NRF91_UART_TASKS_SUSPEND_OFFSET)
+#define NRF91_UART0_EVENTS_CTS              (NRF91_UART0_BASE + NRF91_UART_EVENTS_CTS_OFFSET)
+#define NRF91_UART0_EVENTS_NCTS             (NRF91_UART0_BASE + NRF91_UART_EVENTS_NCTS_OFFSET)
+#define NRF91_UART0_EVENTS_RXDRDY           (NRF91_UART0_BASE + NRF91_UART_EVENTS_RXDRDY_OFFSET)
+#define NRF91_UART0_EVENTS_TXDRDY           (NRF91_UART0_BASE + NRF91_UART_EVENTS_TXDRDY_OFFSET)
+#define NRF91_UART0_EVENTS_ERROR            (NRF91_UART0_BASE + NRF91_UART_EVENTS_ERROR_OFFSET)
+#define NRF91_UART0_EVENTS_RXTO             (NRF91_UART0_BASE + NRF91_UART_EVENTS_RXTO_OFFSET)
+#define NRF91_UART0_SHORTS                  (NRF91_UART0_BASE + NRF91_UART_SHORTS_OFFSET)
+#define NRF91_UART0_INTENSET                (NRF91_UART0_BASE + NRF91_UART_INTENSET_OFFSET)
+#define NRF91_UART0_INTENCLR                (NRF91_UART0_BASE + NRF91_UART_INTENCLR_OFFSET)
+#define NRF91_UART0_ERRORSRC                (NRF91_UART0_BASE + NRF91_UART_ERRORSRC_OFFSET)
+#define NRF91_UART0_ENABLE                  (NRF91_UART0_BASE + NRF91_UART_ENABLE_OFFSET)
+#define NRF91_UART0_PSELRTS                 (NRF91_UART0_BASE + NRF91_UART_PSELRTS_OFFSET)
+#define NRF91_UART0_PSELTXD                 (NRF91_UART0_BASE + NRF91_UART_PSELTXD_OFFSET)
+#define NRF91_UART0_PSELCTS                 (NRF91_UART0_BASE + NRF91_UART_PSELCTS_OFFSET)
+#define NRF91_UART0_PSELRXD                 (NRF91_UART0_BASE + NRF91_UART_PSELRXD_OFFSET)
+#define NRF91_UART0_RXD                     (NRF91_UART0_BASE + NRF91_UART_RXD_OFFSET)
+#define NRF91_UART0_TXD                     (NRF91_UART0_BASE + NRF91_UART_TXD_OFFSET)
+#define NRF91_UART0_BAUDRATE                (NRF91_UART0_BASE + NRF91_UART_BAUDRATE_OFFSET)
+#define NRF91_UART0_CONFIG                  (NRF91_UART0_BASE + NRF91_UART_CONFIG_OFFSET)
+
+#ifdef CONFIG_NRF91_UART1
+#  define NRF91_UARTE1_TASKS_STARTRX        (NRF91_UARTE1_BASE + NRF91_UARTE_TASKS_STARTRX_OFFSET)
+#  define NRF91_UARTE1_TASKS_STOPRX         (NRF91_UARTE1_BASE + NRF91_UARTE_TASKS_STOPRX_OFFSET)
+#  define NRF91_UARTE1_TASKS_STARTTX        (NRF91_UARTE1_BASE + NRF91_UARTE_TASKS_STARTTX_OFFSET)
+#  define NRF91_UARTE1_TASKS_STOPTX         (NRF91_UARTE1_BASE + NRF91_UARTE_TASKS_STOPTX_OFFSET)
+#  define NRF91_UARTE1_TASKS_FLUSHRX        (NRF91_UARTE1_BASE + NRF91_UARTE_TASKS_FLUSHRX_OFFSET)
+#  define NRF91_UARTE1_EVENTS_CTS           (NRF91_UARTE1_BASE + NRF91_UARTE_EVENTS_CTS_OFFSET)
+#  define NRF91_UARTE1_EVENTS_NCTS          (NRF91_UARTE1_BASE + NRF91_UARTE_EVENTS_NCTS_OFFSET)
+#  define NRF91_UARTE1_EVENTS_RXDRDY        (NRF91_UARTE1_BASE + NRF91_UARTE_EVENTS_RXDRDY_OFFSET)
+#  define NRF91_UARTE1_EVENTS_ENDRX         (NRF91_UARTE1_BASE + NRF91_UARTE_EVENTS_ENDRX_OFFSET)
+#  define NRF91_UARTE1_EVENTS_TXDRDY        (NRF91_UARTE1_BASE + NRF91_UARTE_EVENTS_TXDRDY_OFFSET)
+#  define NRF91_UARTE1_EVENTS_ENDTX         (NRF91_UARTE1_BASE + NRF91_UARTE_EVENTS_ENDTX_OFFSET)
+#  define NRF91_UARTE1_EVENTS_ERROR         (NRF91_UARTE1_BASE + NRF91_UARTE_EVENTS_ERROR_OFFSET)
+#  define NRF91_UARTE1_EVENTS_RXTO          (NRF91_UARTE1_BASE + NRF91_UARTE_EVENTS_RXTO_OFFSET)
+#  define NRF91_UARTE1_EVENTS_RXSTARTED     (NRF91_UARTE1_BASE + NRF91_UARTE_EVENTS_RXSTARTED_OFFSET)
+#  define NRF91_UARTE1_EVENTS_TXSTARTED     (NRF91_UARTE1_BASE + NRF91_UARTE_EVENTS_TXSTARTED_OFFSET)
+#  define NRF91_UARTE1_EVENTS_TXSTOPPED     (NRF91_UARTE1_BASE + NRF91_UARTE_EVENTS_TXSTOPPED_OFFSET)
+#  define NRF91_UARTE1_SHORTS               (NRF91_UARTE1_BASE + NRF91_UARTE_SHORTS_OFFSET)
+#  define NRF91_UARTE1_INTEN                (NRF91_UARTE1_BASE + NRF91_UARTE_INTEN_OFFSET)
+#  define NRF91_UARTE1_INTENSET             (NRF91_UARTE1_BASE + NRF91_UARTE_INTENSET_OFFSET)
+#  define NRF91_UARTE1_INTENCLR             (NRF91_UARTE1_BASE + NRF91_UARTE_INTENCLR_OFFSET)
+#  define NRF91_UARTE1_ERRORSRC             (NRF91_UARTE1_BASE + NRF91_UARTE_ERRORSRC_OFFSET)
+#  define NRF91_UARTE1_ENABLE               (NRF91_UARTE1_BASE + NRF91_UARTE_ENABLE_OFFSET)
+#  define NRF91_UARTE1_PSEL_RTS             (NRF91_UARTE1_BASE + NRF91_UARTE_PSEL_RTS_OFFSET)
+#  define NRF91_UARTE1_PSEL_TXD             (NRF91_UARTE1_BASE + NRF91_UARTE_PSEL_TXD_OFFSET)
+#  define NRF91_UARTE1_PSEL_CTS             (NRF91_UARTE1_BASE + NRF91_UARTE_PSEL_CTS_OFFSET)
+#  define NRF91_UARTE1_PSEL_RXD             (NRF91_UARTE1_BASE + NRF91_UARTE_PSEL_RXD_OFFSET)
+#  define NRF91_UARTE1_BAUDRATE             (NRF91_UARTE1_BASE + NRF91_UARTE_BAUDRATE_OFFSET)
+#  define NRF91_UARTE1_RXD_PTR              (NRF91_UARTE1_BASE + NRF91_UARTE_RXD_PTR_OFFSET)
+#  define NRF91_UARTE1_RXD_MAXCNT           (NRF91_UARTE1_BASE + NRF91_UARTE_RXD_MAXCNT_OFFSET)
+#  define NRF91_UARTE1_RXD_AMOUNT           (NRF91_UARTE1_BASE + NRF91_UARTE_RXD_AMOUNT_OFFSET)
+#  define NRF91_UARTE1_TXD_PTR              (NRF91_UARTE1_BASE + NRF91_UARTE_TXD_PTR_OFFSET)
+#  define NRF91_UARTE1_TXD_MAXCNT           (NRF91_UARTE1_BASE + NRF91_UARTE_TXD_MAXCNT_OFFSET)
+#  define NRF91_UARTE1_TXD_AMOUNT           (NRF91_UARTE1_BASE + NRF91_UARTE_TXD_AMOUNT_OFFSET)
+#  define NRF91_UARTE1_CONFIG               (NRF91_UARTE1_BASE + NRF91_UARTE_CONFIG_OFFSET)
+
+#  define NRF91_UART1_TASKS_STARTRX         (NRF91_UART1_BASE + NRF91_UART_TASKS_STARTRX_OFFSET)
+#  define NRF91_UART1_TASKS_STOPRX          (NRF91_UART1_BASE + NRF91_UART_TASKS_STOPRX_OFFSET)
+#  define NRF91_UART1_TASKS_STARTTX         (NRF91_UART1_BASE + NRF91_UART_TASKS_STARTTX_OFFSET)
+#  define NRF91_UART1_TASKS_STOPTX          (NRF91_UART1_BASE + NRF91_UART_TASKS_STOPTX_OFFSET)
+#  define NRF91_UART1_TASKS_SUSPEND         (NRF91_UART1_BASE + NRF91_UART_TASKS_SUSPEND_OFFSET)
+#  define NRF91_UART1_EVENTS_CTS            (NRF91_UART1_BASE + NRF91_UART_EVENTS_CTS_OFFSET)
+#  define NRF91_UART1_EVENTS_NCTS           (NRF91_UART1_BASE + NRF91_UART_EVENTS_NCTS_OFFSET)
+#  define NRF91_UART1_EVENTS_RXDRDY         (NRF91_UART1_BASE + NRF91_UART_EVENTS_RXDRDY_OFFSET)
+#  define NRF91_UART1_EVENTS_TXDRDY         (NRF91_UART1_BASE + NRF91_UART_EVENTS_TXDRDY_OFFSET)
+#  define NRF91_UART1_EVENTS_ERROR          (NRF91_UART1_BASE + NRF91_UART_EVENTS_ERROR_OFFSET)
+#  define NRF91_UART1_EVENTS_RXTO           (NRF91_UART1_BASE + NRF91_UART_EVENTS_RXTO_OFFSET)
+#  define NRF91_UART1_SHORTS                (NRF91_UART1_BASE + NRF91_UART_SHORTS_OFFSET)
+#  define NRF91_UART1_INTENSET              (NRF91_UART1_BASE + NRF91_UART_INTENSET_OFFSET)
+#  define NRF91_UART1_INTENCLR              (NRF91_UART1_BASE + NRF91_UART_INTENCLR_OFFSET)
+#  define NRF91_UART1_ERRORSRC              (NRF91_UART1_BASE + NRF91_UART_ERRORSRC_OFFSET)
+#  define NRF91_UART1_ENABLE                (NRF91_UART1_BASE + NRF91_UART_ENABLE_OFFSET)
+#  define NRF91_UART1_PSELRTS               (NRF91_UART1_BASE + NRF91_UART_PSELRTS_OFFSET)
+#  define NRF91_UART1_PSELTXD               (NRF91_UART1_BASE + NRF91_UART_PSELTXD_OFFSET)
+#  define NRF91_UART1_PSELCTS               (NRF91_UART1_BASE + NRF91_UART_PSELCTS_OFFSET)
+#  define NRF91_UART1_PSELRXD               (NRF91_UART1_BASE + NRF91_UART_PSELRXD_OFFSET)
+#  define NRF91_UART1_RXD                   (NRF91_UART1_BASE + NRF91_UART_RXD_OFFSET)
+#  define NRF91_UART1_TXD                   (NRF91_UART1_BASE + NRF91_UART_TXD_OFFSET)
+#  define NRF91_UART1_BAUDRATE              (NRF91_UART1_BASE + NRF91_UART_BAUDRATE_OFFSET)
+#  define NRF91_UART1_CONFIG                (NRF91_UART1_BASE + NRF91_UART_CONFIG_OFFSET)
+#endif
+
+/* UART Register Bitfield Definitions **************************************/
+
+/* PSELRTS Register */
+
+#define UART_PSELRTS_PIN_SHIFT              (0)       /* Bits 0-4: Pin number*/
+#define UART_PSELRTS_PIN_MASK               (0x1f << UART_PSELRTS_PIN_SHIFT)
+#define UART_PSELRTS_PORT_SHIFT             (5)       /* Bit 5: Port number */
+#define UART_PSELRTS_PORT_MASK              (0x1 << UART_PSELRTS_PORT_SHIFT)
+#define UART_PSELRTS_CONNECT                (1 << 31) /* Bit 31: Connection */
+#define UART_PSELRTS_RESET                  (0xffffffff)
+
+/* PSELTXD Register */
+
+#define UART_PSELTXD_PIN_SHIFT              (0)       /* Bits 0-4: Pin number*/
+#define UART_PSELTXD_PIN_MASK               (0x1f << UART_PSELTXD_PIN_SHIFT)
+#define UART_PSELTXD_PORT_SHIFT             (5)       /* Bit 5: Port number */
+#define UART_PSELTXD_PORT_MASK              (0x1 << UART_PSELTXD_PORT_SHIFT)
+#define UART_PSELTXD_CONNECT                (1 << 31) /* Bit 31: Connection */
+#define UART_PSELTXD_RESET                  (0xffffffff)
+
+/* PSELCTS Register */
+
+#define UART_PSELCTS_PIN_SHIFT              (0)       /* Bits 0-4: Pin number*/
+#define UART_PSELCTS_PIN_MASK               (0x1f << UART_PSELCTS_PIN_SHIFT)
+#define UART_PSELCTS_PORT_SHIFT             (5)       /* Bit 5: Port number */
+#define UART_PSELCTS_PORT_MASK              (0x1 << UART_PSELCTS_PORT_SHIFT)
+#define UART_PSELCTS_CONNECT                (1 << 31) /* Bit 31: Connection */
+#define UART_PSELCTS_RESET                  (0xffffffff)
+
+/* PSELRXD Register */
+
+#define UART_PSELRXD_PIN_SHIFT              (0)       /* Bits 0-4: Pin number*/
+#define UART_PSELRXD_PIN_MASK               (0x1f << UART_PSELRXD_PIN_SHIFT)
+#define UART_PSELRXD_PORT_SHIFT             (5)       /* Bit 5: Port number */
+#define UART_PSELRXD_PORT_MASK              (0x1 << UART_PSELRXD_PORT_SHIFT)
+#define UART_PSELRXD_CONNECT                (1 << 31) /* Bit 31: Connection */
+#define UART_PSELRXD_RESET                  (0xffffffff)
+
+/* ENABLE Register */
+
+#define NRF91_UART_ENABLE_DISABLE           (0)
+#define NRF91_UART_ENABLE_ENABLE            (8)
+
+/* INTEN/INTENSET/INTENCLR Register */
+
+#define UART_INT_CTS                        (1 << 0)
+#define UART_INT_NCTS                       (1 << 1)
+#define UART_INT_RXDRDY                     (1 << 2)
+#define UART_INT_ENDRX                      (1 << 4)
+#define UART_INT_TXDRDY                     (1 << 7)
+#define UART_INT_ENDTX                      (1 << 8)
+#define UART_INT_ERROR                      (1 << 9)
+#define UART_INT_RXTO                       (1 << 17)
+#define UART_INT_RXSTARTED                  (1 << 19)
+#define UART_INT_TXSTARTED                  (1 << 20)
+#define UART_INT_TXSTOPPED                  (1 << 22)
+
+/* BAUDRATE Register */
+
+#define UART_BAUDRATE_1200                  (0x0004f000)
+#define UART_BAUDRATE_2400                  (0x0009d000)
+#define UART_BAUDRATE_4800                  (0x0013b000)
+#define UART_BAUDRATE_9600                  (0x00275000)
+#define UART_BAUDRATE_14400                 (0x003af000)
+#define UART_BAUDRATE_19200                 (0x004ea000)
+#define UART_BAUDRATE_28800                 (0x0075c000)
+#define UART_BAUDRATE_31250                 (0x00800000)
+#define UART_BAUDRATE_38400                 (0x009d0000)
+#define UART_BAUDRATE_56000                 (0x00e50000)
+#define UART_BAUDRATE_57600                 (0x00eb0000)
+#define UART_BAUDRATE_76000                 (0x013a9000)
+#define UART_BAUDRATE_115200                (0x01d60000)
+#define UART_BAUDRATE_230400                (0x03b00000)
+#define UART_BAUDRATE_250000                (0x04000000)
+#define UART_BAUDRATE_460800                (0x07400000)
+#define UART_BAUDRATE_921600                (0x0f000000)
+#define UART_BAUDRATE_1000000               (0x10000000)
+
+/* CONFIG Register */
+
+#define UART_CONFIG_HWFC                    (1 << 0) /* Bit 0: Hardware flow control */
+#define UART_CONFIG_PARITY_SHIFT            (1)      /* Bits 1-3: Parity */
+#define UART_CONFIG_PARITY                  (7 << UART_CONFIG_PARITY_SHIFT)
+#define UART_CONFIG_STOP                    (1 << 4) /* Bit 4: Stop bits */
+
+#endif /* __ARCH_ARM_SRC_NRF91_HARDWARE_NRF91!_UARTE_H */

arch/arm/src/nrf91/hardware/nrf91_uicr.h

@@ -0,0 +1,63 @@
+/***************************************************************************
+ * arch/arm/src/nrf91/hardware/nrf91_uicr.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ***************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_NRF91_HARDWARE_NRF91_UICR_H
+#define __ARCH_ARM_SRC_NRF91_HARDWARE_NRF91_UICR_H
+
+/***************************************************************************
+ * Included Files
+ ***************************************************************************/
+
+#include <nuttx/config.h>
+#include "hardware/nrf91_memorymap.h"
+
+/***************************************************************************
+ * Pre-processor Definitions
+ ***************************************************************************/
+
+/* UICR Register Offsets ***************************************************/
+
+#define NRF91_UICR_APPROTECT_OFFSET         0x000  /* Access port protection */
+#define NRF91_UICR_XOSC32M_OFFSET           0x014  /* Oscillator control */
+#define NRF91_UICR_HFXOSRC_OFFSET           0x01C  /* HFXO clock source selection */
+#define NRF91_UICR_HFXOCNT_OFFSET           0x020  /* HFXO startup counter */
+#define NRF91_UICR_APPNVMCPOFGUARD_OFFSET   0x024  /* Enable blocking NVM WRITE and aborting NVM ERASE for Application NVM in POFWARN condition */
+#define NRF91_UICR_SECUREAPPROTECT_OFFSET   0x02c  /* Secure access port protection */
+#define NRF91_UICR_ERASEPROTECT_OFFSET      0x030  /* Erase protection */
+#define NRF91_UICR_OTP_OFFSET               0x100  /* One time programmable memory */
+#define NRF91_UICR_KEYSLOTCONFIGDEST_OFFSET 0x400  /* Key slot destination address */
+#define NRF91_UICR_KEYSLOTCONFIGPERM_OFFSET 0x404  /* Permissions for the key slot */
+#define NRF91_UICR_KEYSLOTKEYVALUE_OFFSET   0x800  /* Define bits [31+o*32:0+o*32] of value assigned to KMU key slot. */
+
+/* UICR Register Addresses *************************************************/
+
+#define NRF91_UICR_APPROTECT         (NRF91_UICR_BASE + NRF91_UICR_APPROTECT_OFFSET)
+#define NRF91_UICR_XOSC32M           (NRF91_UICR_BASE + NRF91_UICR_XOSC32M_OFFSET)
+#define NRF91_UICR_HFXOSRC           (NRF91_UICR_BASE + NRF91_UICR_HFXOSRC_OFFSET)
+#define NRF91_UICR_HFXOCNT           (NRF91_UICR_BASE + NRF91_UICR_HFXOCNT_OFFSET)
+#define NRF91_UICR_APPNVMCPOFGUARD   (NRF91_UICR_BASE + NRF91_UICR_APPNVMCPOFGUARD_OFFSET)
+#define NRF91_UICR_SECUREAPPROTECT   (NRF91_UICR_BASE + NRF91_UICR_SECUREAPPROTECT_OFFSET)
+#define NRF91_UICR_ERASEPROTECT      (NRF91_UICR_BASE + NRF91_UICR_ERASEPROTECT_OFFSET)
+#define NRF91_UICR_OTP               (NRF91_UICR_BASE + NRF91_UICR_OTP_OFFSET)
+#define NRF91_UICR_KEYSLOTCONFIGDEST (NRF91_UICR_BASE + NRF91_UICR_KEYSLOTCONFIGDEST_OFFSET)
+#define NRF91_UICR_KEYSLOTCONFIGPERM (NRF91_UICR_BASE + NRF91_UICR_KEYSLOTCONFIGPERM_OFFSET)
+#define NRF91_UICR_KEYSLOTKEYVALUE   (NRF91_UICR_BASE + NRF91_UICR_KEYSLOTKEYVALUE_OFFSET)
+
+#endif /* __ARCH_ARM_SRC_NRF91_HARDWARE_NRF91_UICR_H */

arch/arm/src/nrf91/hardware/nrf91_utils.h

@@ -0,0 +1,109 @@
+/****************************************************************************
+ * arch/arm/src/nrf91/hardware/nrf91_utils.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_NRF91_HARDWARE_NRF91_UTILS_H
+#define __ARCH_ARM_SRC_NRF91_HARDWARE_NRF91_UTILS_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+/****************************************************************************
+ * Public Function Prototypes / Inline Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: nrf91_clrpend
+ *
+ * Description:
+ *   Clear a pending interrupt at the NVIC.  This does not seem to be
+ *   required for most interrupts.
+ *
+ ****************************************************************************/
+
+void nrf91_clrpend(int irq);
+
+/****************************************************************************
+ * Name: nrf91_easydma_valid
+ *
+ * Description:
+ *   Validate if easyDMA transfer is possible.
+ *
+ ****************************************************************************/
+
+bool nrf91_easydma_valid(uint32_t addr);
+
+/****************************************************************************
+ * Name: nrf91_task_trigger
+ *
+ * Description:
+ *   trigger the special task which is passed from task parameter
+ *
+ ****************************************************************************/
+
+static inline void nrf91_task_trigger(uint32_t task)
+{
+  putreg32(1, task);
+}
+
+/****************************************************************************
+ * Name: nrf91_event_clear
+ *
+ * Description:
+ *   clear the Event
+ *
+ ****************************************************************************/
+
+static inline void nrf91_event_clear(uint32_t event)
+{
+  putreg32(0, event);
+}
+
+/****************************************************************************
+ * Name: nrf91_interrupt_enable
+ *
+ * Description:
+ *   Enable the bitfield interrupt
+ *
+ ****************************************************************************/
+
+static inline void nrf91_interrupt_enable(uint32_t reg_intenset,
+                                          uint32_t bitfield)
+{
+  putreg32(bitfield, reg_intenset);
+}
+
+/****************************************************************************
+ * Name: nrf91_interrupt_disable
+ *
+ * Description:
+ *   Disable the bitfield interrupt
+ *
+ ****************************************************************************/
+
+static inline void nrf91_interrupt_disable(uint32_t reg_intenclr,
+                                           uint32_t bitfield)
+{
+  putreg32(bitfield, reg_intenclr);
+}
+
+#endif /* __ARCH_ARM_SRC_NRF91_HARDWARE_NRF91_UTILS_H */

arch/arm/src/nrf91/nrf91_allocateheap.c

@@ -0,0 +1,191 @@
+/****************************************************************************
+ * arch/arm/src/nrf91/nrf91_allocateheap.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <assert.h>
+#include <debug.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/board.h>
+#include <nuttx/kmalloc.h>
+#include <nuttx/userspace.h>
+
+#include "arm_internal.h"
+#include "hardware/nrf91_memorymap.h"
+
+#include <arch/board/board.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Configuration ************************************************************/
+
+/* .bss and .data is always positioned in internal SRAM.  The remaining SRAM
+ * after the static .bss, .data, and IDLE stack allocations are always added
+ * to the heap.
+ */
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/* _sbss is the start of the BSS region (see the linker script) _ebss is the
+ * end of the BSS region (see the linker script). The idle task stack starts
+ * at the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE.  The IDLE
+ * thread is the thread that the system boots on and, eventually, becomes the
+ * idle, do nothing task that runs only when there is nothing else to run.
+ * The heap continues from there until the configured end of memory.
+ * g_idle_topstack is the beginning of this heap region (not necessarily
+ * aligned).
+ */
+
+const uintptr_t g_idle_topstack = (uintptr_t)_ebss +
+    CONFIG_IDLETHREAD_STACKSIZE;
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_allocate_heap/up_allocate_kheap
+ *
+ * Description:
+ *   This function will be called to dynamically set aside the heap region.
+ *
+ *   - For the normal "flat" build, this function returns the size of the
+ *     single heap.
+ *   - For the protected build (CONFIG_BUILD_PROTECTED=y) with both kernel-
+ *     and user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function
+ *     provides the size of the unprotected, user-space heap.
+ *   - For the kernel build (CONFIG_BUILD_KERNEL=y), this function provides
+ *     the size of the protected, kernel-space heap.
+ *
+ *   If a protected kernel-space heap is provided, the kernel heap must be
+ *   allocated by an analogous up_allocate_kheap(). A custom version of this
+ *   file is needed if memory protection of the kernel heap is required.
+ *
+ *   The following memory map is assumed for the flat build:
+ *
+ *     .data region.  Size determined at link time.
+ *     .bss  region  Size determined at link time.
+ *     IDLE thread stack.  Size determined by CONFIG_IDLETHREAD_STACKSIZE.
+ *     Heap.  Extends to the end of SRAM.
+ *
+ *   The following memory map is assumed for the kernel build:
+ *
+ *     Kernel .data region.  Size determined at link time.
+ *     Kernel .bss  region  Size determined at link time.
+ *     Kernel IDLE thread stack.  Size determined by
+ *     CONFIG_IDLETHREAD_STACKSIZE.
+ *     Padding for alignment
+ *     User .data region.  Size determined at link time.
+ *     User .bss region  Size determined at link time.
+ *     Kernel heap.  Size determined by CONFIG_MM_KERNEL_HEAPSIZE.
+ *     User heap.  Extends to the end of SRAM.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_BUILD_KERNEL
+void up_allocate_kheap(void **heap_start, size_t *heap_size)
+#else
+void up_allocate_heap(void **heap_start, size_t *heap_size)
+#endif
+{
+#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
+  /* Get the unaligned size and position of the user-space heap.
+   * This heap begins after the user-space .bss section at an offset
+   * of CONFIG_MM_KERNEL_HEAPSIZE (subject to alignment).
+   */
+
+  uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend +
+                               CONFIG_MM_KERNEL_HEAPSIZE;
+  size_t    usize = CONFIG_RAM_END - ubase;
+
+  DEBUGASSERT(ubase < (uintptr_t)CONFIG_RAM_END);
+
+  /* Return the user-space heap settings */
+
+  board_autoled_on(LED_HEAPALLOCATE);
+  *heap_start = (void *)ubase;
+  *heap_size  = usize;
+#else
+
+  /* Return the heap settings */
+
+  board_autoled_on(LED_HEAPALLOCATE);
+  *heap_start = (void *)g_idle_topstack;
+  *heap_size  = CONFIG_RAM_END - g_idle_topstack;
+#endif
+}
+
+/****************************************************************************
+ * Name: up_allocate_kheap
+ *
+ * Description:
+ *   For the kernel build (CONFIG_BUILD_PROTECTED/KERNEL=y) with both kernel-
+ *   and user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function allocates
+ *   the kernel-space heap.  A custom version of this function is needed if
+ *   memory protection of the kernel heap is required.
+ *
+ ****************************************************************************/
+
+#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
+void up_allocate_kheap(void **heap_start, size_t *heap_size)
+{
+  /* Get the unaligned size and position of the user-space heap.
+   * This heap begins after the user-space .bss section at an offset
+   * of CONFIG_MM_KERNEL_HEAPSIZE (subject to alignment).
+   */
+
+  uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend +
+                               CONFIG_MM_KERNEL_HEAPSIZE;
+  DEBUGASSERT(ubase < (uintptr_t)CONFIG_RAM_END);
+
+  /* Return the kernel heap settings (i.e., the part of the heap region
+   * that was not dedicated to the user heap).
+   */
+
+  *heap_start = (void *)USERSPACE->us_bssend;
+  *heap_size  = ubase - (uintptr_t)USERSPACE->us_bssend;
+}
+#endif
+
+/****************************************************************************
+ * Name: arm_addregion
+ *
+ * Description:
+ *   Memory may be added in non-contiguous chunks.  Additional chunks are
+ *   added by calling this function.
+ *
+ ****************************************************************************/
+
+#if CONFIG_MM_REGIONS > 1
+void arm_addregion(void)
+{
+}
+#endif /* CONFIG_MM_REGIONS > 1 */

arch/arm/src/nrf91/nrf91_clockconfig.c

@@ -0,0 +1,103 @@
+/****************************************************************************
+ * arch/arm/src/nrf91/nrf91_clockconfig.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <debug.h>
+
+#include <nuttx/arch.h>
+#include <arch/board/board.h>
+
+#include "arm_internal.h"
+#include "nrf91_clockconfig.h"
+#include "hardware/nrf91_clock.h"
+#include "hardware/nrf91_power.h"
+#include "hardware/nrf91_gpio.h"
+
+#ifdef CONFIG_NRF91_APPCORE
+#  include "nrf91_oscconfig.h"
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: nrf91_clockconfig
+ *
+ * Description:
+ *   Called to initialize the NRF91xxx.  This does whatever setup is needed
+ *   to put the MCU in a usable state.  This includes the initialization of
+ *   clocking using the settings in board.h.  This function also performs
+ *   other low-level chip as necessary.
+ *
+ ****************************************************************************/
+
+void nrf91_clockconfig(void)
+{
+#ifdef CONFIG_NRF91_HFCLK_XTAL
+  /* Initialize HFCLK crystal oscillator */
+
+  putreg32(0x0, NRF91_CLOCK_EVENTS_HFCLKSTARTED);
+  putreg32(0x1, NRF91_CLOCK_TASKS_HFCLKSTART);
+
+  while (!getreg32(NRF91_CLOCK_EVENTS_HFCLKSTARTED))
+    {
+      /* wait for external oscillator to start */
+    }
+#endif
+
+#ifdef CONFIG_NRF91_USE_LFCLK
+  /* Initialize LFCLK */
+
+#if defined(CONFIG_NRF91_LFCLK_XTAL)
+  putreg32(CLOCK_LFCLKSRC_SRC_LFXO, NRF91_CLOCK_LFCLKSRC);
+#elif defined(CONFIG_NRF91_LFCLK_SYNTH)
+  putreg32(CLOCK_LFCLKSRC_SRC_LFSYNT, NRF91_CLOCK_LFCLKSRC);
+#else
+  putreg32(CLOCK_LFCLKSRC_SRC_LFRC, NRF91_CLOCK_LFCLKSRC);
+#endif
+
+  /* Trigger LFCLK start */
+
+  putreg32(0x0, NRF91_CLOCK_EVENTS_LFCLKSTARTED);
+  putreg32(0x1, NRF91_CLOCK_TASKS_LFCLKSTART);
+
+  /* NOTE: Oscillator must be configured on the app core */
+
+  while (!getreg32(NRF91_CLOCK_EVENTS_LFCLKSTARTED))
+    {
+      /* Wait for LFCLK to be running */
+    }
+
+#if defined(CONFIG_NRF91_LFCLK_RC)
+  /* TODO: calibrate LFCLK RC oscillator */
+#endif
+#endif
+}

arch/arm/src/nrf91/nrf91_clockconfig.h

@@ -0,0 +1,79 @@
+/****************************************************************************
+ * arch/arm/src/nrf91/nrf91_clockconfig.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_NRF91_NRF91_CLOCKCONFIG_H
+#define __ARCH_ARM_SRC_NRF91_NRF91_CLOCKCONFIG_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Frequencies of internal clocks */
+
+#define NRF91_SYSTEM_CLOCK     64000000  /* Default System clock value */
+#define NRF91_RTC_CLOCK           32768  /* RTC oscillator 32 kHz output
+                                          * (32k_clk)
+                                          */
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: nrf91_clockconfig
+ *
+ * Description:
+ *   Called to initialize the NRF91xxx.  This does whatever setup is needed
+ *   to put the MCU in a usable state.  This includes the initialization of
+ *   clocking using the settings in board.h.  This function also performs
+ *   other low-level chip as necessary.
+ *
+ ****************************************************************************/
+
+void nrf91_clockconfig(void);
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_ARM_SRC_NRF91_NRF91_CLOCKCONFIG_H */

arch/arm/src/nrf91/nrf91_config.h

@@ -0,0 +1,83 @@
+/****************************************************************************
+ * arch/arm/src/nrf91/nrf91_config.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_NRF91_NRF91_CONFIG_H
+#define __ARCH_ARM_SRC_NRF91_NRF91_CONFIG_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <arch/board/board.h>
+
+#include "chip.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Configuration ************************************************************/
+
+/* Make sure that no unsupported UART, I2C master, or SPI master peripherals
+ * are enabled.
+ */
+
+/* Map logical UART names (Just for simplicity of naming) */
+
+#undef HAVE_UART0
+#undef HAVE_UART1
+
+#ifdef CONFIG_NRF91_UART0
+#  define HAVE_UART0 1
+#endif
+
+#ifdef CONFIG_NRF91_UART1
+#  define HAVE_UART1 1
+#endif
+
+/* Check if we have a UART device */
+
+#undef CONFIG_NRF91_HAVE_UART
+#undef HAVE_UART_DEVICE
+
+#if defined(HAVE_UART0)
+#  define HAVE_UART_DEVICE 1
+#endif
+
+#if defined(HAVE_UART1)
+#  define HAVE_UART_DEVICE 1
+#endif
+
+/* Is there a serial console? There should be at most one defined. */
+
+#undef HAVE_UART_CONSOLE
+
+#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(HAVE_UART0)
+#  undef CONFIG_UART1_SERIAL_CONSOLE
+#  define HAVE_UART_CONSOLE 1
+#endif
+
+#if defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(HAVE_UART1)
+#  undef CONFIG_UART0_SERIAL_CONSOLE
+#  define HAVE_UART_CONSOLE 1
+#endif
+
+#endif /* __ARCH_ARM_SRC_NRF91_NRF91_CONFIG_H */

arch/arm/src/nrf91/nrf91_gpio.c

@@ -0,0 +1,428 @@
+/****************************************************************************
+ * arch/arm/src/nrf91/nrf91_gpio.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <errno.h>
+#include <debug.h>
+
+#include <nuttx/spinlock.h>
+
+#include "arm_internal.h"
+#include "hardware/nrf91_gpio.h"
+#include "nrf91_gpio.h"
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: nrf91_gpio_regget
+ *
+ * Description:
+ *   Get a register address for given GPIO port and register offset
+ *
+ ****************************************************************************/
+
+static inline uint32_t nrf91_gpio_regget(int port, uint32_t offset)
+{
+  uint32_t base = 0;
+
+  /* Get base address for port */
+
+  if (port == 0)
+    {
+      base = NRF91_GPIO_P0_BASE;
+    }
+  else
+    {
+      ASSERT(0);
+    }
+
+  return (base + offset);
+}
+
+/****************************************************************************
+ * Name: nrf91_gpio_input
+ *
+ * Description:
+ *   Configure a GPIO input pin based on bit-encoded description of the pin.
+ *
+ ****************************************************************************/
+
+static inline void nrf91_gpio_input(unsigned int port, unsigned int pin)
+{
+  uint32_t offset;
+
+  offset = nrf91_gpio_regget(port, NRF91_GPIO_DIRCLR_OFFSET);
+
+  /* Configure the pin as an input */
+
+  putreg32(1U << pin, offset);
+
+  /* Enable input buffer */
+
+  offset = nrf91_gpio_regget(port, NRF91_GPIO_PIN_CNF_OFFSET(pin));
+  modifyreg32(offset, GPIO_CNF_INPUT, 0);
+}
+
+/****************************************************************************
+ * Name: nrf91_gpio_output
+ *
+ * Description:
+ *   Configure a GPIO output pin based on bit-encoded description of the pin.
+ *
+ ****************************************************************************/
+
+static inline void nrf91_gpio_output(nrf91_pinset_t cfgset,
+                                     unsigned int port, unsigned int pin)
+{
+  uint32_t offset;
+
+  /* Disable input buffer */
+
+  offset = nrf91_gpio_regget(port, NRF91_GPIO_PIN_CNF_OFFSET(pin));
+  modifyreg32(offset, 0, GPIO_CNF_INPUT);
+
+  offset = nrf91_gpio_regget(port, NRF91_GPIO_DIRSET_OFFSET);
+
+  nrf91_gpio_write(cfgset, ((cfgset & GPIO_VALUE) != GPIO_VALUE_ZERO));
+
+  /* Configure the pin as an output */
+
+  putreg32(1U << pin, offset);
+}
+
+/****************************************************************************
+ * Name: nrf91_gpio_mode
+ *
+ * Description:
+ *   Configure a GPIO mode based on bit-encoded description of the pin.
+ *
+ ****************************************************************************/
+
+static inline void nrf91_gpio_mode(nrf91_pinset_t cfgset,
+                                   unsigned int port, unsigned int pin)
+{
+  uint32_t mode;
+  uint32_t regval;
+  uint32_t offset;
+
+  offset = nrf91_gpio_regget(port, NRF91_GPIO_PIN_CNF_OFFSET(pin));
+
+  mode = cfgset & GPIO_MODE_MASK;
+
+  regval = getreg32(offset);
+  regval &= ~GPIO_CNF_PULL_MASK;
+
+  if (mode == GPIO_PULLUP)
+    {
+      regval |= GPIO_CNF_PULL_UP;
+    }
+  else if (mode == GPIO_PULLDOWN)
+    {
+      regval |= GPIO_CNF_PULL_DOWN;
+    }
+
+  putreg32(regval, offset);
+}
+
+/****************************************************************************
+ * Name: nrf91_gpio_sense
+ *
+ * Description:
+ *   Set SENSE configuration for an input pin
+ *
+ ****************************************************************************/
+
+static inline void nrf91_gpio_sense(nrf91_pinset_t cfgset,
+                                    unsigned int port, unsigned int pin)
+{
+  uint32_t mode;
+  uint32_t regval;
+  uint32_t offset;
+
+  mode = cfgset & GPIO_SENSE_MASK;
+
+  offset = nrf91_gpio_regget(port, NRF91_GPIO_PIN_CNF_OFFSET(pin));
+  regval = getreg32(offset);
+
+  regval &= ~GPIO_CNF_SENSE_MASK;
+
+  if (mode == GPIO_SENSE_HIGH)
+    {
+      regval |= GPIO_CNF_SENSE_HIGH;
+    }
+  else if (mode == GPIO_SENSE_LOW)
+    {
+      regval |= GPIO_CNF_SENSE_LOW;
+    }
+
+  putreg32(regval, offset);
+}
+
+/****************************************************************************
+ * Name: nrf91_gpio_drive
+ *
+ * Description:
+ *   Set DRIVE configuration for a pin
+ *
+ ****************************************************************************/
+
+static inline void nrf91_gpio_drive(nrf91_pinset_t cfgset,
+                                    unsigned int port, unsigned int pin)
+{
+  uint32_t drive;
+  uint32_t regval;
+  uint32_t offset;
+
+  drive = cfgset & GPIO_DRIVE_MASK;
+
+  offset = nrf91_gpio_regget(port, NRF91_GPIO_PIN_CNF_OFFSET(pin));
+  regval = getreg32(offset);
+
+  regval &= ~GPIO_CNF_DRIVE_MASK;
+
+  switch (drive)
+    {
+      case GPIO_DRIVE_S0S1:
+        regval |= GPIO_CNF_DRIVE_S0S1;
+        break;
+      case GPIO_DRIVE_S0H1:
+        regval |= GPIO_CNF_DRIVE_S0H1;
+        break;
+      case GPIO_DRIVE_S0D1:
+        regval |= GPIO_CNF_DRIVE_S0D1;
+        break;
+      case GPIO_DRIVE_H0D1:
+        regval |= GPIO_CNF_DRIVE_H0D1;
+        break;
+      case GPIO_DRIVE_H0H1:
+        regval |= GPIO_CNF_DRIVE_H0H1;
+        break;
+      case GPIO_DRIVE_H0S1:
+        regval |= GPIO_CNF_DRIVE_H0S1;
+        break;
+      case GPIO_DRIVE_D0H1:
+        regval |= GPIO_CNF_DRIVE_D0H1;
+        break;
+      case GPIO_DRIVE_D0S1:
+        regval |= GPIO_CNF_DRIVE_D0S1;
+        break;
+    }
+
+  putreg32(regval, offset);
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: nrf91_gpio_config
+ *
+ * Description:
+ *   Configure a GPIO pin based on bit-encoded description of the pin.
+ *
+ ****************************************************************************/
+
+int nrf91_gpio_config(nrf91_pinset_t cfgset)
+{
+  unsigned int port = 0;
+  unsigned int pin;
+  irqstate_t flags;
+  int ret = OK;
+
+  /* Verify that this hardware supports the select GPIO port */
+
+  port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
+
+  if (port < NRF91_GPIO_NPORTS)
+    {
+      /* Get the pin number and select the port configuration register for
+       * that pin.
+       */
+
+      pin = GPIO_PIN_DECODE(cfgset);
+
+      flags = spin_lock_irqsave(NULL);
+
+      /* First, configure the port as a generic input so that we have a
+       * known starting point and consistent behavior during the re-
+       * configuration.
+       */
+
+      nrf91_gpio_input(port, pin);
+
+      /* Set the mode bits */
+
+      nrf91_gpio_mode(cfgset, port, pin);
+
+      /* Set the drive bits (needed also for input pins
+       * for some peripherals).
+       */
+
+      nrf91_gpio_drive(cfgset, port, pin);
+
+      /* Handle according to pin function */
+
+      switch (cfgset & GPIO_FUNC_MASK)
+        {
+        case GPIO_INPUT:   /* GPIO input pin */
+          nrf91_gpio_sense(cfgset, port, pin);
+          break;
+
+        case GPIO_OUTPUT:  /* GPIO outpout pin */
+          nrf91_gpio_output(cfgset, port, pin);
+          break;
+
+        default:
+          ret = -EINVAL;
+        }
+
+      spin_unlock_irqrestore(NULL, flags);
+    }
+  else
+    {
+      ret = -EINVAL;
+    }
+
+  return ret;
+}
+
+/****************************************************************************
+ * Name: nrf91_gpio_unconfig
+ *
+ * Description:
+ *   Unconfigure a GPIO pin based on bit-encoded description of the pin.
+ *
+ ****************************************************************************/
+
+int nrf91_gpio_unconfig(nrf91_pinset_t cfgset)
+{
+  unsigned int pin;
+  unsigned int port = 0;
+  uint32_t offset;
+
+  /* Get port and pin number */
+
+  pin  = GPIO_PIN_DECODE(cfgset);
+  port = GPIO_PORT_DECODE(cfgset);
+
+  /* Get address offset */
+
+  offset = nrf91_gpio_regget(port, NRF91_GPIO_PIN_CNF_OFFSET(pin));
+
+  /* Configure as input and disconnect input buffer */
+
+  putreg32(GPIO_CNF_INPUT, offset);
+
+  return OK;
+}
+
+/****************************************************************************
+ * Name: nrf91_gpio_write
+ *
+ * Description:
+ *   Write one or zero to the selected GPIO pin
+ *
+ ****************************************************************************/
+
+void nrf91_gpio_write(nrf91_pinset_t pinset, bool value)
+{
+  unsigned int pin;
+  unsigned int port = 0;
+  uint32_t offset;
+
+  /* Get port and pin number */
+
+  pin  = GPIO_PIN_DECODE(pinset);
+  port = GPIO_PORT_DECODE(pinset);
+
+  /* Get register address */
+
+  if (value)
+    {
+      offset = nrf91_gpio_regget(port, NRF91_GPIO_OUTSET_OFFSET);
+    }
+  else
+    {
+      offset = nrf91_gpio_regget(port, NRF91_GPIO_OUTCLR_OFFSET);
+    }
+
+  /* Put register value */
+
+  putreg32(1 << pin, offset);
+}
+
+/****************************************************************************
+ * Name: nrf91_gpio_read
+ *
+ * Description:
+ *   Read one or zero from the selected GPIO pin
+ *
+ ****************************************************************************/
+
+bool nrf91_gpio_read(nrf91_pinset_t pinset)
+{
+  unsigned int port;
+  unsigned int pin;
+  uint32_t regval;
+  uint32_t offset;
+
+  /* Get port and pin number */
+
+  pin  = GPIO_PIN_DECODE(pinset);
+  port = GPIO_PORT_DECODE(pinset);
+
+  /* Get register address */
+
+  offset = nrf91_gpio_regget(port, NRF91_GPIO_IN_OFFSET);
+
+  /* Get register value */
+
+  regval = getreg32(offset);
+
+  return (regval >> pin) & 1UL;
+}
+
+/****************************************************************************
+ * Name: nrf91_gpio_detectmode
+ *
+ * Description:
+ *  Set DETECTMODE to either default or latched
+ *
+ ****************************************************************************/
+
+void nrf91_gpio_detectmode(int port, enum nrf91_gpio_detectmode_e mode)
+{
+  uint32_t offset = nrf91_gpio_regget(port, NRF91_GPIO_DETECTMODE_OFFSET);
+
+  putreg32(mode == NRF91_GPIO_DETECTMODE_DETECT ?
+           GPIO_DETECTMODE_DEFAULT :
+           GPIO_DETECTMODE_LDETECT, offset);
+}

arch/arm/src/nrf91/nrf91_gpio.h

@@ -0,0 +1,264 @@
+/****************************************************************************
+ * arch/arm/src/nrf91/nrf91_gpio.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_NRF91_NRF91_GPIO_H
+#define __ARCH_ARM_SRC_NRF91_NRF91_GPIO_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+#  include <stdint.h>
+#  include <stdbool.h>
+#endif
+
+#include <arch/nrf91/chip.h>
+#include "hardware/nrf91_gpio.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Bit-encoded input to nrf91_gpio_config() *********************************/
+
+/* 32-Bit Encoding: .... .... .... .GGF  FSSD DDDM MVPN NNNN
+ *
+ *   Pin Function:          FF
+ *   Pin Sense:             SS
+ *   Pin Drive:             DDDD
+ *   Pin Mode bits:         MM
+ *   Initial value:         V (output pins)
+ *   Port number:           P (0-1)
+ *   Pin number:            NNNNN (0-31)
+ */
+
+/* Pin Function bits:
+ * Only meaningful when the GPIO function is GPIO_PIN
+ *
+ * .... .... .... ...F  F... .... .... ....
+ */
+
+#define GPIO_FUNC_SHIFT         (15)    /* Bits 15-16: GPIO mode */
+#define GPIO_FUNC_MASK          (0x03 << GPIO_FUNC_SHIFT)
+#  define GPIO_INPUT            (0x00 << GPIO_FUNC_SHIFT)  /* 00000 GPIO input pin */
+#  define GPIO_OUTPUT           (0x01 << GPIO_FUNC_SHIFT)  /* 00001 GPIO output pin */
+
+/* Pin Sense bits:
+ *
+ * .... .... .... ....  .SS. .... .... ....
+ */
+
+#define GPIO_SENSE_SHIFT        (13)     /* Bits 13-14: Pin Sense mode */
+#define GPIO_SENSE_MASK         (0x3 << GPIO_SENSE_SHIFT)
+#  define GPIO_SENSE_NONE       (0 << GPIO_SENSE_SHIFT)
+#  define GPIO_SENSE_HIGH       (2 << GPIO_SENSE_SHIFT)
+#  define GPIO_SENSE_LOW        (3 << GPIO_SENSE_SHIFT)
+
+/* Pin Drive bits:
+ *
+ * .... .... .... ....  ...D DDD. .... ....
+ */
+
+#define GPIO_DRIVE_SHIFT        (9)      /* Bits 9-12: Pin pull-up mode */
+#define GPIO_DRIVE_MASK         (0xf << GPIO_DRIVE_SHIFT)
+#  define GPIO_DRIVE_S0S1       (0 << GPIO_DRIVE_SHIFT)  /* Standard '0', standard '1' */
+#  define GPIO_DRIVE_H0S1       (1 << GPIO_DRIVE_SHIFT)  /* High drive '0', standard '1' */
+#  define GPIO_DRIVE_S0H1       (2 << GPIO_DRIVE_SHIFT)
+#  define GPIO_DRIVE_H0H1       (3 << GPIO_DRIVE_SHIFT)
+#  define GPIO_DRIVE_D0S1       (4 << GPIO_DRIVE_SHIFT)
+#  define GPIO_DRIVE_D0H1       (5 << GPIO_DRIVE_SHIFT)
+#  define GPIO_DRIVE_S0D1       (6 << GPIO_DRIVE_SHIFT)
+#  define GPIO_DRIVE_H0D1       (7 << GPIO_DRIVE_SHIFT)
+#  define GPIO_DRIVE_EOS1       (8 << GPIO_DRIVE_SHIFT)
+#  define GPIO_DRIVE_SOE1       (9 << GPIO_DRIVE_SHIFT)
+#  define GPIO_DRIVE_EOE1       (10 << GPIO_DRIVE_SHIFT)
+#  define GPIO_DRIVE_DOE1       (11 << GPIO_DRIVE_SHIFT)
+#  define GPIO_DRIVE_EOD1       (12 << GPIO_DRIVE_SHIFT)
+
+/* Pin Mode: MM
+ *
+ * .... .... .... ....  .... ...M M... ....
+ */
+
+#define GPIO_MODE_SHIFT         (7)      /* Bits 7-8: Pin pull-up mode */
+#define GPIO_MODE_MASK          (0x3 << GPIO_MODE_SHIFT)
+#  define GPIO_FLOAT            (0 << GPIO_MODE_SHIFT) /* Neither pull-up nor -down */
+#  define GPIO_PULLDOWN         (1 << GPIO_MODE_SHIFT) /* Pull-down resistor enabled */
+#  define GPIO_PULLUP           (2 << GPIO_MODE_SHIFT) /* Pull-up resistor enabled */
+
+/* Initial value: V
+ *
+ * .... .... .... ....  .... .... .V.. ....
+ */
+
+#define GPIO_VALUE              (1 << 6)  /* Bit 6: Initial GPIO output value */
+#  define GPIO_VALUE_ONE        GPIO_VALUE
+#  define GPIO_VALUE_ZERO       (0)
+
+/* Port number: PPP (0-5)
+ *
+ * .... .... .... ....  .... .... ..P. ....
+ */
+
+#define GPIO_PORT_SHIFT         (5)       /* Bit 5:  Port number */
+#define GPIO_PORT_MASK          (0x1 << GPIO_PORT_SHIFT)
+#  define GPIO_PORT0            (0 << GPIO_PORT_SHIFT)
+#  define GPIO_PORT1            (1 << GPIO_PORT_SHIFT)
+
+/* Pin number: NNNNN (0-31)
+ *
+ * .... .... .... ....  .... .... ...N NNNN
+ */
+
+#define GPIO_PIN_SHIFT          0         /* Bits 0-4: GPIO number: 0-31 */
+#define GPIO_PIN_MASK           (0x1f << GPIO_PIN_SHIFT)
+#  define GPIO_PIN0             (0  << GPIO_PIN_SHIFT)
+#  define GPIO_PIN1             (1  << GPIO_PIN_SHIFT)
+#  define GPIO_PIN2             (2  << GPIO_PIN_SHIFT)
+#  define GPIO_PIN3             (3  << GPIO_PIN_SHIFT)
+#  define GPIO_PIN4             (4  << GPIO_PIN_SHIFT)
+#  define GPIO_PIN5             (5  << GPIO_PIN_SHIFT)
+#  define GPIO_PIN6             (6  << GPIO_PIN_SHIFT)
+#  define GPIO_PIN7             (7  << GPIO_PIN_SHIFT)
+#  define GPIO_PIN8             (8  << GPIO_PIN_SHIFT)
+#  define GPIO_PIN9             (9  << GPIO_PIN_SHIFT)
+#  define GPIO_PIN10            (10 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN11            (11 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN12            (12 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN13            (13 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN14            (14 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN15            (15 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN16            (16 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN17            (17 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN18            (18 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN19            (19 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN20            (20 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN21            (21 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN22            (22 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN23            (23 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN24            (24 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN25            (25 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN26            (26 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN27            (27 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN28            (28 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN29            (29 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN30            (30 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN31            (31 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN(n)           ((n) << GPIO_PIN_SHIFT)
+
+/* Helper macros */
+
+#define GPIO_PIN_DECODE(p)  (((p) & GPIO_PIN_MASK)  >> GPIO_PIN_SHIFT)
+#define GPIO_PORT_DECODE(p) (((p) & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT)
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+typedef uint32_t nrf91_pinset_t;
+
+enum nrf91_gpio_detectmode_e
+{
+  NRF91_GPIO_DETECTMODE_DETECT,
+  NRF91_GPIO_DETECTMODE_LDETECT,
+};
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: nrf91_gpio_config
+ *
+ * Description:
+ *   Configure a GPIO pin based on bit-encoded description of the pin.
+ *
+ ****************************************************************************/
+
+int nrf91_gpio_config(nrf91_pinset_t cfgset);
+
+/****************************************************************************
+ * Name: nrf91_gpio_unconfig
+ *
+ * Description:
+ *   Unconfigure a GPIO pin based on bit-encoded description of the pin.
+ *
+ ****************************************************************************/
+
+int nrf91_gpio_unconfig(nrf91_pinset_t cfgset);
+
+/****************************************************************************
+ * Name: rnf52_gpio_write
+ *
+ * Description:
+ *   Write one or zero to the selected GPIO pin
+ *
+ ****************************************************************************/
+
+void nrf91_gpio_write(nrf91_pinset_t pinset, bool value);
+
+/****************************************************************************
+ * Name: nrf91_gpio_read
+ *
+ * Description:
+ *   Read one or zero from the selected GPIO pin
+ *
+ ****************************************************************************/
+
+bool nrf91_gpio_read(nrf91_pinset_t pinset);
+
+/****************************************************************************
+ * Function:  nf52_gpio_dump
+ *
+ * Description:
+ *   Dump all GPIO registers associated with the base address of the provided
+ * pinset.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_DEBUG_GPIO_INFO
+int nrf91_gpio_dump(nrf91_pinset_t pinset, const char *msg);
+#else
+#  define nrf91_gpio_dump(p,m)
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ARCH_ARM_SRC_NRF91_NRF91_GPIO_H */

arch/arm/src/nrf91/nrf91_i2c.h

@@ -0,0 +1,73 @@
+/****************************************************************************
+ * arch/arm/src/nrf91/nrf91_i2c.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_NRF91_NRF91_I2C_H
+#define __ARCH_ARM_SRC_NRF91_NRF91_I2C_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/i2c/i2c_master.h>
+
+#include "chip.h"
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: nrf91_i2cbus_initialize
+ *
+ * Description:
+ *   Initialize the selected I2C port. And return a unique instance of struct
+ *   struct i2c_master_s. This function may be called to obtain multiple
+ *   instances of the interface, each of which may be set up with a
+ *   different frequency and slave address.
+ *
+ * Input Parameters:
+ *   Port number (for hardware that has multiple TWI interfaces)
+ *
+ * Returned Value:
+ *   Valid I2C device structure reference on success; a NULL on failure
+ *
+ ****************************************************************************/
+
+struct i2c_master_s *nrf91_i2cbus_initialize(int port);
+
+/****************************************************************************
+ * Name: nrf91_i2cbus_uninitialize
+ *
+ * Description:
+ *   De-initialize the selected I2C port, and power down the device.
+ *
+ * Input Parameters:
+ *   Device structure as returned by the nrf91_i2cbus_initialize()
+ *
+ * Returned Value:
+ *   OK on success, ERROR when internal reference count mismatch or dev
+ *   points to invalid hardware device.
+ *
+ ****************************************************************************/
+
+int nrf91_i2cbus_uninitialize(struct i2c_master_s *dev);
+
+#endif /* __ARCH_ARM_SRC_NRF91_NRF91_I2C_H */

arch/arm/src/nrf91/nrf91_idle.c

@@ -0,0 +1,96 @@
+/****************************************************************************
+ * arch/arm/src/nrf91/nrf91_idle.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <arch/board/board.h>
+#include <nuttx/config.h>
+
+#include <debug.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/board.h>
+
+#include <nuttx/irq.h>
+
+#include "arm_internal.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Does the board support an IDLE LED to indicate that the board is in the
+ * IDLE state?
+ */
+
+#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE)
+#  define BEGIN_IDLE() board_autoled_on(LED_IDLE)
+#  define END_IDLE()   board_autoled_off(LED_IDLE)
+#else
+#  define BEGIN_IDLE()
+#  define END_IDLE()
+#endif
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_idle
+ *
+ * Description:
+ *   up_idle() is the logic that will be executed when there is no other
+ *   ready-to-run task.  This is processor idle time and will continue until
+ *   some interrupt occurs to cause a context switch from the idle task.
+ *
+ *   Processing in this state may be processor-specific. e.g., this is where
+ *   power management operations might be performed.
+ *
+ ****************************************************************************/
+
+void up_idle(void)
+{
+#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS)
+  /* If the system is idle and there are no timer interrupts, then process
+   * "fake" timer interrupts. Hopefully, something will wake up.
+   */
+
+  nxsched_process_timer();
+#else
+
+  /* Sleep until an interrupt occurs to save power
+   *
+   * The SysTick's clock will only tick when the CPU is
+   * running (not in WFE/WFI) or when the system is in debug interface mode.
+   */
+
+#ifdef CONFIG_NRF91_SYSTIMER_RTC
+  BEGIN_IDLE();
+  asm("WFI");
+  END_IDLE();
+#endif
+#endif
+}

arch/arm/src/nrf91/nrf91_irq.h

@@ -0,0 +1,45 @@
+/****************************************************************************
+ * arch/arm/src/nrf91/nrf91_irq.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_NRF91_NRF91_IRQ_H
+#define __ARCH_ARM_SRC_NRF91_NRF91_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: nrf91_clrpend
+ *
+ * Description:
+ *   Clear a pending interrupt at the NVIC.  This does not seem to be
+ *   required for most interrupts.
+ *
+ ****************************************************************************/
+
+void nrf91_clrpend(int irq);
+
+#endif /* __ARCH_ARM_SRC_NRF91_NRF91_IRQ_H */

arch/arm/src/nrf91/nrf91_lowputc.c

@@ -0,0 +1,443 @@
+/****************************************************************************
+ * arch/arm/src/nrf91/nrf91_lowputc.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdbool.h>
+#include <assert.h>
+
+#include "arm_internal.h"
+#include "hardware/nrf91_memorymap.h"
+#include "hardware/nrf91_uarte.h"
+
+#include "nrf91_config.h"
+#include "nrf91_clockconfig.h"
+#include "nrf91_gpio.h"
+#include "nrf91_lowputc.h"
+
+#include <arch/board/board.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#ifdef HAVE_UART_CONSOLE
+
+#ifdef CONFIG_UART0_SERIAL_CONSOLE
+#  define CONSOLE_BASE     NRF91_UART0_BASE
+#  define CONSOLE_BAUD     CONFIG_UART0_BAUD
+#  define CONSOLE_BITS     CONFIG_UART0_BITS
+#  define CONSOLE_PARITY   CONFIG_UART0_PARITY
+#  define CONSOLE_2STOP    CONFIG_UART0_2STOP
+#  define CONSOLE_TX_PIN   BOARD_UART0_TX_PIN
+#  define CONSOLE_RX_PIN   BOARD_UART0_RX_PIN
+#elif CONFIG_UART1_SERIAL_CONSOLE
+#  define CONSOLE_BASE     NRF91_UART1_BASE
+#  define CONSOLE_BAUD     CONFIG_UART1_BAUD
+#  define CONSOLE_BITS     CONFIG_UART1_BITS
+#  define CONSOLE_PARITY   CONFIG_UART1_PARITY
+#  define CONSOLE_2STOP    CONFIG_UART1_2STOP
+#  define CONSOLE_TX_PIN   BOARD_UART1_TX_PIN
+#  define CONSOLE_RX_PIN   BOARD_UART1_RX_PIN
+#endif
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/* UART console configuration */
+
+static const struct uart_config_s g_console_config =
+{
+  .baud      = CONSOLE_BAUD,
+  .parity    = CONSOLE_PARITY,
+  .bits      = CONSOLE_BITS,
+  .stopbits2 = CONSOLE_2STOP,
+  .txpin     = CONSOLE_TX_PIN,
+  .rxpin     = CONSOLE_RX_PIN,
+};
+#endif /* HAVE_UART_CONSOLE */
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: nrf91_setbaud
+ *
+ * Description:
+ *   Configure the UART BAUD.
+ *
+ ****************************************************************************/
+
+#ifdef HAVE_UART_DEVICE
+static void nrf91_setbaud(uintptr_t base, const struct uart_config_s *config)
+{
+  uint32_t br = 0;
+
+  switch (config->baud)
+    {
+      case 1200:
+        {
+          br = UART_BAUDRATE_1200;
+          break;
+        }
+
+      case 2400:
+        {
+          br = UART_BAUDRATE_2400;
+          break;
+        }
+
+      case 4800:
+        {
+          br = UART_BAUDRATE_4800;
+          break;
+        }
+
+      case 9600:
+        {
+          br = UART_BAUDRATE_9600;
+          break;
+        }
+
+      case 14400:
+        {
+          br = UART_BAUDRATE_14400;
+          break;
+        }
+
+      case 19200:
+        {
+          br = UART_BAUDRATE_19200;
+          break;
+        }
+
+      case 28800:
+        {
+          br = UART_BAUDRATE_28800;
+          break;
+        }
+
+#ifdef UART_BAUDRATE_31250
+      case 31250:
+        {
+          br = UART_BAUDRATE_31250;
+          break;
+        }
+#endif
+
+      case 38400:
+        {
+          br = UART_BAUDRATE_38400;
+          break;
+        }
+
+#ifdef UART_BAUDRATE_56000
+      case 56000:
+        {
+          br = UART_BAUDRATE_56000;
+          break;
+        }
+#endif
+
+      case 57600:
+        {
+          br = UART_BAUDRATE_57600;
+          break;
+        }
+
+      case 76000:
+        {
+          br = UART_BAUDRATE_76000;
+          break;
+        }
+
+      case 115200:
+        {
+          br = UART_BAUDRATE_115200;
+          break;
+        }
+
+      case 230400:
+        {
+          br = UART_BAUDRATE_230400;
+          break;
+        }
+
+      case 250000:
+        {
+          br = UART_BAUDRATE_250000;
+          break;
+        }
+
+      case 460800:
+        {
+          br = UART_BAUDRATE_460800;
+          break;
+        }
+
+      case 921600:
+        {
+          br = UART_BAUDRATE_921600;
+          break;
+        }
+
+      default:
+        {
+          DEBUGPANIC();
+          break;
+        }
+    }
+
+  putreg32(br, base + NRF91_UART_BAUDRATE_OFFSET);
+}
+
+/****************************************************************************
+ * Name: nrf91_setparity
+ ****************************************************************************/
+
+static void nrf91_setparity(uintptr_t base,
+                            const struct uart_config_s *config)
+{
+  uint32_t regval = 0;
+
+  regval = getreg32(base + NRF91_UART_CONFIG_OFFSET);
+
+  if (config->parity == 2)
+    {
+      /* Include even parity */
+
+      regval |= UART_CONFIG_PARITY;
+    }
+  else
+    {
+      /* Exclude parity */
+
+      regval &= ~UART_CONFIG_PARITY;
+    }
+
+  putreg32(regval, base + NRF91_UART_CONFIG_OFFSET);
+}
+
+/****************************************************************************
+ * Name: nrf91_setstops
+ ****************************************************************************/
+
+#ifdef HAVE_UART_STOPBITS
+static void nrf91_setstops(uintptr_t base,
+                           const struct uart_config_s *config)
+{
+  uint32_t regval = 0;
+
+  regval = getreg32(base + NRF91_UART_CONFIG_OFFSET);
+
+  if (config->stopbits2 == true)
+    {
+      regval |= UART_CONFIG_STOP;
+    }
+  else
+    {
+      regval &= ~UART_CONFIG_STOP;
+    }
+
+  putreg32(regval, base + NRF91_UART_CONFIG_OFFSET);
+}
+#endif
+
+/****************************************************************************
+ * Name: nrf91_sethwflow
+ ****************************************************************************/
+
+static void nrf91_sethwflow(uintptr_t base,
+                            const struct uart_config_s *config)
+{
+  /* TODO */
+}
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: nrf91_lowsetup
+ *
+ * Description:
+ *   Called at the very beginning of _start. Performs low level
+ *   initialization including setup of the console UART.
+ *   This UART initialization is done early so that the serial console is
+ *   available for debugging very early in the boot sequence.
+ *
+ ****************************************************************************/
+
+void nrf91_lowsetup(void)
+{
+#ifdef HAVE_UART_DEVICE
+#ifdef HAVE_UART_CONSOLE
+  /* Configure the console UART (if any) */
+
+  nrf91_usart_configure(CONSOLE_BASE, &g_console_config);
+
+#endif /* HAVE_UART_CONSOLE */
+#endif /* HAVE_UART_DEVICE */
+}
+
+/****************************************************************************
+ * Name: nrf91_usart_configure
+ *
+ * Description:
+ *   Configure a UART for non-interrupt driven operation
+ *
+ ****************************************************************************/
+
+#ifdef HAVE_UART_DEVICE
+void nrf91_usart_configure(uintptr_t base,
+                           const struct uart_config_s *config)
+{
+  uint32_t pin    = 0;
+  uint32_t port   = 0;
+  uint32_t regval = 0;
+
+  putreg32(1, base + NRF91_UART_TASKS_STOPRX_OFFSET);
+  putreg32(1, base + NRF91_UART_TASKS_STOPTX_OFFSET);
+  putreg32(NRF91_UART_ENABLE_DISABLE, base + NRF91_UART_ENABLE_OFFSET);
+
+  /* Set UART format */
+
+  nrf91_usart_setformat(base, config);
+
+  /* Config GPIO pins for uart */
+
+  nrf91_gpio_config(config->txpin);
+  nrf91_gpio_config(config->rxpin);
+
+  /* Setect TX pins for UART */
+
+  pin  = GPIO_PIN_DECODE(config->txpin);
+  port = GPIO_PORT_DECODE(config->txpin);
+
+  regval = (pin << UART_PSELTXD_PIN_SHIFT);
+  regval |= (port << UART_PSELTXD_PORT_SHIFT);
+  putreg32(regval, base + NRF91_UART_PSELTXD_OFFSET);
+
+  /* Setect RX pins for UART */
+
+  pin  = GPIO_PIN_DECODE(config->rxpin);
+  port = GPIO_PORT_DECODE(config->rxpin);
+
+  regval = (pin << UART_PSELRXD_PIN_SHIFT);
+  regval |= (port << UART_PSELRXD_PORT_SHIFT);
+  putreg32(regval, base + NRF91_UART_PSELRXD_OFFSET);
+
+  /* Enable UART */
+
+  putreg32(NRF91_UART_ENABLE_ENABLE, base + NRF91_UART_ENABLE_OFFSET);
+}
+
+/****************************************************************************
+ * Name: nrf91_usart_disable
+ *
+ * Description:
+ *   Disable a UART.  it will be necessary to again call
+ *   nrf91_usart_configure() in order to use this UART channel again.
+ *
+ ****************************************************************************/
+
+void nrf91_usart_disable(uintptr_t base, const struct uart_config_s *config)
+{
+  /* Disable interrupts */
+
+  /* Disable the UART */
+
+  putreg32(1, base + NRF91_UART_TASKS_STOPRX_OFFSET);
+  putreg32(1, base + NRF91_UART_TASKS_STOPTX_OFFSET);
+  putreg32(NRF91_UART_ENABLE_DISABLE, base + NRF91_UART_ENABLE_OFFSET);
+
+  putreg32(0xffffffff, base + NRF91_UART_PSELTXD_OFFSET);
+  putreg32(0xffffffff, base + NRF91_UART_PSELRXD_OFFSET);
+
+  /* Unconfigure GPIO */
+
+  nrf91_gpio_unconfig(config->rxpin);
+  nrf91_gpio_unconfig(config->txpin);
+
+  /* Deatach TWI from GPIO */
+
+  putreg32(UART_PSELTXD_RESET, base + NRF91_UART_PSELTXD_OFFSET);
+  putreg32(UART_PSELRXD_RESET, base + NRF91_UART_PSELRXD_OFFSET);
+}
+
+/****************************************************************************
+ * Name: nrf91_usart_setformat
+ *
+ * Description:
+ *   Set the USART line format and speed.
+ *
+ ****************************************************************************/
+
+void nrf91_usart_setformat(uintptr_t base,
+                           const struct uart_config_s *config)
+{
+  /* Configure baud */
+
+  nrf91_setbaud(base, config);
+
+  /* Configure polarity */
+
+  nrf91_setparity(base, config);
+
+#ifdef HAVE_UART_STOPBITS
+  /* Configure STOP bits */
+
+  nrf91_setstops(base, config);
+#endif
+
+  /* Configure hardware flow control */
+
+  nrf91_sethwflow(base, config);
+}
+#endif
+
+/****************************************************************************
+ * Name: arm_lowputc
+ *
+ * Description:
+ *   Output one byte on the serial console
+ *
+ ****************************************************************************/
+
+void arm_lowputc(char ch)
+{
+#ifdef HAVE_UART_CONSOLE
+  putreg32(1, CONSOLE_BASE + NRF91_UART_TASKS_STARTTX_OFFSET);
+  putreg32(0, CONSOLE_BASE + NRF91_UART_EVENTS_TXDRDY_OFFSET);
+  putreg32(ch, CONSOLE_BASE + NRF91_UART_TXD_OFFSET);
+  while (getreg32(CONSOLE_BASE + NRF91_UART_EVENTS_TXDRDY_OFFSET) == 0)
+    {
+    }
+
+  putreg32(1, CONSOLE_BASE + NRF91_UART_TASKS_STOPTX_OFFSET);
+#endif
+}

arch/arm/src/nrf91/nrf91_lowputc.h

@@ -0,0 +1,117 @@
+/****************************************************************************
+ * arch/arm/src/nrf91/nrf91_lowputc.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_NRF91_NRF91_LOWPUTC_H
+#define __ARCH_ARM_SRC_NRF91_NRF91_LOWPUTC_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "nrf91_gpio.h"
+#include "nrf91_config.h"
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+#ifdef HAVE_UART_DEVICE
+/* This structure describes the configuration of an UART */
+
+struct uart_config_s
+{
+  uint32_t baud;          /* Configured baud */
+  uint8_t  parity;        /* 0=none, 1=odd, 2=even */
+  uint8_t  bits;          /* Number of bits (5-9) */
+  bool     stopbits2;     /* Configure with 2 stop bits instead of 1 */
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+  bool     iflow;         /* Input flow control supported */
+#endif
+#ifdef CONFIG_SERIAL_OFLOWCONTROL
+  bool     oflow;         /* Output flow control supported. */
+#endif
+  nrf91_pinset_t txpin;   /* TX pin */
+  nrf91_pinset_t rxpin;   /* RX pin */
+};
+#endif
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: nrf91_lowsetup
+ *
+ * Description:
+ *   Called at the very beginning of _start. Performs low level
+ *   initialization including setup of the console UART. This UART
+ *   initialization is done early so that the serial console is available
+ *   for debugging very early in the boot sequence.
+ *
+ ****************************************************************************/
+
+void nrf91_lowsetup(void);
+
+/****************************************************************************
+ * Name: nrf91_usart_configure
+ *
+ * Description:
+ *   Configure a UART for non-interrupt driven operation
+ *
+ ****************************************************************************/
+
+#ifdef HAVE_UART_DEVICE
+void nrf91_usart_configure(uintptr_t base,
+                           const struct uart_config_s *config);
+#endif
+
+/****************************************************************************
+ * Name: nrf91_usart_disable
+ *
+ * Description:
+ *   Disable a UART.  it will be necessary to again call
+ *   nrf91_usart_configure() in order to use this UART channel again.
+ *
+ ****************************************************************************/
+
+#ifdef HAVE_UART_DEVICE
+void nrf91_usart_disable(uintptr_t base,
+                         const struct uart_config_s *config);
+#endif
+
+/****************************************************************************
+ * Name: nrf91_usart_setformat
+ *
+ * Description:
+ *   Set the USART line format and speed.
+ *
+ ****************************************************************************/
+
+#ifdef HAVE_UART_DEVICE
+void nrf91_usart_setformat(uintptr_t base,
+                           const struct uart_config_s *config);
+#endif
+
+#endif /* __ARCH_ARM_SRC_NRF91_NRF91_LOWPUTC_H */

arch/arm/src/nrf91/nrf91_modem.c

@@ -0,0 +1,95 @@
+/****************************************************************************
+ * arch/arm/src/nrf91/nrf91_modem.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+
+#include <debug.h>
+#include <assert.h>
+
+#include "chip.h"
+
+#include "nrf_modem.h"
+
+#include "nrf91_modem.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#ifndef CONFIG_ARCH_TRUSTZONE_NONSECURE
+#  error NRF91 modem works only in non-secure environment
+#endif
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: nrf91_modem_fault_handler
+ ****************************************************************************/
+
+static void nrf91_modem_fault_handler(struct nrf_modem_fault_info *info)
+{
+  nerr("Modem hard fault");
+  ASSERT(0);
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: nrf91_modem_initialize
+ ****************************************************************************/
+
+int nrf91_modem_initialize(void)
+{
+  struct nrf_modem_init_params init_params;
+  int                          ret = OK;
+
+  /* Modem parameters */
+
+  init_params.shmem.ctrl.base  = NRF91_SHMEM_CTRL_BASE;
+  init_params.shmem.ctrl.size  = NRF91_SHMEM_CTRL_SIZE;
+  init_params.shmem.tx.base    = NRF91_SHMEM_TX_BASE;
+  init_params.shmem.tx.size    = NRF91_SHMEM_TX_SIZE;
+  init_params.shmem.rx.base    = NRF91_SHMEM_RX_BASE;
+  init_params.shmem.rx.size    = NRF91_SHMEM_RX_SIZE;
+  init_params.shmem.trace.base = NRF91_SHMEM_TRACE_BASE;
+  init_params.shmem.trace.size = NRF91_SHMEM_TRACE_SIZE;
+  init_params.ipc_irq_prio     = NVIC_SYSH_PRIORITY_DEFAULT;
+  init_params.fault_handler    = nrf91_modem_fault_handler;
+
+  /* Initialize modem */
+
+  ret = nrf_modem_init(&init_params);
+  if (ret < 0)
+    {
+      nerr("nrf_modem_init failed %d\n", ret);
+    }
+
+  return ret;
+}

arch/arm/src/nrf91/nrf91_modem.h

@@ -0,0 +1,74 @@
+/****************************************************************************
+ * arch/arm/src/nrf91/nrf91_modem.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Constant from nrf_modem */
+
+#define NRF91_SHMEM_CTRL_SIZE  (0x4e8)
+
+/* Shared memory configuration */
+
+#define NRF91_SHMEM_START_ADDR (0x20000000)
+#define NRF91_SHMEM_CTRL_BASE  (NRF91_SHMEM_START_ADDR)
+#define NRF91_SHMEM_TX_BASE    (NRF91_SHMEM_CTRL_BASE+NRF91_SHMEM_CTRL_SIZE)
+#define NRF91_SHMEM_TX_SIZE    (CONFIG_NRF91_MODEM_SHMEM_TX_SIZE)
+#define NRF91_SHMEM_RX_BASE    (NRF91_SHMEM_TX_BASE+NRF91_SHMEM_TX_SIZE)
+#define NRF91_SHMEM_RX_SIZE    (CONFIG_NRF91_MODEM_SHMEM_RX_SIZE)
+#define NRF91_SHMEM_TRACE_BASE (NRF91_SHMEM_RX_BASE+NRF91_SHMEM_RX_SIZE)
+#define NRF91_SHMEM_TRACE_SIZE (CONFIG_NRF91_MODEM_SHMEM_TRACE_SIZE)
+
+#if !(NRF91_SHMEM_CTRL_BASE % 4 == 0)
+#  error SHMEM base addres must be word-aligned (4 bytes)
+#endif
+
+#if !(NRF91_SHMEM_TX_BASE % 4 == 0)
+#  error SHMEM base addres must be word-aligned (4 bytes)
+#endif
+
+#if !(NRF91_SHMEM_RX_BASE % 4 == 0)
+#  error SHMEM base addres must be word-aligned (4 bytes)
+#endif
+
+#if !(NRF91_SHMEM_TRACE_BASE % 4 == 0)
+#  error SHMEM base addres must be word-aligned (4 bytes)
+#endif
+
+#ifdef CONFIG_ARCH_FPU
+#  error missing FPU configuration - FPU must be activated in SPE and NSPE
+#endif
+
+/****************************************************************************
+ * Public Functions Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: nrf91_modem_initialize
+ ****************************************************************************/
+
+int nrf91_modem_initialize(void);

arch/arm/src/nrf91/nrf91_modem_at.c

@@ -0,0 +1,255 @@
+/****************************************************************************
+ * arch/arm/src/nrf91/nrf91_modem_at.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <nuttx/fs/fs.h>
+#include <nuttx/mutex.h>
+
+#include <debug.h>
+#include <fcntl.h>
+#include <semaphore.h>
+#include <string.h>
+
+#include "nrf_modem_at.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define NRF91_MODEM_AT_RX 255
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+struct nrf91_modem_at_s
+{
+  char    rxbuf[NRF91_MODEM_AT_RX];
+  size_t  rx_i;
+  sem_t   rx_sem;
+  mutex_t lock;
+};
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+static void nrf91_modem_at_notify_handler(const char *notif);
+static void nrf91_modem_at_resp_handler(const char *resp);
+static ssize_t nrf91_modem_at_read(struct file *filep, char *buffer,
+                                   size_t buflen);
+static ssize_t nrf91_modem_at_write(struct file *filep, const char *buffer,
+                                    size_t buflen);
+static int nrf91_modem_at_ioctl(struct file *filep, int cmd,
+                                unsigned long arg);
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static const struct file_operations g_nrf91_modem_at_fops =
+{
+  NULL,                 /* open */
+  NULL,                 /* close */
+  nrf91_modem_at_read,  /* read */
+  nrf91_modem_at_write, /* write */
+  NULL,                 /* seek */
+  nrf91_modem_at_ioctl, /* ioctl */
+  NULL,                 /* mmap */
+  NULL,                 /* truncate */
+  NULL                  /* poll */
+};
+
+static struct nrf91_modem_at_s g_nrf91_modem_at;
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: nrf91_modem_at_notify_handler
+ ****************************************************************************/
+
+static void nrf91_modem_at_notify_handler(const char *notif)
+{
+  struct nrf91_modem_at_s *dev = &g_nrf91_modem_at;
+
+  /* Copy notify */
+
+  strncpy(&dev->rxbuf[dev->rx_i], notif, NRF91_MODEM_AT_RX - dev->rx_i);
+  dev->rx_i += strlen(notif);
+
+  /* Wake-up any thread waiting in recv */
+
+  nxsem_post(&dev->rx_sem);
+}
+
+/****************************************************************************
+ * Name: nrf91_modem_at_resp_handler
+ ****************************************************************************/
+
+static void nrf91_modem_at_resp_handler(const char *resp)
+{
+  struct nrf91_modem_at_s *dev = &g_nrf91_modem_at;
+
+  /* Copy response */
+
+  strncpy(&dev->rxbuf[dev->rx_i], resp, NRF91_MODEM_AT_RX - dev->rx_i);
+  dev->rx_i += strlen(resp);
+
+  /* Wake-up any thread waiting in recv */
+
+  nxsem_post(&dev->rx_sem);
+}
+
+/****************************************************************************
+ * Name: nrf91_modem_at_read
+ ****************************************************************************/
+
+static ssize_t nrf91_modem_at_read(struct file *filep, char *buffer,
+                                   size_t len)
+{
+  struct nrf91_modem_at_s *dev   = NULL;
+  struct inode            *inode = NULL;
+  int                      ret   = 0;
+
+  DEBUGASSERT(filep);
+  inode = filep->f_inode;
+
+  DEBUGASSERT(inode && inode->i_private);
+  dev = (struct nrf91_modem_at_s *)inode->i_private;
+
+  ret = nxmutex_lock(&dev->lock);
+  if (ret < 0)
+    {
+      return ret;
+    }
+
+  if ((filep->f_oflags & O_NONBLOCK) != 0)
+    {
+      nxsem_trywait(&dev->rx_sem);
+      ret = 0;
+    }
+  else
+    {
+      ret = nxsem_wait(&dev->rx_sem);
+    }
+
+  if (ret < 0)
+    {
+      return ret;
+    }
+
+  /* Get response data */
+
+  if (len > dev->rx_i)
+    {
+      len = dev->rx_i;
+    }
+
+  strncpy(buffer, dev->rxbuf, len);
+  dev->rx_i = 0;
+  ret = len;
+
+  nxmutex_unlock(&dev->lock);
+  return ret;
+}
+
+/****************************************************************************
+ * Name: nrf91_modem_at_write
+ ****************************************************************************/
+
+static ssize_t nrf91_modem_at_write(struct file *filep, const char *buffer,
+                                    size_t len)
+{
+  struct nrf91_modem_at_s *dev   = NULL;
+  struct inode            *inode = NULL;
+  int                      ret   = 0;
+
+  DEBUGASSERT(filep);
+  inode = filep->f_inode;
+
+  DEBUGASSERT(inode && inode->i_private);
+  dev = (struct nrf91_modem_at_s *)inode->i_private;
+
+  ret = nxmutex_lock(&dev->lock);
+  if (ret < 0)
+    {
+      return ret;
+    }
+
+  /* Send AT command */
+
+  ret = nrf_modem_at_cmd_async(nrf91_modem_at_resp_handler, buffer);
+
+  nxmutex_unlock(&dev->lock);
+  return ret;
+}
+
+/****************************************************************************
+ * Name: nrf91_modem_at_ioct
+ ****************************************************************************/
+
+static int nrf91_modem_at_ioctl(struct file *filep, int cmd,
+                                unsigned long arg)
+{
+  return -ENOTTY;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: nrf91_at_register
+ ****************************************************************************/
+
+int nrf91_at_register(const char *path)
+{
+  struct nrf91_modem_at_s *dev = &g_nrf91_modem_at;
+  int                      ret = OK;
+
+  /* Initialize mutex & sem */
+
+  memset(&g_nrf91_modem_at, 0, sizeof(struct nrf91_modem_at_s));
+
+  nxmutex_init(&dev->lock);
+  nxsem_init(&dev->rx_sem, 0, 0);
+
+  /* Initialize AT modem */
+
+  nrf_modem_at_notif_handler_set(nrf91_modem_at_notify_handler);
+  nrf_modem_at_cmd_custom_set(NULL, 0);
+
+  /* Register driver */
+
+  ret = register_driver(path, &g_nrf91_modem_at_fops, 0666, dev);
+  if (ret < 0)
+    {
+      nerr("ERROR: register_driver failed: %d\n", ret);
+    }
+
+  return ret;
+}

arch/arm/src/nrf91/nrf91_modem_at.h

@@ -0,0 +1,35 @@
+/****************************************************************************
+ * arch/arm/src/nrf91/nrf91_modem_at.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+/****************************************************************************
+ * Public Functions Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: nrf91_at_register
+ ****************************************************************************/
+
+int nrf91_at_register(const char *path);

arch/arm/src/nrf91/nrf91_nrfx_ipc.c

@@ -0,0 +1,168 @@
+/****************************************************************************
+ * arch/arm/src/nrf91/nrf91_nrfx_ipc.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+
+#include "arm_internal.h"
+
+#include "hardware/nrf91_ipc.h"
+
+#include "nrf91_nrfx_ipc.h"
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static nrfx_ipc_handler_t g_nrfx_ipc_handler = NULL;
+static void *g_nrfx_ipc_context = NULL;
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: nrfx_ipc_irq_handler
+ ****************************************************************************/
+
+static int nrfx_ipc_irq_handler(int irq, void *context, void *arg)
+{
+  uint32_t regval = 0;
+  int      i      = 0;
+
+  regval = getreg32(NRF91_IPC_INTPEND);
+
+  for (i = 0; i < NRF91_IPC_CHANS; i += 1)
+    {
+      if (regval & IPC_CHAN_ID(i))
+        {
+          /* Clear EVENT */
+
+          putreg32(0, NRF91_IPC_EVENTS_RECEIVE(i));
+
+          /* Handle event */
+
+          g_nrfx_ipc_handler(i, g_nrfx_ipc_context);
+        }
+    }
+
+  return 0;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: nrfx_ipc_init
+ ****************************************************************************/
+
+nrfx_err_t nrfx_ipc_init(uint8_t irq_priority, nrfx_ipc_handler_t handler,
+                         void *context)
+{
+  /* Store arguments */
+
+  g_nrfx_ipc_handler = handler;
+  g_nrfx_ipc_context = context;
+
+  /* Attach modem IPC handler and set priority */
+
+  irq_attach(NRF91_IRQ_IPC, nrfx_ipc_irq_handler, 0);
+  up_prioritize_irq(NRF91_IRQ_IPC, irq_priority);
+
+#if 0
+  /* IPC interrupts non-secure */
+
+  up_secure_irq(NRF91_IRQ_IPC, false);
+#endif
+
+  /* Enable IPC interrupts */
+
+  up_enable_irq(NRF91_IRQ_IPC);
+
+  return 0;
+}
+
+/****************************************************************************
+ * Name: nrfx_ipc_uninit
+ ****************************************************************************/
+
+void nrfx_ipc_uninit(void)
+{
+  up_disable_irq(NRF91_IRQ_IPC);
+}
+
+/****************************************************************************
+ * Name: nrfx_ipc_config_load
+ ****************************************************************************/
+
+void nrfx_ipc_config_load(const nrfx_ipc_config_t *config)
+{
+  int i = 0;
+
+  /* Configure send events */
+
+  for (i = 0; i < IPC_CONF_NUM; i++)
+    {
+      putreg32(config->send_task_config[i],
+               NRF91_IPC_SEND_CNF(i));
+    }
+
+  /* Configure receive events */
+
+  for (i = 0; i < IPC_CONF_NUM; i++)
+    {
+      putreg32(config->receive_event_config[i],
+               NRF91_IPC_RECEIVE_CNF(i));
+    }
+
+  /* Enable interrupts for a given channel */
+
+  putreg32(config->receive_events_enabled,
+           NRF91_IPC_INTENSET);
+}
+
+/****************************************************************************
+ * Name: nrfx_ipc_receive_event_enable
+ ****************************************************************************/
+
+void nrfx_ipc_receive_event_enable(uint8_t event_index)
+{
+  /* Enable interrupts for a given channel */
+
+  putreg32(IPC_CHAN_ID(event_index), NRF91_IPC_INTENSET);
+}
+
+/****************************************************************************
+ * Name: nrfx_ipc_receive_event_disable
+ ****************************************************************************/
+
+void nrfx_ipc_receive_event_disable(uint8_t event_index)
+{
+  /* Disable interrupts for a given channel */
+
+  putreg32(IPC_CHAN_ID(event_index), NRF91_IPC_INTENCLR);
+}

arch/arm/src/nrf91/nrf91_nrfx_ipc.h

@@ -0,0 +1,85 @@
+/****************************************************************************
+ * arch/arm/src/nrf91/nrf91_nrfx_ipc.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+
+#include "hardware/nrf91_memorymap.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define IPC_CONF_NUM (NRF91_IPC_CHANS)
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+typedef void (*nrfx_ipc_handler_t)(uint8_t event_idx, void *context);
+
+typedef struct
+{
+  uint32_t send_task_config[IPC_CONF_NUM];
+  uint32_t receive_event_config[IPC_CONF_NUM];
+  uint32_t receive_events_enabled;
+} nrfx_ipc_config_t;
+
+typedef int nrfx_err_t;
+
+/****************************************************************************
+ * Public Functions Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: nrfx_ipc_uninit
+ ****************************************************************************/
+
+void nrfx_ipc_uninit(void);
+
+/****************************************************************************
+ * Name: nrfx_ipc_init
+ ****************************************************************************/
+
+nrfx_err_t nrfx_ipc_init(uint8_t irq_priority, nrfx_ipc_handler_t handler,
+                         void *context);
+
+/****************************************************************************
+ * Name: nrfx_ipc_config_load
+ ****************************************************************************/
+
+void nrfx_ipc_config_load(const nrfx_ipc_config_t *config);
+
+/****************************************************************************
+ * Name: nrfx_ipc_receive_event_enable
+ ****************************************************************************/
+
+void nrfx_ipc_receive_event_enable(uint8_t event_index);
+
+/****************************************************************************
+ * Name: nrfx_ipc_receive_event_disable
+ ****************************************************************************/
+
+void nrfx_ipc_receive_event_disable(uint8_t event_index);

arch/arm/src/nrf91/nrf91_rtc.h

@@ -0,0 +1,139 @@
+/****************************************************************************
+ * arch/arm/src/nrf91/nrf91_rtc.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_NRF91_NRF91_RTC_H
+#define __ARCH_ARM_SRC_NRF91_NRF91_RTC_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Helpers ******************************************************************/
+
+#define NRF91_RTC_START(d)                ((d)->ops->start(d))
+#define NRF91_RTC_STOP(d)                 ((d)->ops->stop(d))
+#define NRF91_RTC_CLEAR(d)                ((d)->ops->clear(d))
+#define NRF91_RTC_TRGOVRFLW(d)            ((d)->ops->trgovrflw(d))
+#define NRF91_RTC_GETCOUNTER(d, c)        ((d)->ops->getcounter(d, c))
+#define NRF91_RTC_SETCC(d, i, cc)         ((d)->ops->setcc(d, i, cc))
+#define NRF91_RTC_GETCC(d, i, cc)         ((d)->ops->setcc(d, i, cc))
+#define NRF91_RTC_SETPRE(d, pre)          ((d)->ops->setpre(d, pre))
+#define NRF91_RTC_SETISR(d, hnd, arg)     ((d)->ops->setisr(d, hnd, arg))
+#define NRF91_RTC_ENABLEINT(d, s)         ((d)->ops->enableint(d, s))
+#define NRF91_RTC_DISABLEINT(d, s)        ((d)->ops->disableint(d, s))
+#define NRF91_RTC_CHECKINT(d, s)          ((d)->ops->checkint(d, s))
+#define NRF91_RTC_ACKINT(d, s)            ((d)->ops->ackint(d, s))
+#define NRF91_RTC_ENABLEEVT(d, s)         ((d)->ops->enableevt(d, s))
+#define NRF91_RTC_DISABLEEVT(d, s)        ((d)->ops->disableevt(d, s))
+#define NRF91_RTC_GETBASE(d)              ((d)->ops->getbase(d))
+
+/* These are defined for direct access to registers, which is needed in some
+ * critical parts where access speed is important
+ */
+
+#define NRF91_RTC_GETCOUNTER_REG(base)    (getreg32(base + NRF91_RTC_COUNTER_OFFSET))
+#define NRF91_RTC_SETCC_REG(base, ch, cc) (putreg32(cc, base + NRF91_RTC_CC_OFFSET(ch)))
+#define NRF91_RTC_GETCC_REG(base, ch)     (getreg32(base + NRF91_RTC_CC_OFFSET(ch)))
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/* RTC CC index */
+
+enum nrf91_rtc_cc_e
+{
+  NRF91_RTC_CC0 = 0,
+  NRF91_RTC_CC1 = 1,
+  NRF91_RTC_CC2 = 2,
+  NRF91_RTC_CC3 = 3,
+};
+
+/* RTC Interrupts/Events */
+
+enum nrf91_rtc_evt_e
+{
+  NRF91_RTC_EVT_TICK     = 0,
+  NRF91_RTC_EVT_OVRFLW   = 1,
+  NRF91_RTC_EVT_COMPARE0 = 2,
+  NRF91_RTC_EVT_COMPARE1 = 3,
+  NRF91_RTC_EVT_COMPARE2 = 4,
+  NRF91_RTC_EVT_COMPARE3 = 5,
+};
+
+/* NRF91 RTC device */
+
+struct nrf91_rtc_dev_s
+{
+  struct nrf91_rtc_ops_s *ops;
+};
+
+/* NRF91 RTC ops */
+
+struct nrf91_rtc_ops_s
+{
+  /* RTC tasks */
+
+  int (*start)(struct nrf91_rtc_dev_s *dev);
+  int (*stop)(struct nrf91_rtc_dev_s *dev);
+  int (*clear)(struct nrf91_rtc_dev_s *dev);
+  int (*trgovrflw)(struct nrf91_rtc_dev_s *dev);
+
+  /* RTC operations */
+
+  int (*getcounter)(struct nrf91_rtc_dev_s *dev, uint32_t *cc);
+  int (*setcc)(struct nrf91_rtc_dev_s *dev, uint8_t i, uint32_t cc);
+  int (*getcc)(struct nrf91_rtc_dev_s *dev, uint8_t i, uint32_t *cc);
+  int (*setpre)(struct nrf91_rtc_dev_s *dev, uint16_t pre);
+
+  /* RTC interrupts */
+
+  int (*setisr)(struct nrf91_rtc_dev_s *dev, xcpt_t handler, void *arg);
+  int (*enableint)(struct nrf91_rtc_dev_s *dev, uint8_t source);
+  int (*disableint)(struct nrf91_rtc_dev_s *dev, uint8_t source);
+  int (*checkint)(struct nrf91_rtc_dev_s *dev, uint8_t source);
+  int (*ackint)(struct nrf91_rtc_dev_s *dev, uint8_t source);
+
+  /* RTC events */
+
+  int (*enableevt)(struct nrf91_rtc_dev_s *dev, uint8_t evt);
+  int (*disableevt)(struct nrf91_rtc_dev_s *dev, uint8_t evt);
+
+  /* Utility */
+
+  uint32_t (*getbase)(struct nrf91_rtc_dev_s *dev);
+};
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+struct nrf91_rtc_dev_s *nrf91_rtc_init(int rtc);
+int nrf91_rtc_deinit(struct nrf91_rtc_dev_s *dev);
+
+#endif /* __ARCH_ARM_SRC_NRF91_NRF91_RTC_H */

arch/arm/src/nrf91/nrf91_serial.h

@@ -0,0 +1,52 @@
+/****************************************************************************
+ * arch/arm/src/nrf91/nrf91_serial.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_NRF91_NRF91_SERIAL_H
+#define __ARCH_ARM_SRC_NRF91_NRF91_SERIAL_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "nrf91_config.h"
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: nrf91_earlyserialinit
+ *
+ * Description:
+ *   Performs the low level UART initialization early in debug so that the
+ *   serial console will be available during bootup.  This must be called
+ *   before nrf91_serialinit.  NOTE:  This function depends on GPIO pin
+ *   configuration performed in xmc_lowsetup() and main clock initialization
+ *   performed in xmc_clock_configure().
+ *
+ ****************************************************************************/
+
+#ifdef USE_EARLYSERIALINIT
+void nrf91_earlyserialinit(void);
+#endif
+
+#endif /* __ARCH_ARM_SRC_NRF91_NRF91@_SERIAL_H */