diff --git a/arch/arm/include/xmc4/chip.h b/arch/arm/include/xmc4/chip.h index 7ea5157a736..019c1078230 100644 --- a/arch/arm/include/xmc4/chip.h +++ b/arch/arm/include/xmc4/chip.h @@ -48,11 +48,11 @@ /* Get customizations for each supported chip */ -#if defined(CONFIG_ARCH_XMC4500) +#if defined(CONFIG_ARCH_CHIP_XMC4500) # define XM4_NUSIC 3 /* Three USIC modules: USCI0-2 */ #else -# error "Unsupported XMC4000 chip" +# error "Unsupported XMC4xxx chip" #endif /* NVIC priority levels *************************************************************/ diff --git a/arch/arm/include/xmc4/irq.h b/arch/arm/include/xmc4/irq.h index 65300dcee3b..10fc176a43c 100644 --- a/arch/arm/include/xmc4/irq.h +++ b/arch/arm/include/xmc4/irq.h @@ -37,8 +37,8 @@ * through nuttx/irq.h */ -#ifndef __ARCH_ARM_INCLUDE_XM4_IRQ_H -#define __ARCH_ARM_INCLUDE_XM4_IRQ_H +#ifndef __ARCH_ARM_INCLUDE_XMC4_IRQ_H +#define __ARCH_ARM_INCLUDE_XMC4_IRQ_H /************************************************************************************ * Included Files @@ -58,26 +58,26 @@ /* Processor Exceptions (vectors 0-15) */ -#define XM4_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ - /* Vector 0: Reset stack pointer value */ - /* Vector 1: Reset (not handler as an IRQ) */ -#define XM4_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ -#define XM4_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ -#define XM4_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ -#define XM4_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ -#define XM4_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ - /* Vectors 7-10: Reserved */ -#define XM4_IRQ_SVCALL (11) /* Vector 11: SVC call */ -#define XM4_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */ - /* Vector 13: Reserved */ -#define XM4_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ -#define XM4_IRQ_SYSTICK (15) /* Vector 15: System tick */ +#define XMC4_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ + /* Vector 0: Reset stack pointer value */ + /* Vector 1: Reset (not handler as an IRQ) */ +#define XMC4_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ +#define XMC4_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ +#define XMC4_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ +#define XMC4_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ +#define XMC4_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ + /* Vectors 7-10: Reserved */ +#define XMC4_IRQ_SVCALL (11) /* Vector 11: SVC call */ +#define XMC4_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */ + /* Vector 13: Reserved */ +#define XMC4_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ +#define XMC4_IRQ_SYSTICK (15) /* Vector 15: System tick */ /* External interrupts (vectors >= 16). These definitions are chip-specific */ -#define XM4_IRQ_FIRST (16) /* Vector number of the first external interrupt */ +#define XMC4_IRQ_FIRST (16) /* Vector number of the first external interrupt */ -#if defined(CONFIG_ARCH_XMC4500) +#if defined(CONFIG_ARCH_CHIP_XMC4500) # include #else /* The interrupt vectors for other parts are defined in other documents and may or @@ -116,5 +116,5 @@ extern "C" #endif #endif -#endif /* __ARCH_ARM_INCLUDE_XM4_IRQ_H */ +#endif /* __ARCH_ARM_INCLUDE_XMC4_IRQ_H */ diff --git a/arch/arm/include/xmc4/xmc4500_irq.h b/arch/arm/include/xmc4/xmc4500_irq.h index 1005adeb495..dfd21d6c21d 100644 --- a/arch/arm/include/xmc4/xmc4500_irq.h +++ b/arch/arm/include/xmc4/xmc4500_irq.h @@ -37,8 +37,8 @@ * through nuttx/irq.h */ -#ifndef xmc4__ARCH_ARM_INCLUDE_XM4_XM4500_IRQ_H -#define xmc4__ARCH_ARM_INCLUDE_XM4_XM4500_IRQ_H +#ifndef xmc4__ARCH_ARM_INCLUDE_XMC4_XM4500_IRQ_H +#define xmc4__ARCH_ARM_INCLUDE_XMC4_XM4500_IRQ_H /***************************************************************************** * Included Files @@ -75,125 +75,125 @@ * USCI - Universal Serial Interface */ -#define XM4_IRQ_SCU (XM4_IRQ_FIRST+0) /* 0: System Control */ -#define XM4_IRQ_ERU0_SR0 (XM4_IRQ_FIRST+1) /* 1: ERU0, SR0 */ -#define XM4_IRQ_ERU0_SR1 (XM4_IRQ_FIRST+2) /* 2: ERU0, SR1 */ -#define XM4_IRQ_ERU0_SR2 (XM4_IRQ_FIRST+3) /* 3: ERU0, SR2 */ -#define XM4_IRQ_ERU0_SR3 (XM4_IRQ_FIRST+4) /* 4: ERU0, SR3 */ -#define XM4_IRQ_ERU1_SR0 (XM4_IRQ_FIRST+5) /* 5: ERU1, SR0 */ -#define XM4_IRQ_ERU1_SR1 (XM4_IRQ_FIRST+6) /* 6: ERU1, SR1 */ -#define XM4_IRQ_ERU1_SR2 (XM4_IRQ_FIRST+7) /* 7: ERU1, SR2 */ -#define XM4_IRQ_ERU1_SR3 (XM4_IRQ_FIRST+8) /* 8: ERU1, SR3 */ -#define XM4_IRQ_RESVD009 (XM4_IRQ_FIRST+9) /* 9: Reserved */ -#define XM4_IRQ_RESVD010 (XM4_IRQ_FIRST+10) /* 10: Reserved */ -#define XM4_IRQ_RESVD011 (XM4_IRQ_FIRST+11) /* 11: Reserved */ -#define XM4_IRQ_PMU1_SR0 (XM4_IRQ_FIRST+12) /* 12: PMU, SR0 */ -#define XM4_IRQ_RESVD011 (XM4_IRQ_FIRST+13) /* 13: Reserved */ -#define XM4_IRQ_VADC_COSR0 (XM4_IRQ_FIRST+14) /* 14: ADC Common Block 0 */ -#define XM4_IRQ_VADC_COSR1 (XM4_IRQ_FIRST+15) /* 15: ADC Common Block 1 */ -#define XM4_IRQ_VADC_COSR2 (XM4_IRQ_FIRST+16) /* 16: ADC Common Block 2 */ -#define XM4_IRQ_VADC_COSR3 (XM4_IRQ_FIRST+17) /* 17: ADC Common Block 3 */ -#define XM4_IRQ_VADC_GOSR0 (XM4_IRQ_FIRST+18) /* 18: ADC Group 0, SR0 */ -#define XM4_IRQ_VADC_GOSR1 (XM4_IRQ_FIRST+19) /* 19: ADC Group 0, SR1 */ -#define XM4_IRQ_VADC_GOSR2 (XM4_IRQ_FIRST+20) /* 20: ADC Group 0, SR2 */ -#define XM4_IRQ_VADC_GOSR3 (XM4_IRQ_FIRST+21) /* 21: ADC Group 0, SR3 */ -#define XM4_IRQ_VADC_G1SR0 (XM4_IRQ_FIRST+22) /* 22: ADC Group 1, SR0 */ -#define XM4_IRQ_VADC_G1SR1 (XM4_IRQ_FIRST+23) /* 23: ADC Group 1, SR1 */ -#define XM4_IRQ_VADC_G1SR2 (XM4_IRQ_FIRST+24) /* 24: ADC Group 1, SR2 */ -#define XM4_IRQ_VADC_G1SR3 (XM4_IRQ_FIRST+25) /* 25: ADC Group 1, SR3 */ -#define XM4_IRQ_VADC_G2SR0 (XM4_IRQ_FIRST+26) /* 26: ADC Group 2, SR0 */ -#define XM4_IRQ_VADC_G2SR1 (XM4_IRQ_FIRST+27) /* 27: ADC Group 2, SR1 */ -#define XM4_IRQ_VADC_G2SR2 (XM4_IRQ_FIRST+28) /* 28: ADC Group 2, SR2 */ -#define XM4_IRQ_VADC_G2SR3 (XM4_IRQ_FIRST+29) /* 29: ADC Group 2, SR3 */ -#define XM4_IRQ_VADC_G3SR0 (XM4_IRQ_FIRST+30) /* 30: ADC Group 3, SR0 */ -#define XM4_IRQ_VADC_G3SR1 (XM4_IRQ_FIRST+31) /* 31: ADC Group 3, SR1 */ -#define XM4_IRQ_VADC_G3SR2 (XM4_IRQ_FIRST+32) /* 32: ADC Group 3, SR2 */ -#define XM4_IRQ_VADC_G3SR3 (XM4_IRQ_FIRST+33) /* 33: ADC Group 3, SR3 */ -#define XM4_IRQ_DSD_SRM0 (XM4_IRQ_FIRST+34) /* 34: DSD Main, SRM0 */ -#define XM4_IRQ_DSD_SRM1 (XM4_IRQ_FIRST+35) /* 35: DSD Main, SRM1 */ -#define XM4_IRQ_DSD_SRM2 (XM4_IRQ_FIRST+36) /* 36: DSD Main, SRM2 */ -#define XM4_IRQ_DSD_SRM3 (XM4_IRQ_FIRST+37) /* 37: DSD Main, SRM3 */ -#define XM4_IRQ_DSD_SRA0 (XM4_IRQ_FIRST+38) /* 38: DSD Auxiliary, SRA0 */ -#define XM4_IRQ_DSD_SRA1 (XM4_IRQ_FIRST+39) /* 39: DSD Auxiliary, SRA1 */ -#define XM4_IRQ_DSD_SRA2 (XM4_IRQ_FIRST+40) /* 40: DSD Auxiliary, SRA2 */ -#define XM4_IRQ_DSD_SRA3 (XM4_IRQ_FIRST+41) /* 41: DSD Auxiliary, SRA3 */ -#define XM4_IRQ_DAC_SR0 (XM4_IRQ_FIRST+42) /* 42: DAC, SR0 */ -#define XM4_IRQ_DAC_SR1 (XM4_IRQ_FIRST+43) /* 43: DAC, SR1 */ -#define XM4_IRQ_CCU40_SR0 (XM4_IRQ_FIRST+44) /* 44: CCU4 Module 0, SR0 */ -#define XM4_IRQ_CCU40_SR1 (XM4_IRQ_FIRST+45) /* 45: CCU4 Module 0, SR1 */ -#define XM4_IRQ_CCU40_SR2 (XM4_IRQ_FIRST+46) /* 46: CCU4 Module 0, SR2 */ -#define XM4_IRQ_CCU40_SR3 (XM4_IRQ_FIRST+47) /* 47: CCU4 Module 0, SR3 */ -#define XM4_IRQ_CCU41_SR0 (XM4_IRQ_FIRST+48) /* 48: CCU4 Module 1, SR0 */ -#define XM4_IRQ_CCU41_SR1 (XM4_IRQ_FIRST+49) /* 49: CCU4 Module 1, SR1 */ -#define XM4_IRQ_CCU41_SR2 (XM4_IRQ_FIRST+50) /* 50: CCU4 Module 1, SR2 */ -#define XM4_IRQ_CCU41_SR3 (XM4_IRQ_FIRST+51) /* 51: CCU4 Module 1, SR3 */ -#define XM4_IRQ_CCU42_SR0 (XM4_IRQ_FIRST+52) /* 52: CCU4 Module 2, SR0 */ -#define XM4_IRQ_CCU42_SR1 (XM4_IRQ_FIRST+53) /* 53: CCU4 Module 2, SR1 */ -#define XM4_IRQ_CCU42_SR2 (XM4_IRQ_FIRST+54) /* 54: CCU4 Module 2, SR2 */ -#define XM4_IRQ_CCU42_SR3 (XM4_IRQ_FIRST+55) /* 55: CCU4 Module 2, SR3 */ -#define XM4_IRQ_CCU43_SR0 (XM4_IRQ_FIRST+56) /* 56: CCU4 Module 3, SR0 */ -#define XM4_IRQ_CCU43_SR1 (XM4_IRQ_FIRST+57) /* 57: CCU4 Module 3, SR1 */ -#define XM4_IRQ_CCU43_SR2 (XM4_IRQ_FIRST+58) /* 58: CCU4 Module 3, SR2 */ -#define XM4_IRQ_CCU43_SR3 (XM4_IRQ_FIRST+59) /* 59: CCU4 Module 3, SR3 */ -#define XM4_IRQ_CCU80_SR0 (XM4_IRQ_FIRST+60) /* 60: CCU8 Module 0, SR0 */ -#define XM4_IRQ_CCU80_SR1 (XM4_IRQ_FIRST+61) /* 61: CCU8 Module 0, SR1 */ -#define XM4_IRQ_CCU80_SR2 (XM4_IRQ_FIRST+62) /* 62: CCU8 Module 0, SR2 */ -#define XM4_IRQ_CCU80_SR3 (XM4_IRQ_FIRST+63) /* 63: CCU8 Module 0, SR3 */ -#define XM4_IRQ_CCU81_SR0 (XM4_IRQ_FIRST+64) /* 64: CCU8 Module 1, SR0 */ -#define XM4_IRQ_CCU81_SR1 (XM4_IRQ_FIRST+65) /* 65: CCU8 Module 1, SR1 */ -#define XM4_IRQ_CCU81_SR2 (XM4_IRQ_FIRST+66) /* 66: CCU8 Module 1, SR2 */ -#define XM4_IRQ_CCU81_SR3 (XM4_IRQ_FIRST+67) /* 67: CCU8 Module 1, SR3 */ -#define XM4_IRQ_POSIF0_SR0 (XM4_IRQ_FIRST+68) /* 68: POSIF Module 0, SR0 */ -#define XM4_IRQ_POSIF0_SR1 (XM4_IRQ_FIRST+69) /* 69: POSIF Module 0, SR1 */ -#define XM4_IRQ_POSIF1_SR0 (XM4_IRQ_FIRST+70) /* 70: POSIF Module 1, SR0 */ -#define XM4_IRQ_POSIF1_SR1 (XM4_IRQ_FIRST+71) /* 71: POSIF Module 1, SR1 */ -#define XM4_IRQ_RESVD072 (XM4_IRQ_FIRST+72) /* 72: Reserved */ -#define XM4_IRQ_RESVD073 (XM4_IRQ_FIRST+73) /* 73: Reserved */ -#define XM4_IRQ_RESVD074 (XM4_IRQ_FIRST+74) /* 74: Reserved */ -#define XM4_IRQ_RESVD075 (XM4_IRQ_FIRST+75) /* 75: Reserved */ -#define XM4_IRQ_CAN_SR0 (XM4_IRQ_FIRST+76) /* 76: MultiCAN, SR0 */ -#define XM4_IRQ_CAN_SR1 (XM4_IRQ_FIRST+77) /* 77: MultiCAN, SR1 */ -#define XM4_IRQ_CAN_SR2 (XM4_IRQ_FIRST+78) /* 78: MultiCAN, SR2 */ -#define XM4_IRQ_CAN_SR3 (XM4_IRQ_FIRST+79) /* 79: MultiCAN, SR3 */ -#define XM4_IRQ_CAN_SR4 (XM4_IRQ_FIRST+80) /* 80: MultiCAN, SR4 */ -#define XM4_IRQ_CAN_SR5 (XM4_IRQ_FIRST+81) /* 81: MultiCAN, SR5 */ -#define XM4_IRQ_CAN_SR6 (XM4_IRQ_FIRST+82) /* 82: MultiCAN, SR6 */ -#define XM4_IRQ_CAN_SR7 (XM4_IRQ_FIRST+83) /* 83: MultiCAN, SR7 */ -#define XM4_IRQ_USIC0_SR0 (XM4_IRQ_FIRST+84) /* 84: USIC0 Channel, SR0 */ -#define XM4_IRQ_USIC0_SR1 (XM4_IRQ_FIRST+85) /* 85: USIC0 Channel, SR1 */ -#define XM4_IRQ_USIC0_SR2 (XM4_IRQ_FIRST+86) /* 86: USIC0 Channel, SR2 */ -#define XM4_IRQ_USIC0_SR3 (XM4_IRQ_FIRST+87) /* 87: USIC0 Channel, SR3 */ -#define XM4_IRQ_USIC0_SR4 (XM4_IRQ_FIRST+88) /* 88: USIC0 Channel, SR4 */ -#define XM4_IRQ_USIC0_SR5 (XM4_IRQ_FIRST+89) /* 89: USIC0 Channel, SR5 */ -#define XM4_IRQ_USIC1_SR0 (XM4_IRQ_FIRST+90) /* 90: USIC1 Channel, SR0 */ -#define XM4_IRQ_USIC1_SR1 (XM4_IRQ_FIRST+91) /* 91: USIC1 Channel, SR1 */ -#define XM4_IRQ_USIC1_SR2 (XM4_IRQ_FIRST+92) /* 92: USIC1 Channel, SR2 */ -#define XM4_IRQ_USIC1_SR3 (XM4_IRQ_FIRST+93) /* 93: USIC1 Channel, SR3 */ -#define XM4_IRQ_USIC1_SR4 (XM4_IRQ_FIRST+94) /* 94: USIC1 Channel, SR4 */ -#define XM4_IRQ_USIC1_SR5 (XM4_IRQ_FIRST+95) /* 95: USIC1 Channel, SR5 */ -#define XM4_IRQ_USIC2_SR0 (XM4_IRQ_FIRST+96) /* 96: USIC1 Channel, SR0 */ -#define XM4_IRQ_USIC2_SR1 (XM4_IRQ_FIRST+97) /* 97: USIC1 Channel, SR1 */ -#define XM4_IRQ_USIC2_SR2 (XM4_IRQ_FIRST+98) /* 98: USIC1 Channel, SR2 */ -#define XM4_IRQ_USIC2_SR3 (XM4_IRQ_FIRST+99) /* 99: USIC1 Channel, SR3 */ -#define XM4_IRQ_USIC2_SR4 (XM4_IRQ_FIRST+100) /* 100: USIC1 Channel, SR4 */ -#define XM4_IRQ_USIC2_SR5 (XM4_IRQ_FIRST+101) /* 101: USIC1 Channel, SR5 */ -#define XM4_IRQ_LEDTS0_SR0 (XM4_IRQ_FIRST+102) /* 102: LEDTS0, SR0 */ -#define XM4_IRQ_RESVD103 (XM4_IRQ_FIRST+103) /* 103: Reserved */ -#define XM4_IRQ_FCR_SR0 (XM4_IRQ_FIRST+104) /* 102: FCE, SR0 */ -#define XM4_IRQ_GPCMA0_SR0 (XM4_IRQ_FIRST+105) /* 105: GPDMA0, SR0 */ -#define XM4_IRQ_SDMMC_SR0 (XM4_IRQ_FIRST+106) /* 106: SDMMC, SR0 */ -#define XM4_IRQ_USB0_SR0 (XM4_IRQ_FIRST+107) /* 107: USB, SR0 */ -#define XM4_IRQ_ETH0_SR0 (XM4_IRQ_FIRST+108) /* 108: Ethernet, module 0, SR0 */ -#define XM4_IRQ_RESVD109 (XM4_IRQ_FIRST+109) /* 109: Reserved */ -#define XM4_IRQ_GPCMA1_SR0 (XM4_IRQ_FIRST+110) /* 110: GPDMA1, SR0 */ -#define XM4_IRQ_RESVD111 (XM4_IRQ_FIRST+111) /* 111: Reserved */ +#define XMC4_IRQ_SCU (XMC4_IRQ_FIRST+0) /* 0: System Control */ +#define XMC4_IRQ_ERU0_SR0 (XMC4_IRQ_FIRST+1) /* 1: ERU0, SR0 */ +#define XMC4_IRQ_ERU0_SR1 (XMC4_IRQ_FIRST+2) /* 2: ERU0, SR1 */ +#define XMC4_IRQ_ERU0_SR2 (XMC4_IRQ_FIRST+3) /* 3: ERU0, SR2 */ +#define XMC4_IRQ_ERU0_SR3 (XMC4_IRQ_FIRST+4) /* 4: ERU0, SR3 */ +#define XMC4_IRQ_ERU1_SR0 (XMC4_IRQ_FIRST+5) /* 5: ERU1, SR0 */ +#define XMC4_IRQ_ERU1_SR1 (XMC4_IRQ_FIRST+6) /* 6: ERU1, SR1 */ +#define XMC4_IRQ_ERU1_SR2 (XMC4_IRQ_FIRST+7) /* 7: ERU1, SR2 */ +#define XMC4_IRQ_ERU1_SR3 (XMC4_IRQ_FIRST+8) /* 8: ERU1, SR3 */ +#define XMC4_IRQ_RESVD009 (XMC4_IRQ_FIRST+9) /* 9: Reserved */ +#define XMC4_IRQ_RESVD010 (XMC4_IRQ_FIRST+10) /* 10: Reserved */ +#define XMC4_IRQ_RESVD011 (XMC4_IRQ_FIRST+11) /* 11: Reserved */ +#define XMC4_IRQ_PMU1_SR0 (XMC4_IRQ_FIRST+12) /* 12: PMU, SR0 */ +#define XMC4_IRQ_RESVD011 (XMC4_IRQ_FIRST+13) /* 13: Reserved */ +#define XMC4_IRQ_VADC_COSR0 (XMC4_IRQ_FIRST+14) /* 14: ADC Common Block 0 */ +#define XMC4_IRQ_VADC_COSR1 (XMC4_IRQ_FIRST+15) /* 15: ADC Common Block 1 */ +#define XMC4_IRQ_VADC_COSR2 (XMC4_IRQ_FIRST+16) /* 16: ADC Common Block 2 */ +#define XMC4_IRQ_VADC_COSR3 (XMC4_IRQ_FIRST+17) /* 17: ADC Common Block 3 */ +#define XMC4_IRQ_VADC_GOSR0 (XMC4_IRQ_FIRST+18) /* 18: ADC Group 0, SR0 */ +#define XMC4_IRQ_VADC_GOSR1 (XMC4_IRQ_FIRST+19) /* 19: ADC Group 0, SR1 */ +#define XMC4_IRQ_VADC_GOSR2 (XMC4_IRQ_FIRST+20) /* 20: ADC Group 0, SR2 */ +#define XMC4_IRQ_VADC_GOSR3 (XMC4_IRQ_FIRST+21) /* 21: ADC Group 0, SR3 */ +#define XMC4_IRQ_VADC_G1SR0 (XMC4_IRQ_FIRST+22) /* 22: ADC Group 1, SR0 */ +#define XMC4_IRQ_VADC_G1SR1 (XMC4_IRQ_FIRST+23) /* 23: ADC Group 1, SR1 */ +#define XMC4_IRQ_VADC_G1SR2 (XMC4_IRQ_FIRST+24) /* 24: ADC Group 1, SR2 */ +#define XMC4_IRQ_VADC_G1SR3 (XMC4_IRQ_FIRST+25) /* 25: ADC Group 1, SR3 */ +#define XMC4_IRQ_VADC_G2SR0 (XMC4_IRQ_FIRST+26) /* 26: ADC Group 2, SR0 */ +#define XMC4_IRQ_VADC_G2SR1 (XMC4_IRQ_FIRST+27) /* 27: ADC Group 2, SR1 */ +#define XMC4_IRQ_VADC_G2SR2 (XMC4_IRQ_FIRST+28) /* 28: ADC Group 2, SR2 */ +#define XMC4_IRQ_VADC_G2SR3 (XMC4_IRQ_FIRST+29) /* 29: ADC Group 2, SR3 */ +#define XMC4_IRQ_VADC_G3SR0 (XMC4_IRQ_FIRST+30) /* 30: ADC Group 3, SR0 */ +#define XMC4_IRQ_VADC_G3SR1 (XMC4_IRQ_FIRST+31) /* 31: ADC Group 3, SR1 */ +#define XMC4_IRQ_VADC_G3SR2 (XMC4_IRQ_FIRST+32) /* 32: ADC Group 3, SR2 */ +#define XMC4_IRQ_VADC_G3SR3 (XMC4_IRQ_FIRST+33) /* 33: ADC Group 3, SR3 */ +#define XMC4_IRQ_DSD_SRM0 (XMC4_IRQ_FIRST+34) /* 34: DSD Main, SRM0 */ +#define XMC4_IRQ_DSD_SRM1 (XMC4_IRQ_FIRST+35) /* 35: DSD Main, SRM1 */ +#define XMC4_IRQ_DSD_SRM2 (XMC4_IRQ_FIRST+36) /* 36: DSD Main, SRM2 */ +#define XMC4_IRQ_DSD_SRM3 (XMC4_IRQ_FIRST+37) /* 37: DSD Main, SRM3 */ +#define XMC4_IRQ_DSD_SRA0 (XMC4_IRQ_FIRST+38) /* 38: DSD Auxiliary, SRA0 */ +#define XMC4_IRQ_DSD_SRA1 (XMC4_IRQ_FIRST+39) /* 39: DSD Auxiliary, SRA1 */ +#define XMC4_IRQ_DSD_SRA2 (XMC4_IRQ_FIRST+40) /* 40: DSD Auxiliary, SRA2 */ +#define XMC4_IRQ_DSD_SRA3 (XMC4_IRQ_FIRST+41) /* 41: DSD Auxiliary, SRA3 */ +#define XMC4_IRQ_DAC_SR0 (XMC4_IRQ_FIRST+42) /* 42: DAC, SR0 */ +#define XMC4_IRQ_DAC_SR1 (XMC4_IRQ_FIRST+43) /* 43: DAC, SR1 */ +#define XMC4_IRQ_CCU40_SR0 (XMC4_IRQ_FIRST+44) /* 44: CCU4 Module 0, SR0 */ +#define XMC4_IRQ_CCU40_SR1 (XMC4_IRQ_FIRST+45) /* 45: CCU4 Module 0, SR1 */ +#define XMC4_IRQ_CCU40_SR2 (XMC4_IRQ_FIRST+46) /* 46: CCU4 Module 0, SR2 */ +#define XMC4_IRQ_CCU40_SR3 (XMC4_IRQ_FIRST+47) /* 47: CCU4 Module 0, SR3 */ +#define XMC4_IRQ_CCU41_SR0 (XMC4_IRQ_FIRST+48) /* 48: CCU4 Module 1, SR0 */ +#define XMC4_IRQ_CCU41_SR1 (XMC4_IRQ_FIRST+49) /* 49: CCU4 Module 1, SR1 */ +#define XMC4_IRQ_CCU41_SR2 (XMC4_IRQ_FIRST+50) /* 50: CCU4 Module 1, SR2 */ +#define XMC4_IRQ_CCU41_SR3 (XMC4_IRQ_FIRST+51) /* 51: CCU4 Module 1, SR3 */ +#define XMC4_IRQ_CCU42_SR0 (XMC4_IRQ_FIRST+52) /* 52: CCU4 Module 2, SR0 */ +#define XMC4_IRQ_CCU42_SR1 (XMC4_IRQ_FIRST+53) /* 53: CCU4 Module 2, SR1 */ +#define XMC4_IRQ_CCU42_SR2 (XMC4_IRQ_FIRST+54) /* 54: CCU4 Module 2, SR2 */ +#define XMC4_IRQ_CCU42_SR3 (XMC4_IRQ_FIRST+55) /* 55: CCU4 Module 2, SR3 */ +#define XMC4_IRQ_CCU43_SR0 (XMC4_IRQ_FIRST+56) /* 56: CCU4 Module 3, SR0 */ +#define XMC4_IRQ_CCU43_SR1 (XMC4_IRQ_FIRST+57) /* 57: CCU4 Module 3, SR1 */ +#define XMC4_IRQ_CCU43_SR2 (XMC4_IRQ_FIRST+58) /* 58: CCU4 Module 3, SR2 */ +#define XMC4_IRQ_CCU43_SR3 (XMC4_IRQ_FIRST+59) /* 59: CCU4 Module 3, SR3 */ +#define XMC4_IRQ_CCU80_SR0 (XMC4_IRQ_FIRST+60) /* 60: CCU8 Module 0, SR0 */ +#define XMC4_IRQ_CCU80_SR1 (XMC4_IRQ_FIRST+61) /* 61: CCU8 Module 0, SR1 */ +#define XMC4_IRQ_CCU80_SR2 (XMC4_IRQ_FIRST+62) /* 62: CCU8 Module 0, SR2 */ +#define XMC4_IRQ_CCU80_SR3 (XMC4_IRQ_FIRST+63) /* 63: CCU8 Module 0, SR3 */ +#define XMC4_IRQ_CCU81_SR0 (XMC4_IRQ_FIRST+64) /* 64: CCU8 Module 1, SR0 */ +#define XMC4_IRQ_CCU81_SR1 (XMC4_IRQ_FIRST+65) /* 65: CCU8 Module 1, SR1 */ +#define XMC4_IRQ_CCU81_SR2 (XMC4_IRQ_FIRST+66) /* 66: CCU8 Module 1, SR2 */ +#define XMC4_IRQ_CCU81_SR3 (XMC4_IRQ_FIRST+67) /* 67: CCU8 Module 1, SR3 */ +#define XMC4_IRQ_POSIF0_SR0 (XMC4_IRQ_FIRST+68) /* 68: POSIF Module 0, SR0 */ +#define XMC4_IRQ_POSIF0_SR1 (XMC4_IRQ_FIRST+69) /* 69: POSIF Module 0, SR1 */ +#define XMC4_IRQ_POSIF1_SR0 (XMC4_IRQ_FIRST+70) /* 70: POSIF Module 1, SR0 */ +#define XMC4_IRQ_POSIF1_SR1 (XMC4_IRQ_FIRST+71) /* 71: POSIF Module 1, SR1 */ +#define XMC4_IRQ_RESVD072 (XMC4_IRQ_FIRST+72) /* 72: Reserved */ +#define XMC4_IRQ_RESVD073 (XMC4_IRQ_FIRST+73) /* 73: Reserved */ +#define XMC4_IRQ_RESVD074 (XMC4_IRQ_FIRST+74) /* 74: Reserved */ +#define XMC4_IRQ_RESVD075 (XMC4_IRQ_FIRST+75) /* 75: Reserved */ +#define XMC4_IRQ_CAN_SR0 (XMC4_IRQ_FIRST+76) /* 76: MultiCAN, SR0 */ +#define XMC4_IRQ_CAN_SR1 (XMC4_IRQ_FIRST+77) /* 77: MultiCAN, SR1 */ +#define XMC4_IRQ_CAN_SR2 (XMC4_IRQ_FIRST+78) /* 78: MultiCAN, SR2 */ +#define XMC4_IRQ_CAN_SR3 (XMC4_IRQ_FIRST+79) /* 79: MultiCAN, SR3 */ +#define XMC4_IRQ_CAN_SR4 (XMC4_IRQ_FIRST+80) /* 80: MultiCAN, SR4 */ +#define XMC4_IRQ_CAN_SR5 (XMC4_IRQ_FIRST+81) /* 81: MultiCAN, SR5 */ +#define XMC4_IRQ_CAN_SR6 (XMC4_IRQ_FIRST+82) /* 82: MultiCAN, SR6 */ +#define XMC4_IRQ_CAN_SR7 (XMC4_IRQ_FIRST+83) /* 83: MultiCAN, SR7 */ +#define XMC4_IRQ_USIC0_SR0 (XMC4_IRQ_FIRST+84) /* 84: USIC0 Channel, SR0 */ +#define XMC4_IRQ_USIC0_SR1 (XMC4_IRQ_FIRST+85) /* 85: USIC0 Channel, SR1 */ +#define XMC4_IRQ_USIC0_SR2 (XMC4_IRQ_FIRST+86) /* 86: USIC0 Channel, SR2 */ +#define XMC4_IRQ_USIC0_SR3 (XMC4_IRQ_FIRST+87) /* 87: USIC0 Channel, SR3 */ +#define XMC4_IRQ_USIC0_SR4 (XMC4_IRQ_FIRST+88) /* 88: USIC0 Channel, SR4 */ +#define XMC4_IRQ_USIC0_SR5 (XMC4_IRQ_FIRST+89) /* 89: USIC0 Channel, SR5 */ +#define XMC4_IRQ_USIC1_SR0 (XMC4_IRQ_FIRST+90) /* 90: USIC1 Channel, SR0 */ +#define XMC4_IRQ_USIC1_SR1 (XMC4_IRQ_FIRST+91) /* 91: USIC1 Channel, SR1 */ +#define XMC4_IRQ_USIC1_SR2 (XMC4_IRQ_FIRST+92) /* 92: USIC1 Channel, SR2 */ +#define XMC4_IRQ_USIC1_SR3 (XMC4_IRQ_FIRST+93) /* 93: USIC1 Channel, SR3 */ +#define XMC4_IRQ_USIC1_SR4 (XMC4_IRQ_FIRST+94) /* 94: USIC1 Channel, SR4 */ +#define XMC4_IRQ_USIC1_SR5 (XMC4_IRQ_FIRST+95) /* 95: USIC1 Channel, SR5 */ +#define XMC4_IRQ_USIC2_SR0 (XMC4_IRQ_FIRST+96) /* 96: USIC1 Channel, SR0 */ +#define XMC4_IRQ_USIC2_SR1 (XMC4_IRQ_FIRST+97) /* 97: USIC1 Channel, SR1 */ +#define XMC4_IRQ_USIC2_SR2 (XMC4_IRQ_FIRST+98) /* 98: USIC1 Channel, SR2 */ +#define XMC4_IRQ_USIC2_SR3 (XMC4_IRQ_FIRST+99) /* 99: USIC1 Channel, SR3 */ +#define XMC4_IRQ_USIC2_SR4 (XMC4_IRQ_FIRST+100) /* 100: USIC1 Channel, SR4 */ +#define XMC4_IRQ_USIC2_SR5 (XMC4_IRQ_FIRST+101) /* 101: USIC1 Channel, SR5 */ +#define XMC4_IRQ_LEDTS0_SR0 (XMC4_IRQ_FIRST+102) /* 102: LEDTS0, SR0 */ +#define XMC4_IRQ_RESVD103 (XMC4_IRQ_FIRST+103) /* 103: Reserved */ +#define XMC4_IRQ_FCR_SR0 (XMC4_IRQ_FIRST+104) /* 102: FCE, SR0 */ +#define XMC4_IRQ_GPCMA0_SR0 (XMC4_IRQ_FIRST+105) /* 105: GPDMA0, SR0 */ +#define XMC4_IRQ_SDMMC_SR0 (XMC4_IRQ_FIRST+106) /* 106: SDMMC, SR0 */ +#define XMC4_IRQ_USB0_SR0 (XMC4_IRQ_FIRST+107) /* 107: USB, SR0 */ +#define XMC4_IRQ_ETH0_SR0 (XMC4_IRQ_FIRST+108) /* 108: Ethernet, module 0, SR0 */ +#define XMC4_IRQ_RESVD109 (XMC4_IRQ_FIRST+109) /* 109: Reserved */ +#define XMC4_IRQ_GPCMA1_SR0 (XMC4_IRQ_FIRST+110) /* 110: GPDMA1, SR0 */ +#define XMC4_IRQ_RESVD111 (XMC4_IRQ_FIRST+111) /* 111: Reserved */ -#define NR_INTERRUPTS 112 /* 112 Non core IRQs*/ -#define NR_VECTORS (XM4_IRQ_FIRST+NR_INTERRUPTS) /* 118 vectors */ +#define NR_INTERRUPTS 112 /* 112 Non core IRQs*/ +#define NR_VECTORS (XMC4_IRQ_FIRST+NR_INTERRUPTS) /* 118 vectors */ /* GPIO IRQ interrupts -- To be provided */ -#define NR_IRQS NR_VECTORS +#define NR_IRQS NR_VECTORS /***************************************************************************** * Public Types @@ -222,4 +222,4 @@ extern "C" #endif #endif -#endif /* xmc4__ARCH_ARM_INCLUDE_XM4_XM4500_IRQ_H */ +#endif /* xmc4__ARCH_ARM_INCLUDE_XMC4_XM4500_IRQ_H */ diff --git a/arch/arm/src/xmc4/chip/xmc4_scu.h b/arch/arm/src/xmc4/chip/xmc4_scu.h index e08a64a48c0..7e706f501bd 100644 --- a/arch/arm/src/xmc4/chip/xmc4_scu.h +++ b/arch/arm/src/xmc4/chip/xmc4_scu.h @@ -185,9 +185,9 @@ /* Oscillator Control SCU Registers */ -#define XMC4_OCU_OSCHPSTAT_OFFSET 0x0000 /* OSC_HP Status Register */ -#define XMC4_OCU_OSCHPCTRL_OFFSET 0x0004 /* OSC_HP Control Register */ -#define XMC4_OCU_CLKCALCONST_OFFSET 0x000c /* Clock Calibration Constant Register */ +#define XMC4_SCU_OSCHPSTAT_OFFSET 0x0000 /* OSC_HP Status Register */ +#define XMC4_SCU_OSCHPCTRL_OFFSET 0x0004 /* OSC_HP Control Register */ +#define XMC4_SCU_CLKCALCONST_OFFSET 0x000c /* Clock Calibration Constant Register */ /* PLL Control SCU Registers */ @@ -623,8 +623,8 @@ /* System Clock Control */ #define SCU_SYSCLKCR_SYSDIV_SHIFT (0) /* Bits 0-7: System Clock Division Value */ -#define SCU_SYSCLKCR_SYSDIV_MASK (0xff << SCU_CLK_SYSCLKCR_SYSDIV_SHIFT) -# define SCU_SYSCLKCR_SYSDIV(n) ((uint32_t)((n)-1) << SCU_CLK_SYSCLKCR_SYSDIV_SHIFT) +#define SCU_SYSCLKCR_SYSDIV_MASK (0xff << SCU_SYSCLKCR_SYSDIV_SHIFT) +# define SCU_SYSCLKCR_SYSDIV(n) ((uint32_t)((n)-1) << SCU_SYSCLKCR_SYSDIV_SHIFT) #define SCU_SYSCLKCR_SYSSEL (1 << 16) /* Bit 16: System Clock Selection Value */ # define SCU_SYSCLKCR_SYSSEL_OFI (0) /* 0=OFI clock */ @@ -640,8 +640,8 @@ /* USB Clock Control */ #define SCU_USBCLKCR_USBDIV_SHIFT (0) /* Bits 0-2: USB Clock Divider Value */ -#define SCU_USBCLKCR_USBDIV_MASK (7 << SCU_CLK_USBCLKCR_USBDIV_SHIFT) -# define SCU_SYSCLKCR_USBDIV(n) ((uint32_t)((n)-1) << SCU_CLK_USBCLKCR_USBDIV_SHIFT) +#define SCU_USBCLKCR_USBDIV_MASK (7 << SCU_USBCLKCR_USBDIV_SHIFT) +# define SCU_SYSCLKCR_USBDIV(n) ((uint32_t)((n)-1) << SCU_USBCLKCR_USBDIV_SHIFT) #define SCU_USBCLKCR_USBSEL (1 << 16) /* Bit 16: USB Clock Selection Value */ # define SCU_USBCLKCR_USBSEL_USBPLL (0) /* 0=USB PLL Clock */ # define SCU_USBCLKCR_USBSEL_PLL (1 << 16) /* 1= PLL Clock */ diff --git a/arch/arm/src/xmc4/xmc4_clockconfig.c b/arch/arm/src/xmc4/xmc4_clockconfig.c index 6667ceca861..26608a85b84 100644 --- a/arch/arm/src/xmc4/xmc4_clockconfig.c +++ b/arch/arm/src/xmc4/xmc4_clockconfig.c @@ -57,6 +57,7 @@ #include "up_arch.h" #include "chip/xmc4_scu.h" +#include "xmc4_clockconfig.h" #include @@ -83,7 +84,7 @@ #define SCU_PLLSTAT_OSC_USABLE \ (SCU_PLLSTAT_PLLHV | SCU_PLLSTAT_PLLLV | SCU_PLLSTAT_PLLSP) -#ifndef BOARD_PLL_CLOCKSRC_XTAL +#ifdef BOARD_PLL_CLOCKSRC_XTAL # define VCO ((BOARD_XTAL_FREQUENCY / BOARD_PLL_PDIV) * BOARD_PLL_NDIV) #else /* BOARD_PLL_CLOCKSRC_XTAL */ @@ -171,7 +172,7 @@ void xmc4_clock_configure(void) regval = getreg32(XMC4_SCU_PLLCON0); regval |= SCU_PLLCON0_FOTR; - putreg(regval, XMC4_SCU_PLLCON0); + putreg32(regval, XMC4_SCU_PLLCON0); #else /* Automatic calibration uses the fSTDBY */ @@ -195,10 +196,9 @@ void xmc4_clock_configure(void) /* Remove the reset only if HIB domain were in a state of reset */ regval = getreg32(XMC4_SCU_RSTSTAT); - if ((regval & SCU_RSTSTAT_HIBRS) ! = 0) + if ((regval & SCU_RSTSTAT_HIBRS) != 0) { - regval = getreg32(XMC4_SCU_RSTSTAT); - SCU_RESET->RSTCLR |= SCU_RESET_RSTCLR_HIBRS_Msk; + regval = putreg32(SCU_RSTCLR_HIBRS, XMC4_SCU_RSTCLR); delay(DELAY_CNT_150US_50MHZ); } @@ -271,19 +271,19 @@ void xmc4_clock_configure(void) regval = getreg32(XMC4_SCU_PLLCON0); regval |= SCU_PLLCON0_AOTREN; - putreg(regval, XMC4_SCU_PLLCON0); + putreg32(regval, XMC4_SCU_PLLCON0); #endif /* BOARD_FOFI_CALIBRATION */ delay(DELAY_CNT_50US_50MHZ); -#if BOARD_ENABLE_PLL +#ifdef BOARD_ENABLE_PLL /* Enable PLL */ regval = getreg32(XMC4_SCU_PLLCON0); regval &= ~(SCU_PLLCON0_VCOPWD | SCU_PLLCON0_PLLPWD); - putreg(regval, XMC4_SCU_PLLCON0); + putreg32(regval, XMC4_SCU_PLLCON0); #ifdef BOARD_PLL_CLOCKSRC_XTAL /* Enable OSC_HP */ @@ -292,7 +292,7 @@ void xmc4_clock_configure(void) { regval = getreg32(XMC4_SCU_OSCHPCTRL); regval &= ~(SCU_OSCHPCTRL_MODE_MASK | SCU_OSCHPCTRL_OSCVAL_MASK); - regval |= ((OSCHP_GetFrequency() / FOSCREF) - 1) << SCU_OSCHPCTRL_OSCVAL_SHIFT; + regval |= ((BOARD_XTAL_FREQUENCY / FOSCREF) - 1) << SCU_OSCHPCTRL_OSCVAL_SHIFT; putreg32(regval, XMC4_SCU_OSCHPCTRL); /* Select OSC_HP clock as PLL input */ @@ -305,7 +305,7 @@ void xmc4_clock_configure(void) regval = getreg32(XMC4_SCU_PLLCON0); regval &= ~SCU_PLLCON0_OSCRES; - putreg(regval, XMC4_SCU_PLLCON0); + putreg32(regval, XMC4_SCU_PLLCON0); /* Wait till OSC_HP output frequency is usable */ @@ -330,36 +330,36 @@ void xmc4_clock_configure(void) regval = getreg32(XMC4_SCU_PLLCON0); regval |= SCU_PLLCON0_VCOBYP; - putreg(regval, XMC4_SCU_PLLCON0); + putreg32(regval, XMC4_SCU_PLLCON0); /* Disconnect Oscillator from PLL */ regval |= SCU_PLLCON0_FINDIS; - putreg(regval, XMC4_SCU_PLLCON0); + putreg32(regval, XMC4_SCU_PLLCON0); /* Setup divider settings for main PLL */ regval = (SCU_PLLCON1_NDIV(BOARD_PLL_NDIV) | SCU_PLLCON1_K2DIV(PLL_K2DIV_24MHZ) | - SCU_PLLCON1_PDIV(BOARD_PLL_PDIV); + SCU_PLLCON1_PDIV(BOARD_PLL_PDIV)); putreg32(regval, XMC4_SCU_PLLCON1); /* Set OSCDISCDIS */ regval = getreg32(XMC4_SCU_PLLCON0); regval |= SCU_PLLCON0_OSCDISCDIS; - putreg(regval, XMC4_SCU_PLLCON0); + putreg32(regval, XMC4_SCU_PLLCON0); /* Connect Oscillator to PLL */ regval = getreg32(XMC4_SCU_PLLCON0); regval &= ~SCU_PLLCON0_FINDIS; - putreg(regval, XMC4_SCU_PLLCON0); + putreg32(regval, XMC4_SCU_PLLCON0); /* Restart PLL Lock detection */ regval |= SCU_PLLCON0_RESLD; - putreg(regval, XMC4_SCU_PLLCON0); + putreg32(regval, XMC4_SCU_PLLCON0); /* wait for PLL Lock at 24MHz*/ @@ -371,7 +371,7 @@ void xmc4_clock_configure(void) regval = getreg32(XMC4_SCU_PLLCON0); regval &= ~SCU_PLLCON0_VCOBYP; - putreg(regval, XMC4_SCU_PLLCON0); + putreg32(regval, XMC4_SCU_PLLCON0); /* Wait for normal mode */ @@ -393,7 +393,7 @@ void xmc4_clock_configure(void) putreg32(WDTCLKCR_VALUE, XMC4_SCU_WDTCLKCR); putreg32(EBUCLKCR_VALUE, XMC4_SCU_EBUCLKCR); putreg32(USBCLKCR_VALUE | USB_DIV, XMC4_SCU_USBCLKCR); - putreg32(EXTCLKCR_VALUE, EXTCLKCR); + putreg32(EXTCLKCR_VALUE, XMC4_SCU_EXTCLKCR); #if BOARD_ENABLE_PLL /* PLL frequency stepping...*/ @@ -401,7 +401,7 @@ void xmc4_clock_configure(void) regval = getreg32(XMC4_SCU_PLLCON0); regval &= ~SCU_PLLCON0_OSCDISCDIS; - putreg(regval, XMC4_SCU_PLLCON0); + putreg32(regval, XMC4_SCU_PLLCON0); regval = (SCU_PLLCON1_NDIV(BOARD_PLL_NDIV) | SCU_PLLCON1_K2DIV(PLL_K2DIV_48MHZ) | @@ -440,7 +440,7 @@ void xmc4_clock_configure(void) #endif /* BOARD_ENABLE_PLL */ -#if BOARD_ENABLE_USBPLL +#ifdef BOARD_ENABLE_USBPLL /* Enable USB PLL first */ regval = getreg32(XMC4_SCU_USBPLLCON); @@ -461,19 +461,19 @@ void xmc4_clock_configure(void) regval = getreg32(XMC4_SCU_PLLCON0); regval &= ~(SCU_PLLCON0_VCOPWD | SCU_PLLCON0_PLLPWD); - putreg(regval, XMC4_SCU_PLLCON0); + putreg32(regval, XMC4_SCU_PLLCON0); } regval = getreg32(XMC4_SCU_OSCHPCTRL); regval &= ~(SCU_OSCHPCTRL_MODE_MASK | SCU_OSCHPCTRL_OSCVAL_MASK); - regval |= ((OSCHP_GetFrequency() / FOSCREF) - 1) << SCU_OSCHPCTRL_OSCVAL_SHIFT; + regval |= ((BOARD_XTAL_FREQUENCY / FOSCREF) - 1) << SCU_OSCHPCTRL_OSCVAL_SHIFT; putreg32(regval, XMC4_SCU_OSCHPCTRL); /* Restart OSC Watchdog */ regval = getreg32(XMC4_SCU_PLLCON0); regval &= ~SCU_PLLCON0_OSCRES; - putreg(regval, XMC4_SCU_PLLCON0); + putreg32(regval, XMC4_SCU_PLLCON0); /* Wait till OSC_HP output frequency is usable */ @@ -527,7 +527,7 @@ void xmc4_clock_configure(void) /* Enable selected clocks */ - putreg32(CLKSET_VALUE, XMC4_SCU_CLKSET) + putreg32(CLKSET_VALUE, XMC4_SCU_CLKSET); } /**************************************************************************** @@ -605,7 +605,7 @@ uint32_t xmc4_get_coreclock(void) /* Check if the fSYS clock is divided by two to produce fCPU clock. */ - regval = getreg32(CPUCLKCR); + regval = getreg32(XMC4_SCU_CPUCLKCR); if ((regval & SCU_CPUCLKCR_CPUDIV) != 0) { temp = temp >> 1; diff --git a/arch/arm/src/xmc4/xmc4_irq.c b/arch/arm/src/xmc4/xmc4_irq.c index 17725b8c608..c31482b6385 100644 --- a/arch/arm/src/xmc4/xmc4_irq.c +++ b/arch/arm/src/xmc4/xmc4_irq.c @@ -45,6 +45,7 @@ #include #include #include +#include #include "nvic.h" #include "ram_vectors.h" diff --git a/configs/xmc4500-relax/include/board.h b/configs/xmc4500-relax/include/board.h index f3616a21e2c..dbc2440902d 100644 --- a/configs/xmc4500-relax/include/board.h +++ b/configs/xmc4500-relax/include/board.h @@ -130,6 +130,68 @@ #define BOARD_FLASH_WS 5 +/* LED definitions ******************************************************************/ +/* The XMC4500 Relax Lite v1 board has two LEDs: + * + * LED1 P1.1 High output illuminates + * LED2 P1.0 High output illuminates + * + * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in any + * way. The following definitions are used to access individual LEDs. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED0 0 +#define BOARD_LED1 1 +#define BOARD_NLEDS 2 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED0_BIT (1 << BOARD_LED0) +#define BOARD_LED1_BIT (1 << BOARD_LED1) + +/* These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is + * defined. In that case, the usage by the board port is defined in + * include/board.h and src/sam_autoleds.c. The LEDs are used to encode + * OS-related events as follows: + * + * SYMBOL Meaning LED state + * LED2 LED1 + * --------------------- -------------------------- ------ ------ */ + +#define LED_STARTED 0 /* NuttX has been started OFF OFF */ +#define LED_HEAPALLOCATE 0 /* Heap has been allocated OFF OFF */ +#define LED_IRQSENABLED 0 /* Interrupts enabled OFF OFF */ +#define LED_STACKCREATED 1 /* Idle stack created ON OFF */ +#define LED_INIRQ 2 /* In an interrupt No change */ +#define LED_SIGNAL 2 /* In a signal handler No change */ +#define LED_ASSERTION 2 /* An assertion failed No change */ +#define LED_PANIC 3 /* The system has crashed N/C Blinking */ +#undef LED_IDLE /* MCU is is sleep mode Not used */ + +/* Thus if LED0 is statically on, NuttX has successfully booted and is, + * apparently, running normally. If LED1 is flashing at approximately + * 2Hz, then a fatal error has been detected and the system has halted. + * + * NOTE: That LED0 is not used after completion of booting and may + * be used by other board-specific logic. + */ + +/* Button definitions ***************************************************************/ +/* The XMC4500 Relax Lite v1 board has two buttons: + * + * BUTTON1 P1.14 Low input sensed when button pressed + * BUTTON2 P1.15 Low input sensed when button pressed + */ + +#define BUTTON_0 0 +#define BUTTON_1 1 +#define NUM_BUTTONS 2 + +#define BUTTON_0_BIT (1 << BUTTON_0) +#define BUTTON_1_BIT (1 << BUTTON_1) + /************************************************************************************ * Public Data ************************************************************************************/ diff --git a/configs/xmc4500-relax/src/xmc4500-relax.h b/configs/xmc4500-relax/src/xmc4500-relax.h index 6a004c82448..7934462b70e 100644 --- a/configs/xmc4500-relax/src/xmc4500-relax.h +++ b/configs/xmc4500-relax/src/xmc4500-relax.h @@ -46,9 +46,21 @@ * Pre-processor Definitions ****************************************************************************/ -/* LEDs */ +/* LEDs + * + * The XMC4500 Relax Lite v1 board has two LEDs: + * + * LED1 P1.1 High output illuminates + * LED2 P1.0 High output illuminates + */ -/* BUTTONS */ +/* BUTTONS + * + * The XMC4500 Relax Lite v1 board has two buttons: + * + * BUTTON1 P1.14 Low input sensed when button pressed + * BUTTON2 P1.15 Low input sensed when button pressed + */ /**************************************************************************** * Public Types