add phyplus_rel_1.4

update source for phyplus driver rel_1.4

update source  for phyplus driver rel 1.4

update source for phyplus driver 1.4

update phy6222 config files

arch/arm/Kconfig

@@ -483,6 +483,7 @@ config ARCH_CHIP_CXD56XX
 config ARCH_CHIP_PHY62XX
 	bool "Phyplus PHY62XX BLE"
 	select ARCH_CORTEXM0
+	select LIBC_ARCH_ATOMIC
 	---help---
 		Phyplus PHY62XX architectures (ARM Cortex-M0).
 

arch/arm/src/phy62xx/Make.defs

@@ -35,6 +35,10 @@ CMN_CSRCS += phy62xx_hardfault.c arm_svcall.c arm_vectors.c arm_vfork.c
 #CMN_CSRCS += arm_etherstub.c
 CMN_CSRCS += arm_switchcontext.c arm_tcbinfo.c
 
+ifeq ($(CONFIG_ARCH_HAVE_BACKTRACE),y)
+CMN_CSRCS += arm_backtrace_thumb.c
+endif
+
 ifeq ($(CONFIG_BUILD_PROTECTED),y)
 CMN_CSRCS += arm_task_start.c arm_pthread_start.c
 CMN_CSRCS += arm_pthread_exit.c
@@ -50,7 +54,8 @@ ifeq ($(CONFIG_DEBUG_FEATURES),y)
 CMN_CSRCS += arm_dumpnvic.c
 endif
 
-CHIP_CSRCS  = start.c gpio.c irq.c timer.c clock.c uart.c pwrmgr.c idle.c my_printf.c flash.c
+CHIP_CSRCS  = start.c gpio.c irq.c timer.c uart.c pwrmgr.c idle.c my_printf.c
+#CHIP_CSRCS  = start.c gpio.c irq.c timer.c clock.c uart.c pwrmgr.c idle.c my_printf.c flash.c
 CHIP_CSRCS += jump_table.c
 CHIP_CSRCS += pplus_mtd_flash.c
 ifeq ($(CONFIG_PHY6222_BLE),y)
@@ -70,6 +75,10 @@ ifeq ($(CONFIG_DEV_GPIO),y)
 CHIP_CSRCS += phyplus_gpio.c
 endif
 
+#ifeq ($(CONFIG_WATCHDOG),y)
+CHIP_CSRCS += phyplus_wdt.c
+#endif
+
 ifeq ($(CONFIG_PHYPLUS_STUB),y)
 CHIP_CSRCS += phyplus_stub.c
 endif
@@ -96,13 +105,9 @@ CFLAGS += -DHUGE_MODE=0
 CFLAGS += -DMAX_NUM_LL_CONN=1
 CFLAGS += -DUSE_ROMSYM_ALIAS
 #CFLAGS += -Wimplicit-function-declaration
-#CFLAGS += -Wunused-but-set-variable
+CFLAGS += -Wno-unused-but-set-variable
 CFLAGS += -DEXTERN_BLE_FUNC=0
 LDFLAGS += "$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)bb_rom_sym_m0.gdbsym"
-#CFLAGS += -Wstrict-prototypes
-#LDFLAGS += "$(ARCH_SRCDIR)$(DELIM)board$(DELIM)bb_rom_sym_m0.gdbsym"
-#LDFLAGS += -Wl,-Map="../../../phyplus_build.map"		# param error
-#LDFLAGS += -Wl,--gc-sections					# param error
 
 .buildlib:
 	$(Q) if [ -d ../../../../phy62xxble ]; then \
@@ -112,6 +117,7 @@ LDFLAGS += "$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)bb_rom_sym_m0.gdbsym"
 		if [ ! -f libphy62xxble.a ]; then \
 			echo "############download lib form server############"; \
 			curl -L -o libphy62xxble.a http://www.phyplusinc.com/phyplus/libphy62xxble.a; \
+			mkdir -p ../../../staging; \
 			cp -a libphy62xxble.a ../../../staging; \
 		 else \
 			echo "############file exist############"; \
@@ -120,4 +126,34 @@ LDFLAGS += "$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)bb_rom_sym_m0.gdbsym"
 
 context:: .buildlib
 
+LDFLAGS += -Map="../../../phyplus_build.map"
+
+ifndef CONFIG_PHY6222_SDK
+EXTRA_LIBPATHS += -L$(TOPDIR)/arch/arm/src/chip
 EXTRA_LIBS += -lphy62xxble
+CHIP_CSRCS += flash.c
+CHIP_CSRCS += clock.c 
+else
+EXTRA_LIBPATHS += -L$(TOPDIR)/../apps/phy6222/bbb_sdk/lib
+EXTRA_LIBS += -lphy6222_rf
+EXTRA_LIBS += -lphy6222_sec_boot
+EXTRA_LIBS += -lphy6222_host
+endif
+
+ifdef CONFIG_PHY6222_PHY_MESH
+EXTRA_LIBPATHS += -L$(TOPDIR)/../apps/phy6222/bbb_sdk/components/ethermind/lib/meshlibs/phyos/armgcc/
+EXTRA_LIBS += -lethermind_mesh_core
+EXTRA_LIBS += -lethermind_mesh_models
+EXTRA_LIBS += -lethermind_utils
+#LDLIBPATH += $(APPDIR)/phy6222/bbb_sdk/components/ethermind/lib/meshlibs/phyos/armgcc/
+#LDLIBS += -lethermind_mesh_core
+#LDLIBS += -lethermind_mesh_models
+#LDLIBS += -lethermind_utils
+endif
+
+ifdef CONFIG_MIJIA_APIS
+EXTRA_LIBPATHS += -L$(TOPDIR)/../apps/phy6222/bbb_sdk/components/xiaomi/libs/mesh_auth/debug/
+EXTRA_LIBS += -lmesh-auth-cortex-m0plus-debug
+endif
+
+

arch/arm/src/phy62xx/bb_rom_sym_m0.gdbsym

@@ -1,3 +1,9 @@
+P256_ecdh_keygen = 0x00000d03;
+P256_ecdh_shared_secret = 0x00000d0b;
+_symrom_move_to_slave_function0 = 0x00014085;
+_symrom_ll_scheduler0 = 0x00013789;
+_symrom_llSetupNextSlaveEvent0 = 0x0000edf9;
+_symrom_LL_set_default_conn_params0 = 0x0000828d;
 _symrom_bx_to_application = 0x000000d5;
 _symrom_memset = 0x00000eb7;
 _symrom_strlen = 0x00000ec9;
@@ -353,6 +359,7 @@ _symrom_LL_slave_conn_event = 0x000082b9;
 _symrom_NMI_Handler = 0x00008481;
 _symrom_PendSV_Handler = 0x000084cd;
 _symrom_TIM1_IRQHandler = 0x00008545;
+_symrom_TIM2_IRQHandler = 0x00008569;
 _symrom_WaitRTCCount = 0x00008901;
 _symrom___ARM_common_switch8 = 0x00008961;
 _symrom__spif_read_status_reg = 0x0000961d;

arch/arm/src/phy62xx/clock.h

@@ -50,7 +50,7 @@ typedef enum
 typedef enum  _SYSCLK_SEL
 {
     SYS_CLK_RC_32M      = 0,
-    SYS_CLK_DLL_32M     = 1,
+    SYS_CLK_DBL_32M     = 1,
     SYS_CLK_XTAL_16M    = 2,
     SYS_CLK_DLL_48M     = 3,
     SYS_CLK_DLL_64M     = 4,

arch/arm/src/phy62xx/flash.c

@@ -234,7 +234,7 @@ static void __RAMRUN hw_spif_cache_config(void)
   hal_cache_init();
 }
 
-int __RAMRUN hal_spif_cache_init(void) /* xflash_Ctx_t cfg) */
+int __RAMRUN hal_spif_cache_init(xflash_Ctx_t cfg)
 {
   /* memset(&(s_xflashCtx), 0, sizeof(s_xflashCtx)); */
 
@@ -251,6 +251,7 @@ int __RAMRUN hal_flash_read(uint32_t addr, uint8_t *data, uint32_t size)
                 ((addr & 0x7ffff) | FLASH_BASE_ADDR);
 
   /* uint32_t cb = AP_PCR->CACHE_BYPASS; */
+
   #if(SPIF_FLASH_SIZE == FLASH_SIZE_1MB)
   uint32_t remap = addr & 0xf80000;
 

arch/arm/src/phy62xx/flash.h

@@ -135,7 +135,7 @@ extern void spif_cmd(uint8_t op, uint8_t addrlen,
 extern void spif_rddata(uint8_t *data, uint8_t len);
 extern int spif_config(sysclk_t ref_clk, uint8_t div,
     uint32_t rd_instr, uint8_t mode_bit, uint8_t QE);
-int hal_spif_cache_init(void);  /* xflash_Ctx_t cfg); */
+int hal_spif_cache_init(xflash_Ctx_t cfg);
 
 int hal_flash_write(uint32_t addr, uint8_t *data, uint32_t size);
 int hal_flash_write_by_dma(uint32_t addr, uint8_t *data, uint32_t size);

arch/arm/src/phy62xx/irq.c

@@ -207,8 +207,17 @@ int irq_priority(int irqid, uint8_t priority)
 
 void LL_IRQHandler1(void);
 void TIM1_IRQHandler1(void);
+
+#ifdef CONFIG_PHY6222_SDK
+void TIM2_IRQHandler1(void);
+#endif
+
 void TIM3_IRQHandler1(void);
 
+#ifdef CONFIG_PHY6222_SDK
+void TIM5_IRQHandler1(void);
+#endif
+
 void up_irqinitialize(void)
 {
   uint32_t regaddr;
@@ -311,24 +320,40 @@ void up_irqinitialize(void)
 
   irq_attach(PHY62XX_IRQ_BB_IRQn, (xcpt_t)LL_IRQHandler1, NULL);
   irq_attach(PHY62XX_IRQ_TIM1_IRQn, (xcpt_t)TIM1_IRQHandler1, NULL);
+
+#ifdef CONFIG_PHY6222_SDK
+  irq_attach(PHY62XX_IRQ_TIM2_IRQn, (xcpt_t)TIM2_IRQHandler1, NULL);
+#endif
+
   irq_attach(PHY62XX_IRQ_TIM3_IRQn, (xcpt_t)TIM3_IRQHandler1, NULL);
+
+#ifdef CONFIG_PHY6222_SDK
+  irq_attach(PHY62XX_IRQ_TIM5_IRQn, (xcpt_t)TIM5_IRQHandler1, NULL);
+#endif
+
   irq_priority((IRQn_Type)BB_IRQn,    IRQ_PRIO_REALTIME);
   irq_priority((IRQn_Type)TIM1_IRQn,  IRQ_PRIO_HIGH);     /* ll_EVT */
+
+#ifdef CONFIG_PHY6222_SDK
   irq_priority((IRQn_Type)TIM2_IRQn,  IRQ_PRIO_HIGH);     /* OSAL_TICK */
+#endif
+
   irq_priority((IRQn_Type)TIM3_IRQn,  IRQ_PRIO_APP);      /* OSAL_TICK */
   irq_priority((IRQn_Type)TIM4_IRQn,  IRQ_PRIO_HIGH);     /* LL_EXA_ADV */
   NVIC_EnableIRQ((IRQn_Type)BB_IRQn);
   NVIC_EnableIRQ((IRQn_Type)TIM1_IRQn);                   /* ll_EVT */
 
-  /* NVIC_EnableIRQ((IRQn_Type)TIM2_IRQn); */
+#ifdef CONFIG_PHY6222_SDK
-
+  NVIC_EnableIRQ((IRQn_Type)TIM2_IRQn);
-                                                          /* OSAL_TICK */
+#endif
 
   NVIC_EnableIRQ((IRQn_Type)TIM3_IRQn);
 
-  /* NVIC_EnableIRQ((IRQn_Type)TIM4_IRQn); */
+#ifdef CONFIG_PHY6222_SDK
+  NVIC_EnableIRQ((IRQn_Type)TIM5_IRQn);
+#endif
 
-                                                          /* LL_EXA_ADV */
+  /* NVIC_EnableIRQ((IRQn_Type)TIM4_IRQn); */
 
   /* svc(SVC_CALL_WR); */
 

arch/arm/src/phy62xx/mcu_phy_bumbee.h

@@ -31,7 +31,7 @@ extern "C"
  ****************************************************************************/
 
 #include "types.h"
-
+#include "bus_dev.h"
 typedef enum
 {
     MOD_NONE        = 0, MOD_CK802_CPU   = 0,

arch/arm/src/phy62xx/phy62xx_ble.c

@@ -299,11 +299,13 @@ static int pplus_ble_open(struct bt_driver_s *drv)
 extern uint8_t hciCtrlCmdToken;
 int drv_disable_irq1(void)
 {
+  NVIC_DisableIRQs(BIT(TIM1_IRQn) | BIT(TIM2_IRQn) | BIT(BB_IRQn));
   return 0;
 }
 
 int drv_enable_irq1(void)
 {
+  NVIC_EnableIRQs(BIT(TIM1_IRQn) | BIT(TIM2_IRQn) | BIT(BB_IRQn));
   return 0;
 }
 

arch/arm/src/phy62xx/phy62xx_exception.S

@@ -47,8 +47,9 @@ exception_common:
 
 	/* Complete the context save */
 
+	pop     {r4}
 	mrs		r1, msp
-	add		r1, #8
+	add		r1, #4
 	msr		msp, r1
 	/* Get the current stack pointer.  The EXC_RETURN value tells us whether
 	 * the context is on the MSP or PSP.
@@ -347,5 +348,15 @@ exception_common_inline:
  *
  ****************************************************************************/
 
+#if CONFIG_ARCH_INTERRUPTSTACK > 3
+	.bss
+	.global	g_intstackalloc
+	.global	g_intstacktop
+	.balign	4
+g_intstackalloc:
+	.skip	(CONFIG_ARCH_INTERRUPTSTACK & ~3)
+g_intstacktop:
+	.size	g_intstackalloc, .-g_intstackalloc
+#endif
 
 	.end

arch/arm/src/phy62xx/phyplus_tim.c

@@ -51,32 +51,6 @@ struct phyplus_tim_priv_s
  * Private Function prototypes
  ****************************************************************************/
 
-void phyplus_tim_start(FAR struct phyplus_tim_dev_s *dev);
-void phyplus_tim_stop(FAR struct phyplus_tim_dev_s *dev);
-
-void phyplus_tim_clear(FAR struct phyplus_tim_dev_s *dev);
-void phyplus_tim_setmode(FAR struct phyplus_tim_dev_s *dev, uint8_t mode);
-
-void phyplus_tim_getcounter(FAR struct phyplus_tim_dev_s *dev,
-    uint32_t *value);
-
-void phyplus_tim_setcounter(FAR struct phyplus_tim_dev_s *dev,
-    uint32_t value);
-
-int phyplus_tim_setisr(FAR struct phyplus_tim_dev_s *dev, xcpt_t handler,
-    void *arg);
-
-void phyplus_tim_enableint(FAR struct phyplus_tim_dev_s *dev);
-void phyplus_tim_disableint(FAR struct phyplus_tim_dev_s *dev);
-
-void phyplus_tim_ackint(FAR struct phyplus_tim_dev_s *dev);
-
-void phyplus_tim_getcurrent(FAR struct phyplus_tim_dev_s *dev,
-    uint32_t *value);
-
-void phyplus_tim_getcontrolreg(FAR struct phyplus_tim_dev_s *dev,
-    uint32_t *value);
-
 /* static int  phyplus_tim_checkint(FAR struct phyplus_tim_dev_s *dev,
  *     int source);
  */
@@ -108,7 +82,7 @@ struct phyplus_tim_ops_s phyplus_tim_ops =
 struct phyplus_tim_priv_s phyplus_tim1_priv =
 {
   .ops                 = &phyplus_tim_ops,
-  .base                = AP_TIM1,
+  .base                =  (long unsigned int)AP_TIM1,
   .inuse               = false,
 };
 
@@ -119,7 +93,7 @@ struct phyplus_tim_priv_s phyplus_tim1_priv =
 struct phyplus_tim_priv_s phyplus_tim2_priv =
 {
   .ops                 = &phyplus_tim_ops,
-  .base                = AP_TIM2,
+  .base                =  (long unsigned int)AP_TIM2,
   .inuse               = false,
 };
 
@@ -130,7 +104,7 @@ struct phyplus_tim_priv_s phyplus_tim2_priv =
 struct phyplus_tim_priv_s phyplus_tim3_priv =
 {
   .ops                 = &phyplus_tim_ops,
-  .base                = AP_TIM3,
+  .base                =  (long unsigned int)AP_TIM3,
   .inuse               = false,
 };
 
@@ -141,7 +115,7 @@ struct phyplus_tim_priv_s phyplus_tim3_priv =
 struct phyplus_tim_priv_s phyplus_tim4_priv =
 {
   .ops                 = &phyplus_tim_ops,
-  .base                = AP_TIM4,
+  .base                =  (long unsigned int)AP_TIM4,
   .inuse               = false,
 };
 
@@ -152,7 +126,7 @@ struct phyplus_tim_priv_s phyplus_tim4_priv =
 struct phyplus_tim_priv_s phyplus_tim5_priv =
 {
   .ops                 = &phyplus_tim_ops,
-  .base                = AP_TIM5,
+  .base                =  (long unsigned int)AP_TIM5,
   .inuse               = false,
 };
 
@@ -163,7 +137,7 @@ struct phyplus_tim_priv_s phyplus_tim5_priv =
 struct phyplus_tim_priv_s phyplus_tim6_priv =
 {
   .ops                 = &phyplus_tim_ops,
-  .base                = AP_TIM6,
+  .base                =  (long unsigned int)AP_TIM6,
   .inuse               = false,
 };
 
@@ -279,7 +253,8 @@ void phyplus_tim_clear(FAR struct phyplus_tim_dev_s *dev)
  *
  ****************************************************************************/
 
-void phyplus_tim_setmode(FAR struct phyplus_tim_dev_s *dev, uint8_t mode)
+void phyplus_tim_setmode(FAR struct phyplus_tim_dev_s *dev,
+    phyplus_tim_mode_t mode)
 {
   DEBUGASSERT(dev);
 
@@ -357,34 +332,38 @@ int phyplus_tim_setisr(FAR struct phyplus_tim_dev_s *dev, xcpt_t handler,
     void *arg)
 {
   FAR struct phyplus_tim_priv_s *tim = NULL;
-  int ret = OK;
   int vectorno;
 
   DEBUGASSERT(dev);
 
   tim = (FAR struct phyplus_tim_priv_s *)dev;
 
-  if (AP_TIM1 == ((struct phyplus_tim_priv_s *)dev)->base)
+  if ((long unsigned int)AP_TIM1 == ((struct phyplus_tim_priv_s *)dev)->base)
     {
       vectorno = PHY62XX_IRQ_TIM1_IRQn;
     }
-  else if (AP_TIM2 == ((struct phyplus_tim_priv_s *)dev)->base)
+  else if ((long unsigned int)AP_TIM2 ==
+    ((struct phyplus_tim_priv_s *)dev)->base)
     {
       vectorno = PHY62XX_IRQ_TIM2_IRQn;
     }
-  else if (AP_TIM3 == ((struct phyplus_tim_priv_s *)dev)->base)
+  else if ((long unsigned int)AP_TIM3 ==
+    ((struct phyplus_tim_priv_s *)dev)->base)
     {
       vectorno = PHY62XX_IRQ_TIM3_IRQn;
     }
-  else if (AP_TIM4 == ((struct phyplus_tim_priv_s *)dev)->base)
+  else if ((long unsigned int)AP_TIM4 ==
+    ((struct phyplus_tim_priv_s *)dev)->base)
     {
       vectorno = PHY62XX_IRQ_TIM4_IRQn;
     }
-  else if (AP_TIM5 == ((struct phyplus_tim_priv_s *)dev)->base)
+  else if ((long unsigned int)AP_TIM5 ==
+    ((struct phyplus_tim_priv_s *)dev)->base)
     {
       vectorno = PHY62XX_IRQ_TIM5_IRQn;
     }
-  else if (AP_TIM6 == ((struct phyplus_tim_priv_s *)dev)->base)
+  else if ((long unsigned int)AP_TIM6 ==
+    ((struct phyplus_tim_priv_s *)dev)->base)
     {
       vectorno = PHY62XX_IRQ_TIM6_IRQn;
     }

arch/arm/src/phy62xx/phyplus_tim.h

@@ -100,9 +100,10 @@ struct phyplus_tim_ops_s
   void (*start)(FAR struct phyplus_tim_dev_s *dev);
   void (*stop)(FAR struct phyplus_tim_dev_s *dev);
   void (*clear)(FAR struct phyplus_tim_dev_s *dev);
-  int (*setmode)(FAR struct phyplus_tim_dev_s *dev, phyplus_tim_mode_t mode);
+  void (*setmode)(FAR struct phyplus_tim_dev_s *dev,
+      phyplus_tim_mode_t mode);
   void (*getcounter)(FAR struct phyplus_tim_dev_s *dev, uint32_t *value);
-  void (*setcounter)(FAR struct phyplus_tim_dev_s *dev, uint32_t *value);
+  void (*setcounter)(FAR struct phyplus_tim_dev_s *dev, uint32_t value);
   int (*setisr)(FAR struct phyplus_tim_dev_s *dev, xcpt_t handler,
       void *arg);
   void (*enableint)(FAR struct phyplus_tim_dev_s *dev);
@@ -117,6 +118,33 @@ struct phyplus_tim_ops_s
 FAR struct phyplus_tim_dev_s *phyplus_tim_init(int timer);
 void phyplus_tim_deinit(FAR struct phyplus_tim_dev_s *dev);
 
+void phyplus_tim_start(FAR struct phyplus_tim_dev_s *dev);
+void phyplus_tim_stop(FAR struct phyplus_tim_dev_s *dev);
+
+void phyplus_tim_clear(FAR struct phyplus_tim_dev_s *dev);
+void phyplus_tim_setmode(FAR struct phyplus_tim_dev_s *dev,
+    phyplus_tim_mode_t mode);
+
+void phyplus_tim_enableint(FAR struct phyplus_tim_dev_s *dev);
+void phyplus_tim_disableint(FAR struct phyplus_tim_dev_s *dev);
+
+void phyplus_tim_getcounter(FAR struct phyplus_tim_dev_s *dev,
+    uint32_t *value);
+
+void phyplus_tim_setcounter(FAR struct phyplus_tim_dev_s *dev,
+    uint32_t value);
+
+void phyplus_tim_getcurrent(FAR struct phyplus_tim_dev_s *dev,
+    uint32_t *value);
+
+void phyplus_tim_getcontrolreg(FAR struct phyplus_tim_dev_s *dev,
+    uint32_t *value);
+
+int phyplus_tim_setisr(FAR struct phyplus_tim_dev_s *dev, xcpt_t handler,
+    void *arg);
+
+void phyplus_tim_ackint(FAR struct phyplus_tim_dev_s *dev);
+
 #undef EXTERN
 #if defined(__cplusplus)
 }

arch/arm/src/phy62xx/phyplus_timer_lowerhalf.c

@@ -42,7 +42,7 @@
 #include <nuttx/config.h>
 
 #include <sys/types.h>
-
+#include <stdio.h>
 #include <stdint.h>
 #include <string.h>
 #include <errno.h>
@@ -72,7 +72,7 @@
 struct phyplus_lowerhalf_s
 {
   FAR const struct timer_ops_s   *ops;     /* Lower half operations        */
-  FAR struct phyplus_timer_dev_s *tim;     /* pic32mz timer driver         */
+  FAR struct phyplus_tim_dev_s   *tim;     /* pic32mz timer driver         */
   tccb_t                         callback; /* Current user interrupt cb    */
   FAR void                       *arg;     /* Argument to upper half cb    */
   bool                           started;  /* True: Timer has been started */
@@ -323,7 +323,7 @@ static int phyplus_settimeout(FAR struct timer_lowerhalf_s *lower,
 
   if (timeout < 1 || timeout > TMR_MAXTIMEOUT)
     {
-      wderr("ERROR: Cannot represent timeout=%" PRId32 " > %" PRId32 "\n",
+      wderr("ERROR: Cannot represent timeout=%" PRId32 " > %" PRId16"\n",
             timeout, TMR_MAXTIMEOUT);
       return -ERANGE;
     }
@@ -561,7 +561,7 @@ static int phyplus_getstatus(FAR struct timer_lowerhalf_s *lower,
                              FAR struct timer_status_s *status)
 {
   FAR struct phyplus_lowerhalf_s *priv =
-      (FAR struct stm32l4_lowerhalf_s *)lower;
+      (FAR struct phyplus_lowerhalf_s *)lower;
   uint32_t value;
 
   DEBUGASSERT(priv);
@@ -598,7 +598,7 @@ int phyplus_timer_register(FAR struct phyplus_timer_param_s
 {
   FAR const char *fmt;
   char devname[16];
-  int ret;
+
   fmt = "/dev/timer%u";
 
   if ((phyplus_timer_param->timer_idx < 1) ||
@@ -614,7 +614,7 @@ int phyplus_timer_register(FAR struct phyplus_timer_param_s
 int phyplus_timer_ungister(FAR struct phyplus_timer_param_s
                            *phyplus_timer_param)
 {
-  return phyplus_timer_uninitialize(phyplus_timer_param->timer_idx);
+  return 0;
 }
 
 #endif

arch/arm/src/phy62xx/phyplus_wdt.c

@@ -0,0 +1,464 @@
+/****************************************************************************
+ * arch/arm/src/phy62xx/phyplus_wdt.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <debug.h>
+#include <assert.h>
+
+#include <nuttx/irq.h>
+#include <nuttx/clock.h>
+#include <nuttx/timers/watchdog.h>
+#include <arch/board/board.h>
+
+#include "phyplus_wdt.h"
+#include "jump_function.h"
+#include "mcu_phy_bumbee.h"
+#include "clock.h"
+
+#if defined(CONFIG_WATCHDOG)
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define WATCHDOG_1000MS_EVENT    0x0001
+#define WATCHDOG_1000MS_CYCLE    1000
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/* This structure provides the private representation of the "lower-half"
+ * driver state structure.  This structure must be cast-compatible with the
+ * well-known watchdog_lowerhalf_s structure.
+ */
+
+void __attribute__((used))  hal_WATCHDOG_IRQHandler(void)
+{
+    volatile uint32_t a;
+    a = AP_WDT->EOI;
+    AP_WDT->CRR = 0x76;
+}
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/* "Lower half" driver methods **********************************************/
+
+static int    phyplus_wdt_start(FAR struct watchdog_lowerhalf_s *lower);
+static int    phyplus_wdt_stop(FAR struct watchdog_lowerhalf_s *lower);
+static int    phyplus_wdt_keepalive(FAR struct watchdog_lowerhalf_s *lower);
+static int    phyplus_wdt_getstatus(FAR struct watchdog_lowerhalf_s *lower,
+                                     FAR struct watchdog_status_s *status);
+static int    phyplus_wdt_settimeout(FAR struct watchdog_lowerhalf_s *lower,
+                                      uint32_t timeout);
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/* "Lower half" driver methods */
+
+static const struct watchdog_ops_s g_wdgops =
+{
+  .start      = phyplus_wdt_start,
+  .stop       = phyplus_wdt_stop,
+  .keepalive  = phyplus_wdt_keepalive,
+  .getstatus  = phyplus_wdt_getstatus,
+  .settimeout = phyplus_wdt_settimeout,
+  .capture    = NULL, /* phyplus_wdt_capture, */
+  .ioctl      = NULL, /* phyplus_wdt_ioctl, */
+};
+
+struct phyplus_lowerhalf_s
+{
+  FAR const struct watchdog_ops_s  *ops; /* Lower half operations */
+  bool     started;                      /* true: The watchdog timer has been started */
+  bool     intr_mode;                    /* 0: not use intr_callback handle, 1: use intr_callback handle */
+  WDG_CYCLE_Type_e wdt_cycle;
+};
+
+static struct phyplus_lowerhalf_s g_wdgdev;
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+static int pp_watchdog_init(void)
+{
+  wdinfo("pp_init\n");
+
+  uint8_t delay;
+  hal_clk_gate_enable(MOD_WDT);
+
+  /* wdt_reset_en : software reset enable */
+
+  /* 1---enable  0---disable */
+
+  if ((AP_PCR->SW_RESET0 & 0x04) == 0)
+    {
+      AP_PCR->SW_RESET0 |= 0x04;
+      delay = 20;
+
+      while (delay-- > 0);
+    }
+
+  /* wdt software reset enable in 0xc */
+
+  /* 1---enable  0---disable */
+
+  if ((AP_PCR->SW_RESET2 & 0x04) == 0)
+    {
+      AP_PCR->SW_RESET2 |= 0x04;
+      delay = 20;
+
+      while (delay-- > 0);
+    }
+
+  /* watchdog software reset  */
+
+  /* 1---normal  0---reset */
+
+  AP_PCR->SW_RESET2 &= ~0x20;
+  delay = 20;
+
+  while (delay-- > 0);
+
+  AP_PCR->SW_RESET2 |= 0x20;
+  delay = 20;
+
+  while (delay-- > 0);
+
+  return 0;
+}
+
+static int pp_watchdog_start(bool interrupt_mode, WDG_CYCLE_Type_e cycle)
+{
+  wdinfo("pp_start\n");
+  volatile uint32_t a;
+
+  a = AP_WDT->EOI;
+  AP_WDT->TORR = cycle;
+  if (TRUE == interrupt_mode)
+    {
+      JUMP_FUNCTION(WDT_IRQ_HANDLER) = (uint32_t)&hal_WATCHDOG_IRQHandler;
+      AP_WDT->CR = 0x1f;
+      NVIC_SetPriority((IRQn_Type)WDT_IRQn, IRQ_PRIO_HAL);
+      NVIC_EnableIRQ((IRQn_Type)WDT_IRQn);
+    }
+  else
+    {
+      JUMP_FUNCTION(WDT_IRQ_HANDLER) = 0;
+      AP_WDT->CR = 0x1d;
+      NVIC_DisableIRQ((IRQn_Type)WDT_IRQn);
+    }
+  AP_WDT->CRR = 0x76;
+
+  return 0;
+}
+
+static int pp_watchdog_stop(void)
+{
+  wdinfo("pp_stop not support\n");
+
+  /* phyplus current not support stop watchdog while watchdog is running */
+
+  return 0;
+}
+
+static int __attribute__((used)) pp_watchdog_settimer(WDG_CYCLE_Type_e cycle)
+{
+  wdinfo("pp_settimer\n");
+  AP_WDT->TORR = cycle;
+  return 0;
+}
+
+static int pp_watchdog_feed(void)
+{
+  wdinfo("pp_feed\n");
+  AP_WDT->CRR = 0x76;
+  return 0;
+}
+
+/****************************************************************************
+ * Name: phyplus_wdt_start
+ *
+ * Description:
+ *   Start the watchdog timer, resetting the time to the current timeout,
+ *
+ * Input Parameters:
+ *   lower - A pointer the publicly visible representation of
+ *           the "lower-half" driver state structure.
+ *
+ * Returned Value:
+ *   Zero on success; a negated errno value on failure.
+ *
+ ****************************************************************************/
+
+static int phyplus_wdt_start(FAR struct watchdog_lowerhalf_s *lower)
+{
+  FAR struct phyplus_lowerhalf_s *priv =
+    (FAR struct phyplus_lowerhalf_s *)lower;
+  irqstate_t flags;
+
+  wdinfo("wdt_start\n");
+
+  DEBUGASSERT(priv);
+
+  /* Have we already been started? */
+
+  if (!priv->started)
+    {
+      /* Enable IWDG (the LSI oscillator will be enabled by hardware).  NOTE:
+       * If the "Hardware watchdog" feature is enabled through the device
+       * option bits, the watchdog is automatically enabled at power-on.
+       */
+
+      flags           = enter_critical_section();
+      pp_watchdog_start(priv->intr_mode, priv->wdt_cycle);
+      priv->started   = true;
+      leave_critical_section(flags);
+    }
+
+  return OK;
+}
+
+/****************************************************************************
+ * Name: phyplus_wdt_stop
+ *
+ * Description:
+ *   Stop the watchdog timer
+ *
+ * Input Parameters:
+ *   lower - A pointer the publicly visible representation of the
+ *           "lower-half" driver state structure.
+ *
+ * Returned Value:
+ *   Zero on success; a negated errno value on failure.
+ *
+ ****************************************************************************/
+
+static int phyplus_wdt_stop(FAR struct watchdog_lowerhalf_s *lower)
+{
+  FAR struct phyplus_lowerhalf_s *priv =
+    (FAR struct phyplus_lowerhalf_s *)lower;
+
+  wdinfo("wdt_stop\n");
+
+  if (priv->started)
+    {
+      priv->started   = false;
+      pp_watchdog_stop();
+    }
+
+  return -ENOSYS;
+}
+
+/****************************************************************************
+ * Name: phyplus_wdt_keepalive
+ *
+ * Description:
+ *   Reset the watchdog timer to the current timeout value, prevent any
+ *   imminent watchdog timeouts.  This is sometimes referred as "pinging"
+ *   the watchdog timer or "petting the dog".
+ *
+ * Input Parameters:
+ *   lower - A pointer the publicly visible representation of the
+ *           "lower-half" driver state structure.
+ *
+ * Returned Value:
+ *   Zero on success; a negated errno value on failure.
+ *
+ ****************************************************************************/
+
+static int phyplus_wdt_keepalive(FAR struct watchdog_lowerhalf_s *lower)
+{
+  /* FAR struct phyplus_lowerhalf_s *priv =
+   * (FAR struct phyplus_lowerhalf_s *)lower;
+   */
+
+  irqstate_t flags;
+
+  wdinfo("wdt_feed\n");
+
+  flags = enter_critical_section();
+
+  pp_watchdog_feed();
+
+  leave_critical_section(flags);
+
+  return OK;
+}
+
+/****************************************************************************
+ * Name: phyplus_wdt_getstatus
+ *
+ * Description:
+ *   Get the current watchdog timer status
+ *
+ * Input Parameters:
+ *   lower  - A pointer the publicly visible representation of the
+ *            "lower-half" driver state structure.
+ *   status - The location to return the watchdog status information.
+ *
+ * Returned Value:
+ *   Zero on success; a negated errno value on failure.
+ *
+ ****************************************************************************/
+
+static int phyplus_wdt_getstatus(FAR struct watchdog_lowerhalf_s *lower,
+                             FAR struct watchdog_status_s *status)
+{
+  FAR struct phyplus_lowerhalf_s *priv =
+    (FAR struct phyplus_lowerhalf_s *)lower;
+  DEBUGASSERT(priv);
+
+  wdinfo("wdt getstatus\n");
+
+  wdinfo("CR:%08x , TORR:%08lx , CCVR:%08lx , STAT:%08x\n", AP_WDT->CR ,
+      AP_WDT->TORR , AP_WDT->CCVR , AP_WDT->STAT);
+
+  if (priv->started)
+    {
+      status->flags |= WDFLAGS_ACTIVE;
+    }
+  else
+    {
+      status->flags |= WDFLAGS_RESET;
+    }
+
+  status->timeout = 0x0;
+  status->timeleft = AP_WDT->CCVR;
+
+  return OK;
+}
+
+/****************************************************************************
+ * Name: phhyplus_wdt_settimeout
+ *
+ * Description:
+ *   Set a new timeout value (and reset the watchdog timer)
+ *
+ * Input Parameters:
+ *   lower   - A pointer the publicly visible representation of the
+ *             "lower-half" driver state structure.
+ *   timeout - The new timeout value in milliseconds.
+ *
+ * Returned Value:
+ *   Zero on success; a negated errno value on failure.
+ *
+ ****************************************************************************/
+
+static int phyplus_wdt_settimeout(FAR struct watchdog_lowerhalf_s *lower,
+                              uint32_t timeout)
+{
+  FAR struct phyplus_lowerhalf_s *priv =
+    (FAR struct phyplus_lowerhalf_s *)lower;
+
+  wdinfo("wdt set timeout timeout=%lu\n", timeout);
+  timeout = timeout / 1000;
+
+  if (timeout < 4)
+    {
+      priv->wdt_cycle = WDG_2S;
+    }
+  else if((timeout < 8) && (timeout >= 4))
+    {
+      priv->wdt_cycle = WDG_4S;
+    }
+  else if((timeout < 16) && (timeout >= 8))
+    {
+      priv->wdt_cycle = WDG_8S;
+    }
+  else if((timeout < 32) && (timeout >= 16))
+    {
+      priv->wdt_cycle = WDG_16S;
+    }
+  else if((timeout < 64) && (timeout >= 32))
+    {
+      priv->wdt_cycle = WDG_32S;
+    }
+  else if((timeout < 128) && (timeout >= 64))
+    {
+      priv->wdt_cycle = WDG_64S;
+    }
+  else if((timeout < 256) && (timeout >= 128))
+    {
+      priv->wdt_cycle = WDG_128S;
+    }
+  else if(timeout > 256)
+    {
+      priv->wdt_cycle = WDG_256S;
+    }
+
+  AP_WDT->TORR = priv->wdt_cycle;
+
+  return OK;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: phyplus_wdt_initialize
+ *
+ * Description:
+ *   Initialize the IWDG watchdog timer.  The watchdog timer is initialized
+ *   and registers as 'devpath'.  The initial state of the watchdog timer is
+ *   disabled.
+ *
+ * Input Parameters:
+ *   devpath - The full path to the watchdog.  This should be of the form
+ *     /dev/watchdog0
+ *   lsifreq - The calibrated LSI clock frequency
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+void phyplus_wdt_initialize(FAR const char *devpath)
+{
+  FAR struct phyplus_lowerhalf_s *priv = &g_wdgdev;
+
+  wdinfo("wdt initialize\n");
+
+  /* Initialize the driver state structure. */
+
+  priv->ops     = &g_wdgops;
+  priv->started = false;
+  priv->intr_mode = false;
+  priv->wdt_cycle = WDG_2S;
+
+  pp_watchdog_init();
+
+  watchdog_register(devpath, (FAR struct watchdog_lowerhalf_s *)priv);
+}
+
+#endif /* CONFIG_WATCHDOG */
+

arch/arm/src/phy62xx/phyplus_wdt.h

@@ -0,0 +1,74 @@
+/****************************************************************************
+ * arch/arm/src/phy62xx/phyplus_wdt.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_PHY62XX_PHYPLUS_WDT_H
+#define __ARCH_ARM_SRC_PHY62XX_PHYPLUS_WDT_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "chip.h"
+
+#ifdef CONFIG_WATCHDOG
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+typedef enum
+{
+    WDG_2S =   0,
+    WDG_4S =   1,
+    WDG_8S =   2,
+    WDG_16S =  3,
+    WDG_32S =  4,
+    WDG_64S =  5,
+    WDG_128S = 6,
+    WDG_256S = 7
+} WDG_CYCLE_Type_e;
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+void phyplus_wdt_initialize(FAR const char *devpath);
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* CONFIG_WATCHDOG */
+#endif /* __ARCH_ARM_SRC_PHY62XX_PHYPLUS_WDT_H */

arch/arm/src/phy62xx/pplus_mtd_flash.c

@@ -126,8 +126,11 @@ static int pplus_fls_erase_sector(struct pplus_fls_dev_s *priv, off_t sector)
   /* Get the address associated with the sector */
 
   address = (off_t)((sector << priv->sectorshift) + priv->offset);
+  _HAL_CS_ALLOC_();
+  HAL_ENTER_CRITICAL_SECTION();
 
   hal_flash_erase_sector(address);
+  HAL_EXIT_CRITICAL_SECTION();
   return OK;
 }
 
@@ -144,7 +147,10 @@ static int pplus_fls_erase_chip(struct pplus_fls_dev_s *priv)
 
   for (i = 0; i < priv->nsectors; i++)
     {
+      _HAL_CS_ALLOC_();
+      HAL_ENTER_CRITICAL_SECTION();
       hal_flash_erase_sector(address);
+      HAL_EXIT_CRITICAL_SECTION();
       address += (1ul << priv->sectorshift);
     }
 
@@ -213,9 +219,12 @@ static ssize_t pplus_fls_bwrite(FAR struct mtd_dev_s *dev, off_t startblock,
 
   finfo("startblock: %08lx nblocks: %d\n", (long)startblock, (int)nblocks);
 
+  _HAL_CS_ALLOC_();
+  HAL_ENTER_CRITICAL_SECTION();
   int ret = hal_flash_write(priv->offset + (startblock << priv->pageshift),
       (uint8_t *)buffer, nblocks << priv->pageshift);
 
+  HAL_EXIT_CRITICAL_SECTION();
   if (ret)
     {
       ferr("ERROR: spif_write failed: %d\n", ret);
@@ -363,7 +372,7 @@ struct mtd_dev_s *pplus_fls_initialize(uint32_t offset, uint32_t size)
       priv->size        = size;
       priv->sectorshift = 12;
       priv->pageshift   = 8;
-      priv->nsectors    = 64;
+      priv->nsectors    = 32;
 
       /* Identify the FLASH chip and get its capacity */
 
@@ -379,6 +388,7 @@ struct mtd_dev_s *pplus_fls_initialize(uint32_t offset, uint32_t size)
 
   /* errout_with_priv: */
 
-  kmm_free(priv);
+  /* kmm_free(priv); */
-  return NULL;
+
+  /* return NULL; */
 }

arch/arm/src/phy62xx/rom_sym_def.h

@@ -31,6 +31,7 @@
    * #define x _symrom_
    */
 
+  #define TIM2_IRQHandler _symrom_TIM2_IRQHandler
   #define gpio_write _symrom_gpio_write
   #define ll_processExtInitIRQ _symrom_ll_processExtInitIRQ
   #define ll_processExtScanIRQ _symrom_ll_processExtScanIRQ
@@ -956,6 +957,7 @@
   #define spif_wrdata _symrom_spif_wrdata
   #define spif_write _symrom_spif_write
   #define spif_write_protect _symrom_spif_write_protect
+  #define spif_write_dma _symrom_spif_write_dma
   #define sram_ret_patch _symrom_sram_ret_patch
   #define supportedCmdsTable _symrom_supportedCmdsTable
   #define syncInfo _symrom_syncInfo

arch/arm/src/phy62xx/start.c

@@ -37,10 +37,10 @@
 
 #include "start.h"
 #include "clock.h"
-#include "flash.h"
 #include "log.h"
+#include "flash.h"
 #include "jump_function.h"
-
+#include "rom_sym_def.h"
 /* #include "rf_phy_driver.h" */
 
 /****************************************************************************
@@ -52,7 +52,7 @@ extern const uint32_t _sramscttext;
 extern const uint32_t _eramscttext;
 
 extern const uint32_t _sjtblss;
-extern uint32_t _sjtbls;
+extern const uint32_t _sjtbls;
 extern const uint32_t _ejtbls;
 
 #define IDLE_STACK ((uint32_t)&_ebss+CONFIG_IDLETHREAD_STACKSIZE)
@@ -95,10 +95,14 @@ const uintptr_t g_idle_topstack = IDLE_STACK;
 extern uint32_t *jump_table_base[];
 
 extern volatile sysclk_t g_system_clk;
+extern void *osal_memset(void *s, int c, size_t n);
+extern void *osal_memcpy(void *dest, const void *src, size_t n);
+
 void c_start(void)
 {
-  const uint32_t *src;
+  const uint8_t *src;
-  uint32_t *dest;
+  uint8_t *dest;
+  uint8_t *edest;
 
   /* Configure the uart so that we can get debug output as soon as possible */
 
@@ -108,8 +112,10 @@ void c_start(void)
 
   HAL_CRITICAL_SECTION_INIT();
 
-  g_system_clk = SYS_CLK_DLL_48M;
+  /* g_system_clk = SYS_CLK_DLL_48M; */
-  clk_init(SYS_CLK_DLL_48M);
+
+  g_system_clk = SYS_CLK_DBL_32M;
+  clk_init(SYS_CLK_DBL_32M);
 
   /* clk_init(SYS_CLK_XTAL_16M); */
 #if 1
@@ -119,10 +125,15 @@ void c_start(void)
    * certain that there are no issues with the state of global variables.
    */
 
-  for (dest = &_sbss; dest < &_ebss; )
+  dest = (uint8_t *)&_sbss;
-    {
+  edest = (uint8_t *)&_ebss;
-      *dest++ = 0;
+  osal_memset(dest, 0, edest - dest);
-    }
+
+  /* for (dest = &_sbss; dest < &_ebss; )
+   *  {
+   *    *dest++ = 0;
+   *  }
+   */
 
   /* showprogress('B'); */
 
@@ -132,10 +143,16 @@ void c_start(void)
    * end of all of the other read-only data (.text, .rodata) at _eronly.
    */
 
-  for (src = &_eronly, dest = &_sdata; dest < &_edata; )
+  src = (const uint8_t *)&_eronly;
-    {
+  dest = (uint8_t *)&_sdata;
-      *dest++ = *src++;
+  edest = (uint8_t *)&_edata;
-    }
+  osal_memcpy(dest, src, edest - dest);
+
+  /* for (src = &_eronly, dest = &_sdata; dest < &_edata; )
+   *  {
+   *    *dest++ = *src++;
+   *  }
+   */
 
   /* showprogress('C'); */
 
@@ -145,16 +162,36 @@ void c_start(void)
    *  }
    */
 
-  for (src = &_sjtblss, dest = &_sjtbls; dest < &_ejtbls; )
+  src = (const uint8_t *)&_sjtblss;
-    {
+  dest = (uint8_t *)&_sjtbls;
-      *dest++ = *src++;
+  edest = (uint8_t *)&_ejtbls;
-    }
+  osal_memcpy(dest, src, edest - dest);
+
+  /* osal_memcpy(&_sjtbls, &_sjtblss, _ejtbls - _sjtbls);
+   * for (src = &_sjtblss, dest = &_sjtbls; dest < &_ejtbls; )
+   * {
+   *  *dest++ = *src++;
+   * }
+   */
 
   /* showprogress('J'); */
 
   /* Perform early serial initialization */
 
-  hal_gpio_init();
+  /* hal_cache_init(); */
+
+    {
+      xflash_Ctx_t cfg =
+        {
+          .spif_ref_clk   =   SYS_CLK_DLL_64M,
+          .rd_instr       =   XFRD_FCMD_READ_DUAL
+        };
+
+      hal_spif_cache_init(cfg);
+    }
+
+  /* hal_gpio_init(); */
+
   LOG_INIT();
   showprogress('A');
 #ifdef USE_EARLYSERIALINIT

arch/arm/src/phy62xx/uart.c

@@ -41,13 +41,20 @@
 #include "pwrmgr.h"
 #include "error.h"
 #include "jump_function.h"
+
 #include <nuttx/irq.h>
 #include <nuttx/arch.h>
 #include <nuttx/fs/ioctl.h>
 #include <nuttx/serial/serial.h>
 #include <nuttx/mm/circbuf.h>
 
-#define UART_TX_BUFFER_SIZE   256
+#define UART_TX_BUFFER_SIZE   64
+#define UART_RX_BUFFER_SIZE   64
+uint8_t fifo_data_store[2][UART_RX_FIFO_SIZE];
+uint8_t fifo_len_store[2] =
+{
+  0, 0
+};
 
 typedef struct _uart_Context
 {
@@ -62,6 +69,9 @@ typedef struct _uart_Context
   uint8_t       tx_state;
   uart_Tx_Buf_t tx_buf;
   uart_Cfg_t    cfg;
+  uint8_t fifo_buf_store[UART_RX_BUFFER_SIZE];
+  int buf_head;
+  int buf_tail;
 } uart_Ctx_t;
 
 static uart_Ctx_t m_uartCtx[2] =
@@ -183,9 +193,12 @@ static void irq_rx_handler(UART_INDEX_e uart_index, uint8_t flg)
   if (m_uartCtx[uart_index].cfg.use_fifo)
     {
       len = cur_uart->RFL;
-
+      fifo_len_store[uart_index] = len;
       for (i = 0; i < len; i++)
+        {
           data[i] = (uint8_t)(cur_uart->RBR & 0xff);
+          fifo_data_store[uart_index][i] = data[i];
+        }
     }
   else
     {
@@ -407,6 +420,9 @@ int uart_hw_init(UART_INDEX_e uart_index)
       cur_uart->IER |= IER_PTIME;
     }
 
+  if (pcfg->use_tx_buf)
+      cur_uart->IER |= IER_ETBEI;
+
   NVIC_SetPriority(irq_type, IRQ_PRIO_HAL);
   NVIC_EnableIRQ(irq_type);
   return PPlus_SUCCESS;
@@ -615,7 +631,7 @@ static int pplus_uart_setup(struct uart_dev_s *dev)
       .rts_pin = GPIO_DUMMY,
       .cts_pin = GPIO_DUMMY,
       .baudrate = 115200,
-      .use_fifo = FALSE,
+      .use_fifo = TRUE,
       .hw_fwctrl = FALSE,
       .use_tx_buf = FALSE,
       .parity     = FALSE,
@@ -877,11 +893,31 @@ static int pplus_uart_ioctl(struct file *filep, int cmd, unsigned long arg)
 static int pplus_uart_receive(struct uart_dev_s *dev, unsigned int *status)
 {
   uart_Ctx_t *priv = (uart_Ctx_t *)dev->priv;
-  uint32_t data;
 
-  /* Get input data along with receiver control information */
+  /* uint32_t data;
+   * static uint8_t fifo_buf_store[UART_RX_BUFFER_SIZE];
+   * static int buf_head;
+   * static int buf_tail;
+   */
+
+  /* Put fifo data into loopback buffer */
+
+  for (int i = 0; i < fifo_len_store[priv->ID] ; i++)
+    {
+      priv->fifo_buf_store[priv->buf_head] = fifo_data_store[priv->ID][i];
+      priv->buf_head = priv->buf_head + 1;
+      if (priv->buf_head == UART_RX_BUFFER_SIZE)
+        {
+          priv->buf_head = 0;
+        }
+    }
+
+  fifo_len_store[priv->ID] = 0;
+  if (priv->buf_tail == UART_RX_BUFFER_SIZE)
+    {
+      priv->buf_tail = 0;
+    }
 
-  data = (uint32_t)(priv->reg->RBR & 0xff);
   priv->rx_available = false;
 
   /* Return receiver control information */
@@ -891,9 +927,9 @@ static int pplus_uart_receive(struct uart_dev_s *dev, unsigned int *status)
       *status = 0x00;
     }
 
-  /* Then return the actual received data. */
+  /* Then return the fifo data byte by byte. */
 
-  return data;
+  return (char)priv->fifo_buf_store[priv->buf_tail++];
 }
 
 /****************************************************************************
@@ -921,11 +957,26 @@ static void pplus_uart_rxint(struct uart_dev_s *dev, bool enable)
 
 static bool pplus_uart_rxavailable(struct uart_dev_s *dev)
 {
+  static int len_fifo;
   uart_Ctx_t *priv = (uart_Ctx_t *)dev->priv;
 
-  /* Return true if the receive buffer/fifo is not "empty." */
+  /* Detect the length of received data from fifo */
 
-  return priv->rx_available;
+  if (len_fifo == 0)
+    {
+      hal_UART0_IRQHandler();
+      len_fifo = fifo_len_store[priv->ID];
+    }
+
+  if (len_fifo <= 0)
+    {
+      len_fifo = 0;
+      return len_fifo;
+    }
+  else
+    {
+      return len_fifo--;
+    }
 }
 
 /****************************************************************************

boards/arm/phy62xx/phy6222/configs/nsh/defconfig

@@ -33,8 +33,8 @@ CONFIG_NSH_FILEIOSIZE=64
 CONFIG_NUNGET_CHARS=0
 CONFIG_PREALLOC_TIMERS=0
 CONFIG_PTHREAD_STACK_DEFAULT=1536
-CONFIG_RAM_SIZE=59392
+CONFIG_RAM_SIZE=59264
-CONFIG_RAM_START=0x1fff1c00
+CONFIG_RAM_START=0x1fff1880
 CONFIG_RAW_BINARY=y
 CONFIG_RR_INTERVAL=200
 CONFIG_SCHED_WAITPID=y

boards/arm/phy62xx/phy6222/configs/phy_sbp/defconfig

@@ -63,8 +63,8 @@ CONFIG_NSH_FILE_APPS=y
 CONFIG_NUNGET_CHARS=0
 CONFIG_PREALLOC_TIMERS=0
 CONFIG_PTHREAD_STACK_DEFAULT=1536
-CONFIG_RAM_SIZE=59392
+CONFIG_RAM_SIZE=59264
-CONFIG_RAM_START=0x1fff1c00
+CONFIG_RAM_START=0x1fff1880
 CONFIG_RAW_BINARY=y
 CONFIG_RR_INTERVAL=200
 CONFIG_SCHED_WAITPID=y

boards/arm/phy62xx/phy6222/scripts/Make.defs

@@ -51,6 +51,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS)
 CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS)
 AFLAGS := $(CFLAGS) -D__ASSEMBLY__
 
+CFLAGS += -ffunction-sections -fdata-sections
+
 NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common
 NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections
 LDNXFLATFLAGS = -e main -s 2048
@@ -62,4 +64,4 @@ ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
   LDFLAGS += -g
 endif
 
-
+LDFLAGS += --gc-sections

boards/arm/phy62xx/phy6222/scripts/flash.ld

@@ -4,8 +4,8 @@ MEMORY
 {
   jumptbl (rwx) : ORIGIN = 0x1fff0000, LENGTH = 1K
   gcfgtbl  (rwx) : ORIGIN = 0x1fff0400, LENGTH = 1K
-  flash (rx) : ORIGIN = 0x1100e000, LENGTH = 256K
+  flash (rx) : ORIGIN = 0x1100e000, LENGTH = 384K
-  sram (rwx) : ORIGIN = 0x1fff1c00, LENGTH = 58K
+  sram (rwx) : ORIGIN = 0x1fff1880, LENGTH = 59264
 }
 
 OUTPUT_ARCH(arm)
@@ -62,7 +62,7 @@ SECTIONS
     .data : {
         _sdata = ABSOLUTE(.);
         _stextram = ABSOLUTE(.);
-        *flash.o(.text .text.*)
+        *libarch.a:*flash.o(.text .text.*)
 	*libarch.a:phy62xx_exception.o(.text .text.*)
 	*libarch.a:irq.o(.text.arm_ack_irq)
 	*phy62xx_ble_patch.o(.text .text.*)
@@ -88,8 +88,53 @@ SECTIONS
         //*libarch.a:phy62xx_ble_patch.o(.text.ll_processBasicIRQ_SRX0)
         //*libarch.a:phy62xx_ble_patch.o(.text.ll_hw_read_rfifo1)
 		
+
+        *libphy6222_rf.a:patch.o(.text.ll_hw_go1)
+        *libphy6222_rf.a:patch.o(.text.TIM1_IRQHandler1)
+        *libphy6222_rf.a:patch.o(.text.LL_IRQHandler1)
+        *libphy6222_rf.a:patch.o(.text.rf_phy_change_cfg0)
+        *libphy6222_rf.a:patch.o(.text.rf_calibrate1)
+        *libphy6222_rf.a:patch.o(.text.l2capPocessFragmentTxData)
+        *libphy6222_rf.a:patch.o(.text.LL_SetDataLengh1)
+        *libphy6222_rf.a:patch.o(.text.llProcessTxData1)
+        *libphy6222_rf.a:patch.o(.text.ll_generateTxBuffer1)
+        *libphy6222_rf.a:patch.o(.text.ll_adptive_adj_next_time1)
+        *libphy6222_rf.a:patch.o(.text.llSecAdvAllow1)
+        *libphy6222_rf.a:patch.o(.text.ll_scheduler1)
+        *libphy6222_rf.a:patch.o(.text.osal_set_event1)
+        *libphy6222_rf.a:patch.o(.text.ll_processBasicIRQ_SRX)
+        *libphy6222_rf.a:patch.o(.text.ll_processBasicIRQ_secondaryAdvTRX)
+        *libphy6222_rf.a:patch.o(.text.ll_processBasicIRQ_ScanTRX)
+        *libphy6222_rf.a:patch.o(.text.llSlaveEvt_TaskEndOk1)
+        *libphy6222_rf.a:patch.o(.text.ll_processBasicIRQ_secondaryAdvTRX0)
+        *libphy6222_rf.a:patch.o(.text.ll_processBasicIRQ_ScanTRX0)
+        *libphy6222_rf.a:patch.o(.text.ll_processBasicIRQ_SRX0)
+        *libphy6222_rf.a:patch.o(.text.ll_hw_read_rfifo1)
+		
+        *libphy6222_rf.a:patch.o(.text.LL_set_default_conn_params1)
+        *libphy6222_rf.a:patch.o(.text.llConnTerminate1)
+        *libphy6222_rf.a:patch.o(.text.config_RTC1)
+        *libphy6222_rf.a:patch.o(.text.wakeup_init1)
+        *libphy6222_rf.a:patch.o(.text.LL_ENC_AES128_Encrypt1)
+        *libphy6222_rf.a:patch.o(.text.LL_ENC_Encrypt1)
+        *libphy6222_rf.a:patch.o(.text.LL_ENC_Decrypt1)
+        *libphy6222_rf.a:patch.o(.text.ll_processBasicIRQ_secondaryScanSRX)
+        *libphy6222_rf.a:patch.o(.text.llProcessSlaveControlProcedures1)
+        *libphy6222_rf.a:patch.o(.text.llCalcMaxScanTime1)
+        *libphy6222_rf.a:patch.o(.text.LL_SetAdvControl1)
+        *libphy6222_rf.a:patch.o(.text.llSetupSecAdvEvt1)
+        *libphy6222_rf.a:patch.o(.text.ll_scheduler2)
+        *libphy6222_rf.a:patch.o(.text.llSetupNextSlaveEvent1)
+		
+	*libapps.a:flash.c.*.o(.text .text.*)
+	*libapps.a:*.o(.text.drv_disable_irq1)
+	*libapps.a:*.o(.text.drv_enable_irq1)
+
         *rf_phy_driver.o(.text.rf_phy_get_pktFoot)
         *rf_phy_driver.o(.text.rf_phy_change_cfg0 )
+        *libphy6222_host.a:l2cap_util.o(.text.L2CAP_Fragment_SendDataPkt)
+        *libphy6222_host.a:l2cap_util.o(.text.l2capSegmentBuffToLinkLayer)
+        *libphy6222_host.a:l2cap_util.o(.text.l2capPocessFragmentTxData)
 		
         *libarch.a:phy62xx_ble_hcitl.o(.text.phy62xx_ble_init)
         *libarch.a:phy62xx_ble_hcitl.o(.text.HCI_ProcessEvent1)
@@ -102,8 +147,8 @@ SECTIONS
         *libarch.a:phy62xx_ble.o(.text.pplus_ble_recv_cb_h4 .text.pplus_ble_recv_cb_acl)
         *libarch.a:phy62xx_ble.o(.text.pplus_ble_recv_msg )
         *libarch.a:arm_doirq.o(.text.arm_doirq )
-        *libarch.a:arm_hardfault.o(.text.arm_hardfault )
+        *libarch.a:phy62xx_hardfault.o(.text.arm_hardfault )
-        *libarch.a:irq_dispatch.o(.text.irq_dispatch )
+        *libsched.a:irq_dispatch.o(.text.irq_dispatch )
 		
         *libsched.a:clock_initialize.o(.text.clock_timer)
         *libsched.a:sched_processtimer.o(.text.nxsched_process_timer)
@@ -113,6 +158,7 @@ SECTIONS
         *libsched.a:sched_lock.o(.text .text.*)
         *libsched.a:sched_unlock.o(.text .text.*)
 		
+
         *libdrivers.a:uart_bth4.o(.text.uart_bth4_pollnotify)
         *libdrivers.a:uart_bth4.o(.text.uart_bth4_post)
         *libdrivers.a:uart_bth4.o(.text.uart_bth4_receive)
@@ -121,6 +167,9 @@ SECTIONS
 		
         *libmm.a:circbuf.o(.text .text.*)
 		
+	*libc.a:lib_libvsprintf.o(.text .text.*)
+	*libc.a:lib_printf.o(.text .text.*)
+	*libc.a:lib_vfprintf.o(.text .text.*)
 	*libc.a:lib_skipspace.o(.text .text.*)
         *libc.a:lib_sprintf.o(.text .text.*)
         *libc.a:lib_strlen.o(.text .text.*)

boards/arm/phy62xx/phy6222/src/Makefile

@@ -30,4 +30,6 @@ CSRCS += buttons.c
 
 CSRCS += appinit.c
 
+CSRCS += reset.c
+
 include $(TOPDIR)/boards/Board.mk

boards/arm/phy62xx/phy6222/src/bringup.c

@@ -36,7 +36,18 @@
 
 #include "phy6222.h"
 #include "pplus_mtd_flash.h"
+#ifdef CONFIG_PHY6222_BLE
 #include "phy62xx_ble.h"
+#endif
+
+#ifdef CONFIG_WATCHDOG
+#include "phyplus_wdt.h"
+#endif
+
+#ifdef CONFIG_TIMER
+extern int phyplus_timer_initialize(FAR const char *devpath, int timer);
+#endif
+
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
@@ -54,8 +65,8 @@
  *     Called from the NSH library
  *
  ****************************************************************************/
-#define PPLUS_MTD_START_OFFSET  0x40000   //start from 256k offset
+#define PPLUS_MTD_START_OFFSET  0x60000   //start from 384k offset
-#define PPLUS_MTD_SIZE          0x40000   //mtd size is 256k bytes
+#define PPLUS_MTD_SIZE          0x20000   //mtd size is 128k bytes
 
 int phy62xx_bringup(void)
 {
@@ -103,6 +114,7 @@ int phy62xx_bringup(void)
         }
 
 #endif
+
 #ifdef CONFIG_FS_LITTLEFS
 
       struct mtd_dev_s *mtd =
@@ -125,16 +137,26 @@ int phy62xx_bringup(void)
 
       /* Mount the LittleFS file system */
 
-      ret = nx_mount("/dev/mtd", "/mnt/lfs", "littlefs", 0,
+      ret = nx_mount("/dev/mtd", "/data", "littlefs", 0,
-                "forceformat");
+                "autoformat");
       if (ret < 0)
         {
           syslog(LOG_ERR,
-              "ERROR: Failed to mount LittleFS at /mnt/lfs: %d\n", ret);
+              "ERROR: Failed to mount LittleFS at /data: %d\n", ret);
         }
 
 #endif
 
+#ifndef CONFIG_PHY6222_SDK
+#ifdef CONFIG_TIMER
+  phyplus_timer_initialize("/dev/timer3", 3);
+#endif
+
+#ifdef CONFIG_WATCHDOG
+  phyplus_wdt_initialize("/dev/watchdog0");
+#endif
+#endif
+
 #ifdef CONFIG_PHY6222_BLE
 
   ret = pplus_ble_initialize();

boards/arm/phy62xx/phy6222/src/reset.c

@@ -0,0 +1,58 @@
+/****************************************************************************
+ * boards/arm/phy62xx/phy6222/src/reset.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/board.h>
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: board_reset
+ *
+ * Description:
+ *   Reset board.  Support for this function is required by board-level
+ *   logic if CONFIG_BOARDCTL_RESET is selected.
+ *
+ * Input Parameters:
+ *   status - Status information provided with the reset event.  This
+ *            meaning of this status information is board-specific.  If not
+ *            used by a board, the value zero may be provided in calls to
+ *            board_reset().
+ *
+ * Returned Value:
+ *   If this function returns, then it was not possible to power-off the
+ *   board due to some constraints.  The return value int this case is a
+ *   board-specific reason for the failure to shutdown.
+ *
+ ****************************************************************************/
+
+int board_reset(int status)
+{
+  up_systemreset();
+  return 0;
+}