More PIC32 debug updates

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4083 42af7a65-404d-4744-a932-0658087f49c3

arch/mips/src/common/up_internal.h

@@ -182,6 +182,10 @@ extern void up_dumpstate(void);
 
 extern uint32_t *up_doirq(int irq, uint32_t *regs);
 
+/* Software interrupt 0 handler */
+
+extern int up_swint0(int irq, FAR void *context);
+
 /* Signals */
 
 extern void up_sigdeliver(void);

arch/mips/src/mips32/up_swint0.c

@@ -326,7 +326,7 @@ int up_swint0(int irq, FAR void *context)
       case SYS_switch_context:
         {
           DEBUGASSERT(regs[REG_A1] != 0 && regs[REG_A2] != 0);
-          memcpy((uint32_t*)regs[REG_A1], regs, XCPTCONTEXT_SIZE);
+          up_copystate((uint32_t*)regs[REG_A1], regs);
           current_regs = (uint32_t*)regs[REG_A2];
         }
         break;

arch/mips/src/pic32mx/excptmacros.h

@@ -136,8 +136,8 @@
 	/* Then insert pending interrupt level as the current mask level in the CP0 status
 	 * register. Also clear bits 1-4 in new value of the status register:
 	 *
-     *   Bit 1: Exception Level
+	 *   Bit 1: Exception Level
-     *   Bit 2: Error Level
+	 *   Bit 2: Error Level
 	 *   Bit 3: (not used in PIC32MX)
 	 *   Bit 4: Operating mode == USER
 	 */

arch/mips/src/pic32mx/pic32mx-decodeirq.c

@@ -127,21 +127,9 @@ uint32_t *pic32mx_decodeirq(uint32_t *regs)
 
       irq = ((regval) & INT_INTSTAT_VEC_MASK) >> INT_INTSTAT_VEC_SHIFT;
       
-      /* Disable further interrupts from this source until the driver has
-       * cleared the pending interrupt sources.
-       */
-
-      up_disable_irq(irq);
-
       /* Deliver the IRQ */
 
       irq_dispatch(irq, regs);
-
-      /* Unmask the last interrupt (global interrupt below the current interrupt
-       * level are are still disabled)
-       */
-
-      up_enable_irq(irq);
     }
 
   /* If a context switch occurred while processing the interrupt then

arch/mips/src/pic32mx/pic32mx-head.S

@@ -435,6 +435,7 @@ _bev_handler:
 	USE_INTSTACK t0, t1, t2			/* Switch to the interrupt stack */
 	la		t0, pic32mx_dobev		/* Call up_dobev(regs) */
 	jalr	ra, t0
+	nop
 	di								/* Disable interrupts */
 	RESTORE_STACK t0, t1			/* Undo the operations of USE_STACK */
 	EXCPT_EPILOGUE v0				/* Return to the context returned by up_dobev() */
@@ -457,6 +458,7 @@ _int_handler:
 	USE_INTSTACK t0, t1, t2			/* Switch to the interrupt stack */
 	la		t0, pic32mx_decodeirq	/* Call pic32mx_decodeirq(regs) */
 	jalr	ra, t0
+	nop
 	di								/* Disable interrupts */
 	RESTORE_STACK t0, t1			/* Undo the operations of USE_STACK */
 	EXCPT_EPILOGUE v0				/* Return to the context returned by pic32mx_decodeirq() */
@@ -480,6 +482,7 @@ _nmi_handler:
 	USE_INTSTACK t0, t1, t2			/* Switch to the interrupt stack */
 	la		t0, pic32mx_donmi		/* Call up_donmi(regs) */
 	jalr	ra, t0
+	nop
 	di								/* Disable interrupts */
 	RESTORE_STACK t0, t1			/* Undo the operations of USE_STACK */
 	EXCPT_EPILOGUE v0				/* Return to the context returned by pic32mx_donmi() */

arch/mips/src/pic32mx/pic32mx-irq.c

@@ -143,12 +143,17 @@ void up_irqinitialize(void)
   putreg32(INT_INTCON_MVEC, PIC32MX_INT_INTCONCLR);
 #endif
 
-  /* Initialize GPIO change notifiction handling */
+  /* Initialize GPIO change notification handling */
  
 #ifdef CONFIG_GPIO_IRQ
   pic32mx_gpioirqinitialize();
 #endif
 
+  /* Attach and enable software interrupts */
+
+  irq_attach(PIC32MX_IRQ_CS0, up_swint0);
+  up_enable_irq(PIC32MX_IRQSRC_CS0);
+
   /* currents_regs is non-NULL only while processing an interrupt */
 
   current_regs = NULL;
@@ -194,14 +199,14 @@ void up_disable_irq(int irq)
           /* Use IEC0 */
 
           regaddr = PIC32MX_INT_IEC0CLR;
-          bitno  -= PIC32MX_IRQSRC0_FIRST;
+          bitno   = irq - PIC32MX_IRQSRC0_FIRST;
         }
       else if (irq <= PIC32MX_IRQSRC1_LAST)
         {
           /* Use IEC1 */
 
           regaddr = PIC32MX_INT_IEC1CLR;
-          bitno  -= PIC32MX_IRQSRC1_FIRST;
+          bitno   = irq - PIC32MX_IRQSRC1_FIRST;
         }
 #ifdef PIC32MX_IRQSRC2_FIRST
       else if (irq <= PIC32MX_IRQSRC2_LAST)
@@ -209,7 +214,7 @@ void up_disable_irq(int irq)
           /* Use IEC2 */
 
           regaddr = PIC32MX_INT_IEC2CLR;
-          bitno  -= PIC32MX_IRQSRC2_FIRST;
+          bitno   = irq - PIC32MX_IRQSRC2_FIRST;
         }
 #endif
       else
@@ -248,14 +253,14 @@ void up_enable_irq(int irq)
           /* Use IEC0 */
 
           regaddr = PIC32MX_INT_IEC0SET;
-          bitno  -= PIC32MX_IRQSRC0_FIRST;
+          bitno   = irq - PIC32MX_IRQSRC0_FIRST;
         }
       else if (irq <= PIC32MX_IRQSRC1_LAST)
         {
           /* Use IEC1 */
 
           regaddr = PIC32MX_INT_IEC1SET;
-          bitno  -= PIC32MX_IRQSRC1_FIRST;
+          bitno   = irq - PIC32MX_IRQSRC1_FIRST;
         }
 #ifdef PIC32MX_IRQSRC2_FIRST
       else if (irq <= PIC32MX_IRQSRC2_LAST)
@@ -263,7 +268,7 @@ void up_enable_irq(int irq)
           /* Use IEC2 */
 
           regaddr = PIC32MX_INT_IEC2SET;
-          bitno  -= PIC32MX_IRQSRC2_FIRST;
+          bitno   = irq - PIC32MX_IRQSRC2_FIRST;
         }
 #endif
       else

configs/pcblogic-pic32mx/ostest/defconfig

@@ -871,7 +871,7 @@ CONFIG_BOOT_RUNFROMFLASH=n
 CONFIG_BOOT_COPYTORAM=n
 CONFIG_CUSTOM_STACK=n
 CONFIG_STACK_POINTER=
-CONFIG_IDLETHREAD_STACKSIZE=1024
+CONFIG_IDLETHREAD_STACKSIZE=2048
 CONFIG_USERMAIN_STACKSIZE=2048
 CONFIG_PTHREAD_STACK_MIN=256
 CONFIG_PTHREAD_STACK_DEFAULT=2048

configs/pcblogic-pic32mx/ostest/ld.script

@@ -60,7 +60,7 @@ MEMORY
 	 *   Debug code    0x1fc02000 KSEG1  4096-16   12272
 	 *   DEVCFG3-0     0x1fc02ff0 KSEG1  16        12288 (12Kb)
 	 *
-	 * Exceptions assme:
+	 * Exceptions assume:
 	 *
 	 *   STATUS: BEV=1 and EXL=0
 	 *   CAUSE:  IV=1
@@ -79,9 +79,12 @@ MEMORY
 	/* The PIC32MX460F512L has 32Kb of data memory at physical address
 	 * 0x00000000.  Since the PIC32MX has no data cache, this memory is
 	 * always accessed through KSEG1.
+	 *
+	 * When used with MPLAB, we need to set aside 512 bytes of memory
+	 * for use by MPLAB.
 	 */
 
-	kseg1_datamem (w!x) : ORIGIN = 0xa0000000, LENGTH = 32K
+	kseg1_datamem (w!x) : ORIGIN = 0xa0000200, LENGTH = 32K - 512
 }
 
 OUTPUT_FORMAT("elf32-tradlittlemips")

configs/pic32-starterkit/ostest/defconfig

@@ -902,7 +902,7 @@ CONFIG_BOOT_RUNFROMFLASH=n
 CONFIG_BOOT_COPYTORAM=n
 CONFIG_CUSTOM_STACK=n
 CONFIG_STACK_POINTER=
-CONFIG_IDLETHREAD_STACKSIZE=1024
+CONFIG_IDLETHREAD_STACKSIZE=2048
 CONFIG_USERMAIN_STACKSIZE=2048
 CONFIG_PTHREAD_STACK_MIN=256
 CONFIG_PTHREAD_STACK_DEFAULT=2048

configs/pic32-starterkit/ostest/ld.script

@@ -60,7 +60,7 @@ MEMORY
 	 *   Debug code    0x1fc02000 KSEG1  4096-16   12272
 	 *   DEVCFG3-0     0x1fc02ff0 KSEG1  16        12288 (12Kb)
 	 *
-	 * Exceptions assme:
+	 * Exceptions assume:
 	 *
 	 *   STATUS: BEV=1 and EXL=0
 	 *   CAUSE:  IV=1
@@ -79,9 +79,12 @@ MEMORY
 	/* The PIC32MX795F512L has 128Kb of data memory at physical address
 	 * 0x00000000.  Since the PIC32MX has no data cache, this memory is
 	 * always accessed through KSEG1.
+	 *
+	 * When used with MPLAB, we need to set aside 512 bytes of memory
+	 * for use by MPLAB.
 	 */
 
-	kseg1_datamem (w!x) : ORIGIN = 0xa0000000, LENGTH = 128K
+	kseg1_datamem (w!x) : ORIGIN = 0xa0000200, LENGTH = 128K - 512
 }
 
 OUTPUT_FORMAT("elf32-tradlittlemips")

configs/stm3210e-eval/README.txt

@@ -12,6 +12,7 @@ Contents
   - IDEs
   - NuttX buildroot Toolchain
   - DFU and JTAG
+  - OpenOCD
   - LEDs
   - Temperature Sensor
   - RTC
@@ -238,6 +239,32 @@ DFU and JTAG
   The default setting (none of the above defined) is SWJ_CFG[2:0] set to 100
   which disable JTAG-DP and SW-DP.
 
+OpenOCD
+=======
+
+I have also used OpenOCD with the STM3210E-EVAL.  In this case, I used
+the Olimex USB ARM OCD.  See the script in configs/stm3210e-eval/tools/oocd.sh
+for more information.  Using the script:
+
+1) Start the OpenOCD GDB server
+
+   cd <nuttx-build-directory>
+   configs/stm3210e-eval/tools/oocd.sh $PWD
+
+2) Load Nuttx
+
+   cd <nuttx-built-directory>
+   arm-none-eabi-gdb nuttx
+   gdb> target remote localhost:3333
+   gdb> mon reset
+   gdb> mon halt
+   gdb> load nuttx
+
+3) Running NuttX
+
+   gdb> mon reset
+   gdb> c
+
 LEDs
 ====
 

configs/stm3210e-eval/tools/olimex-arm-usb-ocd.cfg

@@ -0,0 +1,11 @@
+#
+# Olimex ARM-USB-OCD
+#
+# http://www.olimex.com/dev/arm-usb-ocd.html
+#
+
+interface ft2232
+ft2232_device_desc "Olimex OpenOCD JTAG"
+ft2232_layout olimex-jtag
+ft2232_vid_pid 0x15ba 0x0003
+

configs/stm3210e-eval/tools/oocd.sh

@@ -0,0 +1,90 @@
+#!/bin/sh
+
+# Get command line parameters
+
+USAGE="USAGE: $0 [-dh] <TOPDIR>"
+ADVICE="Try '$0 -h' for more information"
+
+
+while [ ! -z "$1" ]; do
+	case $1 in
+	-d )
+		set -x
+		;;
+	-h )
+		echo "$0 is a tool for generation of proper version files for the NuttX build"
+		echo ""
+		echo $USAGE
+		echo ""
+		echo "Where:"
+		echo "  -d"
+		echo "	  Enable script debug"
+		echo "  -h"
+		echo "	  show this help message and exit"
+		echo "	  Use the OpenOCD 0.4.0"
+		echo "  <TOPDIR>"
+		echo "	  The full path to the top-level NuttX directory"
+		exit 0
+		;;
+	* )
+		break;
+		;;
+	esac
+	shift
+done
+
+TOPDIR=$1
+if [ -z "${TOPDIR}" ]; then
+	echo "Missing argument"
+	echo $USAGE
+	echo $ADVICE
+	exit 1
+fi
+
+# This script *probably* only works with the following versions of OpenOCD:
+
+# Local search directory and configurations
+
+OPENOCD_SEARCHDIR="${TOPDIR}/configs/stm3210e-eval/tools"
+OPENOCD_WSEARCHDIR="`cygpath -w ${OPENOCD_SEARCHDIR}`"
+
+OPENOCD_PATH="/cygdrive/c/Program Files (x86)/OpenOCD/0.4.0/bin"
+OPENOCD_EXE=openocd.exe
+OPENOCD_INTERFACE="olimex-arm-usb-ocd.cfg"
+
+
+OPENOCD_TARGET="stm32.cfg"
+OPENOCD_ARGS="-s ${OPENOCD_WSEARCHDIR} -f ${OPENOCD_INTERFACE} -f ${OPENOCD_TARGET}"
+
+echo "Trying OpenOCD 0.4.0 path: ${OPENOCD_PATH}/${OPENOCD_EXE}"
+
+# Verify that everything is what it claims it is and is located where it claims it is.
+
+if [ ! -x "${OPENOCD_PATH}/${OPENOCD_EXE}" ]; then
+	echo "OpenOCD executable does not exist: ${OPENOCD_PATH}/${OPENOCD_EXE}"
+	exit 1
+fi
+if [ ! -f "${OPENOCD_SEARCHDIR}/${OPENOCD_TARGET}" ]; then
+	echo "OpenOCD target config file does not exist: ${OPENOCD_SEARCHDIR}/${OPENOCD_TARGET}"
+	exit 1
+fi
+if [ ! -f "${OPENOCD_SEARCHDIR}/${OPENOCD_INTERFACE}" ]; then
+	echo "OpenOCD interface config file does not exist: ${OPENOCD_SEARCHDIR}/${OPENOCD_INTERFACE}"
+	exit 1
+fi
+
+# Enable debug if so requested
+
+if [ "X$2" = "X-d" ]; then
+	OPENOCD_ARGS=$OPENOCD_ARGS" -d3"
+	set -x
+fi
+
+# Okay... do it!
+
+echo "Starting OpenOCD"
+"${OPENOCD_PATH}/${OPENOCD_EXE}" ${OPENOCD_ARGS} &
+echo "OpenOCD daemon started"
+ps -ef | grep openocd
+echo "In GDB: target remote localhost:3333"
+

configs/stm3210e-eval/tools/stm32.cfg

@@ -0,0 +1,69 @@
+# script for stm32
+
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
+   set  _CHIPNAME stm32
+}
+
+if { [info exists ENDIAN] } {
+   set  _ENDIAN $ENDIAN
+} else {
+   set  _ENDIAN little
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 16kB
+if { [info exists WORKAREASIZE] } {
+   set  _WORKAREASIZE $WORKAREASIZE
+} else {
+   set  _WORKAREASIZE 0x4000
+}
+
+# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
+jtag_khz 1000
+
+jtag_nsrst_delay 100
+jtag_ntrst_delay 100
+
+#jtag scan chain
+if { [info exists CPUTAPID ] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+  # See STM Document RM0008
+  # Section 26.6.3
+   set _CPUTAPID 0x3ba00477
+}
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+if { [info exists BSTAPID ] } {
+   # FIXME this never gets used to override defaults...
+   set _BSTAPID $BSTAPID
+} else {
+  # See STM Document RM0008
+  # Section 29.6.2
+  # Low density devices, Rev A
+  set _BSTAPID1 0x06412041
+  # Medium density devices, Rev A
+  set _BSTAPID2 0x06410041
+  # Medium density devices, Rev B and Rev Z
+  set _BSTAPID3 0x16410041
+  # High density devices, Rev A
+  set _BSTAPID4 0x06414041
+  # Connectivity line devices, Rev A and Rev Z
+  set _BSTAPID5 0x06418041
+}
+jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 \
+	-expected-id $_BSTAPID2 -expected-id $_BSTAPID3 \
+	-expected-id $_BSTAPID4 -expected-id $_BSTAPID5
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stm32x 0 0 0 0 $_TARGETNAME
+
+# For more information about the configuration files, take a look at:
+# openocd.texi

configs/sure-pic32mx/ostest/defconfig

@@ -870,7 +870,7 @@ CONFIG_BOOT_RUNFROMFLASH=n
 CONFIG_BOOT_COPYTORAM=n
 CONFIG_CUSTOM_STACK=n
 CONFIG_STACK_POINTER=
-CONFIG_IDLETHREAD_STACKSIZE=1024
+CONFIG_IDLETHREAD_STACKSIZE=2048
 CONFIG_USERMAIN_STACKSIZE=2048
 CONFIG_PTHREAD_STACK_MIN=256
 CONFIG_PTHREAD_STACK_DEFAULT=2048

configs/sure-pic32mx/ostest/ld.script

@@ -60,7 +60,7 @@ MEMORY
 	 *   Debug code    0x1fc02000 KSEG1  4096-16   12272
 	 *   DEVCFG3-0     0x1fc02ff0 KSEG1  16        12288 (12Kb)
 	 *
-	 * Exceptions assme:
+	 * Exceptions assume:
 	 *
 	 *   STATUS: BEV=1 and EXL=0
 	 *   CAUSE:  IV=1
@@ -79,9 +79,12 @@ MEMORY
 	/* The PIC32MX440F512H has 32Kb of data memory at physical address
 	 * 0x00000000.  Since the PIC32MX has no data cache, this memory is
 	 * always accessed through KSEG1.
+	 *
+	 * When used with MPLAB, we need to set aside 512 bytes of memory
+	 * for use by MPLAB.
 	 */
 
-	kseg1_datamem (w!x) : ORIGIN = 0xa0000000, LENGTH = 32K
+	kseg1_datamem (w!x) : ORIGIN = 0xa0000200, LENGTH = 32K - 512
 }
 
 OUTPUT_FORMAT("elf32-tradlittlemips")