diff --git a/configs/nucleo-144/include/board.h b/configs/nucleo-144/include/board.h index b31d7b5a8b4..fe10e5ebdda 100644 --- a/configs/nucleo-144/include/board.h +++ b/configs/nucleo-144/include/board.h @@ -111,7 +111,7 @@ * * PLL_VCO = (8,000,000 / 4) * 216 = 432 MHz * SYSCLK = 432 MHz / 2 = 216 MHz - * USB OTG FS, SDMMC and RNG Clock = 432 MHz / 9 = 48MHz + * USB OTG FS, SDMMC and RNG Clock = 432 MHz / 9 = 48 MHz */ #define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(4) @@ -125,6 +125,7 @@ /* Configure factors for PLLSAI clock */ +#define CONFIG_STM32F7_PLLSAI 1 #define STM32_RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN(192) #define STM32_RCC_PLLSAICFGR_PLLSAIP RCC_PLLSAICFGR_PLLSAIP(2) #define STM32_RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ(2) @@ -132,16 +133,20 @@ /* Configure Dedicated Clock Configuration Register */ -#define STM32_RCC_DCKCFGR_PLLI2SDIVQ RCC_DCKCFGR_PLLI2SDIVQ(1) -#define STM32_RCC_DCKCFGR_PLLSAIDIVQ RCC_DCKCFGR_PLLSAIDIVQ(1) -#define STM32_RCC_DCKCFGR_SAI1SRC RCC_DCKCFGR_SAI1SRC_PLLSAI -#define STM32_RCC_DCKCFGR_SAI2SRC RCC_DCKCFGR_SAI2SRC_PLLSAI -#define STM32_RCC_DCKCFGR_TIMPRE 0 -#define STM32_RCC_DCKCFGR_I2S1SRC RCC_DCKCFGR_SAI1SRC_PLL -#define STM32_RCC_DCKCFGR_I2S2SRC RCC_DCKCFGR_SAI2SRC_PLL +#define STM32_RCC_DCKCFGR1_PLLI2SDIVQ RCC_DCKCFGR1_PLLI2SDIVQ(1) +#define STM32_RCC_DCKCFGR1_PLLSAIDIVQ RCC_DCKCFGR1_PLLSAIDIVQ(1) +#define STM32_RCC_DCKCFGR1_PLLSAIDIVR RCC_DCKCFGR1_PLLSAIDIVR(0) +#define STM32_RCC_DCKCFGR1_SAI1SRC RCC_DCKCFGR1_SAI1SEL(0) +#define STM32_RCC_DCKCFGR1_SAI2SRC RCC_DCKCFGR1_SAI2SEL(0) +#define STM32_RCC_DCKCFGR1_TIMPRESRC 0 +#define STM32_RCC_DCKCFGR1_DFSDM1SRC 0 +#define STM32_RCC_DCKCFGR1_ADFSDM1SRC 0 + + /* Configure factors for PLLI2S clock */ +#define CONFIG_STM32F7_PLLI2S 1 #define STM32_RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN(192) #define STM32_RCC_PLLI2SCFGR_PLLI2SP RCC_PLLI2SCFGR_PLLI2SP(2) #define STM32_RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ(2) @@ -149,11 +154,24 @@ /* Configure Dedicated Clock Configuration Register 2 */ -#define STM32_RCC_DCKCFGR2_FMPI2C1SEL RCC_DCKCFGR2_FMPI2C1SEL_APB -#define STM32_RCC_DCKCFGR2_CECSEL RCC_DCKCFGR2_CECSEL_HSI -#define STM32_RCC_DCKCFGR2_CK48MSEL RCC_DCKCFGR2_CK48MSEL_PLLSAI -#define STM32_RCC_DCKCFGR2_SDIOSEL RCC_DCKCFGR2_SDIOSEL_48MHZ -#define STM32_RCC_DCKCFGR2_SPDIFRXSEL RCC_DCKCFGR2_SPDIFRXSEL_PLL +#define STM32_RCC_DCKCFGR2_USART1SRC RCC_DCKCFGR2_USART1SEL_APB +#define STM32_RCC_DCKCFGR2_USART2SRC RCC_DCKCFGR2_USART2SEL_APB +#define STM32_RCC_DCKCFGR2_UART4SRC RCC_DCKCFGR2_UART4SEL_APB +#define STM32_RCC_DCKCFGR2_UART5SRC RCC_DCKCFGR2_UART5SEL_APB +#define STM32_RCC_DCKCFGR2_USART6SRC RCC_DCKCFGR2_USART6SEL_APB +#define STM32_RCC_DCKCFGR2_UART7SRC RCC_DCKCFGR2_UART7SEL_APB +#define STM32_RCC_DCKCFGR2_UART8SRC RCC_DCKCFGR2_UART8SEL_APB +#define STM32_RCC_DCKCFGR2_I2C1SRC RCC_DCKCFGR2_I2C1SEL_HSI +#define STM32_RCC_DCKCFGR2_I2C2SRC RCC_DCKCFGR2_I2C2SEL_HSI +#define STM32_RCC_DCKCFGR2_I2C3SRC RCC_DCKCFGR2_I2C3SEL_HSI +#define STM32_RCC_DCKCFGR2_I2C4SRC RCC_DCKCFGR2_I2C4SEL_HSI +#define STM32_RCC_DCKCFGR2_LPTIM1SRC RCC_DCKCFGR2_LPTIM1SEL_APB +#define STM32_RCC_DCKCFGR2_CECSRC RCC_DCKCFGR2_CECSEL_HSI +#define STM32_RCC_DCKCFGR2_CK48MSRC RCC_DCKCFGR2_CK48MSEL_PLLSAI +#define STM32_RCC_DCKCFGR2_SDMMCSRC RCC_DCKCFGR2_SDMMCSEL_48MHZ +#define STM32_RCC_DCKCFGR2_SDMMC2SRC RCC_DCKCFGR2_SDMMC2SEL_48MHZ +#define STM32_RCC_DCKCFGR2_DSISRC RCC_DCKCFGR2_DSISEL_48MHZ + /* Several prescalers allow the configuration of the two AHB buses, the * high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum @@ -321,17 +339,17 @@ /* SPI * * - * PA6 MISO CN12-13 - * PA7 MOSI CN12-15 - * PA5 SCK CN12-11 + * PA6 SPI1_MISO CN12-13 + * PA7 SPI1_MOSI CN12-15 + * PA5 SPI1_SCK CN12-11 * - * PB14 MISO CN12-28 - * PB15 MOSI CN12-26 - * PB10 SCK CN12-25 + * PB14 SPI2_MISO CN12-28 + * PB15 SPI2_MOSI CN12-26 + * PB13 SPI2_SCK CN12-30 * - * PB4 MISO CN12-27 - * PB5 MOSI CN12-29 - * PB3 SCK CN12-31 + * PB4 SPI3_MISO CN12-27 + * PB5 SPI3_MOSI CN12-29 + * PB3 SPI3_SCK CN12-31 */ #define GPIO_SPI1_MISO GPIO_SPI1_MISO_1 @@ -340,7 +358,7 @@ #define GPIO_SPI2_MISO GPIO_SPI2_MISO_1 #define GPIO_SPI2_MOSI GPIO_SPI2_MOSI_1 -#define GPIO_SPI2_SCK GPIO_SPI2_SCK_2 +#define GPIO_SPI2_SCK GPIO_SPI2_SCK_3 #define GPIO_SPI3_MISO GPIO_SPI3_MISO_1 #define GPIO_SPI3_MOSI GPIO_SPI3_MOSI_2 @@ -352,8 +370,8 @@ * PB8 I2C1_SCL CN12-3 * PB9 I2C1_SDA CN12-5 - * PF1 I2C2_SCL CN11-51 - * PF0 I2C2_SDA CN11-53 + * PB10 I2C2_SCL CN11-51 + * PB11 I2C2_SDA CN12-18 * * PA8 I2C3_SCL CN12-23 * PC9 I2C3_SDA CN12-1 @@ -363,8 +381,8 @@ #define GPIO_I2C1_SCL GPIO_I2C1_SCL_2 #define GPIO_I2C1_SDA GPIO_I2C1_SDA_2 -#define GPIO_I2C2_SCL GPIO_I2C2_SCL_2 -#define GPIO_I2C2_SDA GPIO_I2C2_SDA_2 +#define GPIO_I2C2_SCL GPIO_I2C2_SCL_1 +#define GPIO_I2C2_SDA GPIO_I2C2_SDA_1 #define GPIO_I2C3_SCL GPIO_I2C3_SCL_1 #define GPIO_I2C3_SDA GPIO_I2C3_SDA_1