diff --git a/arch/xtensa/src/common/xtensa_context.S b/arch/xtensa/src/common/xtensa_context.S
index 6bcab6a5018..37cdb796fdc 100644
--- a/arch/xtensa/src/common/xtensa_context.S
+++ b/arch/xtensa/src/common/xtensa_context.S
@@ -160,7 +160,7 @@ _xtensa_context_save:
 #endif
 
 #if XTENSA_EXTRA_SA_SIZE > 0 || !defined(CONFIG_XTENSA_CALL0_ABI)
-	mov		a9,  a0						/* Preserve ret addr */
+	mov		a9,  a0							/* Preserve ret addr */
 	#endif
 
 #ifndef CONFIG_XTENSA_CALL0_ABI
@@ -171,7 +171,7 @@ _xtensa_context_save:
 	 * disabled (assured by PS.EXCM == 1).
 	 */
 
-	s32i	a12, a2, (4 * REG_TMP0)		/* Temp. save stuff in stack frame */
+	s32i	a12, a2, (4 * REG_TMP0)			/* Temp. save stuff in stack frame */
 	s32i	a13, a2, (4 * REG_TMP1)
 	s32i	a9,  a2, (4 * REG_TMP2)
 
@@ -181,9 +181,9 @@ _xtensa_context_save:
 	 */
 
 #ifdef CONFIG_XTENSA_USE_OVLY
-	l32i	a9,  a2, (4 * REG_PC)		/* Recover saved PC */
+	l32i	a9,  a2, (4 * REG_PC)			/* Recover saved PC */
 	_xt_overlay_get_state	a9, a12, a13
-	s32i	a9,  a2, (4 * REG_OVLY)		/* Save overlay state */
+	s32i	a9,  a2, (4 * REG_OVLY)			/* Save overlay state */
 #endif
 
 	l32i	a12, a2, (4 * REG_A12)			/* Recover original a9,12,13 */
diff --git a/arch/xtensa/src/common/xtensa_inthandlers.S b/arch/xtensa/src/common/xtensa_inthandlers.S
index 817e458d507..32562b58344 100644
--- a/arch/xtensa/src/common/xtensa_inthandlers.S
+++ b/arch/xtensa/src/common/xtensa_inthandlers.S
@@ -167,12 +167,12 @@
 	l32i	a6, a3, 4					/* a6 = _xt_vpri_mask */
 	neg		a2, a2
 	addi	a2, a2, -1					/* a2 = mask to apply */
-	and		a5, a6, a2					/* mask off all bits <= a4 bit */
-	s32i	a5, a3, 4					/* update _xt_vpri_mask */
+	and		a5, a6, a2					/* Mask off all bits <= a4 bit */
+	s32i	a5, a3, 4					/* Update _xt_vpri_mask */
 	rsr		a3, INTENABLE
-	and		a3, a3, a2					/* mask off all bits <= a4 bit */
+	and		a3, a3, a2					/* Mask off all bits <= a4 bit */
 	wsr		a3, INTENABLE
-	rsil	a3, \level - 1				/* lower interrupt level by 1 */
+	rsil	a3, \level - 1				/* Lower interrupt level by 1 */
 #endif
 
 	movi	a3, XT_TIMER_INTEN			/* a3 = timer interrupt bit */
@@ -226,7 +226,7 @@
 #ifdef CONFIG_XTENSA_USE_SWPRI
 	j		8f
 #else
-	j		.L_xt_user_int_&level&		/* check for more interrupts */
+	j		.L_xt_user_int_&level&		/* Check for more interrupts */
 #endif
 
 #ifdef CONFIG_XTENSA_USE_SWPRI
@@ -237,9 +237,9 @@
 
 	movi	a3, _xt_intdata
 	l32i	a4, a3, 0					/* a4 = _xt_intenable */
-	s32i	a2, a3, 4					/* update _xt_vpri_mask */
+	s32i	a2, a3, 4					/* Update _xt_vpri_mask */
 	and		a4, a4, a2					/* a4 = masked intenable */
-	wsr		a4, INTENABLE				/* update INTENABLE */
+	wsr		a4, INTENABLE				/* Update INTENABLE */
 #endif
 
 9:
@@ -498,7 +498,7 @@ _xtensa_level5_handler:
 	 * ADD HIGH PRIORITY LEVEL 5 INTERRUPT HANDLER CODE HERE.
 	 */
 
-	rsr		a0, EXCSAVE_5				/* restore a0 */
+	rsr		a0, EXCSAVE_5				/* Restore a0 */
 	rfi		5
 
 #endif /* XCHAL_INT_NLEVELS >=5 && XCHAL_EXCM_LEVEL < 5 && XCHAL_DEBUGLEVEL !=5 */
diff --git a/arch/xtensa/src/common/xtensa_irq.S b/arch/xtensa/src/common/xtensa_irq.S
index d601d6d9ced..9244a42052b 100644
--- a/arch/xtensa/src/common/xtensa_irq.S
+++ b/arch/xtensa/src/common/xtensa_irq.S
@@ -30,6 +30,8 @@
  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  ****************************************************************************/
 
+	.file	"xtensa_irq.S"
+
 /****************************************************************************
  * Included Files
  ****************************************************************************/
diff --git a/arch/xtensa/src/esp32/Make.defs b/arch/xtensa/src/esp32/Make.defs
index c9f4ea0ae39..5ec3886f99e 100644
--- a/arch/xtensa/src/esp32/Make.defs
+++ b/arch/xtensa/src/esp32/Make.defs
@@ -80,7 +80,7 @@ CHIP_CSRCS  = esp32_allocateheap.c esp32_intdecode.c esp32_start.c
 # Configuration-dependent ESP32 files
 
 ifeq ($(CONFIG_SMP),y)
-#CMN_CSRCS += esp32_cpuindex.c esp32_cpustart.c esp32_cpupause.c
-#CMN_CSRCS += esp32_cpuidlestack.c
+CHIP_ASRCS  = esp32_cpuindex.S
+#CMN_CSRCS += esp32_cpustart.c esp32_cpupause.c esp32_cpuidlestack.c
 CMN_CSRCS += esp32_cpustart.c
 endif
diff --git a/arch/xtensa/src/esp32/esp32_cpuindex.S b/arch/xtensa/src/esp32/esp32_cpuindex.S
new file mode 100644
index 00000000000..0059f256e26
--- /dev/null
+++ b/arch/xtensa/src/esp32/esp32_cpuindex.S
@@ -0,0 +1,76 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32/exp32_cpuindex.S
+ *
+ *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+	.file	"xtensa_cpumacros.S"
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include "chip_macros.h"
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_cpu_index
+ *
+ * Description:
+ *   Return an index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
+ *   corresponds to the currently executing CPU.
+ *
+ *   If TLS is enabled, then the RTOS can get this information from the TLS
+ *   info structure.  Otherwise, the MCU-specific logic must provide some
+ *   mechanism to provide the CPU index.
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   An integer index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
+ *   corresponds to the currently executing CPU.
+ *
+ ****************************************************************************/
+
+	.text
+	.align	4
+	.global	up_cpu_index
+	.type	up_cpu_index, @function
+
+up_cpu_index:
+	getcoreid	a2
+	ret
+	.size	up_cpu_index, . - up_cpu_index