Merge remote-tracking branch 'origin/master' into ieee802154

2026-06-06 00:14:22 +08:00 · 2017-06-15 10:34:38 -06:00
parent 4a88d6a50a 1bb5a74035
commit 535ea4e0f5
130 changed files with 9903 additions and 783 deletions
@@ -8,7 +8,7 @@ Make.dep
 .swp
 .*.swp
 core
-.gdbinit
+/.gdbinit
 /cscope.*
 /.config
 /.config.old
@@ -24,5 +24,7 @@ core
 /*.bin
 /*.ihx
 /*.hex
+/.cproject
+/.project
 /pcode
 /tags
@@ -8,7 +8,7 @@
  <tr align="center" bgcolor="#e4e4e4">
    <td>
      <h1><big><font color="#3c34ec"><i>NuttShell (NSH)</i></font></big></h1>
-      <p>Last Updated: June 6, 2017</p>
+      <p>Last Updated: June 13, 2017</p>
    </td>
  </tr>
 </table>
@@ -305,7 +305,7 @@
 <tr>
  <td><br></td>
  <td>
-    <a href="#cmdmkfatfs">2.37 Create a FAT Filesystem (mkfatfs)</a>
+    <a href="#cmdmkfatfs">2.37 Create a FAT File System (mkfatfs)</a>
  </td>
 </tr>
 <tr>
@@ -335,7 +335,7 @@
 <tr>
  <td><br></td>
  <td>
-    <a href="#cmdnfsmount">2.42 Mount an NFS file system (nfsmount)</a>
+    <a href="#cmdnfsmount">2.42 Mount an NFS File System (nfsmount)</a>
  </td>
 </tr>
 <tr>
@@ -619,9 +619,35 @@
 NuttShell (NSH)
 nsh&gt;
 </pre></ul>
-  The greating may also include NuttX versioning information if you are using a versioned copy of NuttX.
+  The greeting may also include NuttX versioning information if you are using a versioned copy of NuttX.
  <code>nsh&gt;</code> is the NSH prompt and indicates that you may enter a command from the console.
 </p>
+<p>
+  <a name="usbstartup"><b>USB console startup</b></a>.
+  When using a USB console, the start-up sequence differs a little:  In this case, you are required to press <i>ENTER</i> three times.  Then NSH prompt will appear as described above.
+  This is required for the following reasons:
+</p>
+<ol>
+  <li>
+    This assures that the USB connection is stable.
+    The USB connection may be made, broken, and re-established a few times if the USB cable is not yet fully seated.
+    Waiting for <i>ENTER</i> to be pressed three times assures that the connection is stable.
+  </li>
+  <li>
+    The establishment of the connection is two step process:  First, the USB serial connection is made with the host PC.  Then the application that uses the serial interface is started on the host.
+    When the serial connection is established on the host, the host operating system may send several <i>AT</i> modem commands to the host depending upon how the host serial port is configured.
+    By waiting for <i>ENTER</i> to be pressed three consecutive times, all of these modem commands will go to the bit-bucket and will not be interpreted as NSH command input.
+  </li>
+  <li>
+    Similarly, in the second step when the applications is started, there may be additional <i>AT</i> modem commands sent out the serial port.
+    Most serial terminal programs will do this unless they are specifically configured to suppress the modem command output.
+    Waiting for the <i>ENTER</i> input eliminates the invalid command errors from both (2) and (3).
+  </li>
+  <li>
+    Finally, if NSH did not wait for some positive indication that the serial terminal program is up and running, then the output of the NSH greeting and initial NSH prompt would be lost.
+  </li>
+</ol>
+
 <p>
  <a name="cle"><b>Extended Command Line Editing</b></a>.
  By default, NuttX uses a simple command line editor that allows command entry after the <code>nsh&gt;</code> and supports only the <i>backspace</i> key for editing.
@@ -752,7 +778,7 @@ nsh&gt;
    <td><code>&lt;file&gt;</code></td>
    <td>
      is the full or relative path to any writable object
-      in the filesystem name space (file or character driver).
+      in the file system name space (file or character driver).
      Such objects will be referred to simply as files throughout
      this document.
    </td>
@@ -968,7 +994,7 @@ done
  <ul>
    <li>
      NSH will create a read-only RAM disk (a ROM disk), containing a tiny
-      ROMFS filesystem containing the following:
+      ROMFS file system containing the following:
 <ul><pre>
 `--init.d/
     `-- rcS
@@ -976,7 +1002,7 @@ done
      Where rcS is the NSH start-up script.
    </li>
    <li>
-      NSH will then mount the ROMFS filesystem at <code>/etc</code>, resulting in:
+      NSH will then mount the ROMFS file system at <code>/etc</code>, resulting in:
 <ul><pre>
 |--dev/
 |   `-- ram0
@@ -1352,7 +1378,7 @@ cp &lt;source-path&gt; &lt;dest-path&gt;
 <p>
  <b>Synopsis</b>.
  Copy of the contents of the file at <code>&lt;source-path&gt;</code> to the location
-  in the filesystem indicated by <code>&lt;dest-path&gt;</code>.
+  in the file system indicated by <code>&lt;dest-path&gt;</code>.
 </p>

 <table width ="100%">
@@ -1726,7 +1752,7 @@ ifconfig [nic_name [&lt;ip-address&gt;|dhcp]] [dr|gw|gateway &lt;dr-address&gt;]
  <li>
    <p>
      With one or no arguments, <code>ifconfig</code> will shows the
-      current configuration of the network and, perhaps, the status of ethernet
+      current configuration of the network and, perhaps, the status of Ethernet
      device:
    </p>
    <ul><pre>
@@ -1749,7 +1775,7 @@ eth0    HWaddr 00:18:11:80:10:06
  <li>
    <p>
      If both the network interface name and an IP address are supplied as arguments,
-      then <code>ifconfig</code> will set the address of the ethernet device:
+      then <code>ifconfig</code> will set the address of the Ethernet device:
    </p>
    <ul><pre>
 ifconfig nic_name ip_address
@@ -1970,7 +1996,7 @@ ln [-s] &lt;target&gt; &lt;link&gt;
  This implementation is simplified for use with NuttX in these ways:
 </p>
 <ul>
-    <li>Links may be created only within the NuttX top-level, <a href="NuttxUserGuide.html#FileSystemOverview"><i>pseudo</i> filesystem</a>.
+    <li>Links may be created only within the NuttX top-level, <a href="NuttxUserGuide.html#FileSystemOverview"><i>pseudo</i> file system</a>.
        No file system currently supported by NuttX provides symbolic links.</li>
    <li>For the same reason, only soft links are implemented.</li>
    <li>File privileges are ignored.</li>
@@ -1992,7 +2018,7 @@ ls [-lRs] &lt;dir-path&gt;
 <p>
  <b>Synopsis</b>.
  Show the contents of the directory at <code>&lt;dir-path&gt;</code>.  NOTE:
-  <code>&lt;dir-path&gt;</code> must refer to a directory and no other filesystem
+  <code>&lt;dir-path&gt;</code> must refer to a directory and no other file system
  object.
 </p>
 <p><b>Options:</b></p>
@@ -2172,10 +2198,10 @@ mkdir &lt;path&gt;
 </p>
 <p>
  <b>Limited to Mounted File Systems</b>.
-  Recall that NuttX uses a <a href="NuttxUserGuide.html#FileSystemOverview"><i>pseudo</i> filesystem</a> for its root file
+  Recall that NuttX uses a <a href="NuttxUserGuide.html#FileSystemOverview"><i>pseudo</i> file system</a> for its root file
  system.
  The <code>mkdir</code> command can only be used to create directories in volumes set up with the
-  <a href="#cmdmount"><code>mount</code></a> command; it cannot be used to create directories in the <i>pseudo</i> filesystem.
+  <a href="#cmdmount"><code>mount</code></a> command; it cannot be used to create directories in the <i>pseudo</i> file system.
 </p>
 <p><b>Example:</b></p>
 <ul><pre>
@@ -2190,7 +2216,7 @@ nsh&gt;
 <table width ="100%">
  <tr bgcolor="#e4e4e4">
  <td>
-    <a name="cmdmkfatfs"><h2>2.37 Create a FAT Filesystem (mkfatfs)</h2></a>
+    <a name="cmdmkfatfs"><h2>2.37 Create a FAT File System (mkfatfs)</h2></a>
  </td>
 </tr>
 </table>
@@ -2208,7 +2234,7 @@ mkfatfs [-F &lt;fatsize&gt;] &lt;block-driver&gt;
 </p>
 <p>
  NSH provides this command to access the <a href="mkfatfs"><code>mkfatfs()</code></a> NuttX API.
-  This block device must reside in the NuttX <a href="NuttxUserGuide.html#FileSystemOverview"><i>pseudo</i> filesystem</a> and
+  This block device must reside in the NuttX <a href="NuttxUserGuide.html#FileSystemOverview"><i>pseudo</i> file system</a> and
  must have been created by some call to <code>register_blockdriver()</code> (see <code>include/nuttx/fs/fs.h</code>).
 </p>

@@ -2323,22 +2349,22 @@ mount -t &lt;fstype&gt; [-o &lt;options&gt;] &lt;block-device&gt; <code>&lt;dir-
  <code>mount</code> performs a three way association, binding:
 </p>
 <ol>
-  <li><b>File system.</b>
+  <li><b>File System.</b>
    The '-t <code>&lt;fstype&gt;</code>' option identifies the type of
    file system that has been formatted on the <code>&lt;block-device&gt;</code>.
    As of this writing, <code>vfat</code> is the only supported value for <code>&lt;fstype&gt;</code>
  </li>
  <li><b>Block Device.</b>
    The <code>&lt;block-device&gt;</code> argument is the full or relative
-    path to a block driver inode in the <a href="NuttxUserGuide.html#FileSystemOverview"><i>pseudo</i> filesystem</a>.
+    path to a block driver inode in the <a href="NuttxUserGuide.html#FileSystemOverview"><i>pseudo</i> file system</a>.
    By convention, this is a name under the <code>/dev</code> sub-directory.
    This <code>&lt;block-device&gt;</code>  must have been previously formatted with the same file system
    type as specified by <code>&lt;fstype&gt;</code>
  </li>
  <li><b>Mount Point.</b>
    The mount point, <code>&lt;dir-path&gt;</code>, is the location in the
-    <a href="NuttxUserGuide.html#FileSystemOverview"><i>pseudo</i> filesystem</a> where the mounted volume will appear.
-    This mount point can only reside in the NuttX <a href="NuttxUserGuide.html#FileSystemOverview"><i>pseudo</i> filesystem</a>.
+    <a href="NuttxUserGuide.html#FileSystemOverview"><i>pseudo</i> file system</a> where the mounted volume will appear.
+    This mount point can only reside in the NuttX <a href="NuttxUserGuide.html#FileSystemOverview"><i>pseudo</i> file system</a>.
    By convention, this mount point is a subdirectory under <code>/mnt</code>.
    The mount command will create whatever pseudo directories that may be needed to complete the
    full path but the full path must not already exist.
@@ -2346,7 +2372,7 @@ mount -t &lt;fstype&gt; [-o &lt;options&gt;] &lt;block-device&gt; <code>&lt;dir-
 </ol>
 <p>
  After the volume has been mounted in the NuttX
-  <a href="NuttxUserGuide.html#FileSystemOverview"><i>pseudo</i> filesystem</a>,
+  <a href="NuttxUserGuide.html#FileSystemOverview"><i>pseudo</i> file system</a>,
  it may be access in the same way as other objects in the file system.
 </p>
 <p><b>Examples</b>:</p>
@@ -2395,7 +2421,7 @@ mv &lt;old-path&gt; &lt;new-path&gt;
 <p>
  <b>Synopsis</b>.
  Rename the file object at <code>&lt;old-path&gt;</code> to <code>&lt;new-path&gt;</code>.
-  Both paths must reside in the same mounted filesystem.
+  Both paths must reside in the same mounted file system.
 </p>

 <table width ="100%">
@@ -2628,11 +2654,11 @@ rm &lt;file-path&gt;
 <p>
  <b>Synopsis</b>.
  Remove the specified <code>&lt;file-path&gt;</code> name from the mounted file system.
-  Recall that NuttX uses a <a href="NuttxUserGuide.html#FileSystemOverview"><i>pseudo</i> filesystem</a> for its root file
+  Recall that NuttX uses a <a href="NuttxUserGuide.html#FileSystemOverview"><i>pseudo</i> file system</a> for its root file
  system.
  The <code>rm</code> command can only be used to remove (unlink) files in volumes set up with the
  <a href="#cmdmount"><code>mount</code></a> command;
-  it cannot be used to remove names in the <i>pseudo</i> filesystem.
+  it cannot be used to remove names in the <i>pseudo</i> file system.
 </p>
 <p><b>Example:</b></p>
 <ul><pre>
@@ -2662,11 +2688,11 @@ rmdir &lt;dir-path&gt;
 <p>
  <b>Synopsis</b>.
  Remove the specified <code>&lt;dir-path&gt;</code> directory from the mounted file system.
-  Recall that NuttX uses a <a href="NuttxUserGuide.html#FileSystemOverview"><i>pseudo</i> filesystem</a> for its root file
+  Recall that NuttX uses a <a href="NuttxUserGuide.html#FileSystemOverview"><i>pseudo</i> file system</a> for its root file
  system.
  The <code>rmdir</code> command can only be used to remove directories from volumes set up with the
  <a href="#cmdmount"><code>mount</code></a> command;
-  it cannot be used to remove directories from the <i>pseudo</i> filesystem.
+  it cannot be used to remove directories from the <i>pseudo</i> file system.
 </p>
 <p><b>Example:</b></p>
 <ul><pre>
@@ -3563,11 +3589,11 @@ nsh&gt;
  creation of files for the correct operation of the <code>put</code> command.</small><br>
  <sup>3</sup><small>
  <code>CONFIG_FS_READABLE</code> is not a user configuration but is set automatically
-  if any readable filesystem is selected.  At present, this is either <code>CONFIG_FS_FAT</code>
+  if any readable file system is selected.  At present, this is either <code>CONFIG_FS_FAT</code>
  or <code>CONFIG_FS_ROMFS</code>.</small><br>
  <sup>4</sup><small>
  <code>CONFIG_FS_WRITABLE</code> is not a user configuration but is set automatically
-  if any writable filesystem is selected.  At present, this is only <code>CONFIG_FS_FAT</code>.</small><br>
+  if any writable file system is selected.  At present, this is only <code>CONFIG_FS_FAT</code>.</small><br>
  <sup>5</sup><small>
  Verbose help output can be suppressed by defining <code>CONFIG_NSH_HELP_TERSE</code>.
  In that case, the help command is still available but will be slightly smaller.
@@ -3625,7 +3651,7 @@ nsh&gt;
    <td valign="top"><b><code>CONFIG_NSH_FILEIOSIZE</code></b></td>
    <td>
      Size of a static I/O buffer used for file access (ignored if
-      there is no filesystem). Default is 1024.
+      there is no file system). Default is 1024.
    </td>
  </tr>
  <tr>
@@ -3698,7 +3724,7 @@ set FOOBAR ABC_${FOO}_${BAR}
    <td valign="top"><b><code>CONFIG_NSH_NESTDEPTH</code></b></td>
    <td>
      The maximum number of nested <a href="#conditional"><code>if-then[-else]-fi</code></a> sequences that
-      are permissable.  Default: 3
+      are permissible.  Default: 3
    </td>
  </tr>
  <tr>
@@ -3746,7 +3772,7 @@ set FOOBAR ABC_${FOO}_${BAR}
  <tr>
    <td valign="top"><b><code>CONFIG_NSH_ROMFSETC</code></b></td>
    <td>
-      Mount a ROMFS filesystem at <code>/etc</code> and provide a startup script
+      Mount a ROMFS file system at <code>/etc</code> and provide a startup script
      at <code>/etc/init.d/rcS</code>.  The default startup script will mount
      a FAT FS RAMDISK at <code>/tmp</code> but the logic is
      <a href="#startupscript">easily extensible</a>.
@@ -3975,7 +4001,7 @@ set FOOBAR ABC_${FOO}_${BAR}
  <tr>
    <td valign="top"><b><code>CONFIG_NSH_NOMAC</code></b></td>
    <td>
-      Set if your ethernet hardware has no built-in MAC address.
+      Set if your Ethernet hardware has no built-in MAC address.
      If set, a bogus MAC will be assigned.
    </td>
  </tr>
@@ -4248,7 +4274,7 @@ mount -t vfat /dev/ram1 /tmp
      </p>
    <li>
      <p>
-        Mount the  FAT filesystem at a configured mountpoint, <code>/tmp</code>.
+        Mount the  FAT file system at a configured mountpoint, <code>/tmp</code>.
      </p>
    </ul>
    <p>
@@ -4666,7 +4692,7 @@ CONFIG_SCHED_WAITPID=y
    <p>
      You replace the sample code at <code>apps/examples/nsh/nsh_main.c</code> with whatever start-up logic that you want.
      NSH is a library at <code>apps/nshlib</code>.
-      <code>apps.examplex/nsh</code> is just a tiny, example start-up function (<code>CONFIG_USER_ENTRYPOINT</code>()) that that runs immediately and illustrates how to start NSH
+      <code>apps.examples/nsh</code> is just a tiny, example start-up function (<code>CONFIG_USER_ENTRYPOINT</code>()) that that runs immediately and illustrates how to start NSH
      If you want something else to run immediately then you can write your write your own custom <code>CONFIG_USER_ENTRYPOINT</code>() function and then start other tasks from your custom <code>CONFIG_USER_ENTRYPOINT</code>().
    </p>
  <li>
@@ -4723,7 +4749,7 @@ CONFIG_SCHED_WAITPID=y
 <ul>
  <li>
    <p>
-      NSH will create a read-only RAM disk (a ROM disk), containing a tiny ROMFS filesystem containing the following:
+      NSH will create a read-only RAM disk (a ROM disk), containing a tiny ROMFS file system containing the following:
    </p>
 <ul><pre>
 `--init.d/
@@ -4734,7 +4760,7 @@ CONFIG_SCHED_WAITPID=y
    </p>
  <li>
    <p>
-      NSH will then mount the ROMFS filesystem at <code>/etc</code>, resulting in:
+      NSH will then mount the ROMFS file system at <code>/etc</code>, resulting in:
    </p>
 <ul><pre>
 |--dev/
@@ -4841,7 +4867,7 @@ mount -t vfat /dev/ram1 /tmp
    </p>
    <p>
       To generate a custom <code>rcS</code> file a copy of <code>rcS.template</code> needs to be placed at <code>tools/</code> and changed according to the desired start-up behaviour.
-       Running <code>tools/mkromfsimg.h</code> creates <code>nsh_romfsimg.h</code> which needs to be copied to <code>apps/nhslib</code> OR if <code>CONFIG_NSH_ARCHROMFS</code> is defined to <code>configs/&lt;board&gt;/include</code>.
+       Running <code>tools/mkromfsimg.h</code> creates <code>nsh_romfsimg.h</code> which needs to be copied to <code>apps/nshlib</code> OR if <code>CONFIG_NSH_ARCHROMFS</code> is defined to <code>configs/&lt;board&gt;/include</code>.
    </p>
 </ol>

@@ -5343,10 +5369,10 @@ xxd -i romfs_img >nsh_romfsimg.h
  <li><a href="#cmdmkrd"><code>mkrd</code></a></li>
  <li><a href="#custinit"><code>mkromfsimg.sh</code></a></li>
  <li><a href="#cmdmount"><code>mount</code></a></li>
+  <li><a href="#cmdmv"><code>mv</code></a></li>
 </ul></td>
 <td width="34%" valign="top">
 <ul>
-  <li><a href="#cmdmv"><code>mv</code></a></li>
  <li><a href="#cmdnfsmount"><code>nfsmount</code></a></li>
  <li><a href="#cmdoverview"><code>nice</code></a></li>
  <li><a href="#custonshlib">NSH library (<code>nshlib</code>)</a></li>
@@ -5403,6 +5429,7 @@ xxd -i romfs_img >nsh_romfsimg.h
  <li><a href="#custonshlib"><code>up_cxxinitialize()</code></a></li>
  <li><a href="#cmdurldec"><code>urldecode</code></a></li>
  <li><a href="#cmdurlencode"><code>urlencode</code></a></li>
+  <li><a href="#usbstartup">USB console startup</a></li>
  <li><a href="#cmduseradd"><code>useradd</code></a></li>
  <li><a href="#cmduserdel"><code>userdel</code></a></li>
  <li><a href="#cmdusleep"><code>usleep</code></a></li>
@@ -12,7 +12,7 @@
      <h1><big><font color="#3c34ec">
        <i>NuttX C Coding Standard</i>
      </font></big></h1>
-      <p>Last Updated: May 6, 2017</p>
+      <p>Last Updated: June 11, 2017</p>
    </td>
  </tr>
 </table>
@@ -736,12 +736,25 @@ void some_function(void)
 <ul>
  <li>
    <b>Always on Separate Lines</b>.
-    Braces always appear on a separate line containing nothing else other that white space.
+    Braces always appear on a separate line containing nothing else other than white space.
  </li>
  <li>
    <b>Never Comments on Braces</b>.
    Do not put comments on the same line as braces.
  </li>
+  <li>
+    <b>Compound Statements</b>.
+    Within this document, an opening left brace followed by a sequence of statments, and ending with a closing right brace is refered to as a <i>compound statement</i>.
+  </li>
+  <li>
+    <b>Nested Compound Statements</b>.
+    In the case where there are nested compound statements that end with several consecutive right braces, each closing right brace must lie on a separate line and must be indented to match the corresponding opening brace.
+  </li>
+  <li>
+    <b>Final brace followed by a single blank line</b>.
+    The <i>final</i> right brace must be followed by a blank line as per standard rules.
+    In the case where there are nested several consecutive right braces, no blank lines should be inserted except for after the <i>final</i> right brace.
+  </li>
  <li>
    <b>Special Indentation Rules</b>.
    Special <a href="#indentation">indentation rules</a> apply to braces.
@@ -763,6 +776,19 @@ while (true)
      ...
      } /* not valid */
  } /* end forever */
+if (a < b) {
+  if (a < 0) {
+      c = -a;
+  } else {
+      c = a;
+  }
+} else {
+  if (b < 0) {
+      c = -b;
+  } else {
+      c = b;
+  }
+}
 </ul></pre></font>
 </td></tr>
 <tr><td bgcolor="white">
@@ -779,12 +805,36 @@ while (true)
      ...
      }
  }
+
+if (a < b)
+  {
+    if (a < 0)
+      {
+        c = -a;
+      }
+    else
+      {
+        c = a;
+      }
+  }
+else
+  {
+    if (b < 0)
+      {
+        c = -b;
+      }
+    else
+      {
+        c = b;
+      }
+  }
+
 </ul></pre></font>
 </td></tr>
 </table></center>

 <p>
-  <b>Exceptions</b>.
+  <b>Exception to Indentation Rule for Braces</b>.
  The exception is braces that following structure, enumeration, union, and function declarations.
  There is no additional indentation for those braces;
  those braces align with the beginning of the definition
@@ -854,6 +904,7 @@ int animals(int animal)
 {
  ...
 }
+
 </ul></pre></font>
 </td></tr>
 </table></center>
@@ -2099,12 +2150,24 @@ x++;
 </td></tr>
 </table></center>

+<p>
+  <b>Forbidden Multicharacter Forms</b>.
+  Many operators are expressed as a character in combination with <code>=</code> such as <code>+=</code>, <code>>=</code>, <code>>>=</code>, etc.
+  Some compilers will accept the <code>=</code> at the beginning or the end of the sequence.
+  This standard, however, requires that the <code>=</code> always appear last in order to avoid amiguities that may arise if the <code>=</code> were to appear first.  For example, <code>a =++ b;</code> could also be interpreted as <code>a =+ +b;</code> or <code>a = ++b</code> all of which are very different.
+</p>
+
 <p>
 <h2>4.4 <a name="ifthenelse"></a><code>if then else</code> Statement</h2>

 <p><b>Coding Standard:</b></p>
 <ul>
  <li>
+    <b><code>if</code> separated from <code>&lt;condition&gt;</code></b>.
+    The <code>if</code> keyword and the <code>&lt;condition&gt;</code> must appear on the same line.
+    The <code>if</code> keyword and the <code>&lt;condition&gt;</code> must be separated by a single space.
+  </li>
+  </li>
    <b>Keywords on separate lines</b>.
    <code>if &lt;condition&gt;</code> and <code>else</code> must lie on separate lines with nothing else present on the line.
  </li>
@@ -2118,16 +2181,24 @@ x++;
  </li>
  <li>
    <b>Statement(s) always enclosed in braces</b>.
-    Statement(s) following the <code>if &lt;condition&gt;</code> and <code>else</code> lines must always be enclosed in braces.
-    Braces must follow the <code>if &lt;condition&gt;</code> and <code>else</code> lines even in the case where these is no contained statement!
+    Statement(s) following the <code>if &lt;condition&gt;</code> and <code>else</code> keywords must always be enclosed in braces.
+    Braces must follow the <code>if &lt;condition&gt;</code> and <code>else</code> lines even in the cases where (a) there is no contained statement or (b) there is only a single statement!
  </li>
  <li>
    <b>Braces and indentation</b>.
-    The placement of braces and statements must follow the standard rules for braces and indentation.
+    The placement of braces and statements must follow the standard rules for <a href="#braces">braces and indentation</a>.
  </li>
  <li>
-    <b>Followed by a single blank line</b>.
-    The final right brace must be followed by a blank line.
+    <b>Final brace followed by a single blank line</b>.
+    The <i>final</i> right brace of the <code>if</code>-<code>else</code> must be followed by a blank line in most cases (the exception given below).
+    This may be the final brace of the <code>if</code> compound statement if the <code>else</code> keyword is not present.
+    Or it may be the the final brace of the <code>else</code> compound statement if present.
+    A blank line never follows the right brace closing the <code>if</code> compound statement if the <code>else</code> keyword is present.
+    Use of braces must follow all other standard rules for <a href="#braces">braces and spacing</a>.
+  </li>
+  <li>
+    <b>Exception</b>.
+    That blank line must also be omitted for certain cases where the <code>if &lt;condition&gt;</code>-<code>else</code> statement is nested within another compound statement; there should be no blank lines between consecutive right braces as discussed in the standard rules for use of <a href="#braces">braces</a>.
  </li>
 </ul>
 <p>
@@ -2221,6 +2292,11 @@ x++;

 <p><b>Coding Standard:</b></p>
 <ul>
+  <li>
+    <b><code>switch</code> separated from <code>&lt;value&gt;</code></b>.
+    The <code>switch</code> keyword and the switch <code>&lt;value&gt;</code> must appear on the same line.
+    The <code>if</code> keyword and the <code>&lt;value&gt;</code> must be separated by a single space.
+  </li>
  <li>
    <b>Falling through</b>.
    Falling through a case statement into the next case statement is be permitted as long as a comment is included.
@@ -2239,6 +2315,14 @@ x++;
    <code>break</code> statements are normally indented by two spaces.
    When used conditionally with case logic, the placement of the break statement follows normal indentation rules.
  </li>
+  <li>
+    <b>Followed by a single blank line</b>.
+    The final right brace that closes the <code>switch &lt;value&gt;</code> statement must be followed by a single blank line.
+  </li>
+  <li>
+    <b>Exception</b>.
+    That blank line must be omitted for certain cases where the <code>switch &lt;value&gt;</code> statement is nested within another compound statement; there should be no blank lines between consecutive right braces as discussed in the standard rules for use of <a href="#braces">braces</a>.
+  </li>
 </ul>
 <p>
  <b>Other Applicable Coding Standards</b>.
@@ -2274,6 +2358,11 @@ x++;
 <h2>4.6 <a name="while"><code>while</code> Statement</a></h2>
 <p><b>Coding Standard:</b></p>
 <ul>
+  <li>
+    <b><code>while</code> separated from <code>&lt;condition&gt;</code></b>.
+    The <code>while</code> keyword and the <code>&lt;condition&gt;</code> must appear on the same line.
+    The <code>while</code> keyword and the <code>&lt;condition&gt;</code> must be separated by a single space.
+  </li>
  <li>
    <b>Keywords on separate lines</b>.
    <code>while &lt;condition&gt;</code> must lie on a separate line with nothing else present on the line.
@@ -2297,7 +2386,11 @@ x++;
  </li>
  <li>
    <b>Followed by a single blank line</b>.
-    The final right brace must be followed by a blank line.
+    The final right brace that closes the <code>while &lt;condition&gt;</code> statment must be followed by a single blank line.
+  </li>
+  <li>
+    <b>Exception</b>.
+    That blank line must be omitted for certain cases where the <code>while &lt;condition&gt;</code> statement is nested within another compound statement; there should be no blank lines between consecutive right braces as discussed in the standard rules for use of <a href="#braces">braces</a>.
  </li>
 </ul>
 <p>
@@ -2345,15 +2438,20 @@ x++;
  </li>
  <li>
    <b>Statements enclosed in braces</b>
-    Statement(s) following the <code>do</code> must always be enclosed in braces, even if only a single statement follows.
+    Statement(s) following the <code>do</code> must always be enclosed in braces, even if only a single statement (or no statement) follows.
  </li>
  <li>
    <b>Braces and indentation</b>.
    The placement of braces and statements must follow the standard rules for braces and indentation.
  </li>
+  <li>
+    <b><code>while</code> separated from <code>&lt;condition&gt;</code></b>.
+    The <code>while</code> keyword and the <code>&lt;condition&gt;</code> must appear on the same line.
+    The <code>while</code> keyword and the <code>&lt;condition&gt;</code> must be separated by a single space.
+  </li>
  <li>
    <b>Followed by a single blank line</b>.
-    The final right brace must be followed by a blank line.
+    The concluding <code>while &lt;condition&gt;</code> must be followed by a single blank line.
  </li>
 </ul>
 <p>
@@ -2388,6 +2486,7 @@ x++;
      ptr++;
    }
  while (*ptr != '\0');
+
 </ul></pre></font>
 </td></tr>
 </table></center>
@@ -8,7 +8,7 @@
  <tr align="center" bgcolor="#e4e4e4">
    <td>
      <h1><big><font color="#3c34ec"><i>NuttX README Files</i></font></big></h1>
-      <p>Last Updated: May 9, 2017</p>
+      <p>Last Updated: June 10, 2017</p>
    </td>
  </tr>
 </table>
@@ -62,6 +62,8 @@ nuttx/
 |   |   `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/arduino-due/README.txt" target="_blank"><b><i>README.txt</i></b></a>
 |   |- avr32dev1/
 |   |   `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/avr32dev1/README.txt" target="_blank"><b><i>README.txt</i></b></a>
+ |   |- b-l475e-iot01a/
+ |   |   `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/b-l475e-iot01a/README.txt" target="_blank"><b><i>README.txt</i></b></a>
 |   |- bambino-200e/
 |   |   `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/bambino-200e/README.txt" target="_blank"><b><i>README.txt</i></b></a>
 |   |- c5471evm/
@@ -556,6 +556,9 @@ clean: subdir_clean
 	$(call DELFILE, _SAVED_APPS_config)
 	$(call DELFILE, nuttx-export*)
 	$(call DELFILE, nuttx_user*)
+	$(call DELFILE, .gdbinit)
+	$(call DELFILE, .cproject)
+	$(call DELFILE, .project)
 	$(call CLEAN)

 subdir_distclean:
@@ -538,6 +538,9 @@ clean: subdir_clean
 	$(call DELFILE, _SAVED_APPS_config)
 	$(call DELFILE, nuttx-export*)
 	$(call DELFILE, nuttx_user*)
+	$(call DELFILE, .gdbinit)
+	$(call DELFILE, .cproject)
+	$(call DELFILE, .project)
 	$(call CLEAN)

 subdir_distclean:
@@ -583,13 +583,18 @@ Instantiating "Canned" Configurations
      included in the build and what is not.  This file is also used
      to generate a C configuration header at include/nuttx/config.h.

+   Copy other, environment-specic files to ${TOPDIR
+
+      This might include files like .gdbinit or IDE configuration files
+      like .project or .cproject.
+
   General information about configuring NuttX can be found in:

      ${TOPDIR}/configs/README.txt
      ${TOPDIR}/configs/<board-name>/README.txt

-    There is a configuration script in the tools/ directory that makes this
-    easier.  It is used as follows:
+    There is a configuration script in the tools/ directory that makes does
+    all of the above steps for you.  It is used as follows:

      cd ${TOPDIR}/tools
      ./configure.sh <board-name>/<config-dir>
@@ -600,6 +605,10 @@ Instantiating "Canned" Configurations
      cd ${TOPDIR}\tools
      configure.bat <board-name>\<config-dir>

+    And, to make sure that other platform is supported, there is also a
+    C program at tools/configure.c that can be compiled to establish the
+    board configuration.
+
    See tools/README.txt for more information about these scripts.

 Refreshing Configurations
@@ -1462,6 +1471,8 @@ nuttx/
 |   |   `- README.txt
 |   |- avr32dev1/
 |   |   `- README.txt
+ |   |- b-l475e-iot01a/
+ |   |   `- README.txt
 |   |- bambino-200e/
 |   |   `- README.txt
 |   |- c5471evm/
@@ -1,4 +1,4 @@
-NuttX TODO List (Last updated May 31, 2017)
+NuttX TODO List (Last updated June 14, 2017)
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

 This file summarizes known NuttX bugs, limitations, inconsistencies with
@@ -234,6 +234,33 @@ o Task/Scheduler (sched/)
               could be improved and made a little more efficient with this
               change.

+  Title:       INAPPROPRIATE USE OF sched_lock() BY pthreads
+  Description: In implementation of standard pthread functions, the non-
+               standard, NuttX function sched_lock() is used.  This is very
+               strong sense it disables pre-emption for all threads in all
+               task groups.  I believe it is only really necessary in most
+               cases to lock threads in the task group with a new non-
+               standard interface, say pthread_lock().
+
+               This is because the OS resources used by a thread such as
+               mutexes, condition variable, barriers, etc. are only
+               meaningful from within the task group.  So, in order to
+               performance exclusive operations on these resources, it is
+               only necessary to block other threads executing within the
+               task group.
+
+               This is an easy change:  pthread_lock() and pthread_unlock()
+               would simply operate on a semaphore retained in the task
+               group structure.  I am, however, hesitant to make this change:
+               I the flat build model, there is nothing that prevents people
+               from accessing the inter-thread controls from threads in
+               differnt task groups.  Making this change, while correct,
+               might introduce subtle bugs in code by people who are not
+               using NuttX correctly.
+  Status:      Open
+  Priority:    Low.  This change would improve real-time performance of the
+               OS but is not otherwise required.
+
 o SMP
  ^^^

@@ -397,7 +397,7 @@ config ARCH_CORTEXR5
 	select ARCH_HAVE_MPU
 	select ARCH_HAVE_COHERENT_DCACHE if ELF || MODULE

-config ARCH_CORTEX5F
+config ARCH_CORTEXR5F
 	bool
 	default n
 	select ARCH_HAVE_MPU
@@ -1,8 +1,10 @@
 /************************************************************************************
 * arch/arm/include/stm32l4/chip.h
 *
+ *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
 *   Copyright (C) 2016 Sebastien Lorquet. All rights reserved.
 *   Author: Sebastien Lorquet <sebastien@lorquet.fr>
+ *           Gregory Nutt <gnutt@nuttx.org>
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
@@ -45,9 +47,11 @@
 /************************************************************************************
 * Pre-processor Definitions
 ************************************************************************************/
-/* STM32L476, STM32L486, STM32L496, STM32L4A6
+/* STM32L475, STM32L476, STM32L486, STM32L496, STM32L4A6
 *
 * Differences between family members:
+ *  - L475 has no TSC, no LCD, no AES, no I2C4, no CAN2, No Hash/CRS, no DCMI,
+ *    no DMA2D
 *  - L486 has AES
 *  - L496, L4A6 has 320 Kib SRAM, 2xCAN and CameraIF. Most (all?) of these have I2C4.
 *  - L4A6 has AES and HASH
@@ -55,6 +59,8 @@
 *   ----------- ---------------- ----- ------ ------ ---- ---- -----
 *   PART        PACKAGE          GPIOs LCD    Tamper FSMC CapS AdcCh
 *   ----------- ---------------- ----- ------ ------ ---- ---- -----
+ *   STM32L475Rx LQFP100            82          3     Yes   21   16
+ *   STM32L475Vx LQFP64             51          2     No    12   16
 *   STM32L4x6Jx WLCSP72L           57   8x28   2     No    12   16
 *   STM32L476Mx WLCSP81L           65   ?      ?     ?     ?    ?
 *   STM32L4x6Qx UFBGA132L         109   8x40   3     Yes   24   16
@@ -75,7 +81,8 @@
 #if defined(CONFIG_STM32L4_STM32L496XX)
 #  define STM32L4_SRAM1_SIZE       (256*1024)  /* 256Kb SRAM1 on AHB bus Matrix */
 #  define STM32L4_SRAM2_SIZE       (64*1024)   /* 64Kb  SRAM2 on AHB bus Matrix */
-#elif defined(CONFIG_STM32L4_STM32L476XX) || defined(CONFIG_STM32L4_STM32L486XX)
+#elif defined(CONFIG_STM32L4_STM32L475XX) || defined(CONFIG_STM32L4_STM32L476XX) || \
+      defined(CONFIG_STM32L4_STM32L486XX)
 #  define STM32L4_SRAM1_SIZE       (96*1024)   /* 96Kb SRAM1 on AHB bus Matrix */
 #  define STM32L4_SRAM2_SIZE       (32*1024)   /* 32Kb SRAM2 on AHB bus Matrix */
 #elif defined(CONFIG_STM32L4_STM32L451XX) || defined(CONFIG_STM32L4_STM32L452XX) || \
@@ -89,6 +96,36 @@
 #  error "Unsupported STM32L4 chip"
 #endif

+#if defined(CONFIG_STM32L4_STM32L4X5)
+#  define STM32L4_NFSMC                    1   /* Have FSMC memory controller */
+#  define STM32L4_NATIM                    2   /* Two advanced timers TIM1 and 8 */
+#  define STM32L4_NGTIM32                  2   /* 32-bit general timers TIM2 and 5 with DMA */
+#  define STM32L4_NGTIM16                  2   /* 16-bit general timers TIM3 and 4 with DMA */
+#  define STM32L4_NGTIMNDMA                3   /* 16-bit general timers TIM15-17 without DMA */
+#  define STM32L4_NBTIM                    2   /* Two basic timers, TIM6-7 */
+#  define STM32L4_NLPTIM                   2   /* Two low-power timers, LPTIM1-2 */
+#  define STM32L4_NRNG                     1   /* Random number generator (RNG) */
+#  define STM32L4_NUART                    2   /* UART 4-5 */
+#  define STM32L4_NUSART                   3   /* USART 1-3 */
+#  define STM32L4_NLPUART                  1   /* LPUART 1 */
+#  define STM32L4_QSPI                     1   /* QuadSPI1 */
+#  define STM32L4_NSPI                     3   /* SPI1-3 */
+#  define STM32L4_NI2C                     3   /* I2C1-3 */
+#  define STM32L4_NSWPMI                   1   /* SWPMI1 */
+#  define STM32L4_NUSBOTGFS                1   /* USB OTG FS */
+#  define STM32L4_NUSBFS                   0   /* No USB FS */
+#  define STM32L4_NCAN                     1   /* CAN1 */
+#  define STM32L4_NSAI                     2   /* SAI1-2 */
+#  define STM32L4_NSDMMC                   1   /* SDMMC interface */
+#  define STM32L4_NDMA                     2   /* DMA1-2 */
+#  define STM32L4_NPORTS                   8   /* 8 GPIO ports, GPIOA-H */
+#  define STM32L4_NADC                     3   /* 12-bit ADC1-3, 16 channels */
+#  define STM32L4_NDAC                     2   /* 12-bit DAC1-2 */
+#  define STM32L4_NCRC                     1   /* CRC */
+#  define STM32L4_NCOMP                    2   /* Comparators */
+#  define STM32L4_NOPAMP                   2   /* Operational Amplifiers */
+#endif /* CONFIG_STM32L4_STM32L4X5 */
+
 #if defined(CONFIG_STM32L4_STM32L4X6)
 #  define STM32L4_NFSMC                    1   /* Have FSMC memory controller */
 #  define STM32L4_NATIM                    2   /* Two advanced timers TIM1 and 8 */
@@ -101,12 +138,14 @@
 #  define STM32L4_NUART                    2   /* UART 4-5 */
 #  define STM32L4_NUSART                   3   /* USART 1-3 */
 #  define STM32L4_NLPUART                  1   /* LPUART 1 */
+#  define STM32L4_QSPI                     1   /* QuadSPI1 */
 #  define STM32L4_NSPI                     3   /* SPI1-3 */
 #if defined(CONFIG_STM32L4_STM32L496XX)
 #  define STM32L4_NI2C                     4   /* I2C1-4 */
 #else
 #  define STM32L4_NI2C                     3   /* I2C1-3 */
 #endif
+#  define STM32L4_NSWPMI                   1   /* SWPMI1 */
 #  define STM32L4_NUSBOTGFS                1   /* USB OTG FS */
 #  define STM32L4_NUSBFS                   0   /* No USB FS */
 #if defined(CONFIG_STM32L4_STM32L496XX)
@@ -142,8 +181,10 @@
 #  define STM32L4_NUART                    1   /* UART 4 */
 #  define STM32L4_NUSART                   3   /* USART 1-3 */
 #  define STM32L4_NLPUART                  1   /* LPUART 1 */
+#  define STM32L4_QSPI                     1   /* QuadSPI1 */
 #  define STM32L4_NSPI                     3   /* SPI1-3 */
 #  define STM32L4_NI2C                     4   /* I2C1-4 */
+#  define STM32L4_NSWPMI                   1   /* SWPMI1 */
 #  define STM32L4_NUSBOTGFS                0   /* No USB OTG FS */
 #if defined(CONFIG_STM32L4_STM32L451XX)
 #  define STM32L4_NUSBFS                   0   /* No USB FS */
@@ -178,8 +219,10 @@
 #  define STM32L4_NUART                    0   /* No UART */
 #  define STM32L4_NUSART                   2   /* USART 1-2 */
 #  define STM32L4_NLPUART                  1   /* LPUART 1 */
+#  define STM32L4_QSPI                     1   /* QuadSPI1 */
 #  define STM32L4_NSPI                     2   /* SPI1, SPI3 */
 #  define STM32L4_NI2C                     2   /* I2C1, I2C3 */
+#  define STM32L4_NSWPMI                   1   /* SWPMI1 */
 #  define STM32L4_NUSBOTGFS                0   /* No USB OTG FS */
 #  define STM32L4_NUSBFS                   1   /* USB FS */
 #  define STM32L4_NCAN                     1   /* CAN1 */
@@ -76,10 +76,12 @@

 #define STM32L4_IRQ_FIRST         (16) /* Vector number of the first external interrupt */

-#if defined(CONFIG_STM32L4_STM32L4X6)
-#  include <arch/stm32l4/stm32l4x6xx_irq.h>
-#elif defined(CONFIG_STM32L4_STM32L4X3)
+#if defined(CONFIG_STM32L4_STM32L4X3)
 #  include <arch/stm32l4/stm32l4x3xx_irq.h>
+#elif defined(CONFIG_STM32L4_STM32L4X5)
+#  include <arch/stm32l4/stm32l4x5xx_irq.h>
+#elif defined(CONFIG_STM32L4_STM32L4X6)
+#  include <arch/stm32l4/stm32l4x6xx_irq.h>
 #else
 #  error "Unsupported STM32 L4 chip"
 #endif
@@ -0,0 +1,185 @@
+/****************************************************************************************************
+ * arch/arm/include/stm32l4/stm32l4x5xx_irq.h
+ *
+ *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2015 Sebastien Lorquet. All rights reserved.
+ *   Author: Sebastien Lorquet <sebastien@lorquet.fr>
+ *           Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************************************/
+
+/* This file should never be included directed but, rather, only indirectly through arch/irq.h */
+
+#ifndef __ARCH_ARM_INCLUDE_STM32L4_STM32L4X5XX_IRQ_H
+#define __ARCH_ARM_INCLUDE_STM32L4_STM32L4X5XX_IRQ_H
+
+/****************************************************************************************************
+ * Included Files
+ ****************************************************************************************************/
+
+#include <nuttx/config.h>
+
+/****************************************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************************************/
+
+/* IRQ numbers.  The IRQ number corresponds vector number and hence map directly to bits in the
+ * NVIC.  This does, however, waste several words of memory in the IRQ to handle mapping tables.
+ *
+ * Processor Exceptions (vectors 0-15).  These common definitions can be found in the file
+ * nuttx/arch/arm/include/stm32f7/irq.h which includes this file
+ *
+ * External interrupts (vectors >= 16)
+ */
+
+#define STM32L4_IRQ_WWDG        (STM32L4_IRQ_FIRST+0)  /* 0:  Window Watchdog interrupt */
+#define STM32L4_IRQ_PVD         (STM32L4_IRQ_FIRST+1)  /* 1:  PVD through EXTI Line detection interrupt */
+#define STM32L4_IRQ_TAMPER      (STM32L4_IRQ_FIRST+2)  /* 2:  Tamper and time stamp interrupts */
+#define STM32L4_IRQ_TIMESTAMP   (STM32L4_IRQ_FIRST+2)  /* 2:  Tamper and time stamp interrupts */
+#define STM32L4_IRQ_RTC_WKUP    (STM32L4_IRQ_FIRST+3)  /* 3:  RTC global interrupt */
+#define STM32L4_IRQ_FLASH       (STM32L4_IRQ_FIRST+4)  /* 4:  Flash global interrupt */
+#define STM32L4_IRQ_RCC         (STM32L4_IRQ_FIRST+5)  /* 5:  RCC global interrupt */
+#define STM32L4_IRQ_EXTI0       (STM32L4_IRQ_FIRST+6)  /* 6:  EXTI Line 0 interrupt */
+#define STM32L4_IRQ_EXTI1       (STM32L4_IRQ_FIRST+7)  /* 7:  EXTI Line 1 interrupt */
+#define STM32L4_IRQ_EXTI2       (STM32L4_IRQ_FIRST+8)  /* 8:  EXTI Line 2 interrupt */
+#define STM32L4_IRQ_EXTI3       (STM32L4_IRQ_FIRST+9)  /* 9:  EXTI Line 3 interrupt */
+#define STM32L4_IRQ_EXTI4       (STM32L4_IRQ_FIRST+10) /* 10: EXTI Line 4 interrupt */
+#define STM32L4_IRQ_DMA1CH1     (STM32L4_IRQ_FIRST+11) /* 11: DMA1 Channel 1 global interrupt */
+#define STM32L4_IRQ_DMA1CH2     (STM32L4_IRQ_FIRST+12) /* 12: DMA1 Channel 2 global interrupt */
+#define STM32L4_IRQ_DMA1CH3     (STM32L4_IRQ_FIRST+13) /* 13: DMA1 Channel 3 global interrupt */
+#define STM32L4_IRQ_DMA1CH4     (STM32L4_IRQ_FIRST+14) /* 14: DMA1 Channel 4 global interrupt */
+#define STM32L4_IRQ_DMA1CH5     (STM32L4_IRQ_FIRST+15) /* 15: DMA1 Channel 5 global interrupt */
+#define STM32L4_IRQ_DMA1CH6     (STM32L4_IRQ_FIRST+16) /* 16: DMA1 Channel 6 global interrupt */
+#define STM32L4_IRQ_DMA1CH7     (STM32L4_IRQ_FIRST+17) /* 17: DMA1 Channel 7 global interrupt */
+#define STM32L4_IRQ_ADC12       (STM32L4_IRQ_FIRST+18) /* 18: ADC1 and ADC2 global interrupt */
+#define STM32L4_IRQ_CAN1TX      (STM32L4_IRQ_FIRST+19) /* 19: CAN1 TX interrupts */
+#define STM32L4_IRQ_CAN1RX0     (STM32L4_IRQ_FIRST+20) /* 20: CAN1 RX0 interrupts */
+#define STM32L4_IRQ_CAN1RX1     (STM32L4_IRQ_FIRST+21) /* 21: CAN1 RX1 interrupt */
+#define STM32L4_IRQ_CAN1SCE     (STM32L4_IRQ_FIRST+22) /* 22: CAN1 SCE interrupt */
+#define STM32L4_IRQ_EXTI95      (STM32L4_IRQ_FIRST+23) /* 23: EXTI Line[9:5] interrupts */
+#define STM32L4_IRQ_TIM1BRK     (STM32L4_IRQ_FIRST+24) /* 24: TIM1 Break interrupt */
+#define STM32L4_IRQ_TIM15       (STM32L4_IRQ_FIRST+24) /* 24: TIM15 global interrupt */
+#define STM32L4_IRQ_TIM1UP      (STM32L4_IRQ_FIRST+25) /* 25: TIM1 Update interrupt */
+#define STM32L4_IRQ_TIM16       (STM32L4_IRQ_FIRST+25) /* 25: TIM16 global interrupt */
+#define STM32L4_IRQ_TIM1TRGCOM  (STM32L4_IRQ_FIRST+26) /* 26: TIM1 Trigger and Commutation interrupts */
+#define STM32L4_IRQ_TIM17       (STM32L4_IRQ_FIRST+26) /* 26: TIM17 global interrupt */
+#define STM32L4_IRQ_TIM1CC      (STM32L4_IRQ_FIRST+27) /* 27: TIM1 Capture Compare interrupt */
+#define STM32L4_IRQ_TIM2        (STM32L4_IRQ_FIRST+28) /* 28: TIM2 global interrupt */
+#define STM32L4_IRQ_TIM3        (STM32L4_IRQ_FIRST+29) /* 29: TIM3 global interrupt */
+#define STM32L4_IRQ_TIM4        (STM32L4_IRQ_FIRST+30) /* 30: TIM4 global interrupt */
+#define STM32L4_IRQ_I2C1EV      (STM32L4_IRQ_FIRST+31) /* 31: I2C1 event interrupt */
+#define STM32L4_IRQ_I2C1ER      (STM32L4_IRQ_FIRST+32) /* 32: I2C1 error interrupt */
+#define STM32L4_IRQ_I2C2EV      (STM32L4_IRQ_FIRST+33) /* 33: I2C2 event interrupt */
+#define STM32L4_IRQ_I2C2ER      (STM32L4_IRQ_FIRST+34) /* 34: I2C2 error interrupt */
+#define STM32L4_IRQ_SPI1        (STM32L4_IRQ_FIRST+35) /* 35: SPI1 global interrupt */
+#define STM32L4_IRQ_SPI2        (STM32L4_IRQ_FIRST+36) /* 36: SPI2 global interrupt */
+#define STM32L4_IRQ_USART1      (STM32L4_IRQ_FIRST+37) /* 37: USART1 global interrupt */
+#define STM32L4_IRQ_USART2      (STM32L4_IRQ_FIRST+38) /* 38: USART2 global interrupt */
+#define STM32L4_IRQ_USART3      (STM32L4_IRQ_FIRST+39) /* 39: USART3 global interrupt */
+#define STM32L4_IRQ_EXTI1510    (STM32L4_IRQ_FIRST+40) /* 40: EXTI Line[15:10] interrupts */
+#define STM32L4_IRQ_RTCALRM     (STM32L4_IRQ_FIRST+41) /* 41: RTC alarm through EXTI line interrupt */
+#define STM32L4_IRQ_DFSDM3      (STM32L4_IRQ_FIRST+42) /* 42: Digital Filter / Sigma Delta Modulator interrupt */
+#define STM32L4_IRQ_TIM8BRK     (STM32L4_IRQ_FIRST+43) /* 43: TIM8 Break interrupt */
+#define STM32L4_IRQ_TIM8UP      (STM32L4_IRQ_FIRST+44) /* 44: TIM8 Update interrupt */
+#define STM32L4_IRQ_TIM8TRGCOM  (STM32L4_IRQ_FIRST+45) /* 45: TIM8 Trigger and Commutation interrupts */
+#define STM32L4_IRQ_TIM8CC      (STM32L4_IRQ_FIRST+46) /* 46: TIM8 Capture Compare interrupt */
+#define STM32L4_IRQ_ADC3        (STM32L4_IRQ_FIRST+47) /* 47: ADC3 global interrupt */
+#define STM32L4_IRQ_FSMC        (STM32L4_IRQ_FIRST+48) /* 48: FSMC global interrupt */
+#define STM32L4_IRQ_SDMMC1      (STM32L4_IRQ_FIRST+49) /* 49: SDMMC1 global interrupt */
+#define STM32L4_IRQ_TIM5        (STM32L4_IRQ_FIRST+50) /* 50: TIM5 global interrupt */
+#define STM32L4_IRQ_SPI3        (STM32L4_IRQ_FIRST+51) /* 51: SPI3 global interrupt */
+#define STM32L4_IRQ_UART4       (STM32L4_IRQ_FIRST+52) /* 52: UART4 global interrupt */
+#define STM32L4_IRQ_UART5       (STM32L4_IRQ_FIRST+53) /* 53: UART5 global interrupt */
+#define STM32L4_IRQ_TIM6        (STM32L4_IRQ_FIRST+54) /* 54: TIM6 global interrupt */
+#define STM32L4_IRQ_DAC         (STM32L4_IRQ_FIRST+54) /* 54: DAC1 and DAC2 underrun error interrupts */
+#define STM32L4_IRQ_TIM7        (STM32L4_IRQ_FIRST+55) /* 55: TIM7 global interrupt */
+#define STM32L4_IRQ_DMA2CH1     (STM32L4_IRQ_FIRST+56) /* 56: DMA2 Channel 1 global interrupt */
+#define STM32L4_IRQ_DMA2CH2     (STM32L4_IRQ_FIRST+57) /* 57: DMA2 Channel 2 global interrupt */
+#define STM32L4_IRQ_DMA2CH3     (STM32L4_IRQ_FIRST+58) /* 58: DMA2 Channel 3 global interrupt */
+#define STM32L4_IRQ_DMA2CH4     (STM32L4_IRQ_FIRST+59) /* 59: DMA2 Channel 4 global interrupt */
+#define STM32L4_IRQ_DMA2CH5     (STM32L4_IRQ_FIRST+60) /* 60: DMA2 Channel 5 global interrupt */
+#define STM32L4_IRQ_DFSDM0      (STM32L4_IRQ_FIRST+61) /* 61: DFSDM0 global interrupt */
+#define STM32L4_IRQ_DFSDM1      (STM32L4_IRQ_FIRST+62) /* 62: DFSDM1 global interrupt*/
+#define STM32L4_IRQ_DFSDM2      (STM32L4_IRQ_FIRST+63) /* 63: DFSDM2 global interrupt */
+#define STM32L4_IRQ_COMP        (STM32L4_IRQ_FIRST+64) /* 64: COMP1/COMP2 interrupts */
+#define STM32L4_IRQ_LPTIM1      (STM32L4_IRQ_FIRST+65) /* 65: LPTIM1 global interrupt */
+#define STM32L4_IRQ_LPTIM2      (STM32L4_IRQ_FIRST+66) /* 66: LPTIM2 global interrupt */
+#define STM32L4_IRQ_OTGFS       (STM32L4_IRQ_FIRST+67) /* 67: USB On The Go FS global interrupt */
+#define STM32L4_IRQ_DMA2CH6     (STM32L4_IRQ_FIRST+68) /* 68: DMA2 Channel 6 global interrupt */
+#define STM32L4_IRQ_DMA2CH7     (STM32L4_IRQ_FIRST+69) /* 69: DMA2 Channel 7 global interrupt */
+#define STM32L4_IRQ_LPUART1     (STM32L4_IRQ_FIRST+70) /* 70: Low power UART 1 global interrupt */
+#define STM32L4_IRQ_QUADSPI     (STM32L4_IRQ_FIRST+71) /* 71: QUADSPI global interrupt */
+#define STM32L4_IRQ_I2C3EV      (STM32L4_IRQ_FIRST+72) /* 72: I2C3 event interrupt */
+#define STM32L4_IRQ_I2C3ER      (STM32L4_IRQ_FIRST+73) /* 73: I2C3 error interrupt */
+#define STM32L4_IRQ_SAI1        (STM32L4_IRQ_FIRST+74) /* 74: SAI1 global interrupt */
+#define STM32L4_IRQ_SAI2        (STM32L4_IRQ_FIRST+75) /* 75: SAI2 global interrupt */
+#define STM32L4_IRQ_SWPMI1      (STM32L4_IRQ_FIRST+76) /* 76: SWPMI1 global interrupt */
+#define STM32L4_IRQ_TSC         (STM32L4_IRQ_FIRST+77) /* 77: TSC global interrupt */
+#define STM32_IRQ_RESERVED78    (STM32L4_IRQ_FIRST+78) /* 78: Reserved */
+#define STM32_IRQ_RESERVED79    (STM32L4_IRQ_FIRST+79) /* 79: Reserved */
+#define STM32L4_IRQ_RNG         (STM32L4_IRQ_FIRST+80) /* 80: RNG global interrupt */
+#define STM32L4_IRQ_FPU         (STM32L4_IRQ_FIRST+81) /* 81: FPU global interrupt */
+
+#define NR_INTERRUPTS           82
+#define NR_VECTORS              (STM32L4_IRQ_FIRST+NR_INTERRUPTS)
+
+/* EXTI interrupts (Do not use IRQ numbers) */
+
+#define NR_IRQS                 NR_VECTORS
+
+/****************************************************************************************************
+ * Public Types
+ ****************************************************************************************************/
+
+/****************************************************************************************************
+ * Public Data
+ ****************************************************************************************************/
+
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************************************
+ * Public Functions
+ ****************************************************************************************************/
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+#endif
+
+#endif /* __ARCH_ARM_INCLUDE_STM32L4_STM32L4X5XX_IRQ_H */
@@ -70,12 +70,12 @@
 #define STM32L4_IRQ_EXTI2       (STM32L4_IRQ_FIRST+8)  /* 8:  EXTI Line 2 interrupt */
 #define STM32L4_IRQ_EXTI3       (STM32L4_IRQ_FIRST+9)  /* 9:  EXTI Line 3 interrupt */
 #define STM32L4_IRQ_EXTI4       (STM32L4_IRQ_FIRST+10) /* 10: EXTI Line 4 interrupt */
-#define STM32L4_IRQ_DMA1CH1     (STM32L4_IRQ_FIRST+11) /* 12: DMA1 Channel 1 global interrupt */
-#define STM32L4_IRQ_DMA1CH2     (STM32L4_IRQ_FIRST+12) /* 13: DMA1 Channel 2 global interrupt */
-#define STM32L4_IRQ_DMA1CH3     (STM32L4_IRQ_FIRST+13) /* 14: DMA1 Channel 3 global interrupt */
-#define STM32L4_IRQ_DMA1CH4     (STM32L4_IRQ_FIRST+14) /* 15: DMA1 Channel 4 global interrupt */
-#define STM32L4_IRQ_DMA1CH5     (STM32L4_IRQ_FIRST+15) /* 16: DMA1 Channel 5 global interrupt */
-#define STM32L4_IRQ_DMA1CH6     (STM32L4_IRQ_FIRST+16) /* 17: DMA1 Channel 6 global interrupt */
+#define STM32L4_IRQ_DMA1CH1     (STM32L4_IRQ_FIRST+11) /* 11: DMA1 Channel 1 global interrupt */
+#define STM32L4_IRQ_DMA1CH2     (STM32L4_IRQ_FIRST+12) /* 12: DMA1 Channel 2 global interrupt */
+#define STM32L4_IRQ_DMA1CH3     (STM32L4_IRQ_FIRST+13) /* 13: DMA1 Channel 3 global interrupt */
+#define STM32L4_IRQ_DMA1CH4     (STM32L4_IRQ_FIRST+14) /* 14: DMA1 Channel 4 global interrupt */
+#define STM32L4_IRQ_DMA1CH5     (STM32L4_IRQ_FIRST+15) /* 15: DMA1 Channel 5 global interrupt */
+#define STM32L4_IRQ_DMA1CH6     (STM32L4_IRQ_FIRST+16) /* 16: DMA1 Channel 6 global interrupt */
 #define STM32L4_IRQ_DMA1CH7     (STM32L4_IRQ_FIRST+17) /* 17: DMA1 Channel 7 global interrupt */
 #define STM32L4_IRQ_ADC12       (STM32L4_IRQ_FIRST+18) /* 18: ADC1 and ADC2 global interrupt */
 #define STM32L4_IRQ_CAN1TX      (STM32L4_IRQ_FIRST+19) /* 19: CAN1 TX interrupts */
@@ -1,7 +1,7 @@
 /****************************************************************************
 * arch/arm/src/a1x/a1x_serial.c
 *
- *   Copyright (C) 2013-2014 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2013-2014, 2017 Gregory Nutt. All rights reserved.
 *   Author: Gregory Nutt <gnutt@nuttx.org>
 *
 * Redistribution and use in source and binary forms, with or without
@@ -1035,7 +1035,7 @@ static int up_attach(struct uart_dev_s *dev)

  /* Attach and enable the IRQ */

-  ret = irq_attach(priv->irq, uart_interrupt, priv);
+  ret = irq_attach(priv->irq, uart_interrupt, dev);
  if (ret == OK)
    {
      /* Enable the interrupt (RX and TX interrupts are still disabled
@@ -1080,7 +1080,7 @@ static void up_detach(struct uart_dev_s *dev)
 static int uart_interrupt(int irq, void *context, void *arg)
 {
  struct uart_dev_s *dev = (struct uart_dev_s *)arg;
-  struct up_dev_s *priv = (struct up_dev_s *)arg;
+  struct up_dev_s *priv;
  uint32_t status;
  int passes;

@@ -128,11 +128,7 @@ ifeq ($(CONFIG_ARCH_CORTEXM4),y)
  TOOLCHAIN_MTUNE    := -mtune=cortex-m4
  TOOLCHAIN_MARCH    := -march=armv7e-m
  ifeq ($(CONFIG_ARCH_FPU),y)
-  ifeq ($(CONFIG_ARCH_DPFPU),y)
-    TOOLCHAIN_MFLOAT := -mfpu=fpv4-sp -mfloat-abi=hard
-  else
    TOOLCHAIN_MFLOAT := -mfpu=fpv4-sp-d16 -mfloat-abi=hard
-  endif
  else
    TOOLCHAIN_MFLOAT := -mfloat-abi=soft
  endif
@@ -1,8 +1,7 @@
 /****************************************************************************
 * arch/arm/src/imx1/imx_serial.c
- * arch/arm/src/chip/imx_serial.c
 *
- *   Copyright (C) 2009, 2012-2013 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2009, 2012-2013, 2017 Gregory Nutt. All rights reserved.
 *   Author: Gregory Nutt <gnutt@nuttx.org>
 *
 * Redistribution and use in source and binary forms, with or without
@@ -111,7 +110,6 @@ static int  up_setup(struct uart_dev_s *dev);
 static void up_shutdown(struct uart_dev_s *dev);
 static int  up_attach(struct uart_dev_s *dev);
 static void up_detach(struct uart_dev_s *dev);
-static inline struct uart_dev_s *up_mapirq(int irq);
 static int  up_interrupt(int irq, void *context, FAR void *arg);
 static int  up_ioctl(struct file *filep, int cmd, unsigned long arg);
 static int  up_receive(struct uart_dev_s *dev, uint32_t *status);
@@ -753,13 +751,13 @@ static int up_attach(struct uart_dev_s *dev)
  /* Attach and enable the IRQ */

 #if defined(CONFIG_ARCH_CHIP_IMX1) || defined(CONFIG_ARCH_CHIP_IMXL)
-  ret = irq_attach(priv->rxirq, up_interrupt, NULL);
+  ret = irq_attach(priv->rxirq, up_interrupt, dev);
  if (ret < 0)
    {
      return ret;
    }

-  ret = irq_attach(priv->txirq, up_interrupt, NULL);
+  ret = irq_attach(priv->txirq, up_interrupt, dev);
  if (ret < 0)
    {
      irq_detach(priv->rxirq);
@@ -772,7 +770,7 @@ static int up_attach(struct uart_dev_s *dev)
  up_enable_irq(priv->txirq);

 #else
-  ret = irq_attach(priv->irq, up_interrupt, NULL);
+  ret = irq_attach(priv->irq, up_interrupt, dev);
  if (ret == OK)
    {
      /* Enable the interrupt (RX and TX interrupts are still disabled
@@ -810,60 +808,6 @@ static void up_detach(struct uart_dev_s *dev)
 #endif
 }

-/****************************************************************************
- * Name: up_mapirq
- *
- * Description:
- *   Map an IRQ number to internal UART state structure
- *
- ****************************************************************************/
-
-static inline struct uart_dev_s *up_mapirq(int irq)
-{
-  struct uart_dev_s *dev;
-
-  switch (irq)
-    {
-#ifdef CONFIG_IMX1_UART1
-#if defined(CONFIG_ARCH_CHIP_IMX1) || defined(CONFIG_ARCH_CHIP_IMXL)
-      case IMX_IRQ_UART1RX:
-      case IMX_IRQ_UART1TX:
-#else
-      case IMX_IRQ_UART1:
-#endif
-        dev = &g_uart1port;
-        break;
-#endif
-
-#ifdef CONFIG_IMX1_UART2
-#if defined(CONFIG_ARCH_CHIP_IMX1) || defined(CONFIG_ARCH_CHIP_IMXL)
-      case IMX_IRQ_UART2RX:
-      case IMX_IRQ_UART2TX:
-#else
-      case IMX_IRQ_UART2:
-#endif
-        dev = &g_uart2port;
-        break;
-#endif
-
-#ifdef CONFIG_IMX1_UART3
-#if defined(CONFIG_ARCH_CHIP_IMX1) || defined(CONFIG_ARCH_CHIP_IMXL)
-      case IMX_IRQ_UART3RX:
-      case IMX_IRQ_UART3TX:
-#else
-      case IMX_IRQ_UART3:
-#endif
-        dev = &g_uart3port;
-        break;
-#endif
-
-      default:
-        PANIC();
-        break;
-    }
-  return dev;
-}
-
 /****************************************************************************
 * Name: up_interrupt (and front-ends)
 *
@@ -879,12 +823,12 @@ static inline struct uart_dev_s *up_mapirq(int irq)

 static int up_interrupt(int irq, void *context, FAR void *arg)
 {
-  struct uart_dev_s *dev;
-  struct up_dev_s   *priv;
+  struct uart_dev_s *dev = (struct uart_dev_s *)arg;
+  struct up_dev_s *priv;
  uint32_t usr1;
-  int    passes = 0;
+  int passes = 0;

-  dev  = up_mapirq(irq);
+  DEBUGASSERT(dev != NULL && dev->priv != NULL);
  priv = (struct up_dev_s *)dev->priv;

  /* Loop until there are no characters to be transferred or,
@@ -595,7 +595,7 @@ static int imx_attach(struct uart_dev_s *dev)

  /* Attach and enable the IRQ */

-  ret = irq_attach(priv->irq, imx_interrupt, priv);
+  ret = irq_attach(priv->irq, imx_interrupt, dev);
  if (ret == OK)
    {
      /* Configure as a (high) level interrupt */
@@ -140,6 +140,10 @@ ifeq ($(CONFIG_KINETIS_SDHC),y)
 CHIP_CSRCS += kinetis_sdhc.c
 endif

+ifeq ($(CONFIG_SPI),y)
+CHIP_CSRCS += kinetis_spi.c
+endif
+
 ifeq ($(CONFIG_USBDEV),y)
 CHIP_CSRCS += kinetis_usbdev.c
 endif
@@ -140,7 +140,7 @@
 #define SPI_MCR_PCSIS_SHIFT        (16)      /* Bits 16-21: Peripheral Chip Select x Inactive State */
 #define SPI_MCR_PCSIS_MASK         (0x3f << SPI_MCR_PCSIS_SHIFT)
 #  define SPI_MCR_PCSIS_CS(n)      ((1 << (n)) << SPI_MCR_PCSIS_SHIFT)
-                                             /* Bits 22–23: Reserved */
+                                             /* Bits 22-23: Reserved */
 #define SPI_MCR_ROOE               (1 << 24) /* Bit 24: Receive FIFO Overflow Overwrite Enable */
 #define SPI_MCR_PCSSE              (1 << 25) /* Bit 25: Peripheral Chip Select Strobe Enable */
 #define SPI_MCR_MTFE               (1 << 26) /* Bit 26: Modified Timing Format Enable */
@@ -165,6 +165,7 @@

 #define SPI_CTARM_BR_SHIFT         (0)       /* Bits 0-3: Baud Rate Scaler */
 #define SPI_CTARM_BR_MASK          (15 << SPI_CTARM_BR_SHIFT)
+#  define SPI_CTARM_BR(n)          ((((n) & 0xf)) << SPI_CTARM_BR_SHIFT)
 #  define SPI_CTARM_BR_2           (0 << SPI_CTARM_BR_SHIFT)
 #  define SPI_CTARM_BR_4           (1 << SPI_CTARM_BR_SHIFT)
 #  define SPI_CTARM_BR_6           (2 << SPI_CTARM_BR_SHIFT)
@@ -205,6 +206,7 @@
 #  define SPI_CTARM_CSSCK_65536    (15 << SPI_CTARM_CSSCK_SHIFT)
 #define SPI_CTARM_PBR_SHIFT        (16)      /* Bits 16-17: Baud Rate Prescaler */
 #define SPI_CTARM_PBR_MASK         (3 << SPI_CTARM_PBR_SHIFT)
+#  define SPI_CTARM_PBR(n)         (((n) & 0x3) << SPI_CTARM_PBR_SHIFT)
 #  define SPI_CTARM_PBR_2          (0 << SPI_CTARM_PBR_SHIFT)
 #  define SPI_CTARM_PBR_3          (1 << SPI_CTARM_PBR_SHIFT)
 #  define SPI_CTARM_PBR_5          (2 << SPI_CTARM_PBR_SHIFT)
@@ -231,6 +233,7 @@
                                             /* Bits 25-26:  See common bits above */
 #define SPI_CTARM_FMSZ_SHIFT       (27)      /* Bits 27-30: Frame Size */
 #define SPI_CTARM_FMSZ_MASK        (15 << SPI_CTARM_FMSZ_SHIFT)
+#define SPI_CTARM_FMSZ(n)          ((((n) & 0xf)) << SPI_CTARM_FMSZ_SHIFT)
 #define SPI_CTARM_DBR              (1 << 31) /* Bit 31:  Double Baud Rate */

 /* DSPI Clock and Transfer Attributes Register (Slave Mode) */
@@ -281,6 +284,7 @@

 #define SPI_PUSHR_TXDATA_SHIFT     (0)       /* Bits 0-15: Transmit Data */
 #define SPI_PUSHR_TXDATA_MASK      (0xffff << SPI_PUSHR_TXDATA_SHIFT)
+#  define SPI_PUSHR_TXDATA(d)      (((d) & 0xffff) << SPI_PUSHR_TXDATA_SHIFT)
 #define SPI_PUSHR_PCS_SHIFT        (16)      /* Bits 16-21: Select PCS signals to assert */
 #define SPI_PUSHR_PCS_MASK         (0x3f << SPI_PUSHR_PCS_SHIFT)
 #  define SPI_PUSHR_PCS(n)         ((1 << (n)) << SPI_PUSHR_PCS_SHIFT)
@@ -63,11 +63,9 @@
 #include "up_arch.h"
 #include "up_internal.h"

-#include "kinetis_config.h"
-#include "chip.h"
+#include "kinetis.h"
 #include "chip/kinetis_lpuart.h"
 #include "chip/kinetis_pinmux.h"
-#include "kinetis.h"

 /****************************************************************************
 * Pre-processor Definitions
@@ -1,7 +1,7 @@
 /****************************************************************************
 * arch/arm/src/lpc31xx/lpc31_serial.c
 *
- *   Copyright (C) 2009, 2012-2013 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2009, 2012-2013, 2017 Gregory Nutt. All rights reserved.
 *   Author: Gregory Nutt <gnutt@nuttx.org>
 *
 * Redistribution and use in source and binary forms, with or without
@@ -444,7 +444,7 @@ static int up_attach(struct uart_dev_s *dev)

  /* Attach and enable the IRQ */

-  ret = irq_attach(LPC31_IRQ_UART, up_interrupt, NULL);
+  ret = irq_attach(LPC31_IRQ_UART, up_interrupt, dev);
  if (ret == OK)
    {
      /* Enable the interrupt (RX and TX interrupts are still disabled
@@ -453,6 +453,7 @@ static int up_attach(struct uart_dev_s *dev)

      up_enable_irq(LPC31_IRQ_UART);
    }
+
  return ret;
 }

@@ -484,9 +485,9 @@ static void up_detach(struct uart_dev_s *dev)

 static int up_interrupt(int irq, void *context, FAR void *arg)
 {
-  struct uart_dev_s *dev   = &g_uartport;
-  uint8_t            status;
-  int                passes;
+  struct uart_dev_s *dev = (struct uart_dev_s *)arg;
+  uint8_t status;
+  int passes;

  /* Loop until there are no characters to be transferred or,
   * until we have been looping for a long time.
@@ -287,7 +287,7 @@ static int dbgu_attach(struct uart_dev_s *dev)

  /* Attach and enable the IRQ */

-  ret = irq_attach(SAM_IRQ_DBGU, dbgu_interrupt, NULL);
+  ret = irq_attach(SAM_IRQ_DBGU, dbgu_interrupt, dev);
  if (ret == OK)
    {
      /* Enable the interrupt (RX and TX interrupts are still disabled
@@ -330,13 +330,16 @@ static void dbgu_detach(struct uart_dev_s *dev)

 static int dbgu_interrupt(int irq, void *context, FAR void *arg)
 {
-  struct uart_dev_s *dev = &g_dbgu_port;
-  struct dbgu_dev_s *priv = (struct dbgu_dev_s *)dev->priv;
+  struct uart_dev_s *dev = (struct uart_dev_s *)arg;
+  struct dbgu_dev_s *priv;
  uint32_t           pending;
  uint32_t           imr;
  int                passes;
  bool               handled;

+  DEBUGASSERT(dev != NULL && dev->priv != NULL);
+  priv = (struct dbgu_dev_s *)dev->priv;
+
  /* Loop until there are no characters to be transferred or, until we have
   * been looping for a long time.
   */
@@ -225,6 +225,10 @@ ifeq ($(CONFIG_OPAMP),y)
 CHIP_CSRCS += stm32_opamp.c
 endif

+ifeq ($(CONFIG_HRTIM),y)
+CHIP_CSRCS += stm32_hrtim.c
+endif
+
 ifeq ($(CONFIG_STM32_1WIREDRIVER),y)
 CHIP_CSRCS += stm32_1wire.c
 endif
@@ -67,6 +67,7 @@
 #include "stm32_flash.h"
 #include "stm32_fsmc.h"
 #include "stm32_gpio.h"
+#include "stm32_hrtim.h"
 #include "stm32_i2c.h"
 #include "stm32_ltdc.h"
 #include "stm32_opamp.h"
@@ -0,0 +1,305 @@
+/************************************************************************************
+ * arch/arm/src/stm32/stm32_hrtim.h
+ *
+ *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
+ *   Author: Mateusz Szafoni <raiden00@railab.me>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32_STM32_HRTIM_H
+#define __ARCH_ARM_SRC_STM32_STM32_HRTIM_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "chip.h"
+
+#ifdef CONFIG_STM32_HRTIM1
+
+#if defined(CONFIG_STM32_STM32F33XX)
+#  include "chip/stm32f33xxx_hrtim.h"
+#else
+#  error
+#endif
+
+/************************************************************************************
+ * Pre-processor definitions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/* HRTIM Timer X index */
+
+enum stm32_hrtim_tim_e
+{
+  HRTIM_TIMER_MASTER,
+#ifdef CONFIG_STM32_HRTIM_TIMA
+  HRTIM_TIMER_TIMA,
+#endif
+#ifdef CONFIG_STM32_HRTIM_TIMB
+  HRTIM_TIMER_TIMB,
+#endif
+#ifdef CONFIG_STM32_HRTIM_TIMC
+  HRTIM_TIMER_TIMC,
+#endif
+#ifdef CONFIG_STM32_HRTIM_TIMD
+  HRTIM_TIMER_TIMD,
+#endif
+#ifdef CONFIG_STM32_HRTIM_TIME
+  HRTIM_TIMER_TIME,
+#endif
+};
+
+/* Source which can force the Tx1/Tx2 output to its inactive state */
+
+enum stm32_hrtim_out_rst_e
+{
+  HRTIM_OUT_RST_UPDATE    = (1 << 0),
+  HRTIM_OUT_RST_EXTEVNT10 = (1 << 1),
+  HRTIM_OUT_RST_EXTEVNT9  = (1 << 2),
+  HRTIM_OUT_RST_EXTEVNT8  = (1 << 3),
+  HRTIM_OUT_RST_EXTEVNT7  = (1 << 4),
+  HRTIM_OUT_RST_EXTEVNT6  = (1 << 5),
+  HRTIM_OUT_RST_EXTEVNT5  = (1 << 6),
+  HRTIM_OUT_RST_EXTEVNT4  = (1 << 7),
+  HRTIM_OUT_RST_EXTEVNT3  = (1 << 8),
+  HRTIM_OUT_RST_EXTEVNT2  = (1 << 9),
+  HRTIM_OUT_RST_EXTEVNT1  = (1 << 10),
+  HRTIM_OUT_RST_TIMEVNT9  = (1 << 11),
+  HRTIM_OUT_RST_TIMEVNT8  = (1 << 12),
+  HRTIM_OUT_RST_TIMEVNT7  = (1 << 13),
+  HRTIM_OUT_RST_TIMEVNT6  = (1 << 14),
+  HRTIM_OUT_RST_TIMEVNT5  = (1 << 15),
+  HRTIM_OUT_RST_TIMEVNT4  = (1 << 16),
+  HRTIM_OUT_RST_TIMEVNT3  = (1 << 17),
+  HRTIM_OUT_RST_TIMEVNT2  = (1 << 18),
+  HRTIM_OUT_RST_TIMEVNT1  = (1 << 19),
+  HRTIM_OUT_RST_MSTCMP4   = (1 << 20),
+  HRTIM_OUT_RST_MSTCMP3   = (1 << 21),
+  HRTIM_OUT_RST_MSTCMP2   = (1 << 22),
+  HRTIM_OUT_RST_MSTCMP1   = (1 << 23),
+  HRTIM_OUT_RST_MSTPER    = (1 << 24),
+  HRTIM_OUT_RST_CMP4      = (1 << 25),
+  HRTIM_OUT_RST_CMP3      = (1 << 26),
+  HRTIM_OUT_RST_CMP2      = (1 << 27),
+  HRTIM_OUT_RST_CMP1      = (1 << 28),
+  HRTIM_OUT_RST_PER       = (1 << 29),
+  HRTIM_OUT_RST_RESYNC    = (1 << 30),
+  HRTIM_OUT_RST_SOFT      = (1 << 31),
+};
+
+/* Source which can force the Tx1/Tx2 output to its active state  */
+
+enum stm32_hrtim_out_set_e
+{
+  HRTIM_OUT_SET_UPDATE    = (1 << 0),
+  HRTIM_OUT_SET_EXTEVNT10 = (1 << 1),
+  HRTIM_OUT_SET_EXTEVNT9  = (1 << 2),
+  HRTIM_OUT_SET_EXTEVNT8  = (1 << 3),
+  HRTIM_OUT_SET_EXTEVNT7  = (1 << 4),
+  HRTIM_OUT_SET_EXTEVNT6  = (1 << 5),
+  HRTIM_OUT_SET_EXTEVNT5  = (1 << 6),
+  HRTIM_OUT_SET_EXTEVNT4  = (1 << 7),
+  HRTIM_OUT_SET_EXTEVNT3  = (1 << 8),
+  HRTIM_OUT_SET_EXTEVNT2  = (1 << 9),
+  HRTIM_OUT_SET_EXTEVNT1  = (1 << 10),
+  HRTIM_OUT_SET_TIMEVNT9  = (1 << 11),
+  HRTIM_OUT_SET_TIMEVNT8  = (1 << 12),
+  HRTIM_OUT_SET_TIMEVNT7  = (1 << 13),
+  HRTIM_OUT_SET_TIMEVNT6  = (1 << 14),
+  HRTIM_OUT_SET_TIMEVNT5  = (1 << 15),
+  HRTIM_OUT_SET_TIMEVNT4  = (1 << 16),
+  HRTIM_OUT_SET_TIMEVNT3  = (1 << 17),
+  HRTIM_OUT_SET_TIMEVNT2  = (1 << 18),
+  HRTIM_OUT_SET_TIMEVNT1  = (1 << 19),
+  HRTIM_OUT_SET_MSTCMP4   = (1 << 20),
+  HRTIM_OUT_SET_MSTCMP3   = (1 << 21),
+  HRTIM_OUT_SET_MSTCMP2   = (1 << 22),
+  HRTIM_OUT_SET_MSTCMP1   = (1 << 23),
+  HRTIM_OUT_SET_MSTPER    = (1 << 24),
+  HRTIM_OUT_SET_CMP4      = (1 << 25),
+  HRTIM_OUT_SET_CMP3      = (1 << 26),
+  HRTIM_OUT_SET_CMP2      = (1 << 27),
+  HRTIM_OUT_SET_CMP1      = (1 << 28),
+  HRTIM_OUT_SET_PER       = (1 << 29),
+  HRTIM_OUT_SET_RESYNC    = (1 << 30),
+  HRTIM_OUT_SET_SOFT      = (1 << 31),
+};
+
+/* Events that can reset TimerX Counter */
+
+enum stm32_hrtim_tim_rst_e
+{
+  /* Timer owns events */
+
+  HRTIM_RST_UPDT,
+  HRTIM_RST_CMP4,
+  HRTIM_RST_CMP2,
+
+  /* Master Timer Events */
+
+  HRTIM_RST_MSTCMP4,
+  HRTIM_RST_MSTCMP3,
+  HRTIM_RST_MSTCMP2,
+  HRTIM_RST_MSTCMP1,
+  HRTIM_RST_MSTPER,
+
+  /* TimerX events */
+
+  HRTIM_RST_TECMP4,
+  HRTIM_RST_TECMP2,
+  HRTIM_RST_TECMP1,
+  HRTIM_RST_TDCMP4,
+  HRTIM_RST_TDCMP2,
+  HRTIM_RST_TDCMP1,
+  HRTIM_RST_TCCMP4,
+  HRTIM_RST_TCCMP2,
+  HRTIM_RST_TCCMP1,
+  HRTIM_RST_TBCMP4,
+  HRTIM_RST_TBCMP2,
+  HRTIM_RST_TBCMP1,
+  HRTIM_RST_TACMP4,
+  HRTIM_RST_TACMP2,
+  HRTIM_RST_TACMP1,
+
+  /* External Events */
+
+  HRTIM_RST_EXTEVNT10,
+  HRTIM_RST_EXTEVNT9,
+  HRTIM_RST_EXTEVNT8,
+  HRTIM_RST_EXTEVNT7,
+  HRTIM_RST_EXTEVNT6,
+  HRTIM_RST_EXTEVNT5,
+  HRTIM_RST_EXTEVNT4,
+  HRTIM_RST_EXTEVNT3,
+  HRTIM_RST_EXTEVNT2,
+  HRTIM_RST_EXTEVNT1,
+};
+
+/* HRTIM Timer X prescaler */
+
+enum stm32_hrtim_tim_prescaler_e
+{
+  HRTIM_PRESCALER_1,
+  HRTIM_PRESCALER_2,
+  HRTIM_PRESCALER_4,
+  HRTIM_PRESCALER_8,
+  HRTIM_PRESCALER_16,
+  HRTIM_PRESCALER_32,
+  HRTIM_PRESCALER_64,
+  HRTIM_PRESCALER_128,
+};
+
+/* HRTIM Fault Source */
+
+enum stm32_hrtim_fault_src_e
+{
+  HRTIM_FAULT_SRC_PIN,
+  HRTIM_FAULT_SRC_INTERNAL
+};
+
+/* HRTIM External Event Source
+ * NOTE: according to Table 82 from STM32F334XX Manual
+ */
+
+enum stm32_hrtim_eev_src_e
+{
+  HRTIM_EEV_SRC_PIN,
+  HRTIM_EEV_SRC_ANALOG,
+  HRTIM_EEV_SRC_TRGO,
+  HRTIM_EEV_SRC_ADC
+};
+
+struct hrtim_dev_s
+{
+#ifdef CONFIG_HRTIM
+  /* Fields managed by common upper half HRTIM logic */
+
+  uint8_t                 hd_ocount;    /* The number of times the device has been opened */
+  sem_t                   hd_closesem;  /* Locks out new opens while close is in progress */
+#endif
+
+  /* Fields provided by lower half HRTIM logic */
+
+  FAR void                     *hd_priv; /* Used by the arch-specific logic */
+};
+
+/************************************************************************************
+ * Public Function Prototypes
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Name: stm32_hrtiminitialize
+ *
+ * Description:
+ *   Initialize the HRTIM.
+ *
+ * Input Parameters:
+ *  None
+ *
+ * Returned Value:
+ *   Valid HRTIM device structure reference on succcess; a NULL on failure.
+ *
+ * Assumptions:
+ *   1. Clock to the HRTIM block has enabled,
+ *   2. Board-specific logic has already configured
+ *
+ ****************************************************************************/
+
+FAR struct hrtim_dev_s* stm32_hrtiminitialize(void);
+
+/****************************************************************************
+ * Name: hrtim_register
+ ****************************************************************************/
+
+int hrtim_register(FAR const char *path, FAR struct hrtim_dev_s *dev);
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+#endif /* __ASSEMBLY__ */
+
+#endif /* CONFIG_STM32_HRTIM1 */
+#endif /* __ARCH_ARM_SRC_STM32_STM32_HRTIM_H */
@@ -1,7 +1,7 @@
 /****************************************************************************
 * arch/arm/src/stm32/stm32_irq.c
 *
- *   Copyright (C) 2009-2016 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2009-2017 Gregory Nutt. All rights reserved.
 *   Author: Gregory Nutt <gnutt@nuttx.org>
 *
 * Redistribution and use in source and binary forms, with or without
@@ -387,6 +387,12 @@ void up_irqinitialize(void)
  up_enable_irq(STM32_IRQ_MEMFAULT);
 #endif

+#ifdef CONFIG_RTC
+  /* RTC was initialized earlier but IRQs weren't ready at that time */
+
+  stm32_rtc_irqinitialize();
+#endif
+
  /* Attach all other processor exceptions (except reset and sys tick) */

 #ifdef CONFIG_DEBUG_FEATURES
@@ -1301,7 +1301,7 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv,
  timclk = priv->pclk / prescaler;

  reload = timclk / info->frequency;
-  if (reload < 1)
+  if (reload < 2)
    {
      reload = 1;
    }
@@ -1309,6 +1309,10 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv,
    {
      reload = 65535;
    }
+  else
+    {
+      reload--;
+    }

  pwminfo("TIM%u PCLK: %u frequency: %u TIMCLK: %u prescaler: %u reload: %u\n",
          priv->timid, priv->pclk, info->frequency, timclk, prescaler, reload);
@@ -2,7 +2,7 @@
 * arch/arm/src/stm32/stm32_rtc.h
 *
 *   Copyright (C) 2011 Uros Platise. All rights reserved.
- *   Copyright (C) 2011-2013, 2015-2016 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2011-2013, 2015-2017 Gregory Nutt. All rights reserved.
 *   Author: Uros Platise <uros.platise@isotel.eu> (Original for the F1)
 *           Gregory Nutt <gnutt@nuttx.org> (On-going support and development)
 *
@@ -76,24 +76,41 @@
 * Pre-processor Definitions
 ****************************************************************************/

-#define STM32_RTC_PRESCALER_SECOND  32767  /* Default prescaler to get a second base */
-#define STM32_RTC_PRESCALER_MIN         1  /* Maximum speed of 16384 Hz */
+#define STM32_RTC_PRESCALER_SECOND 32767    /* Default prescaler to get a
+                                             * second base */
+#define STM32_RTC_PRESCALER_MIN    1        /* Maximum speed of 16384 Hz */
+
+#if defined(CONFIG_STM32_STM32F10XX)
+/* RTC is only a counter, store RTC data in backup domain register DR1 (if
+ * CONFIG_RTC_HIRES) and DR2 (state).
+ */

 #if !defined(CONFIG_RTC_MAGIC)
-# define CONFIG_RTC_MAGIC           (0xfacefeee)
+#  define CONFIG_RTC_MAGIC         (0xface) /* only 16 bit */
 #endif

-#if !defined(CONFIG_RTC_MAGIC_TIME_SET)
-#  define CONFIG_RTC_MAGIC_TIME_SET  (CONFIG_RTC_MAGIC + 1)
+#define RTC_MAGIC_REG              STM32_BKP_DR2
+
+#else /* !CONFIG_STM32_STM32F10XX */
+
+#if !defined(CONFIG_RTC_MAGIC)
+#  define CONFIG_RTC_MAGIC         (0xfacefeee)
 #endif

 #if !defined(CONFIG_RTC_MAGIC_REG)
-# define CONFIG_RTC_MAGIC_REG       (0)
+#  define CONFIG_RTC_MAGIC_REG     (0)
 #endif

-#define RTC_MAGIC                   CONFIG_RTC_MAGIC
-#define RTC_MAGIC_TIME_SET          CONFIG_RTC_MAGIC_TIME_SET
-#define RTC_MAGIC_REG               STM32_RTC_BKR(CONFIG_RTC_MAGIC_REG)
+#define RTC_MAGIC_REG              STM32_RTC_BKR(CONFIG_RTC_MAGIC_REG)
+
+#endif /* CONFIG_STM32_STM32F10XX */
+
+#define RTC_MAGIC                  CONFIG_RTC_MAGIC
+#define RTC_MAGIC_TIME_SET         CONFIG_RTC_MAGIC_TIME_SET
+
+#if !defined(CONFIG_RTC_MAGIC_TIME_SET)
+#  define CONFIG_RTC_MAGIC_TIME_SET (CONFIG_RTC_MAGIC + 1)
+#endif

 /****************************************************************************
 * Public Types
@@ -118,6 +135,23 @@ extern "C"
 * Public Functions
 ****************************************************************************/

+/************************************************************************************
+ * Name: stm32_rtc_irqinitialize
+ *
+ * Description:
+ *   Initialize IRQs for RTC, not possible during up_rtc_initialize because
+ *   up_irqinitialize is called later.
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   Zero (OK) on success; a negated errno on failure
+ *
+ ************************************************************************************/
+
+int stm32_rtc_irqinitialize(void);
+
 /****************************************************************************
 * Name: stm32_rtc_getdatetime_with_subseconds
 *
@@ -365,7 +365,11 @@ static int stm32_settime(FAR struct rtc_lowerhalf_s *lower,

 static bool stm32_havesettime(FAR struct rtc_lowerhalf_s *lower)
 {
+#if defined(CONFIG_STM32_STM32F10XX)
+  return getreg16(RTC_MAGIC_REG) == RTC_MAGIC_TIME_SET;
+#else
  return getreg32(RTC_MAGIC_REG) == RTC_MAGIC_TIME_SET;
+#endif
 }

 /****************************************************************************
@@ -1,7 +1,7 @@
 /************************************************************************************
 * arch/arm/src/stm32/stm32_rtcc.c
 *
- *   Copyright (C) 2012-2016 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2012-2017 Gregory Nutt. All rights reserved.
 *   Author: Gregory Nutt <gnutt@nuttx.org>
 *
 * Redistribution and use in source and binary forms, with or without
@@ -763,17 +763,37 @@ int up_rtc_initialize(void)
   * 3. Configure the RTC to generate RTC alarms (Alarm A or Alarm B).
   */

+  g_rtc_enabled = true;
+  rtc_dumpregs("After Initialization");
+  return OK;
+}
+
+/************************************************************************************
+ * Name: stm32_rtc_irqinitialize
+ *
+ * Description:
+ *   Initialize IRQs for RTC, not possible during up_rtc_initialize because
+ *   up_irqinitialize is called later.
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   Zero (OK) on success; a negated errno on failure
+ *
+ ************************************************************************************/
+
+int stm32_rtc_irqinitialize(void)
+{
 #ifdef CONFIG_RTC_ALARM
 #  warning "Missing EXTI setup logic"

-  /* Then attach the ALARM interrupt handler */
+  /* Attach the ALARM interrupt handler */

  irq_attach(STM32_IRQ_RTC_WKUP, rtc_interrupt, NULL);
  up_enable_irq(STM32_IRQ_RTC_WKUP);
 #endif

-  g_rtc_enabled = true;
-  rtc_dumpregs("After Initialization");
  return OK;
 }

@@ -6,7 +6,7 @@
 *
 * With extensions, modifications by:
 *
- *   Copyright (C) 2011-2013, 2015 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2011-2013, 2015, 2017 Gregory Nutt. All rights reserved.
 *   Author: Gregroy Nutt <gnutt@nuttx.org>
 *
 * Redistribution and use in source and binary forms, with or without
@@ -331,7 +331,9 @@ static int stm32_rtc_interrupt(int irq, void *context, FAR void *arg)
 #ifdef CONFIG_RTC_HIRES
  if ((source & RTC_CRL_OWF) != 0)
    {
+      stm32_pwr_enablebkp(true);
      putreg16(getreg16(RTC_TIMEMSB_REG) + 1, RTC_TIMEMSB_REG);
+      stm32_pwr_enablebkp(false);
    }
 #endif

@@ -373,24 +375,33 @@ static int stm32_rtc_interrupt(int irq, void *context, FAR void *arg)

 int up_rtc_initialize(void)
 {
+  uint32_t regval;
+
  /* Enable write access to the backup domain (RTC registers, RTC backup data
   * registers and backup SRAM).
   */

  stm32_pwr_enablebkp(true);

+  regval = getreg32(RTC_MAGIC_REG);
+  if (regval != RTC_MAGIC && regval != RTC_MAGIC_TIME_SET)
+    {
+      /* Reset backup domain if bad magic */
+
+      modifyreg32(STM32_RCC_BDCR, 0, RCC_BDCR_BDRST);
+      modifyreg32(STM32_RCC_BDCR, RCC_BDCR_BDRST, 0);
+      putreg16(RTC_MAGIC, RTC_MAGIC_REG);
+    }
+  
  /* Select the lower power external 32,768Hz (Low-Speed External, LSE) oscillator
-   * as RTC Clock Source and enable the Clock */
-  
-  modifyreg16(STM32_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_LSE);
-  modifyreg16(STM32_RCC_BDCR, 0, RCC_BDCR_RTCEN);
-
-  /* TODO: Get state from this function, if everything is
-   *   okay and whether it is already enabled (if it was disabled
-   *   reset upper time register)
+   * as RTC Clock Source and enable the Clock.
   */
  
-  g_rtc_enabled = true;
+  modifyreg16(STM32_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_LSE);
+
+  /* Enable RTC and wait for RSF */
+
+  modifyreg16(STM32_RCC_BDCR, 0, RCC_BDCR_RTCEN);

  /* TODO: Possible stall? should we set the timeout period? and return with -1 */

@@ -403,21 +414,22 @@ int up_rtc_initialize(void)
  putreg16(STM32_RTC_PRESCALAR_VALUE & 0xffff, STM32_RTC_PRLL);
  stm32_rtc_endwr();

-  /* Configure RTC interrupt to catch overflow and alarm interrupts. */
+  stm32_rtc_wait4rsf();

-#if defined(CONFIG_RTC_HIRES) || defined(CONFIG_RTC_ALARM)
-  irq_attach(STM32_IRQ_RTC, stm32_rtc_interrupt, NULL);
-  up_enable_irq(STM32_IRQ_RTC);
-#endif
-
-  /* Previous write is done? This is required prior writing into CRH */
-
-  while ((getreg16(STM32_RTC_CRL) & RTC_CRL_RTOFF) == 0)
-    {
-      up_waste();
-    }
+#ifdef CONFIG_RTC_HIRES
+  /* Enable overflow interrupt - alarm interrupt is enabled in
+   * stm32_rtc_setalarm.
+   */

  modifyreg16(STM32_RTC_CRH, 0, RTC_CRH_OWIE);
+#endif
+
+  /* TODO: Get state from this function, if everything is
+   *   okay and whether it is already enabled (if it was disabled
+   *   reset upper time register)
+   */
+
+  g_rtc_enabled = true;

  /* Alarm Int via EXTI Line */

@@ -432,6 +444,33 @@ int up_rtc_initialize(void)
  return OK;
 }

+/************************************************************************************
+ * Name: stm32_rtc_irqinitialize
+ *
+ * Description:
+ *   Initialize IRQs for RTC, not possible during up_rtc_initialize because
+ *   up_irqinitialize is called later.
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   Zero (OK) on success; a negated errno on failure
+ *
+ ************************************************************************************/
+
+int stm32_rtc_irqinitialize(void)
+{
+#if defined(CONFIG_RTC_HIRES) || defined(CONFIG_RTC_ALARM)
+  /* Configure RTC interrupt to catch overflow and alarm interrupts. */
+
+  irq_attach(STM32_IRQ_RTC, stm32_rtc_interrupt, NULL);
+  up_enable_irq(STM32_IRQ_RTC);
+#endif
+
+  return OK;
+}
+
 /************************************************************************************
 * Name: up_rtc_time
 *
@@ -613,6 +652,7 @@ int up_rtc_settime(FAR const struct timespec *tp)
  do
    {
      stm32_rtc_beginwr();
+      putreg16(RTC_MAGIC, RTC_MAGIC_TIME_SET);
      putreg16(regvals.cnth, STM32_RTC_CNTH);
      putreg16(regvals.cntl, STM32_RTC_CNTL);
      cntl = getreg16(STM32_RTC_CNTL);
@@ -652,6 +692,8 @@ int stm32_rtc_setalarm(FAR const struct timespec *tp, alarmcb_t callback)
  uint16_t cr;
  int ret = -EBUSY;

+  flags = enter_critical_section();
+
  /* Is there already something waiting on the ALARM? */

  if (g_alarmcb == NULL)
@@ -664,6 +706,8 @@ int stm32_rtc_setalarm(FAR const struct timespec *tp, alarmcb_t callback)

      stm32_rtc_breakout(tp, &regvals);

+      stm32_pwr_enablebkp(true);
+
      /* Enable RTC alarm */

      cr  = getreg16(STM32_RTC_CRH);
@@ -672,16 +716,18 @@ int stm32_rtc_setalarm(FAR const struct timespec *tp, alarmcb_t callback)

      /* The set the alarm */

-      flags = enter_critical_section();
      stm32_rtc_beginwr();
      putreg16(regvals.cnth, STM32_RTC_ALRH);
      putreg16(regvals.cntl, STM32_RTC_ALRL);
      stm32_rtc_endwr();
-      leave_critical_section(flags);
+
+      stm32_pwr_enablebkp(false);

      ret = OK;
    }

+  leave_critical_section(flags);
+
  return ret;
 }
 #endif
@@ -706,6 +752,8 @@ int stm32_rtc_cancelalarm(void)
  irqstate_t flags;
  int ret = -ENODATA;

+  flags = enter_critical_section();
+
  if (g_alarmcb != NULL)
    {
      /* Cancel the global callback function */
@@ -714,16 +762,18 @@ int stm32_rtc_cancelalarm(void)

      /* Unset the alarm */

-      flags = enter_critical_section();
+      stm32_pwr_enablebkp(true);
      stm32_rtc_beginwr();
      putreg16(0xffff, STM32_RTC_ALRH);
      putreg16(0xffff, STM32_RTC_ALRL);
      stm32_rtc_endwr();
-      leave_critical_section(flags);
+      stm32_pwr_enablebkp(false);

      ret = OK;
    }

+  leave_critical_section(flags);
+
  return ret;
 }
 #endif
@@ -332,9 +332,7 @@ static inline void rcc_enableapb2(void)
 #ifdef CONFIG_STM32_HRTIM1
  /* HRTIM1 Timer clock enable */

-#ifdef CONFIG_STM32_FORCEPOWER
  regval |= RCC_APB2ENR_HRTIM1EN;
-#endif
 #endif

  putreg32(regval, STM32_RCC_APB2ENR);
@@ -1058,6 +1058,28 @@ int up_rtc_initialize(void)
  return OK;
 }

+/************************************************************************************
+ * Name: stm32_rtc_irqinitialize
+ *
+ * Description:
+ *   Initialize IRQs for RTC, not possible during up_rtc_initialize because
+ *   up_irqinitialize is called later.
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   Zero (OK) on success; a negated errno on failure
+ *
+ ************************************************************************************/
+
+int stm32_rtc_irqinitialize(void)
+{
+  /* Nothing to do */
+
+  return OK;
+}
+
 /****************************************************************************
 * Name: stm32_rtc_getdatetime_with_subseconds
 *
@@ -220,6 +220,54 @@ config ARCH_CHIP_STM32L462VE
 	---help---
 		STM32 L4 Cortex M4, USB FS, AES, 512 Kb FLASH, 128+32 Kb SRAM

+config ARCH_CHIP_STM32L475RG
+	bool "STM32L475RG"
+	select STM32L4_STM32L475XX
+	select STM32L4_FLASH_CONFIG_G
+	select STM32L4_IO_CONFIG_R
+	---help---
+		STM32 L4 Cortex M4, 1024Kb FLASH, 96+32 Kb SRAM, LQFP100
+
+config ARCH_CHIP_STM32L475RE
+	bool "STM32L475RE"
+	select STM32L4_STM32L475XX
+	select STM32L4_FLASH_CONFIG_E
+	select STM32L4_IO_CONFIG_R
+	---help---
+		STM32 L4 Cortex M4, 512Kb FLASH, 96+32 Kb SRAM, LQFP100
+
+config ARCH_CHIP_STM32L475RC
+	bool "STM32L475RC"
+	select STM32L4_STM32L475XX
+	select STM32L4_FLASH_CONFIG_E
+	select STM32L4_IO_CONFIG_R
+	---help---
+		STM32 L4 Cortex M4, 256Kb FLASH, 96+32 Kb SRAM, LQFP100
+
+config ARCH_CHIP_STM32L475VG
+	bool "STM32L475VG"
+	select STM32L4_STM32L475XX
+	select STM32L4_FLASH_CONFIG_G
+	select STM32L4_IO_CONFIG_R
+	---help---
+		STM32 L4 Cortex M4, 1024Kb FLASH, 96+32 Kb SRAM, LQFP64
+
+config ARCH_CHIP_STM32L475VE
+	bool "STM32L475VE"
+	select STM32L4_STM32L475XX
+	select STM32L4_FLASH_CONFIG_E
+	select STM32L4_IO_CONFIG_R
+	---help---
+		STM32 L4 Cortex M4, 512Kb FLASH, 96+32 Kb SRAM, LQFP64
+
+config ARCH_CHIP_STM32L475VC
+	bool "STM32L475VC"
+	select STM32L4_STM32L475XX
+	select STM32L4_FLASH_CONFIG_E
+	select STM32L4_IO_CONFIG_R
+	---help---
+		STM32 L4 Cortex M4, 256Kb FLASH, 96+32 Kb SRAM, LQFP64
+
 config ARCH_CHIP_STM32L476RG
 	bool "STM32L476RG"
 	select STM32L4_STM32L476XX
@@ -322,6 +370,33 @@ config STM32L4_STM32L4X5
 	select STM32L4_HAVE_OTGFS
 	select STM32L4_HAVE_DFSDM1

+config STM32L4_STM32L4X5
+	bool
+	default n
+	select ARCH_HAVE_FPU
+	select STM32L4_HAVE_USART1
+	select STM32L4_HAVE_USART2
+	select STM32L4_HAVE_USART3
+	select STM32L4_HAVE_UART4
+	select STM32L4_HAVE_UART5
+	select STM32L4_HAVE_ADC2
+	select STM32L4_HAVE_ADC3
+	select STM32L4_HAVE_DAC2
+	select STM32L4_HAVE_FSMC
+	select STM32L4_HAVE_TIM3
+	select STM32L4_HAVE_TIM4
+	select STM32L4_HAVE_TIM5
+	select STM32L4_HAVE_TIM7
+	select STM32L4_HAVE_TIM8
+	select STM32L4_HAVE_TIM17
+	select STM32L4_HAVE_LPTIM1
+	select STM32L4_HAVE_LPTIM2
+	select STM32L4_HAVE_COMP
+	select STM32L4_HAVE_SAI1
+	select STM32L4_HAVE_SAI2
+	select STM32L4_HAVE_SDMMC1
+	select STM32L4_HAVE_OTGFS
+
 config STM32L4_STM32L4X6
 	bool
 	default n
@@ -422,6 +497,11 @@ config STM32L4_STM32L471XX
 	default n
 	# TODO

+config STM32L4_STM32L475XX
+	bool
+	default n
+	select STM32L4_STM32L4X5
+
 config STM32L4_STM32L476XX
 	bool
 	default n
@@ -51,6 +51,10 @@
 #include "chip/stm32l4_pinmap.h"
 #include "chip/stm32l4_memorymap.h"

+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
 /* If the common ARMv7-M vector handling logic is used, then it expects the
 * following definition in this file that provides the number of supported external
 * interrupts which, for this architecture, is provided in the arch/stm32l4/chip.h
@@ -64,20 +68,4 @@
 #define ARMV7M_DCACHE_LINESIZE 0  /* no cache */
 #define ARMV7M_ICACHE_LINESIZE 0  /* no cache */

-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
-
 #endif /* __ARCH_ARM_SRC_STM32L4_CHIP_H */
@@ -1,6 +1,7 @@
 /************************************************************************************
 * arch/arm/src/stm32l4/chip/stm32l4_pinmap.h
 *
+ *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
 *   Copyright (C) 2015 Sebastien Lorquet. All rights reserved.
 *   Author: Sebastien Lorquet <sebastien@lorquet.fr>
 *
@@ -43,10 +44,12 @@
 #include <nuttx/config.h>
 #include "chip.h"

-#if defined(CONFIG_STM32L4_STM32L4X6)
-#  include "chip/stm32l4x6xx_pinmap.h"
-#elif defined(CONFIG_STM32L4_STM32L4X3)
+#if defined(CONFIG_STM32L4_STM32L4X3)
 #  include "chip/stm32l4x3xx_pinmap.h"
+#elif defined(CONFIG_STM32L4_STM32L4X5)
+#  include "chip/stm32l4x5xx_pinmap.h"
+#elif defined(CONFIG_STM32L4_STM32L4X6)
+#  include "chip/stm32l4x6xx_pinmap.h"
 #else
 #  error "Unsupported STM32 L4 pin map"
 #endif
@@ -43,13 +43,14 @@
 #include <nuttx/config.h>
 #include "chip.h"

-#if defined(CONFIG_STM32L4_STM32L4X6)
-#  include "chip/stm32l4x6xx_syscfg.h"
-#elif defined(CONFIG_STM32L4_STM32L4X3)
+#if defined(CONFIG_STM32L4_STM32L4X3)
 #  include "chip/stm32l4x3xx_syscfg.h"
+#elif defined(CONFIG_STM32L4_STM32L4X5)
+#  include "chip/stm32l4x5xx_syscfg.h"
+#elif defined(CONFIG_STM32L4_STM32L4X6)
+#  include "chip/stm32l4x6xx_syscfg.h"
 #else
 #  error "Unsupported STM32 L4 chip"
 #endif

 #endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_SYSCFG_H */
-
@@ -126,7 +126,7 @@
 #define RCC_CR_MSION                (1 << 0)  /* Bit 0: Internal Multi Speed clock enable */
 #define RCC_CR_MSIRDY               (1 << 1)  /* Bit 1: Internal Multi Speed clock ready flag */
 #define RCC_CR_MSIPLLEN             (1 << 2)  /* Bit 2: MSI clock PLL enable */
-#define RCC_CR_MSIRGSEL             (1 << 3)  /* Bit 2: MSI clock range selection */
+#define RCC_CR_MSIRGSEL             (1 << 3)  /* Bit 3: MSI clock range selection */
 #define RCC_CR_MSIRANGE_SHIFT       (4)       /* Bits 7-4: MSI clock range */
 #define RCC_CR_MSIRANGE_MASK        (0x0f << RCC_CR_MSIRANGE_SHIFT)
 #  define RCC_CR_MSIRANGE_100K      (0  << RCC_CR_MSIRANGE_SHIFT) /* 0000: around 100 kHz */
@@ -0,0 +1,113 @@
+/****************************************************************************
+ * arch/arm/src/stm32l4/chip/stm32l4x5xx_dbgmcu.h
+ *
+ *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
+ *   Authors: Gregory Nutt <gnutt@nuttx.org>
+ *            David Sidrane <david_s5@nscdg.com>
+ *            Juha Niskanen <juha.niskanen@haltian.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X5XX_DBGMCU_H
+#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X5XX_DBGMCU_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "chip.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Register Addresses *******************************************************/
+
+#define STM32_DBGMCU_IDCODE       0xe0042000  /* MCU identifier */
+#define STM32_DBGMCU_CR           0xe0042004  /* MCU debug */
+#define STM32_DBGMCU_APB1_FZ      0xe0042008  /* Debug MCU APB1 freeze register */
+#define STM32_DBGMCU_APB1_FZ2     0xe004200c  /* Debug MCU APB1 freeze register 2 */
+#define STM32_DBGMCU_APB2_FZ      0xe0042010  /* Debug MCU APB2 freeze register */
+
+/* Register Bitfield Definitions ********************************************/
+
+/* MCU identifier */
+
+#define DBGMCU_IDCODE_DEVID_SHIFT (0)       /* Bits 11-0: Device Identifier */
+#define DBGMCU_IDCODE_DEVID_MASK  (0x0fff << DBGMCU_IDCODE_DEVID_SHIFT)
+#define DBGMCU_IDCODE_REVID_SHIFT (16)      /* Bits 31-16:  Revision Identifier */
+#define DBGMCU_IDCODE_REVID_MASK  (0xffff << DBGMCU_IDCODE_REVID_SHIFT)
+
+/* MCU debug */
+
+#define DBGMCU_CR_SLEEP           (1 << 0)  /* Bit 0: Debug Sleep Mode */
+#define DBGMCU_CR_STOP            (1 << 1)  /* Bit 1: Debug Stop Mode */
+#define DBGMCU_CR_STANDBY         (1 << 2)  /* Bit 2: Debug Standby mode */
+#define DBGMCU_CR_TRACEIOEN       (1 << 5)  /* Bit 5: Trace enabled */
+
+#define DBGMCU_CR_TRACEMODE_SHIFT (6)       /* Bits 7-6: Trace mode pin assignment */
+#define DBGMCU_CR_TRACEMODE_MASK  (3 << DBGMCU_CR_TRACEMODE_SHIFT)
+#  define DBGMCU_CR_ASYNCH        (0 << DBGMCU_CR_TRACEMODE_SHIFT) /* Asynchronous Mode */
+#  define DBGMCU_CR_SYNCH1        (1 << DBGMCU_CR_TRACEMODE_SHIFT) /* Synchronous Mode, TRACEDATA size=1 */
+#  define DBGMCU_CR_SYNCH2        (2 << DBGMCU_CR_TRACEMODE_SHIFT) /* Synchronous Mode, TRACEDATA size=2 */
+#  define DBGMCU_CR_SYNCH4        (3 << DBGMCU_CR_TRACEMODE_SHIFT) /* Synchronous Mode, TRACEDATA size=4 */
+
+/* Debug MCU APB1 freeze register */
+
+#define DBGMCU_APB1_TIM2STOP      (1 << 0)   /* Bit 0: TIM2 stopped when core is halted */
+#define DBGMCU_APB1_TIM3STOP      (1 << 1)   /* Bit 1: TIM3 stopped when core is halted */
+#define DBGMCU_APB1_TIM4STOP      (1 << 2)   /* Bit 2: TIM4 stopped when core is halted */
+#define DBGMCU_APB1_TIM5STOP      (1 << 3)   /* Bit 3: TIM5 stopped when core is halted */
+#define DBGMCU_APB1_TIM6STOP      (1 << 4)   /* Bit 4: TIM6 stopped when core is halted */
+#define DBGMCU_APB1_TIM7STOP      (1 << 5)   /* Bit 5: TIM7 stopped when core is halted */
+#define DBGMCU_APB1_RTCSTOP       (1 << 10)  /* Bit 10: RTC stopped when Core is halted */
+#define DBGMCU_APB1_WWDGSTOP      (1 << 11)  /* Bit 11: Window Watchdog stopped when core is halted */
+#define DBGMCU_APB1_IWDGSTOP      (1 << 12)  /* Bit 12: Independent Watchdog stopped when core is halted */
+#define DBGMCU_APB1_I2C1STOP      (1 << 21)  /* Bit 21: I2C1 SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_APB1_I2C2STOP      (1 << 22)  /* Bit 22: I2C2 SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_APB1_I2C3STOP      (1 << 23)  /* Bit 23: I2C3 SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_APB1_CAN1STOP      (1 << 25)  /* Bit 25: CAN1 stopped when core is halted */
+#define DBGMCU_APB1_LPTIM1STOP    (1 << 31)  /* Bit 31: LPTIM1 stopper when core is halted */
+
+/* Debug MCU APB1 freeze register 2 */
+
+#define DBGMCU_APB1_FZ2_LPTIM2STOP (1 << 5)  /* Bit 5: LPTIM2 stopper when core is halted */
+
+/* Debug MCU APB2 freeze register */
+
+#define DBGMCU_APB2_TIM1STOP      (1 << 11)  /* Bit 11: TIM1 stopped when core is halted */
+#define DBGMCU_APB2_TIM8STOP      (1 << 13)  /* Bit 13: TIM8 stopped when core is halted */
+#define DBGMCU_APB2_TIM15STOP     (1 << 16)  /* Bit 16: TIM15 stopped when core is halted */
+#define DBGMCU_APB2_TIM16STOP     (1 << 17)  /* Bit 17: TIM16 stopped when core is halted */
+#define DBGMCU_APB2_TIM17STOP     (1 << 18)  /* Bit 18: TIM17 stopped when core is halted */
+
+#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X5XXDBGMCU_H */
@@ -0,0 +1,485 @@
+/************************************************************************************
+ * arch/arm/src/stm32l4/chip/stm32l4x6xx_dma.h
+ *
+ *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X5XX_DMA_H
+#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X5XX_DMA_H
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+/* 14 Channels Total: 7 DMA1 Channels(1-7) and 7 DMA2 channels (1-7) */
+
+#define DMA1 0
+#define DMA2 1
+#define DMA3 2
+#define DMA4 3
+#define DMA5 4
+#define DMA6 5
+#define DMA7 6
+
+/* Register Offsets *****************************************************************/
+
+#define STM32L4_DMA_ISR_OFFSET       0x0000 /* DMA interrupt status register */
+#define STM32L4_DMA_IFCR_OFFSET      0x0004 /* DMA interrupt flag clear register */
+
+#define STM32L4_DMACHAN_OFFSET(n)    (0x0014*(n))
+#define STM32L4_DMACHAN1_OFFSET      0x0000
+#define STM32L4_DMACHAN2_OFFSET      0x0014
+#define STM32L4_DMACHAN3_OFFSET      0x0028
+#define STM32L4_DMACHAN4_OFFSET      0x003c
+#define STM32L4_DMACHAN5_OFFSET      0x0050
+#define STM32L4_DMACHAN6_OFFSET      0x0064
+#define STM32L4_DMACHAN7_OFFSET      0x0078
+
+#define STM32L4_DMACHAN_CCR_OFFSET   0x0008 /* DMA channel configuration register */
+#define STM32L4_DMACHAN_CNDTR_OFFSET 0x000c /* DMA channel number of data register */
+#define STM32L4_DMACHAN_CPAR_OFFSET  0x0010 /* DMA channel peripheral address register */
+#define STM32L4_DMACHAN_CMAR_OFFSET  0x0014 /* DMA channel memory address register */
+
+#define STM32L4_DMA_CCR_OFFSET(n)   (STM32L4_DMACHAN_CCR_OFFSET+STM32L4_DMACHAN_OFFSET(n))
+#define STM32L4_DMA_CNDTR_OFFSET(n) (STM32L4_DMACHAN_CNDTR_OFFSET+STM32L4_DMACHAN_OFFSET(n))
+#define STM32L4_DMA_CPAR_OFFSET(n)  (STM32L4_DMACHAN_CPAR_OFFSET+STM32L4_DMACHAN_OFFSET(n))
+#define STM32L4_DMA_CMAR_OFFSET(n)  (STM32L4_DMACHAN_CMAR_OFFSET+STM32L4_DMACHAN_OFFSET(n))
+
+#define STM32L4_DMA_CCR1_OFFSET     0x0008 /* DMA channel 1 configuration register */
+#define STM32L4_DMA_CCR2_OFFSET     0x001c /* DMA channel 2 configuration register */
+#define STM32L4_DMA_CCR3_OFFSET     0x0030 /* DMA channel 3 configuration register */
+#define STM32L4_DMA_CCR4_OFFSET     0x0044 /* DMA channel 4 configuration register */
+#define STM32L4_DMA_CCR5_OFFSET     0x0058 /* DMA channel 5 configuration register */
+#define STM32L4_DMA_CCR6_OFFSET     0x006c /* DMA channel 6 configuration register */
+#define STM32L4_DMA_CCR7_OFFSET     0x0080 /* DMA channel 7 configuration register */
+
+#define STM32L4_DMA_CNDTR1_OFFSET   0x000c /* DMA channel 1 number of data register */
+#define STM32L4_DMA_CNDTR2_OFFSET   0x0020 /* DMA channel 2 number of data register */
+#define STM32L4_DMA_CNDTR3_OFFSET   0x0034 /* DMA channel 3 number of data register */
+#define STM32L4_DMA_CNDTR4_OFFSET   0x0048 /* DMA channel 4 number of data register */
+#define STM32L4_DMA_CNDTR5_OFFSET   0x005c /* DMA channel 5 number of data register */
+#define STM32L4_DMA_CNDTR6_OFFSET   0x0070 /* DMA channel 6 number of data register */
+#define STM32L4_DMA_CNDTR7_OFFSET   0x0084 /* DMA channel 7 number of data register */
+
+#define STM32L4_DMA_CPAR1_OFFSET    0x0010 /* DMA channel 1 peripheral address register */
+#define STM32L4_DMA_CPAR2_OFFSET    0x0024 /* DMA channel 2 peripheral address register */
+#define STM32L4_DMA_CPAR3_OFFSET    0x0038 /* DMA channel 3 peripheral address register */
+#define STM32L4_DMA_CPAR4_OFFSET    0x004c /* DMA channel 4 peripheral address register */
+#define STM32L4_DMA_CPAR5_OFFSET    0x0060 /* DMA channel 5 peripheral address register */
+#define STM32L4_DMA_CPAR6_OFFSET    0x0074 /* DMA channel 6 peripheral address register */
+#define STM32L4_DMA_CPAR7_OFFSET    0x0088 /* DMA channel 7 peripheral address register */
+
+#define STM32L4_DMA_CMAR1_OFFSET    0x0014 /* DMA channel 1 memory address register */
+#define STM32L4_DMA_CMAR2_OFFSET    0x0028 /* DMA channel 2 memory address register */
+#define STM32L4_DMA_CMAR3_OFFSET    0x003c /* DMA channel 3 memory address register */
+#define STM32L4_DMA_CMAR4_OFFSET    0x0050 /* DMA channel 4 memory address register */
+#define STM32L4_DMA_CMAR5_OFFSET    0x0064 /* DMA channel 5 memory address register */
+#define STM32L4_DMA_CMAR6_OFFSET    0x0078 /* DMA channel 6 memory address register */
+#define STM32L4_DMA_CMAR7_OFFSET    0x008c /* DMA channel 7 memory address register */
+
+#define STM32L4_DMA_CSELR_OFFSET    0x00a8 /* DMA channel selection register */
+
+/* Register Addresses ***************************************************************/
+
+#define STM32L4_DMA1_ISRC           (STM32L4_DMA1_BASE+STM32L4_DMA_ISR_OFFSET)
+#define STM32L4_DMA1_IFCR           (STM32L4_DMA1_BASE+STM32L4_DMA_IFCR_OFFSET)
+
+#define STM32L4_DMA1_CCR(n)         (STM32L4_DMA1_BASE+STM32L4_DMA_CCR_OFFSET(n))
+#define STM32L4_DMA1_CCR1           (STM32L4_DMA1_BASE+STM32L4_DMA_CCR1_OFFSET)
+#define STM32L4_DMA1_CCR2           (STM32L4_DMA1_BASE+STM32L4_DMA_CCR2_OFFSET)
+#define STM32L4_DMA1_CCR3           (STM32L4_DMA1_BASE+STM32L4_DMA_CCR3_OFFSET)
+#define STM32L4_DMA1_CCR4           (STM32L4_DMA1_BASE+STM32L4_DMA_CCR4_OFFSET)
+#define STM32L4_DMA1_CCR5           (STM32L4_DMA1_BASE+STM32L4_DMA_CCR5_OFFSET)
+#define STM32L4_DMA1_CCR6           (STM32L4_DMA1_BASE+STM32L4_DMA_CCR6_OFFSET)
+#define STM32L4_DMA1_CCR7           (STM32L4_DMA1_BASE+STM32L4_DMA_CCR7_OFFSET)
+
+#define STM32L4_DMA1_CNDTR(n)       (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR_OFFSET(n))
+#define STM32L4_DMA1_CNDTR1         (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR1_OFFSET)
+#define STM32L4_DMA1_CNDTR2         (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR2_OFFSET)
+#define STM32L4_DMA1_CNDTR3         (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR3_OFFSET)
+#define STM32L4_DMA1_CNDTR4         (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR4_OFFSET)
+#define STM32L4_DMA1_CNDTR5         (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR5_OFFSET)
+#define STM32L4_DMA1_CNDTR6         (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR6_OFFSET)
+#define STM32L4_DMA1_CNDTR7         (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR7_OFFSET)
+
+#define STM32L4_DMA1_CPAR(n)        (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR_OFFSET(n))
+#define STM32L4_DMA1_CPAR1          (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR1_OFFSET)
+#define STM32L4_DMA1_CPAR2          (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR2_OFFSET)
+#define STM32L4_DMA1_CPAR3          (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR3_OFFSET)
+#define STM32L4_DMA1_CPAR4          (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR4_OFFSET)
+#define STM32L4_DMA1_CPAR5          (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR5_OFFSET)
+#define STM32L4_DMA1_CPAR6          (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR6_OFFSET)
+#define STM32L4_DMA1_CPAR7          (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR7_OFFSET)
+
+#define STM32L4_DMA1_CMAR(n)        (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR_OFFSET(n))
+#define STM32L4_DMA1_CMAR1          (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR1_OFFSET)
+#define STM32L4_DMA1_CMAR2          (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR2_OFFSET)
+#define STM32L4_DMA1_CMAR3          (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR3_OFFSET)
+#define STM32L4_DMA1_CMAR4          (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR4_OFFSET)
+#define STM32L4_DMA1_CMAR5          (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR5_OFFSET)
+#define STM32L4_DMA1_CMAR6          (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR6_OFFSET)
+#define STM32L4_DMA1_CMAR7          (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR7_OFFSET)
+
+#define STM32L4_DMA2_ISRC           (STM32L4_DMA2_BASE+STM32L4_DMA_ISR_OFFSET)
+#define STM32L4_DMA2_IFCR           (STM32L4_DMA2_BASE+STM32L4_DMA_IFCR_OFFSET)
+
+#define STM32L4_DMA2_CCR(n)         (STM32L4_DMA2_BASE+STM32L4_DMA_CCR_OFFSET(n))
+#define STM32L4_DMA2_CCR1           (STM32L4_DMA2_BASE+STM32L4_DMA_CCR1_OFFSET)
+#define STM32L4_DMA2_CCR2           (STM32L4_DMA2_BASE+STM32L4_DMA_CCR2_OFFSET)
+#define STM32L4_DMA2_CCR3           (STM32L4_DMA2_BASE+STM32L4_DMA_CCR3_OFFSET)
+#define STM32L4_DMA2_CCR4           (STM32L4_DMA2_BASE+STM32L4_DMA_CCR4_OFFSET)
+#define STM32L4_DMA2_CCR5           (STM32L4_DMA2_BASE+STM32L4_DMA_CCR5_OFFSET)
+#define STM32L4_DMA2_CCR6           (STM32L4_DMA2_BASE+STM32L4_DMA_CCR6_OFFSET)
+#define STM32L4_DMA2_CCR7           (STM32L4_DMA2_BASE+STM32L4_DMA_CCR7_OFFSET)
+
+#define STM32L4_DMA2_CNDTR(n)       (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR_OFFSET(n))
+#define STM32L4_DMA2_CNDTR1         (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR1_OFFSET)
+#define STM32L4_DMA2_CNDTR2         (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR2_OFFSET)
+#define STM32L4_DMA2_CNDTR3         (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR3_OFFSET)
+#define STM32L4_DMA2_CNDTR4         (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR4_OFFSET)
+#define STM32L4_DMA2_CNDTR5         (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR5_OFFSET)
+#define STM32L4_DMA2_CNDTR6         (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR6_OFFSET)
+#define STM32L4_DMA2_CNDTR7         (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR7_OFFSET)
+
+#define STM32L4_DMA2_CPAR(n)        (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR_OFFSET(n))
+#define STM32L4_DMA2_CPAR1          (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR1_OFFSET)
+#define STM32L4_DMA2_CPAR2          (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR2_OFFSET)
+#define STM32L4_DMA2_CPAR3          (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR3_OFFSET)
+#define STM32L4_DMA2_CPAR4          (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR4_OFFSET)
+#define STM32L4_DMA2_CPAR5          (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR5_OFFSET)
+#define STM32L4_DMA2_CPAR6          (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR6_OFFSET)
+#define STM32L4_DMA2_CPAR7          (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR7_OFFSET)
+
+#define STM32L4_DMA2_CMAR(n)        (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR_OFFSET(n))
+#define STM32L4_DMA2_CMAR1          (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR1_OFFSET)
+#define STM32L4_DMA2_CMAR2          (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR2_OFFSET)
+#define STM32L4_DMA2_CMAR3          (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR3_OFFSET)
+#define STM32L4_DMA2_CMAR4          (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR4_OFFSET)
+#define STM32L4_DMA2_CMAR5          (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR5_OFFSET)
+#define STM32L4_DMA2_CMAR6          (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR6_OFFSET)
+#define STM32L4_DMA2_CMAR7          (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR7_OFFSET)
+
+/* Register Bitfield Definitions ****************************************************/
+
+#define DMA_CHAN_SHIFT(n)         ((n) << 2)
+#define DMA_CHAN_MASK             0x0f
+#define DMA_CHAN_GIF_BIT          (1 << 0)  /* Bit 0: Channel Global interrupt flag */
+#define DMA_CHAN_TCIF_BIT         (1 << 1)  /* Bit 1: Channel Transfer Complete flag */
+#define DMA_CHAN_HTIF_BIT         (1 << 2)  /* Bit 2: Channel Half Transfer flag */
+#define DMA_CHAN_TEIF_BIT         (1 << 3)  /* Bit 3: Channel Transfer Error flag */
+
+/* DMA interrupt status register */
+
+#define DMA_ISR_CHAN_SHIFT(n)     DMA_CHAN_SHIFT(n)
+#define DMA_ISR_CHAN_MASK(n)      (DMA_CHAN_MASK <<  DMA_ISR_CHAN_SHIFT(n))
+#define DMA_ISR_CHAN1_SHIFT       (0)       /* Bits 3-0:  DMA Channel 1 interrupt status */
+#define DMA_ISR_CHAN1_MASK        (DMA_CHAN_MASK <<  DMA_ISR_CHAN1_SHIFT)
+#define DMA_ISR_CHAN2_SHIFT       (4)       /* Bits 7-4:  DMA Channel 2 interrupt status */
+#define DMA_ISR_CHAN2_MASK        (DMA_CHAN_MASK <<  DMA_ISR_CHAN2_SHIFT)
+#define DMA_ISR_CHAN3_SHIFT       (8)       /* Bits 11-8:  DMA Channel 3 interrupt status */
+#define DMA_ISR_CHAN3_MASK        (DMA_CHAN_MASK <<  DMA_ISR_CHAN3_SHIFT)
+#define DMA_ISR_CHAN4_SHIFT       (12)      /* Bits 15-12:  DMA Channel 4 interrupt status */
+#define DMA_ISR_CHAN4_MASK        (DMA_CHAN_MASK <<  DMA_ISR_CHAN4_SHIFT)
+#define DMA_ISR_CHAN5_SHIFT       (16)      /* Bits 19-16:  DMA Channel 5 interrupt status */
+#define DMA_ISR_CHAN5_MASK        (DMA_CHAN_MASK <<  DMA_ISR_CHAN5_SHIFT)
+#define DMA_ISR_CHAN6_SHIFT       (20)      /* Bits 23-20:  DMA Channel 6 interrupt status */
+#define DMA_ISR_CHAN6_MASK        (DMA_CHAN_MASK <<  DMA_ISR_CHAN6_SHIFT)
+#define DMA_ISR_CHAN7_SHIFT       (24)      /* Bits 27-24:  DMA Channel 7 interrupt status */
+#define DMA_ISR_CHAN7_MASK        (DMA_CHAN_MASK <<  DMA_ISR_CHAN7_SHIFT)
+
+#define DMA_ISR_GIF(n)            (DMA_CHAN_GIF_BIT << DMA_ISR_CHAN_SHIFT(n))
+#define DMA_ISR_TCIF(n)           (DMA_CHAN_TCIF_BIT << DMA_ISR_CHAN_SHIFT(n))
+#define DMA_ISR_HTIF(n)           (DMA_CHAN_HTIF_BIT << DMA_ISR_CHAN_SHIFT(n))
+#define DMA_ISR_TEIF(n)           (DMA_CHAN_TEIF_BIT << DMA_ISR_CHAN_SHIFT(n))
+
+/* DMA interrupt flag clear register */
+
+#define DMA_IFCR_CHAN_SHIFT(n)    DMA_CHAN_SHIFT(n)
+#define DMA_IFCR_CHAN_MASK(n)     (DMA_CHAN_MASK <<  DMA_IFCR_CHAN_SHIFT(n))
+#define DMA_IFCR_CHAN1_SHIFT      (0)       /* Bits 3-0:  DMA Channel 1 interrupt flag clear */
+#define DMA_IFCR_CHAN1_MASK       (DMA_CHAN_MASK <<  DMA_IFCR_CHAN1_SHIFT)
+#define DMA_IFCR_CHAN2_SHIFT      (4)       /* Bits 7-4:  DMA Channel 2 interrupt flag clear */
+#define DMA_IFCR_CHAN2_MASK       (DMA_CHAN_MASK <<  DMA_IFCR_CHAN2_SHIFT)
+#define DMA_IFCR_CHAN3_SHIFT      (8)       /* Bits 11-8:  DMA Channel 3 interrupt flag clear */
+#define DMA_IFCR_CHAN3_MASK       (DMA_CHAN_MASK <<  DMA_IFCR_CHAN3_SHIFT)
+#define DMA_IFCR_CHAN4_SHIFT      (12)      /* Bits 15-12:  DMA Channel 4 interrupt flag clear */
+#define DMA_IFCR_CHAN4_MASK       (DMA_CHAN_MASK <<  DMA_IFCR_CHAN4_SHIFT)
+#define DMA_IFCR_CHAN5_SHIFT      (16)      /* Bits 19-16:  DMA Channel 5 interrupt flag clear */
+#define DMA_IFCR_CHAN5_MASK       (DMA_CHAN_MASK <<  DMA_IFCR_CHAN5_SHIFT)
+#define DMA_IFCR_CHAN6_SHIFT      (20)      /* Bits 23-20:  DMA Channel 6 interrupt flag clear */
+#define DMA_IFCR_CHAN6_MASK       (DMA_CHAN_MASK <<  DMA_IFCR_CHAN6_SHIFT)
+#define DMA_IFCR_CHAN7_SHIFT      (24)      /* Bits 27-24:  DMA Channel 7 interrupt flag clear */
+#define DMA_IFCR_CHAN7_MASK       (DMA_CHAN_MASK <<  DMA_IFCR_CHAN7_SHIFT)
+#define DMA_IFCR_ALLCHANNELS      (0x0fffffff)
+
+#define DMA_IFCR_CGIF(n)          (DMA_CHAN_GIF_BIT << DMA_IFCR_CHAN_SHIFT(n))
+#define DMA_IFCR_CTCIF(n)         (DMA_CHAN_TCIF_BIT << DMA_IFCR_CHAN_SHIFT(n))
+#define DMA_IFCR_CHTIF(n)         (DMA_CHAN_HTIF_BIT << DMA_IFCR_CHAN_SHIFT(n))
+#define DMA_IFCR_CTEIF(n)         (DMA_CHAN_TEIF_BIT << DMA_IFCR_CHAN_SHIFT(n))
+
+/* DMA channel configuration register */
+
+#define DMA_CCR_EN                (1 << 0)  /* Bit 0: Channel enable */
+#define DMA_CCR_TCIE              (1 << 1)  /* Bit 1: Transfer complete interrupt enable */
+#define DMA_CCR_HTIE              (1 << 2)  /* Bit 2: Half Transfer interrupt enable */
+#define DMA_CCR_TEIE              (1 << 3)  /* Bit 3: Transfer error interrupt enable */
+#define DMA_CCR_DIR               (1 << 4)  /* Bit 4: Data transfer direction */
+#define DMA_CCR_CIRC              (1 << 5)  /* Bit 5: Circular mode */
+#define DMA_CCR_PINC              (1 << 6)  /* Bit 6: Peripheral increment mode */
+#define DMA_CCR_MINC              (1 << 7)  /* Bit 7: Memory increment mode */
+#define DMA_CCR_PSIZE_SHIFT       (8)       /* Bits 8-9: Peripheral size */
+#define DMA_CCR_PSIZE_MASK        (3 << DMA_CCR_PSIZE_SHIFT)
+#  define DMA_CCR_PSIZE_8BITS     (0 << DMA_CCR_PSIZE_SHIFT) /* 00: 8-bits */
+#  define DMA_CCR_PSIZE_16BITS    (1 << DMA_CCR_PSIZE_SHIFT) /* 01: 16-bits */
+#  define DMA_CCR_PSIZE_32BITS    (2 << DMA_CCR_PSIZE_SHIFT) /* 10: 32-bits */
+#define DMA_CCR_MSIZE_SHIFT       (10)      /* Bits 10-11: Memory size */
+#define DMA_CCR_MSIZE_MASK        (3 << DMA_CCR_MSIZE_SHIFT)
+#  define DMA_CCR_MSIZE_8BITS     (0 << DMA_CCR_MSIZE_SHIFT) /* 00: 8-bits */
+#  define DMA_CCR_MSIZE_16BITS    (1 << DMA_CCR_MSIZE_SHIFT) /* 01: 16-bits */
+#  define DMA_CCR_MSIZE_32BITS    (2 << DMA_CCR_MSIZE_SHIFT) /* 10: 32-bits */
+#define DMA_CCR_PL_SHIFT          (12)      /* Bits 12-13: Channel Priority level */
+#define DMA_CCR_PL_MASK           (3 << DMA_CCR_PL_SHIFT)
+#  define DMA_CCR_PRILO           (0 << DMA_CCR_PL_SHIFT) /* 00: Low */
+#  define DMA_CCR_PRIMED          (1 << DMA_CCR_PL_SHIFT) /* 01: Medium */
+#  define DMA_CCR_PRIHI           (2 << DMA_CCR_PL_SHIFT) /* 10: High */
+#  define DMA_CCR_PRIVERYHI       (3 << DMA_CCR_PL_SHIFT) /* 11: Very high */
+#define DMA_CCR_MEM2MEM           (1 << 14) /* Bit 14: Memory to memory mode */
+
+#define DMA_CCR_ALLINTS           (DMA_CCR_TEIE|DMA_CCR_HTIE|DMA_CCR_TCIE)
+
+/* DMA channel number of data register */
+
+#define DMA_CNDTR_NDT_SHIFT       (0)       /* Bits 15-0: Number of data to Transfer */
+#define DMA_CNDTR_NDT_MASK        (0xffff << DMA_CNDTR_NDT_SHIFT)
+
+/* DMA Channel mapping.  Each DMA channel has a mapping to one of several
+ * possible sources/sinks of data.  The requests from peripherals assigned to a
+ * channel are multiplexed together before entering the DMA block. This means
+ * that only one request on a given channel can be enabled at once.
+ *
+ * Alternative DMA channel selections are provided with a numeric suffix like _1,
+ * _2, etc.  Drivers, however, will use the pin selection without the numeric suffix.
+ * Additional definitions are required in the board.h file.
+ */
+
+#define STM32L4_DMA1_CHAN1          (0)
+#define STM32L4_DMA1_CHAN2          (1)
+#define STM32L4_DMA1_CHAN3          (2)
+#define STM32L4_DMA1_CHAN4          (3)
+#define STM32L4_DMA1_CHAN5          (4)
+#define STM32L4_DMA1_CHAN6          (5)
+#define STM32L4_DMA1_CHAN7          (6)
+
+#define STM32L4_DMA2_CHAN1          (7)
+#define STM32L4_DMA2_CHAN2          (8)
+#define STM32L4_DMA2_CHAN3          (9)
+#define STM32L4_DMA2_CHAN4          (10)
+#define STM32L4_DMA2_CHAN5          (11)
+#define STM32L4_DMA2_CHAN6          (12)
+#define STM32L4_DMA2_CHAN7          (13)
+
+/* DMA Channel settings include a channel and an alternative function.
+ * Channel is in bits 0..7
+ * Request number is in bits 8..15
+ */
+
+#define DMACHAN_SETTING(chan, req)     ((((req) & 0xff) << 8) | ((chan) & 0xff))
+#define DMACHAN_SETTING_CHANNEL_MASK   0x00FF
+#define DMACHAN_SETTING_CHANNEL_SHIFT  (0)
+#define DMACHAN_SETTING_FUNCTION_MASK  0xFF00
+#define DMACHAN_SETTING_FUNCTION_SHIFT (8)
+
+/* ADC */
+
+#define DMACHAN_ADC1_1          DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 0)
+#define DMACHAN_ADC1_2          DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 0)
+
+#define DMACHAN_ADC2_1          DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 0)
+#define DMACHAN_ADC2_2          DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 0)
+
+#define DMACHAN_ADC3_1          DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 0)
+#define DMACHAN_ADC3_2          DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 0)
+
+/* DAC */
+
+#define DMACHAN_DAC1_1          DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 6)
+#define DMACHAN_DAC1_3          DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 3)
+
+#define DMACHAN_DAC2_1          DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 5)
+#define DMACHAN_DAC2_2          DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 3)
+
+/* DFSDM */
+
+#define DMACHAN_DFSDM0          DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 0)
+#define DMACHAN_DFSDM1          DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 0)
+#define DMACHAN_DFSDM2          DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 0)
+#define DMACHAN_DFSDM3          DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 0)
+
+/* I2C */
+
+#define DMACHAN_I2C1_RX_1       DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 3)
+#define DMACHAN_I2C1_RX_2       DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 5)
+#define DMACHAN_I2C1_TX_1       DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 3)
+#define DMACHAN_I2C1_TX_2       DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 5)
+
+#define DMACHAN_I2C2_RX         DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 3)
+#define DMACHAN_I2C2_TX         DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 3)
+
+#define DMACHAN_I2C3_RX         DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 3)
+#define DMACHAN_I2C3_TX         DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 3)
+
+/* QUADSPI */
+
+#define DMACHAN_QUADSPI_1       DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 5)
+#define DMACHAN_QUADSPI_2       DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 3)
+
+/* SAI */
+
+#define DMACHAN_SAI1_A_1        DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 1)
+#define DMACHAN_SAI1_A_2        DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 1)
+#define DMACHAN_SAI1_B_1        DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 1)
+#define DMACHAN_SAI1_B_2        DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 1)
+
+#define DMACHAN_SAI2_A_1        DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 1)
+#define DMACHAN_SAI2_A_2        DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 1)
+#define DMACHAN_SAI2_B_1        DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 1)
+#define DMACHAN_SAI2_B_2        DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 1)
+
+/* SDMMC */
+
+#define DMACHAN_SDMMC_1         DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 7)
+#define DMACHAN_SDMMC_2         DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 7)
+
+/* SPI */
+
+#define DMACHAN_SPI1_RX_1       DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 1)
+#define DMACHAN_SPI1_RX_2       DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 4)
+#define DMACHAN_SPI1_TX_1       DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 1)
+#define DMACHAN_SPI1_TX_2       DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 4)
+
+#define DMACHAN_SPI2_RX         DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 1)
+#define DMACHAN_SPI2_TX         DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 1)
+
+#define DMACHAN_SPI3_RX         DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 3)
+#define DMACHAN_SPI3_TX         DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 3)
+
+/* SWPMI */
+
+#define DMACHAN_SWPMI_RX        DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 4)
+#define DMACHAN_SWPMI_TX        DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 4)
+
+/* TIM */
+
+#define DMACHAN_TIM1_CH1        DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 7)
+#define DMACHAN_TIM1_CH2        DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 7)
+#define DMACHAN_TIM1_CH3        DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 7)
+#define DMACHAN_TIM1_CH4        DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 7)
+#define DMACHAN_TIM1_COM        DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 7)
+#define DMACHAN_TIM1_TRIG       DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 7)
+#define DMACHAN_TIM1_UP         DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 7)
+
+#define DMACHAN_TIM2_CH1        DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 4)
+#define DMACHAN_TIM2_CH2        DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 4)
+#define DMACHAN_TIM2_CH3        DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 4)
+#define DMACHAN_TIM2_CH4        DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 4)
+#define DMACHAN_TIM2_UP         DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 4)
+
+#define DMACHAN_TIM3_CH1        DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 5)
+#define DMACHAN_TIM3_CH3        DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 5)
+#define DMACHAN_TIM3_CH4        DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 5)
+#define DMACHAN_TIM3_TRIG       DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 5)
+#define DMACHAN_TIM3_UP         DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 5)
+
+#define DMACHAN_TIM4_CH1        DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 6)
+#define DMACHAN_TIM4_CH2        DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 6)
+#define DMACHAN_TIM4_CH3        DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 6)
+#define DMACHAN_TIM4_UP         DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 6)
+
+#define DMACHAN_TIM5_CH1        DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 5)
+#define DMACHAN_TIM5_CH2        DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 5)
+#define DMACHAN_TIM5_CH3        DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 5)
+#define DMACHAN_TIM5_CH4        DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 5)
+#define DMACHAN_TIM5_COM        DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 5)
+#define DMACHAN_TIM5_TRIG       DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 5)
+#define DMACHAN_TIM5_UP         DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 5)
+
+#define DMACHAN_TIM6_UP_1       DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 6)
+#define DMACHAN_TIM6_UP_2       DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 3)
+
+#define DMACHAN_TIM7_UP_1       DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 5)
+#define DMACHAN_TIM7_UP_2       DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 3)
+
+#define DMACHAN_TIM8_CH1        DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 7)
+#define DMACHAN_TIM8_CH2        DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 7)
+#define DMACHAN_TIM8_CH3        DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 7)
+#define DMACHAN_TIM8_CH4        DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 7)
+#define DMACHAN_TIM8_COM        DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 7)
+#define DMACHAN_TIM8_TRIG       DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 7)
+#define DMACHAN_TIM8_UP         DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 7)
+
+#define DMACHAN_TIM15_CH1       DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 7)
+#define DMACHAN_TIM15_COM       DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 7)
+#define DMACHAN_TIM15_TRIG      DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 7)
+#define DMACHAN_TIM15_UP        DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 7)
+
+#define DMACHAN_TIM16_CH1_1     DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 4)
+#define DMACHAN_TIM16_CH1_2     DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 4)
+#define DMACHAN_TIM16_UP_1      DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 4)
+#define DMACHAN_TIM16_UP_2      DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 4)
+
+#define DMACHAN_TIM17_CH1_1     DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 5)
+#define DMACHAN_TIM17_CH1_2     DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 5)
+#define DMACHAN_TIM17_UP_1      DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 5)
+#define DMACHAN_TIM17_UP_2      DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 5)
+
+/* UART */
+
+#define DMACHAN_USART1_RX_1     DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 2)
+#define DMACHAN_USART1_RX_2     DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 2)
+#define DMACHAN_USART1_TX_1     DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 2)
+#define DMACHAN_USART1_TX_2     DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 2)
+
+#define DMACHAN_USART2_RX       DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 2)
+#define DMACHAN_USART2_TX       DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 2)
+
+#define DMACHAN_USART3_RX       DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 2)
+#define DMACHAN_USART3_TX       DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 2)
+
+#define DMACHAN_UART5_RX        DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 2)
+#define DMACHAN_UART5_TX        DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 2)
+
+#define DMACHAN_UART4_RX        DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 2)
+#define DMACHAN_UART4_TX        DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 2)
+
+#define DMACHAN_LPUART_RX       DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 4)
+#define DMACHAN_LPUART_TX       DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 4)
+
+#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X5XX_DMA_H */
@@ -0,0 +1,112 @@
+/************************************************************************************
+ * arch/arm/src/stm32l4/chip/stm32l4x5xx_firewall.h
+ *
+ *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2016 Sebastien Lorquet. All rights reserved.
+ *   Author: Sebastien Lorquet <sebastien@lorquet.fr>
+ *           Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X5XX_FIREWALL_H
+#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X5XX_FIREWALL_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+
+#include "chip.h"
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Register Offsets *****************************************************************/
+
+#define STM32L4_FIREWALL_CSSA_OFFSET    0x0000
+#define STM32L4_FIREWALL_CSL_OFFSET     0x0004
+#define STM32L4_FIREWALL_NVDSSA_OFFSET  0x0008
+#define STM32L4_FIREWALL_NVDSL_OFFSET   0x000C
+#define STM32L4_FIREWALL_VDSSA_OFFSET   0x0010
+#define STM32L4_FIREWALL_VDSL_OFFSET    0x0014
+#define STM32L4_FIREWALL_CR_OFFSET      0x0020
+
+/* Register Addresses ***************************************************************/
+
+#define STM32L4_FIREWALL_CSSA           (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CSSA_OFFSET)
+#define STM32L4_FIREWALL_CSL            (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CSL_OFFSET)
+#define STM32L4_FIREWALL_NVDSSA         (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_NVDSSA_OFFSET)
+#define STM32L4_FIREWALL_NVDSL          (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_NVDSL_OFFSET)
+#define STM32L4_FIREWALL_VDSSA          (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_VDSSA_OFFSET)
+#define STM32L4_FIREWALL_VDSL           (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_VDSL_OFFSET)
+#define STM32L4_FIREWALL_CR             (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CR_OFFSET)
+
+/* Register Bitfield Definitions ****************************************************/
+
+/* Code Segment Start Address */
+
+#define FIREWALL_CSSADD_SHIFT           8
+#define FIREWALL_CSSADD_MASK            (0xffff << FIREWALL_CSSADD_SHIFT)
+
+/* Code Segment Length */
+
+#define FIREWALL_CSSLENG_SHIFT          8
+#define FIREWALL_CSSLENG_MASK           (0x3fff << FIREWALL_CSSLENG_SHIFT)
+
+/* Non-volatile Data Segment Start Address */
+
+#define FIREWALL_NVDSADD_SHIFT          8
+#define FIREWALL_NVDSADD_MASK           (0xffff << FIREWALL_NVDSADD_SHIFT)
+
+/* Non-volatile Data Segment Length */
+
+#define FIREWALL_NVDSLENG_SHIFT         8
+#define FIREWALL_NVDSLENG_MASK          (0x3fff << FIREWALL_NVDSLENG_SHIFT)
+
+/* Volatile Data Segment Start Address */
+
+#define FIREWALL_VDSADD_SHIFT           6
+#define FIREWALL_VDSADD_MASK            (0x07ff << FIREWALL_VDSADD_SHIFT)
+
+/* Volatile Data Segment Length */
+
+#define FIREWALL_VDSLENG_SHIFT          6
+#define FIREWALL_VDSLENG_MASK           (0x07ff << FIREWALL_VDSLENG_SHIFT)
+
+/* Configuration Register */
+
+#define FIREWALL_CR_FPA                 (1 << 0) /* Bit 0: Firewall prearm */
+#define FIREWALL_CR_VDS                 (1 << 1) /* Bit 1: Volatile data shared */
+#define FIREWALL_CR_VDE                 (1 << 2) /* Bit 2: Volatile data execution */
+
+#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X5XX_FIREWALL_H */
@@ -0,0 +1,177 @@
+/****************************************************************************************************
+ * arch/arm/src/stm32l4/chip/stm32l4x5xx_syscfg.h
+ *
+ *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X5XX_SYSCFG_H
+#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X5XX_SYSCFG_H
+
+/****************************************************************************************************
+ * Included Files
+ ****************************************************************************************************/
+
+#include <nuttx/config.h>
+#include "chip.h"
+
+#if defined(CONFIG_STM32L4_STM32L4X5)
+
+/****************************************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************************************/
+
+/* Register Offsets *********************************************************************************/
+
+#define STM32L4_SYSCFG_MEMRMP_OFFSET    0x0000 /* SYSCFG memory remap register */
+#define STM32L4_SYSCFG_CFGR1_OFFSET     0x0004 /* SYSCFG configuration register 1 */
+#define STM32L4_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */
+#define STM32L4_SYSCFG_EXTICR1_OFFSET   0x0008 /* SYSCFG external interrupt configuration register 1 */
+#define STM32L4_SYSCFG_EXTICR2_OFFSET   0x000c /* SYSCFG external interrupt configuration register 2 */
+#define STM32L4_SYSCFG_EXTICR3_OFFSET   0x0010 /* SYSCFG external interrupt configuration register 3 */
+#define STM32L4_SYSCFG_EXTICR4_OFFSET   0x0014 /* SYSCFG external interrupt configuration register 4 */
+#define STM32L4_SYSCFG_SCSR_OFFSET      0x0018 /* SYSCFG SRAM2 control and status register */
+#define STM32L4_SYSCFG_CFGR2_OFFSET     0x001c /* SYSCFG configuration register 2 */
+#define STM32L4_SYSCFG_SWPR_OFFSET      0x0020 /* SYSCFG SRAM2 write protection register */
+#define STM32L4_SYSCFG_SKR_OFFSET       0x0024 /* SYSCFG SRAM2 key register */
+
+/* Register Addresses *******************************************************************************/
+
+#define STM32L4_SYSCFG_MEMRMP           (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_MEMRMP_OFFSET)
+#define STM32L4_SYSCFG_CFGR1            (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_CFGR1_OFFSET)
+#define STM32L4_SYSCFG_EXTICR(p)        (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR_OFFSET(p))
+#define STM32L4_SYSCFG_EXTICR1          (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR1_OFFSET)
+#define STM32L4_SYSCFG_EXTICR2          (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR2_OFFSET)
+#define STM32L4_SYSCFG_EXTICR3          (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR3_OFFSET)
+#define STM32L4_SYSCFG_EXTICR4          (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR4_OFFSET)
+#define STM32L4_SYSCFG_SCSR             (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SCSR_OFFSET)
+#define STM32L4_SYSCFG_CFGR2            (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_CFGR2_OFFSET)
+#define STM32L4_SYSCFG_SWPR             (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SWPR_OFFSET)
+#define STM32L4_SYSCFG_SKR              (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SKR_OFFSET)
+
+/* Register Bitfield Definitions ********************************************************************/
+
+/* SYSCFG memory remap register */
+
+#define SYSCFG_MEMRMP_SHIFT           (0)       /* Bits 2:0 MEM_MODE: Memory mapping selection */
+#define SYSCFG_MEMRMP_MASK            (7 << SYSCFG_MEMRMP_SHIFT)
+#  define SYSCFG_MEMRMP_FLASH         (0 << SYSCFG_MEMRMP_SHIFT) /* 000: Main Flash memory mapped at 0x0000 0000 */
+#  define SYSCFG_MEMRMP_SYSTEM        (1 << SYSCFG_MEMRMP_SHIFT) /* 001: System Flash memory mapped at 0x0000 0000 */
+#  define SYSCFG_MEMRMP_FMC           (2 << SYSCFG_MEMRMP_SHIFT) /* 010: FSMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x0000 0000 */
+#  define SYSCFG_MEMRMP_SRAM          (3 << SYSCFG_MEMRMP_SHIFT) /* 011: SRAM1 (112kB) mapped at 0x0000 0000 */
+#  define SYSCFG_MEMRMP_QSPI          (6 << SYSCFG_MEMRMP_SHIFT) /* 110: QUADSPI mapped at 0x0000 0000 */
+#define SYSCFG_FBMODE                 (1 << 8) /* Bit 8: Flash Bank mode selection */
+
+/* SYSCFG configuration register 1 */
+
+#define SYSCFG_CFGR1_FWDIS            (1 <<  0) /* Bit  0: Firewall disable */
+#define SYSCFG_CFGR1_BOOSTEN          (1 <<  8) /* Bit  8: I/O analog switch voltage booster enable (use when vdd is low) */
+#define SYSCFG_CFGR1_I2C_PB6_FMP      (1 << 16) /* Bit 16: Fast-mode Plus (Fm+) driving capability activation on PB6 */
+#define SYSCFG_CFGR1_I2C_PB7_FMP      (1 << 17) /* Bit 17: Fast-mode Plus (Fm+) driving capability activation on PB7 */
+#define SYSCFG_CFGR1_I2C_PB8_FMP      (1 << 18) /* Bit 18: Fast-mode Plus (Fm+) driving capability activation on PB8 */
+#define SYSCFG_CFGR1_I2C_PB9_FMP      (1 << 19) /* Bit 19: Fast-mode Plus (Fm+) driving capability activation on PB9 */
+#define SYSCFG_CFGR1_I2C1_FMP         (1 << 20) /* Bit 20: I2C1 Fast-mode Plus (Fm+) driving capability activation */
+#define SYSCFG_CFGR1_I2C2_FMP         (1 << 21) /* Bit 21: I2C2 Fast-mode Plus (Fm+) driving capability activation */
+#define SYSCFG_CFGR1_I2C3_FMP         (1 << 22) /* Bit 22: I2C3 Fast-mode Plus (Fm+) driving capability activation */
+#define SYSCFG_CFGR1_FPU_IE0          (1 << 26) /* Bit 26: FPU Invalid operation interrupt enable */
+#define SYSCFG_CFGR1_FPU_IE1          (1 << 27) /* Bit 27: FPU Divide-by-zero interrupt enable */
+#define SYSCFG_CFGR1_FPU_IE2          (1 << 28) /* Bit 28: FPU Underflow interrupt enable */
+#define SYSCFG_CFGR1_FPU_IE3          (1 << 29) /* Bit 29: FPU Overflow interrupt enable */
+#define SYSCFG_CFGR1_FPU_IE4          (1 << 30) /* Bit 30: FPU Input denormal interrupt enable */
+#define SYSCFG_CFGR1_FPU_IE5          (1 << 31) /* Bit 31: FPU Inexact interrupt enable */
+
+/* SYSCFG external interrupt configuration register 1-4 */
+
+#define SYSCFG_EXTICR_PORTA           (0)       /* 0000: PA[x] pin */
+#define SYSCFG_EXTICR_PORTB           (1)       /* 0001: PB[x] pin */
+#define SYSCFG_EXTICR_PORTC           (2)       /* 0010: PC[x] pin */
+#define SYSCFG_EXTICR_PORTD           (3)       /* 0011: PD[x] pin */
+#define SYSCFG_EXTICR_PORTE           (4)       /* 0100: PE[x] pin */
+#define SYSCFG_EXTICR_PORTF           (5)       /* 0101: PF[C] pin */
+#define SYSCFG_EXTICR_PORTG           (6)       /* 0110: PG[x] pin */
+#define SYSCFG_EXTICR_PORTH           (7)       /* 0111: PH[x] pin (only on STM32L496xx/4A6xx) */
+#define SYSCFG_EXTICR_PORTI           (8)       /* 1000: PI[x] pin (only on STM32L496xx/4A6xx) */
+
+#define SYSCFG_EXTICR_PORT_MASK       (15)
+#define SYSCFG_EXTICR_EXTI_SHIFT(g)   (((g) & 3) << 2)
+#define SYSCFG_EXTICR_EXTI_MASK(g)    (SYSCFG_EXTICR_PORT_MASK << (SYSCFG_EXTICR_EXTI_SHIFT(g)))
+
+#define SYSCFG_EXTICR1_EXTI0_SHIFT    (0)       /* Bits 0-2: EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI0_MASK     (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI0_SHIFT)
+#define SYSCFG_EXTICR1_EXTI1_SHIFT    (4)       /* Bits 4-6: EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI1_MASK     (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI1_SHIFT)
+#define SYSCFG_EXTICR1_EXTI2_SHIFT    (8)       /* Bits 8-10: EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI2_MASK     (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI2_SHIFT)
+#define SYSCFG_EXTICR1_EXTI3_SHIFT    (12)      /* Bits 12-14: EXTI 3 configuration */
+#define SYSCFG_EXTICR1_EXTI3_MASK     (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI3_SHIFT)
+
+#define SYSCFG_EXTICR2_EXTI4_SHIFT    (0)       /* Bits 0-2: EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI4_MASK     (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI4_SHIFT)
+#define SYSCFG_EXTICR2_EXTI5_SHIFT    (4)       /* Bits 4-6: EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI5_MASK     (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI5_SHIFT)
+#define SYSCFG_EXTICR2_EXTI6_SHIFT    (8)       /* Bits 8-10: EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI6_MASK     (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI6_SHIFT)
+#define SYSCFG_EXTICR2_EXTI7_SHIFT    (12)      /* Bits 12-14: EXTI 7 configuration */
+#define SYSCFG_EXTICR2_EXTI7_MASK     (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI7_SHIFT)
+
+#define SYSCFG_EXTICR3_EXTI8_SHIFT    (0)       /* Bits 0-2: EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI8_MASK     (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI8_SHIFT)
+#define SYSCFG_EXTICR3_EXTI9_SHIFT    (4)       /* Bits 4-6: EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI9_MASK     (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI9_SHIFT)
+#define SYSCFG_EXTICR3_EXTI10_SHIFT   (8)       /* Bits 8-10: EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI10_MASK    (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI10_SHIFT)
+#define SYSCFG_EXTICR3_EXTI11_SHIFT   (12)      /* Bits 12-14: EXTI 11 configuration */
+#define SYSCFG_EXTICR3_EXTI11_MASK    (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI11_SHIFT)
+
+#define SYSCFG_EXTICR4_EXTI12_SHIFT   (0)       /* Bits 0-2: EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI12_MASK    (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI12_SHIFT)
+#define SYSCFG_EXTICR4_EXTI13_SHIFT   (4)       /* Bits 4-6: EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI13_MASK    (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI13_SHIFT)
+#define SYSCFG_EXTICR4_EXTI14_SHIFT   (8)       /* Bits 8-10: EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI14_MASK    (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI14_SHIFT)
+#define SYSCFG_EXTICR4_EXTI15_SHIFT   (12)      /* Bits 12-14: EXTI 15 configuration */
+#define SYSCFG_EXTICR4_EXTI15_MASK    (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI15_SHIFT)
+
+/* SYSCFG SRAM2 control and status register */
+
+#define SYSCFG_SCSR_SRAM2ER           (1 <<  0) /* Bit  0: SRAM2 Erase */
+#define SYSCFG_SCSR_SRAM2BSY          (1 <<  1) /* Bit  1: SRAM2 busy in erase operation */
+
+/* SYSCFG configuration register 2 */
+
+#define SYSCFG_CFGR2_CLL              (1 <<  0) /* Bit  0: Cortex-M4 LOCKUP (Hardfault) output enable (TIMx break enable, see refman) */
+#define SYSCFG_CFGR2_SPL              (1 <<  1) /* Bit  1: SRAM2 parity lock enable (same) */
+#define SYSCFG_CFGR2_PVDL             (1 <<  2) /* Bit  2: PVD lock enable (same) */
+#define SYSCFG_CFGR2_ECCL             (1 <<  3) /* Bit  3: ECC lock enable (same) */
+#define SYSCFG_CFGR2_SPF              (1 <<  8) /* Bit  8: SRAM2 parity error flag */
+
+#endif /* CONFIG_STM32L4_STM32L4X5 */
+#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X5XX_SYSCFG_H */
@@ -72,22 +72,27 @@
 /* Register Bitfield Definitions ****************************************************/

 /* Code Segment Start Address */
+
 #define FIREWALL_CSSADD_SHIFT           8
 #define FIREWALL_CSSADD_MASK            (0xFFFF << FIREWALL_CSSADD_SHIFT)

 /* Code Segment Length */
+
 #define FIREWALL_CSSLENG_SHIFT          8
 #define FIREWALL_CSSLENG_MASK           (0x3FFF << FIREWALL_CSSLENG_SHIFT)

 /* Non-volatile Data Segment Start Address */
+
 #define FIREWALL_NVDSADD_SHIFT          8
 #define FIREWALL_NVDSADD_MASK           (0xFFFF << FIREWALL_NVDSADD_SHIFT)

 /* Non-volatile Data Segment Length */
+
 #define FIREWALL_NVDSLENG_SHIFT         8
 #define FIREWALL_NVDSLENG_MASK          (0x3FFF << FIREWALL_NVDSLENG_SHIFT)

 /* Volatile Data Segment Start Address */
+
 #define FIREWALL_VDSADD_SHIFT           6
 #if defined(CONFIG_STM32L4_STM32L496XX)
 #define FIREWALL_VDSADD_MASK            (0x0FFF << FIREWALL_VDSADD_SHIFT)
@@ -96,6 +101,7 @@
 #endif

 /* Volatile Data Segment Length */
+
 #define FIREWALL_VDSLENG_SHIFT          6
 #if defined(CONFIG_STM32L4_STM32L496XX)
 #define FIREWALL_VDSLENG_MASK           (0x0FFF << FIREWALL_VDSLENG_SHIFT)
@@ -104,6 +110,7 @@
 #endif

 /* Configuration Register */
+
 #define FIREWALL_CR_FPA                 (1 << 0) /* Bit 0: Firewall prearm */
 #define FIREWALL_CR_VDS                 (1 << 1) /* Bit 1: Volatile data shared */
 #define FIREWALL_CR_VDE                 (1 << 2) /* Bit 2: Volatile data execution */
@@ -439,7 +439,9 @@
 #  define OTGFS_HNPTXSTS_EPNUM_SHIFT    (27)      /* Bits 27-30: Endpoint number */
 #  define OTGFS_HNPTXSTS_EPNUM_MASK     (15 << OTGFS_HNPTXSTS_EPNUM_SHIFT)
                                                  /* Bit 31 Reserved, must be kept at reset value */
+
 /* General core configuration register */
+
 #define OTGFS_GCCFG_DCDET               (1 << 0) /* Bit 0: Data contact detect */
 #define OTGFS_GCCFG_PDET                (1 << 1) /* Bit 1: Primary detect */
 #define OTGFS_GCCFG_SDET                (1 << 2) /* Bit 2: Secondary detect */
@@ -453,35 +455,48 @@
 #define OTGFS_GCCFG_VBDEN               (1 << 21) /* Bit 21: USB VBUS detection enable */
                                                  /* Bits 22-31: Reserved, must be kept at reset value */

-/* Core ID register  (32-bit product ID) */
+/* Core ID register (32-bit product ID) */

-//XXX GLPMCFG
-#define OTGFS_GLPMCFG_LPMEN             (1 << 0) /* Bit 0: XXX */
-#define OTGFS_GLPMCFG_LPMACK            (1 << 1) /* Bit 1: XXX */
-//#define OTGFS_GLPMCFG_BESL
-#define OTGFS_GLPMCFG_REMWAKE           (1 << 6) /* Bit 6: XXX */
-#define OTGFS_GLPMCFG_L1SSEN            (1 << 7) /* Bit 7: XXX */
-//#define OTGFS_GLPMCFG_BESLTHRS
+/* LPM configuration register */
+
+#define OTGFS_GLPMCFG_LPMEN             (1 << 0)  /* Bit 0: XXX */
+#define OTGFS_GLPMCFG_LPMACK            (1 << 1)  /* Bit 1: XXX */
+#define OTGFS_GLPMCFG_BESL_SHIFT        (2)       /* Bits 2-5: XXX */
+#define OTGFS_GLPMCFG_BESL_MASK         (15 << OTGFS_GLPMCFG_BESL_SHIFT)
+#define OTGFS_GLPMCFG_REMWAKE           (1 << 6)  /* Bit 6: XXX */
+#define OTGFS_GLPMCFG_L1SSEN            (1 << 7)  /* Bit 7: XXX */
+#define OTGFS_GLPMCFG_BESLTHRS_SHIFT    (8)       /* Bits 8-11: XXX */
+#define OTGFS_GLPMCFG_BESLTHRS_MASK     (15 << OTGFS_GLPMCFG_BESLTHRS_SHIFT)
 #define OTGFS_GLPMCFG_L1DSEN            (1 << 12) /* Bit 12: XXX */
-//#define OTGFS_GLPMCFG_LPMRSP
+#define OTGFS_GLPMCFG_LPMRSP_SHIFT      (13)      /* Bits 13-14: XXXX */
+#define OTGFS_GLPMCFG_LPMRSP_MASK       (3 << OTGFS_GLPMCFG_LPMRSP_SHIFT)
 #define OTGFS_GLPMCFG_SLPSTS            (1 << 15) /* Bit 15: XXX */
 #define OTGFS_GLPMCFG_L1RSMOK           (1 << 16) /* Bit 16: XXX */
-//#define OTGFS_GLPMCFG_LPMCHIDX
-//#define OTGFS_GLPMCFG_LPMRCNT
+#define OTGFS_GLPMCFG_LPMCHIDX_SHIFT    (17)      /* Bits 17-20: XXX */
+#define OTGFS_GLPMCFG_LPMCHIDX_MASK     (15 << OTGFS_GLPMCFG_LPMCHIDX_SHIFT)
+#define OTGFS_GLPMCFG_LPMRCNT_SHIFT     (21)      /* Bits 21-23: XXX */
+#define OTGFS_GLPMCFG_LPMRCNT_MASK      (7 << OTGFS_GLPMCFG_LPMRCNT_SHIFT)
 #define OTGFS_GLPMCFG_SNDLPM            (1 << 24) /* Bit 24: XXX */
-//#define OTGFS_GLPMCFG_LPMRCNTSTS
+#define OTGFS_GLPMCFG_LPMRCNTSTS_SHIFT  (25)      /* Bits 25-27: XXX */
+#define OTGFS_GLPMCFG_LPMRCNTSTS_MASK   (7 << OTGFS_GLPMCFG_LPMRCNTSTS_SHIFT)
 #define OTGFS_GLPMCFG_ENBESL            (1 << 28) /* Bit 28: XXX */
                                                  /* Bits 29-31: Reserved, must be kept at reset value */

-//XXX GPWRDN
-#define OTGFS_GPWRDN_ADPMEN             (1 << 0) /* Bit 0: XXX */
+/* Power down register */
+
+#define OTGFS_GPWRDN_ADPMEN             (1 << 0)  /* Bit 0: XXX */
 #define OTGFS_GPWRDN_ADPIF              (1 << 23) /* Bit 23: XXX */

-//XXX GADPCTL
-//#define OTGFS_GADPCTL_PRBDSCHG
-//#define OTGFS_GADPCTL_PRBDELTA
-//#define OTGFS_GADPCTL_PRBPER
-//#define OTGFS_GADPCTL_RTIM
+/* ADP timer, control and status register */
+
+#define OTGFS_GADPCTL_PRBDSCHG_SHIFT    (0)       /* Bits 0-1: XXX */
+#define OTGFS_GADPCTL_PRBDSCHG_MASK     (3 << OTGFS_GADPCTL_PRBDSCHG_SHIFT)
+#define OTGFS_GADPCTL_PRBDELTA_SHIFT    (2)       /* Bits 2-3: XXX */
+#define OTGFS_GADPCTL_PRBDELTA_MASK     (3 << OTGFS_GADPCTL_PRBDELTA_SHIFT)
+#define OTGFS_GADPCTL_PRBPER_SHIFT      (4)       /* Bits 4-5: XXX */
+#define OTGFS_GADPCTL_PRBPER_MASK       (15 << OTGFS_GADPCTL_PRBPER_SHIFT)
+#define OTGFS_GADPCTL_RTIM_SHIFT        (6)       /* Bits 6-9: XXX */
+#define OTGFS_GADPCTL_RTIM_SHIFT        (6)       /* Bits 6-9: XXX */
 #define OTGFS_GADPCTL_ENAPRB            (1 << 17) /* Bit 17: XXX */
 #define OTGFS_GADPCTL_ENASNS            (1 << 18) /* Bit 18: XXX */
 #define OTGFS_GADPCTL_ADPRST            (1 << 19) /* Bit 19: XXX */
@@ -492,7 +507,8 @@
 #define OTGFS_GADPCTL_ADPPRBIM          (1 << 24) /* Bit 24: XXX */
 #define OTGFS_GADPCTL_ADPSNSIM          (1 << 25) /* Bit 25: XXX */
 #define OTGFS_GADPCTL_ADPTOIM           (1 << 26) /* Bit 26: XXX */
-//#define OTGFS_GADPCTL_AR
+#define OTGFS_GADPCTL_AR_SHIFT          (27)      /* Bits 27-28: XXX */
+#define OTGFS_GADPCTL_AR_MASK           (3 << OTGFS_GADPCTL_AR_SHIFT)

 /* Host periodic transmit FIFO size register */

@@ -622,7 +638,6 @@
 #define OTGFS_HCINT_STALL               (1 << 3)  /* Bit 3:  STALL response received interrupt */
 #define OTGFS_HCINT_NAK                 (1 << 4)  /* Bit 4:  NAK response received interrupt */
 #define OTGFS_HCINT_ACK                 (1 << 5)  /* Bit 5:  ACK response received/transmitted interrupt */
-//#define OTGFS_HCINT_NYET                (1 << 6)  /* Bit 6:  Response received interrupt */
 #define OTGFS_HCINT_TXERR               (1 << 7)  /* Bit 7:  Transaction error */
 #define OTGFS_HCINT_BBERR               (1 << 8)  /* Bit 8:  Babble error */
 #define OTGFS_HCINT_FRMOR               (1 << 9)  /* Bit 9:  Frame overrun */
@@ -704,7 +719,6 @@
 #define OTGFS_DSTS_SOFFN_ODD            OTGFS_DSTS_SOFFN0
 #define OTGFS_DSTS_DEVLNSTS_SHIFT       (22)       /* Bits 22-23: XXX */
 #define OTGFS_DSTS_DEVLNSTS_MASK        (0x3 << OTGFS_DSTS_DEVLNSTS_SHIFT)
-//XXX
                                                  /* Bits 24-31: Reserved, must be kept at reset value */
 /* Device IN endpoint common interrupt mask register */

--- a/Show More
+++ b/Show More