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Merge remote-tracking branch 'origin/master' into ieee802154

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This commit is contained in:
Gregory Nutt
2017-04-18 10:38:08 -06:00
parent 1d1d633e6f 27e212a291
commit 52cddc45de
60 changed files with 4077 additions and 587 deletions
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Documentation/NuttXCCodingStandard.html
+52 -14
View File
@@ -12,7 +12,7 @@
<h1><big><font color="#3c34ec">
<i>NuttX C Coding Standard</i>
</font></big></h1>
<p>Last Updated: February 9, 2017</p>
<p>Last Updated: April 17, 2017</p>
</td>
</tr>
</table>
@@ -1291,14 +1291,23 @@ typedef int myinteger_t;
<li>
<b>No un-named structures</b>.
All structures must be named, even if they are part of a type definition.
That is, a structure name must follow the reserved word <code>struct</code> in all structure definitions.
The exception to this rule is for structures that are defined within another union or structure. In those cases, the structure name should always be omitted.
</li>
<li>
<b>No un-named structure fields</b>.
Structure may contain other structures as fields.
This this case, the structure field must be named.
C11 permits such un-named structure fields within structure.
NuttX generally follows C89 and all code outside of architecture specific directories must be compatible with C89.
<li>
<b>No structure definitions within Type Definition</b>.
The practice of defining a structure within a type definition is discouraged.
It is preferred that the structure definition and the type definition be separate definitions.
In general, the NuttX coding style discourages any <code>typdef</code>-ing of structures;
normally the full structure name is used as types throughout the code.
The reason for this is that is structure pointers may be forward referenced in header files without having to include the file the provides the type definition.
This greatly reduces header file coupling.
</li>
<li>
<b>Short structure names</b>.
@@ -1373,7 +1382,7 @@ typedef int myinteger_t;
<tr><td bgcolor="white">
<p><font color="red"><b>Incorrect</b></p>
<ul><pre>
typedef struct
typedef struct /* Un-named structure */
{
...
int val1, val2, val3; /* Values 1-3 */
@@ -1388,6 +1397,18 @@ struct xyz_information
bitc : 1; /* Bit C */
...
};
struct abc_s
{
...
struct
{
int a; /* Value A */
int b; /* Value B */
int c; /* Value C */
}; /* Un-named structure field */
...
};
</ul></pre></font>
</td></tr>
<tr><td bgcolor="white">
@@ -1396,23 +1417,35 @@ struct xyz_information
struct xyz_info_s
{
...
int val1; /* Value 1. */
int val2; /* Value 2. */
int val3; /* Value 3. */
int val1; /* Value 1 */
int val2; /* Value 2 */
int val3; /* Value 3 */
...
};
</pre>
<font color="blue"><pre>
typdef struct xyz_info_s xzy_info_t;
typedef struct xyz_info_s xzy_info_t;
</pre>
<p>(The use of typedef'ed structures is acceptable but discouraged)</p></font>
<pre>
struct xyz_info_s
{
...
uint8_t bita : 1, /* Bit A. */
uint8_t bitb : 1, /* Bit B. */
uint8_t bitc : 1, /* Bit C. */
uint8_t bita : 1, /* Bit A */
uint8_t bitb : 1, /* Bit B */
uint8_t bitc : 1, /* Bit C */
...
};
struct abc_s
{
...
struct
{
int a; /* Value A */
int b; /* Value B */
int c; /* Value C */
} abc;
...
};
</ul></pre></font>
@@ -1433,13 +1466,18 @@ struct xyz_info_s
<tr><td bgcolor="white">
<p><font color="green"><b>Example</b></p>
<ul><pre>
union xyz_union_u
union xyz_union_u /* All unions must be named */
{
uint8_t b[4]; /* Byte values. */
uint16_t h[2]; /* Half word values. */
uint32_t w; /* Word Value. */
};
</pre>
<font color="blue"><pre>
typedef union xyz_union_u xzy_union_t;
</pre>
<p>(The use of typedef'ed unions is acceptable but discouraged)</p></font>
<pre>
struct xyz_info_s
{
...
@@ -1448,7 +1486,7 @@ struct xyz_info_s
uint8_t b[4]; /* Byte values. */
uint16_t h[2]; /* Half word values. */
uint32_t w; /* Word Value. */
} u;
} u; /* All union fields must be named */
...
};
</ul></pre></font>
@@ -1456,9 +1494,9 @@ struct xyz_info_s
</table></center>
<p>
<b>NOTE:</b>
Note that the union name <code>u</code> is used often.
Note that the union fields within structures are often named <code>u</code>.
This is another exception to the prohibition against using single character variable and field names.
The short field name <code>u</code> clearly identifies a union field and prevents the full name to the union value from being excessively long.
The short field name <code>u</code> clearly identifies a union field and prevents the full name of the union value from being excessively long.
</p>
<h2>2.7 <a name="enumerations">Enumerations</a></h2>
Documentation/README.html
+4 -1
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@@ -8,7 +8,7 @@
<tr align="center" bgcolor="#e4e4e4">
<td>
<h1><big><font color="#3c34ec"><i>NuttX README Files</i></font></big></h1>
<p>Last Updated: April 15, 2017</p>
<p>Last Updated: April 18, 2017</p>
</td>
</tr>
</table>
@@ -161,6 +161,9 @@ nuttx/
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/ntosd-dm320/README.txt" target="_blank"><b><i>README.txt</i></b></a>
| |- nucleo-144/
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/nucleo-144/README.txt" target="_blank"><b><i>README.txt</i></b></a>
| | `- README.txt
| |- nucleo-f072rb/
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/nucleo-f072rb/README.txt" target="_blank"><i>README.txt</i></a>
| |- nucleo-f303re/
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/nucleo-f303re/README.txt" target="_blank"><i>README.txt</i></a>
| |- nucleo-f334r8/
README.txt
+2
View File
@@ -1548,6 +1548,8 @@ nuttx/
| | `- README.txt
| |- nucleo-144/
| | `- README.txt
| |- nucleo-f072rb/
| | `- README.txt
| |- nucleo-f303re/
| | `- README.txt
| |- nucleo-f334r8/
arch/arm/include/stm32f0/chip.h
+106 -12
View File
@@ -51,22 +51,116 @@
#if defined(CONFIG_ARCH_CHIP_STM32F051R8)
# define STM32F051x 1 /* STM32F051x family */
# undef STM32F072x /* Not STM32F072x family */
# define STM32F0_FLASH_SIZE (64*1024) /* 64Kb */
# define STM32F0_SRAM_SIZE (8*1024) /* 8Kb */
# define STM32F0_CPUSRAM_SIZE (8*1024)
# undef STM32F0_HAVE_BANK0 /* No AHB SRAM bank 0 */
# undef STM32F0_HAVE_BANK1 /* No AHB SRAM bank 1 */
# define STM32F0_NETHCONTROLLERS 0 /* No Ethernet controller */
# define STM32F0_NUSBHOST 0 /* No USB host controller */
# define STM32F0_NUSBOTG 0 /* No USB OTG controller */
# define STM32F0_NSPI 2 /* Two SPI modules (SPI or I2S) */
# define STM32F0_NI2S 2 /* Two I2S modules (SPI or I2S) */
# define STM32F0_NI2C 2 /* Two I2C modules */
# define STM32F0_NUSART 2 /* Two USARTs modules */
# define STM32F0_NCAN 0 /* No CAN controllers */
# define STM32F0_NUSBDEV 1 /* One USB device controller */
# define STM32F0_NUSART 2 /* Two USARTs module */
# define STM32F0_NPORTS 6 /* 6 GPIO ports, GPIOA-F */
# define STM32F0_NCAN 1 /* One CAN controller */
# define STM32F0_NI2C 2 /* Two I2C module */
# define STM32F0_NI2S 1 /* One I2S module */
# define STM32F0_NDAC 1 /* One DAC module */
# define STM32F0_NSPI 2 /* Two DAC module */
# define STM32F0_NDACCHAN 1 /* One DAC channels */
# define STM32F0_NCOMP 2 /* Two Analog Comparators */
# define STM32F0_NCAP 13 /* Capacitive sensing channels (14 on UFQFPN32)) */
# define STM32F0_NPORTS 6 /* Six GPIO ports, GPIOA-F */
#elif defined(CONFIG_ARCH_CHIP_STM32F072C8) || defined(CONFIG_ARCH_CHIP_STM32F072CB)
# undef STM32F051x /* Not STM32F051x family */
# define STM32F072x 1 /* STM32F072x family */
# ifdef CONFIG_ARCH_CHIP_STM32F072C8
# define STM32F0_FLASH_SIZE (64*1024) /* 64Kb */
# else
# define STM32F0_FLASH_SIZE (128*1024) /* 128Kb */
# endif
# define STM32F0_SRAM_SIZE (16*1024) /* 16Kb */
# define STM32F0_NATIM 1 /* One advanced timer TIM1 */
# define STM32F0_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14-17 */
# define STM32F0_NGTIM32 1 /* 32-bit general up/down timers TIM2 */
# define STM32F0_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */
# define STM32F0_NSPI 2 /* Two SPI modules (SPI or I2S) */
# define STM32F0_NI2S 2 /* Two I2S modules (SPI or I2S) */
# define STM32F0_NI2C 2 /* Two I2C modules */
# define STM32F0_NUSART 4 /* Four USARTs module */
# define STM32F0_NCAN 1 /* One CAN controller */
# define STM32F0_NUSBDEV 1 /* One USB device controller */
# define STM32F0_NCEC 1 /* One HDMI-CEC controller */
# define STM32F0_NADC16 1 /* One 16-bit module */
# define STM32F0_NADCCHAN 10 /* Ten external channels */
# define STM32F0_NADCEXT 3 /* Three external channels */
# define STM32F0_NDAC 1 /* One DAC module */
# define STM32F0_NDACCHAN 2 /* Two DAC channels */
# define STM32F0_NCOMP 2 /* Two Analog Comparators */
# define STM32F0_NCAP 17 /* Capacitive sensing channels */
# define STM32F0_NPORTS 6 /* Six GPIO ports, GPIOA-F */
#elif defined(CONFIG_ARCH_CHIP_STM32F072R8) || defined(CONFIG_ARCH_CHIP_STM32F072RB)
# undef STM32F051x /* Not STM32F051x family */
# define STM32F072x 1 /* STM32F072x family */
# ifdef CONFIG_ARCH_CHIP_STM32F072R8
# define STM32F0_FLASH_SIZE (64*1024) /* 64Kb */
# else
# define STM32F0_FLASH_SIZE (128*1024) /* 128Kb */
# endif
# define STM32F0_SRAM_SIZE (16*1024) /* 16Kb */
# define STM32F0_NATIM 1 /* One advanced timer TIM1 */
# define STM32F0_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14-17 */
# define STM32F0_NGTIM32 1 /* 32-bit general up/down timers TIM2 */
# define STM32F0_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */
# define STM32F0_NSPI 2 /* Two SPI modules (SPI or I2S) */
# define STM32F0_NI2S 2 /* Two I2S modules (SPI or I2S) */
# define STM32F0_NI2C 2 /* Two I2C modules */
# define STM32F0_NUSART 4 /* Four USARTs module */
# define STM32F0_NCAN 1 /* One CAN controller */
# define STM32F0_NUSBDEV 1 /* One USB device controller */
# define STM32F0_NCEC 1 /* One HDMI-CEC controller */
# define STM32F0_NADC16 1 /* One 16-bit module */
# define STM32F0_NADCCHAN 16 /* 16 external channels */
# define STM32F0_NADCEXT 3 /* Three external channels */
# define STM32F0_NDAC 1 /* One DAC module */
# define STM32F0_NDACCHAN 2 /* Two DAC channels */
# define STM32F0_NCOMP 2 /* Two Analog Comparators */
# define STM32F0_NCAP 18 /* Capacitive sensing channels */
# define STM32F0_NPORTS 6 /* Six GPIO ports, GPIOA-F */
#elif defined(CONFIG_ARCH_CHIP_STM32F072V8) || defined(CONFIG_ARCH_CHIP_STM32F072VB)
# undef STM32F051x /* Not STM32F051x family */
# define STM32F072x 1 /* STM32F072x family */
# ifdef CONFIG_ARCH_CHIP_STM32F072V8
# define STM32F0_FLASH_SIZE (64*1024) /* 64Kb */
# else
# define STM32F0_FLASH_SIZE (128*1024) /* 128Kb */
# endif
# define STM32F0_SRAM_SIZE (16*1024) /* 16Kb */
# define STM32F0_NATIM 1 /* One advanced timer TIM1 */
# define STM32F0_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14-17 */
# define STM32F0_NGTIM32 1 /* 32-bit general up/down timers TIM2 */
# define STM32F0_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */
# define STM32F0_NSPI 2 /* Two SPI modules (SPI or I2S) */
# define STM32F0_NI2S 2 /* Two I2S modules (SPI or I2S) */
# define STM32F0_NI2C 2 /* Two I2C modules */
# define STM32F0_NUSART 4 /* Four USARTs module */
# define STM32F0_NCAN 1 /* One CAN controller */
# define STM32F0_NUSBDEV 1 /* One USB device controller */
# define STM32F0_NCEC 1 /* One HDMI-CEC controller */
# define STM32F0_NADC16 1 /* One 16-bit module */
# define STM32F0_NADCCHAN 16 /* 16 external channels */
# define STM32F0_NADCEXT 3 /* Three external channels */
# define STM32F0_NDAC 1 /* One DAC module */
# define STM32F0_NDACCHAN 2 /* Two DAC channels */
# define STM32F0_NCOMP 2 /* Two Analog Comparators */
# define STM32F0_NCAP 24 /* Capacitive sensing channels */
# define STM32F0_NPORTS 6 /* Six GPIO ports, GPIOA-F */
#else
# error "Unsupported STM32F0xx chip"
#endif
arch/arm/src/stm32/Kconfig
+6
View File
@@ -5627,6 +5627,12 @@ endmenu # Timer Configuration
menu "ADC Configuration"
depends on STM32_ADC
config STM32_ADC_NO_STARTUP_CONV
bool "Do not start conversion when opening ADC device"
default n
---help---
Do not start conversion when opening ADC device.
config STM32_ADC1_DMA
bool "ADC1 DMA"
depends on STM32_ADC1 && STM32_HAVE_ADC1_DMA
arch/arm/src/stm32/stm32_adc.c
+2 -2
View File
@@ -2054,11 +2054,11 @@ static void adc_reset(FAR struct adc_dev_s *dev)
aerr("ERROR: adc_timinit failed: %d\n", ret);
}
}
#ifndef CONFIG_ADC_NO_STARTUP_CONV
#ifndef CONFIG_STM32_ADC_NO_STARTUP_CONV
else
#endif
#endif
#ifndef CONFIG_ADC_NO_STARTUP_CONV
#ifndef CONFIG_STM32_ADC_NO_STARTUP_CONV
{
adc_startconv(priv, true);
}
arch/arm/src/stm32f0/Kconfig
+28 -108
View File
@@ -474,11 +474,10 @@ config STM32F0_VALUELINE
select STM32F0_HAVE_USART4
select STM32F0_HAVE_USART5
select STM32F0_HAVE_TIM1
select STM32F0_HAVE_TIM5
select STM32F0_HAVE_TIM2
select STM32F0_HAVE_TIM3
select STM32F0_HAVE_TIM6
select STM32F0_HAVE_TIM7
select STM32F0_HAVE_TIM12
select STM32F0_HAVE_TIM13
select STM32F0_HAVE_TIM14
select STM32F0_HAVE_TIM15
select STM32F0_HAVE_TIM16
@@ -489,46 +488,62 @@ config STM32F0_VALUELINE
config STM32F0_ACCESSLINE
bool
default n
select STM32F0_HAVE_OTGFS
select STM32F0_HAVE_USART3
select STM32F0_HAVE_USART4
select STM32F0_HAVE_USART5
select STM32F0_HAVE_TIM1
select STM32F0_HAVE_TIM5
select STM32F0_HAVE_TIM2
select STM32F0_HAVE_TIM3
select STM32F0_HAVE_TIM6
select STM32F0_HAVE_TIM7
select STM32F0_HAVE_TIM14
select STM32F0_HAVE_TIM15
select STM32F0_HAVE_TIM16
select STM32F0_HAVE_TIM17
select STM32F0_HAVE_ADC2
select STM32F0_HAVE_CAN1
select STM32F0_HAVE_CAN2
select STM32F0_HAVE_ETHMAC
select STM32F0_HAVE_SPI2
select STM32F0_HAVE_SPI3
config STM32F0_LOWVOLTLINE
bool
default n
select STM32F0_HAVE_OTGFS
select STM32F0_HAVE_USART3
select STM32F0_HAVE_USART4
select STM32F0_HAVE_USART5
select STM32F0_HAVE_TIM1
select STM32F0_HAVE_TIM5
select STM32F0_HAVE_TIM2
select STM32F0_HAVE_TIM3
select STM32F0_HAVE_TIM6
select STM32F0_HAVE_TIM7
select STM32F0_HAVE_TIM14
select STM32F0_HAVE_TIM15
select STM32F0_HAVE_TIM16
select STM32F0_HAVE_TIM17
select STM32F0_HAVE_ADC2
select STM32F0_HAVE_CAN1
select STM32F0_HAVE_CAN2
select STM32F0_HAVE_ETHMAC
select STM32F0_HAVE_SPI2
select STM32F0_HAVE_SPI3
config STM32F0_USBLINE
bool
default n
select STM32F0_HAVE_USBDEV
select STM32F0_HAVE_FSMC
select STM32F0_HAVE_USART3
select STM32F0_HAVE_USART4
select STM32F0_HAVE_TIM1
select STM32F0_HAVE_TIM2
select STM32F0_HAVE_TIM3
select STM32F0_HAVE_TIM6
select STM32F0_HAVE_TIM7
select STM32F0_HAVE_TIM14
select STM32F0_HAVE_TIM15
select STM32F0_HAVE_TIM16
select STM32F0_HAVE_TIM17
select STM32F0_HAVE_ADC2
select STM32F0_HAVE_CAN1
select STM32F0_HAVE_SPI2
select STM32F0_HAVE_SPI3
select STM32F0_HAVE_USBDEV
config STM32F0_DFU
bool "DFU bootloader"
@@ -565,10 +580,6 @@ config STM32F0_HAVE_USBDEV
bool
default n
config STM32F0_HAVE_OTGFS
bool
default n
config STM32F0_HAVE_FSMC
bool
default n
@@ -617,14 +628,6 @@ config STM32F0_HAVE_TIM3
bool
default n
config STM32F0_HAVE_TIM4
bool
default n
config STM32F0_HAVE_TIM5
bool
default n
config STM32F0_HAVE_TIM6
bool
default n
@@ -633,30 +636,6 @@ config STM32F0_HAVE_TIM7
bool
default n
config STM32F0_HAVE_TIM8
bool
default n
config STM32F0_HAVE_TIM9
bool
default n
config STM32F0_HAVE_TIM10
bool
default n
config STM32F0_HAVE_TIM11
bool
default n
config STM32F0_HAVE_TIM12
bool
default n
config STM32F0_HAVE_TIM13
bool
default n
config STM32F0_HAVE_TIM14
bool
default n
@@ -733,10 +712,6 @@ config STM32F0_HAVE_CAN1
bool
default n
config STM32F0_HAVE_CAN2
bool
default n
config STM32F0_HAVE_COMP1
bool
default n
@@ -777,10 +752,6 @@ config STM32F0_HAVE_RNG
bool
default n
config STM32F0_HAVE_ETHMAC
bool
default n
config STM32F0_HAVE_I2C2
bool
default n
@@ -930,13 +901,6 @@ config STM32F0_CAN1
select STM32F0_CAN
depends on STM32F0_HAVE_CAN1
config STM32F0_CAN2
bool "CAN2"
default n
select CAN
select STM32F0_CAN
depends on STM32F0_HAVE_CAN2
config STM32F0_CEC
bool "CEC"
default n
@@ -1083,16 +1047,6 @@ config STM32F0_TIM3
default n
depends on STM32F0_HAVE_TIM3
config STM32F0_TIM4
bool "TIM4"
default n
depends on STM32F0_HAVE_TIM4
config STM32F0_TIM5
bool "TIM5"
default n
depends on STM32F0_HAVE_TIM5
config STM32F0_TIM6
bool "TIM6"
default n
@@ -1103,36 +1057,6 @@ config STM32F0_TIM7
default n
depends on STM32F0_HAVE_TIM7
config STM32F0_TIM8
bool "TIM8"
default n
depends on STM32F0_HAVE_TIM8
config STM32F0_TIM9
bool "TIM9"
default n
depends on STM32F0_HAVE_TIM9
config STM32F0_TIM10
bool "TIM10"
default n
depends on STM32F0_HAVE_TIM10
config STM32F0_TIM11
bool "TIM11"
default n
depends on STM32F0_HAVE_TIM11
config STM32F0_TIM12
bool "TIM12"
default n
depends on STM32F0_HAVE_TIM12
config STM32F0_TIM13
bool "TIM13"
default n
depends on STM32F0_HAVE_TIM13
config STM32F0_TIM14
bool "TIM14"
default n
@@ -1291,7 +1215,6 @@ config USART1_RS485_DIR_POLARITY
endif # STM32F0_USART1_SERIALDRIVER
choice
prompt "USART2 Driver Configuration"
default STM32F0_USART2_SERIALDRIVER
@@ -1329,7 +1252,6 @@ config USART2_RS485_DIR_POLARITY
endif # STM32F0_USART2_SERIALDRIVER
choice
prompt "USART3 Driver Configuration"
default STM32F0_USART3_SERIALDRIVER
@@ -1481,7 +1403,6 @@ config USART6_RS485_DIR_POLARITY
endif # STM32F0_USART6_SERIALDRIVER
choice
prompt "USART7 Driver Configuration"
default STM32F0_USART7_SERIALDRIVER
@@ -1519,7 +1440,6 @@ config USART7_RS485_DIR_POLARITY
endif # STM32F0_USART7_SERIALDRIVER
choice
prompt "USART8 Driver Configuration"
default STM32F0_USART8_SERIALDRIVER
arch/arm/src/stm32f0/chip/stm32f05xr_pinmap.h → arch/arm/src/stm32f0/chip/stm32f05x_pinmap.h
+54 -45
View File
@@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0/chip/stm32f0_pinmap.h
* arch/arm/src/stm32f0/chip/stm32f05x_pinmap.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@@ -34,8 +34,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_PINMMAP_H
#define __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_PINMMAP_H
#ifndef __ARCH_ARM_SRC_STM32F0_CHIP_STM32F05X_PINMAP_H
#define __ARCH_ARM_SRC_STM32F0_CHIP_STM32F05X_PINMAP_H
/************************************************************************************
* Included Files
@@ -49,6 +49,25 @@
* Pre-processor Definitions
************************************************************************************/
/* Alternate Pin Functions.
*
* Alternative pin selections are provided with a numeric suffix like _1,
* _2, etc. Drivers, however, will use the pin selection without the numeric
* suffix. Additional definitions are required in the board.h file. For
* example, if USART1_TX connects vis PA9 on some board, then the following
* definition should appear inthe board.h header file for that board:
*
* #define GPIO_USART1_TX GPIO_USART1_TX_1
*
* The driver will then automatically configre PD0 as the CAN1 RX pin.
*/
/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
* Additional effort is required to select specific GPIO options such as frequency,
* open-drain/push-pull, and pull-up/down! Just the basics are defined for most
* pins in this file.
*/
/* ADC */
#define GPIO_ADC_IN0 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN0)
@@ -74,54 +93,44 @@
/* USART */
#if defined(CONFIG_STM32F0_USART1_REMAP)
# define GPIO_USART1_TX (GPIO_ALT|GPIO_AF0 |GPIO_PORTB|GPIO_PIN6)
# define GPIO_USART1_RX (GPIO_ALT|GPIO_AF0 |GPIO_PORTB|GPIO_PIN7)
#else
# define GPIO_USART1_TX (GPIO_ALT|GPIO_AF1 |GPIO_PORTA|GPIO_PIN9)
# define GPIO_USART1_RX (GPIO_ALT|GPIO_AF1 |GPIO_PORTA|GPIO_PIN10)
#endif
#define GPIO_USART1_CTS (GPIO_ALT|GPIO_AF1 |GPIO_PORTA|GPIO_PIN11)
#define GPIO_USART1_RTS (GPIO_ALT|GPIO_AF1 |GPIO_PORTA|GPIO_PIN12)
#define GPIO_USART1_CK (GPIO_ALT|GPIO_AF1 |GPIO_PORTA|GPIO_PIN8)
#define GPIO_USART1_TX_1 (GPIO_ALT|GPIO_AF1|GPIO_PORTA|GPIO_PIN9)
#define GPIO_USART1_TX_2 (GPIO_ALT|GPIO_AF0|GPIO_PORTB|GPIO_PIN6)
#define GPIO_USART1_RX_1 (GPIO_ALT|GPIO_AF1|GPIO_PORTA|GPIO_PIN10)
#define GPIO_USART1_RX_2 (GPIO_ALT|GPIO_AF0|GPIO_PORTB|GPIO_PIN7)
#define GPIO_USART1_CTS (GPIO_ALT|GPIO_AF1|GPIO_PORTA|GPIO_PIN11)
#define GPIO_USART1_RTS (GPIO_ALT|GPIO_AF1|GPIO_PORTA|GPIO_PIN12)
#define GPIO_USART1_CK (GPIO_ALT|GPIO_AF1|GPIO_PORTA|GPIO_PIN8)
#define GPIO_USART2_CTS (GPIO_ALT|GPIO_AF1 |GPIO_PORTA|GPIO_PIN0)
#define GPIO_USART2_RTS (GPIO_ALT|GPIO_AF1 |GPIO_PORTA|GPIO_PIN1)
#define GPIO_USART2_TX (GPIO_ALT|GPIO_AF1 |GPIO_PORTA|GPIO_PIN2)
#define GPIO_USART2_RX (GPIO_ALT|GPIO_AF1 |GPIO_PORTA|GPIO_PIN3)
#define GPIO_USART2_CK (GPIO_ALT|GPIO_AF1 |GPIO_PORTA|GPIO_PIN4)
#define GPIO_USART2_CTS (GPIO_ALT|GPIO_AF1|GPIO_PORTA|GPIO_PIN0)
#define GPIO_USART2_RTS (GPIO_ALT|GPIO_AF1|GPIO_PORTA|GPIO_PIN1)
#define GPIO_USART2_TX (GPIO_ALT|GPIO_AF1|GPIO_PORTA|GPIO_PIN2)
#define GPIO_USART2_RX (GPIO_ALT|GPIO_AF1|GPIO_PORTA|GPIO_PIN3)
#define GPIO_USART2_CK (GPIO_ALT|GPIO_AF1|GPIO_PORTA|GPIO_PIN4)
/* SPI */
#if defined(CONFIG_STM32F0_SPI1_REMAP)
# define GPIO_SPI1_NSS (GPIO_ALT|GPIO_AF0 |GPIO_PORTA|GPIO_PIN15)
# define GPIO_SPI1_SCK (GPIO_ALT|GPIO_AF0 |GPIO_PORTB|GPIO_PIN3)
# define GPIO_SPI1_MISO (GPIO_ALT|GPIO_AF0 |GPIO_PORTB|GPIO_PIN4)
# define GPIO_SPI1_MOSI (GPIO_ALT|GPIO_AF0 |GPIO_PORTB|GPIO_PIN5)
#else
# define GPIO_SPI1_NSS (GPIO_ALT|GPIO_AF0 |GPIO_PORTA|GPIO_PIN4)
# define GPIO_SPI1_SCK (GPIO_ALT|GPIO_AF0 |GPIO_PORTA|GPIO_PIN5)
# define GPIO_SPI1_MISO (GPIO_ALT|GPIO_AF0 |GPIO_PORTA|GPIO_PIN6)
# define GPIO_SPI1_MOSI (GPIO_ALT|GPIO_AF0 |GPIO_PORTA|GPIO_PIN7)
#endif
#define GPIO_SPI2_NSS (GPIO_ALT|GPIO_AF0 |GPIO_PORTB|GPIO_PIN12)
#define GPIO_SPI2_SCK (GPIO_ALT|GPIO_AF0 |GPIO_PORTB|GPIO_PIN13)
#define GPIO_SPI2_MISO (GPIO_ALT|GPIO_AF0 |GPIO_PORTB|GPIO_PIN14)
#define GPIO_SPI2_MOSI (GPIO_ALT|GPIO_AF0 |GPIO_PORTB|GPIO_PIN15)
#define GPIO_SPI1_NSS_1 (GPIO_ALT|GPIO_AF0|GPIO_PORTA|GPIO_PIN4)
#define GPIO_SPI1_NSS_2 (GPIO_ALT|GPIO_AF0|GPIO_PORTA|GPIO_PIN15)
#define GPIO_SPI1_SCK_1 (GPIO_ALT|GPIO_AF0|GPIO_PORTA|GPIO_PIN5)
#define GPIO_SPI1_SCK_2 (GPIO_ALT|GPIO_AF0|GPIO_PORTB|GPIO_PIN3)
#define GPIO_SPI1_MISO_1 (GPIO_ALT|GPIO_AF0|GPIO_PORTA|GPIO_PIN6)
#define GPIO_SPI1_MISO_2 (GPIO_ALT|GPIO_AF0|GPIO_PORTB|GPIO_PIN4)
#define GPIO_SPI1_MOSI_1 (GPIO_ALT|GPIO_AF0|GPIO_PORTA|GPIO_PIN7)
#define GPIO_SPI1_MOSI_2 (GPIO_ALT|GPIO_AF0|GPIO_PORTB|GPIO_PIN5)
#define GPIO_SPI2_NSS (GPIO_ALT|GPIO_AF0|GPIO_PORTB|GPIO_PIN12)
#define GPIO_SPI2_SCK (GPIO_ALT|GPIO_AF0|GPIO_PORTB|GPIO_PIN13)
#define GPIO_SPI2_MISO (GPIO_ALT|GPIO_AF0|GPIO_PORTB|GPIO_PIN14)
#define GPIO_SPI2_MOSI (GPIO_ALT|GPIO_AF0|GPIO_PORTB|GPIO_PIN15)
/* I2C */
#if defined(CONFIG_STM32F0_I2C1_REMAP)
# define GPIO_I2C1_SCL (GPIO_ALT|GPIO_AF1 |GPIO_PORTB|GPIO_PIN8)
# define GPIO_I2C1_SDA (GPIO_ALT|GPIO_AF1 |GPIO_PORTB|GPIO_PIN9)
#else
# define GPIO_I2C1_SCL (GPIO_ALT|GPIO_AF1 |GPIO_PORTB|GPIO_PIN6)
# define GPIO_I2C1_SDA (GPIO_ALT|GPIO_AF1 |GPIO_PORTB|GPIO_PIN7)
#endif
#define GPIO_I2C1_SMBA (GPIO_ALT|GPIO_AF3 |GPIO_PORTB|GPIO_PIN5)
#define GPIO_I2C1_SCL_1 (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN6)
#define GPIO_I2C1_SCL_2 (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN8)
#define GPIO_I2C1_SDA_1 (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN7)
#define GPIO_I2C1_SDA_2 (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN9)
#define GPIO_I2C1_SMBA (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN5)
#define GPIO_I2C2_SCL (GPIO_ALT|GPIO_AF1 |GPIO_PORTB|GPIO_PIN10)
#define GPIO_I2C2_SDA (GPIO_ALT|GPIO_AF1 |GPIO_PORTB|GPIO_PIN11)
#define GPIO_I2C2_SCL (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN10)
#define GPIO_I2C2_SDA (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN11)
#endif /* __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_PINMMAP_H */
#endif /* __ARCH_ARM_SRC_STM32F0_CHIP_STM32F05X_PINMAP_H */
arch/arm/src/stm32f0/chip/stm32f05xxx_memorymap.h → arch/arm/src/stm32f0/chip/stm32f05xf07x_memorymap.h
+5 -5
View File
@@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0/chip/stm32f05xxx_memorymap.h
* arch/arm/src/stm32f0/chip/stm32f05xf07x_memorymap.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@@ -34,14 +34,14 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0_CHIP_STM32F05XXX_MEMORYMAP_H
#define __ARCH_ARM_SRC_STM32F0_CHIP_STM32F05XXX_MEMORYMAP_H
#ifndef __ARCH_ARM_SRC_STM32F0_CHIP_ST32F05XF07X_MEMORYMAP_H
#define __ARCH_ARM_SRC_STM32F0_CHIP_ST32F05XF07X_MEMORYMAP_H
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* STM32F050XXX Address Blocks *******************************************************/
/* ST32F05XF07X Address Blocks ******************************************************/
#define STM32F0_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */
#define STM32F0_SRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: 512Mb sram block */
@@ -154,4 +154,4 @@
#define STM32F0_SCS_BASE 0xe000e000
#define STM32F0_DEBUGMCU_BASE 0xe0042000
#endif /* __ARCH_ARM_SRC_STM32F0_CHIP_STM32F30XXX_MEMORYMAP_H */
#endif /* __ARCH_ARM_SRC_STM32F0_CHIP_ST32F05XF07X_MEMORYMAP_H */
arch/arm/src/stm32f0/chip/stm32f07x_pinmap.h
+400
View File
@@ -0,0 +1,400 @@
/************************************************************************************
* arch/arm/src/stm32f0/chip/stm32f07x_pinmap.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* Alan Carvalho de Assis <acassis@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0_CHIP_STM32F07X_PINMAP_H
#define __ARCH_ARM_SRC_STM32F0_CHIP_STM32F07X_PINMAP_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "stm32f0_gpio.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Alternate Pin Functions.
*
* Alternative pin selections are provided with a numeric suffix like _1, _2, etc.
* Drivers, however, will use the pin selection without the numeric suffix.
* Additional definitions are required in the board.h file. For example, if
* CAN1_RX connects vis PD0 on some board, then the following definition should
* appear inthe board.h header file for that board:
*
* #define GPIO_CAN1_RX GPIO_CAN1_RX_1
*
* The driver will then automatically configre PD0 as the CAN1 RX pin.
*/
/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
* Additional effort is required to select specific GPIO options such as frequency,
* open-drain/push-pull, and pull-up/down! Just the basics are defined for most
* pins in this file.
*/
/* ADC */
#define GPIO_ADC_IN0 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN0)
#define GPIO_ADC_IN1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN1)
#define GPIO_ADC_IN2 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN2)
#define GPIO_ADC_IN3 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN3)
#define GPIO_ADC_IN4 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN4)
#define GPIO_ADC_IN5 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN5)
#define GPIO_ADC_IN6 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN6)
#define GPIO_ADC_IN7 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN7)
#define GPIO_ADC_IN8 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN0)
#define GPIO_ADC_IN9 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN1)
#define GPIO_ADC_IN10 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN0)
#define GPIO_ADC_IN11 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN1)
#define GPIO_ADC_IN12 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN2)
#define GPIO_ADC_IN13 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN3)
#define GPIO_ADC_IN14 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN4)
#define GPIO_ADC_IN15 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN5)
/* CAN */
#define GPIO_CAN_RX_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTD | GPIO_PIN0)
#define GPIO_CAN_RX_2 (GPIO_ALT | GPIO_AF4 | GPIO_PORTA | GPIO_PIN11)
#define GPIO_CAN_RX_3 (GPIO_ALT | GPIO_AF4 | GPIO_PORTB | GPIO_PIN8)
#define GPIO_CAN_TX_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTD | GPIO_PIN1)
#define GPIO_CAN_TX_3 (GPIO_ALT | GPIO_AF4 | GPIO_PORTA | GPIO_PIN12)
#define GPIO_CAN_TX_4 (GPIO_ALT | GPIO_AF4 | GPIO_PORTB | GPIO_PIN9)
/* HDMI-CEC */
#define GPIO_CEC_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN10)
#define GPIO_CEC_2 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN8)
#define GPIO_CEC_3 (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN5)
/* Analog Comparators */
#define GPIO_COMP1_OUT_1 (GPIO_ALT | GPIO_AF7 | GPIO_PORTA | GPIO_PIN0)
#define GPIO_COMP1_OUT_2 (GPIO_ALT | GPIO_AF7 | GPIO_PORTA | GPIO_PIN11)
#define GPIO_COMP1_OUT_3 (GPIO_ALT | GPIO_AF7 | GPIO_PORTA | GPIO_PIN6)
#define GPIO_COMP2_OUT_1 (GPIO_ALT | GPIO_AF7 | GPIO_PORTA | GPIO_PIN12)
#define GPIO_COMP2_OUT_2 (GPIO_ALT | GPIO_AF7 | GPIO_PORTA | GPIO_PIN2)
#define GPIO_COMP2_OUT_3 (GPIO_ALT | GPIO_AF7 | GPIO_PORTA | GPIO_PIN7)
/* CRS */
#define GPIO_CRS_SYNC_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTD | GPIO_PIN15)
#define GPIO_CRS_SYNC_2 (GPIO_ALT | GPIO_AF0 | GPIO_PORTF | GPIO_PIN0)
#define GPIO_CRS_SYNC_3 (GPIO_ALT | GPIO_AF4 | GPIO_PORTA | GPIO_PIN8)
/* Events */
#define GPIO_EVENTOUT_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN1)
#define GPIO_EVENTOUT_2 (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN11)
#define GPIO_EVENTOUT_3 (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN12)
#define GPIO_EVENTOUT_4 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN0)
#define GPIO_EVENTOUT_5 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN11)
#define GPIO_EVENTOUT_6 (GPIO_ALT | GPIO_AF0 | GPIO_PORTC | GPIO_PIN0)
#define GPIO_EVENTOUT_7 (GPIO_ALT | GPIO_AF0 | GPIO_PORTC | GPIO_PIN1)
#define GPIO_EVENTOUT_8 (GPIO_ALT | GPIO_AF0 | GPIO_PORTC | GPIO_PIN2)
#define GPIO_EVENTOUT_9 (GPIO_ALT | GPIO_AF0 | GPIO_PORTC | GPIO_PIN3)
#define GPIO_EVENTOUT_10 (GPIO_ALT | GPIO_AF0 | GPIO_PORTC | GPIO_PIN4)
#define GPIO_EVENTOUT_11 (GPIO_ALT | GPIO_AF0 | GPIO_PORTF | GPIO_PIN2)
#define GPIO_EVENTOUT_12 (GPIO_ALT | GPIO_AF0 | GPIO_PORTF | GPIO_PIN3)
#define GPIO_EVENTOUT_13 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN12)
#define GPIO_EVENTOUT_14 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN3)
#define GPIO_EVENTOUT_15 (GPIO_ALT | GPIO_AF1 | GPIO_PORTE | GPIO_PIN0)
#define GPIO_EVENTOUT_16 (GPIO_ALT | GPIO_AF1 | GPIO_PORTE | GPIO_PIN1)
#define GPIO_EVENTOUT_17 (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN4)
#define GPIO_EVENTOUT_18 (GPIO_ALT | GPIO_AF3 | GPIO_PORTA | GPIO_PIN15)
#define GPIO_EVENTOUT_19 (GPIO_ALT | GPIO_AF3 | GPIO_PORTA | GPIO_PIN8)
#define GPIO_EVENTOUT_20 (GPIO_ALT | GPIO_AF3 | GPIO_PORTB | GPIO_PIN9)
#define GPIO_EVENTOUT_21 (GPIO_ALT | GPIO_AF6 | GPIO_PORTA | GPIO_PIN6)
#define GPIO_EVENTOUT_22 (GPIO_ALT | GPIO_AF6 | GPIO_PORTA | GPIO_PIN7)
/* I2C */
#define GPIO_I2C1_SCL_1 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN6)
#define GPIO_I2C1_SCL_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN8)
#define GPIO_I2C1_SDA_1 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN7)
#define GPIO_I2C1_SDA_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN9)
#define GPIO_I2C1_SMBA (GPIO_ALT | GPIO_AF3 | GPIO_PORTB | GPIO_PIN5)
#define GPIO_I2C2_SCL_1 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN10)
#define GPIO_I2C2_SCL_2 (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN13)
#define GPIO_I2C2_SDA_1 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN11)
#define GPIO_I2C2_SDA_2 (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN14)
/* I2S */
#define GPIO_I2S1_CK_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN5)
#define GPIO_I2S1_CK_2 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN3)
#define GPIO_I2S1_CK_3 (GPIO_ALT | GPIO_AF1 | GPIO_PORTE | GPIO_PIN13)
#define GPIO_I2S1_MCK_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN6)
#define GPIO_I2S1_MCK_2 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN4)
#define GPIO_I2S1_MCK_3 (GPIO_ALT | GPIO_AF1 | GPIO_PORTE | GPIO_PIN14)
#define GPIO_I2S1_SD_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN7)
#define GPIO_I2S1_SD_2 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN5)
#define GPIO_I2S1_SD_3 (GPIO_ALT | GPIO_AF1 | GPIO_PORTE | GPIO_PIN15)
#define GPIO_I2S1_WS_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN15)
#define GPIO_I2S1_WS_2 (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN4)
#define GPIO_I2S1_WS_3 (GPIO_ALT | GPIO_AF1 | GPIO_PORTE | GPIO_PIN12)
#define GPIO_I2S2_CK_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN13)
#define GPIO_I2S2_CK_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTD | GPIO_PIN1)
#define GPIO_I2S2_CK_3 (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN10)
#define GPIO_I2S2_MCK_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN14)
#define GPIO_I2S2_MCK_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTC | GPIO_PIN2)
#define GPIO_I2S2_MCK_3 (GPIO_ALT | GPIO_AF1 | GPIO_PORTD | GPIO_PIN3)
#define GPIO_I2S2_SD_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN15)
#define GPIO_I2S2_SD_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTC | GPIO_PIN3)
#define GPIO_I2S2_SD_3 (GPIO_ALT | GPIO_AF1 | GPIO_PORTD | GPIO_PIN4)
#define GPIO_I2S2_WS_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN12)
#define GPIO_I2S2_WS_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTD | GPIO_PIN0)
#define GPIO_I2S2_WS_3 (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN9)
/* IR */
#define GPIO_IR_OUT_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN9)
#define GPIO_IR_OUT_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN13)
/* Clock output */
#define GPIO_MCO (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN8)
/* SPI */
#define GPIO_SPI1_MISO_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN6)
#define GPIO_SPI1_MISO_2 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN4)
#define GPIO_SPI1_MISO_3 (GPIO_ALT | GPIO_AF1 | GPIO_PORTE | GPIO_PIN14)
#define GPIO_SPI1_MOSI_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN7)
#define GPIO_SPI1_MOSI_2 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN5)
#define GPIO_SPI1_MOSI_3 (GPIO_ALT | GPIO_AF1 | GPIO_PORTE | GPIO_PIN15)
#define GPIO_SPI1_NSS_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN15)
#define GPIO_SPI1_NSS_2 (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN4)
#define GPIO_SPI1_NSS_3 (GPIO_ALT | GPIO_AF1 | GPIO_PORTE | GPIO_PIN12)
#define GPIO_SPI1_SCK_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN5)
#define GPIO_SPI1_SCK_2 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN3)
#define GPIO_SPI1_SCK_3 (GPIO_ALT | GPIO_AF1 | GPIO_PORTE | GPIO_PIN13)
#define GPIO_SPI2_MISO_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN14)
#define GPIO_SPI2_MISO_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTC | GPIO_PIN2)
#define GPIO_SPI2_MISO_3 (GPIO_ALT | GPIO_AF1 | GPIO_PORTD | GPIO_PIN3)
#define GPIO_SPI2_MOSI_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN15)
#define GPIO_SPI2_MOSI_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTC | GPIO_PIN3)
#define GPIO_SPI2_MOSI_3 (GPIO_ALT | GPIO_AF1 | GPIO_PORTD | GPIO_PIN4)
#define GPIO_SPI2_NSS_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN12)
#define GPIO_SPI2_NSS_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTD | GPIO_PIN0)
#define GPIO_SPI2_NSS_3 (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN9)
#define GPIO_SPI2_SCK_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN13)
#define GPIO_SPI2_SCK_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTD | GPIO_PIN1)
#define GPIO_SPI2_SCK_3 (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN10)
/* SWD */
#define GPIO_SWCLK (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN14)
#define GPIO_SWDIO (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN13)
/* Timers */
#define GPIO_TIM1_BKIN_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTE | GPIO_PIN15)
#define GPIO_TIM1_BKIN_2 (GPIO_ALT | GPIO_AF2 | GPIO_PORTA | GPIO_PIN6)
#define GPIO_TIM1_BKIN_3 (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN12)
#define GPIO_TIM1_CH1_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTE | GPIO_PIN9)
#define GPIO_TIM1_CH1_2 (GPIO_ALT | GPIO_AF2 | GPIO_PORTA | GPIO_PIN8)
#define GPIO_TIM1_CH1N_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTE | GPIO_PIN8)
#define GPIO_TIM1_CH1N_2 (GPIO_ALT | GPIO_AF2 | GPIO_PORTA | GPIO_PIN7)
#define GPIO_TIM1_CH1N_3 (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN13)
#define GPIO_TIM1_CH2_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTE | GPIO_PIN11)
#define GPIO_TIM1_CH2_2 (GPIO_ALT | GPIO_AF2 | GPIO_PORTA | GPIO_PIN9)
#define GPIO_TIM1_CH2N_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTE | GPIO_PIN10)
#define GPIO_TIM1_CH2N_2 (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN0)
#define GPIO_TIM1_CH2N_3 (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN14)
#define GPIO_TIM1_CH3_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTE | GPIO_PIN13)
#define GPIO_TIM1_CH3_2 (GPIO_ALT | GPIO_AF2 | GPIO_PORTA | GPIO_PIN10)
#define GPIO_TIM1_CH3N_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTE | GPIO_PIN12)
#define GPIO_TIM1_CH3N_2 (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN1)
#define GPIO_TIM1_CH3N_3 (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN15)
#define GPIO_TIM1_CH4_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTE | GPIO_PIN14)
#define GPIO_TIM1_CH4_2 (GPIO_ALT | GPIO_AF2 | GPIO_PORTA | GPIO_PIN11)
#define GPIO_TIM1_ETR_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTE | GPIO_PIN7)
#define GPIO_TIM1_ETR_2 (GPIO_ALT | GPIO_AF2 | GPIO_PORTA | GPIO_PIN12)
#define GPIO_TIM2_CH1_ETR_1 (GPIO_ALT | GPIO_AF2 | GPIO_PORTA | GPIO_PIN0)
#define GPIO_TIM2_CH1_ETR_2 (GPIO_ALT | GPIO_AF2 | GPIO_PORTA | GPIO_PIN15)
#define GPIO_TIM2_CH1_ETR_3 (GPIO_ALT | GPIO_AF2 | GPIO_PORTA | GPIO_PIN5)
#define GPIO_TIM2_CH2_1 (GPIO_ALT | GPIO_AF2 | GPIO_PORTA | GPIO_PIN1)
#define GPIO_TIM2_CH2_2 (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN3)
#define GPIO_TIM2_CH3_1 (GPIO_ALT | GPIO_AF2 | GPIO_PORTA | GPIO_PIN2)
#define GPIO_TIM2_CH3_2 (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN10)
#define GPIO_TIM2_CH4_1 (GPIO_ALT | GPIO_AF2 | GPIO_PORTA | GPIO_PIN3)
#define GPIO_TIM2_CH4_2 (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN11)
#define GPIO_TIM3_CH1_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTC | GPIO_PIN6)
#define GPIO_TIM3_CH1_2 (GPIO_ALT | GPIO_AF0 | GPIO_PORTE | GPIO_PIN3)
#define GPIO_TIM3_CH1_3 (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN6)
#define GPIO_TIM3_CH1_4 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN4)
#define GPIO_TIM3_CH2_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTC | GPIO_PIN7)
#define GPIO_TIM3_CH2_2 (GPIO_ALT | GPIO_AF0 | GPIO_PORTE | GPIO_PIN4)
#define GPIO_TIM3_CH2_3 (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN7)
#define GPIO_TIM3_CH2_4 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN5)
#define GPIO_TIM3_CH3_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTC | GPIO_PIN8)
#define GPIO_TIM3_CH3_2 (GPIO_ALT | GPIO_AF0 | GPIO_PORTE | GPIO_PIN5)
#define GPIO_TIM3_CH3_3 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN0)
#define GPIO_TIM3_CH4_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTC | GPIO_PIN9)
#define GPIO_TIM3_CH4_2 (GPIO_ALT | GPIO_AF0 | GPIO_PORTE | GPIO_PIN6)
#define GPIO_TIM3_CH4_3 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN1)
#define GPIO_TIM3_ETR_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTD | GPIO_PIN2)
#define GPIO_TIM3_ETR_2 (GPIO_ALT | GPIO_AF0 | GPIO_PORTE | GPIO_PIN2)
#define GPIO_TIM14_CH1_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN1)
#define GPIO_TIM14_CH1_2 (GPIO_ALT | GPIO_AF4 | GPIO_PORTA | GPIO_PIN4)
#define GPIO_TIM14_CH1_3 (GPIO_ALT | GPIO_AF4 | GPIO_PORTA | GPIO_PIN7)
#define GPIO_TIM15_BKIN_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN9)
#define GPIO_TIM15_BKIN_2 (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN12)
#define GPIO_TIM15_CH1_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN2)
#define GPIO_TIM15_CH1_2 (GPIO_ALT | GPIO_AF0 | GPIO_PORTF | GPIO_PIN9)
#define GPIO_TIM15_CH1_3 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN14)
#define GPIO_TIM15_CH1N_1 (GPIO_ALT | GPIO_AF3 | GPIO_PORTB | GPIO_PIN15)
#define GPIO_TIM15_CH1N_2 (GPIO_ALT | GPIO_AF5 | GPIO_PORTA | GPIO_PIN1)
#define GPIO_TIM15_CH2_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN3)
#define GPIO_TIM15_CH2_2 (GPIO_ALT | GPIO_AF0 | GPIO_PORTF | GPIO_PIN10)
#define GPIO_TIM15_CH2_3 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN15)
#define GPIO_TIM16_BKIN (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN5)
#define GPIO_TIM16_CH1_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTE | GPIO_PIN0)
#define GPIO_TIM16_CH1_2 (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN8)
#define GPIO_TIM16_CH1_3 (GPIO_ALT | GPIO_AF5 | GPIO_PORTA | GPIO_PIN6)
#define GPIO_TIM16_CH1N (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN6)
#define GPIO_TIM17_BKIN_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN10)
#define GPIO_TIM17_BKIN_2 (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN4)
#define GPIO_TIM17_CH1_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTE | GPIO_PIN1)
#define GPIO_TIM17_CH1_2 (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN9)
#define GPIO_TIM17_CH1_3 (GPIO_ALT | GPIO_AF5 | GPIO_PORTA | GPIO_PIN7)
#define GPIO_TIM17_CH1N (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN7)
/* TSC */
#define GPIO_TSC_G1_IO1 (GPIO_ALT | GPIO_AF3 | GPIO_PORTA | GPIO_PIN0)
#define GPIO_TSC_G1_IO2 (GPIO_ALT | GPIO_AF3 | GPIO_PORTA | GPIO_PIN1)
#define GPIO_TSC_G1_IO3 (GPIO_ALT | GPIO_AF3 | GPIO_PORTA | GPIO_PIN2)
#define GPIO_TSC_G1_IO4 (GPIO_ALT | GPIO_AF3 | GPIO_PORTA | GPIO_PIN3)
#define GPIO_TSC_G2_IO1 (GPIO_ALT | GPIO_AF3 | GPIO_PORTA | GPIO_PIN4)
#define GPIO_TSC_G2_IO2 (GPIO_ALT | GPIO_AF3 | GPIO_PORTA | GPIO_PIN5)
#define GPIO_TSC_G2_IO3 (GPIO_ALT | GPIO_AF3 | GPIO_PORTA | GPIO_PIN6)
#define GPIO_TSC_G2_IO4 (GPIO_ALT | GPIO_AF3 | GPIO_PORTA | GPIO_PIN7)
#define GPIO_TSC_G3_IO1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTC | GPIO_PIN5)
#define GPIO_TSC_G3_IO2 (GPIO_ALT | GPIO_AF3 | GPIO_PORTB | GPIO_PIN0)
#define GPIO_TSC_G3_IO3 (GPIO_ALT | GPIO_AF3 | GPIO_PORTB | GPIO_PIN1)
#define GPIO_TSC_G3_IO4 (GPIO_ALT | GPIO_AF3 | GPIO_PORTB | GPIO_PIN2)
#define GPIO_TSC_G4_IO1 (GPIO_ALT | GPIO_AF3 | GPIO_PORTA | GPIO_PIN9)
#define GPIO_TSC_G4_IO2 (GPIO_ALT | GPIO_AF3 | GPIO_PORTA | GPIO_PIN10)
#define GPIO_TSC_G4_IO3 (GPIO_ALT | GPIO_AF3 | GPIO_PORTA | GPIO_PIN11)
#define GPIO_TSC_G4_IO4 (GPIO_ALT | GPIO_AF3 | GPIO_PORTA | GPIO_PIN12)
#define GPIO_TSC_G5_IO1 (GPIO_ALT | GPIO_AF3 | GPIO_PORTB | GPIO_PIN3)
#define GPIO_TSC_G5_IO2 (GPIO_ALT | GPIO_AF3 | GPIO_PORTB | GPIO_PIN4)
#define GPIO_TSC_G5_IO3 (GPIO_ALT | GPIO_AF3 | GPIO_PORTB | GPIO_PIN6)
#define GPIO_TSC_G5_IO4 (GPIO_ALT | GPIO_AF3 | GPIO_PORTB | GPIO_PIN7)
#define GPIO_TSC_G6_IO1 (GPIO_ALT | GPIO_AF3 | GPIO_PORTB | GPIO_PIN11)
#define GPIO_TSC_G6_IO2 (GPIO_ALT | GPIO_AF3 | GPIO_PORTB | GPIO_PIN12)
#define GPIO_TSC_G6_IO3 (GPIO_ALT | GPIO_AF3 | GPIO_PORTB | GPIO_PIN13)
#define GPIO_TSC_G6_IO4 (GPIO_ALT | GPIO_AF3 | GPIO_PORTB | GPIO_PIN14)
#define GPIO_TSC_G7_IO1 (GPIO_ALT | GPIO_AF1 | GPIO_PORTE | GPIO_PIN2)
#define GPIO_TSC_G7_IO2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTE | GPIO_PIN3)
#define GPIO_TSC_G7_IO3 (GPIO_ALT | GPIO_AF1 | GPIO_PORTE | GPIO_PIN4)
#define GPIO_TSC_G7_IO4 (GPIO_ALT | GPIO_AF1 | GPIO_PORTE | GPIO_PIN5)
#define GPIO_TSC_G8_IO1 (GPIO_ALT | GPIO_AF1 | GPIO_PORTD | GPIO_PIN12)
#define GPIO_TSC_G8_IO2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTD | GPIO_PIN13)
#define GPIO_TSC_G8_IO3 (GPIO_ALT | GPIO_AF1 | GPIO_PORTD | GPIO_PIN14)
#define GPIO_TSC_G8_IO4 (GPIO_ALT | GPIO_AF1 | GPIO_PORTD | GPIO_PIN15)
#define GPIO_TSC_SYNC_1 (GPIO_ALT | GPIO_AF3 | GPIO_PORTB | GPIO_PIN10)
#define GPIO_TSC_SYNC_2 (GPIO_ALT | GPIO_AF3 | GPIO_PORTB | GPIO_PIN8)
/* USARTs */
#define GPIO_USART1_CK (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN8)
#define GPIO_USART1_CTS (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN11)
#define GPIO_USART1_RTS (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN12)
#define GPIO_USART1_RX_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN7)
#define GPIO_USART1_RX_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN10)
#define GPIO_USART1_TX_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN6)
#define GPIO_USART1_TX_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN9)
#define GPIO_USART2_CK_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTD | GPIO_PIN7)
#define GPIO_USART2_CK_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN4)
#define GPIO_USART2_CTS_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTD | GPIO_PIN3)
#define GPIO_USART2_CTS_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN0)
#define GPIO_USART2_RTS_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTD | GPIO_PIN4)
#define GPIO_USART2_RTS_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN1)
#define GPIO_USART2_RX_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTD | GPIO_PIN6)
#define GPIO_USART2_RX_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN15)
#define GPIO_USART2_RX_3 (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN3)
#define GPIO_USART2_TX_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTD | GPIO_PIN5)
#define GPIO_USART2_TX_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN14)
#define GPIO_USART2_TX_3 (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN2)
#define GPIO_USART3_CK_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTD | GPIO_PIN10)
#define GPIO_USART3_CK_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTC | GPIO_PIN12)
#define GPIO_USART3_CK_3 (GPIO_ALT | GPIO_AF4 | GPIO_PORTB | GPIO_PIN0)
#define GPIO_USART3_CK_4 (GPIO_ALT | GPIO_AF4 | GPIO_PORTB | GPIO_PIN12)
#define GPIO_USART3_CTS_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTD | GPIO_PIN11)
#define GPIO_USART3_CTS_2 (GPIO_ALT | GPIO_AF4 | GPIO_PORTA | GPIO_PIN6)
#define GPIO_USART3_CTS_3 (GPIO_ALT | GPIO_AF4 | GPIO_PORTB | GPIO_PIN13)
#define GPIO_USART3_RTS_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTD | GPIO_PIN12)
#define GPIO_USART3_RTS_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTD | GPIO_PIN2)
#define GPIO_USART3_RTS_3 (GPIO_ALT | GPIO_AF4 | GPIO_PORTB | GPIO_PIN1)
#define GPIO_USART3_RTS_4 (GPIO_ALT | GPIO_AF4 | GPIO_PORTB | GPIO_PIN14)
#define GPIO_USART3_RX_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTD | GPIO_PIN9)
#define GPIO_USART3_RX_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTC | GPIO_PIN11)
#define GPIO_USART3_RX_3 (GPIO_ALT | GPIO_AF1 | GPIO_PORTC | GPIO_PIN5)
#define GPIO_USART3_RX_4 (GPIO_ALT | GPIO_AF4 | GPIO_PORTB | GPIO_PIN11)
#define GPIO_USART3_TX_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTD | GPIO_PIN8)
#define GPIO_USART3_TX_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTC | GPIO_PIN10)
#define GPIO_USART3_TX_3 (GPIO_ALT | GPIO_AF1 | GPIO_PORTC | GPIO_PIN4)
#define GPIO_USART3_TX_4 (GPIO_ALT | GPIO_AF4 | GPIO_PORTB | GPIO_PIN10)
#define GPIO_USART4_CK (GPIO_ALT | GPIO_AF0 | GPIO_PORTC | GPIO_PIN12)
#define GPIO_USART4_CTS (GPIO_ALT | GPIO_AF4 | GPIO_PORTB | GPIO_PIN7)
#define GPIO_USART4_RTS (GPIO_ALT | GPIO_AF4 | GPIO_PORTA | GPIO_PIN15)
#define GPIO_USART4_RX_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTC | GPIO_PIN11)
#define GPIO_USART4_RX_2 (GPIO_ALT | GPIO_AF4 | GPIO_PORTA | GPIO_PIN1)
#define GPIO_USART4_TX_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTC | GPIO_PIN10)
#define GPIO_USART4_TX_2 (GPIO_ALT | GPIO_AF4 | GPIO_PORTA | GPIO_PIN0)
/* USB */
#define GPIO_USB_NOE (GPIO_ALT | GPIO_AF2 | GPIO_PORTA | GPIO_PIN13)
#endif /* __ARCH_ARM_SRC_STM32F0_CHIP_STM32F07X_PINMAP_H */
arch/arm/src/stm32f0/chip/stm32f0_dma.h
+5 -5
View File
@@ -434,7 +434,7 @@
#define DMACHAN_TIM17_UP_1 DMACHAN_SETTING(STM32F0_DMA1_CHAN1, 5)
#define DMACHAN_TIM17_UP_2 DMACHAN_SETTING(STM32F0_DMA1_CHAN7, 5)
/* UART */
/* USARTs */
#define DMACHAN_USART1_RX_1 DMACHAN_SETTING(STM32F0_DMA1_CHAN5, 2)
#define DMACHAN_USART1_RX_2 DMACHAN_SETTING(STM32F0_DMA2_CHAN7, 2)
@@ -447,10 +447,10 @@
#define DMACHAN_USART3_RX DMACHAN_SETTING(STM32F0_DMA1_CHAN3, 1)
#define DMACHAN_USART3_TX DMACHAN_SETTING(STM32F0_DMA1_CHAN2, 2)
#define DMACHAN_UART5_RX DMACHAN_SETTING(STM32F0_DMA2_CHAN2, 2)
#define DMACHAN_UART5_TX DMACHAN_SETTING(STM32F0_DMA2_CHAN1, 2)
#define DMACHAN_USART4_RX DMACHAN_SETTING(STM32F0_DMA2_CHAN5, 2)
#define DMACHAN_USART4_TX DMACHAN_SETTING(STM32F0_DMA2_CHAN3, 2)
#define DMACHAN_UART4_RX DMACHAN_SETTING(STM32F0_DMA2_CHAN5, 2)
#define DMACHAN_UART4_TX DMACHAN_SETTING(STM32F0_DMA2_CHAN3, 2)
#define DMACHAN_USART5_RX DMACHAN_SETTING(STM32F0_DMA2_CHAN2, 2)
#define DMACHAN_USART5_TX DMACHAN_SETTING(STM32F0_DMA2_CHAN1, 2)
#endif /* __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_DMA_H */
arch/arm/src/stm32f0/chip/stm32f0_memorymap.h
+2 -2
View File
@@ -44,8 +44,8 @@
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32F0_STM32F05X)
# include "chip/stm32f05xxx_memorymap.h"
#if defined(CONFIG_STM32F0_STM32F05X) || defined(CONFIG_STM32F0_STM32F07X)
# include "chip/stm32f05xf07x_memorymap.h"
#else
# error "Unsupported STM32 memory map"
#endif
arch/arm/src/stm32f0/chip/stm32f0_pinmap.h
+3 -1
View File
@@ -44,7 +44,9 @@
#include "chip.h"
#if defined(CONFIG_STM32F0_STM32F05X)
# include "chip/stm32f05xr_pinmap.h"
# include "chip/stm32f05x_pinmap.h"
#elif defined(CONFIG_STM32F0_STM32F07X)
# include "chip/stm32f07x_pinmap.h"
#else
# error "Unsupported STM32F0 pin map"
#endif
arch/arm/src/stm32f0/chip/stm32f0_rcc.h
+4 -4
View File
@@ -222,8 +222,8 @@
#define RCC_APB1RSTR_SPI2RST (1 << 14) /* Bit 14: SPI 2 reset */
#define RCC_APB1RSTR_USART2RST (1 << 17) /* Bit 17: USART 2 reset */
#define RCC_APB1RSTR_USART3RST (1 << 18) /* Bit 18: USART 3 reset */
#define RCC_APB1RSTR_UART4RST (1 << 19) /* Bit 19: UART 4 reset */
#define RCC_APB1RSTR_UART5RST (1 << 20) /* Bit 20: UART 5 reset */
#define RCC_APB1RSTR_USART4RST (1 << 19) /* Bit 19: USART 4 reset */
#define RCC_APB1RSTR_USART5RST (1 << 20) /* Bit 20: USART 5 reset */
#define RCC_APB1RSTR_I2C1RST (1 << 21) /* Bit 21: I2C 1 reset */
#define RCC_APB1RSTR_I2C2RST (1 << 22) /* Bit 22: I2C 2 reset */
#define RCC_APB1RSTR_USBRST (1 << 23) /* Bit 23: USB reset */
@@ -275,8 +275,8 @@
#define RCC_APB1ENR_SPI2EN (1 << 14) /* Bit 14: SPI 2 clock enable */
#define RCC_APB1ENR_USART2EN (1 << 17) /* Bit 17: USART 2 clock enable */
#define RCC_APB1ENR_USART3EN (1 << 18) /* Bit 18: USART 3 clock enable */
#define RCC_APB1ENR_UART4EN (1 << 19) /* Bit 19: UART 4 clock enable */
#define RCC_APB1ENR_UART5EN (1 << 20) /* Bit 20: UART 5 clock enable */
#define RCC_APB1ENR_USART4EN (1 << 19) /* Bit 19: USART 4 clock enable */
#define RCC_APB1ENR_USART5EN (1 << 20) /* Bit 20: USART 5 clock enable */
#define RCC_APB1ENR_I2C1EN (1 << 21) /* Bit 21: I2C 1 clock enable */
#define RCC_APB1ENR_I2C2EN (1 << 22) /* Bit 22: I2C 2 clock enable */
#define RCC_APB1ENR_USBEN (1 << 23) /* Bit 23: USB clock enable */
arch/arm/src/stm32f0/chip/stm32f0_uart.h
+22 -64
View File
@@ -108,73 +108,31 @@
#endif
#if STM32F0_NUSART > 3
# define STM32F0_UART4_CR1 (STM32F0_UART4_BASE+STM32F0_USART_CR1_OFFSET)
# define STM32F0_UART4_CR2 (STM32F0_UART4_BASE+STM32F0_USART_CR2_OFFSET)
# define STM32F0_UART4_CR3 (STM32F0_UART4_BASE+STM32F0_USART_CR3_OFFSET)
# define STM32F0_UART4_BRR (STM32F0_UART4_BASE+STM32F0_USART_BRR_OFFSET)
# define STM32F0_UART4_GTPR (STM32F0_UART4_BASE+STM32F0_USART_GTPR_OFFSET)
# define STM32F0_UART4_RTOR (STM32F0_UART4_BASE+STM32F0_USART_RTOR_OFFSET)
# define STM32F0_UART4_RQR (STM32F0_UART4_BASE+STM32F0_USART_RQR_OFFSET)
# define STM32F0_UART4_ISR (STM32F0_UART4_BASE+STM32F0_USART_ISR_OFFSET)
# define STM32F0_UART4_ICR (STM32F0_UART4_BASE+STM32F0_USART_ICR_OFFSET)
# define STM32F0_UART4_RDR (STM32F0_UART4_BASE+STM32F0_USART_RDR_OFFSET)
# define STM32F0_UART4_TDR (STM32F0_UART4_BASE+STM32F0_USART_TDR_OFFSET)
# define STM32F0_USART4_CR1 (STM32F0_USART4_BASE+STM32F0_USART_CR1_OFFSET)
# define STM32F0_USART4_CR2 (STM32F0_USART4_BASE+STM32F0_USART_CR2_OFFSET)
# define STM32F0_USART4_CR3 (STM32F0_USART4_BASE+STM32F0_USART_CR3_OFFSET)
# define STM32F0_USART4_BRR (STM32F0_USART4_BASE+STM32F0_USART_BRR_OFFSET)
# define STM32F0_USART4_GTPR (STM32F0_USART4_BASE+STM32F0_USART_GTPR_OFFSET)
# define STM32F0_USART4_RTOR (STM32F0_USART4_BASE+STM32F0_USART_RTOR_OFFSET)
# define STM32F0_USART4_RQR (STM32F0_USART4_BASE+STM32F0_USART_RQR_OFFSET)
# define STM32F0_USART4_ISR (STM32F0_USART4_BASE+STM32F0_USART_ISR_OFFSET)
# define STM32F0_USART4_ICR (STM32F0_USART4_BASE+STM32F0_USART_ICR_OFFSET)
# define STM32F0_USART4_RDR (STM32F0_USART4_BASE+STM32F0_USART_RDR_OFFSET)
# define STM32F0_USART4_TDR (STM32F0_USART4_BASE+STM32F0_USART_TDR_OFFSET)
#endif
#if STM32F0_NUSART > 4
# define STM32F0_UART5_CR1 (STM32F0_UART5_BASE+STM32F0_USART_CR1_OFFSET)
# define STM32F0_UART5_CR2 (STM32F0_UART5_BASE+STM32F0_USART_CR2_OFFSET)
# define STM32F0_UART5_CR3 (STM32F0_UART5_BASE+STM32F0_USART_CR3_OFFSET)
# define STM32F0_UART5_BRR (STM32F0_UART5_BASE+STM32F0_USART_BRR_OFFSET)
# define STM32F0_UART5_GTPR (STM32F0_UART5_BASE+STM32F0_USART_GTPR_OFFSET)
# define STM32F0_UART5_RTOR (STM32F0_UART5_BASE+STM32F0_USART_RTOR_OFFSET)
# define STM32F0_UART5_RQR (STM32F0_UART5_BASE+STM32F0_USART_RQR_OFFSET)
# define STM32F0_UART5_ISR (STM32F0_UART5_BASE+STM32F0_USART_ISR_OFFSET)
# define STM32F0_UART5_ICR (STM32F0_UART5_BASE+STM32F0_USART_ICR_OFFSET)
# define STM32F0_UART5_RDR (STM32F0_UART5_BASE+STM32F0_USART_RDR_OFFSET)
# define STM32F0_UART5_TDR (STM32F0_UART5_BASE+STM32F0_USART_TDR_OFFSET)
#endif
#if STM32F0_NUSART > 5
# define STM32F0_UART6_CR1 (STM32F0_UART6_BASE+STM32F0_USART_CR1_OFFSET)
# define STM32F0_UART6_CR2 (STM32F0_UART6_BASE+STM32F0_USART_CR2_OFFSET)
# define STM32F0_UART6_CR3 (STM32F0_UART6_BASE+STM32F0_USART_CR3_OFFSET)
# define STM32F0_UART6_BRR (STM32F0_UART6_BASE+STM32F0_USART_BRR_OFFSET)
# define STM32F0_UART6_GTPR (STM32F0_UART6_BASE+STM32F0_USART_GTPR_OFFSET)
# define STM32F0_UART6_RTOR (STM32F0_UART6_BASE+STM32F0_USART_RTOR_OFFSET)
# define STM32F0_UART6_RQR (STM32F0_UART6_BASE+STM32F0_USART_RQR_OFFSET)
# define STM32F0_UART6_ISR (STM32F0_UART6_BASE+STM32F0_USART_ISR_OFFSET)
# define STM32F0_UART6_ICR (STM32F0_UART6_BASE+STM32F0_USART_ICR_OFFSET)
# define STM32F0_UART6_RDR (STM32F0_UART6_BASE+STM32F0_USART_RDR_OFFSET)
# define STM32F0_UART6_TDR (STM32F0_UART6_BASE+STM32F0_USART_TDR_OFFSET)
#endif
#if STM32F0_NUSART > 6
# define STM32F0_UART7_CR1 (STM32F0_UART7_BASE+STM32F0_USART_CR1_OFFSET)
# define STM32F0_UART7_CR2 (STM32F0_UART7_BASE+STM32F0_USART_CR2_OFFSET)
# define STM32F0_UART7_CR3 (STM32F0_UART7_BASE+STM32F0_USART_CR3_OFFSET)
# define STM32F0_UART7_BRR (STM32F0_UART7_BASE+STM32F0_USART_BRR_OFFSET)
# define STM32F0_UART7_GTPR (STM32F0_UART7_BASE+STM32F0_USART_GTPR_OFFSET)
# define STM32F0_UART7_RTOR (STM32F0_UART7_BASE+STM32F0_USART_RTOR_OFFSET)
# define STM32F0_UART7_RQR (STM32F0_UART7_BASE+STM32F0_USART_RQR_OFFSET)
# define STM32F0_UART7_ISR (STM32F0_UART7_BASE+STM32F0_USART_ISR_OFFSET)
# define STM32F0_UART7_ICR (STM32F0_UART7_BASE+STM32F0_USART_ICR_OFFSET)
# define STM32F0_UART7_RDR (STM32F0_UART7_BASE+STM32F0_USART_RDR_OFFSET)
# define STM32F0_UART7_TDR (STM32F0_UART7_BASE+STM32F0_USART_TDR_OFFSET)
#endif
#if STM32F0_NUSART > 7
# define STM32F0_UART8_CR1 (STM32F0_UART8_BASE+STM32F0_USART_CR1_OFFSET)
# define STM32F0_UART8_CR2 (STM32F0_UART8_BASE+STM32F0_USART_CR2_OFFSET)
# define STM32F0_UART8_CR3 (STM32F0_UART8_BASE+STM32F0_USART_CR3_OFFSET)
# define STM32F0_UART8_BRR (STM32F0_UART8_BASE+STM32F0_USART_BRR_OFFSET)
# define STM32F0_UART8_GTPR (STM32F0_UART8_BASE+STM32F0_USART_GTPR_OFFSET)
# define STM32F0_UART8_RTOR (STM32F0_UART8_BASE+STM32F0_USART_RTOR_OFFSET)
# define STM32F0_UART8_RQR (STM32F0_UART8_BASE+STM32F0_USART_RQR_OFFSET)
# define STM32F0_UART8_ISR (STM32F0_UART8_BASE+STM32F0_USART_ISR_OFFSET)
# define STM32F0_UART8_ICR (STM32F0_UART8_BASE+STM32F0_USART_ICR_OFFSET)
# define STM32F0_UART8_RDR (STM32F0_UART8_BASE+STM32F0_USART_RDR_OFFSET)
# define STM32F0_UART8_TDR (STM32F0_UART8_BASE+STM32F0_USART_TDR_OFFSET)
# define STM32F0_USART5_CR1 (STM32F0_USART5_BASE+STM32F0_USART_CR1_OFFSET)
# define STM32F0_USART5_CR2 (STM32F0_USART5_BASE+STM32F0_USART_CR2_OFFSET)
# define STM32F0_USART5_CR3 (STM32F0_USART5_BASE+STM32F0_USART_CR3_OFFSET)
# define STM32F0_USART5_BRR (STM32F0_USART5_BASE+STM32F0_USART_BRR_OFFSET)
# define STM32F0_USART5_GTPR (STM32F0_USART5_BASE+STM32F0_USART_GTPR_OFFSET)
# define STM32F0_USART5_RTOR (STM32F0_USART5_BASE+STM32F0_USART_RTOR_OFFSET)
# define STM32F0_USART5_RQR (STM32F0_USART5_BASE+STM32F0_USART_RQR_OFFSET)
# define STM32F0_USART5_ISR (STM32F0_USART5_BASE+STM32F0_USART_ISR_OFFSET)
# define STM32F0_USART5_ICR (STM32F0_USART5_BASE+STM32F0_USART_ICR_OFFSET)
# define STM32F0_USART5_RDR (STM32F0_USART5_BASE+STM32F0_USART_RDR_OFFSET)
# define STM32F0_USART5_TDR (STM32F0_USART5_BASE+STM32F0_USART_TDR_OFFSET)
#endif
/* Register Bitfield Definitions ****************************************************/
arch/arm/src/stm32f0/stm32f0_clockconfig.c
+20 -11
View File
@@ -69,32 +69,33 @@
void stm32f0_clockconfig(void)
{
int regval;
uint32_t regval;
/* Verify if PLL is already setup, if so define to use HSI mode */
/* Verify if PLL is already setup. If so configure to use HSI mode */
if ((getreg32(STM32F0_RCC_CFGR) & RCC_CFGR_SWS_MASK) == RCC_CFGR_SWS_PLL)
{
/* Select HSI mode */
regval = getreg32(STM32F0_RCC_CFGR);
regval &= (uint32_t) (~RCC_CFGR_SW_MASK);
regval &= ~RCC_CFGR_SW_MASK;
putreg32(regval, STM32F0_RCC_CFGR);
while ((getreg32(STM32F0_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_HSI) ;
while ((getreg32(STM32F0_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_HSI);
}
/* Disable the PLL */
regval = getreg32(STM32F0_RCC_CR);
regval &= (uint32_t)(~RCC_CR_PLLON);
regval &= ~RCC_CR_PLLON;
putreg32(regval, STM32F0_RCC_CR);
while ((getreg32(STM32F0_RCC_CR) & RCC_CR_PLLRDY) != 0) ;
while ((getreg32(STM32F0_RCC_CR) & RCC_CR_PLLRDY) != 0);
/* Configure the PLL. Multiple x6 to get 48MHz */
/* Configure the PLL. Multiply the HSI to get System Clock */
regval = getreg32(STM32F0_RCC_CFGR);
regval &= (RCC_CFGR_PLLMUL_CLKx6 | ~RCC_CFGR_PLLMUL_MASK);
regval &= ~RCC_CFGR_PLLMUL_MASK;
regval |= STM32F0_CFGR_PLLMUL;
putreg32(regval, STM32F0_RCC_CFGR);
/* Enable the PLL */
@@ -102,12 +103,20 @@ void stm32f0_clockconfig(void)
regval = getreg32(STM32F0_RCC_CR);
regval |= RCC_CR_PLLON;
putreg32(regval, STM32F0_RCC_CR);
while ((getreg32(STM32F0_RCC_CR) & RCC_CR_PLLRDY) == 0) ;
while ((getreg32(STM32F0_RCC_CR) & RCC_CR_PLLRDY) == 0);
/* Configure to use the PLL */
regval = getreg32(STM32F0_RCC_CFGR);
regval |= (uint32_t) (RCC_CFGR_SW_PLL);
regval |= RCC_CFGR_SW_PLL;
putreg32(regval, STM32F0_RCC_CFGR);
while ((getreg32(STM32F0_RCC_CFGR) & RCC_CFGR_SW_MASK) != RCC_CFGR_SW_PLL) ;
while ((getreg32(STM32F0_RCC_CFGR) & RCC_CFGR_SW_MASK) != RCC_CFGR_SW_PLL);
/* Enable basic peripheral support */
/* Enable all GPIO modules */
regval = getreg32(STM32F0_RCC_AHBENR);
regval |= RCC_AHBENR_IOPAEN | RCC_AHBENR_IOPAEN | RCC_AHBENR_IOPAEN |\
RCC_AHBENR_IOPAEN | RCC_AHBENR_IOPAEN | RCC_AHBENR_IOPAEN;
putreg32(regval, STM32F0_RCC_AHBENR);
}
arch/arm/src/stm32f0/stm32f0_gpio.h
+5 -20
View File
@@ -54,12 +54,7 @@
#include <arch/stm32f0/chip.h>
#include "chip.h"
#if defined(CONFIG_STM32F0_STM32F05X)
# include "chip/stm32f05xr_pinmap.h"
#else
# error "Unsupported STM32F0 chip"
#endif
#include "chip/stm32f0_pinmap.h"
/************************************************************************************
* Pre-Processor Declarations
@@ -84,7 +79,7 @@
* ---- ---- ---- ---- ----
* Inputs: MMUU .... ...X PPPP BBBB
* Outputs: MMUU .... FFOV PPPP BBBB
* Alternate Functions: MMUU AAAA FFO. PPPP BBBB
* Alternate Functions: MMUU .AAA FFO. PPPP BBBB
* Analog: MM.. .... .... PPPP BBBB
*/
@@ -122,11 +117,11 @@
* 1111 1111 1100 0000 0000
* 9876 5432 1098 7654 3210
* ---- ---- ---- ---- ----
* .... AAAA .... .... ....
* .... .AAA .... .... ....
*/
#define GPIO_AF_SHIFT (12) /* Bits 12-15: Alternate function */
#define GPIO_AF_MASK (15 << GPIO_AF_SHIFT)
#define GPIO_AF_SHIFT (12) /* Bits 12-14: Alternate function */
#define GPIO_AF_MASK (7 << GPIO_AF_SHIFT)
# define GPIO_AF(n) ((n) << GPIO_AF_SHIFT)
# define GPIO_AF0 (0 << GPIO_AF_SHIFT)
# define GPIO_AF1 (1 << GPIO_AF_SHIFT)
@@ -136,14 +131,6 @@
# define GPIO_AF5 (5 << GPIO_AF_SHIFT)
# define GPIO_AF6 (6 << GPIO_AF_SHIFT)
# define GPIO_AF7 (7 << GPIO_AF_SHIFT)
# define GPIO_AF8 (8 << GPIO_AF_SHIFT)
# define GPIO_AF9 (9 << GPIO_AF_SHIFT)
# define GPIO_AF10 (10 << GPIO_AF_SHIFT)
# define GPIO_AF11 (11 << GPIO_AF_SHIFT)
# define GPIO_AF12 (12 << GPIO_AF_SHIFT)
# define GPIO_AF13 (13 << GPIO_AF_SHIFT)
# define GPIO_AF14 (14 << GPIO_AF_SHIFT)
# define GPIO_AF15 (15 << GPIO_AF_SHIFT)
/* Output/Alt function frequency selection:
*
@@ -209,8 +196,6 @@
# define GPIO_PORTD (3 << GPIO_PORT_SHIFT) /* GPIOD */
# define GPIO_PORTE (4 << GPIO_PORT_SHIFT) /* GPIOE */
# define GPIO_PORTF (5 << GPIO_PORT_SHIFT) /* GPIOF */
# define GPIO_PORTG (6 << GPIO_PORT_SHIFT) /* GPIOG */
# define GPIO_PORTH (7 << GPIO_PORT_SHIFT) /* GPIOH */
/* This identifies the bit in the port:
*
arch/arm/src/stm32f0/stm32f0_lowputc.c
+93 -54
View File
@@ -63,14 +63,10 @@
# if defined(CONFIG_USART1_SERIAL_CONSOLE)
# define STM32F0_CONSOLE_BASE STM32F0_USART1_BASE
# define STM32F0_APBCLOCK STM32F0_PCLK2_FREQUENCY
# define STM32F0_CONSOLE_APBREG STM32F0_RCC_APB2ENR
# define STM32F0_CONSOLE_APBEN RCC_APB2ENR_USART1EN
# define STM32F0_CONSOLE_BAUD CONFIG_USART1_BAUD
# define STM32F0_CONSOLE_BITS CONFIG_USART1_BITS
# define STM32F0_CONSOLE_PARITY CONFIG_USART1_PARITY
# define STM32F0_CONSOLE_2STOP CONFIG_USART1_2STOP
# define STM32F0_CONSOLE_TX GPIO_USART1_TX
# define STM32F0_CONSOLE_RX GPIO_USART1_RX
# ifdef CONFIG_USART1_RS485
# define STM32F0_CONSOLE_RS485_DIR GPIO_USART1_RS485_DIR
# if (CONFIG_USART1_RS485_DIR_POLARITY == 0)
@@ -82,14 +78,10 @@
# elif defined(CONFIG_USART2_SERIAL_CONSOLE)
# define STM32F0_CONSOLE_BASE STM32F0_USART2_BASE
# define STM32F0_APBCLOCK STM32F0_PCLK1_FREQUENCY
# define STM32F0_CONSOLE_APBREG STM32F0_RCC_APB1ENR1
# define STM32F0_CONSOLE_APBEN RCC_APB1ENR1_USART2EN
# define STM32F0_CONSOLE_BAUD CONFIG_USART2_BAUD
# define STM32F0_CONSOLE_BITS CONFIG_USART2_BITS
# define STM32F0_CONSOLE_PARITY CONFIG_USART2_PARITY
# define STM32F0_CONSOLE_2STOP CONFIG_USART2_2STOP
# define STM32F0_CONSOLE_TX GPIO_USART2_TX
# define STM32F0_CONSOLE_RX GPIO_USART2_RX
# ifdef CONFIG_USART2_RS485
# define STM32F0_CONSOLE_RS485_DIR GPIO_USART2_RS485_DIR
# if (CONFIG_USART2_RS485_DIR_POLARITY == 0)
@@ -101,14 +93,10 @@
# elif defined(CONFIG_USART3_SERIAL_CONSOLE)
# define STM32F0_CONSOLE_BASE STM32F0_USART3_BASE
# define STM32F0_APBCLOCK STM32F0_PCLK1_FREQUENCY
# define STM32F0_CONSOLE_APBREG STM32F0_RCC_APB1ENR1
# define STM32F0_CONSOLE_APBEN RCC_APB1ENR1_USART3EN
# define STM32F0_CONSOLE_BAUD CONFIG_USART3_BAUD
# define STM32F0_CONSOLE_BITS CONFIG_USART3_BITS
# define STM32F0_CONSOLE_PARITY CONFIG_USART3_PARITY
# define STM32F0_CONSOLE_2STOP CONFIG_USART3_2STOP
# define STM32F0_CONSOLE_TX GPIO_USART3_TX
# define STM32F0_CONSOLE_RX GPIO_USART3_RX
# ifdef CONFIG_USART3_RS485
# define STM32F0_CONSOLE_RS485_DIR GPIO_USART3_RS485_DIR
# if (CONFIG_USART3_RS485_DIR_POLARITY == 0)
@@ -117,39 +105,31 @@
# define STM32F0_CONSOLE_RS485_DIR_POLARITY true
# endif
# endif
# elif defined(CONFIG_UART4_SERIAL_CONSOLE)
# define STM32F0_CONSOLE_BASE STM32F0_UART4_BASE
# elif defined(CONFIG_USART4_SERIAL_CONSOLE)
# define STM32F0_CONSOLE_BASE STM32F0_USART4_BASE
# define STM32F0_APBCLOCK STM32F0_PCLK1_FREQUENCY
# define STM32F0_CONSOLE_APBREG STM32F0_RCC_APB1ENR1
# define STM32F0_CONSOLE_APBEN RCC_APB1ENR1_UART4EN
# define STM32F0_CONSOLE_BAUD CONFIG_UART4_BAUD
# define STM32F0_CONSOLE_BITS CONFIG_UART4_BITS
# define STM32F0_CONSOLE_PARITY CONFIG_UART4_PARITY
# define STM32F0_CONSOLE_2STOP CONFIG_UART4_2STOP
# define STM32F0_CONSOLE_TX GPIO_UART4_TX
# define STM32F0_CONSOLE_RX GPIO_UART4_RX
# ifdef CONFIG_UART4_RS485
# define STM32F0_CONSOLE_RS485_DIR GPIO_UART4_RS485_DIR
# if (CONFIG_UART4_RS485_DIR_POLARITY == 0)
# define STM32F0_CONSOLE_BAUD CONFIG_USART4_BAUD
# define STM32F0_CONSOLE_BITS CONFIG_USART4_BITS
# define STM32F0_CONSOLE_PARITY CONFIG_USART4_PARITY
# define STM32F0_CONSOLE_2STOP CONFIG_USART4_2STOP
# ifdef CONFIG_USART4_RS485
# define STM32F0_CONSOLE_RS485_DIR GPIO_USART4_RS485_DIR
# if (CONFIG_USART4_RS485_DIR_POLARITY == 0)
# define STM32F0_CONSOLE_RS485_DIR_POLARITY false
# else
# define STM32F0_CONSOLE_RS485_DIR_POLARITY true
# endif
# endif
# elif defined(CONFIG_UART5_SERIAL_CONSOLE)
# define STM32F0_CONSOLE_BASE STM32F0_UART5_BASE
# elif defined(CONFIG_USART5_SERIAL_CONSOLE)
# define STM32F0_CONSOLE_BASE STM32F0_USART5_BASE
# define STM32F0_APBCLOCK STM32F0_PCLK1_FREQUENCY
# define STM32F0_CONSOLE_APBREG STM32F0_RCC_APB1ENR1
# define STM32F0_CONSOLE_APBEN RCC_APB1ENR1_UART5EN
# define STM32F0_CONSOLE_BAUD CONFIG_UART5_BAUD
# define STM32F0_CONSOLE_BITS CONFIG_UART5_BITS
# define STM32F0_CONSOLE_PARITY CONFIG_UART5_PARITY
# define STM32F0_CONSOLE_2STOP CONFIG_UART5_2STOP
# define STM32F0_CONSOLE_TX GPIO_UART5_TX
# define STM32F0_CONSOLE_RX GPIO_UART5_RX
# ifdef CONFIG_UART5_RS485
# define STM32F0_CONSOLE_RS485_DIR GPIO_UART5_RS485_DIR
# if (CONFIG_UART5_RS485_DIR_POLARITY == 0)
# define STM32F0_CONSOLE_BAUD CONFIG_USART5_BAUD
# define STM32F0_CONSOLE_BITS CONFIG_USART5_BITS
# define STM32F0_CONSOLE_PARITY CONFIG_USART5_PARITY
# define STM32F0_CONSOLE_2STOP CONFIG_USART5_2STOP
# ifdef CONFIG_USART5_RS485
# define STM32F0_CONSOLE_RS485_DIR GPIO_USART5_RS485_DIR
# if (CONFIG_USART5_RS485_DIR_POLARITY == 0)
# define STM32F0_CONSOLE_RS485_DIR_POLARITY false
# else
# define STM32F0_CONSOLE_RS485_DIR_POLARITY true
@@ -293,32 +273,91 @@ void up_lowputc(char ch)
void stm32f0_lowsetup(void)
{
#if defined(HAVE_UART)
#if defined(HAVE_USART)
#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG)
uint32_t cr;
#endif
#if defined(HAVE_CONSOLE)
/* Enable USART APB1/2 clock */
/* Setup clocking and GPIO pins for all configured USARTs */
modifyreg32(STM32F0_CONSOLE_APBREG, 0, STM32F0_CONSOLE_APBEN);
#ifdef CONFIG_STM32F0_USART1
/* Enable USART APB2 clock */
modifyreg32(STM32F0_RCC_APB2ENR, 0, RCC_APB2ENR_USART1EN);
/* Configure RX/TX pins */
stm32f0_configgpio(GPIO_USART1_TX);
stm32f0_configgpio(GPIO_USART1_RX);
#ifdef CONFIG_USART1_RS485
stm32f0_configgpio(GPIO_USART1_RS485_DIR);
stm32f0_gpiowrite(GPIO_USART1_RS485_DIR, !CONFIG_USART1_RS485_DIR_POLARITY);
#endif
#endif
/* Enable the console USART and configure GPIO pins needed for rx/tx.
*
* NOTE: Clocking for selected U[S]ARTs was already provided in stm32f0_rcc.c
*/
#ifdef CONFIG_STM32F0_USART2
/* Enable USART APB1 clock */
#ifdef STM32F0_CONSOLE_TX
stm32f0_configgpio(STM32F0_CONSOLE_TX);
modifyreg32(STM32F0_RCC_APB1ENR, 0, RCC_APB1ENR_USART2EN);
/* Configure RX/TX pins */
stm32f0_configgpio(GPIO_USART2_TX);
stm32f0_configgpio(GPIO_USART2_RX);
#ifdef CONFIG_USART2_RS485
stm32f0_configgpio(GPIO_USART2_RS485_DIR);
stm32f0_gpiowrite(GPIO_USART2_RS485_DIR, !CONFIG_USART2_RS485_DIR_POLARITY);
#endif
#ifdef STM32F0_CONSOLE_RX
stm32f0_configgpio(STM32F0_CONSOLE_RX);
#endif
#ifdef STM32F0_CONSOLE_RS485_DIR
stm32f0_configgpio(STM32F0_CONSOLE_RS485_DIR);
stm32f0_gpiowrite(STM32F0_CONSOLE_RS485_DIR, !STM32F0_CONSOLE_RS485_DIR_POLARITY);
#ifdef CONFIG_STM32F0_USART3
/* Enable USART APB1 clock */
modifyreg32(STM32F0_RCC_APB1ENR, 0, RCC_APB1ENR_USART3EN);
/* Configure RX/TX pins */
stm32f0_configgpio(GPIO_USART3_TX);
stm32f0_configgpio(GPIO_USART3_RX);
#ifdef CONFIG_USART3_RS485
stm32f0_configgpio(GPIO_USART3_RS485_DIR);
stm32f0_gpiowrite(GPIO_USART3_RS485_DIR, !CONFIG_USART3_RS485_DIR_POLARITY);
#endif
#endif
#ifdef CONFIG_STM32F0_USART4
/* Enable USART APB1 clock */
modifyreg32(STM32F0_RCC_APB1ENR, 0, RCC_APB1ENR_USART4EN);
/* Configure RX/TX pins */
stm32f0_configgpio(GPIO_USART4_TX);
stm32f0_configgpio(GPIO_USART4_RX);
#ifdef CONFIG_USART4_RS485
stm32f0_configgpio(GPIO_USART4_RS485_DIR);
stm32f0_gpiowrite(GPIO_USART4_RS485_DIR, !CONFIG_USART4_RS485_DIR_POLARITY);
#endif
#endif
#ifdef CONFIG_STM32F0_USART5
/* Enable USART APB1 clock */
modifyreg32(STM32F0_RCC_APB1ENR, 0, RCC_APB1ENR_USART5EN);
/* Configure RX/TX pins */
stm32f0_configgpio(GPIO_USART5_TX);
stm32f0_configgpio(GPIO_USART5_RX);
#ifdef CONFIG_USART5_RS485
stm32f0_configgpio(GPIO_USART5_RS485_DIR);
stm32f0_gpiowrite(GPIO_USART5_RS485_DIR, !CONFIG_USART5_RS485_DIR_POLARITY);
#endif
#endif
/* Enable and configure the selected console device */
@@ -363,5 +402,5 @@ void stm32f0_lowsetup(void)
putreg32(cr, STM32F0_CONSOLE_BASE + STM32F0_USART_CR1_OFFSET);
#endif /* HAVE_CONSOLE && !CONFIG_SUPPRESS_UART_CONFIG */
#endif /* HAVE_UART */
#endif /* HAVE_USART */
}
arch/arm/src/stm32f0/stm32f0_serial.c
+51 -51
View File
@@ -84,7 +84,7 @@
/* If DMA is enabled on any USART, then very that other pre-requisites
* have also been selected.
* UART DMA1 DMA2
* USART DMA1 DMA2
* 1 X X
* 2 X
* 3 X
@@ -105,7 +105,7 @@
# if defined(CONFIG_USART4_RXDMA) || defined(CONFIG_USART5_RXDMA)
# ifndef CONFIG_STM32F0_DMA2
# error STM32F0 UART4/5 receive DMA requires CONFIG_STM32F0_DMA2
# error STM32F0 USART4/5 receive DMA requires CONFIG_STM32F0_DMA2
# endif
# endif
@@ -130,7 +130,7 @@
# error "USART1 DMA channel not defined (DMAMAP_USART1_RX)"
# endif
/* UART2-5 have no alternate channels */
/* USART2-5 have no alternate channels */
# define DMAMAP_USART2_RX DMACHAN_USART2_RX
# define DMAMAP_USART3_RX DMACHAN_USART3_RX
@@ -196,7 +196,7 @@
#endif
#ifdef USE_SERIALDRIVER
#ifdef HAVE_UART
#ifdef HAVE_USART
/****************************************************************************
* Private Types
@@ -204,7 +204,7 @@
struct stm32f0_serial_s
{
struct uart_dev_s dev; /* Generic UART device */
struct uart_dev_s dev; /* Generic USART device */
uint16_t ie; /* Saved interrupt mask bits value */
uint16_t sr; /* Saved status bits */
@@ -387,18 +387,18 @@ static char g_usart3rxfifo[RXDMA_BUFFER_SIZE];
#endif
#ifdef CONFIG_STM32F0_USART4
static char g_uart4rxbuffer[CONFIG_USART4_RXBUFSIZE];
static char g_uart4txbuffer[CONFIG_USART4_TXBUFSIZE];
static char g_usart4rxbuffer[CONFIG_USART4_RXBUFSIZE];
static char g_usart4txbuffer[CONFIG_USART4_TXBUFSIZE];
# ifdef CONFIG_USART4_RXDMA
static char g_uart4rxfifo[RXDMA_BUFFER_SIZE];
static char g_usart4rxfifo[RXDMA_BUFFER_SIZE];
# endif
#endif
#ifdef CONFIG_STM32F0_USART5
static char g_uart5rxbuffer[CONFIG_USART5_RXBUFSIZE];
static char g_uart5txbuffer[CONFIG_USART5_TXBUFSIZE];
static char g_usart5rxbuffer[CONFIG_USART5_RXBUFSIZE];
static char g_usart5txbuffer[CONFIG_USART5_TXBUFSIZE];
# ifdef CONFIG_USART5_RXDMA
static char g_uart5rxfifo[RXDMA_BUFFER_SIZE];
static char g_usart5rxfifo[RXDMA_BUFFER_SIZE];
# endif
#endif
@@ -585,10 +585,10 @@ static struct stm32f0_serial_s g_usart3priv =
};
#endif
/* This describes the state of the STM32 UART4 port. */
/* This describes the state of the STM32 USART4 port. */
#ifdef CONFIG_STM32F0_USART4
static struct stm32f0_serial_s g_uart4priv =
static struct stm32f0_serial_s g_usart4priv =
{
.dev =
{
@@ -598,19 +598,19 @@ static struct stm32f0_serial_s g_uart4priv =
.recv =
{
.size = CONFIG_USART4_RXBUFSIZE,
.buffer = g_uart4rxbuffer,
.buffer = g_usart4rxbuffer,
},
.xmit =
{
.size = CONFIG_USART4_TXBUFSIZE,
.buffer = g_uart4txbuffer,
.buffer = g_usart4txbuffer,
},
#ifdef CONFIG_USART4_RXDMA
.ops = &g_uart_dma_ops,
#else
.ops = &g_uart_ops,
#endif
.priv = &g_uart4priv,
.priv = &g_usart4priv,
},
.irq = STM32F0_IRQ_USART4,
@@ -636,7 +636,7 @@ static struct stm32f0_serial_s g_uart4priv =
#endif
#ifdef CONFIG_USART4_RXDMA
.rxdma_channel = DMAMAP_USART4_RX,
.rxfifo = g_uart4rxfifo,
.rxfifo = g_usart4rxfifo,
#endif
#ifdef CONFIG_USART4_RS485
@@ -650,10 +650,10 @@ static struct stm32f0_serial_s g_uart4priv =
};
#endif
/* This describes the state of the STM32 UART5 port. */
/* This describes the state of the STM32 USART5 port. */
#ifdef CONFIG_STM32F0_USART5
static struct stm32f0_serial_s g_uart5priv =
static struct stm32f0_serial_s g_usart5priv =
{
.dev =
{
@@ -663,19 +663,19 @@ static struct stm32f0_serial_s g_uart5priv =
.recv =
{
.size = CONFIG_USART5_RXBUFSIZE,
.buffer = g_uart5rxbuffer,
.buffer = g_usart5rxbuffer,
},
.xmit =
{
.size = CONFIG_USART5_TXBUFSIZE,
.buffer = g_uart5txbuffer,
.buffer = g_usart5txbuffer,
},
#ifdef CONFIG_USART5_RXDMA
.ops = &g_uart_dma_ops,
#else
.ops = &g_uart_ops,
#endif
.priv = &g_uart5priv,
.priv = &g_usart5priv,
},
.irq = STM32F0_IRQ_USART5,
@@ -701,7 +701,7 @@ static struct stm32f0_serial_s g_uart5priv =
#endif
#ifdef CONFIG_USART5_RXDMA
.rxdma_channel = DMAMAP_USART5_RX,
.rxfifo = g_uart5rxfifo,
.rxfifo = g_usart5rxfifo,
#endif
#ifdef CONFIG_USART5_RS485
@@ -729,10 +729,10 @@ FAR static struct stm32f0_serial_s * const uart_devs[STM32F0_NUSART] =
[2] = &g_usart3priv,
#endif
#ifdef CONFIG_STM32F0_USART4
[3] = &g_uart4priv,
[3] = &g_usart4priv,
#endif
#ifdef CONFIG_STM32F0_USART5
[4] = &g_uart5priv,
[4] = &g_usart5priv,
#endif
};
@@ -1010,7 +1010,7 @@ static void stm32f0serial_setformat(FAR struct uart_dev_s *dev)
* Enable or disable APB clock for the USART peripheral
*
* Input parameters:
* dev - A reference to the UART driver state structure
* dev - A reference to the USART driver state structure
* on - Enable clock if 'on' is 'true' and disable if 'false'
*
****************************************************************************/
@@ -1035,26 +1035,26 @@ static void stm32f0serial_setapbclock(FAR struct uart_dev_s *dev, bool on)
#endif
#ifdef CONFIG_STM32F0_USART2
case STM32F0_USART2_BASE:
rcc_en = RCC_APB1ENR1_USART2EN;
regaddr = STM32F0_RCC_APB1ENR1;
rcc_en = RCC_APB1ENR_USART2EN;
regaddr =STM32F0_RCC_APB1ENR;
break;
#endif
#ifdef CONFIG_STM32F0_USART3
case STM32F0_USART3_BASE:
rcc_en = RCC_APB1ENR1_USART3EN;
regaddr = STM32F0_RCC_APB1ENR1;
rcc_en = RCC_APB1ENR_USART3EN;
regaddr =STM32F0_RCC_APB1ENR;
break;
#endif
#ifdef CONFIG_STM32F0_USART4
case STM32F0_USART4_BASE:
rcc_en = RCC_APB1ENR1_USART4EN;
regaddr = STM32F0_RCC_APB1ENR1;
rcc_en = RCC_APB1ENR_USART4EN;
regaddr =STM32F0_RCC_APB1ENR;
break;
#endif
#ifdef CONFIG_STM32F0_USART5
case STM32F0_USART5_BASE:
rcc_en = RCC_APB1ENR1_USART5EN;
regaddr = STM32F0_RCC_APB1ENR1;
rcc_en = RCC_APB1ENR_USART5EN;
regaddr =STM32F0_RCC_APB1ENR;
break;
#endif
}
@@ -1196,7 +1196,7 @@ static int stm32f0serial_dmasetup(FAR struct uart_dev_s *dev)
int result;
uint32_t regval;
/* Do the basic UART setup first, unless we are the console */
/* Do the basic USART setup first, unless we are the console */
if (!dev->isconsole)
{
@@ -1240,7 +1240,7 @@ static int stm32f0serial_dmasetup(FAR struct uart_dev_s *dev)
priv->rxdmanext = 0;
/* Enable receive DMA for the UART */
/* Enable receive DMA for the USART */
regval = stm32f0serial_getreg(priv, STM32F0_USART_CR3_OFFSET);
regval |= USART_CR3_DMAR;
@@ -1295,7 +1295,7 @@ static void stm32f0serial_shutdown(FAR struct uart_dev_s *dev)
stm32f0serial_setapbclock(dev, false);
/* Disable Rx, Tx, and the UART */
/* Disable Rx, Tx, and the USART */
regval = stm32f0serial_getreg(priv, STM32F0_USART_CR1_OFFSET);
regval &= ~(USART_CR1_UE | USART_CR1_TE | USART_CR1_RE);
@@ -1348,7 +1348,7 @@ static void stm32f0serial_dmashutdown(FAR struct uart_dev_s *dev)
{
FAR struct stm32f0_serial_s *priv = (FAR struct stm32f0_serial_s *)dev->priv;
/* Perform the normal UART shutdown */
/* Perform the normal USART shutdown */
stm32f0serial_shutdown(dev);
@@ -1880,11 +1880,11 @@ static bool stm32f0serial_rxavailable(FAR struct uart_dev_s *dev)
* Description:
* Called when Rx buffer is full (or exceeds configured watermark levels
* if CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS is defined).
* Return true if UART activated RX flow control to block more incoming
* Return true if USART activated RX flow control to block more incoming
* data
*
* Input parameters:
* dev - UART device instance
* dev - USART device instance
* nbuffered - the number of characters currently buffered
* (if CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS is
* not defined the value will be 0 for an empty buffer or the
@@ -1924,7 +1924,7 @@ static bool stm32f0serial_rxflowcontrol(FAR struct uart_dev_s *dev,
* peripheral. When hardware RTS is enabled, this will
* prevent more data from coming in.
*
* This function is only called when UART recv buffer is full,
* This function is only called when USART recv buffer is full,
* that is: "dev->recv.head + 1 == dev->recv.tail".
*
* Logic in "uart_read" will automatically toggle Rx interrupts
@@ -2327,7 +2327,7 @@ static int stm32f0serial_pmprepare(FAR struct pm_callback_s *cb, int domain,
return OK;
}
#endif
#endif /* HAVE_UART */
#endif /* HAVE_USART */
#endif /* USE_SERIALDRIVER */
/****************************************************************************
@@ -2349,7 +2349,7 @@ static int stm32f0serial_pmprepare(FAR struct pm_callback_s *cb, int domain,
#ifdef USE_EARLYSERIALINIT
void up_earlyserialinit(void)
{
#ifdef HAVE_UART
#ifdef HAVE_USART
unsigned i;
/* Disable all USART interrupts */
@@ -2367,7 +2367,7 @@ void up_earlyserialinit(void)
#if CONSOLE_USART > 0
stm32f0serial_setup(&uart_devs[CONSOLE_USART - 1]->dev);
#endif
#endif /* HAVE UART */
#endif /* HAVE USART */
}
#endif
@@ -2382,7 +2382,7 @@ void up_earlyserialinit(void)
void up_serialinit(void)
{
#ifdef HAVE_UART
#ifdef HAVE_USART
char devname[16];
unsigned i;
unsigned minor = 0;
@@ -2404,7 +2404,7 @@ void up_serialinit(void)
(void)uart_register("/dev/console", &uart_devs[CONSOLE_USART - 1]->dev);
#ifndef CONFIG_SERIAL_DISABLE_REORDERING
/* If not disabled, register the console UART to ttyS0 and exclude
/* If not disabled, register the console USART to ttyS0 and exclude
* it from initializing it further down
*/
@@ -2446,7 +2446,7 @@ void up_serialinit(void)
devname[9] = '0' + minor++;
(void)uart_register(devname, &uart_devs[i]->dev);
}
#endif /* HAVE UART */
#endif /* HAVE USART */
}
/****************************************************************************
@@ -2489,16 +2489,16 @@ void stm32f0serial_dmapoll(void)
#endif
#ifdef CONFIG_USART4_RXDMA
if (g_uart4priv.rxdma != NULL)
if (g_usart4priv.rxdma != NULL)
{
stm32f0serial_dmarxcallback(g_uart4priv.rxdma, 0, &g_uart4priv);
stm32f0serial_dmarxcallback(g_usart4priv.rxdma, 0, &g_usart4priv);
}
#endif
#ifdef CONFIG_USART5_RXDMA
if (g_uart5priv.rxdma != NULL)
if (g_usart5priv.rxdma != NULL)
{
stm32f0serial_dmarxcallback(g_uart5priv.rxdma, 0, &g_uart5priv);
stm32f0serial_dmarxcallback(g_usart5priv.rxdma, 0, &g_usart5priv);
}
#endif
arch/arm/src/stm32f0/stm32f0_serial.h
-33
View File
@@ -42,42 +42,9 @@
************************************************************************************/
#include <nuttx/config.h>
#include <arch/board/board.h>
#include "chip/stm32f0_uart.h"
#include "chip/stm32f0_syscfg.h"
#include "stm32f0_gpio.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Configuration *********************************************************************/
/* Are any UARTs enabled? */
#undef HAVE_UART
#if defined(CONFIG_STM32F0_UART0)
# define HAVE_UART 1
#endif
/* Is there a serial console? There should be at most one defined. It could be on
* any UARTn, n=0,1,2,3
*/
#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_STM32F0_UART0)
# define HAVE_SERIAL_CONSOLE 1
#else
# undef CONFIG_UART0_SERIAL_CONSOLE
# undef HAVE_SERIAL_CONSOLE
#endif
/* We cannot allow the DLM/DLL divisor to become to small or will will lose too
* much accuracy. This following is a "fudge factor" that represents the minimum
* value of the divisor that we will permit.
*/
#define UART_MINDL 32
#endif /* __ARCH_ARM_SRC_STM32F0_STM32F0_SERIAL_H */
arch/arm/src/stm32f0/stm32f0_start.c
+2 -5
View File
@@ -52,10 +52,7 @@
#include "stm32f0_clockconfig.h"
#include "stm32f0_lowputc.h"
#ifdef CONFIG_ARCH_FPU
# include "nvic.h"
#endif
#include "stm32f0_start.h"
/****************************************************************************
* Pre-processor Definitions
@@ -78,7 +75,7 @@ const uint32_t g_idle_topstack = IDLE_STACK;
* Name: showprogress
*
* Description:
* Print a character on the UART to show boot status.
* Print a character on the CONSOLE USART to show boot status.
*
****************************************************************************/
arch/arm/src/stm32f0/stm32f0_start.h
+76
View File
@@ -0,0 +1,76 @@
/************************************************************************************
* arch/arm/src/stm32f0/stm32f0_start.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0_STM32F0_START_H
#define __ARCH_ARM_SRC_STM32F0_STM32F0_START_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
/************************************************************************************
* Public Data
************************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
extern "C"
{
#endif
/************************************************************************************
* Public Functions
************************************************************************************/
/************************************************************************************
* Name: stm32f0_boardinitialize
*
* Description:
* All STM32 architectures must provide the following entry point. This entry
* point is called early in the intitialization -- after all memory has been
* configured and mapped but before any devices have been initialized.
*
************************************************************************************/
void stm32f0_boardinitialize(void);
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_STM32F0_STM32F0_START_H */
arch/arm/src/stm32f0/stm32f0_timerisr.c
+2 -2
View File
@@ -63,9 +63,9 @@
*/
#if defined(CONFIG_STM32F0_SYSTICK_CORECLK)
# define SYSTICK_CLOCK STM32F0_MCLK /* Core clock */
# define SYSTICK_CLOCK STM32F0_SYSCLK_FREQUENCY /* Core clock */
#elif defined(CONFIG_STM32F0_SYSTICK_CORECLK_DIV16)
# define SYSTICK_CLOCK (STM32F0_MCLK / 16) /* Core clock divided by 16 */
# define SYSTICK_CLOCK (STM32F0_SYSCLK_FREQUENCY / 16) /* Core clock divided by 16 */
#endif
/* The desired timer interrupt frequency is provided by the definition
arch/arm/src/stm32f0/stm32f0_uart.h
+7 -7
View File
@@ -54,22 +54,22 @@
* device.
*/
#if STM32F0_NUSART < 8 || !defined(CONFIG_STM32F0_HAVE_UART8)
#if STM32F0_NUSART < 8 || !defined(CONFIG_STM32F0_HAVE_USART8)
# undef CONFIG_STM32F0_USART8
#endif
#if STM32F0_NUSART < 7 || !defined(CONFIG_STM32F0_HAVE_UART7)
#if STM32F0_NUSART < 7 || !defined(CONFIG_STM32F0_HAVE_USART7)
# undef CONFIG_STM32F0_USART7
#endif
#if STM32F0_NUSART < 6 || !defined(CONFIG_STM32F0_HAVE_UART6)
#if STM32F0_NUSART < 6 || !defined(CONFIG_STM32F0_HAVE_USART6)
# undef CONFIG_STM32F0_USART6
#endif
#if STM32F0_NUSART < 5 || !defined(CONFIG_STM32F0_HAVE_UART5)
#if STM32F0_NUSART < 5 || !defined(CONFIG_STM32F0_HAVE_USART5)
# undef CONFIG_STM32F0_USART5
#endif
#if STM32F0_NUSART < 4 || !defined(CONFIG_STM32F0_HAVE_UART4)
#if STM32F0_NUSART < 4 || !defined(CONFIG_STM32F0_HAVE_USART4)
# undef CONFIG_STM32F0_USART4
#endif
#if STM32F0_NUSART < 3 || !defined(CONFIG_STM32F0_HAVE_UART3)
#if STM32F0_NUSART < 3 || !defined(CONFIG_STM32F0_HAVE_USART3)
# undef CONFIG_STM32F0_USART3
#endif
#if STM32F0_NUSART < 2
@@ -84,7 +84,7 @@
#if defined(CONFIG_STM32F0_USART1) || defined(CONFIG_STM32F0_USART2) || \
defined(CONFIG_STM32F0_USART3) || defined(CONFIG_STM32F0_USART4) || \
defined(CONFIG_STM32F0_USART5)
# define HAVE_UART 1
# define HAVE_USART 1
#endif
/* Sanity checks */
arch/arm/src/stm32f7/Kconfig
+7 -3
View File
@@ -1014,7 +1014,6 @@ config STM32F7_ADC1
bool "ADC1"
default n
select STM32F7_ADC
select STM32F7_HAVE_ADC1_DMA if STM32F7_DMA1
select STM32F7_HAVE_ADC1_DMA if STM32F7_DMA2
config STM32F7_ADC2
@@ -1027,8 +1026,7 @@ config STM32F7_ADC3
bool "ADC3"
default n
select STM32F7_ADC
select STM32F7_HAVE_ADC1_DMA if STM32F7_DMA1
select STM32F7_HAVE_ADC1_DMA if STM32F7_DMA2
select STM32F7_HAVE_ADC3_DMA if STM32F7_DMA2
config STM32F7_BKPSRAM
bool "Enable BKP RAM Domain"
@@ -4398,6 +4396,12 @@ endmenu # Timer Configuration
menu "ADC Configuration"
depends on STM32F7_ADC
config STM32F7_ADC_NO_STARTUP_CONV
bool "Do not start conversion when opening ADC device"
default n
---help---
Do not start conversion when opening ADC device.
config STM32F7_ADC1_DMA
bool "ADC1 DMA"
depends on STM32F7_ADC1 && STM32F7_HAVE_ADC1_DMA
arch/arm/src/stm32f7/chip/stm32_adc.h
-4
View File
@@ -41,10 +41,6 @@
* Included Files
****************************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include <nuttx/config.h>
#include "chip.h"
arch/arm/src/stm32f7/stm32_adc.c
+11 -5
View File
@@ -131,6 +131,12 @@
#define ADC_MAX_CHANNELS_DMA 16
#define ADC_MAX_CHANNELS_NODMA 1
#ifdef ADC_HAVE_DMA
# ifndef CONFIG_STM32F7_DMA2
# error "STM32F7 ADC DMA support requires CONFIG_STM32F7_DMA2"
# endif
#endif
#ifdef ADC_HAVE_DMA
# define ADC_MAX_SAMPLES ADC_MAX_CHANNELS_DMA
#else
@@ -1133,7 +1139,7 @@ static void adc_dmaconvcallback(DMA_HANDLE handle, uint8_t isr, FAR void *arg)
for (i = 0; i < priv->nchannels; i++)
{
priv->cb->au_receive(dev, priv->current, priv->dmabuffer[priv->current]);
priv->cb->au_receive(dev, priv->chanlist[priv->current], priv->dmabuffer[priv->current]);
priv->current++;
if (priv->current >= priv->nchannels)
{
@@ -1276,7 +1282,7 @@ static void adc_reset(FAR struct adc_dev_s *dev)
if (adc_internal(priv))
{
setbits = ADC_CCR_TSVREFE;
setbits |= ADC_CCR_TSVREFE;
}
clrbits |= ADC_CCR_MULTI_MASK | ADC_CCR_DELAY_MASK | ADC_CCR_DDS |
@@ -1325,11 +1331,11 @@ static void adc_reset(FAR struct adc_dev_s *dev)
aerr("ERROR: adc_timinit failed: %d\n", ret);
}
}
#ifndef CONFIG_ADC_NO_STARTUP_CONV
#ifndef CONFIG_STM32F7_ADC_NO_STARTUP_CONV
else
#endif
#endif
#ifndef CONFIG_ADC_NO_STARTUP_CONV
#ifndef CONFIG_STM32F7_ADC_NO_STARTUP_CONV
{
adc_startconv(priv, true);
}
@@ -1721,7 +1727,7 @@ static int adc123_interrupt(int irq, FAR void *context, FAR void *arg)
* cchannels - Number of channels
*
* Returned Value:
* Valid ADC device structure reference on succcess; a NULL on failure
* Valid ADC device structure reference on success; a NULL on failure
*
****************************************************************************/
arch/arm/src/stm32f7/stm32_adc.h
+1 -1
View File
@@ -750,7 +750,7 @@ extern "C"
* nchannels - Number of channels
*
* Returned Value:
* Valid can device structure reference on succcess; a NULL on failure
* Valid ADC device structure reference on success; a NULL on failure
*
****************************************************************************/
arch/arm/src/stm32f7/stm32_dma.c
+1 -1
View File
@@ -80,7 +80,7 @@
/* Convert the DMA stream base address to the DMA register block address */
#define DMA_BASE(ch) (ch & 0xfffffc00)
#define DMA_BASE(ch) ((ch) & 0xfffffc00)
/****************************************************************************
* Private Types
configs/Kconfig
+13
View File
@@ -724,6 +724,15 @@ config ARCH_BOARD_NUCLEO_144
NUCLEO-F767ZI - STM32F767ZIT6 a 216MHz Cortex-M7, w/DPFPU -
2048KiB Flash memory and 512KiB SRAM.
config ARCH_BOARD_NUCLEO_F072RB
bool "STM32F072 Nucleo F072RB"
depends on ARCH_CHIP_STM32F072RB
select ARCH_HAVE_LEDS
select ARCH_HAVE_BUTTONS
select ARCH_HAVE_IRQBUTTONS
---help---
STMicro Nucleo F072RB board based on the STMicro STM32F072RBT6 MCU.
config ARCH_BOARD_NUCLEO_F303RE
bool "STM32F303 Nucleo F303RE"
depends on ARCH_CHIP_STM32F303RE
@@ -1504,6 +1513,7 @@ config ARCH_BOARD
default "pic32mx7mmb" if ARCH_BOARD_PIC32MX7MMB
default "pic32mz-starterkit" if ARCH_BOARD_PIC32MZ_STARTERKIT
default "nucleo-144" if ARCH_BOARD_NUCLEO_144
default "nucleo-f072rb" if ARCH_BOARD_NUCLEO_F072RB
default "nucleo-f303re" if ARCH_BOARD_NUCLEO_F303RE
default "nucleo-f334r8" if ARCH_BOARD_NUCLEO_F334R8
default "nucleo-f4x1re" if ARCH_BOARD_NUCLEO_F401RE || ARCH_BOARD_NUCLEO_F411RE
@@ -1810,6 +1820,9 @@ endif
if ARCH_BOARD_NUCLEO_144
source "configs/nucleo-144/Kconfig"
endif
if ARCH_BOARD_NUCLEO_F072RB
source "configs/nucleo-f072rb/Kconfig"
endif
if ARCH_BOARD_NUCLEO_F303RE
source "configs/nucleo-f303re/Kconfig"
endif
configs/README.txt
+3
View File
@@ -411,6 +411,9 @@ configs/nucleo-144
STM32F767ZIT6 is a 216MHz Cortex-M7 operation with 2048Kb Flash memory
and 512Kb SRAM.
configs/nucleo-f072rb
STMicro Nucleo F072RB board based on the STMicro STM32F072RBT6 MCU.
configs/nucleo-f4x1re
STMicro ST Nucleo F401RE and F411RE boards. See
http://mbed.org/platforms/ST-Nucleo-F401RE and
configs/nucleo-f072rb/Kconfig
+8
View File
@@ -0,0 +1,8 @@
#
# For a description of the syntax of this configuration file,
# see the file kconfig-language.txt in the NuttX tools repository.
#
if ARCH_BOARD_NUCLEO_F072RB
endif
configs/nucleo-f072rb/README.txt
+284
View File
@@ -0,0 +1,284 @@
Nucleo-F072RB README
====================
This README file discusess the port of NuttX to the STMicro Nucleo-F4072RB
board. That board features the STM32F072RBT6 MCU with 128KiB with 128KiB
of FLASH and 16KiB of SRAM.
Contents
========
- Nucleo-64 Boards
- LEDs
- Buttons
- Serial Console
- Configurations
Nucleo-64 Boards
================
The Nucleo-F072RB is a member of the Nucleo-64 board family. The Nucleo-64
is a standard board for use with several STM32 parts in the LQFP64 package.
Variants including:
Order code Targeted STM32
------------- --------------
NUCLEO-F030R8 STM32F030R8T6
NUCLEO-F070RB STM32F070RBT6
NUCLEO-F072RB STM32F072RBT6
NUCLEO-F091RC STM32F091RCT6
NUCLEO-F103RB STM32F103RBT6
NUCLEO-F302R8 STM32F302R8T6
NUCLEO-F303RE STM32F303RET6
NUCLEO-F334R8 STM32F334R8T6
NUCLEO-F401RE STM32F401RET6
NUCLEO-F410RB STM32F410RBT6
NUCLEO-F411RE STM32F411RET6
NUCLEO-F446RE STM32F446RET6
NUCLEO-L053R8 STM32L053R8T6
NUCLEO-L073RZ STM32L073RZT6
NUCLEO-L152RE STM32L152RET6
NUCLEO-L452RE STM32L452RET6
NUCLEO-L476RG STM32L476RGT6
LEDs
====
The Nucleo-64 board has one user controlable LED, User LD2. This green
LED is a user LED connected to Arduino signal D13 corresponding to STM32
I/O PA5 (PB13 on other some other Nucleo-64 boards).
- When the I/O is HIGH value, the LED is on
- When the I/O is LOW, the LED is off
These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is
defined. In that case, the usage by the board port is defined in
include/board.h and src/sam_leds.c. The LEDs are used to encode OS-related
events as follows when the red LED (PE24) is available:
SYMBOL Meaning LD2
------------------- ----------------------- -----------
LED_STARTED NuttX has been started OFF
LED_HEAPALLOCATE Heap has been allocated OFF
LED_IRQSENABLED Interrupts enabled OFF
LED_STACKCREATED Idle stack created ON
LED_INIRQ In an interrupt No change
LED_SIGNAL In a signal handler No change
LED_ASSERTION An assertion failed No change
LED_PANIC The system has crashed Blinking
LED_IDLE MCU is is sleep mode Not used
Thus if LD2, NuttX has successfully booted and is, apparently, running
normally. If LD2 is flashing at approximately 2Hz, then a fatal error
has been detected and the system has halted.
Buttons
=======
B1 USER: the user button is connected to the I/O PC13 (pin 2) of the STM32
microcontroller.
Serial Console
==============
USART1
------
Pins and Connectors:
RXD: PA10 D3 CN9 pin 3, CN10 pin 33
PB7 CN7 pin 21
TXD: PA9 D8 CN5 pin 1, CN10 pin 21
PB6 D10 CN5 pin 3, CN10 pin 17
NOTE: You may need to edit the include/board.h to select different USART1
pin selections.
TTL to RS-232 converter connection:
Nucleo CN10 STM32F072RB
----------- ------------
Pin 21 PA9 USART1_TX *Warning you make need to reverse RX/TX on
Pin 33 PA10 USART1_RX some RS-232 converters
Pin 20 GND
Pin 8 U5V
To configure USART1 as the console:
CONFIG_STM32_USART1=y
CONFIG_USART1_SERIALDRIVER=y
CONFIG_USART1_SERIAL_CONSOLE=y
CONFIG_USART1_RXBUFSIZE=256
CONFIG_USART1_TXBUFSIZE=256
CONFIG_USART1_BAUD=115200
CONFIG_USART1_BITS=8
CONFIG_USART1_PARITY=0
CONFIG_USART1_2STOP=0
USART2
------
Pins and Connectors:
RXD: PA3 To be provided
PA15
PD6
TXD: PA2
PA14
PD5
USART3
------
Pins and Connectors:
RXD: PB11 To be provided
PC5
PC11
D9
TXD: PB10
PC4
PC10
D8
See "Virtual COM Port" and "RS-232 Shield" below.
USART3
------
Pins and Connectors:
RXD: PA1 To be provided
PC11
TXD: PA0
PC10
Virtual COM Port
----------------
Yet another option is to use UART2 and the USB virtual COM port. This
option may be more convenient for long term development, but is painful
to use during board bring-up.
Solder Bridges. This configuration requires:
- SB62 and SB63 Open: PA2 and PA3 on STM32 MCU are disconnected to D1
and D0 (pin 7 and pin 8) on Arduino connector CN9 and ST Morpho
connector CN10.
- SB13 and SB14 Closed: PA2 and PA3 on STM32F103C8T6 (ST-LINK MCU) are
connected to PA3 and PA2 on STM32 MCU to have USART communication
between them. Thus SB61, SB62 and SB63 should be OFF.
Configuring USART2 is the same as given above.
Question: What BAUD should be configure to interface with the Virtual
COM port? 115200 8N1?
Default
-------
As shipped, SB62 and SB63 are open and SB13 and SB14 closed, so the
virtual COM port is enabled.
RS-232 Shield
-------------
Supports a single RS-232 connected via
Nucleo STM32F4x1RE Shield
--------- --------------- --------
CN9 Pin 1 PA3 USART2_RXD RXD
CN9 Pin 2 PA2 USART2_TXD TXD
Support for this shield is enabled by selecting USART2 and configuring
SB13, 14, 62, and 63 as described above under "Virtual COM Port"
Configurations
==============
Information Common to All Configurations
----------------------------------------
Each Clicker2 configuration is maintained in a sub-directory and can be
selected as follow:
cd tools
./configure.sh nucleo-f702rb/<subdir>
cd -
. ./setenv.sh
Before sourcing the setenv.sh file above, you should examine it and
perform edits as necessary so that TOOLCHAIN_BIN is the correct path
to the directory than holds your toolchain binaries.
And then build NuttX by simply typing the following. At the conclusion of
the make, the nuttx binary will reside in an ELF file called, simply, nuttx.
make oldconfig
make
The <subdir> that is provided above as an argument to the tools/configure.sh
must be is one of the following.
NOTES:
1. These configurations use the mconf-based configuration tool. To
change any of these configurations using that tool, you should:
a. Build and install the kconfig-mconf tool. See nuttx/README.txt
see additional README.txt files in the NuttX tools repository.
b. Execute 'make menuconfig' in nuttx/ in order to start the
reconfiguration process.
2. Unless stated otherwise, all configurations generate console
output on USART2, as described above under "Serial Console". The
elevant configuration settings are listed below:
CONFIG_STM32_USART2=y
CONFIG_STM32_USART2_SERIALDRIVER=y
CONFIG_STM32_USART=y
CONFIG_USART2_SERIALDRIVER=y
CONFIG_USART2_SERIAL_CONSOLE=y
CONFIG_USART2_RXBUFSIZE=256
CONFIG_USART2_TXBUFSIZE=256
CONFIG_USART2_BAUD=115200
CONFIG_USART2_BITS=8
CONFIG_USART2_PARITY=0
CONFIG_USART2_2STOP=0
3. All of these configurations are set up to build under Linux using the
"GNU Tools for ARM Embedded Processors" that is maintained by ARM
(unless stated otherwise in the description of the configuration).
https://launchpad.net/gcc-arm-embedded
That toolchain selection can easily be reconfigured using
'make menuconfig'. Here are the relevant current settings:
Build Setup:
CONFIG_HOST_LINUX=y : Linux environment
System Type -> Toolchain:
CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL=y : GNU ARM EABI toolchain
Configuration sub-directories
-----------------------------
nsh:
Configures the NuttShell (nsh) located at examples/nsh. This
configuration is focused on low level, command-line driver testing.
NOTES:
1. Support for NSH built-in applications is provided:
Binary Formats:
CONFIG_BUILTIN=y : Enable support for built-in programs
Application Configuration:
CONFIG_NSH_BUILTIN_APPS=y : Enable starting apps from NSH command line
No built applications are enabled in the base configuration, however.
2. C++ support for applications is enabled:
CONFIG_HAVE_CXX=y
CONFIG_HAVE_CXXINITIALIZE=y
CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y
configs/nucleo-f072rb/include/board.h
+241
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@@ -0,0 +1,241 @@
/************************************************************************************
* configs/nucleo-f072rb/include/board.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* Alan Carvalho de Assis <acassis@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __CONFIG_NUCLEO_F072RB_INCLUDE_BOARD_H
#define __CONFIG_NUCLEO_F072RB_INCLUDE_BOARD_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#ifndef __ASSEMBLY__
# include <stdint.h>
#endif
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Clocking *************************************************************************/
/* Four different clock sources can be used to drive the system clock (SYSCLK):
*
* - HSI high-speed internal oscillator clock
* Generated from an internal 8 MHz RC oscillator
* - HSE high-speed external oscillator clock
* Normally driven by an external crystal (X3). However, this crystal is not
* fitted on the Nucleo-F072RB board.
* - PLL clock
* - MSI multispeed internal oscillator clock
* The MSI clock signal is generated from an internal RC oscillator. Seven frequency
* ranges are available: 65.536 kHz, 131.072 kHz, 262.144 kHz, 524.288 kHz, 1.048 MHz,
* 2.097 MHz (default value) and 4.194 MHz.
*
* The devices have the following two secondary clock sources
* - LSI low-speed internal RC clock
* Drives the watchdog and RTC. Approximately 37KHz
* - LSE low-speed external oscillator clock
* Driven by 32.768KHz crystal (X2) on the OSC32_IN and OSC32_OUT pins.
*/
#define STM32F0_BOARD_XTAL 8000000ul /* X3 on board (not fitted)*/
#define STM32F0_HSI_FREQUENCY 8000000ul /* Approximately 8MHz */
#define STM32F0_HSI14_FREQUENCY 14000000ul /* HSI14 for ADC */
#define STM32F0_HSI48_FREQUENCY 48000000ul /* HSI48 for USB, only some STM32F0xx */
#define STM32F0_HSE_FREQUENCY STM32F0_BOARD_XTAL
#define STM32F0_LSI_FREQUENCY 40000 /* Approximately 40KHz */
#define STM32F0_LSE_FREQUENCY 32768 /* X2 on board */
/* PLL Configuration
*
* - PLL source is HSI -> 8MHz input (nominal)
* - PLL source predivider 2 -> 4MHz divided down PLL VCO clock output
* - PLL multipler is 12 -> 48MHz PLL VCO clock output (for USB)
*
* Resulting SYSCLK frequency is 8MHz x 12 / 2 = 48MHz
*
* USB:
* If the USB interface is used in the application, it requires a precise
* 48MHz clock which can be generated from either the (1) the internal
* main PLL with the HSE clock source using an HSE crystal oscillator. In
* this case, the PLL VCO clock (defined by STM32F0_CFGR_PLLMUL) must be
* programmed to output a 96 MHz frequency. This is required to provide a
* 48MHz clock to the (USBCLK = PLLVCO/2). Or (2) by using the internal
* 48MHz oscillator in automatic trimming mode. The synchronization for
* this oscillator can be taken from the USB data stream itself (SOF
* signalization) which allows crystal-less operation.
* SYSCLK
* The system clock is derived from the PLL VCO divided by the output
* division factor.
* Limitations:
* - 96 MHz as PLLVCO when the product is in range 1 (1.8V),
* - 48 MHz as PLLVCO when the product is in range 2 (1.5V),
* - 24 MHz when the product is in range 3 (1.2V).
* - Output division to avoid exceeding 32 MHz as SYSCLK.
* - The minimum input clock frequency for PLL is 2 MHz (when using HSE as
* PLL source).
*/
#define STM32F0_CFGR_PLLSRC RCC_CFGR_PLLSRC_HSId2 /* Source is HSI/2 */
#define STM32F0_PLLSRC_FREQUENCY (STM32F0_HSI_FREQUENCY/2) /* 8MHz / 2 = 4MHz */
#ifdef CONFIG_STM32F0_USB
# undef STM32F0_CFGR2_PREDIV /* Not used with source HSI/2 */
# define STM32F0_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx12 /* PLLMUL = 12 */
# define STM32F0_PLL_FREQUENCY (12*STM32F0_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */
#else
# undef STM32F0_CFGR2_PREDIV /* Not used with source HSI/2 */
# define STM32F0_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx12 /* PLLMUL = 12 */
# define STM32F0_PLL_FREQUENCY (12*STM32F0_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */
#endif
/* Use the PLL and set the SYSCLK source to be the divided down PLL VCO output
* frequency (STM32F0_PLL_FREQUENCY divided by the PLLDIV value).
*/
#define STM32F0_SYSCLK_SW RCC_CFGR_SW_PLL /* Use the PLL as the SYSCLK */
#define STM32F0_SYSCLK_SWS RCC_CFGR_SWS_PLL
#ifdef CONFIG_STM32F0_USB
# define STM32F0_SYSCLK_FREQUENCY STM32F0_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */
#else
# define STM32F0_SYSCLK_FREQUENCY STM32F0_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */
#endif
#define STM32F0_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK
#define STM32F0_HCLK_FREQUENCY STM32F0_SYSCLK_FREQUENCY
#define STM32F0_BOARD_HCLK STM32F0_HCLK_FREQUENCY /* Same as above, to satisfy compiler */
/* APB1 clock (PCLK1) is HCLK (48MHz) */
#define STM32F0_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK
#define STM32F0_PCLK1_FREQUENCY (STM32F0_HCLK_FREQUENCY)
/* APB2 clock (PCLK2) is HCLK (48MHz) */
#define STM32F0_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK
#define STM32F0_PCLK2_FREQUENCY STM32F0_HCLK_FREQUENCY
#define STM32F0_APB2_CLKIN (STM32F0_PCLK2_FREQUENCY)
/* APB1 timers 1-3, 6-7, and 14-17 will receive PCLK1 */
#define STM32F0_APB1_TIM1_CLKIN (STM32F0_PCLK1_FREQUENCY)
#define STM32F0_APB1_TIM2_CLKIN (STM32F0_PCLK1_FREQUENCY)
#define STM32F0_APB1_TIM3_CLKIN (STM32F0_PCLK1_FREQUENCY)
#define STM32F0_APB1_TIM6_CLKIN (STM32F0_PCLK1_FREQUENCY)
#define STM32F0_APB1_TIM7_CLKIN (STM32F0_PCLK1_FREQUENCY)
#define STM32F0_APB1_TIM14_CLKIN (STM32F0_PCLK1_FREQUENCY)
#define STM32F0_APB1_TIM15_CLKIN (STM32F0_PCLK1_FREQUENCY)
#define STM32F0_APB1_TIM16_CLKIN (STM32F0_PCLK1_FREQUENCY)
#define STM32F0_APB1_TIM17_CLKIN (STM32F0_PCLK1_FREQUENCY)
/* LED definitions ******************************************************************/
/* LEDs
*
* The Nucleo-64 board has one user controlable LED, User LD2. This green
* LED is a user LED connected to Arduino signal D13 corresponding to STM32
* I/O PA5 (PB13 on other some other Nucleo-64 boards).
*
* - When the I/O is HIGH value, the LED is on
* - When the I/O is LOW, the LED is off
*/
/* LED index values for use with board_userled() */
#define BOARD_LD2 0
#define BOARD_NLEDS 1
/* LED bits for use with board_userled_all() */
#define BOARD_LD2_BIT (1 << BOARD_LD2)
/* These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is
* defined. In that case, the usage by the board port is defined in
* include/board.h and src/sam_leds.c. The LEDs are used to encode OS-related
* events as follows when the red LED (PE24) is available:
*
* SYMBOL Meaning LD2
* ------------------- ----------------------- -----------
* LED_STARTED NuttX has been started OFF
* LED_HEAPALLOCATE Heap has been allocated OFF
* LED_IRQSENABLED Interrupts enabled OFF
* LED_STACKCREATED Idle stack created ON
* LED_INIRQ In an interrupt No change
* LED_SIGNAL In a signal handler No change
* LED_ASSERTION An assertion failed No change
* LED_PANIC The system has crashed Blinking
* LED_IDLE MCU is is sleep mode Not used
*
* Thus if LD2, NuttX has successfully booted and is, apparently, running
* normally. If LD2 is flashing at approximately 2Hz, then a fatal error
* has been detected and the system has halted.
*/
#define LED_STARTED 0
#define LED_HEAPALLOCATE 0
#define LED_IRQSENABLED 0
#define LED_STACKCREATED 1
#define LED_INIRQ 2
#define LED_SIGNAL 2
#define LED_ASSERTION 2
#define LED_PANIC 1
/* Button definitions ***************************************************************/
/* Buttons
*
* B1 USER: the user button is connected to the I/O PC13 (pin 2) of the STM32
* microcontroller.
*/
#define BUTTON_USER 0
#define NUM_BUTTONS 1
#define BUTTON_USER_BIT (1 << BUTTON_USER)
/* Alternate Pin Functions **********************************************************/
/* USART 1 */
#define GPIO_USART1_TX GPIO_USART1_TX_2
#define GPIO_USART1_RX GPIO_USART1_RX_2
/* USART 2 */
#define GPIO_USART2_TX GPIO_USART2_TX_3
#define GPIO_USART2_RX GPIO_USART2_RX_3
#endif /* __CONFIG_NUCLEO_F072RB_INCLUDE_BOARD_H */
configs/nucleo-f072rb/nsh/Make.defs
+113
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############################################################################
# configs/nucleo-f072rb/nsh/Make.defs
#
# Copyright (C) 2017 Gregory Nutt. All rights reserved.
# Author: Gregory Nutt <gnutt@nuttx.org>
# Alan Carvalho de Assis <acassis@gmail.com>
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# 1. Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in
# the documentation and/or other materials provided with the
# distribution.
# 3. Neither the name NuttX nor the names of its contributors may be
# used to endorse or promote products derived from this software
# without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
#
############################################################################
include ${TOPDIR}/.config
include ${TOPDIR}/tools/Config.mk
include ${TOPDIR}/arch/arm/src/armv6-m/Toolchain.defs
LDSCRIPT = flash.ld
ifeq ($(WINTOOL),y)
# Windows-native toolchains
DIRLINK = $(TOPDIR)/tools/copydir.sh
DIRUNLINK = $(TOPDIR)/tools/unlink.sh
MKDEP = $(TOPDIR)/tools/mkwindeps.sh
ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}"
ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}"
ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}"
else
# Linux/Cygwin-native toolchain
MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT)
ARCHINCLUDES = -I. -isystem $(TOPDIR)/include
ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx
ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)
endif
CC = $(CROSSDEV)gcc
CXX = $(CROSSDEV)g++
CPP = $(CROSSDEV)gcc -E
LD = $(CROSSDEV)ld
AR = $(ARCROSSDEV)ar rcs
NM = $(ARCROSSDEV)nm
OBJCOPY = $(CROSSDEV)objcopy
OBJDUMP = $(CROSSDEV)objdump
ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'}
ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1}
ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
ARCHOPTIMIZATION = -g
endif
ifneq ($(CONFIG_DEBUG_NOOPT),y)
ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer
endif
ARCHCFLAGS = -fno-builtin
ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -fno-rtti
ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef
ARCHWARNINGSXX = -Wall -Wshadow -Wundef
ARCHDEFINES =
ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10
CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe
CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS)
CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe
CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS)
CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES)
AFLAGS = $(CFLAGS) -D__ASSEMBLY__
NXFLATLDFLAGS1 = -r -d -warn-common
NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections
LDNXFLATFLAGS = -e main -s 2048
ASMEXT = .S
OBJEXT = .o
LIBEXT = .a
EXEEXT =
ifneq ($(CROSSDEV),arm-nuttx-elf-)
LDFLAGS += -nostartfiles -nodefaultlibs
endif
ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
LDFLAGS += -g
endif
HOSTCC = gcc
HOSTINCLUDES = -I.
HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe
HOSTLDFLAGS =
configs/nucleo-f072rb/nsh/defconfig
+1043
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configs/nucleo-f072rb/nsh/setenv.sh
+81
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@@ -0,0 +1,81 @@
#!/bin/bash
# configs/nucleo-f072rb/nsh/setenv.sh
#
# Copyright (C) 2017 Gregory Nutt. All rights reserved.
# Author: Gregory Nutt <gnutt@nuttx.org>
# Alan Carvalho de Assis <acassis@gmail.com>
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# 1. Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in
# the documentation and/or other materials provided with the
# distribution.
# 3. Neither the name NuttX nor the names of its contributors may be
# used to endorse or promote products derived from this software
# without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
#
if [ "$_" = "$0" ] ; then
echo "You must source this script, not run it!" 1>&2
exit 1
fi
WD=`pwd`
if [ ! -x "setenv.sh" ]; then
echo "This script must be executed from the top-level NuttX build directory"
exit 1
fi
if [ -z "${PATH_ORIG}" ]; then
export PATH_ORIG="${PATH}"
fi
# This is the Cygwin path to the location where I installed the CodeSourcery
# toolchain under windows. You will also have to edit this if you install
# the CodeSourcery toolchain in any other location
#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin"
#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery_CodeBench_Lite_for_ARM_EABI/bin"
# export TOOLCHAIN_BIN="/cygdrive/c/Users/MyName/MentorGraphics/Sourcery_CodeBench_Lite_for_ARM_EABI/bin"
# This is the location where I installed the ARM "GNU Tools for ARM Embedded Processors"
# You can this free toolchain here https://launchpad.net/gcc-arm-embedded
export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/GNU Tools ARM Embedded/4.9 2015q2/bin"
# This is the path to the location where I installed the devkitARM toolchain
# You can get this free toolchain from http://devkitpro.org/ or http://sourceforge.net/projects/devkitpro/
#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/devkitARM/bin"
# These are the Cygwin paths to the locations where I installed the Atollic
# toolchain under windows. You will also have to edit this if you install
# the Atollic toolchain in any other location. /usr/bin is added before
# the Atollic bin path because there is are binaries named gcc.exe and g++.exe
# at those locations as well.
#export TOOLCHAIN_BIN="/usr/bin:/cygdrive/c/Program Files (x86)/Atollic/TrueSTUDIO for ARM Pro 2.3.0/ARMTools/bin"
#export TOOLCHAIN_BIN="/usr/bin:/cygdrive/c/Program Files (x86)/Atollic/TrueSTUDIO for STMicroelectronics STM32 Lite 2.3.0/ARMTools/bin"
# This is the Cygwin path to the location where I build the buildroot
# toolchain.
# export TOOLCHAIN_BIN="${WD}/../buildroot/build_arm_nofpu/staging_dir/bin"
# Add the path to the toolchain to the PATH varialble
export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}"
echo "PATH : ${PATH}"
configs/nucleo-f072rb/scripts/flash.ld
+127
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/****************************************************************************
* configs/nucleo-f072rb/scripts/flash.ld
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* Alan Carvalho de Assis <acassis@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/* The STM32F072RBT6 has 128KB of FLASH beginning at address 0x0800:0000 and
* 16Kb of SRAM at address 0x20000000.
*
* When booting from FLASH, FLASH memory is aliased to address 0x0000:0000
* where the code expects to begin execution by jumping to the entry point in
* the 0x0800:0000 address range.
*/
MEMORY
{
flash (rx) : ORIGIN = 0x08000000, LENGTH = 128K
sram (rwx) : ORIGIN = 0x20000000, LENGTH = 16K
}
OUTPUT_ARCH(arm)
EXTERN(_vectors)
ENTRY(_stext)
SECTIONS
{
.text :
{
_stext = ABSOLUTE(.);
*(.vectors)
*(.text .text.*)
*(.fixup)
*(.gnu.warning)
*(.rodata .rodata.*)
*(.gnu.linkonce.t.*)
*(.glue_7)
*(.glue_7t)
*(.got)
*(.gcc_except_table)
*(.gnu.linkonce.r.*)
_etext = ABSOLUTE(.);
} > flash
.init_section :
{
_sinit = ABSOLUTE(.);
*(.init_array .init_array.*)
_einit = ABSOLUTE(.);
} > flash
.ARM.extab :
{
*(.ARM.extab*)
} > flash
__exidx_start = ABSOLUTE(.);
.ARM.exidx :
{
*(.ARM.exidx*)
} > flash
__exidx_end = ABSOLUTE(.);
_eronly = ABSOLUTE(.);
.data :
{
_sdata = ABSOLUTE(.);
*(.data .data.*)
*(.gnu.linkonce.d.*)
CONSTRUCTORS
_edata = ABSOLUTE(.);
} > sram AT > flash
.bss :
{
_sbss = ABSOLUTE(.);
*(.bss .bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
_ebss = ABSOLUTE(.);
} > sram
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_info 0 : { *(.debug_info) }
.debug_line 0 : { *(.debug_line) }
.debug_pubnames 0 : { *(.debug_pubnames) }
.debug_aranges 0 : { *(.debug_aranges) }
}
configs/nucleo-f072rb/src/.gitignore
+2
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@@ -0,0 +1,2 @@
/.depend
/Make.dep
configs/nucleo-f072rb/src/Makefile
+56
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@@ -0,0 +1,56 @@
############################################################################
# configs/nucleo-f072rb/src/Makefile
#
# Copyright (C) 2017 Gregory Nutt. All rights reserved.
# Author: Gregory Nutt <gnutt@nuttx.org>
# Alan Carvalho de Assis <acassis@gmail.com>
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# 1. Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in
# the documentation and/or other materials provided with the
# distribution.
# 3. Neither the name NuttX nor the names of its contributors may be
# used to endorse or promote products derived from this software
# without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
#
############################################################################
-include $(TOPDIR)/Make.defs
ASRCS =
CSRCS = stm32_boot.c stm32_bringup.c
ifeq ($(CONFIG_ARCH_LEDS),y)
CSRCS += stm32_autoleds.c
else
CSRCS += stm32_userleds.c
endif
ifeq ($(CONFIG_ARCH_BUTTONS),y)
CSRCS += stm32_buttons.c
endif
ifeq ($(CONFIG_LIB_BOARDCTL),y)
CSRCS += stm32_appinit.c
endif
include $(TOPDIR)/configs/Board.mk
configs/nucleo-f072rb/src/nucleo-f072rb.h
+123
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/****************************************************************************
* configs/nucleo-f072rb/src/nucleo-f072rb.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* Alan Carvalho de Assis <acassis@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __CONFIGS_NUCLEO_F072RB_SRC_NUCLEO_F072RB_H
#define __CONFIGS_NUCLEO_F072RB_SRC_NUCLEO_F072RB_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/compiler.h>
#include <stdint.h>
#include "stm32f0_gpio.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Configuration ************************************************************/
/* How many SPI modules does this chip support? */
#if STM32F0_NSPI < 1
# undef CONFIG_STM32F0_SPI1
# undef CONFIG_STM32F0_SPI2
# undef CONFIG_STM32F0_SPI3
#elif STM32F0_NSPI < 2
# undef CONFIG_STM32F0_SPI2
# undef CONFIG_STM32F0_SPI3
#elif STM32F0_NSPI < 3
# undef CONFIG_STM32F0_SPI3
#endif
/* Nucleo-F072RB GPIOs ******************************************************/
/* LED. User LD2: the green LED is a user LED connected to Arduino signal
* D13 corresponding to MCU I/O PA5 (pin 21) or PB13 (pin 34) depending on
* the STM32 target.
*
* - When the I/O is HIGH value, the LED is on.
* - When the I/O is LOW, the LED is off.
*/
#define GPIO_LD2 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_10MHz | \
GPIO_OUTPUT_CLEAR | GPIO_PORTA | GPIO_PIN5)
/* Button definitions *******************************************************/
/* B1 USER: the user button is connected to the I/O PC13 (pin 2) of the STM32
* microcontroller.
*/
#define MIN_IRQBUTTON BUTTON_USER
#define MAX_IRQBUTTON BUTTON_USER
#define NUM_IRQBUTTONS 1
#define GPIO_BTN_USER (GPIO_INPUT | GPIO_FLOAT | GPIO_EXTI | \
GPIO_PORTC | GPIO_PIN13)
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public data
****************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: stm32_bringup
*
* Description:
* Perform architecture-specific initialization
*
* CONFIG_BOARD_INITIALIZE=y :
* Called from board_initialize().
*
* CONFIG_BOARD_INITIALIZE=n && CONFIG_LIB_BOARDCTL=y :
* Called from the NSH library
*
****************************************************************************/
int stm32_bringup(void);
#endif /* __ASSEMBLY__ */
#endif /* __CONFIGS_NUCLEO_F072RB_SRC_NUCLEO_F072RB_H */
configs/nucleo-f072rb/src/stm32_appinit.c
+87
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/****************************************************************************
* config/nucleo-f072rb/src/stm32_appinit.c
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* Alan Carvalho de Assis <acassis@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <nuttx/board.h>
#include "nucleo-f072rb.h"
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: board_app_initialize
*
* Description:
* Perform application specific initialization. This function is never
* called directly from application code, but only indirectly via the
* (non-standard) boardctl() interface using the command BOARDIOC_INIT.
*
* Input Parameters:
* arg - The boardctl() argument is passed to the board_app_initialize()
* implementation without modification. The argument has no
* meaning to NuttX; the meaning of the argument is a contract
* between the board-specific initalization logic and the the
* matching application logic. The value cold be such things as a
* mode enumeration value, a set of DIP switch switch settings, a
* pointer to configuration data read from a file or serial FLASH,
* or whatever you would like to do with it. Every implementation
* should accept zero/NULL as a default configuration.
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned on
* any failure to indicate the nature of the failure.
*
****************************************************************************/
int board_app_initialize(uintptr_t arg)
{
/* Did we already initialize via board_initialize()? */
#ifndef CONFIG_BOARD_INITIALIZE
return stm32_bringup();
#else
return OK;
#endif
}
configs/nucleo-f072rb/src/stm32_autoleds.c
+96
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@@ -0,0 +1,96 @@
/****************************************************************************
* configs/nucleo-f072rb/src/stm32_autoleds.c
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <stdbool.h>
#include <debug.h>
#include <nuttx/board.h>
#include <arch/board/board.h>
#include "chip.h"
#include "up_arch.h"
#include "up_internal.h"
#include "stm32f0_gpio.h"
#include "nucleo-f072rb.h"
#ifdef CONFIG_ARCH_LEDS
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: board_autoled_initialize
****************************************************************************/
void board_autoled_initialize(void)
{
/* Configure LD2 GPIO for output */
stm32f0_configgpio(GPIO_LD2);
}
/****************************************************************************
* Name: board_autoled_on
****************************************************************************/
void board_autoled_on(int led)
{
if (led == 1)
{
stm32f0_gpiowrite(GPIO_LD2, true);
}
}
/****************************************************************************
* Name: board_autoled_off
****************************************************************************/
void board_autoled_off(int led)
{
if (led == 1)
{
stm32f0_gpiowrite(GPIO_LD2, false);
}
}
#endif /* CONFIG_ARCH_LEDS */
configs/nucleo-f072rb/src/stm32_boot.c
+94
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@@ -0,0 +1,94 @@
/************************************************************************************
* configs/nucleo-f072rb/src/stm32f0_boot.c
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* Alan Carvalho de Assis <acassis@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include <debug.h>
#include <nuttx/board.h>
#include <arch/board/board.h>
#include "up_arch.h"
#include "nucleo-f072rb.h"
/************************************************************************************
* Public Functions
************************************************************************************/
/************************************************************************************
* Name: stm32f0_boardinitialize
*
* Description:
* All STM32 architectures must provide the following entry point. This entry point
* is called early in the intitialization -- after all memory has been configured
* and mapped but before any devices have been initialized.
*
************************************************************************************/
void stm32f0_boardinitialize(void)
{
#ifdef CONFIG_ARCH_LEDS
/* Configure on-board LEDs if LED support has been selected. */
board_autoled_initialize();
#endif
}
/****************************************************************************
* Name: board_initialize
*
* Description:
* If CONFIG_BOARD_INITIALIZE is selected, then an additional
* initialization call will be performed in the boot-up sequence to a
* function called board_initialize(). board_initialize() will be
* called immediately after up_initialize() is called and just before the
* initial application is started. This additional initialization phase
* may be used, for example, to initialize board-specific device drivers.
*
****************************************************************************/
#ifdef CONFIG_BOARD_INITIALIZE
void board_initialize(void)
{
/* Perform board-specific initialization here if so configured */
(void)stm32_bringup();
}
#endif
configs/nucleo-f072rb/src/stm32_bringup.c
+81
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@@ -0,0 +1,81 @@
/****************************************************************************
* config/nucleo-f072rb/src/stm32_bringup.c
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/mount.h>
#include <sys/types.h>
#include "nucleo-f072rb.h"
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: stm32_bringup
*
* Description:
* Perform architecture-specific initialization
*
* CONFIG_BOARD_INITIALIZE=y :
* Called from board_initialize().
*
* CONFIG_BOARD_INITIALIZE=n && CONFIG_LIB_BOARDCTL=y :
* Called from the NSH library
*
****************************************************************************/
int stm32_bringup(void)
{
int ret;
#ifdef CONFIG_FS_PROCFS
/* Mount the procfs file system */
ret = mount(NULL, "/proc", "procfs", 0, NULL);
if (ret < 0)
{
syslog(LOG_ERR, "ERROR: Failed to mount procfs at /proc: %d\n", ret);
}
#endif
UNUSED(ret);
return OK;
}
configs/nucleo-f072rb/src/stm32_buttons.c
+126
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/****************************************************************************
* configs/nucleo-f072rb/src/stm32_buttons.c
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <errno.h>
#include <nuttx/arch.h>
#include <nuttx/board.h>
#include <arch/board/board.h>
#include "nucleo-f072rb.h"
#ifdef CONFIG_ARCH_BUTTONS
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: board_button_initialize
*
* Description:
* board_button_initialize() must be called to initialize button resources.
* After that, board_buttons() may be called to collect the current state
* of all buttons or board_button_irq() may be called to register button
* interrupt handlers.
*
****************************************************************************/
void board_button_initialize(void)
{
/* Configure the single button as an input. NOTE that EXTI interrupts are
* also configured for the pin.
*/
stm32_configgpio(GPIO_BTN_USER);
}
/****************************************************************************
* Name: board_buttons
****************************************************************************/
uint32_t board_buttons(void)
{
/* Check that state of each USER button. A LOW value means that the key is
* pressed.
*/
bool released = stm32_gpioread(GPIO_BTN_USER);
return !released;
}
/************************************************************************************
* Button support.
*
* Description:
* board_button_initialize() must be called to initialize button resources. After
* that, board_buttons() may be called to collect the current state of all
* buttons or board_button_irq() may be called to register button interrupt
* handlers.
*
* After board_button_initialize() has been called, board_buttons() may be called to
* collect the state of all buttons. board_buttons() returns an 32-bit bit set
* with each bit associated with a button. See the BUTTON_*_BIT
* definitions in board.h for the meaning of each bit.
*
* board_button_irq() may be called to register an interrupt handler that will
* be called when a button is depressed or released. The ID value is a
* button enumeration value that uniquely identifies a button resource. See the
* BUTTON_* definitions in board.h for the meaning of enumeration
* value.
*
************************************************************************************/
#ifdef CONFIG_ARCH_IRQBUTTONS
int board_button_irq(int id, xcpt_t irqhandler, FAR void *arg)
{
int ret = -EINVAL;
if (id == BUTTON_USER)
{
ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, irqhandler, arg);
}
return ret;
}
#endif
#endif /* CONFIG_ARCH_BUTTONS */
configs/nucleo-f072rb/src/stm32_userleds.c
+217
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@@ -0,0 +1,217 @@
/****************************************************************************
* configs/nucleo-f072rb/src/stm32_userleds.c
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <stdbool.h>
#include <debug.h>
#include <arch/board/board.h>
#include <nuttx/power/pm.h>
#include "chip.h"
#include "up_arch.h"
#include "up_internal.h"
#include "stm32f0_gpio.h"
#include "nucleo-f072rb.h"
#ifndef CONFIG_ARCH_LEDS
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
/* LED Power Management */
#ifdef CONFIG_PM
static void led_pm_notify(struct pm_callback_s *cb, int domain,
enum pm_state_e pmstate);
static int led_pm_prepare(struct pm_callback_s *cb, int domain,
enum pm_state_e pmstate);
#endif
/****************************************************************************
* Private Data
****************************************************************************/
#ifdef CONFIG_PM
static struct pm_callback_s g_ledscb =
{
.notify = led_pm_notify,
.prepare = led_pm_prepare,
};
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: led_pm_notify
*
* Description:
* Notify the driver of new power state. This callback is called after
* all drivers have had the opportunity to prepare for the new power state.
*
****************************************************************************/
#ifdef CONFIG_PM
static void led_pm_notify(struct pm_callback_s *cb, int domain,
enum pm_state_e pmstate)
{
switch (pmstate)
{
case(PM_NORMAL):
{
/* Restore normal LEDs operation */
}
break;
case(PM_IDLE):
{
/* Entering IDLE mode - Turn leds off */
}
break;
case(PM_STANDBY):
{
/* Entering STANDBY mode - Logic for PM_STANDBY goes here */
}
break;
case(PM_SLEEP):
{
/* Entering SLEEP mode - Logic for PM_SLEEP goes here */
}
break;
default:
{
/* Should not get here */
}
break;
}
}
#endif
/****************************************************************************
* Name: led_pm_prepare
*
* Description:
* Request the driver to prepare for a new power state. This is a warning
* that the system is about to enter into a new power state. The driver
* should begin whatever operations that may be required to enter power
* state. The driver may abort the state change mode by returning a
* non-zero value from the callback function.
*
****************************************************************************/
#ifdef CONFIG_PM
static int led_pm_prepare(struct pm_callback_s *cb, int domain,
enum pm_state_e pmstate)
{
/* No preparation to change power modes is required by the LEDs driver.
* We always accept the state change by returning OK.
*/
return OK;
}
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: board_userled_initialize
****************************************************************************/
void board_userled_initialize(void)
{
/* Configure LD2 GPIO for output */
stm32f0_configgpio(GPIO_LD2);
}
/****************************************************************************
* Name: board_userled
****************************************************************************/
void board_userled(int led, bool ledon)
{
if (led == 1)
{
stm32f0_gpiowrite(GPIO_LD2, ldeon);
}
}
/****************************************************************************
* Name: board_userled_all
****************************************************************************/
void board_userled_all(uint8_t ledset)
{
if (led == 1)
{
stm32f0_gpiowrite(GPIO_LD2, (ledset & BOARD_LD2_BIT) != 0);
}
}
/****************************************************************************
* Name: stm32f0_led_pminitialize
****************************************************************************/
#ifdef CONFIG_PM
void stm32f0_led_pminitialize(void)
{
/* Register to receive power management callbacks */
int ret = pm_register(&g_ledscb);
DEBUGASSERT(ret == OK);
UNUSED(ret);
}
#endif /* CONFIG_PM */
#endif /* !CONFIG_ARCH_LEDS */
configs/nucleo-f303re/adc/defconfig
+24 -4
View File
@@ -90,6 +90,7 @@ CONFIG_ARCH="arm"
# CONFIG_ARCH_CHIP_LPC2378 is not set
# CONFIG_ARCH_CHIP_LPC31XX is not set
# CONFIG_ARCH_CHIP_LPC43XX is not set
# CONFIG_ARCH_CHIP_MOXART is not set
# CONFIG_ARCH_CHIP_NUC1XX is not set
# CONFIG_ARCH_CHIP_SAMA5 is not set
# CONFIG_ARCH_CHIP_SAMD is not set
@@ -97,11 +98,12 @@ CONFIG_ARCH="arm"
# CONFIG_ARCH_CHIP_SAM34 is not set
# CONFIG_ARCH_CHIP_SAMV7 is not set
CONFIG_ARCH_CHIP_STM32=y
# CONFIG_ARCH_CHIP_STM32F0 is not set
# CONFIG_ARCH_CHIP_STM32F7 is not set
# CONFIG_ARCH_CHIP_STM32L4 is not set
# CONFIG_ARCH_CHIP_STR71X is not set
# CONFIG_ARCH_CHIP_TMS570 is not set
# CONFIG_ARCH_CHIP_MOXART is not set
# CONFIG_ARCH_CHIP_XMC4 is not set
# CONFIG_ARCH_ARM7TDMI is not set
# CONFIG_ARCH_ARM926EJS is not set
# CONFIG_ARCH_ARM920T is not set
@@ -371,9 +373,13 @@ CONFIG_STM32_HAVE_ADC1_DMA=y
# CONFIG_STM32_HAVE_SDADC3_DMA is not set
CONFIG_STM32_HAVE_CAN1=y
# CONFIG_STM32_HAVE_CAN2 is not set
# CONFIG_STM32_HAVE_COMP1 is not set
# CONFIG_STM32_HAVE_COMP2 is not set
# CONFIG_STM32_HAVE_COMP3 is not set
# CONFIG_STM32_HAVE_COMP4 is not set
# CONFIG_STM32_HAVE_COMP5 is not set
# CONFIG_STM32_HAVE_COMP6 is not set
# CONFIG_STM32_HAVE_COMP7 is not set
CONFIG_STM32_HAVE_DAC1=y
CONFIG_STM32_HAVE_DAC2=y
# CONFIG_STM32_HAVE_RNG is not set
@@ -387,7 +393,10 @@ CONFIG_STM32_HAVE_SPI4=y
# CONFIG_STM32_HAVE_SPI6 is not set
# CONFIG_STM32_HAVE_SAIPLL is not set
# CONFIG_STM32_HAVE_I2SPLL is not set
# CONFIG_STM32_HAVE_OPAMP is not set
# CONFIG_STM32_HAVE_OPAMP1 is not set
# CONFIG_STM32_HAVE_OPAMP2 is not set
# CONFIG_STM32_HAVE_OPAMP3 is not set
# CONFIG_STM32_HAVE_OPAMP4 is not set
CONFIG_STM32_ADC1=y
# CONFIG_STM32_ADC2 is not set
# CONFIG_STM32_ADC3 is not set
@@ -401,6 +410,7 @@ CONFIG_STM32_DMA2=y
# CONFIG_STM32_I2C1 is not set
# CONFIG_STM32_I2C2 is not set
# CONFIG_STM32_I2C3 is not set
# CONFIG_STM32_OPAMP is not set
# CONFIG_STM32_PWR is not set
# CONFIG_STM32_SDIO is not set
# CONFIG_STM32_SPI1 is not set
@@ -433,6 +443,7 @@ CONFIG_STM32_ADC=y
#
# Alternate Pin Mapping
#
# CONFIG_STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW is not set
# CONFIG_STM32_JTAG_DISABLE is not set
# CONFIG_STM32_JTAG_FULL_ENABLE is not set
# CONFIG_STM32_JTAG_NOJNTRST_ENABLE is not set
@@ -456,6 +467,7 @@ CONFIG_STM32_CCMEXCLUDE=y
#
# ADC Configuration
#
# CONFIG_STM32_ADC_NO_STARTUP_CONV is not set
# CONFIG_STM32_ADC1_DMA is not set
# CONFIG_STM32_HAVE_RTC_COUNTER is not set
# CONFIG_STM32_HAVE_RTC_SUBSECONDS is not set
@@ -611,6 +623,8 @@ CONFIG_SCHED_WAITPID=y
#
# CONFIG_PTHREAD_MUTEX_TYPES is not set
CONFIG_PTHREAD_MUTEX_ROBUST=y
# CONFIG_PTHREAD_MUTEX_UNSAFE is not set
# CONFIG_PTHREAD_MUTEX_BOTH is not set
CONFIG_NPTHREAD_KEYS=4
# CONFIG_PTHREAD_CLEANUP is not set
# CONFIG_CANCELLATION_POINTS is not set
@@ -709,10 +723,11 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y
CONFIG_ANALOG=y
CONFIG_ADC=y
CONFIG_ADC_FIFOSIZE=8
# CONFIG_ADC_NO_STARTUP_CONV is not set
# CONFIG_ADC_ADS1242 is not set
# CONFIG_ADC_ADS125X is not set
# CONFIG_ADC_LTC1867L is not set
# CONFIG_ADC_PGA11X is not set
# CONFIG_COMP is not set
# CONFIG_DAC is not set
# CONFIG_AUDIO_DEVICES is not set
# CONFIG_VIDEO_DEVICES is not set
@@ -749,6 +764,7 @@ CONFIG_ADC_FIFOSIZE=8
# CONFIG_SERIAL is not set
# CONFIG_USBDEV is not set
# CONFIG_USBHOST is not set
# CONFIG_USBMISC is not set
# CONFIG_HAVE_USBTRACE is not set
# CONFIG_DRIVERS_WIRELESS is not set
# CONFIG_DRIVERS_CONTACTLESS is not set
@@ -979,7 +995,6 @@ CONFIG_EXAMPLES_ADC_SWTRIG=y
# CONFIG_EXAMPLES_MM is not set
# CONFIG_EXAMPLES_MODBUS is not set
# CONFIG_EXAMPLES_MOUNT is not set
# CONFIG_EXAMPLES_NRF24L01TERM is not set
# CONFIG_EXAMPLES_NSH is not set
# CONFIG_EXAMPLES_NULL is not set
# CONFIG_EXAMPLES_NX is not set
@@ -1010,6 +1025,7 @@ CONFIG_EXAMPLES_ADC_SWTRIG=y
# CONFIG_EXAMPLES_USBSERIAL is not set
# CONFIG_EXAMPLES_WATCHDOG is not set
# CONFIG_EXAMPLES_WEBSERVER is not set
# CONFIG_EXAMPLES_XBC_TEST is not set
#
# File System Utilities
@@ -1080,3 +1096,7 @@ CONFIG_EXAMPLES_ADC_SWTRIG=y
# CONFIG_SYSTEM_UBLOXMODEM is not set
# CONFIG_SYSTEM_VI is not set
# CONFIG_SYSTEM_ZMODEM is not set
#
# Wireless Libraries and NSH Add-Ons
#
configs/nucleo-f303re/serialrx/defconfig
+23 -4
View File
@@ -90,6 +90,7 @@ CONFIG_ARCH="arm"
# CONFIG_ARCH_CHIP_LPC2378 is not set
# CONFIG_ARCH_CHIP_LPC31XX is not set
# CONFIG_ARCH_CHIP_LPC43XX is not set
# CONFIG_ARCH_CHIP_MOXART is not set
# CONFIG_ARCH_CHIP_NUC1XX is not set
# CONFIG_ARCH_CHIP_SAMA5 is not set
# CONFIG_ARCH_CHIP_SAMD is not set
@@ -97,11 +98,12 @@ CONFIG_ARCH="arm"
# CONFIG_ARCH_CHIP_SAM34 is not set
# CONFIG_ARCH_CHIP_SAMV7 is not set
CONFIG_ARCH_CHIP_STM32=y
# CONFIG_ARCH_CHIP_STM32F0 is not set
# CONFIG_ARCH_CHIP_STM32F7 is not set
# CONFIG_ARCH_CHIP_STM32L4 is not set
# CONFIG_ARCH_CHIP_STR71X is not set
# CONFIG_ARCH_CHIP_TMS570 is not set
# CONFIG_ARCH_CHIP_MOXART is not set
# CONFIG_ARCH_CHIP_XMC4 is not set
# CONFIG_ARCH_ARM7TDMI is not set
# CONFIG_ARCH_ARM926EJS is not set
# CONFIG_ARCH_ARM920T is not set
@@ -372,9 +374,13 @@ CONFIG_STM32_HAVE_ADC4=y
# CONFIG_STM32_HAVE_SDADC3_DMA is not set
CONFIG_STM32_HAVE_CAN1=y
# CONFIG_STM32_HAVE_CAN2 is not set
# CONFIG_STM32_HAVE_COMP1 is not set
# CONFIG_STM32_HAVE_COMP2 is not set
# CONFIG_STM32_HAVE_COMP3 is not set
# CONFIG_STM32_HAVE_COMP4 is not set
# CONFIG_STM32_HAVE_COMP5 is not set
# CONFIG_STM32_HAVE_COMP6 is not set
# CONFIG_STM32_HAVE_COMP7 is not set
CONFIG_STM32_HAVE_DAC1=y
CONFIG_STM32_HAVE_DAC2=y
# CONFIG_STM32_HAVE_RNG is not set
@@ -388,7 +394,10 @@ CONFIG_STM32_HAVE_SPI4=y
# CONFIG_STM32_HAVE_SPI6 is not set
# CONFIG_STM32_HAVE_SAIPLL is not set
# CONFIG_STM32_HAVE_I2SPLL is not set
# CONFIG_STM32_HAVE_OPAMP is not set
# CONFIG_STM32_HAVE_OPAMP1 is not set
# CONFIG_STM32_HAVE_OPAMP2 is not set
# CONFIG_STM32_HAVE_OPAMP3 is not set
# CONFIG_STM32_HAVE_OPAMP4 is not set
# CONFIG_STM32_ADC1 is not set
# CONFIG_STM32_ADC2 is not set
# CONFIG_STM32_ADC3 is not set
@@ -402,6 +411,7 @@ CONFIG_STM32_HAVE_SPI4=y
# CONFIG_STM32_I2C1 is not set
# CONFIG_STM32_I2C2 is not set
# CONFIG_STM32_I2C3 is not set
# CONFIG_STM32_OPAMP is not set
# CONFIG_STM32_PWR is not set
# CONFIG_STM32_SDIO is not set
# CONFIG_STM32_SPI1 is not set
@@ -433,6 +443,7 @@ CONFIG_STM32_UART4=y
#
# Alternate Pin Mapping
#
# CONFIG_STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW is not set
# CONFIG_STM32_JTAG_DISABLE is not set
# CONFIG_STM32_JTAG_FULL_ENABLE is not set
# CONFIG_STM32_JTAG_NOJNTRST_ENABLE is not set
@@ -626,6 +637,8 @@ CONFIG_SCHED_WAITPID=y
#
# CONFIG_PTHREAD_MUTEX_TYPES is not set
CONFIG_PTHREAD_MUTEX_ROBUST=y
# CONFIG_PTHREAD_MUTEX_UNSAFE is not set
# CONFIG_PTHREAD_MUTEX_BOTH is not set
CONFIG_NPTHREAD_KEYS=4
# CONFIG_PTHREAD_CLEANUP is not set
# CONFIG_CANCELLATION_POINTS is not set
@@ -724,10 +737,11 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y
CONFIG_ANALOG=y
CONFIG_ADC=y
CONFIG_ADC_FIFOSIZE=8
# CONFIG_ADC_NO_STARTUP_CONV is not set
# CONFIG_ADC_ADS1242 is not set
# CONFIG_ADC_ADS125X is not set
# CONFIG_ADC_LTC1867L is not set
# CONFIG_ADC_PGA11X is not set
# CONFIG_COMP is not set
# CONFIG_DAC is not set
# CONFIG_AUDIO_DEVICES is not set
# CONFIG_VIDEO_DEVICES is not set
@@ -812,6 +826,7 @@ CONFIG_UART4_2STOP=0
# CONFIG_PSEUDOTERM is not set
# CONFIG_USBDEV is not set
# CONFIG_USBHOST is not set
# CONFIG_USBMISC is not set
# CONFIG_HAVE_USBTRACE is not set
# CONFIG_DRIVERS_WIRELESS is not set
# CONFIG_DRIVERS_CONTACTLESS is not set
@@ -1038,7 +1053,6 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512
# CONFIG_EXAMPLES_MM is not set
# CONFIG_EXAMPLES_MODBUS is not set
# CONFIG_EXAMPLES_MOUNT is not set
# CONFIG_EXAMPLES_NRF24L01TERM is not set
# CONFIG_EXAMPLES_NSH is not set
# CONFIG_EXAMPLES_NULL is not set
# CONFIG_EXAMPLES_NX is not set
@@ -1077,6 +1091,7 @@ CONFIG_EXAMPLES_SERIALRX_PRINTSTR=y
# CONFIG_EXAMPLES_USBSERIAL is not set
# CONFIG_EXAMPLES_WATCHDOG is not set
# CONFIG_EXAMPLES_WEBSERVER is not set
# CONFIG_EXAMPLES_XBC_TEST is not set
#
# File System Utilities
@@ -1147,3 +1162,7 @@ CONFIG_EXAMPLES_SERIALRX_PRINTSTR=y
# CONFIG_SYSTEM_UBLOXMODEM is not set
# CONFIG_SYSTEM_VI is not set
# CONFIG_SYSTEM_ZMODEM is not set
#
# Wireless Libraries and NSH Add-Ons
#
configs/olimex-stm32-h405/usbnsh/defconfig
+24 -4
View File
@@ -90,6 +90,7 @@ CONFIG_ARCH="arm"
# CONFIG_ARCH_CHIP_LPC2378 is not set
# CONFIG_ARCH_CHIP_LPC31XX is not set
# CONFIG_ARCH_CHIP_LPC43XX is not set
# CONFIG_ARCH_CHIP_MOXART is not set
# CONFIG_ARCH_CHIP_NUC1XX is not set
# CONFIG_ARCH_CHIP_SAMA5 is not set
# CONFIG_ARCH_CHIP_SAMD is not set
@@ -97,11 +98,12 @@ CONFIG_ARCH="arm"
# CONFIG_ARCH_CHIP_SAM34 is not set
# CONFIG_ARCH_CHIP_SAMV7 is not set
CONFIG_ARCH_CHIP_STM32=y
# CONFIG_ARCH_CHIP_STM32F0 is not set
# CONFIG_ARCH_CHIP_STM32F7 is not set
# CONFIG_ARCH_CHIP_STM32L4 is not set
# CONFIG_ARCH_CHIP_STR71X is not set
# CONFIG_ARCH_CHIP_TMS570 is not set
# CONFIG_ARCH_CHIP_MOXART is not set
# CONFIG_ARCH_CHIP_XMC4 is not set
# CONFIG_ARCH_ARM7TDMI is not set
# CONFIG_ARCH_ARM926EJS is not set
# CONFIG_ARCH_ARM920T is not set
@@ -378,9 +380,13 @@ CONFIG_STM32_HAVE_ADC3=y
# CONFIG_STM32_HAVE_SDADC3_DMA is not set
CONFIG_STM32_HAVE_CAN1=y
CONFIG_STM32_HAVE_CAN2=y
# CONFIG_STM32_HAVE_COMP1 is not set
# CONFIG_STM32_HAVE_COMP2 is not set
# CONFIG_STM32_HAVE_COMP3 is not set
# CONFIG_STM32_HAVE_COMP4 is not set
# CONFIG_STM32_HAVE_COMP5 is not set
# CONFIG_STM32_HAVE_COMP6 is not set
# CONFIG_STM32_HAVE_COMP7 is not set
CONFIG_STM32_HAVE_DAC1=y
CONFIG_STM32_HAVE_DAC2=y
CONFIG_STM32_HAVE_RNG=y
@@ -394,7 +400,10 @@ CONFIG_STM32_HAVE_SPI3=y
# CONFIG_STM32_HAVE_SPI6 is not set
# CONFIG_STM32_HAVE_SAIPLL is not set
# CONFIG_STM32_HAVE_I2SPLL is not set
# CONFIG_STM32_HAVE_OPAMP is not set
# CONFIG_STM32_HAVE_OPAMP1 is not set
# CONFIG_STM32_HAVE_OPAMP2 is not set
# CONFIG_STM32_HAVE_OPAMP3 is not set
# CONFIG_STM32_HAVE_OPAMP4 is not set
CONFIG_STM32_ADC1=y
# CONFIG_STM32_ADC2 is not set
# CONFIG_STM32_ADC3 is not set
@@ -414,6 +423,7 @@ CONFIG_STM32_CAN1=y
# CONFIG_STM32_I2C1 is not set
# CONFIG_STM32_I2C2 is not set
# CONFIG_STM32_I2C3 is not set
# CONFIG_STM32_OPAMP is not set
CONFIG_STM32_OTGFS=y
# CONFIG_STM32_OTGHS is not set
CONFIG_STM32_PWR=y
@@ -453,6 +463,7 @@ CONFIG_STM32_CAN=y
# Alternate Pin Mapping
#
# CONFIG_STM32_FLASH_PREFETCH is not set
# CONFIG_STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW is not set
# CONFIG_STM32_JTAG_DISABLE is not set
# CONFIG_STM32_JTAG_FULL_ENABLE is not set
# CONFIG_STM32_JTAG_NOJNTRST_ENABLE is not set
@@ -488,6 +499,7 @@ CONFIG_STM32_ADC1_TIMTRIG=0
#
# ADC Configuration
#
# CONFIG_STM32_ADC_NO_STARTUP_CONV is not set
CONFIG_STM32_USART=y
CONFIG_STM32_SERIALDRIVER=y
@@ -668,6 +680,8 @@ CONFIG_SCHED_WAITPID=y
#
# CONFIG_PTHREAD_MUTEX_TYPES is not set
CONFIG_PTHREAD_MUTEX_ROBUST=y
# CONFIG_PTHREAD_MUTEX_UNSAFE is not set
# CONFIG_PTHREAD_MUTEX_BOTH is not set
CONFIG_NPTHREAD_KEYS=4
# CONFIG_PTHREAD_CLEANUP is not set
# CONFIG_CANCELLATION_POINTS is not set
@@ -777,10 +791,11 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y
CONFIG_ANALOG=y
CONFIG_ADC=y
CONFIG_ADC_FIFOSIZE=8
# CONFIG_ADC_NO_STARTUP_CONV is not set
# CONFIG_ADC_ADS1242 is not set
# CONFIG_ADC_ADS125X is not set
# CONFIG_ADC_LTC1867L is not set
# CONFIG_ADC_PGA11X is not set
# CONFIG_COMP is not set
# CONFIG_DAC is not set
# CONFIG_AUDIO_DEVICES is not set
# CONFIG_VIDEO_DEVICES is not set
@@ -905,6 +920,7 @@ CONFIG_CDCACM_VENDORSTR="NuttX"
CONFIG_CDCACM_PRODUCTSTR="CDC/ACM Serial"
# CONFIG_USBMSC is not set
# CONFIG_USBHOST is not set
# CONFIG_USBMISC is not set
# CONFIG_HAVE_USBTRACE is not set
# CONFIG_DRIVERS_WIRELESS is not set
# CONFIG_DRIVERS_CONTACTLESS is not set
@@ -1161,7 +1177,6 @@ CONFIG_EXAMPLES_CAN_READWRITE=y
# CONFIG_EXAMPLES_MM is not set
# CONFIG_EXAMPLES_MODBUS is not set
# CONFIG_EXAMPLES_MOUNT is not set
# CONFIG_EXAMPLES_NRF24L01TERM is not set
CONFIG_EXAMPLES_NSH=y
CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y
# CONFIG_EXAMPLES_NULL is not set
@@ -1194,6 +1209,7 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y
# CONFIG_EXAMPLES_USBSERIAL is not set
# CONFIG_EXAMPLES_WATCHDOG is not set
# CONFIG_EXAMPLES_WEBSERVER is not set
# CONFIG_EXAMPLES_XBC_TEST is not set
#
# File System Utilities
@@ -1363,3 +1379,7 @@ CONFIG_READLINE_ECHO=y
# CONFIG_SYSTEM_UBLOXMODEM is not set
# CONFIG_SYSTEM_VI is not set
# CONFIG_SYSTEM_ZMODEM is not set
#
# Wireless Libraries and NSH Add-Ons
#

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