diff --git a/boards/arm/stm32f0l0g0/nucleo-g070rb/README.txt b/boards/arm/stm32f0l0g0/nucleo-g070rb/README.txt
index e16f2f7bbf0..9a035a10efc 100644
--- a/boards/arm/stm32f0l0g0/nucleo-g070rb/README.txt
+++ b/boards/arm/stm32f0l0g0/nucleo-g070rb/README.txt
@@ -8,4 +8,5 @@ STATUS
 
   2019-09-04: Initial support for the STM32 Nucleo-G070RB board, based on STM32 Nucleo-G071RB.  
               Basic NSH configuration is functional.
+  2019-09-16: Enable PWR peripheral and increase sysclk to max. frequency.
 
diff --git a/boards/arm/stm32f0l0g0/nucleo-g070rb/configs/nsh/defconfig b/boards/arm/stm32f0l0g0/nucleo-g070rb/configs/nsh/defconfig
index 112369d7aa1..7898744ef56 100644
--- a/boards/arm/stm32f0l0g0/nucleo-g070rb/configs/nsh/defconfig
+++ b/boards/arm/stm32f0l0g0/nucleo-g070rb/configs/nsh/defconfig
@@ -11,8 +11,8 @@ CONFIG_ARCH="arm"
 CONFIG_ARCH_BOARD="nucleo-g070rb"
 CONFIG_ARCH_BOARD_NUCLEO_G070RB=y
 CONFIG_ARCH_CHIP="stm32f0l0g0"
-CONFIG_ARCH_CHIP_STM32G070RB=y
 CONFIG_ARCH_CHIP_STM32G0=y
+CONFIG_ARCH_CHIP_STM32G070RB=y
 CONFIG_ARCH_STACKDUMP=y
 CONFIG_BOARD_LOOPSPERMSEC=2796
 CONFIG_BUILTIN=y
@@ -48,6 +48,8 @@ CONFIG_START_DAY=19
 CONFIG_START_MONTH=5
 CONFIG_START_YEAR=2013
 CONFIG_STDIO_DISABLE_BUFFERING=y
+CONFIG_STM32F0L0G0_PWR=y
+CONFIG_STM32F0L0G0_STM32G0=y
 CONFIG_STM32F0L0G0_USART2=y
 CONFIG_SYSTEM_NSH=y
 CONFIG_TASK_NAME_SIZE=0
diff --git a/boards/arm/stm32f0l0g0/nucleo-g070rb/include/board.h b/boards/arm/stm32f0l0g0/nucleo-g070rb/include/board.h
index 502d3c4a76d..384aac51861 100644
--- a/boards/arm/stm32f0l0g0/nucleo-g070rb/include/board.h
+++ b/boards/arm/stm32f0l0g0/nucleo-g070rb/include/board.h
@@ -89,42 +89,42 @@
 
 /* Considering:
  * - PLL_SOURCE_FREQUENCY = STM32_HSI_FREQUENCY = 16,000,000
- * - PLL_DIV_M = 2
+ * - PLL_DIV_M = 1
  * - PLL_DIV_N = 8
  * - PLL_DIV_R = 2
  * - PLL_DIV_P = 2
  *
- *   PLL_VCO = (16,000,000 / 2) * 8 = 64 MHz
- *   PLLP    =    (PLL_VCO / 2)     = 32 MHz
- *   PLLR    =    (PLL_VCO / 2)     = 32 MHz
+ *   PLL_VCO = (16,000,000 / 1) * 8 = 128 MHz
+ *   PLLP    =    (PLL_VCO / 2)     = 64 MHz
+ *   PLLR    =    (PLL_VCO / 2)     = 64 MHz
  */
 
 #define STM32_PLLCFG_PLLSRC     RCC_PLLCFG_PLLSRC_HSI
 #define STM32_PLLCFG_PLLCFG     (RCC_PLLCFG_PLLPEN | \
                                  RCC_PLLCFG_PLLREN)
 
-#define STM32_PLLCFG_PLLM       RCC_PLLCFG_PLLM(2)
+#define STM32_PLLCFG_PLLM       RCC_PLLCFG_PLLM(1)
 #define STM32_PLLCFG_PLLN       RCC_PLLCFG_PLLN(8)
 #define STM32_PLLCFG_PLLP       RCC_PLLCFG_PLLP(2)
 #define STM32_PLLCFG_PLLR       RCC_PLLCFG_PLLR(2)
 
-#define STM32_VCO_FREQUENCY     ((STM32_HSI_FREQUENCY / 2) * 8)
+#define STM32_VCO_FREQUENCY     ((STM32_HSI_FREQUENCY / 1) * 8)
 #define STM32_PLLP_FREQUENCY    (STM32_VCO_FREQUENCY / 2)
 #define STM32_PLLR_FREQUENCY    (STM32_VCO_FREQUENCY / 2)
 
-/* Use the PLL and set the SYSCLK source to be the PLLR (32 MHz) */
+/* Use the PLL and set the SYSCLK source to be the PLLR (64 MHz) */
 
 #define STM32_SYSCLK_SW         RCC_CFGR_SW_PLL
 #define STM32_SYSCLK_SWS        RCC_CFGR_SWS_PLL
 #define STM32_SYSCLK_FREQUENCY  (STM32_PLLR_FREQUENCY)
 
-/* AHB clock (HCLK) is SYSCLK (32 MHz) */
+/* AHB clock (HCLK) is SYSCLK (64 MHz) */
 
 #define STM32_RCC_CFGR_HPRE     RCC_CFGR_HPRE_SYSCLK
 #define STM32_HCLK_FREQUENCY    STM32_SYSCLK_FREQUENCY
 #define STM32_BOARD_HCLK        STM32_HCLK_FREQUENCY
 
-/* APB1 clock (PCLK1) is HCLK (32 MHz) */
+/* APB1 clock (PCLK1) is HCLK (64 MHz) */
 
 #define STM32_RCC_CFGR_PPRE1    RCC_CFGR_PPRE1_HCLK
 #define STM32_PCLK1_FREQUENCY   STM32_HCLK_FREQUENCY