diff --git a/arch/arm/src/stm32/Kconfig b/arch/arm/src/stm32/Kconfig index a89fc985fc1..93ebf3ab4e7 100644 --- a/arch/arm/src/stm32/Kconfig +++ b/arch/arm/src/stm32/Kconfig @@ -5849,6 +5849,10 @@ config STM32_DAC1CH1_DMA if STM32_DAC1CH1_DMA +config STM32_DAC1CH1_DMA_BUFFER_SIZE + int "DAC1CH1 DMA buffer size" + default 256 + config STM32_DAC1CH1_TIMER int "DAC1CH1 timer" range 2 8 @@ -5871,6 +5875,10 @@ config STM32_DAC1CH2_DMA if STM32_DAC1CH2_DMA +config STM32_DAC1CH2_DMA_BUFFER_SIZE + int "DAC1CH2 DMA buffer size" + default 256 + config STM32_DAC1CH2_TIMER int "DAC1CH2 timer" range 2 8 @@ -5893,6 +5901,10 @@ config STM32_DAC2CH1_DMA if STM32_DAC2CH1_DMA +config STM32_DAC2CH1_DMA_BUFFER_SIZE + int "DAC2CH1 DMA buffer size" + default 256 + config STM32_DAC2CH1_TIMER int "DAC2CH1 timer" default 0 @@ -5904,10 +5916,6 @@ config STM32_DAC2CH1_TIMER_FREQUENCY endif -config STM32_DAC_DMA_BUFFER_SIZE - int "DAC DMA buffer size" - default 256 - endmenu config STM32_USART diff --git a/arch/arm/src/stm32/chip/stm32f10xxx_dma.h b/arch/arm/src/stm32/chip/stm32f10xxx_dma.h index 673093189ac..6cbd365fc4c 100644 --- a/arch/arm/src/stm32/chip/stm32f10xxx_dma.h +++ b/arch/arm/src/stm32/chip/stm32f10xxx_dma.h @@ -306,14 +306,14 @@ # define DMACHAN_TIM2_UP STM32_DMA1_CHAN2 # define DMACHAN_TIM3_CH3 STM32_DMA1_CHAN2 # define DMACHAN_TIM6_UP STM32_DMA1_CHAN2 -# define DMACHAN_DAC_CHAN1 STM32_DMA1_CHAN2 +# define DMACHAN_DAC1_CH1 STM32_DMA1_CHAN2 # define DMACHAN_SPI1_TX STM32_DMA1_CHAN3 # define DMACHAN_USART3_RX STM32_DMA1_CHAN3 # define DMACHAN_TIM3_CH4 STM32_DMA1_CHAN3 # define DMACHAN_TIM3_UP STM32_DMA1_CHAN3 # define DMACHAN_TIM7_UP STM32_DMA1_CHAN3 -# define DMACHAN_DAC_CHAN2 STM32_DMA1_CHAN3 +# define DMACHAN_DAC1_CH2 STM32_DMA1_CHAN3 # define DMACHAN_SPI2_RX STM32_DMA1_CHAN4 # define DMACHAN_USART1_TX STM32_DMA1_CHAN4 @@ -421,13 +421,13 @@ # define DMACHAN_UART4_RX STM32_DMA2_CHAN3 # define DMACHAN_TIM6_UP STM32_DMA2_CHAN3 -# define DMACHAN_DAC_CHAN1 STM32_DMA2_CHAN3 +# define DMACHAN_DAC1_CH1 STM32_DMA2_CHAN3 # define DMACHAN_TIM8_CH1 STM32_DMA2_CHAN3 # define DMACHAN_SDIO STM32_DMA2_CHAN4 # define DMACHAN_TIM5_CH2 STM32_DMA2_CHAN4 # define DMACHAN_TIM7_UP STM32_DMA2_CHAN4 -# define DMACHAN_DAC_CHAN2 STM32_DMA2_CHAN4 +# define DMACHAN_DAC1_CH2 STM32_DMA2_CHAN4 # define DMACHAN_ADC3 STM32_DMA2_CHAN5 # define DMACHAN_UART4_TX STM32_DMA2_CHAN5 @@ -509,86 +509,17 @@ # define DMACHAN_ADC2_2 STM32_DMA2_CHAN3 # define DMACHAN_UART4_RX STM32_DMA2_CHAN3 # define DMACHAN_TIM6_UP STM32_DMA2_CHAN3 -# define DMACHAN_DAC_CHAN1 STM32_DMA2_CHAN3 +# define DMACHAN_DAC1_CH1 STM32_DMA2_CHAN3 # define DMACHAN_TIM8_CH1 STM32_DMA2_CHAN3 # define DMACHAN_ADC4_2 STM32_DMA2_CHAN4 # define DMACHAN_TIM7_UP_2 STM32_DMA2_CHAN4 -# define DMACHAN_DAC_CHAN2 STM32_DMA2_CHAN4 +# define DMACHAN_DAC1_CH2 STM32_DMA2_CHAN4 # define DMACHAN_ADC3 STM32_DMA2_CHAN5 # define DMACHAN_UART4_TX STM32_DMA2_CHAN5 # define DMACHAN_TIM8_CH2 STM32_DMA2_CHAN5 -#elif defined(CONFIG_STM32_STM32F33XX) - -# define DMACHAN_ADC1 STM32_DMA1_CHAN1 -# define DMACHAN_TIM2_CH3 STM32_DMA1_CHAN1 -# define DMACHAN_TIM17_CH1_1 STM32_DMA1_CHAN1 -# define DMACHAN_TIM17_UP_1 STM32_DMA1_CHAN1 - -# define DMACHAN_ADC2_1 STM32_DMA1_CHAN2 -# define DMACHAN_SPI1_RX_1 STM32_DMA1_CHAN2 -# define DMACHAN_USART3_TX STM32_DMA1_CHAN2 -# define DMACHAN_I2C1_TX_3 STM32_DMA1_CHAN4 -# define DMACHAN_TIM1_CH1 STM32_DMA1_CHAN2 -# define DMACHAN_TIM2_UP STM32_DMA1_CHAN2 -# define DMACHAN_TIM3_CH3 STM32_DMA1_CHAN2 -# define DMACHAN_HRTIM1_M STM32_DMA1_CHAN2 - -# define DMACHAN_SPI1_TX_1 STM32_DMA1_CHAN3 -# define DMACHAN_USART3_RX STM32_DMA1_CHAN3 -# define DMACHAN_I2C1_RX_2 STM32_DMA1_CHAN3 -# define DMACHAN_TIM3_CH4 STM32_DMA1_CHAN3 -# define DMACHAN_TIM3_UP STM32_DMA1_CHAN3 -# define DMACHAN_TIM6_UP STM32_DMA1_CHAN3 -# define DMACHAN_DAC1_CH1 STM32_DMA1_CHAN3 -# define DMACHAN_DAC16_CH1_1 STM32_DMA1_CHAN3 -# define DMACHAN_DAC16_UP_1 STM32_DMA1_CHAN3 -# define DMACHAN_HRTIM1_A STM32_DMA1_CHAN3 - -# define DMACHAN_ADC2_2 STM32_DMA1_CHAN4 -# define DMACHAN_SPI1_RX_2 STM32_DMA1_CHAN4 -# define DMACHAN_USART1_TX STM32_DMA1_CHAN4 -# define DMACHAN_I2C1_TX_3 STM32_DMA1_CHAN4 -# define DMACHAN_TIM1_CH4 STM32_DMA1_CHAN4 -# define DMACHAN_TIM1_TRIG STM32_DMA1_CHAN4 -# define DMACHAN_TIM1_COM STM32_DMA1_CHAN4 -# define DMACHAN_TIM7_UP STM32_DMA1_CHAN4 -# define DMACHAN_DAC2_CH2 STM32_DMA1_CHAN4 -# define DMACHAN_HRTIM1_B STM32_DMA1_CHAN4 - -# define DMACHAN_SPI1_TX_2 STM32_DMA1_CHAN5 -# define DMACHAN_USART1_RX STM32_DMA1_CHAN5 -# define DMACHAN_I2C1_RX_3 STM32_DMA1_CHAN5 -# define DMACHAN_TIM1_UP STM32_DMA1_CHAN5 -# define DMACHAN_TIM2_CH1 STM32_DMA1_CHAN5 -# define DMACHAN_DAC2_CH1 STM32_DMA1_CHAN5 -# define DMACHAN_TIM15_CH1 STM32_DMA1_CHAN5 -# define DMACHAN_TIM15_UP STM32_DMA1_CHAN5 -# define DMACHAN_TIM15_TRIG STM32_DMA1_CHAN5 -# define DMACHAN_TIM15_COM STM32_DMA1_CHAN5 -# define DMACHAN_HRTIM1_C STM32_DMA1_CHAN5 - -# define DMACHAN_SPI1_RX_3 STM32_DMA1_CHAN6 -# define DMACHAN_USART2_RX STM32_DMA1_CHAN6 -# define DMACHAN_I2C1_TX_1 STM32_DMA1_CHAN6 -# define DMACHAN_TIM1_CH3 STM32_DMA1_CHAN6 -# define DMACHAN_TIM3_CH1 STM32_DMA1_CHAN6 -# define DMACHAN_TIM3_TRIG STM32_DMA1_CHAN6 -# define DMACHAN_TIM16_CH1_2 STM32_DMA1_CHAN6 -# define DMACHAN_TIM16_UP_2 STM32_DMA1_CHAN6 -# define DMACHAN_HRTIM1_D STM32_DMA1_CHAN6 - -# define DMACHAN_SPI1_TX_3 STM32_DMA1_CHAN7 -# define DMACHAN_USART2_TX STM32_DMA1_CHAN7 -# define DMACHAN_I2C1_RX_1 STM32_DMA1_CHAN7 -# define DMACHAN_TIM2_CH2 STM32_DMA1_CHAN7 -# define DMACHAN_TIM2_CH4 STM32_DMA1_CHAN7 -# define DMACHAN_TIM17_CH1_2 STM32_DMA1_CHAN7 -# define DMACHAN_TIM17_UP_2 STM32_DMA1_CHAN7 -# define DMACHAN_HRTIM1_E STM32_DMA1_CHAN7 - #elif defined(CONFIG_STM32_STM32F37XX) # define DMACHAN_ADC1 STM32_DMA1_CHAN1 @@ -667,7 +598,7 @@ # define DMACHAN_SDADC3 STM32_DMA2_CHAN5 # define DMACHAN_TIM5_CH1 STM32_DMA2_CHAN5 -# define DMACHAN_TIM18_UP_2 STM32_DMA2_CHAN5 +# define DMACHAN_TIM18_UP_2 STM32_DMA2_CHAN5 # define DMACHAN_DAC2_CH1_2 STM32_DMA2_CHAN5 #else diff --git a/arch/arm/src/stm32/chip/stm32f33xxx_dma.h b/arch/arm/src/stm32/chip/stm32f33xxx_dma.h index c30bcb0472c..2642cf67724 100644 --- a/arch/arm/src/stm32/chip/stm32f33xxx_dma.h +++ b/arch/arm/src/stm32/chip/stm32f33xxx_dma.h @@ -317,8 +317,8 @@ #define DMACHAN_TIM3_UP STM32_DMA1_CHAN3 #define DMACHAN_TIM6_UP STM32_DMA1_CHAN3 #define DMACHAN_DAC1_CH1 STM32_DMA1_CHAN3 -#define DMACHAN_DAC16_CH1_1 STM32_DMA1_CHAN3 -#define DMACHAN_DAC16_UP_1 STM32_DMA1_CHAN3 +#define DMACHAN_TIM16_CH1_1 STM32_DMA1_CHAN3 +#define DMACHAN_TIM16_UP_1 STM32_DMA1_CHAN3 #define DMACHAN_HRTIM1_A STM32_DMA1_CHAN3 #define DMACHAN_ADC2_2 STM32_DMA1_CHAN4 @@ -329,7 +329,7 @@ #define DMACHAN_TIM1_TRIG STM32_DMA1_CHAN4 #define DMACHAN_TIM1_COM STM32_DMA1_CHAN4 #define DMACHAN_TIM7_UP STM32_DMA1_CHAN4 -#define DMACHAN_DAC2_CH2 STM32_DMA1_CHAN4 +#define DMACHAN_DAC1_CH2 STM32_DMA1_CHAN4 #define DMACHAN_HRTIM1_B STM32_DMA1_CHAN4 #define DMACHAN_SPI1_TX_2 STM32_DMA1_CHAN5 diff --git a/arch/arm/src/stm32/stm32_dac.c b/arch/arm/src/stm32/stm32_dac.c index 11a9d1cbb87..fabb9af336e 100644 --- a/arch/arm/src/stm32/stm32_dac.c +++ b/arch/arm/src/stm32/stm32_dac.c @@ -142,13 +142,23 @@ # endif #endif +#if defined(CONFIG_STM32_DAC1CH1_HRTIM_TRG1) || defined(CONFIG_STM32_DAC1CH1_HRTIM_TRG2) +# define DAC1CH1_HRTIM +#endif +#if defined(CONFIG_STM32_DAC1CH2_HRTIM_TRG1) || defined(CONFIG_STM32_DAC1CH2_HRTIM_TRG2) +# define DAC1CH2_HRTIM +#endif +#if defined(CONFIG_STM32_DAC2CH1_HRTIM_TRG3) +# define DAC2CH1_HRTIM +#endif + /* If DMA is selected, then a timer and output frequency must also be * provided to support the DMA transfer. The DMA transfer could be * supported by and EXTI trigger, but this feature is not currently * supported by the driver. */ -#ifdef CONFIG_STM32_DAC1CH1_DMA +#if defined(CONFIG_STM32_DAC1CH1_DMA) && !defined(DAC1CH1_HRTIM) # if !defined(CONFIG_STM32_DAC1CH1_TIMER) # warning "A timer number must be specificed in CONFIG_STM32_DAC1CH1_TIMER" # undef CONFIG_STM32_DAC1CH1_DMA @@ -160,7 +170,7 @@ # endif #endif -#ifdef CONFIG_STM32_DAC1CH2_DMA +#if defined(CONFIG_STM32_DAC1CH2_DMA) && !defined(DAC1CH2_HRTIM) # if !defined(CONFIG_STM32_DAC1CH2_TIMER) # warning "A timer number must be specificed in CONFIG_STM32_DAC1CH2_TIMER" # undef CONFIG_STM32_DAC1CH2_DMA @@ -172,7 +182,7 @@ # endif #endif -#ifdef CONFIG_STM32_DAC2CH1_DMA +#if defined(CONFIG_STM32_DAC2CH1_DMA) && !defined(DAC2CH1_HRTIM) # if !defined(CONFIG_STM32_DAC2CH1_TIMER) # warning "A timer number must be specificed in CONFIG_STM32_DAC2CH1_TIMER" # undef CONFIG_STM32_DAC2CH1_DMA @@ -190,19 +200,31 @@ #undef HAVE_DMA #if defined(CONFIG_STM32_DAC1CH1_DMA) || defined(CONFIG_STM32_DAC1CH2_DMA) || \ defined(CONFIG_STM32_DAC2CH1_DMA) -# if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) -# define HAVE_DMA 1 -# define DAC_DMA 2 -# define DAC1CH1_DMA_CHAN DMACHAN_DAC_CHAN1 -# define DAC1CH2_DMA_CHAN DMACHAN_DAC_CHAN2 -# define DAC2CH1_DMA_CHAN DMACHAN_DAC_CHAN2 -# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) || \ - defined(CONFIG_STM32_STM32F33XX) -# define HAVE_DMA 1 -# define DAC_DMA 1 -# define DAC1CH1_DMA_CHAN DMAMAP_DAC1 -# define DAC1CH2_DMA_CHAN DMAMAP_DAC1 -# define DAC2CH1_DMA_CHAN DMAMAP_DAC2 +# if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) || \ + defined(CONFIG_STM32_STM32F33XX) +# define HAVE_DMA 1 +# define DAC_DMA 2 +# ifdef CONFIG_STM32_DAC1CH1 +# define DAC1CH1_DMA_CHAN DMACHAN_DAC1_CH1 +# endif +# ifdef CONFIG_STM32_DAC1CH2 +# define DAC1CH2_DMA_CHAN DMACHAN_DAC1_CH2 +# endif +# ifdef CONFIG_STM32_DAC2CH1 +# define DAC2CH1_DMA_CHAN DMACHAN_DAC2_CH1 +# endif +# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +# define HAVE_DMA 1 +# define DAC_DMA 1 +# ifdef CONFIG_STM32_DAC1CH1 +# define DAC1CH1_DMA_CHAN DMAMAP_DAC1 +# endif +# ifdef CONFIG_STM32_DAC1CH1 +# define DAC1CH2_DMA_CHAN DMAMAP_DAC1 +# endif +# ifdef CONFIG_STM32_DAC1CH1 +# define DAC2CH1_DMA_CHAN DMAMAP_DAC2 +# endif # endif #endif @@ -212,12 +234,16 @@ * TSEL SOURCE DEVICES * ---- ----------------------- ------------------------------------- * 000 Timer 6 TRGO event ALL - * 001 Timer 3 TRGO event STM32 F1 Connectivity Line + * 001 Timer 3 TRGO event STM32 F1 Connectivity Line and STM32 F3 * Timer 8 TRGO event Other STM32 F1 and all STM32 F4 * 010 Timer 7 TRGO event ALL * 011 Timer 5 TRGO event ALL + * Timer 15 TRGO event STM32 F3 + * HRTIM1_DACTRG1 event STM32F33XX (DAC1 only) * 100 Timer 2 TRGO event ALL * 101 Timer 4 TRGO event ALL + * HRTIM1_DACTRG2 event STM32F33XX (DAC1 only) + * HRTIM1_DACTRG3 event STM32F33XX (DAC2 only) * 110 EXTI line9 ALL * 111 SWTRIG Software control ALL * @@ -233,7 +259,17 @@ #undef NEED_TIM4 #ifdef CONFIG_STM32_DAC1CH1_DMA -# if CONFIG_STM32_DAC1CH1_TIMER == 6 +# if defined(CONFIG_STM32_DAC1CH1_HRTIM_TRG1) +# ifndef CONFIG_STM32_HRTIM_DAC +# error "CONFIG_STM32_HRTIM_DAC required for DAC1CH1" +# endif +# define DAC1CH1_TSEL_VALUE DAC_CR_TSEL_HRT1TRG1 +# elif defined(CONFIG_STM32_DAC1CH1_HRTIM_TRG2) +# ifndef CONFIG_STM32_HRTIM_DAC +# error "CONFIG_STM32_HRTIM_DAC required for DAC1CH2" +# endif +# define DAC1CH1_TSEL_VALUE DAC_CR_TSEL_HRT1TRG2 +# elif CONFIG_STM32_DAC1CH1_TIMER == 6 # ifndef CONFIG_STM32_TIM6_DAC # error "CONFIG_STM32_TIM6_DAC required for DAC1CH1" # endif @@ -296,7 +332,17 @@ #endif #ifdef CONFIG_STM32_DAC1CH2_DMA -# if CONFIG_STM32_DAC1CH2_TIMER == 6 +# if defined(CONFIG_STM32_DAC1CH2_HRTIM_TRG1) +# ifndef CONFIG_STM32_HRTIM_DAC +# error "CONFIG_STM32_HRTIM_DAC required for DAC1CH2" +# endif +# define DAC1CH2_TSEL_VALUE DAC_CR_TSEL_HRT1TRG1 +# elif defined(CONFIG_STM32_DAC1CH2_HRTIM_TRG2) +# ifndef CONFIG_STM32_HRTIM_DAC +# error "CONFIG_STM32_HRTIM_DAC required for DAC1CH2" +# endif +# define DAC1CH2_TSEL_VALUE DAC_CR_TSEL_HRT1TRG2 +# elif CONFIG_STM32_DAC1CH2_TIMER == 6 # ifndef CONFIG_STM32_TIM6_DAC # error "CONFIG_STM32_TIM6_DAC required for DAC1CH2" # endif @@ -353,7 +399,12 @@ #endif #ifdef CONFIG_STM32_DAC2CH1_DMA -# if CONFIG_STM32_DAC2CH1_TIMER == 6 +# if defined(CONFIG_STM32_DAC2CH1_HRTIM_TRG3) +# ifndef CONFIG_STM32_HRTIM_DAC +# error "CONFIG_STM32_HRTIM_DAC required for DAC2CH1" +# endif +# define DAC2CH1_TSEL_VALUE DAC_CR_TSEL_HRT1TRG3 +# elif CONFIG_STM32_DAC2CH1_TIMER == 6 # ifndef CONFIG_STM32_TIM6_DAC # error "CONFIG_STM32_TIM6_DAC required for DAC2CH1" # endif @@ -409,8 +460,27 @@ # define DAC2CH1_TSEL_VALUE DAC_CR_TSEL_SW #endif -#ifndef CONFIG_STM32_DAC_DMA_BUFFER_SIZE -# define CONFIG_STM32_DAC_DMA_BUFFER_SIZE 256 +/* + * We need index which describes when HRTIM is selected as trigger. + * It will be used to skip timer configuration where needed. + */ + +#define TIM_INDEX_HRTIM 255 + +#if defined(DAC1_HRTIM) || defined(DAC2_HRTIM) || defined(DAC3_HRTIM) +# define HAVE_HRTIM +#endif + +#ifndef CONFIG_STM32_DAC1CH1_DMA_BUFFER_SIZE +# define CONFIG_STM32_DAC1CH1_DMA_BUFFER_SIZE 256 +#endif + +#ifndef CONFIG_STM32_DAC1CH2_DMA_BUFFER_SIZE +# define CONFIG_STM32_DAC1CH2_DMA_BUFFER_SIZE 256 +#endif + +#ifndef CONFIG_STM32_DAC2CH1_DMA_BUFFER_SIZE +# define CONFIG_STM32_DAC2CH1_DMA_BUFFER_SIZE 256 #endif /* Calculate timer divider values based upon DACn_TIMER_PCLK_FREQUENCY and @@ -462,10 +532,11 @@ struct stm32_chan_s uint32_t tsel; /* CR trigger select value */ #ifdef HAVE_DMA uint16_t dmachan; /* DMA channel needed by this DAC */ + uint16_t buffer_len; /* DMA buffer length */ DMA_HANDLE dma; /* Allocated DMA channel */ uint32_t tbase; /* Timer base address */ uint32_t tfrequency; /* Timer frequency */ - uint16_t dmabuffer[CONFIG_STM32_DAC_DMA_BUFFER_SIZE]; /* DMA transfer buffer */ + uint16_t *dmabuffer; /* DMA transfer buffer */ #endif }; @@ -521,6 +592,10 @@ static const struct dac_ops_s g_dacops = #ifdef CONFIG_STM32_DAC1CH1 /* Channel 1: DAC1 channel 1 */ +#ifdef CONFIG_STM32_DAC1CH1_DMA +uint16_t dac1ch1_buffer[CONFIG_STM32_DAC1CH1_DMA_BUFFER_SIZE]; +#endif + static struct stm32_chan_s g_dac1ch1priv = { .intf = 0, @@ -536,10 +611,19 @@ static struct stm32_chan_s g_dac1ch1priv = #ifdef CONFIG_STM32_DAC1CH1_DMA .hasdma = 1, .dmachan = DAC1CH1_DMA_CHAN, + .buffer_len = CONFIG_STM32_DAC1CH1_DMA_BUFFER_SIZE, + .dmabuffer = dac1ch1_buffer, +# ifdef DAC1CH1_HRTIM + .timer = TIM_INDEX_HRTIM, + .tsel = 0, + .tbase = 0, + .tfrequency = 0, +# else .timer = CONFIG_STM32_DAC1CH1_TIMER, .tsel = DAC1CH1_TSEL_VALUE, .tbase = DAC1CH1_TIMER_BASE, .tfrequency = CONFIG_STM32_DAC1CH1_TIMER_FREQUENCY, +# endif #endif }; @@ -554,19 +638,32 @@ static struct dac_dev_s g_dac1ch1dev = #ifdef CONFIG_STM32_DAC1CH2 /* Channel 2: DAC1 channel 2 */ +#ifdef CONFIG_STM32_DAC1CH2_DMA +uint16_t dac1ch2_buffer[CONFIG_STM32_DAC1CH2_DMA_BUFFER_SIZE]; +#endif + static struct stm32_chan_s g_dac1ch2priv = { .intf = 1, .pin = GPIO_DAC1_OUT2, .dro = STM32_DAC1_DHR12R2, .cr = STM32_DAC1_CR, -#ifdef CONFIG_STM32_DAC2_DMA +#ifdef CONFIG_STM32_DAC1CH2_DMA .hasdma = 1, .dmachan = DAC1CH2_DMA_CHAN, + .buffer_len = CONFIG_STM32_DAC1CH2_DMA_BUFFER_SIZE, + .dmabuffer = dac1ch2_buffer, +# ifdef DAC1CH2_HRTIM + .timer = TIM_INDEX_HRTIM, + .tsel = 0, + .tbase = 0, + .tfrequency = 0, +# else .timer = CONFIG_STM32_DAC1CH2_TIMER, .tsel = DAC1CH2_TSEL_VALUE, .tbase = DAC1CH2_TIMER_BASE, .tfrequency = CONFIG_STM32_DAC1CH2_TIMER_FREQUENCY, +# endif #endif }; @@ -584,6 +681,10 @@ static struct dac_dev_s g_dac1ch2dev = #ifdef CONFIG_STM32_DAC2CH1 /* Channel 3: DAC2 channel 1 */ +#ifdef CONFIG_STM32_DAC2CH1_DMA +uint16_t dac2ch1_buffer[CONFIG_STM32_DAC2CH1_DMA_BUFFER_SIZE]; +#endif + static struct stm32_chan_s g_dac2ch1priv = { .intf = 2, @@ -593,10 +694,19 @@ static struct stm32_chan_s g_dac2ch1priv = #ifdef CONFIG_STM32_DAC2CH1_DMA .hasdma = 1, .dmachan = DAC2CH1_DMA_CHAN, + .buffer_len = CONFIG_STM32_DAC2CH1_DMA_BUFFER_SIZE, + .dmabuffer = dac2ch1_buffer, +# ifdef DAC2CH1_HRTIM + .timer = TIM_INDEX_HRTIM, + .tsel = 0, + .tbase = 0, + .tfrequency = 0, +# else .timer = CONFIG_STM32_DAC2CH1_TIMER, .tsel = DAC2CH1_TSEL_VALUE, .tbase = DAC2CH1_TIMER_BASE, .tfrequency = CONFIG_STM32_DAC2CH1_TIMER_FREQUENCY, +# endif #endif }; @@ -888,7 +998,7 @@ static int dac_send(FAR struct dac_dev_s *dev, FAR struct dac_msg_s *msg) */ stm32_dmasetup(chan->dma, chan->dro, (uint32_t)chan->dmabuffer, - CONFIG_STM32_DAC_DMA_BUFFER_SIZE, DAC_DMA_CONTROL_WORD); + chan->buffer_len, DAC_DMA_CONTROL_WORD); /* Enable DMA */ @@ -907,10 +1017,13 @@ static int dac_send(FAR struct dac_dev_s *dev, FAR struct dac_msg_s *msg) dac_txdone(dev); } - /* Reset counters (generate an update) */ + /* Reset counters (generate an update). Only when timer is not HRTIM */ #ifdef HAVE_DMA - tim_modifyreg(chan, STM32_BTIM_EGR_OFFSET, 0, ATIM_EGR_UG); + if (chan->timer != TIM_INDEX_HRTIM) + { + tim_modifyreg(chan, STM32_BTIM_EGR_OFFSET, 0, ATIM_EGR_UG); + } #endif return OK; } @@ -958,6 +1071,17 @@ static int dac_timinit(FAR struct stm32_chan_s *chan) uint32_t regaddr; uint32_t setbits; + /* Do nothing if HRTIM is selected as trigger. + * All necessary configuration is done in the HRTIM driver. + */ + +#ifdef HAVE_HRTIM + if (chan->timer == TIM_INDEX_HRTIM) + { + return OK; + } +#endif + /* Configure the time base: Timer period, prescaler, clock division, * counter mode (up). */