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SAMV7-XULT: Enable I- and D-caches, correct polaty of LEDs

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This commit is contained in:
Gregory Nutt
2015-03-11 11:23:19 -06:00
parent e8e357cc1d
commit 508d96b571
5 changed files with 28 additions and 17 deletions
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arch/arm/src/armv7-m/nvic.h
+17
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@@ -662,6 +662,23 @@
# define NVIC_TCMCR_SZ_8MB (14 << NVIC_TCMCR_SZ_SHIFT)
# define NVIC_TCMCR_SZ_16MB (15 << NVIC_TCMCR_SZ_SHIFT)
/* AHBP Control Register (AHBPCR, Cortex-M7) */
#define NVIC_AHBPCR_EN (1 << 0) /* Bit 0: AHBP enable */
#define NVIC_AHBPCR_SZ_SHIFT (1) /* Bits 1-3: AHBP size */
#define NVIC_AHBPCR_SZ_MASK (7 << NVIC_AHBPCR_SZ_SHIFT)
# define NVIC_AHBPCR_SZ_DISABLED (0 << NVIC_AHBPCR_SZ_SHIFT)
# define NVIC_AHBPCR_SZ_64MB (1 << NVIC_AHBPCR_SZ_SHIFT)
# define NVIC_AHBPCR_SZ_128MB (2 << NVIC_AHBPCR_SZ_SHIFT)
# define NVIC_AHBPCR_SZ_256MB (3 << NVIC_AHBPCR_SZ_SHIFT)
# define NVIC_AHBPCR_SZ_512MB (4 << NVIC_AHBPCR_SZ_SHIFT)
/* L1 Cache Control Register (CACR, Cortex-M7) */
#define NVIC_CACR_SIWT (1 << 0) /* Bit 0: Shared cacheable-is-WT for data cache */
#define NVIC_CACR_ECCDIS (1 << 1) /* Bit 1: Enables ECC in the instruction and data cache */
#define NVIC_CACR_FORCEWT (1 << 2) /* Bit 2: Enables Force Write-Through in the data cache */
/********************************************************************************************
* Public Types
********************************************************************************************/
configs/samv71-xult/README.txt
+2 -2
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@@ -276,8 +276,8 @@ Configuration sub-directories
4. Performance-related Configuration settings:
# CONFIG_ARMV7M_ICACHE is not set : Can be enabled, not verified
# CONFIG_ARMV7M_DCACHE is not set : Can be enabled, not verified
CONFIG_ARMV7M_ICACHE=y : Instruction cache is enabled
CONFIG_ARMV7M_DCACHE=y : Data cache is enabled
# CONFIG_ARCH_FPU is not set : Can be enabled, not verified
# CONFIG_ARMV7M_ITCM is not set : Support not yet in place
# CONFIG_ARMV7M_DTCM is not set : Support not yet in place
configs/samv71-xult/nsh/defconfig
+4 -3
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@@ -120,8 +120,8 @@ CONFIG_ARCH_HAVE_DPFPU=y
#
CONFIG_ARMV7M_HAVE_ICACHE=y
CONFIG_ARMV7M_HAVE_DCACHE=y
# CONFIG_ARMV7M_ICACHE is not set
# CONFIG_ARMV7M_DCACHE is not set
CONFIG_ARMV7M_ICACHE=y
CONFIG_ARMV7M_DCACHE=y
CONFIG_ARMV7M_HAVE_ITCM=y
CONFIG_ARMV7M_HAVE_DTCM=y
# CONFIG_ARMV7M_ITCM is not set
@@ -255,7 +255,7 @@ CONFIG_ARCH_HAVE_RAMVECTORS=y
#
# Board Settings
#
CONFIG_BOARD_LOOPSPERMSEC=42445
CONFIG_BOARD_LOOPSPERMSEC=51262
# CONFIG_ARCH_CALIBRATION is not set
#
@@ -509,6 +509,7 @@ CONFIG_MCU_SERIAL=y
CONFIG_STANDARD_SERIAL=y
# CONFIG_SERIAL_IFLOWCONTROL is not set
# CONFIG_SERIAL_OFLOWCONTROL is not set
# CONFIG_SERIAL_TIOCSERGSTRUCT is not set
CONFIG_ARCH_HAVE_SERIAL_TERMIOS=y
# CONFIG_SERIAL_TERMIOS is not set
CONFIG_UART3_SERIAL_CONSOLE=y
configs/samv71-xult/src/sam_autoleds.c
+4 -11
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@@ -139,16 +139,13 @@ void board_led_initialize(void)
void board_led_on(int led)
{
bool led0on = false; /* High illuminates */
bool led1on = false; /* High illuminates */
switch (led)
{
case 0: /* LED_STARTED, LED_HEAPALLOCATE, LED_IRQSENABLED */
break;
case 1: /* LED_STACKCREATED */
led0on = true;
sam_gpiowrite(GPIO_LED0, false); /* Low illuminates */
break;
default:
@@ -156,12 +153,9 @@ void board_led_on(int led)
return;
case 3: /* LED_PANIC */
led1on = true;
sam_gpiowrite(GPIO_LED1, false); /* Low illuminates */
break;
}
sam_gpiowrite(GPIO_LED0, led0on);
sam_gpiowrite(GPIO_LED1, led1on);
}
/****************************************************************************
@@ -170,10 +164,9 @@ void board_led_on(int led)
void board_led_off(int led)
{
if (led != 2)
if (led == 3)
{
sam_gpiowrite(GPIO_LED0, false); /* High illuminates */
sam_gpiowrite(GPIO_LED1, false); /* High illuminates */
sam_gpiowrite(GPIO_LED1, true); /* High extinguishes */
}
}
configs/samv71-xult/src/sam_userleds.c
+1 -1
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@@ -101,7 +101,7 @@ void sam_setled(int led, bool ledon)
void sam_setleds(uint8_t ledset)
{
/* Hight illuminates */
/* Low illuminates */
sam_gpiowrite(GPIO_LED0, (ledset & BOARD_LED0_BIT) == 0);
sam_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) == 0);