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drivers/wireless: Run all wireless drivers through tools/nxstyle, correcting as many complaints as possible.

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This commit is contained in:
Gregory Nutt
2019-12-05 11:49:12 -06:00
parent febf226992
commit 504b0e8b5b
39 changed files with 514 additions and 385 deletions
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62
drivers/wireless/cc1101.c
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@@ -2,8 +2,7 @@
* drivers/wireless/cc1101.c
*
* Copyright (C) 2011 Uros Platise. All rights reserved.
*
* Authors: Uros Platise <uros.platise@isotel.eu>
* Author: Uros Platise <uros.platise@isotel.eu>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -122,7 +121,7 @@
#define CC1101_SPIFREQ_BURST 6500000 /* Hz, no delay */
#define CC1101_SPIFREQ_SINGLE 9000000 /* Hz, single access only - no delay */
#define CC1101_MCSM0_VALUE 0x1C
#define CC1101_MCSM0_VALUE 0x1c
/****************************************************************************
* Chipcon CC1101 Internal Registers
@@ -140,12 +139,12 @@
#define CC1101_PKTCTRL1 0x07 /* Packet automation control */
#define CC1101_PKTCTRL0 0x08 /* Packet automation control */
#define CC1101_ADDR 0x09 /* Device address */
#define CC1101_CHANNR 0x0A /* Channel number */
#define CC1101_FSCTRL1 0x0B /* Frequency synthesizer control */
#define CC1101_FSCTRL0 0x0C /* Frequency synthesizer control */
#define CC1101_FREQ2 0x0D /* Frequency control word, high byte */
#define CC1101_FREQ1 0x0E /* Frequency control word, middle byte */
#define CC1101_FREQ0 0x0F /* Frequency control word, low byte */
#define CC1101_CHANNR 0x0a /* Channel number */
#define CC1101_FSCTRL1 0x0b /* Frequency synthesizer control */
#define CC1101_FSCTRL0 0x0c /* Frequency synthesizer control */
#define CC1101_FREQ2 0x0d /* Frequency control word, high byte */
#define CC1101_FREQ1 0x0e /* Frequency control word, middle byte */
#define CC1101_FREQ0 0x0f /* Frequency control word, low byte */
#define CC1101_MDMCFG4 0x10 /* Modem configuration */
#define CC1101_MDMCFG3 0x11 /* Modem configuration */
#define CC1101_MDMCFG2 0x12 /* Modem configuration */
@@ -156,12 +155,12 @@
#define CC1101_MCSM1 0x17 /* Main Radio Cntrl State Machine config */
#define CC1101_MCSM0 0x18 /* Main Radio Cntrl State Machine config */
#define CC1101_FOCCFG 0x19 /* Frequency Offset Compensation config */
#define CC1101_BSCFG 0x1A /* Bit Synchronization configuration */
#define CC1101_AGCCTRL2 0x1B /* AGC control */
#define CC1101_AGCCTRL1 0x1C /* AGC control */
#define CC1101_AGCCTRL0 0x1D /* AGC control */
#define CC1101_WOREVT1 0x1E /* High byte Event 0 timeout */
#define CC1101_WOREVT0 0x1F /* Low byte Event 0 timeout */
#define CC1101_BSCFG 0x1a /* Bit Synchronization configuration */
#define CC1101_AGCCTRL2 0x1b /* AGC control */
#define CC1101_AGCCTRL1 0x1c /* AGC control */
#define CC1101_AGCCTRL0 0x1d /* AGC control */
#define CC1101_WOREVT1 0x1e /* High byte Event 0 timeout */
#define CC1101_WOREVT0 0x1f /* Low byte Event 0 timeout */
#define CC1101_WORCTRL 0x20 /* Wake On Radio control */
#define CC1101_FREND1 0x21 /* Front end RX configuration */
#define CC1101_FREND0 0x22 /* Front end TX configuration */
@@ -172,11 +171,11 @@
#define CC1101_RCCTRL1 0x27 /* RC oscillator configuration */
#define CC1101_RCCTRL0 0x28 /* RC oscillator configuration */
#define CC1101_FSTEST 0x29 /* Frequency synthesizer cal control */
#define CC1101_PTEST 0x2A /* Production test */
#define CC1101_AGCTEST 0x2B /* AGC test */
#define CC1101_TEST2 0x2C /* Various test settings */
#define CC1101_TEST1 0x2D /* Various test settings */
#define CC1101_TEST0 0x2E /* Various test settings */
#define CC1101_PTEST 0x2a /* Production test */
#define CC1101_AGCTEST 0x2b /* AGC test */
#define CC1101_TEST2 0x2c /* Various test settings */
#define CC1101_TEST1 0x2d /* Various test settings */
#define CC1101_TEST0 0x2e /* Various test settings */
/* Status registers */
@@ -230,6 +229,7 @@
#define CC1101_MCSM0_XOSC_FORCE_ON 0x01
/* Chip Status Byte */
/* Bit fields in the chip status byte */
#define CC1101_STATUS_CHIP_RDYn_BM 0x80
@@ -260,12 +260,12 @@
#define CC1101_MARCSTATE_REGON 0x07
#define CC1101_MARCSTATE_STARTCAL 0x08
#define CC1101_MARCSTATE_BWBOOST 0x09
#define CC1101_MARCSTATE_FS_LOCK 0x0A
#define CC1101_MARCSTATE_IFADCON 0x0B
#define CC1101_MARCSTATE_ENDCAL 0x0C
#define CC1101_MARCSTATE_RX 0x0D
#define CC1101_MARCSTATE_RX_END 0x0E
#define CC1101_MARCSTATE_RX_RST 0x0F
#define CC1101_MARCSTATE_FS_LOCK 0x0a
#define CC1101_MARCSTATE_IFADCON 0x0b
#define CC1101_MARCSTATE_ENDCAL 0x0c
#define CC1101_MARCSTATE_RX 0x0d
#define CC1101_MARCSTATE_RX_END 0x0e
#define CC1101_MARCSTATE_RX_RST 0x0f
#define CC1101_MARCSTATE_TXRX_SWITCH 0x10
#define CC1101_MARCSTATE_RXFIFO_OVERFLOW 0x11
#define CC1101_MARCSTATE_FSTXON 0x12
@@ -434,7 +434,9 @@ static int cc1101_file_close(FAR struct file *filep)
}
dev->ops.irq(dev, false);
// nrf24l01_changestate(dev, ST_POWER_DOWN);
#if 0
nrf24l01_changestate(dev, ST_POWER_DOWN);
#endif
dev->nopens--;
nxsem_post(&dev->devsem);
@@ -970,13 +972,14 @@ void cc1101_setpacketctrl(struct cc1101_dev_s *dev)
values[0] = 0x07; /* No time-out */
values[1] = 0x03; /* Clear channel if RSSI < thr && !receiving;
* TX -> RX, RX -> RX: 0x3F */
* TX -> RX, RX -> RX: 0x3f */
values[2] =
CC1101_MCSM0_VALUE; /* Calibrate on IDLE -> RX/TX, OSC Timeout = ~500 us
* TODO: has XOSC_FORCE_ON */
cc1101_access(dev, CC1101_MCSM2, values, -3);
/* Wake-On Radio Control */
/* Not used yet. */
/* WOREVT1:WOREVT0 - 16-bit timeout register */
@@ -1560,7 +1563,8 @@ void cc1101_isr_process(FAR void *arg)
case CC1101_RECV:
{
uint8_t buf[CC1101_FIFO_SIZE], len;
uint8_t buf[CC1101_FIFO_SIZE];
uint8_t len;
memset(buf, 0, sizeof(buf));
len = cc1101_read(dev, buf, sizeof(buf));