Fix Cortex-M3 nested interrupt hard fault

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3119 42af7a65-404d-4744-a932-0658087f49c3

ChangeLog

@@ -1340,5 +1340,11 @@
 	* sched/timer_settime.c - Fix an error in set-up of one-shot timer.  It was
 	  using the repititive timer value (which is zero in the one-shot case,
 	  always resulting in a 10Ms timer!  Found and fixed by Wilton Tong.
+	* arch/arm/src/lpc17xx/lpc17_vector.S, stm32/stm32_vector.S, lm3s/lm3s_vector.S,
+	  sam3u/sam3u_vector.S -- Fixed a hard fault problem that can occur if certain
+	  types of interrupts are pending at the time another interrupt returns
+	  (SYSTICK).  This has not been verified on all plaform, but is a critical
+	  fixed that is needed by all Cortex-M3 NuttX users.
+
 
 

Documentation/NuttX.html

@@ -8,7 +8,7 @@
   <tr align="center" bgcolor="#e4e4e4">
     <td>
       <h1><big><font color="#3c34ec"><i>NuttX RTOS</i></font></big></h1>
-      <p>Last Updated: November 17, 2010</p>
+      <p>Last Updated: November 19, 2010</p>
     </td>
   </tr>
 </table>
@@ -1989,6 +1989,11 @@ nuttx-5.14 2010-xx-xx Gregory Nutt &lt;spudmonkey@racsa.co.cr&gt;
 	* sched/timer_settime.c - Fix an error in set-up of one-shot timer.  It was
 	  using the repititive timer value (which is zero in the one-shot case,
 	  always resulting in a 10Ms timer!  Found and fixed by Wilton Tong.
+	* arch/arm/src/lpc17xx/lpc17_vector.S, stm32/stm32_vector.S, lm3s/lm3s_vector.S,
+	  sam3u/sam3u_vector.S -- Fixed a hard fault problem that can occur if certain
+	  types of interrupts are pending at the time another interrupt returns
+	  (SYSTICK).  This has not been verified on all plaform, but is a critical
+	  fixed that is needed by all Cortex-M3 NuttX users.
 
 pascal-2.1 2010-xx-xx Gregory Nutt &lt;spudmonkey@racsa.co.cr&gt;
 

arch/arm/include/cortexm3/irq.h

@@ -244,7 +244,7 @@ static inline void setbasepri(uint32_t basepri)
       : "memory");
 }
 
-/* Get IPSR */
+/* Get/set IPSR */
 
 static inline uint32_t getipsr(void)
 {
@@ -258,6 +258,16 @@ static inline uint32_t getipsr(void)
   return ipsr;
 }
 
+static inline void setipsr(uint32_t ipsr)
+{
+  __asm__ __volatile__
+    (
+      "\tmsr ipsr, %0\n"
+      :
+      : "r" (ipsr)
+      : "memory");
+}
+
 /* SVC system call */
 
 static inline void svcall(uint32_t cmd, uint32_t arg)

arch/arm/src/lm3s/lm3s_vectors.S

@@ -622,17 +622,18 @@ lm3s_irqcommon:
 2:
 	msr	msp, r1			/* Recover the return MSP value */
 
-	/* Do we need to restore interrupts? */
+	/* Restore the interrupt state.  Preload r14 with the special return
+	 * value first (so that the return actually occurs with interrupts
+	 * still disabled).
+	 */
 
-	tst	r3, #1			/* PRIMASK bit 1=1 means that interrupts are masked */
+	ldr	r14, =EXC_RETURN	/* Load the special value */
-	bne	3f
+	msr	primask, r3		/* Restore interrupts */
-	cpsie	i			/* Restore interrupts */
 
 	/* Always return with R14 containing the special value that will: (1)
 	 * return to thread mode, and (2) continue to use the MSP
 	 */
-3:
+
-	ldr	r14, =EXC_RETURN	/* Load the special value */
 	bx	r14			/* And return */
 	.size	handlers, .-handlers
 

arch/arm/src/lpc17xx/lpc17_ethernet.c

@@ -1124,7 +1124,6 @@ static int lpc17_interrupt(int irq, void *context)
           lpc17_putreg(ETH_INT_WKUP, LPC17_ETH_INTCLR);
           EMAC_STAT(priv, wol);
 #         warning "Missing logic"
-          goto intexit;
         }
       else
 #endif

arch/arm/src/lpc17xx/lpc17_vectors.S

@@ -295,17 +295,18 @@ lpc17_common:
 2:
 	msr		msp, r1					/* Recover the return MSP value */
 
-	/* Do we need to restore interrupts? Why not just: msr primask, r3 */
+	/* Restore the interrupt state.  Preload r14 with the special return
+	 * value first (so that the return actually occurs with interrupts
+	 * still disabled).
+	 */
 
-	tst		r3, #1					/* PRIMASK bit 1=1 means that interrupts are masked */
+	ldr		r14, =EXC_RETURN		/* Load the special value */
-	bne		3f
+	msr		primask, r3				/* Restore interrupts */
-	cpsie	i						/* Restore interrupts */
 
 	/* Always return with R14 containing the special value that will: (1)
 	 * return to thread mode, and (2) continue to use the MSP
 	 */
-3:
+
-	ldr		r14, =EXC_RETURN		/* Load the special value */
 	bx		r14						/* And return */
 	.size	handlers, .-handlers
 

arch/arm/src/sam3u/sam3u_vectors.S

@@ -286,17 +286,18 @@ sam3u_common:
 2:
 	msr	msp, r1					/* Recover the return MSP value */
 
-	/* Do we need to restore interrupts? */
+	/* Restore the interrupt state.  Preload r14 with the special return
+	 * value first (so that the return actually occurs with interrupts
+	 * still disabled).
+	 */
 
-	tst		r3, #1					/* PRIMASK bit 1=1 means that interrupts are masked */
+	ldr		r14, =EXC_RETURN		/* Load the special value */
-	bne		3f
+	msr		primask, r3				/* Restore interrupts */
-	cpsie	i						/* Restore interrupts */
 
 	/* Always return with R14 containing the special value that will: (1)
 	 * return to thread mode, and (2) continue to use the MSP
 	 */
-3:
+
-	ldr		r14, =EXC_RETURN		/* Load the special value */
 	bx		r14						/* And return */
 	.size	handlers, .-handlers
 

arch/arm/src/stm32/stm32_vectors.S

@@ -478,17 +478,18 @@ stm32_common:
 2:
 	msr		msp, r1					/* Recover the return MSP value */
 
-	/* Do we need to restore interrupts? */
+	/* Restore the interrupt state.  Preload r14 with the special return
+	 * value first (so that the return actually occurs with interrupts
+	 * still disabled).
+	 */
 
-	tst		r3, #1					/* PRIMASK bit 1=1 means that interrupts are masked */
+	ldr		r14, =EXC_RETURN		/* Load the special value */
-	bne		3f
+	msr		primask, r3				/* Restore interrupts */
-	cpsie	i						/* Restore interrupts */
 
 	/* Always return with R14 containing the special value that will: (1)
 	 * return to thread mode, and (2) continue to use the MSP
 	 */
-3:
+
-	ldr		r14, =EXC_RETURN		/* Load the special value */
 	bx		r14						/* And return */
 	.size	handlers, .-handlers