diff --git a/arch/mips/src/pic32mx/pic32mx-config.h b/arch/mips/src/pic32mx/pic32mx-config.h index 58b44017f8e..4ef88508d3c 100644 --- a/arch/mips/src/pic32mx/pic32mx-config.h +++ b/arch/mips/src/pic32mx/pic32mx-config.h @@ -729,6 +729,18 @@ /* DEVCFG1 */ +#ifdef BOARD_SOSC_ENABLE +# define CONFIG_PIC32MX_FSOSCEN DEVCFG1_FSOSCEN +#else +# define CONFIG_PIC32MX_FSOSCEN 0 +#endif + +#ifdef BOARD_SOSC_IESO +# define CONFIG_PIC32MX_IESO DEVCFG1_IESO +#else +# define CONFIG_PIC32MX_IESO 0 +#endif + #undef CONFIG_PIC32MX_PBDIV #if BOARD_PBDIV == 1 # define CONFIG_PIC32MX_PBDIV DEVCFG1_FPBDIV_DIV1 @@ -742,6 +754,30 @@ # error "Unsupported BOARD_PBDIV" #endif +#undef CONFIG_PIC32MX_POSCMOD +#if defined(BOARD_POSC_ECMODE) +# define CONFIG_PIC32MX_POSCMOD DEVCFG1_POSCMOD_EC +#elif defined(BOARD_POSC_XTMODE) +# define CONFIG_PIC32MX_POSCMOD DEVCFG1_POSCMOD_XT +#elif defined(BOARD_POSC_HSMODE) +# define CONFIG_PIC32MX_POSCMOD DEVCFG1_POSCMOD_HS +#elif defined(BOARD_POSC_DISABLED) +# define CONFIG_PIC32MX_POSCMOD DEVCFG1_POSCMOD_DIS +#else +# error "Unknown board POSC mode" +#endif + +#undef CONFIG_PIC32MX_FCKSM +#if defined(BOARD_POSC_SWITCH) +# if defined(BOARD_POSC_FSCM) +# define CONFIG_PIC32MX_FCKSM DEVCFG1_FCKSM_BOTH +# else +# define CONFIG_PIC32MX_FCKSM DEVCFG1_FCKSM_CSONLY +# endif +#else +# define CONFIG_PIC32MX_FCKSM DEVCFG1_FCKSM_NONE +#endif + #undef CONFIG_PIC32MX_WDPS #if BOARD_WD_PRESCALER == 1 # define CONFIG_PIC32MX_WDPS DEVCFG1_WDTPS_1 diff --git a/arch/mips/src/pic32mx/pic32mx-head.S b/arch/mips/src/pic32mx/pic32mx-head.S index a0a77579003..9d610aedd76 100644 --- a/arch/mips/src/pic32mx/pic32mx-head.S +++ b/arch/mips/src/pic32mx/pic32mx-head.S @@ -610,8 +610,9 @@ devconfig2: DEVCFG2_UNUSED devconfig1: - .long DEVCFG1_FNOSC_POSCPLL | DEVCFG1_POSCMOD_HS | \ - CONFIG_PIC32MX_PBDIV | DEVCFG1_FCKSM_NONE | \ + .long DEVCFG1_FNOSC_POSCPLL | CONFIG_PIC32MX_FSOSCEN | \ + CONFIG_PIC32MX_IESO | CONFIG_PIC32MX_POSCMOD | \ + CONFIG_PIC32MX_PBDIV | CONFIG_PIC32MX_FCKSM | \ CONFIG_PIC32MX_WDENABLE | DEVCFG1_UNUSED devconfig0: