diff --git a/arch/arm/src/armv7-a/arm_allocpage.c b/arch/arm/src/armv7-a/arm_allocpage.c index b5c2a7e31b0..ae2a4fbdb35 100644 --- a/arch/arm/src/armv7-a/arm_allocpage.c +++ b/arch/arm/src/armv7-a/arm_allocpage.c @@ -50,11 +50,11 @@ typedef uint32_t pgndx_t; #endif #if PG_POOL_MAXL1NDX < 256 -typedef uint8_t L1ndx_t; +typedef uint8_t l1ndx_t; #elif PG_POOL_MAXL1NDX < 65536 -typedef uint16_t L1ndx_t; +typedef uint16_t l1ndx_t; #else -typedef uint32_t L1ndx_t; +typedef uint32_t l1ndx_t; #endif /**************************************************************************** @@ -79,7 +79,7 @@ static pgndx_t g_pgndx; * index, and holds another index to the mapped virtual page. */ -static L1ndx_t g_ptemap[CONFIG_PAGING_NPPAGED]; +static l1ndx_t g_ptemap[CONFIG_PAGING_NPPAGED]; /* The contents of g_ptemap[] are not valid until g_pgndx has wrapped at * least one time. diff --git a/arch/arm/src/armv7-a/cp15_cacheops.h b/arch/arm/src/armv7-a/cp15_cacheops.h index 855588ce992..355adf3d6f2 100644 --- a/arch/arm/src/armv7-a/cp15_cacheops.h +++ b/arch/arm/src/armv7-a/cp15_cacheops.h @@ -41,10 +41,10 @@ /* References: * - * "Cortex-A5™ MPCore, Technical Reference Manual", Revision: r0p1, - * Copyright © 2010 ARM. All rights reserved. ARM DDI 0434B (ID101810) - * "ARM® Architecture Reference Manual, ARMv7-A and ARMv7-R edition", - * Copyright © 1996-1998, 2000, 2004-2012 ARM. + * "Cortex-A5 MPCore, Technical Reference Manual", Revision: r0p1, + * Copyright 2010 ARM. All rights reserved. ARM DDI 0434B (ID101810) + * "ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition", + * Copyright 1996-1998, 2000, 2004-2012 ARM. * All rights reserved. ARM DDI 0406C.b (ID072512) */ @@ -67,7 +67,7 @@ /* CP15 Registers ***********************************************************/ -/* Reference: Cortex-A5™ MPCore +/* Reference: Cortex-A5 MPCore * Paragraph 4.1.5, "Cache Operations Registers." * * Terms: @@ -215,11 +215,11 @@ * ****************************************************************************/ - .macro cp15_enable_dcache, tmp - mrc p15, 0, \tmp, c1, c0, 0 /* Read SCTLR */ - orr \tmp, \tmp, #(0x1 << 2) /* Enable D cache */ - mcr p15, 0, \tmp, c1, c0, 0 /* Update the SCTLR */ - .endm +.macro cp15_enable_dcache, tmp + mrc p15, 0, \tmp, c1, c0, 0 /* Read SCTLR */ + orr \tmp, \tmp, #(0x1 << 2) /* Enable D cache */ + mcr p15, 0, \tmp, c1, c0, 0 /* Update the SCTLR */ +.endm /**************************************************************************** * Name: cp15_disable_dcache @@ -235,11 +235,11 @@ * ****************************************************************************/ - .macro cp15_disable_dcache, tmp - mrc p15, 0, \tmp, c1, c0, 0 /* Read SCTLR */ - bic \tmp, \tmp, #(0x1 << 2) /* Disable D cache */ - mcr p15, 0, \tmp, c1, c0, 0 /* Update the SCTLR */ - .endm +.macro cp15_disable_dcache, tmp + mrc p15, 0, \tmp, c1, c0, 0 /* Read SCTLR */ + bic \tmp, \tmp, #(0x1 << 2) /* Disable D cache */ + mcr p15, 0, \tmp, c1, c0, 0 /* Update the SCTLR */ +.endm /**************************************************************************** * Name: cp15_enable_icache @@ -255,11 +255,11 @@ * ****************************************************************************/ - .macro cp15_enable_icache, tmp - mrc p15, 0, \tmp, c1, c0, 0 /* Read SCTLR */ - orr \tmp, \tmp, #(0x1 << 12) /* Enable I cache */ - mcr p15, 0, \tmp, c1, c0, 0 /* Update the SCTLR */ - .endm +.macro cp15_enable_icache, tmp + mrc p15, 0, \tmp, c1, c0, 0 /* Read SCTLR */ + orr \tmp, \tmp, #(0x1 << 12) /* Enable I cache */ + mcr p15, 0, \tmp, c1, c0, 0 /* Update the SCTLR */ +.endm /**************************************************************************** * Name: cp15_disable_icache @@ -275,11 +275,11 @@ * ****************************************************************************/ - .macro cp15_disable_icache, tmp - mrc p15, 0, \tmp, c1, c0, 0 /* Read SCTLR */ - bic \tmp, \tmp, #(0x1 << 12) /* Disable I cache */ - mcr p15, 0, \tmp, c1, c0, 0 /* Update the SCTLR */ - .endm +.macro cp15_disable_icache, tmp + mrc p15, 0, \tmp, c1, c0, 0 /* Read SCTLR */ + bic \tmp, \tmp, #(0x1 << 12) /* Disable I cache */ + mcr p15, 0, \tmp, c1, c0, 0 /* Update the SCTLR */ +.endm /**************************************************************************** * Name: cp15_invalidate_icache_inner_sharable @@ -295,10 +295,10 @@ * ****************************************************************************/ - .macro cp15_invalidate_icache_inner_sharable, tmp - mov \tmp, #0 - mrc p15, 0, \tmp, c7, c1, 0 /* ICIALLUIS */ - .endm +.macro cp15_invalidate_icache_inner_sharable, tmp + mov \tmp, #0 + mrc p15, 0, \tmp, c7, c1, 0 /* ICIALLUIS */ +.endm /**************************************************************************** * Name: cp15_invalidate_btb_inner_sharable @@ -314,10 +314,10 @@ * ****************************************************************************/ - .macro cp15_invalidate_btb_inner_sharable, tmp - mov \tmp, #0 - mrc p15, 0, \tmp, c7, c1, 6 /* BPIALLIS */ - .endm +.macro cp15_invalidate_btb_inner_sharable, tmp + mov \tmp, #0 + mrc p15, 0, \tmp, c7, c1, 6 /* BPIALLIS */ +.endm /**************************************************************************** * Name: cp15_invalidate_icache @@ -334,10 +334,10 @@ * ****************************************************************************/ - .macro cp15_invalidate_icache, tmp - mov \tmp, #0 - mrc p15, 0, \tmp, c7, c5, 0 /* ICIALLU */ - .endm +.macro cp15_invalidate_icache, tmp + mov \tmp, #0 + mrc p15, 0, \tmp, c7, c5, 0 /* ICIALLU */ +.endm /**************************************************************************** * Name: cp15_invalidate_icache_bymva @@ -353,9 +353,9 @@ * ****************************************************************************/ - .macro cp15_invalidate_icache_bymva, va - mrc p15, 0, \va, c7, c5, 1 /* ICIMVAU */ - .endm +.macro cp15_invalidate_icache_bymva, va + mrc p15, 0, \va, c7, c5, 1 /* ICIMVAU */ +.endm /**************************************************************************** * Name: cp15_flush_btb @@ -371,10 +371,10 @@ * ****************************************************************************/ - .macro cp15_flush_btb, tmp - mov \tmp, #0 - mrc p15, 0, \tmp, c7, c5, 6 /* BPIALL */ - .endm +.macro cp15_flush_btb, tmp + mov \tmp, #0 + mrc p15, 0, \tmp, c7, c5, 6 /* BPIALL */ +.endm /**************************************************************************** * Name: cp15_flush_btb_bymva @@ -390,10 +390,10 @@ * ****************************************************************************/ - .macro cp15_flush_btb_bymva, tmp - mov \tmp, #0 - mrc p15, 0, \tmp, c7, c5, 7 /* BPIMVA */ - .endm +.macro cp15_flush_btb_bymva, tmp + mov \tmp, #0 + mrc p15, 0, \tmp, c7, c5, 7 /* BPIMVA */ +.endm /**************************************************************************** * Name: cp15_invalidate_dcacheline_bymva @@ -409,9 +409,9 @@ * ****************************************************************************/ - .macro cp15_invalidate_dcacheline_bymva, va - mrc p15, 0, \va, c7, c6, 1 /* DCIMVAC */ - .endm +.macro cp15_invalidate_dcacheline_bymva, va + mrc p15, 0, \va, c7, c6, 1 /* DCIMVAC */ +.endm /**************************************************************************** * Name: cp15_invalidate_dcacheline_bysetway @@ -427,9 +427,9 @@ * ****************************************************************************/ - .macro cp15_invalidate_dcacheline_bysetway, setway - mrc p15, 0, \setway, c7, c6, 2 /* DCISW */ - .endm +.macro cp15_invalidate_dcacheline_bysetway, setway + mrc p15, 0, \setway, c7, c6, 2 /* DCISW */ +.endm /**************************************************************************** * Name: cp15_clean_dcache_bymva @@ -445,9 +445,9 @@ * ****************************************************************************/ - .macro cp15_clean_dcache_bymva, va - mrc p15, 0, \va, c7, c10, 1 /* DCCMVAC */ - .endm +.macro cp15_clean_dcache_bymva, va + mrc p15, 0, \va, c7, c10, 1 /* DCCMVAC */ +.endm /**************************************************************************** * Name: cp15_clean_dcache_bysetway @@ -463,9 +463,9 @@ * ****************************************************************************/ - .macro cp15_clean_dcache_bysetway, setway - mrc p15, 0, \setway, c7, c10, 2 /* DCCSW */ - .endm +.macro cp15_clean_dcache_bysetway, setway + mrc p15, 0, \setway, c7, c10, 2 /* DCCSW */ +.endm /**************************************************************************** * Name: cp15_clean_ucache_bymva @@ -481,9 +481,9 @@ * ****************************************************************************/ - .macro cp15_clean_ucache_bymva, setway - mrc p15, 0, \setway, c7, c11, 1 /* DCCMVAU */ - .endm +.macro cp15_clean_ucache_bymva, setway + mrc p15, 0, \setway, c7, c11, 1 /* DCCMVAU */ +.endm /**************************************************************************** * Name: cp15_cleaninvalidate_dcacheline_bymva @@ -499,9 +499,9 @@ * ****************************************************************************/ - .macro cp15_cleaninvalidate_dcacheline_bymva, va - mrc p15, 0, \va, c7, c14, 1 /* DCCIMVAC */ - .endm +.macro cp15_cleaninvalidate_dcacheline_bymva, va + mrc p15, 0, \va, c7, c14, 1 /* DCCIMVAC */ +.endm /**************************************************************************** * Name: cp15_cleaninvalidate_dcacheline @@ -517,9 +517,9 @@ * ****************************************************************************/ - .macro cp15_cleaninvalidate_dcacheline, setway - mrc p15, 0, \setway, c7, c14, 2 /* DCCISW */ - .endm +.macro cp15_cleaninvalidate_dcacheline, setway + mrc p15, 0, \setway, c7, c14, 2 /* DCCISW */ +.endm #endif /* __ASSEMBLY__ */ diff --git a/arch/arm/src/armv7-a/sctlr.h b/arch/arm/src/armv7-a/sctlr.h index 83dcd7321f6..fb1c666a88e 100644 --- a/arch/arm/src/armv7-a/sctlr.h +++ b/arch/arm/src/armv7-a/sctlr.h @@ -19,11 +19,11 @@ ****************************************************************************/ /* References: - * "Cortex-A5™ MPCore, Technical Reference Manual", - * Revision: r0p1, Copyright © 2010 ARM. + * "Cortex-A5 MPCore, Technical Reference Manual", + * Revision: r0p1, Copyright 2010 ARM. * All rights reserved. ARM DDI 0434B (ID101810) - * "ARM® Architecture Reference Manual, ARMv7-A and ARMv7-R edition", - * Copyright © 1996-1998, 2000, 2004-2012 ARM. + * "ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition", + * Copyright 1996-1998, 2000, 2004-2012 ARM. * All rights reserved. ARM DDI 0406C.b (ID072512) */ @@ -38,7 +38,7 @@ * Pre-processor Definitions ****************************************************************************/ -/* Reference: Cortex-A5™ MPCore Paragraph 4.2, "Register summary." */ +/* Reference: Cortex-A5 MPCore Paragraph 4.2, "Register summary." */ /* Main ID Register (MIDR) */ @@ -291,27 +291,27 @@ /* Get the device ID */ - .macro cp15_rdid, id - mrc p15, 0, \id, c0, c0, 0 - .endm +.macro cp15_rdid, id + mrc p15, 0, \id, c0, c0, 0 +.endm /* Read/write the system control register (SCTLR) */ - .macro cp15_rdsctlr, sctlr - mrc p15, 0, \sctlr, c1, c0, 0 - .endm +.macro cp15_rdsctlr, sctlr + mrc p15, 0, \sctlr, c1, c0, 0 +.endm - .macro cp15_wrsctlr, sctlr - mcr p15, 0, \sctlr, c1, c0, 0 - nop - nop - nop - nop - nop - nop - nop - nop - .endm +.macro cp15_wrsctlr, sctlr + mcr p15, 0, \sctlr, c1, c0, 0 + nop + nop + nop + nop + nop + nop + nop + nop +.endm #endif /* __ASSEMBLY__ */ /**************************************************************************** diff --git a/arch/arm/src/armv7-r/cp15_cacheops.h b/arch/arm/src/armv7-r/cp15_cacheops.h index 5b439cf0498..e69250138f6 100644 --- a/arch/arm/src/armv7-r/cp15_cacheops.h +++ b/arch/arm/src/armv7-r/cp15_cacheops.h @@ -41,8 +41,8 @@ /* References: * - * "ARM® Architecture Reference Manual, ARMv7-A and ARMv7-R edition", - * Copyright © 1996-1998, 2000, 2004-2012 ARM. All rights reserved. + * "ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition", + * Copyright 1996-1998, 2000, 2004-2012 ARM. All rights reserved. * ARM DDI 0406C.c (ID051414) */ @@ -222,11 +222,11 @@ * ****************************************************************************/ - .macro cp15_enable_dcache, tmp - mrc p15, 0, \tmp, c1, c0, 0 /* Read SCTLR */ - orr \tmp, \tmp, #(0x1 << 2) /* Enable D cache */ - mcr p15, 0, \tmp, c1, c0, 0 /* Update the SCTLR */ - .endm +.macro cp15_enable_dcache, tmp + mrc p15, 0, \tmp, c1, c0, 0 /* Read SCTLR */ + orr \tmp, \tmp, #(0x1 << 2) /* Enable D cache */ + mcr p15, 0, \tmp, c1, c0, 0 /* Update the SCTLR */ +.endm /**************************************************************************** * Name: cp15_disable_dcache @@ -242,11 +242,11 @@ * ****************************************************************************/ - .macro cp15_disable_dcache, tmp - mrc p15, 0, \tmp, c1, c0, 0 /* Read SCTLR */ - bic \tmp, \tmp, #(0x1 << 2) /* Disable D cache */ - mcr p15, 0, \tmp, c1, c0, 0 /* Update the SCTLR */ - .endm +.macro cp15_disable_dcache, tmp + mrc p15, 0, \tmp, c1, c0, 0 /* Read SCTLR */ + bic \tmp, \tmp, #(0x1 << 2) /* Disable D cache */ + mcr p15, 0, \tmp, c1, c0, 0 /* Update the SCTLR */ +.endm /**************************************************************************** * Name: cp15_enable_icache @@ -262,11 +262,11 @@ * ****************************************************************************/ - .macro cp15_enable_icache, tmp - mrc p15, 0, \tmp, c1, c0, 0 /* Read SCTLR */ - orr \tmp, \tmp, #(0x1 << 12) /* Enable I cache */ - mcr p15, 0, \tmp, c1, c0, 0 /* Update the SCTLR */ - .endm +.macro cp15_enable_icache, tmp + mrc p15, 0, \tmp, c1, c0, 0 /* Read SCTLR */ + orr \tmp, \tmp, #(0x1 << 12) /* Enable I cache */ + mcr p15, 0, \tmp, c1, c0, 0 /* Update the SCTLR */ +.endm /**************************************************************************** * Name: cp15_disable_icache @@ -282,11 +282,11 @@ * ****************************************************************************/ - .macro cp15_disable_icache, tmp - mrc p15, 0, \tmp, c1, c0, 0 /* Read SCTLR */ - bic \tmp, \tmp, #(0x1 << 12) /* Disable I cache */ - mcr p15, 0, \tmp, c1, c0, 0 /* Update the SCTLR */ - .endm +.macro cp15_disable_icache, tmp + mrc p15, 0, \tmp, c1, c0, 0 /* Read SCTLR */ + bic \tmp, \tmp, #(0x1 << 12) /* Disable I cache */ + mcr p15, 0, \tmp, c1, c0, 0 /* Update the SCTLR */ +.endm /**************************************************************************** * Name: cp15_invalidate_icache_inner_sharable @@ -302,10 +302,10 @@ * ****************************************************************************/ - .macro cp15_invalidate_icache_inner_sharable, tmp - mov \tmp, #0 - mrc p15, 0, \tmp, c7, c1, 0 /* ICIALLUIS */ - .endm +.macro cp15_invalidate_icache_inner_sharable, tmp + mov \tmp, #0 + mrc p15, 0, \tmp, c7, c1, 0 /* ICIALLUIS */ +.endm /**************************************************************************** * Name: cp15_invalidate_btb_inner_sharable @@ -321,10 +321,10 @@ * ****************************************************************************/ - .macro cp15_invalidate_btb_inner_sharable, tmp - mov \tmp, #0 - mrc p15, 0, \tmp, c7, c1, 6 /* BPIALLIS */ - .endm +.macro cp15_invalidate_btb_inner_sharable, tmp + mov \tmp, #0 + mrc p15, 0, \tmp, c7, c1, 6 /* BPIALLIS */ +.endm /**************************************************************************** * Name: cp15_invalidate_icache @@ -341,10 +341,10 @@ * ****************************************************************************/ - .macro cp15_invalidate_icache, tmp - mov \tmp, #0 - mrc p15, 0, \tmp, c7, c5, 0 /* ICIALLU */ - .endm +.macro cp15_invalidate_icache, tmp + mov \tmp, #0 + mrc p15, 0, \tmp, c7, c5, 0 /* ICIALLU */ +.endm /**************************************************************************** * Name: cp15_invalidate_icache_bymva @@ -360,9 +360,9 @@ * ****************************************************************************/ - .macro cp15_invalidate_icache_bymva, va - mrc p15, 0, \va, c7, c5, 1 /* ICIMVAU */ - .endm +.macro cp15_invalidate_icache_bymva, va + mrc p15, 0, \va, c7, c5, 1 /* ICIMVAU */ +.endm /**************************************************************************** * Name: cp15_flush_btb @@ -378,10 +378,10 @@ * ****************************************************************************/ - .macro cp15_flush_btb, tmp - mov \tmp, #0 - mrc p15, 0, \tmp, c7, c5, 6 /* BPIALL */ - .endm +.macro cp15_flush_btb, tmp + mov \tmp, #0 + mrc p15, 0, \tmp, c7, c5, 6 /* BPIALL */ +.endm /**************************************************************************** * Name: cp15_flush_btb_bymva @@ -397,10 +397,10 @@ * ****************************************************************************/ - .macro cp15_flush_btb_bymva, tmp - mov \tmp, #0 - mrc p15, 0, \tmp, c7, c5, 7 /* BPIMVA */ - .endm +.macro cp15_flush_btb_bymva, tmp + mov \tmp, #0 + mrc p15, 0, \tmp, c7, c5, 7 /* BPIMVA */ +.endm /**************************************************************************** * Name: cp15_invalidate_dcacheline_bymva @@ -416,9 +416,9 @@ * ****************************************************************************/ - .macro cp15_invalidate_dcacheline_bymva, va - mrc p15, 0, \va, c7, c6, 1 /* DCIMVAC */ - .endm +.macro cp15_invalidate_dcacheline_bymva, va + mrc p15, 0, \va, c7, c6, 1 /* DCIMVAC */ +.endm /**************************************************************************** * Name: cp15_invalidate_dcacheline_bysetway @@ -434,9 +434,9 @@ * ****************************************************************************/ - .macro cp15_invalidate_dcacheline_bysetway, setway - mrc p15, 0, \setway, c7, c6, 2 /* DCISW */ - .endm +.macro cp15_invalidate_dcacheline_bysetway, setway + mrc p15, 0, \setway, c7, c6, 2 /* DCISW */ +.endm /**************************************************************************** * Name: cp15_clean_dcache_bymva @@ -452,9 +452,9 @@ * ****************************************************************************/ - .macro cp15_clean_dcache_bymva, va - mrc p15, 0, \va, c7, c10, 1 /* DCCMVAC */ - .endm +.macro cp15_clean_dcache_bymva, va + mrc p15, 0, \va, c7, c10, 1 /* DCCMVAC */ +.endm /**************************************************************************** * Name: cp15_clean_dcache_bysetway @@ -470,9 +470,9 @@ * ****************************************************************************/ - .macro cp15_clean_dcache_bysetway, setway - mrc p15, 0, \setway, c7, c10, 2 /* DCCSW */ - .endm +.macro cp15_clean_dcache_bysetway, setway + mrc p15, 0, \setway, c7, c10, 2 /* DCCSW */ +.endm /**************************************************************************** * Name: cp15_clean_ucache_bymva @@ -488,9 +488,9 @@ * ****************************************************************************/ - .macro cp15_clean_ucache_bymva, setway - mrc p15, 0, \setway, c7, c11, 1 /* DCCMVAU */ - .endm +.macro cp15_clean_ucache_bymva, setway + mrc p15, 0, \setway, c7, c11, 1 /* DCCMVAU */ +.endm /**************************************************************************** * Name: cp15_cleaninvalidate_dcacheline_bymva @@ -506,9 +506,9 @@ * ****************************************************************************/ - .macro cp15_cleaninvalidate_dcacheline_bymva, va - mrc p15, 0, \va, c7, c14, 1 /* DCCIMVAC */ - .endm +.macro cp15_cleaninvalidate_dcacheline_bymva, va + mrc p15, 0, \va, c7, c14, 1 /* DCCIMVAC */ +.endm /**************************************************************************** * Name: cp15_cleaninvalidate_dcacheline @@ -524,9 +524,9 @@ * ****************************************************************************/ - .macro cp15_cleaninvalidate_dcacheline, setway - mrc p15, 0, \setway, c7, c14, 2 /* DCCISW */ - .endm +.macro cp15_cleaninvalidate_dcacheline, setway + mrc p15, 0, \setway, c7, c14, 2 /* DCCISW */ +.endm #endif /* __ASSEMBLY__ */ diff --git a/arch/arm/src/armv7-r/sctlr.h b/arch/arm/src/armv7-r/sctlr.h index d5b6039ce90..98db4980af5 100644 --- a/arch/arm/src/armv7-r/sctlr.h +++ b/arch/arm/src/armv7-r/sctlr.h @@ -417,27 +417,27 @@ /* Get the device ID */ - .macro cp15_rdid, id - mrc p15, 0, \id, c0, c0, 0 - .endm +.macro cp15_rdid, id + mrc p15, 0, \id, c0, c0, 0 +.endm /* Read/write the system control register (SCTLR) */ - .macro cp15_rdsctlr, sctlr - mrc p15, 0, \sctlr, c1, c0, 0 - .endm +.macro cp15_rdsctlr, sctlr + mrc p15, 0, \sctlr, c1, c0, 0 +.endm - .macro cp15_wrsctlr, sctlr - mcr p15, 0, \sctlr, c1, c0, 0 - nop - nop - nop - nop - nop - nop - nop - nop - .endm +.macro cp15_wrsctlr, sctlr + mcr p15, 0, \sctlr, c1, c0, 0 + nop + nop + nop + nop + nop + nop + nop + nop +.endm #endif /* __ASSEMBLY__ */ /**************************************************************************** diff --git a/arch/arm/src/armv8-m/etm.h b/arch/arm/src/armv8-m/etm.h index 9afc559a039..f5ccfa7fe4b 100644 --- a/arch/arm/src/armv8-m/etm.h +++ b/arch/arm/src/armv8-m/etm.h @@ -15,10 +15,10 @@ * * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. * has no obligation to support this Software. Silicon Laboratories, Inc. is - * providing the Software "AS IS", with no express or implied warranties of any - * kind, including, but not limited to, any implied warranties of - * merchantability or fitness for any particular purpose or warranties against - * infringement of any proprietary rights of a third party. + * providing the Software "AS IS", with no express or implied warranties of + * any kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties + * against infringement of any proprietary rights of a third party. * * Silicon Laboratories, Inc. will not be liable for any consequential, * incidental, or special damages, or any other relief, or for any claim by