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when setting an alarm, ensure that the respective alarm triggered flag is reset, because the alarms are edge-triggered interrupts

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ziggurat29
2016-05-05 11:47:58 -05:00
parent 0d659de226
commit 4e57c36a8c
1 changed files with 24 additions and 6 deletions
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arch/arm/src/stm32l4/stm32l4_rtcc.c
+20 -2
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@@ -636,11 +636,13 @@ static int stm32l4_rtc_alarm_handler(int irq, void *context)
cb(arg, RTC_ALARMA); cb(arg, RTC_ALARMA);
} }
}
/* note, bits 8-13 do /not/ require the write enable procedure */
isr = getreg32(STM32L4_RTC_ISR) & ~RTC_ISR_ALRAF; isr = getreg32(STM32L4_RTC_ISR) & ~RTC_ISR_ALRAF;
putreg32(isr, STM32L4_RTC_ISR); putreg32(isr, STM32L4_RTC_ISR);
} }
}
if ((isr & RTC_ISR_ALRBF) != 0) if ((isr & RTC_ISR_ALRBF) != 0)
{ {
@@ -660,11 +662,13 @@ static int stm32l4_rtc_alarm_handler(int irq, void *context)
cb(arg, RTC_ALARMB); cb(arg, RTC_ALARMB);
} }
}
/* note, bits 8-13 do /not/ require the write enable procedure */
isr = getreg32(STM32L4_RTC_ISR) & ~RTC_ISR_ALRBF; isr = getreg32(STM32L4_RTC_ISR) & ~RTC_ISR_ALRBF;
putreg32(isr, STM32L4_RTC_ISR); putreg32(isr, STM32L4_RTC_ISR);
} }
}
return ret; return ret;
} }
@@ -754,6 +758,7 @@ static int rtchw_check_alrbwf(void)
#ifdef CONFIG_RTC_ALARM #ifdef CONFIG_RTC_ALARM
static int rtchw_set_alrmar(rtc_alarmreg_t alarmreg) static int rtchw_set_alrmar(rtc_alarmreg_t alarmreg)
{ {
int isr;
int ret = -EBUSY; int ret = -EBUSY;
/* Need to allow RTC register write /* Need to allow RTC register write
@@ -778,6 +783,11 @@ static int rtchw_set_alrmar(rtc_alarmreg_t alarmreg)
rtcvdbg(" TR: %08x ALRMAR: %08x\n", rtcvdbg(" TR: %08x ALRMAR: %08x\n",
getreg32(STM32L4_RTC_TR), getreg32(STM32L4_RTC_ALRMAR)); getreg32(STM32L4_RTC_TR), getreg32(STM32L4_RTC_ALRMAR));
/* ensure Alarm A flag reset; this is edge triggered */
isr = getreg32(STM32L4_RTC_ISR) & ~RTC_ISR_ALRAF;
putreg32(isr, STM32L4_RTC_ISR);
/* Enable RTC alarm A */ /* Enable RTC alarm A */
modifyreg32(STM32L4_RTC_CR, 0, (RTC_CR_ALRAE | RTC_CR_ALRAIE)); modifyreg32(STM32L4_RTC_CR, 0, (RTC_CR_ALRAE | RTC_CR_ALRAIE));
@@ -791,6 +801,7 @@ errout_with_wprunlock:
#ifdef CONFIG_RTC_ALARM #ifdef CONFIG_RTC_ALARM
static int rtchw_set_alrmbr(rtc_alarmreg_t alarmreg) static int rtchw_set_alrmbr(rtc_alarmreg_t alarmreg)
{ {
int isr;
int ret = -EBUSY; int ret = -EBUSY;
/* Need to allow RTC register write /* Need to allow RTC register write
@@ -815,6 +826,11 @@ static int rtchw_set_alrmbr(rtc_alarmreg_t alarmreg)
rtcvdbg(" TR: %08x ALRMBR: %08x\n", rtcvdbg(" TR: %08x ALRMBR: %08x\n",
getreg32(STM32L4_RTC_TR), getreg32(STM32L4_RTC_ALRMBR)); getreg32(STM32L4_RTC_TR), getreg32(STM32L4_RTC_ALRMBR));
/* ensure Alarm B flag reset; this is edge triggered */
isr = getreg32(STM32L4_RTC_ISR) & ~RTC_ISR_ALRBF;
putreg32(isr, STM32L4_RTC_ISR);
/* Enable RTC alarm B */ /* Enable RTC alarm B */
modifyreg32(STM32L4_RTC_CR, 0, (RTC_CR_ALRBE | RTC_CR_ALRBIE)); modifyreg32(STM32L4_RTC_CR, 0, (RTC_CR_ALRBE | RTC_CR_ALRBIE));
@@ -1420,6 +1436,7 @@ int stm32l4_rtc_cancelalarm(enum alm_id_e alarmid)
/* Unset the alarm */ /* Unset the alarm */
putreg32(-1, STM32L4_RTC_ALRMAR); putreg32(-1, STM32L4_RTC_ALRMAR);
modifyreg32(STM32L4_RTC_ISR, RTC_ISR_ALRAF, 0);
rtc_wprlock(); rtc_wprlock();
ret = OK; ret = OK;
} }
@@ -1451,6 +1468,7 @@ int stm32l4_rtc_cancelalarm(enum alm_id_e alarmid)
/* Unset the alarm */ /* Unset the alarm */
putreg32(-1, STM32L4_RTC_ALRMBR); putreg32(-1, STM32L4_RTC_ALRMBR);
modifyreg32(STM32L4_RTC_ISR, RTC_ISR_ALRBF, 0);
rtc_wprlock(); rtc_wprlock();
ret = OK; ret = OK;
} }