diff --git a/arch/arm/src/stm32/chip/stm32_flash.h b/arch/arm/src/stm32/chip/stm32_flash.h
index c2e44092390..d6fcecc1146 100644
--- a/arch/arm/src/stm32/chip/stm32_flash.h
+++ b/arch/arm/src/stm32/chip/stm32_flash.h
@@ -110,6 +110,7 @@
 #  define FLASH_ACR_HLFCYA          (1 << 3)                /* FLASH half cycle access */
 #  define FLASH_ACR_PRTFBE          (1 << 4)                /* FLASH prefetch enable */
 #elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
+#  define FLASH_ACR_PRFTEN          (1 << 8)                /* FLASH prefetch enable */
 #  define FLASH_ACR_ICEN            (1 << 9)                /* Bit 9: Instruction cache enable */
 #  define FLASH_ACR_DCEN            (1 << 10)               /* Bit 10: Data cache enable */
 #  define FLASH_ACR_ICRST           (1 << 11)               /* Bit 11: Instruction cache reset */
diff --git a/arch/arm/src/stm32/stm32_serial.c b/arch/arm/src/stm32/stm32_serial.c
index 6c1861ef8cc..c7f97b25acb 100644
--- a/arch/arm/src/stm32/stm32_serial.c
+++ b/arch/arm/src/stm32/stm32_serial.c
@@ -101,11 +101,11 @@
  */
 
 #  if (defined(CONFIG_USART1_RXDMA) && defined(CONFIG_USART1_RS485)) || \
-      (defined(CONFIG_USART2_RXDMA) && defined(CONFIG_USART2_RS485)) ||  \
-      (defined(CONFIG_USART3_RXDMA) && defined(CONFIG_USART3_RS485)) ||  \
-      (defined(CONFIG_UART4_RXDMA) && defined(CONFIG_UART4_RS485)) ||  \
-      (defined(CONFIG_UART5_RXDMA) && defined(CONFIG_UART5_RS485)) ||  \
-      (defined(CONFIG_USART6_RXDMA) && defined(CONFIG_USART6_RS485)) \
+      (defined(CONFIG_USART2_RXDMA) && defined(CONFIG_USART2_RS485)) || \
+      (defined(CONFIG_USART3_RXDMA) && defined(CONFIG_USART3_RS485)) || \
+      (defined(CONFIG_UART4_RXDMA) && defined(CONFIG_UART4_RS485)) || \
+      (defined(CONFIG_UART5_RXDMA) && defined(CONFIG_UART5_RS485)) || \
+      (defined(CONFIG_USART6_RXDMA) && defined(CONFIG_USART6_RS485))
 #    error "RXDMA and RS-485 cannot be enabled at the same time for the same U[S]ART"
 #  endif
 
diff --git a/arch/arm/src/stm32/stm32f40xxx_rcc.c b/arch/arm/src/stm32/stm32f40xxx_rcc.c
index 45980f2889c..14ee1e75499 100644
--- a/arch/arm/src/stm32/stm32f40xxx_rcc.c
+++ b/arch/arm/src/stm32/stm32f40xxx_rcc.c
@@ -633,7 +633,7 @@ static void stm32_stdclockconfig(void)
  
       /* Enable FLASH prefetch, instruction cache, data cache, and 5 wait states */
 
-      regval = (FLASH_ACR_LATENCY_5 | FLASH_ACR_ICEN | FLASH_ACR_DCEN);
+      regval = (FLASH_ACR_LATENCY_5 | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_PRFTEN);
       putreg32(regval, STM32_FLASH_ACR);
 
       /* Select the main PLL as system clock source */