diff --git a/arch/mips/include/mips32/cp0.h b/arch/mips/include/mips32/cp0.h
index e6668fa8e3d..12c02e63b22 100644
--- a/arch/mips/include/mips32/cp0.h
+++ b/arch/mips/include/mips32/cp0.h
@@ -340,13 +340,13 @@
  * Compliance Level: Required.
  */
 
-#define CP0_CONFIG1_FP              (1 << 0 FPU implemented
-#define CP0_CONFIG1_EP              (1 << 1 EJTAG implemented
-#define CP0_CONFIG1_CA              (1 << 2 Code compression (MIPS16) implemented
-#define CP0_CONFIG1_WR              (1 << 3 Watch registers implemented
-#define CP0_CONFIG1_PC              (1 << 4 Performance Counter registers implemented
-#define CP0_CONFIG1_MD              (1 << 5 MDMX ASE implemented (MIPS64)
-#define CP0_CONFIG1_C2              (1 << 6 Coprocessor 2 implemented
+#define CP0_CONFIG1_FP              (1 << 0)  /* FPU implemented */
+#define CP0_CONFIG1_EP              (1 << 1)  /* EJTAG implemented */
+#define CP0_CONFIG1_CA              (1 << 2)  /* Code compression (MIPS16) implemented */
+#define CP0_CONFIG1_WR              (1 << 3)  /* Watch registers implemented */
+#define CP0_CONFIG1_PC              (1 << 4)  /* Performance Counter registers implemented */
+#define CP0_CONFIG1_MD              (1 << 5)  /* MDMX ASE implemented (MIPS64) */
+#define CP0_CONFIG1_C2              (1 << 6)  /* Coprocessor 2 implemented */
 #define CP0_CONFIG1_DA_SHIFT        (7)       /* Bits 7-9: Dcache associativity */
 #define CP0_CONFIG1_DA_MASK         (7 << CP0_CONFIG1_DA_SHIFT)
 #  define CP0_CONFIG1_DA_DIRECT     (0 << CP0_CONFIG1_DA_SHIFT) /* Direct mapped */
diff --git a/configs/pizero/README.txt b/configs/pizero/README.txt
index 560fb0ae8b8..03fa4518853 100644
--- a/configs/pizero/README.txt
+++ b/configs/pizero/README.txt
@@ -20,9 +20,9 @@ STATUS
     still missing.
 
     - Mini-UART Baud divisor calculation,
-    - Start-up logic.  My understand from what I have read on the internet
+    - Start-up logic.  My understand from what I have read on the Internet
       is the PiZero OS starts up in hypervisor mode with the MMU and I- and
-      D-Caches enabled.  This probaby means that the standard, classic ARM
+      D-Caches enabled.  This probably means that the standard, classic ARM
       startup logic at at arch/arm/src/arm/up_head.S will need to be replaced
       with some custom logic.