mirror of
https://github.com/apache/nuttx.git
synced 2026-06-05 15:58:59 +08:00
Merged nuttx/nuttx into master
This commit is contained in:
Ken Fazzone
@@ -11887,6 +11887,14 @@
|
||||
violated the OS/application interface -- by calling flash_eraseall().
|
||||
The old code can be found in the Obsoleted' repository (and a revised
|
||||
version can be found at apps/fsutils/flash_eraseall) (2016-06-03).
|
||||
* arch/arm/src/stm32: STM32 Timer Driver: Change calculation of per-
|
||||
timer pre-scaler value. Add support for all timers (2016-6-03)
|
||||
* drivers/lcd: Correct conditional compilation in ST7565 driver. From
|
||||
Pierre-noel Bouteville (2016-6-03)
|
||||
* arch/arm/src/stm32: Correct conditional compilation in STM32 timer
|
||||
capture logic. From Pierre-noel Bouteville (2016-6-03)
|
||||
* arch/arm/src/efm32: Fix EFM32 FLASH conditional compilation. From
|
||||
Pierre-noel Bouteville (2016-6-03)
|
||||
* arch/arm/src/lpc43xx: Fix errors in GPIO interrupt logic. From v01d
|
||||
(phreakuencies) (2016-06-04)
|
||||
* arch/arm/src/kl and lpc11xx: rename xyz_lowputc to up_putc. Remove
|
||||
@@ -11896,11 +11904,23 @@
|
||||
* arch/arm/src/stm32: Add the up_getc() function to STM32 in order to
|
||||
support the minnsh configuration. From Alan Carvalho de Assis
|
||||
(2016-06-04).
|
||||
* arch/arm/src/stm32: STM32 Timer Driver: Change calculation of per-
|
||||
timer pre-scaler value. Add support for all timers (2016-6-03)
|
||||
* drivers/lcd: Correct conditional compilation in ST7565 driver. From
|
||||
Pierre-noel Bouteville (2016-6-03)
|
||||
* arch/arm/src/stm32: Correct conditional compilation in STM32 timer
|
||||
capture logic. From Pierre-noel Bouteville (2016-6-03)
|
||||
* arch/arm/src/efm32: Fix EFM32 FLASH conditional compilation. From
|
||||
Pierre-noel Bouteville (2016-6-03)
|
||||
* include/sys/boardctl.h: Needs to be usable with C++ files (2016-06-05).
|
||||
* tools/tesbuild.sh will now build NxWM configurations (2016-06-05).
|
||||
* arch/arm/src/stm32: In PWM driver, just update duty if frequency is
|
||||
not changed and PSM started. This removeis glitch or blinking when
|
||||
only duty is frequently changed. From Pierre-noel Bouteville (2016-06-05).
|
||||
* arch/arm/src/kinetis: Add a USB device controller driver. Derived from
|
||||
the pic32mx usb driver, which uses the same usb controller. From kfazz
|
||||
(2016-06).
|
||||
* configs/teensy-3.x: Add USB support and a usbnsh configuration. From
|
||||
kfazz (2016-06).
|
||||
* arch/arm/src/stm32: Add support for the STM32F105R. From Konstantin
|
||||
Berezenko (2016-06-06).
|
||||
* include/signal.h: Change type of SIG_ERR, SIG_IGN, ... to
|
||||
_sa_handler_t. They type void does not work with the IAR toolchain.
|
||||
From Aleksandr Vyhovanec (2016-06-07).
|
||||
* arch/arm/src/stm32f7 and include/stm32f7: Added STM32FF76xxx and
|
||||
STM32FF7xx families. From David Sidrane (2016-06-08).
|
||||
* Refactoring configs/nucleo-144 sub-directories to support additional
|
||||
nucleo-144 board. Add support for the Nucleo-F767ZI board. From David
|
||||
Sidrane (2016-06-08).
|
||||
|
||||
+7
-3
@@ -960,10 +960,13 @@ Native Windows Build
|
||||
In this build, you cannot use a Cygwin or MSYS shell. Rather the build must
|
||||
be performed in a Windows console window. Here is a better terminal than the
|
||||
standard issue, CMD.exe terminal: ConEmu which can be downloaded from:
|
||||
http://code.google.com/p/conemu-maximus5/
|
||||
https://sourceforge.net/projects/conemu/ or https://conemu.github.io/ .
|
||||
|
||||
Build Tools. The build still relies on some Unix-like commands. I use
|
||||
the GNUWin32 tools that can be downloaded from http://gnuwin32.sourceforge.net/.
|
||||
the GNUWin32 tools that can be downloaded from http://gnuwin32.sourceforge.net/
|
||||
using the 'Download all' selection. Individual packages can be download
|
||||
instead if you know what you are doing and want a faster download (No, I
|
||||
can't tell you which packages you should or should not download).
|
||||
|
||||
Host Compiler: I use the MingGW GCC compiler which can be downloaded from
|
||||
http://www.mingw.org/. If you are using GNUWin32, then it is recommended
|
||||
@@ -972,7 +975,8 @@ Native Windows Build
|
||||
This capability should still be considered a work in progress because:
|
||||
|
||||
(1) It has not been verified on all targets and tools, and
|
||||
(2) it still lacks some of the creature-comforts of the more mature environments.
|
||||
(2) it still lacks some of the creature-comforts of the more mature
|
||||
environments.
|
||||
|
||||
There is an alternative to the setenv.sh script available for the Windows
|
||||
native environment: tools/configure.bat. See tools/README.txt for additional
|
||||
|
||||
@@ -1605,6 +1605,11 @@ o Build system
|
||||
Description: The way that apps/ no generates Kmenu files depends on changes added
|
||||
to apps/tools/mkkconfig.sh. Similar changes need to be made to
|
||||
apps/tools/mkkconfig.bat to restore the Windows Native build.
|
||||
UPDATE: The mkkconfig.bat script has been updated and appears to work.
|
||||
A native build has still not been attempted and there could likely be
|
||||
issues the carriage returns in Kconfig files. There are also some
|
||||
issues the interpreters/ficl and bas directories during 'make menuconfig'
|
||||
that still need to be investigated.
|
||||
Status: Open
|
||||
Priority: Low, since I am not aware of anyone using the Windows Native build.
|
||||
But, of course, very high if you want to use it.
|
||||
|
||||
@@ -903,6 +903,43 @@
|
||||
# define STM32_NRNG 0 /* No random number generator (RNG) */
|
||||
# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32F105RB)
|
||||
# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */
|
||||
# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite family */
|
||||
# define CONFIG_STM32_STM32F10XX 1 /* STM32F10xxx family */
|
||||
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
|
||||
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
|
||||
# undef CONFIG_STM32_MEDIUMPLUSDENSITY /* STM32L15xxC w/ 32/256 Kbytes */
|
||||
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
|
||||
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
|
||||
# define CONFIG_STM32_CONNECTIVITYLINE 1 /* STM32F105x and STM32F107x */
|
||||
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
|
||||
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
|
||||
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
|
||||
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */
|
||||
# define STM32_NFSMC 1 /* FSMC */
|
||||
# define STM32_NATIM 1 /* One advanced timers TIM1 */
|
||||
# define STM32_NGTIM 4 /* 16-bit general timers TIM2-5 with DMA */
|
||||
# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */
|
||||
# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */
|
||||
# define STM32_NDMA 2 /* DMA1-2 */
|
||||
# define STM32_NSPI 3 /* SPI1-3 */
|
||||
# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
|
||||
# define STM32_NUSART 5 /* USART1-3, UART 4-5 */
|
||||
# define STM32_NI2C 2 /* I2C1-2 */
|
||||
# define STM32_NCAN 2 /* CAN1-2 */
|
||||
# define STM32_NSDIO 0 /* No SDIO */
|
||||
# define STM32_NLCD 0 /* No LCD */
|
||||
# define STM32_NUSBOTG 1 /* USB OTG FS/HS */
|
||||
# define STM32_NGPIO 51 /* GPIOA-E */
|
||||
# define STM32_NADC 2 /* ADC1-2 */
|
||||
# define STM32_NDAC 2 /* DAC1-2 */
|
||||
# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
|
||||
# define STM32_NCRC 1 /* CRC */
|
||||
# define STM32_NETHERNET 0 /* 100/100 Ethernet MAC */
|
||||
# define STM32_NRNG 0 /* No random number generator (RNG) */
|
||||
# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32F107VC)
|
||||
# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */
|
||||
# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite family */
|
||||
|
||||
+233
-60
@@ -1,7 +1,7 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/include/stm32f7/chip.h
|
||||
*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2015-2016 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@@ -45,99 +45,272 @@
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
/* STM32F745xx, STM32F746xx, and STM32F56xx. Differences between family members:
|
||||
/* STM32F745xx, STM32F746xx, STM32F756xx, STM32F765xx, STM32F767xx, STM32F768xx,
|
||||
* STM32F769xx, STM32F777xx and STM32F779xx Differences between family members:
|
||||
*
|
||||
* ----------- ---------------- ----- -------- ------------ --------
|
||||
* PART PACKAGE GPIOs SPI/I2S ADC CHANNELS LCD-TFT?
|
||||
* ----------- ---------------- ----- -------- ------------ --------
|
||||
* STM32F745Vx LQFP100 82 4/3 16 No
|
||||
* STM32F745Zx WLCSP143/LQFP144 114 6/3 24 No
|
||||
* STM32F745Ix UFBGA176/LQFP176 140 6/3 24 No
|
||||
* STM32F745Bx LQFP208 168 6/3 24 No
|
||||
* STM32F745Nx TFBGA216 68 6/3 24 No
|
||||
* ----------- ---------------- ----- ---- ----- ---- ---- ---- ---- ---- ----- ----- ---- ------------ ------
|
||||
* SPI ADC LCD
|
||||
* PART PACKAGE GPIOs I2S CHAN TFT MIPI JPEG CAN ETH DFSDM CRYPTO FPU RAM L1
|
||||
* ----------- ---------------- ----- ---- ----- ---- ---- ---- ---- ---- ----- ----- ---- ------------ ------
|
||||
* STM32F745Vx LQFP100 82 4/3 16 No No No 2 Yes No No SFPU (240+16+64) 4+4
|
||||
* STM32F745Zx WLCSP143/LQFP144 114 6/3 24 No No No 2 Yes No No SFPU (240+16+64) 4+4
|
||||
* STM32F745Ix UFBGA176/LQFP176 140 6/3 24 No No No 2 Yes No No SFPU (240+16+64) 4+4
|
||||
* STM32F745Bx LQFP208 168 6/3 24 No No No 2 Yes No No SFPU (240+16+64) 4+4
|
||||
* STM32F745Nx TFBGA216 68 6/3 24 No No No 2 Yes No No SFPU (240+16+64) 4+4
|
||||
*
|
||||
* STM32F746Vx LQFP100 82 4/3 16 Yes
|
||||
* STM32F746Zx WLCSP143/LQFP144 114 6/3 24 Yes
|
||||
* STM32F746Ix UFBGA176/LQFP176 140 6/3 24 Yes
|
||||
* STM32F746Bx LQFP208 168 6/3 24 Yes
|
||||
* STM32F746Nx TFBGA216 168 6/3 24 Yes
|
||||
* STM32F746Vx LQFP100 82 4/3 16 Yes No No 2 Yes No No SFPU (240+16+64) 4+4
|
||||
* STM32F746Zx WLCSP143/LQFP144 114 6/3 24 Yes No No 2 Yes No No SFPU (240+16+64) 4+4
|
||||
* STM32F746Ix UFBGA176/LQFP176 140 6/3 24 Yes No No 2 Yes No No SFPU (240+16+64) 4+4
|
||||
* STM32F746Bx LQFP208 168 6/3 24 Yes No No 2 Yes No No SFPU (240+16+64) 4+4
|
||||
* STM32F746Nx TFBGA216 168 6/3 24 Yes No No 2 Yes No No SFPU
|
||||
*
|
||||
* STM32F756Vx LQFP100 82 4/3 16 Yes
|
||||
* STM32F756Zx WLCSP143/LQFP144 114 6/3 24 Yes
|
||||
* STM32F756Ix UFBGA176/LQFP176 140 6/3 24 Yes
|
||||
* STM32F756Bx LQFP208 168 6/3 24 Yes
|
||||
* STM32F756Nx TFBGA216 168 6/3 24 Yes
|
||||
* ----------- ---------------- ----- -------- ------------ --------
|
||||
* STM32F756Vx LQFP100 82 4/3 16 Yes No No 2 Yes No Yes SFPU (240+16+64) 4+4
|
||||
* STM32F756Zx WLCSP143/LQFP144 114 6/3 24 Yes No No 2 Yes No Yes SFPU (240+16+64) 4+4
|
||||
* STM32F756Ix UFBGA176/LQFP176 140 6/3 24 Yes No No 2 Yes No Yes SFPU (240+16+64) 4+4
|
||||
* STM32F756Bx LQFP208 168 6/3 24 Yes No No 2 Yes No Yes SFPU (240+16+64) 4+4
|
||||
* STM32F756Nx TFBGA216 168 6/3 24 Yes No No 2 Yes No Yes SFPU (240+16+64) 4+4
|
||||
*
|
||||
* STM32F765Vx LQFP100 82 4/3 16 No No No 3 Yes Yes No DFPU (368+16+128) 16+16
|
||||
* STM32F765Zx WLCSP143/LQFP144 114 6/3 24 No No No 3 Yes Yes No DFPU (368+16+128) 16+16
|
||||
* STM32F765Ix UFBGA176/LQFP176 140 6/3 24 No No No 3 Yes Yes No DFPU (368+16+128) 16+16
|
||||
* STM32F765Bx LQFP208 168 6/3 24 No No No 3 Yes Yes No DFPU (368+16+128) 16+16
|
||||
* STM32F765Nx TFBGA216 168 6/3 24 No No No 3 Yes Yes No DFPU (368+16+128) 16+16
|
||||
*
|
||||
* STM32F767Vx LQFP100 82 4/3 16 Yes No Yes 3 Yes Yes No DFPU (368+16+128) 16+16
|
||||
* STM32F767Zx WLCSP143/LQFP144 114 6/3 24 Yes No Yes 3 Yes Yes No DFPU (368+16+128) 16+16
|
||||
* STM32F767Ix UFBGA176/LQFP176 132 6/3 24 Yes Yes Yes 3 Yes Yes No DFPU (368+16+128) 16+16
|
||||
* STM32F767Bx LQFP208 168 6/3 24 Yes Yes Yes 3 Yes Yes No DFPU (368+16+128) 16+16
|
||||
* STM32F767Nx TFBGA216 159 6/3 24 Yes Yes Yes 3 Yes Yes No DFPU (368+16+128) 16+16
|
||||
*
|
||||
* STM32F768Ax WLCSP180 129 6/3 24 Yes Yes Yes 3 No Yes No DFPU (368+16+128) 16+16
|
||||
*
|
||||
* STM32F769Vx LQFP100 82 4/3 16 Yes No Yes 3 Yes Yes No DFPU (368+16+128) 16+16
|
||||
* STM32F769Zx LQFP144 114 6/3 24 Yes No Yes 3 Yes Yes No DFPU (368+16+128) 16+16
|
||||
* STM32F769Ix UFBGA176/LQFP176 132 6/3 24 Yes Yes Yes 3 Yes Yes No DFPU (368+16+128) 16+16
|
||||
* STM32F769Bx LQFP208 168 6/3 24 Yes Yes Yes 3 Yes Yes No DFPU (368+16+128) 16+16
|
||||
* STM32F769Nx TFBGA216 159 6/3 24 Yes Yes Yes 3 Yes Yes No DFPU (368+16+128) 16+16
|
||||
*
|
||||
* STM32F769Ax WLCSP180 129 6/3 24 Yes Yes Yes 3 No Yes No DFPU (368+16+128) 16+16
|
||||
*
|
||||
* STM32F777Vx LQFP100 82 4/3 16 Yes No Yes 3 Yes Yes Yes DFPU (368+16+128) 16+16
|
||||
* STM32F777Zx LQFP144 114 6/3 24 Yes No Yes 3 Yes Yes Yes DFPU (368+16+128) 16+16
|
||||
* STM32F777Ix UFBGA176/LQFP176 132 6/3 24 Yes Yes Yes 3 Yes Yes Yes DFPU (368+16+128) 16+16
|
||||
* STM32F777Bx LQFP208 159 6/3 24 Yes Yes Yes 3 Yes Yes Yes DFPU (368+16+128) 16+16
|
||||
* STM32F777Nx TFBGA216 159 6/3 24 Yes Yes Yes 3 Yes Yes Yes DFPU (368+16+128) 16+16
|
||||
*
|
||||
* STM32F778Ax WLCSP180 129 6/3 24 Yes Yes Yes 3 No Yes Yes DFPU (368+16+128) 16+16
|
||||
*
|
||||
* STM32F779Ix UFBGA176/LQFP176 132 6/3 24 Yes Yes Yes 3 Yes Yes Yes DFPU (368+16+128) 16+16
|
||||
* STM32F779Bx LQFP208 159 6/3 24 Yes Yes Yes 3 Yes Yes Yes DFPU (368+16+128) 16+16
|
||||
* STM32F779Nx TFBGA216 159 6/3 24 Yes Yes Yes 3 Yes Yes Yes DFPU (368+16+128) 16+16
|
||||
|
||||
* STM32F779Ax WLCSP180 129 6/3 24 Yes Yes Yes 3 No Yes Yes DFPU (368+16+128) 16+16
|
||||
* ----------- ---------------- ----- ---- ----- ---- ---- ---- ---- ---- ----- ----- ---- ------------ ------
|
||||
*
|
||||
* Parts STM32F74xxE have 512Kb of FLASH
|
||||
* Parts STM32F74xxG have 1024Kb of FLASH
|
||||
* Parts STM32F74xxI have 2048Kb of FLASH
|
||||
*
|
||||
* The correct FLASH size will be set CONFIG_STM32F7_FLASH_CONFIG_x or overridden
|
||||
* with CONFIG_STM32F7_FLASH_OVERRIDE_x
|
||||
*
|
||||
* The correct FLASH size must be set with a CONFIG_STM32F7_FLASH_*KB
|
||||
* selection.
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_STM32F745) || defined(CONFIG_ARCH_CHIP_STM32F746) || \
|
||||
defined(CONFIG_ARCH_CHIP_STM32F756)
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_STM32F745)
|
||||
# define STM32F7_STM32F745XX 1 /* STM32F745xx family */
|
||||
# undef STM32F7_STM32F746XX /* Not STM32F746xx family */
|
||||
# undef STM32F7_STM32F756XX /* Not STM32F756xx family */
|
||||
|
||||
# define STM32F7_NLCDTFT 0 /* No LCD-TFT */
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32F746)
|
||||
|
||||
# undef STM32F7_STM32F745XX /* Not STM32F745xx family */
|
||||
# define STM32F7_STM32F746XX 1 /* STM32F746xx family */
|
||||
# undef STM32F7_STM32F756XX /* Not STM32F756xx family */
|
||||
|
||||
# define STM32F7_NLCDTFT 1 /* One LCD-TFT */
|
||||
|
||||
#else /* if defined(CONFIG_ARCH_CHIP_STM32F746) */
|
||||
|
||||
# undef STM32F7_STM32F745XX /* Not STM32F745xx family */
|
||||
# undef STM32F7_STM32F746XX /* Not STM32F746xx family */
|
||||
# define STM32F7_STM32F756XX 1 /* STM32F756xx family */
|
||||
|
||||
# define STM32F7_NLCDTFT 1 /* One LCD-TFT */
|
||||
#if defined(CONFIG_ARCH_CHIP_STM32F745VG) || \
|
||||
defined(CONFIG_ARCH_CHIP_STM32F745VE) || \
|
||||
defined(CONFIG_ARCH_CHIP_STM32F745IG) || \
|
||||
defined(CONFIG_ARCH_CHIP_STM32F745IE) || \
|
||||
defined(CONFIG_ARCH_CHIP_STM32F745ZE) || \
|
||||
defined(CONFIG_ARCH_CHIP_STM32F745ZG) || \
|
||||
defined(CONFIG_ARCH_CHIP_STM32F746BG) || \
|
||||
defined(CONFIG_ARCH_CHIP_STM32F746VG) || \
|
||||
defined(CONFIG_ARCH_CHIP_STM32F746VE) || \
|
||||
defined(CONFIG_ARCH_CHIP_STM32F746BE) || \
|
||||
defined(CONFIG_ARCH_CHIP_STM32F746ZG) || \
|
||||
defined(CONFIG_ARCH_CHIP_STM32F746IE) || \
|
||||
defined(CONFIG_ARCH_CHIP_STM32F746NG) || \
|
||||
defined(CONFIG_ARCH_CHIP_STM32F746NE) || \
|
||||
defined(CONFIG_ARCH_CHIP_STM32F746ZE) || \
|
||||
defined(CONFIG_ARCH_CHIP_STM32F746IG) || \
|
||||
defined(CONFIG_ARCH_CHIP_STM32F756NG) || \
|
||||
defined(CONFIG_ARCH_CHIP_STM32F756BG) || \
|
||||
defined(CONFIG_ARCH_CHIP_STM32F756IG) || \
|
||||
defined(CONFIG_ARCH_CHIP_STM32F756VG) || \
|
||||
defined(CONFIG_ARCH_CHIP_STM32F756ZG) || \
|
||||
defined(CONFIG_ARCH_CHIP_STM32F765NI) || \
|
||||
defined(CONFIG_ARCH_CHIP_STM32F765VI) || \
|
||||
defined(CONFIG_ARCH_CHIP_STM32F765VG) || \
|
||||
defined(CONFIG_ARCH_CHIP_STM32F765BI) || \
|
||||
defined(CONFIG_ARCH_CHIP_STM32F765NG) || \
|
||||
defined(CONFIG_ARCH_CHIP_STM32F765ZG) || \
|
||||
defined(CONFIG_ARCH_CHIP_STM32F765ZI) || \
|
||||
defined(CONFIG_ARCH_CHIP_STM32F765IG) || \
|
||||
defined(CONFIG_ARCH_CHIP_STM32F765BG) || \
|
||||
defined(CONFIG_ARCH_CHIP_STM32F765II) || \
|
||||
defined(CONFIG_ARCH_CHIP_STM32F767NG) || \
|
||||
defined(CONFIG_ARCH_CHIP_STM32F767IG) || \
|
||||
defined(CONFIG_ARCH_CHIP_STM32F767VG) || \
|
||||
defined(CONFIG_ARCH_CHIP_STM32F767ZG) || \
|
||||
defined(CONFIG_ARCH_CHIP_STM32F767NI) || \
|
||||
defined(CONFIG_ARCH_CHIP_STM32F767VI) || \
|
||||
defined(CONFIG_ARCH_CHIP_STM32F767BG) || \
|
||||
defined(CONFIG_ARCH_CHIP_STM32F767ZI) || \
|
||||
defined(CONFIG_ARCH_CHIP_STM32F767II) || \
|
||||
defined(CONFIG_ARCH_CHIP_STM32F769BI) || \
|
||||
defined(CONFIG_ARCH_CHIP_STM32F769II) || \
|
||||
defined(CONFIG_ARCH_CHIP_STM32F769BG) || \
|
||||
defined(CONFIG_ARCH_CHIP_STM32F769NI) || \
|
||||
defined(CONFIG_ARCH_CHIP_STM32F769AI) || \
|
||||
defined(CONFIG_ARCH_CHIP_STM32F769NG) || \
|
||||
defined(CONFIG_ARCH_CHIP_STM32F769IG) || \
|
||||
defined(CONFIG_ARCH_CHIP_STM32F777ZI) || \
|
||||
defined(CONFIG_ARCH_CHIP_STM32F777VI) || \
|
||||
defined(CONFIG_ARCH_CHIP_STM32F777NI) || \
|
||||
defined(CONFIG_ARCH_CHIP_STM32F777BI) || \
|
||||
defined(CONFIG_ARCH_CHIP_STM32F777II) || \
|
||||
defined(CONFIG_ARCH_CHIP_STM32F778AI) || \
|
||||
defined(CONFIG_ARCH_CHIP_STM32F779II) || \
|
||||
defined(CONFIG_ARCH_CHIP_STM32F779NI) || \
|
||||
defined(CONFIG_ARCH_CHIP_STM32F779BI) || \
|
||||
defined(CONFIG_ARCH_CHIP_STM32F779AI)
|
||||
#else
|
||||
# error STM32 F7 chip not identified
|
||||
#endif
|
||||
|
||||
/* Size SRAM */
|
||||
|
||||
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
|
||||
# define STM32F7_SRAM1_SIZE (240*1024) /* 240Kb SRAM1 on AHB bus Matrix */
|
||||
# define STM32F7_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */
|
||||
# define STM32F7_DTCM_SRAM_SIZE (64*1024) /* 64Kb DTCM SRAM on TCM inerface */
|
||||
# define STM32F7_ITCM_SRAM_SIZE (16*1024) /* 16Kb ITCM SRAM on TCM inerface */
|
||||
# if defined(CONFIG_ARMV7M_HAVE_DTCM)
|
||||
# define STM32F7_DTCM_SRAM_SIZE (64*1024) /* 64Kb DTCM SRAM on TCM interface */
|
||||
# else
|
||||
# define STM32F7_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */
|
||||
# endif
|
||||
# if defined(CONFIG_ARMV7M_HAVE_ITCM)
|
||||
# define STM32F7_ITCM_SRAM_SIZE (16*1024) /* 16Kb ITCM SRAM on TCM interface */
|
||||
# else
|
||||
# define STM32F7_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */
|
||||
# endif
|
||||
#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77X)
|
||||
# define STM32F7_SRAM1_SIZE (368*1024) /* 368Kb SRAM1 on AHB bus Matrix */
|
||||
# define STM32F7_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */
|
||||
# if defined(CONFIG_ARMV7M_HAVE_DTCM)
|
||||
# define STM32F7_DTCM_SRAM_SIZE (128*1024) /* 128Kb DTCM SRAM on TCM interface */
|
||||
# else
|
||||
# define STM32F7_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */
|
||||
# endif
|
||||
# if defined(CONFIG_ARMV7M_HAVE_ITCM)
|
||||
# define STM32F7_ITCM_SRAM_SIZE (16*1024) /* 16Kb ITCM SRAM on TCM interface */
|
||||
# else
|
||||
# define STM32F7_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */
|
||||
# endif
|
||||
#else
|
||||
# error STM32 F7 chip Family not identified
|
||||
#endif
|
||||
|
||||
/* Common to all Family members */
|
||||
|
||||
# define STM32F7_NFSMC 1 /* Have FSMC memory controller */
|
||||
# define STM32F7_NETHERNET 1 /* 100/100 Ethernet MAC */
|
||||
# define STM32F7_NATIM 2 /* Two advanced timers TIM1 and 8 */
|
||||
# define STM32F7_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */
|
||||
# define STM32F7_NGTIM16 2 /* 16-bit general timers TIM3 and 4 with DMA */
|
||||
# define STM32F7_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
|
||||
# define STM32F7_NBTIM 2 /* Two basic timers, TIM6-7 */
|
||||
# define STM32F7_NRNG 1 /* Random number generator (RNG) */
|
||||
# define STM32F7_NUART 4 /* UART 4-5 and 7-8 */
|
||||
# define STM32F7_NUSART 4 /* USART1-3 and 6 */
|
||||
# define STM32F7_NSPI 6 /* SPI1-6 (Except V series) */
|
||||
# define STM32F7_NI2S 3 /* I2S1-2 (multiplexed with SPI1-3) */
|
||||
# define STM32F7_NI2C 4 /* I2C1-4 */
|
||||
# define STM32F7_NUSBOTGFS 1 /* USB OTG FS */
|
||||
# define STM32F7_NUSBOTGHS 1 /* USB OTG HS */
|
||||
# define STM32F7_NCAN 2 /* CAN1-2 */
|
||||
# define STM32F7_NSAI 2 /* SAI1-2 */
|
||||
# define STM32F7_NSPDIFRX 4 /* 4 SPDIFRX inputs */
|
||||
# define STM32F7_NSDMMC 1 /* SDMMC interface */
|
||||
# define STM32F7_NDCMI 1 /* Digital camera interface (DCMI) */
|
||||
# define STM32F7_NDMA 2 /* DMA1-2 */
|
||||
# define STM32F7_NDMA2D 1 /* DChrom-ART Accelerator™ (DMA2D) */
|
||||
# define STM32F7_NGPIO 11 /* 11 GPIO ports, GPIOA-K */
|
||||
# define STM32F7_NADC 3 /* 12-bit ADC1-3, 24 channels *except V series) */
|
||||
# define STM32F7_NDAC 2 /* 12-bit DAC1-2 */
|
||||
# define STM32F7_NCAPSENSE 0 /* No capacitive sensing channels */
|
||||
# define STM32F7_NCRC 1 /* CRC */
|
||||
|
||||
/* TBD FPU Configuration */
|
||||
|
||||
#if defined(CONFIG_ARCH_HAVE_FPU)
|
||||
#else
|
||||
# error STM32 F7 chip not identified
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARCH_HAVE_DPFPU)
|
||||
#else
|
||||
#endif
|
||||
|
||||
/* Diversification based on Family and package */
|
||||
|
||||
#if defined(CONFIG_STM32F7_HAVE_FSMC)
|
||||
# define STM32F7_NFSMC 1 /* Have FSMC memory controller */
|
||||
#else
|
||||
# define STM32F7_NFSMC 0 /* No FSMC memory controller */
|
||||
#endif
|
||||
#if defined(CONFIG_STM32F7_HAVE_ETHRNET)
|
||||
# define STM32F7_NETHERNET 1 /* 100/100 Ethernet MAC */
|
||||
#else
|
||||
# define STM32F7_NETHERNET 0 /* No 100/100 Ethernet MAC */
|
||||
#endif
|
||||
#if defined(CONFIG_STM32F7_HAVE_RNG)
|
||||
# define STM32F7_NRNG 1 /* Random number generator (RNG) */
|
||||
#else
|
||||
# define STM32F7_NRNG 0 /* No Random number generator (RNG) */
|
||||
#endif
|
||||
#if defined(CONFIG_STM32F7_HAVE_SPI5) && defined(CONFIG_STM32F7_HAVE_SPI6)
|
||||
# define STM32F7_NSPI 6 /* SPI1-6 (Except V series) */
|
||||
#else
|
||||
# define STM32F7_NSPI 4 /* SPI1-4 V series */
|
||||
#endif
|
||||
#if defined(CONFIG_STM32F7_HAVE_SDMMC2)
|
||||
# define STM32F7_NSDMMC 2 /* 2 SDMMC interfaces */
|
||||
#else
|
||||
# define STM32F7_NSDMMC 1 /* 1 SDMMC interface */
|
||||
#endif
|
||||
#if defined(CONFIG_STM32F7_HAVE_CAN3)
|
||||
# define STM32F7_NCAN 3 /* CAN1-3 */
|
||||
#else
|
||||
# define STM32F7_NCAN 2 /* CAN1-2 */
|
||||
#endif
|
||||
#if defined(CONFIG_STM32F7_HAVE_DCMI)
|
||||
# define STM32F7_NDCMI 1 /* Digital camera interface (DCMI) */
|
||||
#else
|
||||
# define STM32F7_NDCMI 0 /* No Digital camera interface (DCMI) */
|
||||
#endif
|
||||
#if defined(CONFIG_STM32F7_HAVE_DSIHOST)
|
||||
# define STM32F7_NDSIHOST 1 /* Have MIPI DSI Host */
|
||||
#else
|
||||
# define STM32F7_NDSIHOST 0 /* No MIPI DSI Host */
|
||||
#endif
|
||||
#if defined (CONFIG_STM32F7_HAVE_LTDC)
|
||||
# define STM32F7_NLCDTFT 1 /* One LCD-TFT */
|
||||
#else
|
||||
# define STM32F7_NLCDTFT 0 /* No LCD-TFT */
|
||||
#endif
|
||||
#if defined(CONFIG_STM32F7_HAVE_DMA2D)
|
||||
# define STM32F7_NDMA2D 0 /* No DChrom-ART Accelerator™ (DMA2D) */
|
||||
#else
|
||||
# define STM32F7_NDMA2D 1 /* DChrom-ART Accelerator™ (DMA2D) */
|
||||
#endif
|
||||
#if defined(CONFIG_STM32F7_HAVE_JPEG)
|
||||
#define STM32F7_NJPEG 1 /* One JPEG Converter */
|
||||
#else
|
||||
#define STM32F7_NJPEG 0 /* No JPEG Converter */
|
||||
#endif
|
||||
#if defined(CONFIG_STM32F7_HAVE_CRYP)
|
||||
#define STM32F7_NCRYP 1 /* One CRYP engine */
|
||||
#else
|
||||
#define STM32F7_NCRYP 0 /* No CRYP engine */
|
||||
#endif
|
||||
#if defined(CONFIG_STM32F7_HAVE_HASH)
|
||||
#define STM32F7_NHASH 1 /* One HASH engine */
|
||||
#else
|
||||
#define STM32F7_NHASH 0 /* No HASH engine */
|
||||
#endif
|
||||
#if defined(CONFIG_STM32F7_HAVE_DFSDM)
|
||||
#define STM32F7_NDFSDM 4 /* One set of 4 Digital filters */
|
||||
#else
|
||||
#define STM32F7_NDFSDM 0 /* No Digital filters */
|
||||
#endif
|
||||
|
||||
/* NVIC priority levels *************************************************************/
|
||||
|
||||
@@ -78,6 +78,8 @@
|
||||
|
||||
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
|
||||
# include <arch/stm32f7/stm32f74xx75xx_irq.h>
|
||||
#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
|
||||
# include <arch/stm32f7/stm32f76xx77xx_irq.h>
|
||||
#else
|
||||
# error "Unsupported STM32 F7 chip"
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,215 @@
|
||||
/****************************************************************************************************
|
||||
* arch/arm/include/stm32f7/stm32f76xx77xx_irq.h.h
|
||||
*
|
||||
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************************************/
|
||||
|
||||
/* This file should never be included directed but, rather, only indirectly through arch/irq.h */
|
||||
|
||||
#ifndef __ARCH_ARM_INCLUDE_STM32F7_STM32F76XX77XX_IRQ_H
|
||||
#define __ARCH_ARM_INCLUDE_STM32F7_STM32F76XX77XX_IRQ_H
|
||||
|
||||
/****************************************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/****************************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************************************/
|
||||
|
||||
/* IRQ numbers. The IRQ number corresponds vector number and hence map directly to bits in the
|
||||
* NVIC. This does, however, waste several words of memory in the IRQ to handle mapping tables.
|
||||
*
|
||||
* Processor Exceptions (vectors 0-15). These common definitions can be found in the file
|
||||
* nuttx/arch/arm/include/stm32f7/irq.h which includes this file
|
||||
*
|
||||
* External interrupts (vectors >= 16)
|
||||
*/
|
||||
|
||||
#define STM32_IRQ_WWDG (STM32_IRQ_FIRST+0) /* 0: Window Watchdog interrupt */
|
||||
#define STM32_IRQ_PVD (STM32_IRQ_FIRST+1) /* 1: PVD through EXTI Line detection interrupt */
|
||||
#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST+2) /* 2: Tamper and time stamp interrupts */
|
||||
#define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST+2) /* 2: Tamper and time stamp interrupts */
|
||||
#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST+3) /* 3: RTC global interrupt */
|
||||
#define STM32_IRQ_FLASH (STM32_IRQ_FIRST+4) /* 4: Flash global interrupt */
|
||||
#define STM32_IRQ_RCC (STM32_IRQ_FIRST+5) /* 5: RCC global interrupt */
|
||||
#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST+6) /* 6: EXTI Line 0 interrupt */
|
||||
#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST+7) /* 7: EXTI Line 1 interrupt */
|
||||
#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST+8) /* 8: EXTI Line 2 interrupt */
|
||||
#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST+9) /* 9: EXTI Line 3 interrupt */
|
||||
#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST+10) /* 10: EXTI Line 4 interrupt */
|
||||
#define STM32_IRQ_DMA1S0 (STM32_IRQ_FIRST+11) /* 11: DMA1 Stream 0 global interrupt */
|
||||
#define STM32_IRQ_DMA1S1 (STM32_IRQ_FIRST+12) /* 12: DMA1 Stream 1 global interrupt */
|
||||
#define STM32_IRQ_DMA1S2 (STM32_IRQ_FIRST+13) /* 13: DMA1 Stream 2 global interrupt */
|
||||
#define STM32_IRQ_DMA1S3 (STM32_IRQ_FIRST+14) /* 14: DMA1 Stream 3 global interrupt */
|
||||
#define STM32_IRQ_DMA1S4 (STM32_IRQ_FIRST+15) /* 15: DMA1 Stream 4 global interrupt */
|
||||
#define STM32_IRQ_DMA1S5 (STM32_IRQ_FIRST+16) /* 16: DMA1 Stream 5 global interrupt */
|
||||
#define STM32_IRQ_DMA1S6 (STM32_IRQ_FIRST+17) /* 17: DMA1 Stream 6 global interrupt */
|
||||
#define STM32_IRQ_ADC (STM32_IRQ_FIRST+18) /* 18: ADC1, ADC2, and ADC3 global interrupt */
|
||||
#define STM32_IRQ_CAN1TX (STM32_IRQ_FIRST+19) /* 19: CAN1 TX interrupts */
|
||||
#define STM32_IRQ_CAN1RX0 (STM32_IRQ_FIRST+20) /* 20: CAN1 RX0 interrupts */
|
||||
#define STM32_IRQ_CAN1RX1 (STM32_IRQ_FIRST+21) /* 21: CAN1 RX1 interrupt */
|
||||
#define STM32_IRQ_CAN1SCE (STM32_IRQ_FIRST+22) /* 22: CAN1 SCE interrupt */
|
||||
#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST+23) /* 23: EXTI Line[9:5] interrupts */
|
||||
#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST+24) /* 24: TIM1 Break interrupt */
|
||||
#define STM32_IRQ_TIM9 (STM32_IRQ_FIRST+24) /* 24: TIM9 global interrupt */
|
||||
#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST+25) /* 25: TIM1 Update interrupt */
|
||||
#define STM32_IRQ_TIM10 (STM32_IRQ_FIRST+25) /* 25: TIM10 global interrupt */
|
||||
#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST+26) /* 26: TIM1 Trigger and Commutation interrupts */
|
||||
#define STM32_IRQ_TIM11 (STM32_IRQ_FIRST+26) /* 26: TIM11 global interrupt */
|
||||
#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST+27) /* 27: TIM1 Capture Compare interrupt */
|
||||
#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST+28) /* 28: TIM2 global interrupt */
|
||||
#define STM32_IRQ_TIM3 (STM32_IRQ_FIRST+29) /* 29: TIM3 global interrupt */
|
||||
#define STM32_IRQ_TIM4 (STM32_IRQ_FIRST+30) /* 30: TIM4 global interrupt */
|
||||
#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST+31) /* 31: I2C1 event interrupt */
|
||||
#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST+32) /* 32: I2C1 error interrupt */
|
||||
#define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST+33) /* 33: I2C2 event interrupt */
|
||||
#define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST+34) /* 34: I2C2 error interrupt */
|
||||
#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST+35) /* 35: SPI1 global interrupt */
|
||||
#define STM32_IRQ_SPI2 (STM32_IRQ_FIRST+36) /* 36: SPI2 global interrupt */
|
||||
#define STM32_IRQ_USART1 (STM32_IRQ_FIRST+37) /* 37: USART1 global interrupt */
|
||||
#define STM32_IRQ_USART2 (STM32_IRQ_FIRST+38) /* 38: USART2 global interrupt */
|
||||
#define STM32_IRQ_USART3 (STM32_IRQ_FIRST+39) /* 39: USART3 global interrupt */
|
||||
#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST+40) /* 40: EXTI Line[15:10] interrupts */
|
||||
#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST+41) /* 41: RTC alarm through EXTI line interrupt */
|
||||
#define STM32_IRQ_OTGFSWKUP (STM32_IRQ_FIRST+42) /* 42: USB On-The-Go FS Wakeup through EXTI line interrupt */
|
||||
#define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST+43) /* 43: TIM8 Break interrupt */
|
||||
#define STM32_IRQ_TIM12 (STM32_IRQ_FIRST+43) /* 43: TIM12 global interrupt */
|
||||
#define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST+44) /* 44: TIM8 Update interrupt */
|
||||
#define STM32_IRQ_TIM13 (STM32_IRQ_FIRST+44) /* 44: TIM13 global interrupt */
|
||||
#define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST+45) /* 45: TIM8 Trigger and Commutation interrupts */
|
||||
#define STM32_IRQ_TIM14 (STM32_IRQ_FIRST+45) /* 45: TIM14 global interrupt */
|
||||
#define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST+46) /* 46: TIM8 Capture Compare interrupt */
|
||||
#define STM32_IRQ_DMA1S7 (STM32_IRQ_FIRST+47) /* 47: DMA1 Stream 7 global interrupt */
|
||||
#define STM32_IRQ_FSMC (STM32_IRQ_FIRST+48) /* 48: FSMC global interrupt */
|
||||
#define STM32_IRQ_SDMMC1 (STM32_IRQ_FIRST+49) /* 49: SDMMC1 global interrupt */
|
||||
#define STM32_IRQ_TIM5 (STM32_IRQ_FIRST+50) /* 50: TIM5 global interrupt */
|
||||
#define STM32_IRQ_SPI3 (STM32_IRQ_FIRST+51) /* 51: SPI3 global interrupt */
|
||||
#define STM32_IRQ_UART4 (STM32_IRQ_FIRST+52) /* 52: UART4 global interrupt */
|
||||
#define STM32_IRQ_UART5 (STM32_IRQ_FIRST+53) /* 53: UART5 global interrupt */
|
||||
#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST+54) /* 54: TIM6 global interrupt */
|
||||
#define STM32_IRQ_DAC (STM32_IRQ_FIRST+54) /* 54: DAC1 and DAC2 underrun error interrupts */
|
||||
#define STM32_IRQ_TIM7 (STM32_IRQ_FIRST+55) /* 55: TIM7 global interrupt */
|
||||
#define STM32_IRQ_DMA2S0 (STM32_IRQ_FIRST+56) /* 56: DMA2 Stream 0 global interrupt */
|
||||
#define STM32_IRQ_DMA2S1 (STM32_IRQ_FIRST+57) /* 57: DMA2 Stream 1 global interrupt */
|
||||
#define STM32_IRQ_DMA2S2 (STM32_IRQ_FIRST+58) /* 58: DMA2 Stream 2 global interrupt */
|
||||
#define STM32_IRQ_DMA2S3 (STM32_IRQ_FIRST+59) /* 59: DMA2 Stream 3 global interrupt */
|
||||
#define STM32_IRQ_DMA2S4 (STM32_IRQ_FIRST+60) /* 60: DMA2 Stream 4 global interrupt */
|
||||
#define STM32_IRQ_ETH (STM32_IRQ_FIRST+61) /* 61: Ethernet global interrupt */
|
||||
#define STM32_IRQ_ETHWKUP (STM32_IRQ_FIRST+62) /* 62: Ethernet Wakeup through EXTI line interrupt */
|
||||
#define STM32_IRQ_CAN2TX (STM32_IRQ_FIRST+63) /* 63: CAN2 TX interrupts */
|
||||
#define STM32_IRQ_CAN2RX0 (STM32_IRQ_FIRST+64) /* 64: CAN2 RX0 interrupts */
|
||||
#define STM32_IRQ_CAN2RX1 (STM32_IRQ_FIRST+65) /* 65: CAN2 RX1 interrupt */
|
||||
#define STM32_IRQ_CAN2SCE (STM32_IRQ_FIRST+66) /* 66: CAN2 SCE interrupt */
|
||||
#define STM32_IRQ_OTGFS (STM32_IRQ_FIRST+67) /* 67: USB On The Go FS global interrupt */
|
||||
#define STM32_IRQ_DMA2S5 (STM32_IRQ_FIRST+68) /* 68: DMA2 Stream 5 global interrupt */
|
||||
#define STM32_IRQ_DMA2S6 (STM32_IRQ_FIRST+69) /* 69: DMA2 Stream 6 global interrupt */
|
||||
#define STM32_IRQ_DMA2S7 (STM32_IRQ_FIRST+70) /* 70: DMA2 Stream 7 global interrupt */
|
||||
#define STM32_IRQ_USART6 (STM32_IRQ_FIRST+71) /* 71: USART6 global interrupt */
|
||||
#define STM32_IRQ_I2C3EV (STM32_IRQ_FIRST+72) /* 72: I2C3 event interrupt */
|
||||
#define STM32_IRQ_I2C3ER (STM32_IRQ_FIRST+73) /* 73: I2C3 error interrupt */
|
||||
#define STM32_IRQ_OTGHSEP1OUT (STM32_IRQ_FIRST+74) /* 74: USB On The Go HS End Point 1 Out global interrupt */
|
||||
#define STM32_IRQ_OTGHSEP1IN (STM32_IRQ_FIRST+75) /* 75: USB On The Go HS End Point 1 In global interrupt */
|
||||
#define STM32_IRQ_OTGHSWKUP (STM32_IRQ_FIRST+76) /* 76: USB On The Go HS Wakeup through EXTI interrupt */
|
||||
#define STM32_IRQ_OTGHS (STM32_IRQ_FIRST+77) /* 77: USB On The Go HS global interrupt */
|
||||
#define STM32_IRQ_DCMI (STM32_IRQ_FIRST+78) /* 78: DCMI global interrupt */
|
||||
#define STM32_IRQ_CRYP (STM32_IRQ_FIRST+79) /* 79: CRYP crypto global interrupt */
|
||||
#define STM32_IRQ_HASH (STM32_IRQ_FIRST+80) /* 80: Hash and Rng global interrupt */
|
||||
#define STM32_IRQ_RNG (STM32_IRQ_FIRST+80) /* 80: Hash and Rng global interrupt */
|
||||
#define STM32_IRQ_FPU (STM32_IRQ_FIRST+81) /* 81: FPU global interrupt */
|
||||
#define STM32_IRQ_UART7 (STM32_IRQ_FIRST+82) /* 82: UART7 global interrupt */
|
||||
#define STM32_IRQ_UART8 (STM32_IRQ_FIRST+83) /* 83: UART8 global interrupt */
|
||||
#define STM32_IRQ_SPI4 (STM32_IRQ_FIRST+84) /* 84: SPI4 global interrupt */
|
||||
#define STM32_IRQ_SPI5 (STM32_IRQ_FIRST+85) /* 85: SPI5 global interrupt */
|
||||
#define STM32_IRQ_SPI6 (STM32_IRQ_FIRST+86) /* 86: SPI6 global interrupt */
|
||||
#define STM32_IRQ_SAI1 (STM32_IRQ_FIRST+87) /* 87: SAI1 global interrupt */
|
||||
#define STM32_IRQ_LTDCINT (STM32_IRQ_FIRST+88) /* 88: LCD-TFT global interrupt */
|
||||
#define STM32_IRQ_LTDCERRINT (STM32_IRQ_FIRST+89) /* 89: LCD-TFT global Error interrupt */
|
||||
#define STM32_IRQ_DMA2D (STM32_IRQ_FIRST+90) /* 90: DMA2D global interrupt */
|
||||
#define STM32_IRQ_SAI2 (STM32_IRQ_FIRST+91) /* 91: SAI2 global interrupt */
|
||||
#define STM32_IRQ_QUADSPI (STM32_IRQ_FIRST+92) /* 92: QuadSPI global interrupt */
|
||||
#define STM32_IRQ_LPTIMER1 (STM32_IRQ_FIRST+93) /* 93: LP Timer1 global interrupt */
|
||||
#define STM32_IRQ_HDMICEC (STM32_IRQ_FIRST+94) /* 94: HDMI-CEC global interrupt */
|
||||
#define STM32_IRQ_I2C4EV (STM32_IRQ_FIRST+95) /* 95: I2C4 event interrupt */
|
||||
#define STM32_IRQ_I2C4ER (STM32_IRQ_FIRST+96) /* 96: I2C4 Error interrupt */
|
||||
#define STM32_IRQ_SPDIFRX (STM32_IRQ_FIRST+97) /* 97: SPDIFRX global interrupt */
|
||||
#define STM32_IRQ_DSIHOST (STM32_IRQ_FIRST+98) /* 98: DSI host global interrupt */
|
||||
#define STM32_IRQ_DFSDM1FLT0 (STM32_IRQ_FIRST+99) /* 99: DFSDM1 Filter 0 global interrupt */
|
||||
#define STM32_IRQ_DFSDM1FLT1 (STM32_IRQ_FIRST+100) /* 100: DFSDM1 Filter 1 global interrupt */
|
||||
#define STM32_IRQ_DFSDM1FLT2 (STM32_IRQ_FIRST+101) /* 101: DFSDM1 Filter 2 global interrupt */
|
||||
#define STM32_IRQ_DFSDM1FLT3 (STM32_IRQ_FIRST+102) /* 102: DFSDM1 Filter 3 global interrupt */
|
||||
#define STM32_IRQ_SDMMC2 (STM32_IRQ_FIRST+103) /* 103: SDMMC2 global interrupt */
|
||||
#define STM32_IRQ_CAN3TX (STM32_IRQ_FIRST+104) /* 104: CAN3 TX interrupt */
|
||||
#define STM32_IRQ_CAN3RX0 (STM32_IRQ_FIRST+105) /* 105: CAN3 RX0 interrupt */
|
||||
#define STM32_IRQ_CAN3RX1 (STM32_IRQ_FIRST+106) /* 106: CAN3 RX1 interrupt */
|
||||
#define STM32_IRQ_CAN3SCE (STM32_IRQ_FIRST+107) /* 107: CAN3 SCE interrupt */
|
||||
#define STM32_IRQ_JPEG (STM32_IRQ_FIRST+108) /* 108: JPEG global interrupt */
|
||||
#define STM32_IRQ_MDIOS (STM32_IRQ_FIRST+109) /* 109: MDIO slave global interrupt */
|
||||
|
||||
#define NR_INTERRUPTS 110
|
||||
#define NR_VECTORS (STM32_IRQ_FIRST+NR_INTERRUPTS)
|
||||
|
||||
/* EXTI interrupts (Do not use IRQ numbers) */
|
||||
|
||||
#define NR_IRQS NR_VECTORS
|
||||
|
||||
/****************************************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************************************/
|
||||
|
||||
/****************************************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#ifdef __cplusplus
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/****************************************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************************************/
|
||||
|
||||
#undef EXTERN
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#endif /* __ARCH_ARM_INCLUDE_STM32F7_STM32F76XX77XX_IRQ_H */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,7 +1,7 @@
|
||||
/********************************************************************************************
|
||||
* arch/arm/src/kinetis/kinetis_usbotg.h
|
||||
*
|
||||
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@@ -217,6 +217,8 @@
|
||||
#define USB_INT_ATTACH (1 << 6) /* Bit 6: Attach Interrupt */
|
||||
#define USB_INT_STALL (1 << 7) /* Bit 7: Stall Interrupt */
|
||||
|
||||
#define USB_INT_ALL 0xFF
|
||||
|
||||
/* Error Interrupt Status Register and Error Interrupt Enable Register (8-bit) */
|
||||
|
||||
#define USB_ERRSTAT_PIDERR (1 << 0) /* Bit 0: This bit is set when the PID check field fails */
|
||||
@@ -228,6 +230,8 @@
|
||||
/* Bit 6: Reserved */
|
||||
#define USB_ERRSTAT_BTSERR (1 << 7) /* Bit 7: Bit stuff error is detected */
|
||||
|
||||
#define USB_EINT_ALL 0xBF
|
||||
|
||||
/* Status Register (8-bit) */
|
||||
|
||||
/* Bits 0-1: Reserved */
|
||||
@@ -259,6 +263,7 @@
|
||||
#define USB_BDTPAGE1_MASK (0x7f << USB_BDTPAGE1_SHIFT)
|
||||
|
||||
/* Frame Number Register Low (8-bit, bits 0-7 of the 11 bit frame number) */
|
||||
#define USB_FRMNUML_MASK 0xFF
|
||||
/* Frame Number Register High (8-bit) */
|
||||
/* Bits 3-7: Reserved */
|
||||
#define USB_FRMNUMH_SHIFT (0) /* Bits 0-2: Bits 8-10 of the 11-bit frame number */
|
||||
@@ -313,16 +318,58 @@
|
||||
#define USB_USBTRC0_SYNC_DET (1 << 1) /* Bit 1: Synchronous USB Interrupt Detect */
|
||||
#define USB_USBTRC0_RESUME_INT (1 << 0) /* Bit 0: USB Asynchronous Interrupt */
|
||||
|
||||
/********************************************************************************************
|
||||
* Public Types
|
||||
********************************************************************************************/
|
||||
/* Buffer Descriptor Table (BDT) ****************************************************/
|
||||
/* Offset 0: On write (software->hardware) */
|
||||
|
||||
/********************************************************************************************
|
||||
* Public Data
|
||||
********************************************************************************************/
|
||||
#define USB_BDT_STATUS_MASK 0xfc /* Bits 2-7: Status bits */
|
||||
#define USB_BDT_BSTALL (1 << 2) /* Bit 2: Buffer Stall Enable bit */
|
||||
#define USB_BDT_DTS (1 << 3) /* Bit 3: Data Toggle Synchronization Enable bit */
|
||||
#define USB_BDT_NINC (1 << 4) /* Bit 4: DMA Address Increment Disable bit */
|
||||
#define USB_BDT_KEEP (1 << 5) /* Bit 5: BD Keep Enable bit */
|
||||
#define USB_BDT_DATA01 (1 << 6) /* Bit 6: Data Toggle Packet bit */
|
||||
#define USB_BDT_UOWN (1 << 7) /* Bit 7: USB Own bit */
|
||||
#define USB_BDT_BYTECOUNT_SHIFT (16) /* Bits 16-25: Byte Count bits */
|
||||
#define USB_BDT_BYTECOUNT_MASK (0x3ff << USB_BDT_BYTECOUNT_SHIFT)
|
||||
|
||||
#define USB_BDT_DATA0 0 /* DATA0 packet expected next */
|
||||
#define USB_BDT_DATA1 USB_BDT_DATA01 /* DATA1 packet expected next */
|
||||
#define USB_BDT_COWN 0 /* CPU owns the descriptor */
|
||||
|
||||
/* Offset 0: On read (hardware->software) */
|
||||
|
||||
#define USB_BDT_PID_SHIFT (2) /* Bits 2-5: Packet Identifier bits */
|
||||
#define USB_BDT_PID_MASK (15 << USB_BDT_PID_SHIFT)
|
||||
/* Bit 7: USB Own bit (same) */
|
||||
/* Bits 16-25: Byte Count bits (same) */
|
||||
|
||||
/* Offset 4: BUFFER_ADDRESS, 32-bit Buffer Address bits */
|
||||
|
||||
#define USB_BDT_BYTES_SIZE 8 /* Eight bytes per BDT */
|
||||
#define USB_BDT_WORD_SIZE 2 /* Two 32-bit words per BDT */
|
||||
#define USB_NBDTS_PER_EP 4 /* Number of BDTS per endpoint: IN/OUT and EVEN/ODD */
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/* Buffer Descriptor Status Register layout. */
|
||||
|
||||
struct usbotg_bdtentry_s
|
||||
{
|
||||
uint32_t status; /* Status, byte count, and PID */
|
||||
uint8_t *addr; /* Buffer address */
|
||||
};
|
||||
#endif
|
||||
|
||||
/********************************************************************************************
|
||||
* Public Functions
|
||||
********************************************************************************************/
|
||||
|
||||
struct usbdev_s;
|
||||
int kinetis_usbpullup(FAR struct usbdev_s *dev, bool enable);
|
||||
void kinetis_usbsuspend(FAR struct usbdev_s *dev, bool resume);
|
||||
void khci_usbattach(void);
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_USBOTG_H */
|
||||
|
||||
@@ -484,6 +484,16 @@ config ARCH_CHIP_STM32F105VB
|
||||
select STM32_HAVE_I2C2
|
||||
select STM32_HAVE_TIM4
|
||||
|
||||
config ARCH_CHIP_STM32F105RB
|
||||
bool "STM32F105RB"
|
||||
select ARCH_CORTEXM3
|
||||
select STM32_STM32F10XX
|
||||
select STM32_CONNECTIVITYLINE
|
||||
select STM32_HAVE_DAC1
|
||||
select STM32_HAVE_DAC2
|
||||
select STM32_HAVE_I2C2
|
||||
select STM32_HAVE_TIM4
|
||||
|
||||
config ARCH_CHIP_STM32F107VC
|
||||
bool "STM32F107VC"
|
||||
select ARCH_CORTEXM3
|
||||
|
||||
@@ -109,6 +109,9 @@
|
||||
# elif defined(CONFIG_ARCH_CHIP_STM32F105VB)
|
||||
# include "chip/stm32f105v_pinmap.h"
|
||||
|
||||
# elif defined(CONFIG_ARCH_CHIP_STM32F105RB)
|
||||
# include "chip/stm32f105r_pinmap.h"
|
||||
|
||||
# elif defined(CONFIG_ARCH_CHIP_STM32F107VC)
|
||||
# include "chip/stm32f107v_pinmap.h"
|
||||
# else
|
||||
|
||||
@@ -0,0 +1,328 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32/chip/stm32f105r_pinmap.h
|
||||
*
|
||||
* Copyright (C) 2009, 2011, 2014, 2016 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F105R_PINMAP_H
|
||||
#define __ARCH_ARM_SRC_STM32_CHIP_STM32F105R_PINMAP_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "stm32_gpio.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Alternate Pin Functions: */
|
||||
|
||||
#define GPIO_ADC12_IN0 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0)
|
||||
#define GPIO_ADC12_IN1 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN1)
|
||||
#define GPIO_ADC12_IN10 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN0)
|
||||
#define GPIO_ADC12_IN11 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN1)
|
||||
#define GPIO_ADC12_IN12 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN2)
|
||||
#define GPIO_ADC12_IN13 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN3)
|
||||
#define GPIO_ADC12_IN14 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN4)
|
||||
#define GPIO_ADC12_IN15 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN5)
|
||||
#define GPIO_ADC12_IN2 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN2)
|
||||
#define GPIO_ADC12_IN3 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN3)
|
||||
#define GPIO_ADC12_IN4 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN4)
|
||||
#define GPIO_ADC12_IN5 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN5)
|
||||
#define GPIO_ADC12_IN6 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN6)
|
||||
#define GPIO_ADC12_IN7 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN7)
|
||||
#define GPIO_ADC12_IN8 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN0)
|
||||
#define GPIO_ADC12_IN9 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN1)
|
||||
|
||||
#if defined(CONFIG_STM32_CAN1_REMAP1)
|
||||
# define GPIO_CAN1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN8)
|
||||
# define GPIO_CAN1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN9)
|
||||
#else
|
||||
# define GPIO_CAN1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN11)
|
||||
# define GPIO_CAN1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN12)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_CAN2_REMAP)
|
||||
# define GPIO_CAN2_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN5)
|
||||
# define GPIO_CAN2_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN6)
|
||||
#else
|
||||
# define GPIO_CAN2_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN12)
|
||||
# define GPIO_CAN2_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN13)
|
||||
#endif
|
||||
|
||||
#if 0 /* Needs further investigation */
|
||||
#define GPIO_DAC_OUT1 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN4)
|
||||
#define GPIO_DAC_OUT2 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN5)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_I2C1_REMAP)
|
||||
# define GPIO_I2C1_SCL (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN8)
|
||||
# define GPIO_I2C1_SDA (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN9)
|
||||
#else
|
||||
# define GPIO_I2C1_SCL (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN6)
|
||||
# define GPIO_I2C1_SDA (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN7)
|
||||
#endif
|
||||
#define GPIO_I2C1_SMBA (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN5)
|
||||
|
||||
#define GPIO_I2C2_SCL (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN10)
|
||||
#define GPIO_I2C2_SDA (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN11)
|
||||
#define GPIO_I2C2_SMBA (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN12)
|
||||
#define GPIO_I2S2_CK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN13)
|
||||
#define GPIO_I2S2_MCK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN6)
|
||||
#define GPIO_I2S2_WS (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN12)
|
||||
|
||||
#define GPIO_I2S3_CK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN3)
|
||||
#define GPIO_I2S3_MCK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN7)
|
||||
#define GPIO_I2S3_SD (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN5)
|
||||
#define GPIO_I2S3_WS (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN15)
|
||||
|
||||
#define GPIO_MCO (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN8)
|
||||
|
||||
#define GPIO_OTGFS_DM (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN11)
|
||||
#define GPIO_OTGFS_DP (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN12)
|
||||
#define GPIO_OTGFS_ID (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN10)
|
||||
#define GPIO_OTGFS_SOF (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN8)
|
||||
#define GPIO_OTGFS_VBUS (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN9)
|
||||
|
||||
#if defined(CONFIG_STM32_SPI1_REMAP)
|
||||
# define GPIO_SPI1_NSS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN15)
|
||||
# define GPIO_SPI1_SCK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN3)
|
||||
# define GPIO_SPI1_MISO (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN4)
|
||||
# define GPIO_SPI1_MOSI (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN5)
|
||||
#else
|
||||
# define GPIO_SPI1_NSS (GPIO_INPUT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN4)
|
||||
# define GPIO_SPI1_SCK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN5)
|
||||
# define GPIO_SPI1_MISO (GPIO_INPUT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN6)
|
||||
# define GPIO_SPI1_MOSI (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN7)
|
||||
#endif
|
||||
|
||||
#define GPIO_SPI2_NSS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN12)
|
||||
#define GPIO_SPI2_SCK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN13)
|
||||
#define GPIO_SPI2_MISO (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN14)
|
||||
#define GPIO_SPI2_MOSI (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN15)
|
||||
|
||||
#if defined(CONFIG_STM32_SPI3_REMAP)
|
||||
# define GPIO_SPI3_NSS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN4)
|
||||
# define GPIO_SPI3_SCK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN10)
|
||||
# define GPIO_SPI3_MISO (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN11)
|
||||
# define GPIO_SPI3_MOSI (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN12)
|
||||
#else
|
||||
# define GPIO_SPI3_NSS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN15)
|
||||
# define GPIO_SPI3_SCK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN3)
|
||||
# define GPIO_SPI3_MISO (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN4)
|
||||
# define GPIO_SPI3_MOSI (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN5)
|
||||
#endif
|
||||
|
||||
#if 0 /* Needs further investigation */
|
||||
#define GPIO_TAMPER_RTC (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN13)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_TIM1_PARTIAL_REMAP)
|
||||
# define GPIO_TIM1_ETR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN12)
|
||||
# define GPIO_TIM1_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN8)
|
||||
# define GPIO_TIM1_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN8)
|
||||
# define GPIO_TIM1_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN9)
|
||||
# define GPIO_TIM1_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN9)
|
||||
# define GPIO_TIM1_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN10)
|
||||
# define GPIO_TIM1_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN10)
|
||||
# define GPIO_TIM1_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN11)
|
||||
# define GPIO_TIM1_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN11)
|
||||
# define GPIO_TIM1_BKIN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN6)
|
||||
# define GPIO_TIM1_CH1N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN7)
|
||||
# define GPIO_TIM1_CH2N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN0)
|
||||
# define GPIO_TIM1_CH3N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN1)
|
||||
#else
|
||||
# define GPIO_TIM1_ETR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN12)
|
||||
# define GPIO_TIM1_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN8)
|
||||
# define GPIO_TIM1_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN8)
|
||||
# define GPIO_TIM1_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN9)
|
||||
# define GPIO_TIM1_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN9)
|
||||
# define GPIO_TIM1_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN10)
|
||||
# define GPIO_TIM1_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN10)
|
||||
# define GPIO_TIM1_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN11)
|
||||
# define GPIO_TIM1_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN11)
|
||||
# define GPIO_TIM1_BKIN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN12)
|
||||
# define GPIO_TIM1_CH1N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN13)
|
||||
# define GPIO_TIM1_CH2N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN14)
|
||||
# define GPIO_TIM1_CH3N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN15)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_TIM2_FULL_REMAP)
|
||||
# define GPIO_TIM2_ETR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN15)
|
||||
# define GPIO_TIM2_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN15)
|
||||
# define GPIO_TIM2_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN15)
|
||||
# define GPIO_TIM2_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN3)
|
||||
# define GPIO_TIM2_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN3)
|
||||
# define GPIO_TIM2_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN10)
|
||||
# define GPIO_TIM2_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN10)
|
||||
# define GPIO_TIM2_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN11)
|
||||
# define GPIO_TIM2_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN11)
|
||||
#elif defined(CONFIG_STM32_TIM2_PARTIAL_REMAP_1)
|
||||
# define GPIO_TIM2_ETR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN15)
|
||||
# define GPIO_TIM2_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN15)
|
||||
# define GPIO_TIM2_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN15)
|
||||
# define GPIO_TIM2_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN3)
|
||||
# define GPIO_TIM2_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN3)
|
||||
# define GPIO_TIM2_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN2)
|
||||
# define GPIO_TIM2_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN2)
|
||||
# define GPIO_TIM2_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN3)
|
||||
# define GPIO_TIM2_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN3)
|
||||
#elif defined(CONFIG_STM32_TIM2_PARTIAL_REMAP_2)
|
||||
# define GPIO_TIM2_ETR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0)
|
||||
# define GPIO_TIM2_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0)
|
||||
# define GPIO_TIM2_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN0)
|
||||
# define GPIO_TIM2_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN1)
|
||||
# define GPIO_TIM2_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN1)
|
||||
# define GPIO_TIM2_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN10)
|
||||
# define GPIO_TIM2_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN10)
|
||||
# define GPIO_TIM2_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN11)
|
||||
# define GPIO_TIM2_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN11)
|
||||
#else
|
||||
# define GPIO_TIM2_ETR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0)
|
||||
# define GPIO_TIM2_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0)
|
||||
# define GPIO_TIM2_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN0)
|
||||
# define GPIO_TIM2_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN1)
|
||||
# define GPIO_TIM2_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN1)
|
||||
# define GPIO_TIM2_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN2)
|
||||
# define GPIO_TIM2_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN2)
|
||||
# define GPIO_TIM2_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN3)
|
||||
# define GPIO_TIM2_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN3)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_TIM3_FULL_REMAP)
|
||||
# define GPIO_TIM3_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN6)
|
||||
# define GPIO_TIM3_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN6)
|
||||
# define GPIO_TIM3_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN7)
|
||||
# define GPIO_TIM3_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN7)
|
||||
# define GPIO_TIM3_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN8)
|
||||
# define GPIO_TIM3_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN8)
|
||||
# define GPIO_TIM3_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN9)
|
||||
# define GPIO_TIM3_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN9)
|
||||
#elif defined(CONFIG_STM32_TIM3_PARTIAL_REMAP)
|
||||
# define GPIO_TIM3_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN4)
|
||||
# define GPIO_TIM3_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN4)
|
||||
# define GPIO_TIM3_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN5)
|
||||
# define GPIO_TIM3_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN5)
|
||||
# define GPIO_TIM3_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN0)
|
||||
# define GPIO_TIM3_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN0)
|
||||
# define GPIO_TIM3_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN1)
|
||||
# define GPIO_TIM3_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN1)
|
||||
#else
|
||||
# define GPIO_TIM3_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN6)
|
||||
# define GPIO_TIM3_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN6)
|
||||
# define GPIO_TIM3_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN7)
|
||||
# define GPIO_TIM3_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN7)
|
||||
# define GPIO_TIM3_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN0)
|
||||
# define GPIO_TIM3_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN0)
|
||||
# define GPIO_TIM3_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN1)
|
||||
# define GPIO_TIM3_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN1)
|
||||
#endif
|
||||
#define GPIO_TIM3_ETR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTD|GPIO_PIN2)
|
||||
|
||||
#define GPIO_TIM4_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN6)
|
||||
#define GPIO_TIM4_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN6)
|
||||
#define GPIO_TIM4_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN7)
|
||||
#define GPIO_TIM4_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN7)
|
||||
#define GPIO_TIM4_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN8)
|
||||
#define GPIO_TIM4_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN8)
|
||||
#define GPIO_TIM4_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN9)
|
||||
#define GPIO_TIM4_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN9)
|
||||
|
||||
#define GPIO_TIM5_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0)
|
||||
#define GPIO_TIM5_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN0)
|
||||
#define GPIO_TIM5_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN1)
|
||||
#define GPIO_TIM5_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN1)
|
||||
#define GPIO_TIM5_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN2)
|
||||
#define GPIO_TIM5_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN2)
|
||||
#define GPIO_TIM5_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN3)
|
||||
#define GPIO_TIM5_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN3)
|
||||
|
||||
#if 0 /* Needs further investigation */
|
||||
#if defined(CONFIG_STM32_TRACESWO_REMAP)
|
||||
# define GPIO_TRACESWO (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN3)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#define GPIO_USART1_CTS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN11)
|
||||
#define GPIO_USART1_RTS (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN12)
|
||||
#define GPIO_USART1_CK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN8)
|
||||
#if defined(CONFIG_STM32_USART1_REMAP)
|
||||
# define GPIO_USART1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN9)
|
||||
# define GPIO_USART1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN10)
|
||||
#else
|
||||
# define GPIO_USART1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN9)
|
||||
# define GPIO_USART1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN10)
|
||||
#endif
|
||||
|
||||
#define GPIO_USART2_CTS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0)
|
||||
#define GPIO_USART2_RTS (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN1)
|
||||
#define GPIO_USART2_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN2)
|
||||
#define GPIO_USART2_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN3)
|
||||
#define GPIO_USART2_CK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN4)
|
||||
|
||||
#if defined(CONFIG_STM32_USART3_PARTIAL_REMAP)
|
||||
# define GPIO_USART3_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN10)
|
||||
# define GPIO_USART3_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN11)
|
||||
# define GPIO_USART3_CK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN12)
|
||||
# define GPIO_USART3_CTS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN13)
|
||||
# define GPIO_USART3_RTS (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN14)
|
||||
#else
|
||||
# define GPIO_USART3_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN10)
|
||||
# define GPIO_USART3_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN11)
|
||||
# define GPIO_USART3_CK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN12)
|
||||
# define GPIO_USART3_CTS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN13)
|
||||
# define GPIO_USART3_RTS (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN14)
|
||||
#endif
|
||||
|
||||
#define GPIO_UART4_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN11)
|
||||
#define GPIO_UART4_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN10)
|
||||
|
||||
#define GPIO_UART5_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTD|GPIO_PIN2)
|
||||
#define GPIO_UART5_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN12)
|
||||
|
||||
#define GPIO_WKUP (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN0)
|
||||
|
||||
/* Some GPIOs are accessible only as remapped, alternate functions */
|
||||
|
||||
#if 0 /* Needs further investigation */
|
||||
#define GPIO_PA13 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN13)
|
||||
#define GPIO_PA14 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN14)
|
||||
#define GPIO_PA15 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN15)
|
||||
#define GPIO_PB3 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN3)
|
||||
#define GPIO_PB4 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN4)
|
||||
#endif
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F105R_PINMAP_H */
|
||||
@@ -91,44 +91,6 @@
|
||||
#define GPIO_DAC_OUT2 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN5)
|
||||
#endif
|
||||
|
||||
#if 0 /* Needs further investigation */
|
||||
#define GPIO_ETH_MDC (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN1)
|
||||
#define GPIO_ETH_MDIO (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN2)
|
||||
#define GPIO_ETH_MIICOL (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN3)
|
||||
#define GPIO_ETH_MIICRSWKUP (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN0)
|
||||
#define GPIO_ETH_MIIRXCLK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN1)
|
||||
|
||||
#if defined(CONFIG_STM32_ETH_REMAP)
|
||||
# define GPIO_ETH_MIIRXD0 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN9)
|
||||
# define GPIO_ETH_MIIRXD1 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN10)
|
||||
# define GPIO_ETH_MIIRXD2 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN11)
|
||||
# define GPIO_ETH_MIIRXD3 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN12)
|
||||
# define GPIO_ETH_MIIRXDV (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN8)
|
||||
#else
|
||||
# define GPIO_ETH_MIIRXD0 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN4)
|
||||
# define GPIO_ETH_MIIRXD1 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN5)
|
||||
# define GPIO_ETH_MIIRXD2 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN0)
|
||||
# define GPIO_ETH_MIIRXD3 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN1)
|
||||
# define GPIO_ETH_MIIRXDV (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN7)
|
||||
#endif
|
||||
|
||||
#define GPIO_ETH_MIIRXER (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN10)
|
||||
#define GPIO_ETH_MIITXCLK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN3)
|
||||
#define GPIO_ETH_MIITXD0 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN12)
|
||||
#define GPIO_ETH_MIITXD1 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN13)
|
||||
#define GPIO_ETH_MIITXD2 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN2)
|
||||
#define GPIO_ETH_MIITXD3 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN8)
|
||||
#define GPIO_ETH_MIITXEN (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN11)
|
||||
#define GPIO_ETH_PPSOUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN5)
|
||||
#define GPIO_ETH_RMIICRSDV (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN7)
|
||||
#define GPIO_ETH_RMIIREFCLK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN1)
|
||||
#define GPIO_ETH_RMIIRXD0 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN4)
|
||||
#define GPIO_ETH_RMIIRXD1 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN5)
|
||||
#define GPIO_ETH_RMIITXD0 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN12)
|
||||
#define GPIO_ETH_RMIITXD1 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN13)
|
||||
#define GPIO_ETH_RMIITXEN (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN11)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_I2C1_REMAP)
|
||||
# define GPIO_I2C1_SCL (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN8)
|
||||
# define GPIO_I2C1_SDA (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN9)
|
||||
|
||||
+1005
-36
File diff suppressed because it is too large
Load Diff
@@ -2,7 +2,8 @@
|
||||
* arch/arm/src/stm32f7/chip/stm32_dma.h
|
||||
*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
@@ -45,6 +46,8 @@
|
||||
|
||||
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
|
||||
# include "chip/stm32f74xx75xx_dma.h"
|
||||
#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
|
||||
# include "chip/stm32f76xx77xx_dma.h"
|
||||
#else
|
||||
# error "Unsupported STM32 F7 part"
|
||||
#endif
|
||||
|
||||
@@ -2,7 +2,8 @@
|
||||
* arch/arm/src/stm32f7/chip/stm32_ethernet.h
|
||||
*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
@@ -46,7 +47,8 @@
|
||||
* families
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
|
||||
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) \
|
||||
defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
|
||||
|
||||
/****************************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
@@ -805,6 +807,6 @@ struct eth_rxdesc_s
|
||||
****************************************************************************************************/
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */
|
||||
#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX || CONFIG_STM32F7_STM32F76XX || CONFIG_STM32F7_STM32F77XX */
|
||||
#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32_ETHERNET_H */
|
||||
|
||||
|
||||
@@ -2,7 +2,8 @@
|
||||
* arch/arm/src/stm32f7/chip/stm32_exti.h
|
||||
*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
@@ -47,7 +48,8 @@
|
||||
* families
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
|
||||
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \
|
||||
defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
@@ -127,5 +129,5 @@
|
||||
#define EXTI_IMR_SHIFT (0) /* Bits 0-X: Pending bit for all lines */
|
||||
#define EXTI_IMR_MASK STM32_EXTI_MASK
|
||||
|
||||
#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */
|
||||
#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX || CONFIG_STM32F7_STM32F76XX || CONFIG_STM32F7_STM32F77XX */
|
||||
#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32_EXTI_H */
|
||||
|
||||
@@ -2,7 +2,8 @@
|
||||
* arch/arm/src/stm32f7/chip/stm32_flash.h
|
||||
*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
@@ -45,6 +46,8 @@
|
||||
|
||||
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
|
||||
# include "chip/stm32f74xx75xx_flash.h"
|
||||
#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
|
||||
# include "chip/stm32f76xx77xx_flash.h"
|
||||
#else
|
||||
# error "Unsupported STM32 F7 part"
|
||||
#endif
|
||||
|
||||
@@ -2,7 +2,8 @@
|
||||
* arch/arm/src/stm32f7/chip/stm32_gpio.h
|
||||
*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
@@ -45,6 +46,8 @@
|
||||
|
||||
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
|
||||
# include "chip/stm32f74xx75xx_gpio.h"
|
||||
#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
|
||||
# include "chip/stm32f76xx77xx_gpio.h"
|
||||
#else
|
||||
# error "Unsupported STM32 F7 part"
|
||||
#endif
|
||||
|
||||
@@ -2,7 +2,8 @@
|
||||
* arch/arm/src/stm32f7/chip/stm32_memorymap.h
|
||||
*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
@@ -45,6 +46,8 @@
|
||||
|
||||
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
|
||||
# include "chip/stm32f74xx75xx_memorymap.h"
|
||||
#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
|
||||
# include "chip/stm32f76xx77xx_memorymap.h"
|
||||
#else
|
||||
# error "Unsupported STM32 F7 memory map"
|
||||
#endif
|
||||
|
||||
@@ -2,7 +2,8 @@
|
||||
* arch/arm/src/stm32f7/chip/stm32_pinmap.h
|
||||
*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
@@ -45,8 +46,10 @@
|
||||
|
||||
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
|
||||
# include "chip/stm32f74xx75xx_pinmap.h"
|
||||
#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
|
||||
# include "chip/stm32f76xx77xx_pinmap.h"
|
||||
#else
|
||||
# error "Unsupported STM32 F7 memory map"
|
||||
# error "Unsupported STM32 F7 Pin map"
|
||||
#endif
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32_PINMAP_H */
|
||||
|
||||
@@ -2,7 +2,8 @@
|
||||
* arch/arm/src/stm32f7/chip/stm32_pwr.h
|
||||
*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
@@ -45,6 +46,8 @@
|
||||
|
||||
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
|
||||
# include "chip/stm32f74xx75xx_pwr.h"
|
||||
#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
|
||||
# include "chip/stm32f76xx77xx_pwr.h"
|
||||
#else
|
||||
# error "Unsupported STM32 F7 part"
|
||||
#endif
|
||||
|
||||
@@ -1,8 +1,8 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32f7/chip/stm32_rcc.h
|
||||
*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@uas.net>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
@@ -45,6 +45,8 @@
|
||||
|
||||
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
|
||||
# include "chip/stm32f74xx75xx_rcc.h"
|
||||
#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
|
||||
# include "chip/stm32f76xx77xx_rcc.h"
|
||||
#else
|
||||
# error "Unsupported STM32 F7 part"
|
||||
#endif
|
||||
|
||||
@@ -2,7 +2,8 @@
|
||||
* arch/arm/src/stm32f7/chip/stm32_syscfg.h
|
||||
*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@uas.net>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
@@ -45,6 +46,8 @@
|
||||
|
||||
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
|
||||
# include "chip/stm32f74xx75xx_syscfg.h"
|
||||
#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
|
||||
# include "chip/stm32f76xx77xx_syscfg.h"
|
||||
#else
|
||||
# error "Unsupported STM32 F7 part"
|
||||
#endif
|
||||
|
||||
@@ -1,8 +1,8 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32f7/chip/stm32_uart.h
|
||||
*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@uas.net>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
@@ -43,8 +43,9 @@
|
||||
#include <nuttx/config.h>
|
||||
#include "chip.h"
|
||||
|
||||
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
|
||||
# include "chip/stm32f74xx75xx_uart.h"
|
||||
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \
|
||||
defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
|
||||
# include "chip/stm32f74xx77xx_uart.h"
|
||||
#else
|
||||
# error "Unsupported STM32 F7 part"
|
||||
#endif
|
||||
|
||||
@@ -412,16 +412,16 @@
|
||||
#define DMAMAP_SPDIFRX_CS STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN0)
|
||||
#define DMAMAP_SPI3_TX_2 STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN0)
|
||||
|
||||
#define DMAMAP_I2C1_RX_1 STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN1)
|
||||
#define DMAMAP_I2C3_RX_1 STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN1)
|
||||
#define DMAMAP_I2C1_RX STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN1)
|
||||
#define DMAMAP_I2C3_RX STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN1)
|
||||
#define DMAMAP_TIM7_UP_1 STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN1)
|
||||
#define DMAMAP_TIM7_UP_2 STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN1)
|
||||
#define DMAMAP_I2C1_RX_2 STM32_DMA_MAP(DMA1,DMA_STREAM5,DMA_CHAN1)
|
||||
#define DMAMAP_I2C1_TX_1 STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN1)
|
||||
#define DMAMAP_I2C1_TX_2 STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN1)
|
||||
#define DMAMAP_I2C1_RX_1 STM32_DMA_MAP(DMA1,DMA_STREAM5,DMA_CHAN1)
|
||||
#define DMAMAP_I2C1_TX STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN1)
|
||||
#define DMAMAP_I2C1_TX_1 STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN1)
|
||||
|
||||
#define DMAMAP_TIM4_CH1 STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN2)
|
||||
#define DMAMAP_I2C_RX STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN2)
|
||||
#define DMAMAP_I2C4_RX STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN2)
|
||||
#define DMAMAP_TIM4_CH2 STM32_DMA_MAP(DMA1,DMA_STREAM3,DMA_CHAN2)
|
||||
#define DMAMAP_I2C4_TX STM32_DMA_MAP(DMA1,DMA_STREAM5,DMA_CHAN2)
|
||||
#define DMAMAP_TIM4_UP STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN2)
|
||||
@@ -429,7 +429,7 @@
|
||||
|
||||
#define DMAMAP_TIM2_UP_1 STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN3)
|
||||
#define DMAMAP_TIM2_CH3 STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN3)
|
||||
#define DMAMAP_I2C3_RX_2 STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN3)
|
||||
#define DMAMAP_I2C3_RX_1 STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN3)
|
||||
#define DMAMAP_I2C3_TX STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN3)
|
||||
#define DMAMAP_TIM2_CH1 STM32_DMA_MAP(DMA1,DMA_STREAM5,DMA_CHAN3)
|
||||
#define DMAMAP_TIM2_CH2 STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN3)
|
||||
@@ -468,8 +468,8 @@
|
||||
#define DMAMAP_TIM5_UP_2 STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN6)
|
||||
|
||||
#define DMAMAP_TIM6_UP STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN7)
|
||||
#define DMAMAP_I2C2_RX_1 STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN7)
|
||||
#define DMAMAP_I2C2_RX_2 STM32_DMA_MAP(DMA1,DMA_STREAM3,DMA_CHAN7)
|
||||
#define DMAMAP_I2C2_RX STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN7)
|
||||
#define DMAMAP_I2C2_RX_1 STM32_DMA_MAP(DMA1,DMA_STREAM3,DMA_CHAN7)
|
||||
#define DMAMAP_USART3_TX_2 STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN7)
|
||||
#define DMAMAP_DAC1 STM32_DMA_MAP(DMA1,DMA_STREAM5,DMA_CHAN7)
|
||||
#define DMAMAP_DAC2 STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN7)
|
||||
|
||||
@@ -2,7 +2,8 @@
|
||||
* arch/arm/src/stm32f7/chip/stm32f74xx75xx_flash.h
|
||||
*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
@@ -40,44 +41,62 @@
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Flash size is not known from the chip configuration:
|
||||
/* Flash size is known from the chip selection:
|
||||
*
|
||||
* When CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT is set the
|
||||
* CONFIG_STM32F7_FLASH_CONFIG_x selects the default FLASH size based on the chip
|
||||
* part number. This value can be overridden with CONFIG_STM32F7_FLASH_OVERRIDE_x
|
||||
*
|
||||
* Parts STM32F74xxE have 512Kb of FLASH
|
||||
* Parts STM32F74xxG have 1024Kb of FLASH
|
||||
*
|
||||
* The user has to tell us the FLASH size by setting CONFIG_STM32F7_FLASH_SIZE
|
||||
* N.B. Only Single bank mode is supported
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_STM32F7_FLASH_512KB)
|
||||
|
||||
# define STM32_FLASH_NPAGES 2
|
||||
# define STM32_FLASH_SIZE (512*1024)
|
||||
|
||||
#elif defined(CONFIG_STM32F7_FLASH_1024KB)
|
||||
|
||||
# define STM32_FLASH_NPAGES 4
|
||||
# define STM32_FLASH_SIZE (1024*1024)
|
||||
|
||||
#else
|
||||
# warning Assuming FLASH size 1024KB
|
||||
|
||||
# define STM32_FLASH_NPAGES 4
|
||||
# define STM32_FLASH_SIZE (1024*1024)
|
||||
#define _K(x) ((x)*1024)
|
||||
|
||||
#if !defined(CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT) && \
|
||||
!defined(CONFIG_STM32_FLASH_OVERRIDE_E) && \
|
||||
!defined(CONFIG_STM32_FLASH_OVERRIDE_F) && \
|
||||
!defined(CONFIG_STM32_FLASH_OVERRIDE_G) && \
|
||||
!defined(CONFIG_STM32_FLASH_CONFIG_E) && \
|
||||
!defined(CONFIG_STM32_FLASH_CONFIG_F) && \
|
||||
!defined(CONFIG_STM32_FLASH_CONFIG_G)
|
||||
# define CONFIG_STM32_FLASH_OVERRIDE_E
|
||||
# warning "Flash size not defined defaulting to 512KiB (E)"
|
||||
#endif
|
||||
|
||||
/* The STM32F745xx/46xx have mixed page sizes:
|
||||
*
|
||||
* Sectors: 0-3: 32 KB
|
||||
* Sector 4 128 KB
|
||||
* Sectors: 5-7: 256 KB
|
||||
*
|
||||
* We use the largest page size and set the number of pages equal to the
|
||||
* FLASH size assuming that fixed, largest pages size.
|
||||
*/
|
||||
#if !defined(CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT)
|
||||
|
||||
#define STM32_FLASH_PAGESIZE (256*1024)
|
||||
# undef CONFIG_STM32F7_FLASH_CONFIG_E
|
||||
# undef CONFIG_STM32F7_FLASH_CONFIG_G
|
||||
|
||||
# if defined(CONFIG_STM32F7_FLASH_OVERRIDE_E)
|
||||
|
||||
# define CONFIG_STM32F7_FLASH_CONFIG_E
|
||||
|
||||
# elif defined(CONFIG_STM32F7_FLASH_OVERRIDE_G)
|
||||
|
||||
# define CONFIG_STM32F7_FLASH_CONFIG_G
|
||||
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_FLASH_CONFIG_E)
|
||||
|
||||
# define STM32_FLASH_NPAGES 6
|
||||
# define STM32_FLASH_SIZE _K((4 * 32) + (1 * 128) + (1 * 256))
|
||||
# define STM32_FLASH_SIZES {_K(32), _K(32), _K(32), _K(32), \
|
||||
_K(128), _K(256)}
|
||||
|
||||
#elif defined(CONFIG_STM32_FLASH_CONFIG_G)
|
||||
|
||||
# define STM32_FLASH_NPAGES 8
|
||||
# define STM32_FLASH_SIZE _K((4 * 32) + (1 * 128) + (3 * 256))
|
||||
# define STM32_FLASH_SIZES {_K(32), _K(32), _K(32), _K(32), \
|
||||
_K(128), _K(256), _K(256), _K(256)}
|
||||
|
||||
#endif
|
||||
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
@@ -133,8 +152,8 @@
|
||||
#define FLASH_CR_SER (1 << 1) /* Bit 1: Sector Erase */
|
||||
#define FLASH_CR_MER (1 << 2) /* Bit 2: Mass Erase sectors 0..11 */
|
||||
#define FLASH_CR_SNB_SHIFT (3) /* Bits 3-6: Sector number */
|
||||
#define FLASH_CR_SNB_MASK (15 << FLASH_CR_SNB_SHIFT)
|
||||
# define FLASH_CR_SNB(n) ((uint32_t)(n) << FLASH_CR_SNB_SHIFT) | ((n / 12) << 7)) /* Sector n, n=0..23 */
|
||||
#define FLASH_CR_SNB_MASK (0xf << FLASH_CR_SNB_SHIFT)
|
||||
# define FLASH_CR_SNB(n) ((uint32_t)((n) % 8) << FLASH_CR_SNB_SHIFT) | ((n / 8) << 6)) /* Sector n, n=0..23 */
|
||||
#define FLASH_CR_PSIZE_SHIFT (8) /* Bits 8-9: Program size */
|
||||
#define FLASH_CR_PSIZE_MASK (3 << FLASH_CR_PSIZE_SHIFT)
|
||||
# define FLASH_CR_PSIZE_X8 (0 << FLASH_CR_PSIZE_SHIFT) /* Program x8 */
|
||||
@@ -145,7 +164,6 @@
|
||||
#define FLASH_CR_EOPIE (1 << 24) /* Bit 24: End of operation interrupt enable */
|
||||
#define FLASH_CR_ERRIE (1 << 25) /* Bit 25: Error interrupt enable */
|
||||
#define FLASH_CR_LOCK (1 << 31) /* Bit 31: Lock */
|
||||
#define FLASH_CR_MER1 (1 << 15) /* Bit 15: Mass Erase sectors 12..23 */
|
||||
|
||||
/* Flash Option Control Register (OPTCR) */
|
||||
|
||||
@@ -159,15 +177,15 @@
|
||||
# define FLASH_OPTCR_VBOR0 (3 << FLASH_OPTCR_BORLEV_SHIFT) /* BOR off */
|
||||
#define FLASH_OPTCR_USER_SHIFT (4) /* Bits 5-7: User option bytes */
|
||||
#define FLASH_OPTCR_USER_MASK (15 << FLASH_OPTCR_USER_SHIFT)
|
||||
# define FLASH_OPTCR_WWDG_SW (1 << 4) /* Bit 5: WWDG_SW */
|
||||
# define FLASH_OPTCR_WWDG_SW (1 << 4) /* Bit 4: WWDG_SW */
|
||||
# define FLASH_OPTCR_IWDG_SW (1 << 5) /* Bit 5: IWDG_SW */
|
||||
# define FLASH_OPTCR_NRST_STOP (1 << 6) /* Bit 6: nRST_STOP */
|
||||
# define FLASH_OPTCR_NRST_STDBY (1 << 7) /* Bit 7: nRST_STDBY */
|
||||
#define FLASH_OPTCR_RDP_SHIFT (8) /* Bits 8-15: Read protect */
|
||||
#define FLASH_OPTCR_RDP_MASK (0xff << FLASH_OPTCR_RDP_SHIFT)
|
||||
# define FLASH_OPTCR_RDP(n) ((uint32_t)(n) << FLASH_OPTCR_RDP_SHIFT)
|
||||
#define FLASH_OPTCR_NWRP_SHIFT (16) /* Bits 16-27: Not write protect */
|
||||
#define FLASH_OPTCR_NWRP_MASK (0xfff << FLASH_OPTCR_NWRP_SHIFT)
|
||||
#define FLASH_OPTCR_NWRP_SHIFT (16) /* Bits 16-23: Not write protect */
|
||||
#define FLASH_OPTCR_NWRP_MASK (0xff << FLASH_OPTCR_NWRP_SHIFT)
|
||||
# define FLASH_OPTCR_NWRP(n) ((uint32_t)(n) << FLASH_OPTCR_NWRP_SHIFT)
|
||||
#define FLASH_OPTCR_IWDG_STDBY (1 << 30) /* Bit 30: IWDG freeze in stop mode */
|
||||
#define FLASH_OPTCR_IWDG_STOP (1 << 31) /* Bit 31: IWDG freeze in standby mode */
|
||||
|
||||
@@ -61,7 +61,6 @@
|
||||
#define STM32_GPIO_LCKR_OFFSET 0x001c /* GPIO port configuration lock register */
|
||||
#define STM32_GPIO_AFRL_OFFSET 0x0020 /* GPIO alternate function low register */
|
||||
#define STM32_GPIO_AFRH_OFFSET 0x0024 /* GPIO alternate function high register */
|
||||
#define STM32_GPIO_BRR_OFFSET 0x0028 /* GPIO port bit reset register */
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
@@ -76,7 +75,6 @@
|
||||
# define STM32_GPIOA_LCKR (STM32_GPIOA_BASE+STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOA_AFRL (STM32_GPIOA_BASE+STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOA_AFRH (STM32_GPIOA_BASE+STM32_GPIO_AFRH_OFFSET)
|
||||
# define STM32_GPIOA_BRR (STM32_GPIOA_BASE+STM32_GPIO_BRR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32F7_NGPIO > 1
|
||||
@@ -90,7 +88,6 @@
|
||||
# define STM32_GPIOB_LCKR (STM32_GPIOB_BASE+STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOB_AFRL (STM32_GPIOB_BASE+STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOB_AFRH (STM32_GPIOB_BASE+STM32_GPIO_AFRH_OFFSET)
|
||||
# define STM32_GPIOB_BRR (STM32_GPIOB_BASE+STM32_GPIO_BRR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32F7_NGPIO > 2
|
||||
@@ -104,7 +101,6 @@
|
||||
# define STM32_GPIOC_LCKR (STM32_GPIOC_BASE+STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOC_AFRL (STM32_GPIOC_BASE+STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOC_AFRH (STM32_GPIOC_BASE+STM32_GPIO_AFRH_OFFSET)
|
||||
# define STM32_GPIOC_BRR (STM32_GPIOC_BASE+STM32_GPIO_BRR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32F7_NGPIO > 3
|
||||
@@ -118,7 +114,6 @@
|
||||
# define STM32_GPIOD_LCKR (STM32_GPIOD_BASE+STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOD_AFRL (STM32_GPIOD_BASE+STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOD_AFRH (STM32_GPIOD_BASE+STM32_GPIO_AFRH_OFFSET)
|
||||
# define STM32_GPIOD_BRR (STM32_GPIOD_BASE+STM32_GPIO_BRR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32F7_NGPIO > 4
|
||||
@@ -132,7 +127,6 @@
|
||||
# define STM32_GPIOE_LCKR (STM32_GPIOE_BASE+STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOE_AFRL (STM32_GPIOE_BASE+STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOE_AFRH (STM32_GPIOE_BASE+STM32_GPIO_AFRH_OFFSET)
|
||||
# define STM32_GPIOE_BRR (STM32_GPIOE_BASE+STM32_GPIO_BRR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32F7_NGPIO > 5
|
||||
@@ -146,7 +140,6 @@
|
||||
# define STM32_GPIOF_LCKR (STM32_GPIOF_BASE+STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOF_AFRL (STM32_GPIOF_BASE+STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOF_AFRH (STM32_GPIOF_BASE+STM32_GPIO_AFRH_OFFSET)
|
||||
# define STM32_GPIOF_BRR (STM32_GPIOF_BASE+STM32_GPIO_BRR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32F7_NGPIO > 6
|
||||
@@ -160,7 +153,6 @@
|
||||
# define STM32_GPIOG_LCKR (STM32_GPIOG_BASE+STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOG_AFRL (STM32_GPIOG_BASE+STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOG_AFRH (STM32_GPIOG_BASE+STM32_GPIO_AFRH_OFFSET)
|
||||
# define STM32_GPIOG_BRR (STM32_GPIOG_BASE+STM32_GPIO_BRR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32F7_NGPIO > 7
|
||||
@@ -174,7 +166,6 @@
|
||||
# define STM32_GPIOH_LCKR (STM32_GPIOH_BASE+STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOH_AFRL (STM32_GPIOH_BASE+STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOH_AFRH (STM32_GPIOH_BASE+STM32_GPIO_AFRH_OFFSET)
|
||||
# define STM32_GPIOH_BRR (STM32_GPIOH_BASE+STM32_GPIO_BRR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32F7_NGPIO > 8
|
||||
@@ -188,7 +179,6 @@
|
||||
# define STM32_GPIOI_LCKR (STM32_GPIOI_BASE+STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOI_AFRL (STM32_GPIOI_BASE+STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOI_AFRH (STM32_GPIOI_BASE+STM32_GPIO_AFRH_OFFSET)
|
||||
# define STM32_GPIOI_BRR (STM32_GPIOI_BASE+STM32_GPIO_BRR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32F7_NGPIO > 9
|
||||
@@ -202,7 +192,6 @@
|
||||
# define STM32_GPIOJ_LCKR (STM32_GPIOJ_BASE+STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOJ_AFRL (STM32_GPIOJ_BASE+STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOJ_AFRH (STM32_GPIOJ_BASE+STM32_GPIO_AFRH_OFFSET)
|
||||
# define STM32_GPIOJ_BRR (STM32_GPIOJ_BASE+STM32_GPIO_BRR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32F7_NGPIO > 10
|
||||
@@ -216,7 +205,6 @@
|
||||
# define STM32_GPIOK_LCKR (STM32_GPIOK_BASE+STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOK_AFRL (STM32_GPIOK_BASE+STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOK_AFRH (STM32_GPIOK_BASE+STM32_GPIO_AFRH_OFFSET)
|
||||
# define STM32_GPIOK_BRR (STM32_GPIOK_BASE+STM32_GPIO_BRR_OFFSET)
|
||||
#endif
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************/
|
||||
@@ -411,9 +399,5 @@
|
||||
#define GPIO_AFRH15_SHIFT (28)
|
||||
#define GPIO_AFRH15_MASK (15 << GPIO_AFRH15_SHIFT)
|
||||
|
||||
/* GPIO port bit reset register */
|
||||
|
||||
#define GPIO_BRR(n) (1 << (n))
|
||||
|
||||
#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */
|
||||
#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX75XX_GPIO_H */
|
||||
|
||||
@@ -2,7 +2,8 @@
|
||||
* arch/arm/src/stm3fr2/chip/stm32f74xxx75xxx_memorymap.h
|
||||
*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
@@ -59,9 +60,8 @@
|
||||
#define STM32_FSMC_BASE34 0x80000000 /* 0x80000000-0x8fffffff: 512Mb FSMC bank3&4 block */
|
||||
# define STM32_FSMC_BANK3 0x80000000 /* 0x80000000-0x8fffffff: 256Mb NAND FLASH */
|
||||
# define STM32_FSMC_BANK4 0x90000000 /* 0x90000000-0x9fffffff: 256Mb PC CARD */
|
||||
#define STM32_AHB3_BASE 0xa0000000 /* 0xa0000000-0xa0001fff: 256Mb AHB3 peripheral block */
|
||||
#define STM32_FSMC_BASE5 0xc0000000 /* 0xc0000000-0xcfffffff: 256Mb FSMC */
|
||||
#define STM32_FSMC_BASE6 0xc0000000 /* 0xd0000000-0xdfffffff: 256Mb FSMC */
|
||||
#define STM32_FSMC_BASE6 0xd0000000 /* 0xd0000000-0xdfffffff: 256Mb FSMC */
|
||||
#define STM32_CORTEX_BASE 0xe0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M7 block */
|
||||
|
||||
#define STM32_REGION_MASK 0xf0000000
|
||||
@@ -97,6 +97,7 @@
|
||||
#define STM32_APB2_BASE 0x40010000 /* 0x40010000-0x40016bff: APB2 */
|
||||
#define STM32_AHB1_BASE 0x40020000 /* 0x40020000-0x4007ffff: APB1 */
|
||||
#define STM32_AHB2_BASE 0x50000000 /* 0x50000000-0x5003ffff: AHB2 */
|
||||
#define STM32_AHB3_BASE 0x60000000 /* 0x60000000-0xdfffffff: AHB3 */
|
||||
|
||||
/* APB1 Base Addresses **************************************************************/
|
||||
|
||||
|
||||
@@ -2,7 +2,8 @@
|
||||
* arch/arm/src/stm32f7/chip/stm32f74xx75xx_pinmap.h
|
||||
*
|
||||
* Copyright (C) 2014-2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
@@ -50,7 +51,7 @@
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Alternate Pin Functions. All members of the STM32F40xxx family share the same
|
||||
/* Alternate Pin Functions. All members of the STM32F74|5xxx family share the same
|
||||
* pin multiplexing (although they may differ in the pins physically available).
|
||||
*
|
||||
* Alternative pin selections are provided with a numeric suffix like _1, _2, etc.
|
||||
|
||||
@@ -1,8 +1,9 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32f7/chip/stm32_pwr.h
|
||||
* arch/arm/src/stm32f7/chip/stm32f74xx75xx_pwr.h
|
||||
*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
@@ -103,6 +104,7 @@
|
||||
#define PWR_CSR1_SBF (1 << 1) /* Bit 1: Standby flag */
|
||||
#define PWR_CSR1_PVDO (1 << 2) /* Bit 2: PVD Output */
|
||||
#define PWR_CSR1_BRR (1 << 3) /* Bit 3: Backup regulator ready */
|
||||
#define PWR_CSR1_EIWUP (1 << 8) /* Bit 8: Enable internal wakeup */
|
||||
#define PWR_CSR1_BRE (1 << 9) /* Bit 9: Backup regulator enable */
|
||||
#define PWR_CSR1_VOSRDY (1 << 14) /* Bit 14: Regulator voltage scaling output selection ready bite */
|
||||
#define PWR_CSR1_ODRDY (1 << 16) /* Bit 16: Over Drive generator ready */
|
||||
|
||||
+8
-6
@@ -1,8 +1,9 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32f7/chip/stm32f74xxf75xx_uart.h
|
||||
* arch/arm/src/stm32f7/chip/stm32f74xxf77xx_uart.h
|
||||
*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@uas.net>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
@@ -33,8 +34,8 @@
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_STC_STM32F7_CHIP_STM32F74XX75XX_UART_H
|
||||
#define __ARCH_ARM_STC_STM32F7_CHIP_STM32F74XX75XX_UART_H
|
||||
#ifndef __ARCH_ARM_STC_STM32F7_CHIP_STM32F74XX77XX_UART_H
|
||||
#define __ARCH_ARM_STC_STM32F7_CHIP_STM32F74XX77XX_UART_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
@@ -42,7 +43,8 @@
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
|
||||
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \
|
||||
defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
@@ -366,4 +368,4 @@
|
||||
#define USART_TDR_MASK (0x1ff << USART_TDR_SHIFT)
|
||||
|
||||
#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */
|
||||
#endif /* __ARCH_ARM_STC_STM32F7_CHIP_STM32F74XX75XX_UART_H */
|
||||
#endif /* __ARCH_ARM_STC_STM32F7_CHIP_STM32F74XX77XX_UART_H */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,219 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32f7/chip/stm32f74xx75xx_flash.h
|
||||
*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM327_CHIP_STM32F74XX75XX_FLASH_H
|
||||
#define __ARCH_ARM_SRC_STM327_CHIP_STM32F74XX75XX_FLASH_H
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Flash size is known from the chip selection:
|
||||
*
|
||||
* When CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT is set the
|
||||
* CONFIG_STM32F7_FLASH_CONFIG_x selects the default FLASH size based on the chip
|
||||
* part number. This value can be overridden with CONFIG_STM32F7_FLASH_OVERRIDE_x
|
||||
*
|
||||
* Parts STM32F74xxE have 512Kb of FLASH
|
||||
* Parts STM32F74xxG have 1024Kb of FLASH
|
||||
*
|
||||
* N.B. Only Single bank mode is supported
|
||||
*/
|
||||
|
||||
#define _K(x) ((x)*1024)
|
||||
|
||||
#if !defined(CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT) && \
|
||||
!defined(CONFIG_STM32_FLASH_OVERRIDE_E) && \
|
||||
!defined(CONFIG_STM32_FLASH_OVERRIDE_F) && \
|
||||
!defined(CONFIG_STM32_FLASH_OVERRIDE_G) && \
|
||||
!defined(CONFIG_STM32_FLASH_OVERRIDE_I) && \
|
||||
!defined(CONFIG_STM32_FLASH_CONFIG_E) && \
|
||||
!defined(CONFIG_STM32_FLASH_CONFIG_F) && \
|
||||
!defined(CONFIG_STM32_FLASH_CONFIG_G) && \
|
||||
!defined(CONFIG_STM32_FLASH_CONFIG_I)
|
||||
# define CONFIG_STM32_FLASH_OVERRIDE_E
|
||||
# warning "Flash size not defined defaulting to 512KiB (E)"
|
||||
#endif
|
||||
|
||||
#if !defined(CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT)
|
||||
|
||||
# undef CONFIG_STM32F7_FLASH_CONFIG_E
|
||||
# undef CONFIG_STM32F7_FLASH_CONFIG_G
|
||||
# undef CONFIG_STM32F7_FLASH_CONFIG_I
|
||||
|
||||
# if defined(CONFIG_STM32F7_FLASH_OVERRIDE_E)
|
||||
|
||||
# define CONFIG_STM32F7_FLASH_CONFIG_E
|
||||
|
||||
# elif defined(CONFIG_STM32F7_FLASH_OVERRIDE_G)
|
||||
|
||||
# define CONFIG_STM32F7_FLASH_CONFIG_G
|
||||
|
||||
# elif defined(CONFIG_STM32F7_FLASH_OVERRIDE_I)
|
||||
|
||||
# define CONFIG_STM32F7_FLASH_CONFIG_I
|
||||
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_FLASH_CONFIG_E)
|
||||
|
||||
# define STM32_FLASH_NPAGES 6
|
||||
# define STM32_FLASH_SIZE _K((4 * 32) + (1 * 128) + (1 * 256))
|
||||
# define STM32_FLASH_SIZES {_K(32), _K(32), _K(32), _K(32), \
|
||||
_K(128), _K(256)}
|
||||
|
||||
#elif defined(CONFIG_STM32_FLASH_CONFIG_G)
|
||||
|
||||
# define STM32_FLASH_NPAGES 8
|
||||
# define STM32_FLASH_SIZE _K((4 * 32) + (1 * 128) + (3 * 256))
|
||||
# define STM32_FLASH_SIZES {_K(32), _K(32), _K(32), _K(32), \
|
||||
_K(128), _K(256), _K(256), _K(256)}
|
||||
|
||||
#elif defined(CONFIG_STM32_FLASH_CONFIG_I)
|
||||
|
||||
# define STM32_FLASH_NPAGES 12
|
||||
# define STM32_FLASH_SIZE _K((4 * 32) + (1 * 128) + (7 * 256))
|
||||
# define STM32_FLASH_SIZES {_K(32), _K(32), _K(32), _K(32), \
|
||||
_K(128), _K(256), _K(256), _K(256) \
|
||||
_K(256), _K(256), _K(256), _K(256)}
|
||||
#endif
|
||||
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
#define STM32_FLASH_ACR_OFFSET 0x0000
|
||||
#define STM32_FLASH_KEYR_OFFSET 0x0004
|
||||
#define STM32_FLASH_OPTKEYR_OFFSET 0x0008
|
||||
#define STM32_FLASH_SR_OFFSET 0x000c
|
||||
#define STM32_FLASH_CR_OFFSET 0x0010
|
||||
#define STM32_FLASH_OPTCR_OFFSET 0x0014
|
||||
#define STM32_FLASH_OPTCR1_OFFSET 0x0018
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
#define STM32_FLASH_ACR (STM32_FLASHIF_BASE+STM32_FLASH_ACR_OFFSET)
|
||||
#define STM32_FLASH_KEYR (STM32_FLASHIF_BASE+STM32_FLASH_KEYR_OFFSET)
|
||||
#define STM32_FLASH_OPTKEYR (STM32_FLASHIF_BASE+STM32_FLASH_OPTKEYR_OFFSET)
|
||||
#define STM32_FLASH_SR (STM32_FLASHIF_BASE+STM32_FLASH_SR_OFFSET)
|
||||
#define STM32_FLASH_CR (STM32_FLASHIF_BASE+STM32_FLASH_CR_OFFSET)
|
||||
#define STM32_FLASH_OPTCR (STM32_FLASHIF_BASE+STM32_FLASH_OPTCR_OFFSET)
|
||||
#define STM32_FLASH_OPTCR1 (STM32_FLASHIF_BASE+STM32_FLASH_OPTCR1_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************/
|
||||
/* Flash Access Control Register (ACR) */
|
||||
|
||||
#define FLASH_ACR_LATENCY_SHIFT (0) /* Bits 0-1: Latency */
|
||||
#define FLASH_ACR_LATENCY_MASK (7 << FLASH_ACR_LATENCY_SHIFT)
|
||||
# define FLASH_ACR_LATENCY(n) ((n) << FLASH_ACR_LATENCY_SHIFT) /* n wait states */
|
||||
# define FLASH_ACR_LATENCY_0 (0 << FLASH_ACR_LATENCY_SHIFT) /* 000: Zero wait states */
|
||||
# define FLASH_ACR_LATENCY_1 (1 << FLASH_ACR_LATENCY_SHIFT) /* 001: One wait state */
|
||||
# define FLASH_ACR_LATENCY_2 (2 << FLASH_ACR_LATENCY_SHIFT) /* 010: Two wait states */
|
||||
# define FLASH_ACR_LATENCY_3 (3 << FLASH_ACR_LATENCY_SHIFT) /* 011: Three wait states */
|
||||
# define FLASH_ACR_LATENCY_4 (4 << FLASH_ACR_LATENCY_SHIFT) /* 100: Four wait states */
|
||||
# define FLASH_ACR_LATENCY_5 (5 << FLASH_ACR_LATENCY_SHIFT) /* 101: Five wait states */
|
||||
# define FLASH_ACR_LATENCY_6 (6 << FLASH_ACR_LATENCY_SHIFT) /* 110: Six wait states */
|
||||
# define FLASH_ACR_LATENCY_7 (7 << FLASH_ACR_LATENCY_SHIFT) /* 111: Seven wait states */
|
||||
#define FLASH_ACR_PRFTEN (1 << 8) /* FLASH prefetch enable */
|
||||
#define FLASH_ACR_ARTEN (1 << 9) /* Bit 9: ART Accelerator Enable */
|
||||
#define FLASH_ACR_ARTRST (1 << 11) /* Bit 11: ART Accelerator reset */
|
||||
|
||||
/* Flash Status Register (SR) */
|
||||
|
||||
#define FLASH_SR_EOP (1 << 0) /* Bit 0: End of operation */
|
||||
#define FLASH_SR_OPERR (1 << 1) /* Bit 1: Operation error */
|
||||
#define FLASH_SR_WRPERR (1 << 4) /* Bit 4: Write protection error */
|
||||
#define FLASH_SR_PGAERR (1 << 5) /* Bit 5: Programming alignment error */
|
||||
#define FLASH_SR_PGPERR (1 << 6) /* Bit 6: Programming parallelism error */
|
||||
#define FLASH_SR_PGSERR (1 << 7) /* Bit 7: Programming sequence error */
|
||||
#define FLASH_SR_BSY (1 << 16) /* Bit 16: Busy */
|
||||
|
||||
/* Flash Control Register (CR) */
|
||||
|
||||
#define FLASH_CR_PG (1 << 0) /* Bit 0: Programming */
|
||||
#define FLASH_CR_SER (1 << 1) /* Bit 1: Sector Erase */
|
||||
#define FLASH_CR_MER_MER1 (1 << 2) /* Bit 2: Mass Erase sectors 0..11 */
|
||||
#define FLASH_CR_SNB_SHIFT (3) /* Bits 3-6: Sector number */
|
||||
#define FLASH_CR_SNB_MASK (0x1f << FLASH_CR_SNB_SHIFT)
|
||||
# define FLASH_CR_SNB(n) ((uint32_t)((n) % 12) << FLASH_CR_SNB_SHIFT) | ((n / 12) << 7)) /* Sector n, n=0..23 */
|
||||
#define FLASH_CR_PSIZE_SHIFT (8) /* Bits 8-9: Program size */
|
||||
#define FLASH_CR_PSIZE_MASK (3 << FLASH_CR_PSIZE_SHIFT)
|
||||
# define FLASH_CR_PSIZE_X8 (0 << FLASH_CR_PSIZE_SHIFT) /* Program x8 */
|
||||
# define FLASH_CR_PSIZE_X16 (1 << FLASH_CR_PSIZE_SHIFT) /* Program x16 */
|
||||
# define FLASH_CR_PSIZE_X32 (2 << FLASH_CR_PSIZE_SHIFT) /* Program x32 */
|
||||
# define FLASH_CR_PSIZE_X64 (3 << FLASH_CR_PSIZE_SHIFT) /* Program x64 */
|
||||
#define FLASH_CR_STRT (1 << 16) /* Bit 16: Start Erase */
|
||||
#define FLASH_CR_EOPIE (1 << 24) /* Bit 24: End of operation interrupt enable */
|
||||
#define FLASH_CR_ERRIE (1 << 25) /* Bit 25: Error interrupt enable */
|
||||
#define FLASH_CR_LOCK (1 << 31) /* Bit 31: Lock */
|
||||
#define FLASH_CR_MER2 (1 << 15) /* Bit 15: Mass Erase sectors 12..23 */
|
||||
|
||||
/* Flash Option Control Register (OPTCR) */
|
||||
|
||||
#define FLASH_OPTCR_OPTLOCK (1 << 0) /* Bit 0: Option lock */
|
||||
#define FLASH_OPTCR_OPTSTRT (1 << 1) /* Bit 1: Option start */
|
||||
#define FLASH_OPTCR_BORLEV_SHIFT (2) /* Bits 2-3: BOR reset Level */
|
||||
#define FLASH_OPTCR_BORLEV_MASK (3 << FLASH_OPTCR_BORLEV_SHIFT)
|
||||
# define FLASH_OPTCR_VBOR3 (0 << FLASH_OPTCR_BORLEV_SHIFT) /* BOR Level 3 */
|
||||
# define FLASH_OPTCR_VBOR2 (1 << FLASH_OPTCR_BORLEV_SHIFT) /* BOR Level 2 */
|
||||
# define FLASH_OPTCR_VBOR1 (2 << FLASH_OPTCR_BORLEV_SHIFT) /* BOR Level 1 */
|
||||
# define FLASH_OPTCR_VBOR0 (3 << FLASH_OPTCR_BORLEV_SHIFT) /* BOR off */
|
||||
#define FLASH_OPTCR_USER_SHIFT (4) /* Bits 5-7: User option bytes */
|
||||
#define FLASH_OPTCR_USER_MASK (15 << FLASH_OPTCR_USER_SHIFT)
|
||||
# define FLASH_OPTCR_WWDG_SW (1 << 4) /* Bit 4: WWDG_SW */
|
||||
# define FLASH_OPTCR_IWDG_SW (1 << 5) /* Bit 5: IWDG_SW */
|
||||
# define FLASH_OPTCR_NRST_STOP (1 << 6) /* Bit 6: nRST_STOP */
|
||||
# define FLASH_OPTCR_NRST_STDBY (1 << 7) /* Bit 7: nRST_STDBY */
|
||||
#define FLASH_OPTCR_RDP_SHIFT (8) /* Bits 8-15: Read protect */
|
||||
#define FLASH_OPTCR_RDP_MASK (0xff << FLASH_OPTCR_RDP_SHIFT)
|
||||
# define FLASH_OPTCR_RDP(n) ((uint32_t)(n) << FLASH_OPTCR_RDP_SHIFT)
|
||||
#define FLASH_OPTCR_NWRP_SHIFT (16) /* Bits 16-27: Not write protect */
|
||||
#define FLASH_OPTCR_NWRP_MASK (0xfff << FLASH_OPTCR_NWRP_SHIFT)
|
||||
# define FLASH_OPTCR_NWRP(n) ((uint32_t)(n) << FLASH_OPTCR_NWRP_SHIFT)
|
||||
#define FLASH_OPTCR_NDBANK (1 << 28) /* Bit 28: Not dual bank mode */
|
||||
#define FLASH_OPTCR_NDBOOT (1 << 29) /* Bit 29: Dual Boot mode */
|
||||
#define FLASH_OPTCR_IWDG_STDBY (1 << 30) /* Bit 30: IWDG freeze in stop mode */
|
||||
#define FLASH_OPTCR_IWDG_STOP (1 << 31) /* Bit 31: IWDG freeze in standby mode */
|
||||
|
||||
/* Flash Option Control Register (OPTCR1) */
|
||||
|
||||
#define FLASH_OPTCR1_BOOTADD0_SHIFT (0) /* Bits 0-15: Boot base address when Boot pin=0 */
|
||||
#define FLASH_OPTCR1_BOOTADD0_MASK (0xffff << FLASH_OPTCR1_BOOTADD0_SHIFT)
|
||||
# define FLASH_OPTCR1_BOOTADD0(n) ((uint32_t)(n) << FLASH_OPTCR1_BOOTADD0_SHIFT)
|
||||
#define FLASH_OPTCR1_BOOTADD1_SHIFT (16) /* Bits 16-31:Boot base address when Boot pin=1 */
|
||||
#define FLASH_OPTCR1_BOOTADD1_MASK (0xffff << FLASH_OPTCR1_BOOTADD1_SHIFT)
|
||||
# define FLASH_OPTCR1_BOOTADD1(n) ((uint32_t)(n) << FLASH_OPTCR1_BOOTADD1_SHIFT)
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM327_CHIP_STM32F74XX75XX_FLASH_H */
|
||||
@@ -0,0 +1,404 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32f7/chip/stm32f76xxx77xx_gpio.h
|
||||
*
|
||||
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F76XX77XX_GPIO_H
|
||||
#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F76XX77XX_GPIO_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <arch/stm32f7/chip.h>
|
||||
|
||||
#if defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
#define STM32_GPIO_MODER_OFFSET 0x0000 /* GPIO port mode register */
|
||||
#define STM32_GPIO_OTYPER_OFFSET 0x0004 /* GPIO port output type register */
|
||||
#define STM32_GPIO_OSPEED_OFFSET 0x0008 /* GPIO port output speed register */
|
||||
#define STM32_GPIO_PUPDR_OFFSET 0x000c /* GPIO port pull-up/pull-down register */
|
||||
#define STM32_GPIO_IDR_OFFSET 0x0010 /* GPIO port input data register */
|
||||
#define STM32_GPIO_ODR_OFFSET 0x0014 /* GPIO port output data register */
|
||||
#define STM32_GPIO_BSRR_OFFSET 0x0018 /* GPIO port bit set/reset register */
|
||||
#define STM32_GPIO_LCKR_OFFSET 0x001c /* GPIO port configuration lock register */
|
||||
#define STM32_GPIO_AFRL_OFFSET 0x0020 /* GPIO alternate function low register */
|
||||
#define STM32_GPIO_AFRH_OFFSET 0x0024 /* GPIO alternate function high register */
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
#if STM32F7_NGPIO > 0
|
||||
# define STM32_GPIOA_MODER (STM32_GPIOA_BASE+STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOA_OTYPER (STM32_GPIOA_BASE+STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOA_OSPEED (STM32_GPIOA_BASE+STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOA_PUPDR (STM32_GPIOA_BASE+STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOA_IDR (STM32_GPIOA_BASE+STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOA_ODR (STM32_GPIOA_BASE+STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOA_BSRR (STM32_GPIOA_BASE+STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOA_LCKR (STM32_GPIOA_BASE+STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOA_AFRL (STM32_GPIOA_BASE+STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOA_AFRH (STM32_GPIOA_BASE+STM32_GPIO_AFRH_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32F7_NGPIO > 1
|
||||
# define STM32_GPIOB_MODER (STM32_GPIOB_BASE+STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOB_OTYPER (STM32_GPIOB_BASE+STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOB_OSPEED (STM32_GPIOB_BASE+STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOB_PUPDR (STM32_GPIOB_BASE+STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOB_IDR (STM32_GPIOB_BASE+STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOB_ODR (STM32_GPIOB_BASE+STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOB_BSRR (STM32_GPIOB_BASE+STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOB_LCKR (STM32_GPIOB_BASE+STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOB_AFRL (STM32_GPIOB_BASE+STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOB_AFRH (STM32_GPIOB_BASE+STM32_GPIO_AFRH_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32F7_NGPIO > 2
|
||||
# define STM32_GPIOC_MODER (STM32_GPIOC_BASE+STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOC_OTYPER (STM32_GPIOC_BASE+STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOC_OSPEED (STM32_GPIOC_BASE+STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOC_PUPDR (STM32_GPIOC_BASE+STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOC_IDR (STM32_GPIOC_BASE+STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOC_ODR (STM32_GPIOC_BASE+STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOC_BSRR (STM32_GPIOC_BASE+STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOC_LCKR (STM32_GPIOC_BASE+STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOC_AFRL (STM32_GPIOC_BASE+STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOC_AFRH (STM32_GPIOC_BASE+STM32_GPIO_AFRH_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32F7_NGPIO > 3
|
||||
# define STM32_GPIOD_MODER (STM32_GPIOD_BASE+STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOD_OTYPER (STM32_GPIOD_BASE+STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOD_OSPEED (STM32_GPIOD_BASE+STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOD_PUPDR (STM32_GPIOD_BASE+STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOD_IDR (STM32_GPIOD_BASE+STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOD_ODR (STM32_GPIOD_BASE+STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOD_BSRR (STM32_GPIOD_BASE+STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOD_LCKR (STM32_GPIOD_BASE+STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOD_AFRL (STM32_GPIOD_BASE+STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOD_AFRH (STM32_GPIOD_BASE+STM32_GPIO_AFRH_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32F7_NGPIO > 4
|
||||
# define STM32_GPIOE_MODER (STM32_GPIOE_BASE+STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOE_OTYPER (STM32_GPIOE_BASE+STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOE_OSPEED (STM32_GPIOE_BASE+STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOE_PUPDR (STM32_GPIOE_BASE+STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOE_IDR (STM32_GPIOE_BASE+STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOE_ODR (STM32_GPIOE_BASE+STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOE_BSRR (STM32_GPIOE_BASE+STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOE_LCKR (STM32_GPIOE_BASE+STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOE_AFRL (STM32_GPIOE_BASE+STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOE_AFRH (STM32_GPIOE_BASE+STM32_GPIO_AFRH_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32F7_NGPIO > 5
|
||||
# define STM32_GPIOF_MODER (STM32_GPIOF_BASE+STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOF_OTYPER (STM32_GPIOF_BASE+STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOF_OSPEED (STM32_GPIOF_BASE+STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOF_PUPDR (STM32_GPIOF_BASE+STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOF_IDR (STM32_GPIOF_BASE+STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOF_ODR (STM32_GPIOF_BASE+STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOF_BSRR (STM32_GPIOF_BASE+STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOF_LCKR (STM32_GPIOF_BASE+STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOF_AFRL (STM32_GPIOF_BASE+STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOF_AFRH (STM32_GPIOF_BASE+STM32_GPIO_AFRH_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32F7_NGPIO > 6
|
||||
# define STM32_GPIOG_MODER (STM32_GPIOG_BASE+STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOG_OTYPER (STM32_GPIOG_BASE+STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOG_OSPEED (STM32_GPIOG_BASE+STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOG_PUPDR (STM32_GPIOG_BASE+STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOG_IDR (STM32_GPIOG_BASE+STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOG_ODR (STM32_GPIOG_BASE+STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOG_BSRR (STM32_GPIOG_BASE+STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOG_LCKR (STM32_GPIOG_BASE+STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOG_AFRL (STM32_GPIOG_BASE+STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOG_AFRH (STM32_GPIOG_BASE+STM32_GPIO_AFRH_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32F7_NGPIO > 7
|
||||
# define STM32_GPIOH_MODER (STM32_GPIOH_BASE+STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOH_OTYPER (STM32_GPIOH_BASE+STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOH_OSPEED (STM32_GPIOH_BASE+STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOH_PUPDR (STM32_GPIOH_BASE+STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOH_IDR (STM32_GPIOH_BASE+STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOH_ODR (STM32_GPIOH_BASE+STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOH_BSRR (STM32_GPIOH_BASE+STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOH_LCKR (STM32_GPIOH_BASE+STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOH_AFRL (STM32_GPIOH_BASE+STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOH_AFRH (STM32_GPIOH_BASE+STM32_GPIO_AFRH_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32F7_NGPIO > 8
|
||||
# define STM32_GPIOI_MODER (STM32_GPIOI_BASE+STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOI_OTYPER (STM32_GPIOI_BASE+STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOI_OSPEED (STM32_GPIOI_BASE+STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOI_PUPDR (STM32_GPIOI_BASE+STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOI_IDR (STM32_GPIOI_BASE+STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOI_ODR (STM32_GPIOI_BASE+STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOI_BSRR (STM32_GPIOI_BASE+STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOI_LCKR (STM32_GPIOI_BASE+STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOI_AFRL (STM32_GPIOI_BASE+STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOI_AFRH (STM32_GPIOI_BASE+STM32_GPIO_AFRH_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32F7_NGPIO > 9
|
||||
# define STM32_GPIOJ_MODER (STM32_GPIOJ_BASE+STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOJ_OTYPER (STM32_GPIOJ_BASE+STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOJ_OSPEED (STM32_GPIOJ_BASE+STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOJ_PUPDR (STM32_GPIOJ_BASE+STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOJ_IDR (STM32_GPIOJ_BASE+STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOJ_ODR (STM32_GPIOJ_BASE+STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOJ_BSRR (STM32_GPIOJ_BASE+STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOJ_LCKR (STM32_GPIOJ_BASE+STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOJ_AFRL (STM32_GPIOJ_BASE+STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOJ_AFRH (STM32_GPIOJ_BASE+STM32_GPIO_AFRH_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32F7_NGPIO > 10
|
||||
# define STM32_GPIOK_MODER (STM32_GPIOK_BASE+STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOK_OTYPER (STM32_GPIOK_BASE+STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOK_OSPEED (STM32_GPIOK_BASE+STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOK_PUPDR (STM32_GPIOK_BASE+STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOK_IDR (STM32_GPIOK_BASE+STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOK_ODR (STM32_GPIOK_BASE+STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOK_BSRR (STM32_GPIOK_BASE+STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOK_LCKR (STM32_GPIOK_BASE+STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOK_AFRL (STM32_GPIOK_BASE+STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOK_AFRH (STM32_GPIOK_BASE+STM32_GPIO_AFRH_OFFSET)
|
||||
#endif
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************/
|
||||
|
||||
/* GPIO port mode register */
|
||||
|
||||
#define GPIO_MODER_INPUT (0) /* Input */
|
||||
#define GPIO_MODER_OUTPUT (1) /* General purpose output mode */
|
||||
#define GPIO_MODER_ALT (2) /* Alternate mode */
|
||||
#define GPIO_MODER_ANALOG (3) /* Analog mode */
|
||||
|
||||
#define GPIO_MODER_SHIFT(n) ((n) << 1)
|
||||
#define GPIO_MODER_MASK(n) (3 << GPIO_MODER_SHIFT(n))
|
||||
|
||||
#define GPIO_MODER0_SHIFT (0)
|
||||
#define GPIO_MODER0_MASK (3 << GPIO_MODER0_SHIFT)
|
||||
#define GPIO_MODER1_SHIFT (2)
|
||||
#define GPIO_MODER1_MASK (3 << GPIO_MODER1_SHIFT)
|
||||
#define GPIO_MODER2_SHIFT (4)
|
||||
#define GPIO_MODER2_MASK (3 << GPIO_MODER2_SHIFT)
|
||||
#define GPIO_MODER3_SHIFT (6)
|
||||
#define GPIO_MODER3_MASK (3 << GPIO_MODER3_SHIFT)
|
||||
#define GPIO_MODER4_SHIFT (8)
|
||||
#define GPIO_MODER4_MASK (3 << GPIO_MODER4_SHIFT)
|
||||
#define GPIO_MODER5_SHIFT (10)
|
||||
#define GPIO_MODER5_MASK (3 << GPIO_MODER5_SHIFT)
|
||||
#define GPIO_MODER6_SHIFT (12)
|
||||
#define GPIO_MODER6_MASK (3 << GPIO_MODER6_SHIFT)
|
||||
#define GPIO_MODER7_SHIFT (14)
|
||||
#define GPIO_MODER7_MASK (3 << GPIO_MODER7_SHIFT)
|
||||
#define GPIO_MODER8_SHIFT (16)
|
||||
#define GPIO_MODER8_MASK (3 << GPIO_MODER8_SHIFT)
|
||||
#define GPIO_MODER9_SHIFT (18)
|
||||
#define GPIO_MODER9_MASK (3 << GPIO_MODER9_SHIFT)
|
||||
#define GPIO_MODER10_SHIFT (20)
|
||||
#define GPIO_MODER10_MASK (3 << GPIO_MODER10_SHIFT)
|
||||
#define GPIO_MODER11_SHIFT (22)
|
||||
#define GPIO_MODER11_MASK (3 << GPIO_MODER11_SHIFT)
|
||||
#define GPIO_MODER12_SHIFT (24)
|
||||
#define GPIO_MODER12_MASK (3 << GPIO_MODER12_SHIFT)
|
||||
#define GPIO_MODER13_SHIFT (26)
|
||||
#define GPIO_MODER13_MASK (3 << GPIO_MODER13_SHIFT)
|
||||
#define GPIO_MODER14_SHIFT (28)
|
||||
#define GPIO_MODER14_MASK (3 << GPIO_MODER14_SHIFT)
|
||||
#define GPIO_MODER15_SHIFT (30)
|
||||
#define GPIO_MODER15_MASK (3 << GPIO_MODER15_SHIFT)
|
||||
|
||||
/* GPIO port output type register */
|
||||
|
||||
#define GPIO_OTYPER_OD(n) (1 << (n)) /* 1=Output open-drain */
|
||||
#define GPIO_OTYPER_PP(n) (0) /* 0=Ouput push-pull */
|
||||
|
||||
/* GPIO port output speed register */
|
||||
|
||||
#define GPIO_OSPEED_2MHz (0) /* 2 MHz Low speed */
|
||||
#define GPIO_OSPEED_25MHz (1) /* 25 MHz Medium speed */
|
||||
#define GPIO_OSPEED_50MHz (2) /* 50 MHz Fast speed */
|
||||
#define GPIO_OSPEED_100MHz (3) /* 100 MHz High speed on 30 pF (80 MHz Output max speed on 15 pF) */
|
||||
|
||||
#define GPIO_OSPEED_SHIFT(n) ((n) << 1)
|
||||
#define GPIO_OSPEED_MASK(n) (3 << GPIO_OSPEED_SHIFT(n))
|
||||
|
||||
#define GPIO_OSPEED0_SHIFT (0)
|
||||
#define GPIO_OSPEED0_MASK (3 << GPIO_OSPEED0_SHIFT)
|
||||
#define GPIO_OSPEED1_SHIFT (2)
|
||||
#define GPIO_OSPEED1_MASK (3 << GPIO_OSPEED1_SHIFT)
|
||||
#define GPIO_OSPEED2_SHIFT (4)
|
||||
#define GPIO_OSPEED2_MASK (3 << GPIO_OSPEED2_SHIFT)
|
||||
#define GPIO_OSPEED3_SHIFT (6)
|
||||
#define GPIO_OSPEED3_MASK (3 << GPIO_OSPEED3_SHIFT)
|
||||
#define GPIO_OSPEED4_SHIFT (8)
|
||||
#define GPIO_OSPEED4_MASK (3 << GPIO_OSPEED4_SHIFT)
|
||||
#define GPIO_OSPEED5_SHIFT (10)
|
||||
#define GPIO_OSPEED5_MASK (3 << GPIO_OSPEED5_SHIFT)
|
||||
#define GPIO_OSPEED6_SHIFT (12)
|
||||
#define GPIO_OSPEED6_MASK (3 << GPIO_OSPEED6_SHIFT)
|
||||
#define GPIO_OSPEED7_SHIFT (14)
|
||||
#define GPIO_OSPEED7_MASK (3 << GPIO_OSPEED7_SHIFT)
|
||||
#define GPIO_OSPEED8_SHIFT (16)
|
||||
#define GPIO_OSPEED8_MASK (3 << GPIO_OSPEED8_SHIFT)
|
||||
#define GPIO_OSPEED9_SHIFT (18)
|
||||
#define GPIO_OSPEED9_MASK (3 << GPIO_OSPEED9_SHIFT)
|
||||
#define GPIO_OSPEED10_SHIFT (20)
|
||||
#define GPIO_OSPEED10_MASK (3 << GPIO_OSPEED10_SHIFT)
|
||||
#define GPIO_OSPEED11_SHIFT (22)
|
||||
#define GPIO_OSPEED11_MASK (3 << GPIO_OSPEED11_SHIFT)
|
||||
#define GPIO_OSPEED12_SHIFT (24)
|
||||
#define GPIO_OSPEED12_MASK (3 << GPIO_OSPEED12_SHIFT)
|
||||
#define GPIO_OSPEED13_SHIFT (26)
|
||||
#define GPIO_OSPEED13_MASK (3 << GPIO_OSPEED13_SHIFT)
|
||||
#define GPIO_OSPEED14_SHIFT (28)
|
||||
#define GPIO_OSPEED14_MASK (3 << GPIO_OSPEED14_SHIFT)
|
||||
#define GPIO_OSPEED15_SHIFT (30)
|
||||
#define GPIO_OSPEED15_MASK (3 << GPIO_OSPEED15_SHIFT)
|
||||
|
||||
/* GPIO port pull-up/pull-down register */
|
||||
|
||||
#define GPIO_PUPDR_NONE (0) /* No pull-up, pull-down */
|
||||
#define GPIO_PUPDR_PULLUP (1) /* Pull-up */
|
||||
#define GPIO_PUPDR_PULLDOWN (2) /* Pull-down */
|
||||
|
||||
#define GPIO_PUPDR_SHIFT(n) ((n) << 1)
|
||||
#define GPIO_PUPDR_MASK(n) (3 << GPIO_PUPDR_SHIFT(n))
|
||||
|
||||
#define GPIO_PUPDR0_SHIFT (0)
|
||||
#define GPIO_PUPDR0_MASK (3 << GPIO_PUPDR0_SHIFT)
|
||||
#define GPIO_PUPDR1_SHIFT (2)
|
||||
#define GPIO_PUPDR1_MASK (3 << GPIO_PUPDR1_SHIFT)
|
||||
#define GPIO_PUPDR2_SHIFT (4)
|
||||
#define GPIO_PUPDR2_MASK (3 << GPIO_PUPDR2_SHIFT)
|
||||
#define GPIO_PUPDR3_SHIFT (6)
|
||||
#define GPIO_PUPDR3_MASK (3 << GPIO_PUPDR3_SHIFT)
|
||||
#define GPIO_PUPDR4_SHIFT (8)
|
||||
#define GPIO_PUPDR4_MASK (3 << GPIO_PUPDR4_SHIFT)
|
||||
#define GPIO_PUPDR5_SHIFT (10)
|
||||
#define GPIO_PUPDR5_MASK (3 << GPIO_PUPDR5_SHIFT)
|
||||
#define GPIO_PUPDR6_SHIFT (12)
|
||||
#define GPIO_PUPDR6_MASK (3 << GPIO_PUPDR6_SHIFT)
|
||||
#define GPIO_PUPDR7_SHIFT (14)
|
||||
#define GPIO_PUPDR7_MASK (3 << GPIO_PUPDR7_SHIFT)
|
||||
#define GPIO_PUPDR8_SHIFT (16)
|
||||
#define GPIO_PUPDR8_MASK (3 << GPIO_PUPDR8_SHIFT)
|
||||
#define GPIO_PUPDR9_SHIFT (18)
|
||||
#define GPIO_PUPDR9_MASK (3 << GPIO_PUPDR9_SHIFT)
|
||||
#define GPIO_PUPDR10_SHIFT (20)
|
||||
#define GPIO_PUPDR10_MASK (3 << GPIO_PUPDR10_SHIFT)
|
||||
#define GPIO_PUPDR11_SHIFT (22)
|
||||
#define GPIO_PUPDR11_MASK (3 << GPIO_PUPDR11_SHIFT)
|
||||
#define GPIO_PUPDR12_SHIFT (24)
|
||||
#define GPIO_PUPDR12_MASK (3 << GPIO_PUPDR12_SHIFT)
|
||||
#define GPIO_PUPDR13_SHIFT (26)
|
||||
#define GPIO_PUPDR13_MASK (3 << GPIO_PUPDR13_SHIFT)
|
||||
#define GPIO_PUPDR14_SHIFT (28)
|
||||
#define GPIO_PUPDR14_MASK (3 << GPIO_PUPDR14_SHIFT)
|
||||
#define GPIO_PUPDR15_SHIFT (30)
|
||||
#define GPIO_PUPDR15_MASK (3 << GPIO_PUPDR15_SHIFT)
|
||||
|
||||
/* GPIO port input data register */
|
||||
|
||||
#define GPIO_IDR(n) (1 << (n))
|
||||
|
||||
/* GPIO port output data register */
|
||||
|
||||
#define GPIO_ODR(n) (1 << (n))
|
||||
|
||||
/* GPIO port bit set/reset register */
|
||||
|
||||
#define GPIO_BSRR_SET(n) (1 << (n))
|
||||
#define GPIO_BSRR_RESET(n) (1 << ((n)+16))
|
||||
|
||||
/* GPIO port configuration lock register */
|
||||
|
||||
#define GPIO_LCKR(n) (1 << (n))
|
||||
#define GPIO_LCKK (1 << 16) /* Lock key */
|
||||
|
||||
/* GPIO alternate function low/high register */
|
||||
|
||||
#define GPIO_AFR_SHIFT(n) ((n) << 2)
|
||||
#define GPIO_AFR_MASK(n) (15 << GPIO_AFR_SHIFT(n))
|
||||
|
||||
#define GPIO_AFRL0_SHIFT (0)
|
||||
#define GPIO_AFRL0_MASK (15 << GPIO_AFRL0_SHIFT)
|
||||
#define GPIO_AFRL1_SHIFT (4)
|
||||
#define GPIO_AFRL1_MASK (15 << GPIO_AFRL1_SHIFT)
|
||||
#define GPIO_AFRL2_SHIFT (8)
|
||||
#define GPIO_AFRL2_MASK (15 << GPIO_AFRL2_SHIFT)
|
||||
#define GPIO_AFRL3_SHIFT (12)
|
||||
#define GPIO_AFRL3_MASK (15 << GPIO_AFRL3_SHIFT)
|
||||
#define GPIO_AFRL4_SHIFT (16)
|
||||
#define GPIO_AFRL4_MASK (15 << GPIO_AFRL4_SHIFT)
|
||||
#define GPIO_AFRL5_SHIFT (20)
|
||||
#define GPIO_AFRL5_MASK (15 << GPIO_AFRL5_SHIFT)
|
||||
#define GPIO_AFRL6_SHIFT (24)
|
||||
#define GPIO_AFRL6_MASK (15 << GPIO_AFRL6_SHIFT)
|
||||
#define GPIO_AFRL7_SHIFT (28)
|
||||
#define GPIO_AFRL7_MASK (15 << GPIO_AFRL7_SHIFT)
|
||||
|
||||
#define GPIO_AFRH8_SHIFT (0)
|
||||
#define GPIO_AFRH8_MASK (15 << GPIO_AFRH8_SHIFT)
|
||||
#define GPIO_AFRH9_SHIFT (4)
|
||||
#define GPIO_AFRH9_MASK (15 << GPIO_AFRH9_SHIFT)
|
||||
#define GPIO_AFRH10_SHIFT (8)
|
||||
#define GPIO_AFRH10_MASK (15 << GPIO_AFRH10_SHIFT)
|
||||
#define GPIO_AFRH11_SHIFT (12)
|
||||
#define GPIO_AFRH11_MASK (15 << GPIO_AFRH11_SHIFT)
|
||||
#define GPIO_AFRH12_SHIFT (16)
|
||||
#define GPIO_AFRH12_MASK (15 << GPIO_AFRH12_SHIFT)
|
||||
#define GPIO_AFRH13_SHIFT (20)
|
||||
#define GPIO_AFRH13_MASK (15 << GPIO_AFRH13_SHIFT)
|
||||
#define GPIO_AFRH14_SHIFT (24)
|
||||
#define GPIO_AFRH14_MASK (15 << GPIO_AFRH14_SHIFT)
|
||||
#define GPIO_AFRH15_SHIFT (28)
|
||||
#define GPIO_AFRH15_MASK (15 << GPIO_AFRH15_SHIFT)
|
||||
|
||||
#endif /* CONFIG_STM32F7_STM32F76XX || CONFIG_STM32F7_STM32F77XX */
|
||||
#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F76XX77XX_GPIO_H */
|
||||
@@ -0,0 +1,214 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm3fr2/chip/stm32f76xxx77xxx_memorymap.h
|
||||
*
|
||||
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@uas.net>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F76XXX77XXX_MEMORYMAP_H
|
||||
#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F76XXX77XXX_MEMORYMAP_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#if defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* STM32F40XXX Address Blocks *******************************************************/
|
||||
|
||||
#define STM32_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */
|
||||
#define STM32_SRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: 512Mb sram block */
|
||||
#define STM32_PERIPH_BASE 0x40000000 /* 0x40000000-0x5fffffff: 512Mb AHB1-2 peripheral blocks */
|
||||
#define STM32_FSMC_BASE12 0x60000000 /* 0x60000000-0x7fffffff: 512Mb FSMC bank1&2 block */
|
||||
# define STM32_FSMC_BANK1 0x60000000 /* 0x60000000-0x6fffffff: 256Mb NOR/SRAM */
|
||||
# define STM32_FSMC_BANK2 0x70000000 /* 0x70000000-0x7fffffff: 256Mb NAND FLASH */
|
||||
#define STM32_FSMC_BASE34 0x80000000 /* 0x80000000-0x8fffffff: 512Mb FSMC bank3&4 block */
|
||||
# define STM32_FSMC_BANK3 0x80000000 /* 0x80000000-0x8fffffff: 256Mb NAND FLASH */
|
||||
# define STM32_FSMC_BANK4 0x90000000 /* 0x90000000-0x9fffffff: 256Mb PC CARD */
|
||||
#define STM32_FSMC_BASE5 0xc0000000 /* 0xc0000000-0xcfffffff: 256Mb FSMC */
|
||||
#define STM32_FSMC_BASE6 0xd0000000 /* 0xd0000000-0xdfffffff: 256Mb FSMC */
|
||||
#define STM32_CORTEX_BASE 0xe0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M7 block */
|
||||
|
||||
#define STM32_REGION_MASK 0xf0000000
|
||||
#define STM32_IS_SRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_SRAM_BASE)
|
||||
#define STM32_IS_EXTSRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_FSMC_BANK1)
|
||||
|
||||
/* Code Base Addresses **************************************************************/
|
||||
|
||||
#define STM32_BOOT_BASE 0x00000000 /* 0x00000000-0x000fffff: Aliased boot memory */
|
||||
#define STM32_INSTRAM_BASE 0x00000000 /* 0x00000000-0x00003fff: Instruction RAM (ITCM-RAM) */
|
||||
#define STM32_SYSMEM_ICTM 0x00100000 /* 0x00100000-0x0010edbf: System memory (ITCM) */
|
||||
#define STM32_FLASH_ITCM 0x00200000 /* 0x00200000-0x003fffff: FLASH memory (ITCM) */
|
||||
#define STM32_LOADER_BASE 0x01000000 /* 0x01000000- Bootloader */
|
||||
#define STM32_FLASH_AXIM 0x08000000 /* 0x08000000-0x081fffff: FLASH memory (AXIM) */
|
||||
#define STM32_OPTIONS_BASE 0x1fff0000 /* 0x1ff00000-0x1fff001f: OTP (AXIM) */
|
||||
|
||||
/* Information Addresses ************************************************************/
|
||||
|
||||
|
||||
#define STM32_SYSMEM_AXIM 0x1ff00000 /* 0x1ff00000-0x1ff0edbf: System memory (AXIM) */
|
||||
#define STM32_OTP_ICTM 0x0010f000 /* 0x0010f000-0x0010edbf: OTP (ITCM) */
|
||||
#define STM32_OTP_AXIM 0x1ff0f000 /* 0x1ff00000-0x1ff0f41f: OTP (AXIM) */
|
||||
|
||||
/* SRAM Base Addresses **************************************************************/
|
||||
|
||||
#define STM32_DTCRAM_BASE 0x20000000 /* 0x20000000-0x2001ffff: DTCM-RAM on TCM interface */
|
||||
#define STM32_SRAM1_BASE 0x20020000 /* 0x20020000-0x2007bfff: System SRAM1 */
|
||||
#define STM32_SRAM2_BASE 0x2007c000 /* 0x2007c000-0x2007ffff: System SRAM2 */
|
||||
|
||||
/* Peripheral Base Addresses ********************************************************/
|
||||
|
||||
#define STM32_APB1_BASE 0x40000000 /* 0x40000000-0x40007fff: APB1 */
|
||||
#define STM32_APB2_BASE 0x40010000 /* 0x40010000-0x40016bff: APB2 */
|
||||
#define STM32_AHB1_BASE 0x40020000 /* 0x40020000-0x4007ffff: APB1 */
|
||||
#define STM32_AHB2_BASE 0x50000000 /* 0x50000000-0x5003ffff: AHB2 */
|
||||
#define STM32_AHB3_BASE 0x60000000 /* 0x60000000-0xdfffffff: AHB3 */
|
||||
|
||||
/* APB1 Base Addresses **************************************************************/
|
||||
|
||||
#define STM32_TIM2_BASE 0x40000000 /* 0x40000000-0x400003ff: TIM2 */
|
||||
#define STM32_TIM3_BASE 0x40000400 /* 0x40000400-0x400007ff: TIM3 */
|
||||
#define STM32_TIM4_BASE 0x40000800 /* 0x40000800-0x40000bff: TIM4 */
|
||||
#define STM32_TIM5_BASE 0x40000c00 /* 0x40000c00-0x40000fff: TIM5 */
|
||||
#define STM32_TIM6_BASE 0x40001000 /* 0x40001000-0x400013ff: TIM6 */
|
||||
#define STM32_TIM7_BASE 0x40001400 /* 0x40001400-0x400017ff: TIM7 */
|
||||
#define STM32_TIM12_BASE 0x40001800 /* 0x40001800-0x40001bff: TIM12 */
|
||||
#define STM32_TIM13_BASE 0x40001c00 /* 0x40001c00-0x40001fff: TIM13 */
|
||||
#define STM32_TIM14_BASE 0x40002000 /* 0x40002000-0x400023ff: TIM14 */
|
||||
#define STM32_LPTIM1_BASE 0x40002400 /* 0x40002400-0x400027ff: LPTIM1 */
|
||||
#define STM32_RTC_BASE 0x40002800 /* 0x40002800-0x40002bff: RTC & BKP Registers */
|
||||
#define STM32_BKP_BASE 0x40002800 /* 0x40002800-0x40002bff: RTC & BKP Registers */
|
||||
#define STM32_WWDG_BASE 0x40002c00 /* 0x40002c00-0x40002fff: WWDG */
|
||||
#define STM32_IWDG_BASE 0x40003000 /* 0x40003000-0x400033ff: IWDG */
|
||||
#define STM32_CAN3_BASE 0x40003400 /* 0x40003400-0x400037ff: CAN3 */
|
||||
#define STM32_SPI2_BASE 0x40003800 /* 0x40003800-0x40003bff: SPI2 / I2S2 */
|
||||
#define STM32_I2S2_BASE 0x40003800 /* 0x40003800-0x40003bff: SPI2 / I2S2 */
|
||||
#define STM32_SPI3_BASE 0x40003c00 /* 0x40003c00-0x40003fff: SPI3 / I2S3 */
|
||||
#define STM32_I2S3_BASE 0x40003c00 /* 0x40003c00-0x40003fff: SPI3 / I2S3 */
|
||||
#define STM32_SPDIFRX_BASE 0x40004000 /* 0x40004000-0x400043ff: SPDIFRX */
|
||||
#define STM32_USART2_BASE 0x40004400 /* 0x40004400-0x400047ff: USART2 */
|
||||
#define STM32_USART3_BASE 0x40004800 /* 0x40004800-0x40004bff: USART3 */
|
||||
#define STM32_UART4_BASE 0x40004c00 /* 0x40004c00-0x40004fff: UART4 */
|
||||
#define STM32_UART5_BASE 0x40005000 /* 0x40005000-0x400053ff: UART5 */
|
||||
#define STM32_I2C1_BASE 0x40005400 /* 0x40005400-0x400057ff: I2C1 */
|
||||
#define STM32_I2C2_BASE 0x40005800 /* 0x40005800-0x40005bff: I2C2 */
|
||||
#define STM32_I2C3_BASE 0x40005c00 /* 0x40005c00-0x40005fff: I2C3 */
|
||||
#define STM32_I2C4_BASE 0x40006000 /* 0x40006000-0x400063ff: I2C4 */
|
||||
#define STM32_CAN1_BASE 0x40006400 /* 0x40006400-0x400067ff: CAN1 */
|
||||
#define STM32_CAN2_BASE 0x40006800 /* 0x40006800-0x40006bff: CAN2 */
|
||||
#define STM32_HDMICEC_BASE 0x40006c00 /* 0x40006c00-0x40006fff: HDMI-CEC */
|
||||
#define STM32_PWR_BASE 0x40007000 /* 0x40007000-0x400073ff: PWR */
|
||||
#define STM32_DAC_BASE 0x40007400 /* 0x40007400-0x400077ff: DAC */
|
||||
#define STM32_UART7_BASE 0x40007800 /* 0x40007800-0x40007bff: UART7 */
|
||||
#define STM32_UART8_BASE 0x40007c00 /* 0x40007c00-0x40007fff: UART8 */
|
||||
|
||||
/* APB2 Base Addresses **************************************************************/
|
||||
|
||||
#define STM32_TIM1_BASE 0x40010000 /* 0x40010000-0x400103ff: TIM1 */
|
||||
#define STM32_TIM8_BASE 0x40010400 /* 0x40010400-0x400107ff: TIM8 */
|
||||
#define STM32_USART1_BASE 0x40011000 /* 0x40011000-0x400113ff: USART1 */
|
||||
#define STM32_USART6_BASE 0x40011400 /* 0x40011400-0x400117ff: USART6 */
|
||||
#define STM32_SDMMC2_BASE 0x40011c00 /* 0x40011c00-0x40011fff: SDMMC2 */
|
||||
#define STM32_ADC_BASE 0x40012000 /* 0x40012000-0x400123ff: ADC1 - ADC2 - ADC3 */
|
||||
#define STM32_SDMMC1_BASE 0x40012c00 /* 0x40012c00-0x40012fff: SDMMC1 */
|
||||
#define STM32_SPI1_BASE 0x40013000 /* 0x40013000-0x400133ff: SPI1 */
|
||||
#define STM32_SPI4_BASE 0x40013400 /* 0x40013400-0x400137ff: SPI4 */
|
||||
#define STM32_SYSCFG_BASE 0x40013800 /* 0x40013800-0x40013bff: SYSCFG */
|
||||
#define STM32_EXTI_BASE 0x40013c00 /* 0x40013c00-0x40013fff: EXTI */
|
||||
#define STM32_TIM9_BASE 0x40014000 /* 0x40014000-0x400143ff: TIM9 */
|
||||
#define STM32_TIM10_BASE 0x40014400 /* 0x40014400-0x400147ff: TIM10 */
|
||||
#define STM32_TIM11_BASE 0x40014800 /* 0x40014800-0x40014bff: TIM11 */
|
||||
#define STM32_SPI5_BASE 0x40015000 /* 0x40015000-0x400153ff: SPI5 */
|
||||
#define STM32_SPI6_BASE 0x40015400 /* 0x40015400-0x400157ff: SPI6 */
|
||||
#define STM32_SAI1_BASE 0x40015800 /* 0x40015800-0x40015bff: SAI1 */
|
||||
#define STM32_SAI2_BASE 0x40015c00 /* 0x40015c00-0x40015fff: SAI2 */
|
||||
#define STM32_LCDTFT_BASE 0x40016800 /* 0x40016800-0x40016bff: LCD-TFT */
|
||||
#define STM32_DSIHOST_BASE 0x40016c00 /* 0x40016c00-0x400173ff: DSI Host */
|
||||
#define STM32_DFSDM1_BASE 0x40017400 /* 0x40017400-0x400174ff: DFSDM1 */
|
||||
#define STM32_MDIOS_BASE 0x40017800 /* 0x40017800-0x40017bff: MDIOS */
|
||||
|
||||
/* AHB1 Base Addresses **************************************************************/
|
||||
|
||||
#define STM32_GPIOA_BASE 0x40020000 /* 0x40020000-0x400203ff: GPIOA */
|
||||
#define STM32_GPIOB_BASE 0x40020400 /* 0x40020400-0x400207ff: GPIOB */
|
||||
#define STM32_GPIOC_BASE 0x40020800 /* 0x40020800-0x40020bff: GPIOC */
|
||||
#define STM32_GPIOD_BASE 0x40020c00 /* 0x40020c00-0x40020fff: GPIOD */
|
||||
#define STM32_GPIOE_BASE 0x40021000 /* 0x40021000-0x400213ff: GPIOE */
|
||||
#define STM32_GPIOF_BASE 0x40021400 /* 0x40021400-0x400217ff: GPIOF */
|
||||
#define STM32_GPIOG_BASE 0x40021800 /* 0x40021800-0x40021bff: GPIOG */
|
||||
#define STM32_GPIOH_BASE 0x40021c00 /* 0x40021c00-0x40021fff: GPIOH */
|
||||
#define STM32_GPIOI_BASE 0x40022000 /* 0x40022000-0x400223ff: GPIOI */
|
||||
#define STM32_GPIOJ_BASE 0x40022400 /* 0x40022400-0x400227ff: GPIOJ */
|
||||
#define STM32_GPIOK_BASE 0x40022800 /* 0x40022800-0x40022bff: GPIOK */
|
||||
#define STM32_CRC_BASE 0x40023000 /* 0x40023000-0x400233ff: CRC */
|
||||
#define STM32_RCC_BASE 0x40023800 /* 0x40023800-0x40023bff: RCC */
|
||||
#define STM32_FLASHIF_BASE 0x40023c00 /* 0x40023c00-0x40023fff: Flash interface */
|
||||
#define STM32_BKPSRAM_BASE 0x40024000 /* 0x40024000-0x40024fff: BKPSRAM */
|
||||
#define STM32_DMA1_BASE 0x40026000 /* 0x40026000-0x400263ff: DMA1 */
|
||||
#define STM32_DMA2_BASE 0x40026400 /* 0x40026400-0x400267ff: DMA2 */
|
||||
#define STM32_ETHMAC_BASE 0x40028000 /* 0x40028000-0x400293ff: ETHERNET MAC */
|
||||
#define STM32_DMA2D_BASE 0x4002b000 /* 0x4002b000-0x4002Bbff: Chrom-ART (DMA2D) */
|
||||
#define STM32_USBOTGHS_BASE 0x40040000 /* 0x40040000-0x4007ffff: USB OTG HS */
|
||||
|
||||
/* AHB2 Base Addresses **************************************************************/
|
||||
|
||||
#define STM32_USBOTGFS_BASE 0x50000000 /* 0x50000000-0x5003ffff: USB OTG FS */
|
||||
#define STM32_DCMI_BASE 0x50050000 /* 0x50050000-0x500503ff: DCMI */
|
||||
#define STM32_JPEG_BASE 0x50051000 /* 0x50051000-0x500511ff: JPEG */
|
||||
#define STM32_CRYP_BASE 0x50060000 /* 0x50060000-0x500603ff: CRYP */
|
||||
#define STM32_HASH_BASE 0x50060400 /* 0x50060400-0x500607ff: HASH */
|
||||
#define STM32_RNG_BASE 0x50060800 /* 0x50060800-0x50060bff: RNG */
|
||||
|
||||
/* AHB3 Base Addresses **************************************************************/
|
||||
|
||||
#define STM32_FMCBANK1_BASE 0x60000000 /* 0x60000000-0x6fffffff: FMC bank 1 */
|
||||
#define STM32_FMCBANK2_BASE 0x70000000 /* 0x70000000-0x7fffffff: FMC bank 2 */
|
||||
#define STM32_FMCBANK3_BASE 0x80000000 /* 0x80000000-0x8fffffff: FMC bank 3 */
|
||||
#define STM32_FMCBANK4_BASE 0x90000000 /* 0x90000000-0x9fffffff: FMC bank 4 */
|
||||
#define STM32_FSMC_BASE 0xa0000000 /* 0xa0000000-0xa0000fff: FMC control registers */
|
||||
#define STM32_QUADSPI_BASE 0xa0001000 /* 0xa0001000-0xa0001fff: QuadSPI Control */
|
||||
#define STM32_FMCBANK5_BASE 0xc0000000 /* 0xc0000000-0xcfffffff: FMC bank 5 */
|
||||
#define STM32_FMCBANK6_BASE 0xd0000000 /* 0xd0000000-0xdfffffff: FMC bank 6 */
|
||||
|
||||
/* Cortex-M7 Base Addresses *********************************************************/
|
||||
/* Other registers -- see armv7-m/nvic.h for standard Cortex-M3 registers in this
|
||||
* address range
|
||||
*/
|
||||
|
||||
#endif /* CONFIG_STM32F7_STM32F76XX || CONFIG_STM32F7_STM32F77XX */
|
||||
#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F76XXX77XXX_MEMORYMAP_H */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,159 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32f7/chip/stm32f76xx77xx_pwr.h
|
||||
*
|
||||
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F76XX77XX_PWR_H
|
||||
#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F76XX77XX_PWR_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#if defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F76XX)
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
#define STM32_PWR_CR1_OFFSET 0x0000 /* Power control register 1 */
|
||||
#define STM32_PWR_CSR1_OFFSET 0x0004 /* Power control/status register 1 */
|
||||
#define STM32_PWR_CR2_OFFSET 0x0008 /* Power control register 1 */
|
||||
#define STM32_PWR_CSR2_OFFSET 0x000c /* Power control/status register 1 */
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
#define STM32_PWR_CR1 (STM32_PWR_BASE+STM32_PWR_CR1_OFFSET)
|
||||
#define STM32_PWR_CSR1 (STM32_PWR_BASE+STM32_PWR_CSR1_OFFSET)
|
||||
#define STM32_PWR_CR2 (STM32_PWR_BASE+STM32_PWR_CR2_OFFSET)
|
||||
#define STM32_PWR_CSR2 (STM32_PWR_BASE+STM32_PWR_CSR2_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************/
|
||||
|
||||
/* Power control register 1 */
|
||||
|
||||
#define PWR_CR1_LPDS (1 << 0) /* Bit 0: Low-Power Deepsleep/sleep; low power run */
|
||||
#define PWR_CR1_PDDS (1 << 1) /* Bit 1: Power Down Deepsleep */
|
||||
#define PWR_CR1_CSBF (1 << 3) /* Bit 3: Clear Standby Flag */
|
||||
#define PWR_CR1_PVDE (1 << 4) /* Bit 4: Power Voltage Detector Enable */
|
||||
#define PWR_CR1_PLS_SHIFT (5) /* Bits 7-5: PVD Level Selection */
|
||||
#define PWR_CR1_PLS_MASK (7 << PWR_CR1_PLS_SHIFT)
|
||||
# define PWR_CR1_2p0V (0 << PWR_CR1_PLS_SHIFT) /* 000: 2.0V */
|
||||
# define PWR_CR1_2p1V (1 << PWR_CR1_PLS_SHIFT) /* 001: 2.1V */
|
||||
# define PWR_CR1_2p3V (2 << PWR_CR1_PLS_SHIFT) /* 010: 2.3V */
|
||||
# define PWR_CR1_2p5V (3 << PWR_CR1_PLS_SHIFT) /* 011: 2.5V */
|
||||
# define PWR_CR1_2p6V (4 << PWR_CR1_PLS_SHIFT) /* 100: 2.6V */
|
||||
# define PWR_CR1_2p7V (5 << PWR_CR1_PLS_SHIFT) /* 101: 2.7V */
|
||||
# define PWR_CR1_2p8V (6 << PWR_CR1_PLS_SHIFT) /* 110: 2.8V */
|
||||
# define PWR_CR1_2p9V (7 << PWR_CR1_PLS_SHIFT) /* 111: 2.9V */
|
||||
#define PWR_CR1_DBP (1 << 8) /* Bit 8: Disable Backup Domain write protection */
|
||||
#define PWR_CR1_FPDS (1 << 9) /* Bit 9: Flash power down in Stop mode */
|
||||
#define PWR_CR1_LPUDS (1 << 10) /* Bit 10: Low-power regulator in deepsleep under-drive mode */
|
||||
#define PWR_CR1_MRUDS (1 << 11) /* Bit 11: Main regulator in deepsleep under-drive mode */
|
||||
#define PWR_CR1_ADCDC1 (1 << 13) /* Bit 13: see AN4073 for details */
|
||||
#define PWR_CR1_VOS_SHIFT (14) /* Bits 14-15: Regulator voltage scaling output selection */
|
||||
#define PWR_CR1_VOS_MASK (3 << PWR_CR1_VOS_SHIFT)
|
||||
# define PWR_CR1_VOS_SCALE_3 (1 << PWR_CR1_VOS_SHIFT) /* Fmax = 144MHz */
|
||||
# define PWR_CR1_VOS_SCALE_2 (2 << PWR_CR1_VOS_SHIFT) /* Fmax = 168/180MHz */
|
||||
# define PWR_CR1_VOS_SCALE_1 (3 << PWR_CR1_VOS_SHIFT) /* Fmax = 180/216MHz */
|
||||
#define PWR_CR1_ODEN (1 << 16) /* Bit 16: Over Drive enable */
|
||||
#define PWR_CR1_ODSWEN (1 << 17) /* Bit 17: Over Drive switch enabled */
|
||||
#define PWR_CR1_UDEN_SHIFT (18) /* Bits 18-19: Under-drive enable in stop mode */
|
||||
#define PWR_CR1_UDEN_MASK (3 << PWR_CR1_UDEN_SHIFT)
|
||||
# define PWR_CR1_UDEN_DISABLE (0 << PWR_CR1_UDEN_SHIFT) /* Under-drive disable */
|
||||
# define PWR_CR1_UDEN_ENABLE (3 << PWR_CR1_UDEN_SHIFT) /* Under-drive enable */
|
||||
|
||||
/* Power control/status register 1 */
|
||||
|
||||
#define PWR_CSR1_WUIF (1 << 0) /* Bit 0: Wakeup internal flag */
|
||||
#define PWR_CSR1_SBF (1 << 1) /* Bit 1: Standby flag */
|
||||
#define PWR_CSR1_PVDO (1 << 2) /* Bit 2: PVD Output */
|
||||
#define PWR_CSR1_BRR (1 << 3) /* Bit 3: Backup regulator ready */
|
||||
#define PWR_CSR1_BRE (1 << 9) /* Bit 9: Backup regulator enable */
|
||||
#define PWR_CSR1_VOSRDY (1 << 14) /* Bit 14: Regulator voltage scaling output selection ready bite */
|
||||
#define PWR_CSR1_ODRDY (1 << 16) /* Bit 16: Over Drive generator ready */
|
||||
#define PWR_CSR1_ODSWRDY (1 << 17) /* Bit 17: Over Drive Switch ready */
|
||||
#define PWR_CSR1_UDSRDY_SHIFT (18) /* Bits 18-19: Under-drive ready flag */
|
||||
#define PWR_CSR1_UDSRDY_MASK (3 << PWR_CSR1_UDSRDY_SHIFT)
|
||||
# define PWR_CSR1_UDSRDY_DISAB (0 << PWR_CSR1_UDSRDY_SHIFT) /* Under-drive is disabled */
|
||||
# define PWR_CSR1_UDSRDY_STOP (3 << PWR_CSR1_UDSRDY_SHIFT) /* Under-drive mode is activated in Stop mode */
|
||||
|
||||
/* Power control register 2 */
|
||||
|
||||
#define PWR_CR2_CWUPF1 (1 << 0) /* Bit 0: Clear Wakeup Pin flag for PA0 */
|
||||
#define PWR_CR2_CWUPF2 (1 << 1) /* Bit 1: Clear Wakeup Pin flag for PA2 */
|
||||
#define PWR_CR2_CWUPF3 (1 << 2) /* Bit 2: Clear Wakeup Pin flag for PC1 */
|
||||
#define PWR_CR2_CWUPF4 (1 << 3) /* Bit 3: Clear Wakeup Pin flag for PC13 */
|
||||
#define PWR_CR2_CWUPF5 (1 << 4) /* Bit 4: Clear Wakeup Pin flag for PI8 */
|
||||
#define PWR_CR2_CWUPF6 (1 << 5) /* Bit 5: Clear Wakeup Pin flag for PI11 */
|
||||
#define PWR_CR2_WUPP1 (1 << 8) /* Bit 8: Wakeup pin polarity bit for PA0 */
|
||||
# define PWR_CR2_WUPP1_RISING (0 << 8) /* 0=Detection on rising edge */
|
||||
# define PWR_CR2_WUPP1_FALLING (1 << 8) /* 1= Detection on falling edge */
|
||||
#define PWR_CR2_WUPP2 (1 << 9) /* Bit 9: Wakeup pin polarity bit for PA2 */
|
||||
# define PWR_CR2_WUPP2_RISING (0 << 9) /* 0=Detection on rising edge */
|
||||
# define PWR_CR2_WUPP2_FALLING (1 << 9) /* 1= Detection on falling edge */
|
||||
#define PWR_CR2_WUPP3 (1 << 10) /* Bit 10: Wakeup pin polarity bit for PC1 */
|
||||
# define PWR_CR2_WUPP3_RISING (0 << 10) /* 0=Detection on rising edge */
|
||||
# define PWR_CR2_WUPP3_FALLING (1 << 10) /* 1= Detection on falling edge */
|
||||
#define PWR_CR2_WUPP4 (1 << 11) /* Bit 11: Wakeup pin polarity bit for PC13 */
|
||||
# define PWR_CR2_WUPP4_RISING (0 << 11) /* 0=Detection on rising edge */
|
||||
# define PWR_CR2_WUPP4_FALLING (1 << 11) /* 1= Detection on falling edge */
|
||||
#define PWR_CR2_WUPP5 (1 << 12) /* Bit 12: Wakeup pin polarity bit for PI8 */
|
||||
# define PWR_CR2_WUPP5_RISING (0 << 12) /* 0=Detection on rising edge */
|
||||
# define PWR_CR2_WUPP5_FALLING (1 << 12) /* 1= Detection on falling edge */
|
||||
#define PWR_CR2_WUPP6 (1 << 13) /* Bits 13: Wakeup pin polarity bit for PI11 */
|
||||
# define PWR_CR2_WUPP6_RISING (0 << 13) /* 0=Detection on rising edge */
|
||||
# define PWR_CR2_WUPP6_FALLING (1 << 13) /* 1= Detection on falling edge */
|
||||
|
||||
/* Power control/status register 2 */
|
||||
|
||||
#define PWR_CSR2_WUPF1 (1 << 0) /* Bit 0: Wakeup Pin flag for PA0 */
|
||||
#define PWR_CSR2_WUPF2 (1 << 1) /* Bit 1: Wakeup Pin flag for PA2 */
|
||||
#define PWR_CSR2_WUPF3 (1 << 2) /* Bit 2: Wakeup Pin flag for PC1 */
|
||||
#define PWR_CSR2_WUPF4 (1 << 3) /* Bit 3: Wakeup Pin flag for PC13 */
|
||||
#define PWR_CSR2_WUPF5 (1 << 4) /* Bit 4: Wakeup Pin flag for PI8 */
|
||||
#define PWR_CSR2_WUPF6 (1 << 5) /* Bit 5: Wakeup Pin flag for PI11 */
|
||||
#define PWR_CSR2_EWUP1 (1 << 8) /* Bit 8: Enable wakeup pin for PA0 */
|
||||
#define PWR_CSR2_EWUP2 (1 << 9) /* Bit 9: Enable wakeup pin for PA2 */
|
||||
#define PWR_CSR2_EWUP3 (1 << 10) /* Bit 10: Enable wakeup pin for PC1 */
|
||||
#define PWR_CSR2_EWUP4 (1 << 11) /* Bit 11: Enable wakeup pin for PC13 */
|
||||
#define PWR_CSR2_EWUP5 (1 << 12) /* Bit 12: Enable wakeup pin for PI8 */
|
||||
#define PWR_CSR2_EWUP6 (1 << 13) /* Bit 13: Enable wakeup pin for PI11 */
|
||||
|
||||
#endif /* CONFIG_STM32F7_STM32F76XX || CONFIG_STM32F7_STM32F77XX */
|
||||
#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F76XX77XX_PWR_H */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,180 @@
|
||||
/****************************************************************************************************
|
||||
* arch/arm/src/stm32f7/chip/stm32f76xx77xx_syscfg.h
|
||||
*
|
||||
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@uas.net>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F76XX77XX_SYSCFG_H
|
||||
#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F76XX77XX_SYSCFG_H
|
||||
|
||||
/****************************************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include "chip.h"
|
||||
|
||||
#if defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
|
||||
|
||||
/****************************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************************************/
|
||||
|
||||
/* Register Offsets *********************************************************************************/
|
||||
|
||||
#define STM32_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */
|
||||
#define STM32_SYSCFG_PMC_OFFSET 0x0004 /* SYSCFG peripheral mode configuration register */
|
||||
|
||||
#define STM32_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */
|
||||
#define STM32_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */
|
||||
#define STM32_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */
|
||||
#define STM32_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */
|
||||
#define STM32_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */
|
||||
|
||||
#define STM32_SYSCFG_CBR_OFFSET 0x001c /* Class B register */
|
||||
#define STM32_SYSCFG_CMPCR_OFFSET 0x0020 /* Compensation cell control register */
|
||||
|
||||
/* Register Addresses *******************************************************************************/
|
||||
|
||||
#define STM32_SYSCFG_MEMRMP (STM32_SYSCFG_BASE+STM32_SYSCFG_MEMRMP_OFFSET)
|
||||
#define STM32_SYSCFG_PMC (STM32_SYSCFG_BASE+STM32_SYSCFG_PMC_OFFSET)
|
||||
|
||||
#define STM32_SYSCFG_EXTICR(p) (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR_OFFSET(p))
|
||||
#define STM32_SYSCFG_EXTICR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR1_OFFSET)
|
||||
#define STM32_SYSCFG_EXTICR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR2_OFFSET)
|
||||
#define STM32_SYSCFG_EXTICR3 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR3_OFFSET)
|
||||
#define STM32_SYSCFG_EXTICR4 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR4_OFFSET)
|
||||
|
||||
#define STM32_SYSCFG_CBR (STM32_SYSCFG_BASE+STM32_SYSCFG_CBR_OFFSET)
|
||||
#define STM32_SYSCFG_CMPCR (STM32_SYSCFG_BASE+STM32_SYSCFG_CMPCR_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ********************************************************************/
|
||||
|
||||
/* SYSCFG memory remap register */
|
||||
|
||||
#define SYSCFG_MEMRMP_MEMBOOT (1 << 0) /* Bit 0: Memory boot mapping */
|
||||
#define SYSCFG_MEMRMP_MEMBOOT_ADD0 (0 << 0) /* 0=BOOT_ADD0 defines */
|
||||
#define SYSCFG_MEMRMP_MEMBOOT_ADD1 (1 << 0) /* 1=BOOT_ADD1 defines */
|
||||
#define SYSCFG_MEMRMP_SWP_FB (1 << 8) /* Bits 8: Flash Bank swap */
|
||||
#define SYSCFG_MEMRMP_SWP_FB_BNK1 (0 << 8) /* Flash Bank 1 mapped at 0x08000000
|
||||
* Flash Bank 2 mapped at 0x08100000 */
|
||||
#define SYSCFG_MEMRMP_SWP_FB_BNK2 (1 << 8) /* Flash Bank 2 mapped at 0x08000000
|
||||
* Flash Bank 1 mapped at 0x08100000 */
|
||||
#define SYSCFG_MEMRMP_SWPFMC_SHIFT (10) /* Bits 10-11: FMC memory mapping swap */
|
||||
#define SYSCFG_MEMRMP_SWPFMC_MASK (3 << SYSCFG_MEMRMP_SWPFMC_SHIFT)
|
||||
# define SYSCFG_MEMRMP_SWPFMC_NONE (0 << SYSCFG_MEMRMP_SWPFMC_SHIFT) /* No FMC memory mapping swapping */
|
||||
# define SYSCFG_MEMRMP_SWPFMC_NORRAM (1 << SYSCFG_MEMRMP_SWPFMC_SHIFT) /* NOR/RAM and SDRAM memory mapping swapped */
|
||||
|
||||
/* SYSCFG peripheral mode configuration register */
|
||||
|
||||
#define SYSCFG_PMC_I2C1_FMP (1 << 0) /* Bit 0: I2C1 Fast-mode Plus Enable */
|
||||
#define SYSCFG_PMC_I2C2_FMP (1 << 1) /* Bit 1: I2C2 Fast-mode Plus Enable */
|
||||
#define SYSCFG_PMC_I2C3_FMP (1 << 2) /* Bit 2: I2C3 Fast-mode Plus Enable */
|
||||
#define SYSCFG_PMC_I2C4_FMP (1 << 3) /* Bit 3: I2C4 Fast-mode Plus Enable */
|
||||
#define SYSCFG_PMC_PB6_FMP (1 << 4) /* Bit 4: PB6 IO pads Fast-mode Plus Enable */
|
||||
#define SYSCFG_PMC_PB7_FMP (1 << 5) /* Bit 5: PB7 IO pads Fast-mode Plus Enable */
|
||||
#define SYSCFG_PMC_PB8_FMP (1 << 6) /* Bit 6: PB8 IO pads Fast-mode Plus Enable */
|
||||
#define SYSCFG_PMC_PB9_FMP (1 << 7) /* Bit 7: PB9 IO pads Fast-mode Plus Enable */
|
||||
#define SYSCFG_PMC_ADC1DC2 (1 << 16) /* Bit 16: See AN4073 */
|
||||
#define SYSCFG_PMC_ADC2DC2 (1 << 17) /* Bit 17: See AN4073 */
|
||||
#define SYSCFG_PMC_ADC3DC2 (1 << 18) /* Bit 18: See AN4073 */
|
||||
#define SYSCFG_PMC_MII_RMII_SEL (1 << 23) /* Bit 23: Ethernet PHY interface selection */
|
||||
# define SYSCFG_PMC_MII_SEL (0 << 23) /* 0 selects MII */
|
||||
# define SYSCFG_PMC_RMII_SEL (1 << 23) /* 1 selects RMII */
|
||||
|
||||
/* SYSCFG external interrupt configuration register 1-4 */
|
||||
|
||||
#define SYSCFG_EXTICR_PORTA (0) /* 0000: PA[x] pin */
|
||||
#define SYSCFG_EXTICR_PORTB (1) /* 0001: PB[x] pin */
|
||||
#define SYSCFG_EXTICR_PORTC (2) /* 0010: PC[x] pin */
|
||||
#define SYSCFG_EXTICR_PORTD (3) /* 0011: PD[x] pin */
|
||||
#define SYSCFG_EXTICR_PORTE (4) /* 0100: PE[x] pin */
|
||||
#define SYSCFG_EXTICR_PORTF (5) /* 0101: PF[C] pin */
|
||||
#define SYSCFG_EXTICR_PORTG (6) /* 0110: PG[x] pin */
|
||||
#define SYSCFG_EXTICR_PORTH (7) /* 0111: PH[x] pin */
|
||||
#define SYSCFG_EXTICR_PORTI (8) /* 1000: PI[x] pin */
|
||||
#define SYSCFG_EXTICR_PORTJ (9) /* 1001: PJ[x] pin */
|
||||
#define SYSCFG_EXTICR_PORTK (10) /* 1010: PK[x] pin */
|
||||
|
||||
#define SYSCFG_EXTICR_PORT_MASK (15)
|
||||
#define SYSCFG_EXTICR_EXTI_SHIFT(g) (((g) & 3) << 2)
|
||||
#define SYSCFG_EXTICR_EXTI_MASK(g) (SYSCFG_EXTICR_PORT_MASK << (SYSCFG_EXTICR_EXTI_SHIFT(g)))
|
||||
|
||||
#define SYSCFG_EXTICR1_EXTI0_SHIFT (0) /* Bits 0-3: EXTI 0 coinfiguration */
|
||||
#define SYSCFG_EXTICR1_EXTI0_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI0_SHIFT)
|
||||
#define SYSCFG_EXTICR1_EXTI1_SHIFT (4) /* Bits 4-7: EXTI 1 coinfiguration */
|
||||
#define SYSCFG_EXTICR1_EXTI1_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI1_SHIFT)
|
||||
#define SYSCFG_EXTICR1_EXTI2_SHIFT (8) /* Bits 8-11: EXTI 2 coinfiguration */
|
||||
#define SYSCFG_EXTICR1_EXTI2_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI2_SHIFT)
|
||||
#define SYSCFG_EXTICR1_EXTI3_SHIFT (12) /* Bits 12-15: EXTI 3 coinfiguration */
|
||||
#define SYSCFG_EXTICR1_EXTI3_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI3_SHIFT)
|
||||
|
||||
#define SYSCFG_EXTICR2_EXTI4_SHIFT (0) /* Bits 0-3: EXTI 4 coinfiguration */
|
||||
#define SYSCFG_EXTICR2_EXTI4_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI4_SHIFT)
|
||||
#define SYSCFG_EXTICR2_EXTI5_SHIFT (4) /* Bits 4-7: EXTI 5 coinfiguration */
|
||||
#define SYSCFG_EXTICR2_EXTI5_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI5_SHIFT)
|
||||
#define SYSCFG_EXTICR2_EXTI6_SHIFT (8) /* Bits 8-11: EXTI 6 coinfiguration */
|
||||
#define SYSCFG_EXTICR2_EXTI6_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI6_SHIFT)
|
||||
#define SYSCFG_EXTICR2_EXTI7_SHIFT (12) /* Bits 12-15: EXTI 7 coinfiguration */
|
||||
#define SYSCFG_EXTICR2_EXTI7_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI7_SHIFT)
|
||||
|
||||
#define SYSCFG_EXTICR3_EXTI8_SHIFT (0) /* Bits 0-3: EXTI 8 coinfiguration */
|
||||
#define SYSCFG_EXTICR3_EXTI8_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI8_SHIFT)
|
||||
#define SYSCFG_EXTICR3_EXTI9_SHIFT (4) /* Bits 4-7: EXTI 9 coinfiguration */
|
||||
#define SYSCFG_EXTICR3_EXTI9_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI9_SHIFT)
|
||||
#define SYSCFG_EXTICR3_EXTI10_SHIFT (8) /* Bits 8-11: EXTI 10 coinfiguration */
|
||||
#define SYSCFG_EXTICR3_EXTI10_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI10_SHIFT)
|
||||
#define SYSCFG_EXTICR3_EXTI11_SHIFT (12) /* Bits 12-15: EXTI 11 coinfiguration */
|
||||
#define SYSCFG_EXTICR3_EXTI11_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI11_SHIFT)
|
||||
|
||||
#define SYSCFG_EXTICR4_EXTI12_SHIFT (0) /* Bits 0-3: EXTI 12 coinfiguration */
|
||||
#define SYSCFG_EXTICR4_EXTI12_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI12_SHIFT)
|
||||
#define SYSCFG_EXTICR4_EXTI13_SHIFT (4) /* Bits 4-7: EXTI 13 coinfiguration */
|
||||
#define SYSCFG_EXTICR4_EXTI13_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI13_SHIFT)
|
||||
#define SYSCFG_EXTICR4_EXTI14_SHIFT (8) /* Bits 8-11: EXTI 14 coinfiguration */
|
||||
#define SYSCFG_EXTICR4_EXTI14_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI14_SHIFT)
|
||||
#define SYSCFG_EXTICR4_EXTI15_SHIFT (12) /* Bits 12-15: EXTI 15 coinfiguration */
|
||||
#define SYSCFG_EXTICR4_EXTI15_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI15_SHIFT)
|
||||
|
||||
/* Class B register */
|
||||
|
||||
#define SYSCFG_CBR_PVD (1 << 0) /* Bit 0: PVDL: PVD Lock */
|
||||
#define SYSCFG_CBR_CLL (1 << 2) /* Bit 2: CLL Core Lockup Lock*/
|
||||
|
||||
/* Compensation cell control register */
|
||||
|
||||
#define SYSCFG_CMPCR_CMPPD (1 << 0) /* Bit 0: Compensation cell power-down */
|
||||
#define SYSCFG_CMPCR_READY (1 << 8) /* Bit 8: Compensation cell ready flag */
|
||||
|
||||
#endif /* CONFIG_STM32F7_STM32F76XX || CONFIG_STM32F7_STM32F77XX */
|
||||
#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F76XX77XX_SYSCFG_H */
|
||||
@@ -59,7 +59,8 @@
|
||||
* families
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
|
||||
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) \
|
||||
|| defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
|
||||
@@ -57,7 +57,8 @@
|
||||
* families
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
|
||||
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) \
|
||||
|| defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
|
||||
@@ -65,7 +65,8 @@
|
||||
* families
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
|
||||
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) \
|
||||
|| defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
|
||||
@@ -57,7 +57,8 @@
|
||||
* families
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
|
||||
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) \
|
||||
|| defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
|
||||
@@ -2,7 +2,8 @@
|
||||
* arch/arm/src/stm32f7/stm32_rcc.c
|
||||
*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
@@ -75,6 +76,8 @@
|
||||
|
||||
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
|
||||
# include "stm32f74xx75xx_rcc.c"
|
||||
#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
|
||||
# include "stm32f76xx77xx_rcc.c"
|
||||
#else
|
||||
# error "Unsupported STM32 F7 chip"
|
||||
#endif
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
+17
-4
@@ -649,14 +649,27 @@ config ARCH_BOARD_PIRELLI_DPL10
|
||||
|
||||
config ARCH_BOARD_NUCLEO_144
|
||||
bool "STMicro NUCLEO-144"
|
||||
depends on ARCH_CHIP_STM32F746
|
||||
depends on ARCH_CHIP_STM32F746ZG || ARCH_CHIP_STM32F767ZI
|
||||
select ARCH_HAVE_LEDS
|
||||
select ARCH_HAVE_BUTTONS
|
||||
select ARCH_HAVE_IRQBUTTONS
|
||||
---help---
|
||||
STMicro Nucleo-144 development board featuring the STM32F746ZGT6U
|
||||
MCU. The STM32F746ZGT6U is a 216MHz Cortex-M7 operation with 1024Kb Flash
|
||||
memory and 300Kb SRAM.
|
||||
STMicro Nucleo-144 development board featuring STMicroelectronics
|
||||
F2, F3, F4 and F7 MCU families. The board is a "Hardware pattern"
|
||||
that can be populated with the 144 pin package of the following MCUs:
|
||||
|
||||
Target STM32 Order code
|
||||
STM32F207ZGT6 NUCLEO-F207ZG
|
||||
STM32F303ZET6 NUCLEO-F303ZE
|
||||
STM32F429ZIT6 NUCLEO-F429ZI
|
||||
STM32F446ZET6 NUCLEO-F446ZE
|
||||
|
||||
Supported in this release are:
|
||||
|
||||
NUCLEO-F746ZG - STM32F746ZGT6 a 216MHz Cortex-M7, w/FPU - 1024KiB
|
||||
Flash memory and 320KiB SRAM.
|
||||
NUCLEO-F767ZI - STM32F767ZIT6 a 216MHz Cortex-M7, w/DPFPU -
|
||||
2048KiB Flash memory and 512KiB SRAM.
|
||||
|
||||
config ARCH_BOARD_NUCLEO_F303RE
|
||||
bool "STM32F303 Nucleo F303RE"
|
||||
|
||||
+6
-3
@@ -393,9 +393,12 @@ configs/ntosd-dm320
|
||||
NuttX 0.2.1 release.
|
||||
|
||||
configs/nucleo-144
|
||||
STMicro Nucleo-144 development board featuring the STM32F746ZGT6U MCU. The
|
||||
STM32F746ZGT6U is a 216MHz Cortex-M7 operation with 1024Kb Flash memory
|
||||
and 300Kb SRAM.
|
||||
STMicro Nucleo-144 development board family. Included support for (1) the
|
||||
Nucleo-F767ZG board featuring the STM32F746ZGT6U MCU. The STM32F746ZGT6U
|
||||
is a 216MHz Cortex-M7 operation with 1024Kb Flash memory and 320Kb SRAM.
|
||||
And (2) the Nucleo-F746ZG board featuring the STM32F767ZIT6 MCU. The
|
||||
STM32F767ZIT6 is a 216MHz Cortex-M7 operation with 2048Kb Flash memory
|
||||
and 512Kb SRAM.
|
||||
|
||||
configs/nucleo-f4x1re
|
||||
STMicro ST Nucleo F401RE and F411RE boards. See
|
||||
|
||||
@@ -301,6 +301,86 @@ Where <subdir> is one of the following:
|
||||
configuration. This configuration has far fewer features than the nsh
|
||||
configuration but is also a fraction of the size.
|
||||
|
||||
This minnsh configuration is a "proof-of-concept" and not very usable in
|
||||
its current state. This configuration was created by disabling
|
||||
everything possible INCLUDING file system support. Without file system
|
||||
support, NuttX is pretty much crippled. Here are some of the
|
||||
consequences of disabling the file system:
|
||||
|
||||
- All features that depend on the file system are lost: device drivers,
|
||||
mountpoints, message queues, named semaphores.
|
||||
|
||||
- Without device drivers, you cannot interact with the RTOS using POSIX
|
||||
interfaces. You would have to work with NuttX as with those other
|
||||
tiny RTOSs: As a scheduler and a callable hardare abstraction layer
|
||||
(HAL).
|
||||
|
||||
- You cannot use any of the NuttX upper half device drivers since they
|
||||
depend on the pseudo-file system and device nodes. You can, of
|
||||
course, continue to use the lower half drivers either directly. Or,
|
||||
perhaps, you could write some custom minnsh upper half drivers that
|
||||
do not depend on a file system and expose a HAL interface.
|
||||
|
||||
There is a special version of readline() the NSH uses when there is no
|
||||
file system. It uses a special up_putc() to write data to the console
|
||||
and a special function up_getc() to read data from the console.
|
||||
|
||||
- The current up_getc() implementationsa are a kludge. They are
|
||||
analogous to the up_putc() implementations: They directly poll the
|
||||
hardware for serial availability, locking up all lower priority tasks
|
||||
in the entire system while they poll. So a version of NSH that uses
|
||||
up_getc() essentially blocks the system until a character is received.
|
||||
|
||||
This, of course, could be fixed by creating a special, upper half
|
||||
implementation of the interrupt-driven serial lower half (like
|
||||
stm32_serial) that just supports single character console I/O
|
||||
(perhaps called up_putc and up_getc?). The NSH could wait for serial
|
||||
input without blocking the system. But then that would increase the
|
||||
footprint too.
|
||||
|
||||
So although the minnsh configurations are a good starting point for
|
||||
making things small, they not are really very practical. Why might
|
||||
you want a NuttX minnsh solution? Perhaps you have software that runs
|
||||
on a family of chips including some very tiny MCUs. Then perhaps having
|
||||
the RTOS compatibility would justify the loss of functionality?
|
||||
|
||||
You can re-enable the file system and (true) serial console with
|
||||
these settings:
|
||||
|
||||
Enable the file system:
|
||||
CONFIG_NFILE_DESCRIPTORS=5
|
||||
CONFIG_NFILE_STREAMS=5
|
||||
|
||||
Enable the console device:
|
||||
CONFIG_DEV_CONSOLE=y
|
||||
|
||||
Disable most new NSH commands. Some like 'ls' are really mandatory
|
||||
with a file system:
|
||||
CONFIG_NSH_DISABLE_xxx=y
|
||||
|
||||
Enable the upper half serial driver:
|
||||
CONFIG_SERIAL=y
|
||||
CONFIG_STANDARD_SERIAL=y
|
||||
|
||||
Enable the USART1 serial driver:
|
||||
CONFIG_STM32_USART1=y
|
||||
CONFIG_STM32_USART1_SERIALDRIVER=y
|
||||
CONFIG_USART1_SERIAL_CONSOLE=y
|
||||
|
||||
CONFIG_USART1_2STOP=0
|
||||
CONFIG_USART1_BAUD=115200
|
||||
CONFIG_USART1_BITS=8
|
||||
CONFIG_USART1_PARITY=0
|
||||
CONFIG_USART1_RXBUFSIZE=16
|
||||
CONFIG_USART1_TXBUFSIZE=16
|
||||
|
||||
With these changes, NSH should behave better and we preserve the device
|
||||
driver interface. But this result in a total size increase of about
|
||||
7KB: That is about 5KB of additional OS support for the file system and
|
||||
serial console PLUS about 2KB for the 'ls' command logic (including OS
|
||||
support for opendir(), readdir(), closedir(), stat(), and probably other
|
||||
things).
|
||||
|
||||
nsh:
|
||||
---
|
||||
Configures the NuttShell (nsh) located at apps/examples/nsh. The
|
||||
|
||||
@@ -279,6 +279,86 @@ Where <subdir> is one of the following:
|
||||
configuration. This configuration has far fewer features than the nsh
|
||||
configuration but is also a fraction of the size.
|
||||
|
||||
This minnsh configuration is a "proof-of-concept" and not very usable in
|
||||
its current state. This configuration was created by disabling
|
||||
everything possible INCLUDING file system support. Without file system
|
||||
support, NuttX is pretty much crippled. Here are some of the
|
||||
consequences of disabling the file system:
|
||||
|
||||
- All features that depend on the file system are lost: device drivers,
|
||||
mountpoints, message queues, named semaphores.
|
||||
|
||||
- Without device drivers, you cannot interact with the RTOS using POSIX
|
||||
interfaces. You would have to work with NuttX as with those other
|
||||
tiny RTOSs: As a scheduler and a callable hardare abstraction layer
|
||||
(HAL).
|
||||
|
||||
- You cannot use any of the NuttX upper half device drivers since they
|
||||
depend on the pseudo-file system and device nodes. You can, of
|
||||
course, continue to use the lower half drivers either directly. Or,
|
||||
perhaps, you could write some custom minnsh upper half drivers that
|
||||
do not depend on a file system and expose a HAL interface.
|
||||
|
||||
There is a special version of readline() the NSH uses when there is no
|
||||
file system. It uses a special up_putc() to write data to the console
|
||||
and a special function up_getc() to read data from the console.
|
||||
|
||||
- The current up_getc() implementationsa are a kludge. They are
|
||||
analogous to the up_putc() implementations: They directly poll the
|
||||
hardware for serial availability, locking up all lower priority tasks
|
||||
in the entire system while they poll. So a version of NSH that uses
|
||||
up_getc() essentially blocks the system until a character is received.
|
||||
|
||||
This, of course, could be fixed by creating a special, upper half
|
||||
implementation of the interrupt-driven serial lower half (like
|
||||
stm32_serial) that just supports single character console I/O
|
||||
(perhaps called up_putc and up_getc?). The NSH could wait for serial
|
||||
input without blocking the system. But then that would increase the
|
||||
footprint too.
|
||||
|
||||
So although the minnsh configurations are a good starting point for
|
||||
making things small, they not are really very practical. Why might
|
||||
you want a NuttX minnsh solution? Perhaps you have software that runs
|
||||
on a family of chips including some very tiny MCUs. Then perhaps having
|
||||
the RTOS compatibility would justify the loss of functionality?
|
||||
|
||||
You can re-enable the file system and (true) serial console with
|
||||
these settings:
|
||||
|
||||
Enable the file system:
|
||||
CONFIG_NFILE_DESCRIPTORS=5
|
||||
CONFIG_NFILE_STREAMS=5
|
||||
|
||||
Enable the console device:
|
||||
CONFIG_DEV_CONSOLE=y
|
||||
|
||||
Disable most new NSH commands. Some like 'ls' are really mandatory
|
||||
with a file system:
|
||||
CONFIG_NSH_DISABLE_xxx=y
|
||||
|
||||
Enable the upper half serial driver:
|
||||
CONFIG_SERIAL=y
|
||||
CONFIG_STANDARD_SERIAL=y
|
||||
|
||||
Enable the USART1 serial driver:
|
||||
CONFIG_STM32_USART1=y
|
||||
CONFIG_STM32_USART1_SERIALDRIVER=y
|
||||
CONFIG_USART1_SERIAL_CONSOLE=y
|
||||
|
||||
CONFIG_USART1_2STOP=0
|
||||
CONFIG_USART1_BAUD=115200
|
||||
CONFIG_USART1_BITS=8
|
||||
CONFIG_USART1_PARITY=0
|
||||
CONFIG_USART1_RXBUFSIZE=16
|
||||
CONFIG_USART1_TXBUFSIZE=16
|
||||
|
||||
With these changes, NSH should behave better and we preserve the device
|
||||
driver interface. But this result in a total size increase of about
|
||||
7KB: That is about 5KB of additional OS support for the file system and
|
||||
serial console PLUS about 2KB for the 'ls' command logic (including OS
|
||||
support for opendir(), readdir(), closedir(), stat(), and probably other
|
||||
things).
|
||||
|
||||
nsh:
|
||||
---
|
||||
Configures the NuttShell (nsh) located at apps/examples/nsh. The
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user